From bb0df2740e251ce1046afcfdb2cad2657c881d0c Mon Sep 17 00:00:00 2001 From: Jacob Potter Date: Sat, 31 Oct 2020 11:03:55 -0600 Subject: Add CDC NCM driver --- src/class/cdc/cdc.h | 6 +- src/class/cdc/cdc_ncm_device.c | 493 +++++++++++++++++++++++++++++++++++++++++ src/class/cdc/cdc_ncm_device.h | 88 ++++++++ src/device/usbd.c | 13 ++ src/device/usbd.h | 33 +++ src/tusb.h | 4 + 6 files changed, 635 insertions(+), 2 deletions(-) create mode 100644 src/class/cdc/cdc_ncm_device.c create mode 100644 src/class/cdc/cdc_ncm_device.h diff --git a/src/class/cdc/cdc.h b/src/class/cdc/cdc.h index 2c044ac7f..2a44f0fc8 100644 --- a/src/class/cdc/cdc.h +++ b/src/class/cdc/cdc.h @@ -69,7 +69,8 @@ typedef enum CDC_COMM_SUBCLASS_DEVICE_MANAGEMENT , ///< Device Management [USBWMC1.1] CDC_COMM_SUBCLASS_MOBILE_DIRECT_LINE_MODEL , ///< Mobile Direct Line Model [USBWMC1.1] CDC_COMM_SUBCLASS_OBEX , ///< OBEX [USBWMC1.1] - CDC_COMM_SUBCLASS_ETHERNET_EMULATION_MODEL ///< Ethernet Emulation Model [USBEEM1.0] + CDC_COMM_SUBCLASS_ETHERNET_EMULATION_MODEL , ///< Ethernet Emulation Model [USBEEM1.0] + CDC_COMM_SUBCLASS_NETWORK_CONTROL_MODEL ///< Network Control Model [USBNCM1.0] } cdc_comm_sublcass_type_t; /// Communication Interface Protocol Codes @@ -114,7 +115,8 @@ typedef enum CDC_FUNC_DESC_COMMAND_SET = 0x16 , ///< Command Set Functional Descriptor CDC_FUNC_DESC_COMMAND_SET_DETAIL = 0x17 , ///< Command Set Detail Functional Descriptor CDC_FUNC_DESC_TELEPHONE_CONTROL_MODEL = 0x18 , ///< Telephone Control Model Functional Descriptor - CDC_FUNC_DESC_OBEX_SERVICE_IDENTIFIER = 0x19 ///< OBEX Service Identifier Functional Descriptor + CDC_FUNC_DESC_OBEX_SERVICE_IDENTIFIER = 0x19 , ///< OBEX Service Identifier Functional Descriptor + CDC_FUNC_DESC_NCM = 0x1A , ///< NCM Functional Descriptor }cdc_func_desc_type_t; //--------------------------------------------------------------------+ diff --git a/src/class/cdc/cdc_ncm_device.c b/src/class/cdc/cdc_ncm_device.c new file mode 100644 index 000000000..e6d65171d --- /dev/null +++ b/src/class/cdc/cdc_ncm_device.c @@ -0,0 +1,493 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020 Jacob Berg Potter + * Copyright (c) 2020 Peter Lawrence + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "tusb_option.h" + +#if ( TUSB_OPT_DEVICE_ENABLED && CFG_TUD_NCM ) + +#include "device/usbd_pvt.h" +#include "cdc_device.h" +#include "cdc_ncm_device.h" + +//--------------------------------------------------------------------+ +// MACRO CONSTANT TYPEDEF +//--------------------------------------------------------------------+ + +#define NTH16_SIGNATURE 0x484D434E +#define NDP16_SIGNATURE_NCM0 0x304D434E +#define NDP16_SIGNATURE_NCM1 0x314D434E + +typedef struct +{ + uint8_t itf_num; // Index number of Management Interface, +1 for Data Interface + uint8_t itf_data_alt; // Alternate setting of Data Interface. 0 : inactive, 1 : active + + uint8_t ep_notif; + uint8_t ep_in; + uint8_t ep_out; + + // Endpoint descriptor use to open/close when receving SetInterface + // TODO since configuration descriptor may not be long-lived memory, we should + // keep a copy of endpoint attribute instead + uint8_t const * ecm_desc_epdata; + + enum { + REPORT_SPEED, + REPORT_CONNECTED, + REPORT_DONE + } report_state; + bool report_pending; + + uint8_t current_ntb; // Index in transmit_ntb[] that is currently being filled with datagrams + uint8_t datagram_count; // Number of datagrams in transmit_ntb[current_ntb] + uint16_t next_datagram_offset; // Offset in transmit_ntb[current_ntb].data to place the next datagram + uint16_t ntb_in_size; // Maximum size of transmitted (IN to host) NTBs; initially CFG_TUD_NCM_IN_NTB_MAX_SIZE + uint8_t max_datagrams_per_ntb; // Maximum number of datagrams per NTB; initially CFG_TUD_NCM_MAX_DATAGRAMS_PER_NTB + + uint16_t nth_sequence; // Sequence number counter for transmitted NTBs + + bool transferring; + +} ncm_interface_t; + +typedef struct TU_ATTR_PACKED +{ + uint16_t wLength; + uint16_t bmNtbFormatsSupported; + uint32_t dwNtbInMaxSize; + uint16_t wNdbInDivisor; + uint16_t wNdbInPayloadRemainder; + uint16_t wNdbInAlignment; + uint16_t wReserved; + uint32_t dwNtbOutMaxSize; + uint16_t wNdbOutDivisor; + uint16_t wNdbOutPayloadRemainder; + uint16_t wNdbOutAlignment; + uint16_t wNtbOutMaxDatagrams; +} ntb_parameters_t; + +typedef struct TU_ATTR_PACKED +{ + uint32_t dwSignature; + uint16_t wHeaderLength; + uint16_t wSequence; + uint16_t wBlockLength; + uint16_t wNdpIndex; +} nth16_t; + +typedef struct TU_ATTR_PACKED +{ + uint16_t wDatagramIndex; + uint16_t wDatagramLength; +} ndp16_datagram_t; + +typedef struct TU_ATTR_PACKED +{ + uint32_t dwSignature; + uint16_t wLength; + uint16_t wNextNdpIndex; + ndp16_datagram_t datagram[]; +} ndp16_t; + +typedef union TU_ATTR_PACKED { + struct { + nth16_t nth; + ndp16_t ndp; + }; + uint8_t data[CFG_TUD_NCM_IN_NTB_MAX_SIZE]; +} transmit_ntb_t; + +struct ecm_notify_struct +{ + tusb_control_request_t header; + uint32_t downlink, uplink; +}; + +//--------------------------------------------------------------------+ +// INTERNAL OBJECT & FUNCTION DECLARATION +//--------------------------------------------------------------------+ + +CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static const ntb_parameters_t ntb_parameters = { + .wLength = sizeof(ntb_parameters_t), + .bmNtbFormatsSupported = 0x01, + .dwNtbInMaxSize = CFG_TUD_NCM_IN_NTB_MAX_SIZE, + .wNdbInDivisor = 4, + .wNdbInPayloadRemainder = 0, + .wNdbInAlignment = CFG_TUD_NCM_ALIGNMENT, + .wReserved = 0, + .dwNtbOutMaxSize = CFG_TUD_NCM_OUT_NTB_MAX_SIZE, + .wNdbOutDivisor = 4, + .wNdbOutPayloadRemainder = 0, + .wNdbOutAlignment = CFG_TUD_NCM_ALIGNMENT, + .wNtbOutMaxDatagrams = 0 +}; + +CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static transmit_ntb_t transmit_ntb[2]; + +CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t receive_ntb[CFG_TUD_NCM_OUT_NTB_MAX_SIZE]; + +static ncm_interface_t ncm_interface; + +/* + * Set up the NTB state in ncm_interface to be ready to add datagrams. + */ +static void ncm_prepare_for_tx() { + ncm_interface.datagram_count = 0; + // datagrams start after all the headers + ncm_interface.next_datagram_offset = sizeof(nth16_t) + sizeof(ndp16_t) + + ((CFG_TUD_NCM_MAX_DATAGRAMS_PER_NTB + 1) * sizeof(ndp16_datagram_t)); +} + +/* + * If not already transmitting, start sending the current NTB to the host and swap buffers + * to start filling the other one with datagrams. + */ +static void ncm_start_tx() { + if (ncm_interface.transferring) { + return; + } + + transmit_ntb_t *ntb = &transmit_ntb[ncm_interface.current_ntb]; + size_t ntb_length = ncm_interface.next_datagram_offset; + + // Fill in NTB header + ntb->nth.dwSignature = NTH16_SIGNATURE; + ntb->nth.wHeaderLength = sizeof(nth16_t); + ntb->nth.wSequence = ncm_interface.nth_sequence++; + ntb->nth.wBlockLength = ntb_length; + ntb->nth.wNdpIndex = sizeof(nth16_t); + + // Fill in NDP16 header and terminator + ntb->ndp.dwSignature = NDP16_SIGNATURE_NCM0; + ntb->ndp.wLength = sizeof(ndp16_t) + (ncm_interface.datagram_count + 1) * sizeof(ndp16_datagram_t); + ntb->ndp.wNextNdpIndex = 0; + ntb->ndp.datagram[ncm_interface.datagram_count].wDatagramIndex = 0; + ntb->ndp.datagram[ncm_interface.datagram_count].wDatagramLength = 0; + + // Kick off an endpoint transfer + usbd_edpt_xfer(TUD_OPT_RHPORT, ncm_interface.ep_in, ntb->data, ntb_length); + ncm_interface.transferring = true; + + // Swap to the other NTB and clear it out + ncm_interface.current_ntb = 1 - ncm_interface.current_ntb; + ncm_prepare_for_tx(); +} + +static struct ecm_notify_struct ncm_notify_connected = + { + .header = { + .bmRequestType = 0xA1, + .bRequest = 0 /* NETWORK_CONNECTION aka NetworkConnection */, + .wValue = 1 /* Connected */, + .wLength = 0, + }, + }; + +static struct ecm_notify_struct ncm_notify_speed_change = + { + .header = { + .bmRequestType = 0xA1, + .bRequest = 0x2A /* CONNECTION_SPEED_CHANGE aka ConnectionSpeedChange */, + .wLength = 8, + }, + .downlink = 10000000, + .uplink = 10000000, + }; + +void ncm_receive_renew(void) +{ + usbd_edpt_xfer(TUD_OPT_RHPORT, ncm_interface.ep_out, receive_ntb, sizeof(receive_ntb)); +} + +//--------------------------------------------------------------------+ +// USBD Driver API +//--------------------------------------------------------------------+ + +void ncmd_init(void) +{ + tu_memclr(&ncm_interface, sizeof(ncm_interface)); + ncm_interface.ntb_in_size = CFG_TUD_NCM_IN_NTB_MAX_SIZE; + ncm_interface.max_datagrams_per_ntb = CFG_TUD_NCM_MAX_DATAGRAMS_PER_NTB; + ncm_prepare_for_tx(); +} + +void ncmd_reset(uint8_t rhport) +{ + (void) rhport; + + ncmd_init(); +} + +uint16_t ncmd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len) +{ + // confirm interface hasn't already been allocated + TU_ASSERT(0 == ncm_interface.ep_notif, 0); + + //------------- Management Interface -------------// + ncm_interface.itf_num = itf_desc->bInterfaceNumber; + + uint16_t drv_len = sizeof(tusb_desc_interface_t); + uint8_t const * p_desc = tu_desc_next( itf_desc ); + + // Communication Functional Descriptors + while ( TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc) && drv_len <= max_len ) + { + drv_len += tu_desc_len(p_desc); + p_desc = tu_desc_next(p_desc); + } + + // notification endpoint (if any) + if ( TUSB_DESC_ENDPOINT == tu_desc_type(p_desc) ) + { + TU_ASSERT( usbd_edpt_open(rhport, (tusb_desc_endpoint_t const *) p_desc), 0 ); + + ncm_interface.ep_notif = ((tusb_desc_endpoint_t const *) p_desc)->bEndpointAddress; + + drv_len += tu_desc_len(p_desc); + p_desc = tu_desc_next(p_desc); + } + + //------------- Data Interface -------------// + // - CDC-NCM data interface has 2 alternate settings + // - 0 : zero endpoints for inactive (default) + // - 1 : IN & OUT endpoints for transfer of NTBs + TU_ASSERT(TUSB_DESC_INTERFACE == tu_desc_type(p_desc), 0); + + do + { + tusb_desc_interface_t const * data_itf_desc = (tusb_desc_interface_t const *) p_desc; + TU_ASSERT(TUSB_CLASS_CDC_DATA == data_itf_desc->bInterfaceClass, 0); + + drv_len += tu_desc_len(p_desc); + p_desc = tu_desc_next(p_desc); + } while((TUSB_DESC_INTERFACE == tu_desc_type(p_desc)) && (drv_len <= max_len)); + + // Pair of endpoints + TU_ASSERT(TUSB_DESC_ENDPOINT == tu_desc_type(p_desc), 0); + + // ECM by default is in-active, save the endpoint attribute + // to open later when receive_ntb setInterface + ncm_interface.ecm_desc_epdata = p_desc; + + drv_len += 2*sizeof(tusb_desc_endpoint_t); + + return drv_len; +} + +// Invoked when class request DATA stage is finished. +bool ncmd_control_complete(uint8_t rhport, tusb_control_request_t const * request) +{ + (void) rhport; + (void) request; + return true; +} + +static void ncm_report() +{ + if (ncm_interface.report_state == REPORT_SPEED) { + ncm_notify_speed_change.header.wIndex = ncm_interface.itf_num; + usbd_edpt_xfer(TUD_OPT_RHPORT, ncm_interface.ep_notif, (uint8_t *) &ncm_notify_speed_change, sizeof(ncm_notify_speed_change)); + ncm_interface.report_state = REPORT_CONNECTED; + ncm_interface.report_pending = true; + } else if (ncm_interface.report_state == REPORT_CONNECTED) { + ncm_notify_connected.header.wIndex = ncm_interface.itf_num; + usbd_edpt_xfer(TUD_OPT_RHPORT, ncm_interface.ep_notif, (uint8_t *) &ncm_notify_connected, sizeof(ncm_notify_connected)); + ncm_interface.report_state = REPORT_DONE; + ncm_interface.report_pending = true; + } +} + +// Handle class control request +// return false to stall control endpoint (e.g unsupported request) +bool ncmd_control_request(uint8_t rhport, tusb_control_request_t const * request) +{ + switch ( request->bmRequestType_bit.type ) + { + case TUSB_REQ_TYPE_STANDARD: + switch ( request->bRequest ) + { + case TUSB_REQ_GET_INTERFACE: + { + uint8_t const req_itfnum = (uint8_t) request->wIndex; + TU_VERIFY(ncm_interface.itf_num + 1 == req_itfnum); + + tud_control_xfer(rhport, request, &ncm_interface.itf_data_alt, 1); + } + break; + + case TUSB_REQ_SET_INTERFACE: + { + uint8_t const req_itfnum = (uint8_t) request->wIndex; + uint8_t const req_alt = (uint8_t) request->wValue; + + // Only valid for Data Interface with Alternate is either 0 or 1 + TU_VERIFY(ncm_interface.itf_num + 1 == req_itfnum && req_alt < 2); + + ncm_interface.itf_data_alt = req_alt; + + if ( ncm_interface.itf_data_alt ) + { + // TODO since we don't actually close endpoint + // hack here to not re-open it + if (ncm_interface.ep_in == 0 && ncm_interface.ep_out == 0) + { + TU_ASSERT(ncm_interface.ecm_desc_epdata); + TU_ASSERT( usbd_open_edpt_pair(rhport, ncm_interface.ecm_desc_epdata, 2, TUSB_XFER_BULK, &ncm_interface.ep_out, &ncm_interface.ep_in) ); + + // TODO set flag indicating tx allowed? + ncm_receive_renew(); // prepare for incoming datagrams + tud_ncm_link_state_cb(true); + } + } else { + // TODO close the endpoint pair + // For now pretend that we did, this should have no harm since host won't try to + // communicate with the endpoints again + // ncm_interface.ep_in = ncm_interface.ep_out = 0 + // ncm_interface.report_pending = 0; + } + + tud_control_status(rhport, request); + + if (!ncm_interface.report_pending) ncm_report(); + + } + break; + + // unsupported request + default: return false; + } + break; + + case TUSB_REQ_TYPE_CLASS: + TU_VERIFY (ncm_interface.itf_num == request->wIndex); + + if (0x80 /* GET_NTB_PARAMETERS */ == request->bRequest) + { + tud_control_xfer(rhport, request, (void*)&ntb_parameters, sizeof(ntb_parameters)); + } + + break; + + // unsupported request + default: return false; + } + + return true; +} + +static void handle_incoming_datagram(uint32_t len) +{ + uint32_t size = len; + + if (len == 0) { + return; + } + + TU_ASSERT(size >= sizeof(nth16_t), ); + + const nth16_t *hdr = (const nth16_t *)receive_ntb; + TU_ASSERT(hdr->dwSignature == NTH16_SIGNATURE, ); + TU_ASSERT(hdr->wNdpIndex >= sizeof(nth16_t) && (hdr->wNdpIndex + sizeof(ndp16_t)) <= len, ); + + const ndp16_t *ndp = (const ndp16_t *)(receive_ntb + hdr->wNdpIndex); + TU_ASSERT(ndp->dwSignature == NDP16_SIGNATURE_NCM0 || ndp->dwSignature == NDP16_SIGNATURE_NCM1, ); + TU_ASSERT(hdr->wNdpIndex + ndp->wLength <= len, ); + + int num_datagrams = (ndp->wLength - 12) / 4; + for (int i = 0; i < num_datagrams && ndp->datagram[i].wDatagramIndex && ndp->datagram[i].wDatagramLength; i++) { + tud_ncm_receive_cb(receive_ntb + ndp->datagram[i].wDatagramIndex, ndp->datagram[i].wDatagramLength); + } + + ncm_receive_renew(); +} + +bool ncmd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) +{ + (void) rhport; + (void) result; + + /* new datagram receive_ntb */ + if (ep_addr == ncm_interface.ep_out ) + { + handle_incoming_datagram(xferred_bytes); + } + + /* data transmission finished */ + if (ep_addr == ncm_interface.ep_in ) + { + if (ncm_interface.transferring) { + ncm_interface.transferring = false; + } + + // If there are datagrams queued up that we tried to send while this NTB was being emitted, send them now + if (ncm_interface.datagram_count) { + ncm_start_tx(); + } + } + + if (ep_addr == ncm_interface.ep_notif ) + { + ncm_interface.report_pending = false; + ncm_report(); + } + + return true; +} + +bool tud_ncm_xmit(void *arg, uint16_t size, void (*flatten)(void *, uint8_t *, uint16_t)) { + transmit_ntb_t *ntb = &transmit_ntb[ncm_interface.current_ntb]; + + if (ncm_interface.datagram_count >= ncm_interface.max_datagrams_per_ntb) { + return false; + } + + size_t next_datagram_offset = ncm_interface.next_datagram_offset; + if (next_datagram_offset + size > ncm_interface.ntb_in_size) { + return false; + } + + flatten(arg, ntb->data + next_datagram_offset, size); + + ntb->ndp.datagram[ncm_interface.datagram_count].wDatagramIndex = ncm_interface.next_datagram_offset; + ntb->ndp.datagram[ncm_interface.datagram_count].wDatagramLength = size; + + ncm_interface.datagram_count++; + next_datagram_offset += size; + + // round up so the next datagram is aligned correctly + next_datagram_offset += (CFG_TUD_NCM_ALIGNMENT - 1); + next_datagram_offset -= (next_datagram_offset % CFG_TUD_NCM_ALIGNMENT); + + ncm_interface.next_datagram_offset = next_datagram_offset; + + ncm_start_tx(); + + return true; +} + +#endif \ No newline at end of file diff --git a/src/class/cdc/cdc_ncm_device.h b/src/class/cdc/cdc_ncm_device.h new file mode 100644 index 000000000..1c767cad2 --- /dev/null +++ b/src/class/cdc/cdc_ncm_device.h @@ -0,0 +1,88 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef _TUSB_CDC_NCM_DEVICE_H_ +#define _TUSB_CDC_NCM_DEVICE_H_ + +#include "common/tusb_common.h" +#include "device/usbd.h" +#include "cdc.h" + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef CFG_TUD_NCM_EP_BUFSIZE +#define CFG_TUD_NCM_EP_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) +#endif + +#ifndef CFG_TUD_NCM_IN_NTB_MAX_SIZE +#define CFG_TUD_NCM_IN_NTB_MAX_SIZE 3200 +#endif + +#ifndef CFG_TUD_NCM_OUT_NTB_MAX_SIZE +#define CFG_TUD_NCM_OUT_NTB_MAX_SIZE 3200 +#endif + +#ifndef CFG_TUD_NCM_MAX_DATAGRAMS_PER_NTB +#define CFG_TUD_NCM_MAX_DATAGRAMS_PER_NTB 8 +#endif + +#ifndef CFG_TUD_NCM_ALIGNMENT +#define CFG_TUD_NCM_ALIGNMENT 4 +#endif + +/** + * Transmit data. Returns true if successful, false if the packet was rejected (transmit buffer full, + * interface not up). + * + * This is structured with a callback to avoid the need for multiple copies; some network stacks, + * including LwIP, allow for non-contiguous buffers and provide a function to flatten them. In the + * LwIP case, a thin wrapper around pbuf_copy_partial() can be passed here. + */ +bool tud_ncm_xmit(void *arg, uint16_t size, void (*flatten)(void *arg, uint8_t *buffer, uint16_t size)); + +//--------------------------------------------------------------------+ +// Application Callback API +//--------------------------------------------------------------------+ +void tud_ncm_receive_cb(uint8_t *data, size_t length); +void tud_ncm_link_state_cb(bool state); + +//--------------------------------------------------------------------+ +// INTERNAL USBD-CLASS DRIVER API +//--------------------------------------------------------------------+ +void ncmd_init (void); +void ncmd_reset (uint8_t rhport); +uint16_t ncmd_open (uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len); +bool ncmd_control_request (uint8_t rhport, tusb_control_request_t const * request); +bool ncmd_control_complete (uint8_t rhport, tusb_control_request_t const * request); +bool ncmd_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes); + +#ifdef __cplusplus +} +#endif + +#endif /* _TUSB_CDC_NCM_DEVICE_H_ */ diff --git a/src/device/usbd.c b/src/device/usbd.c index 90edc3dde..2edcf79f3 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -220,6 +220,19 @@ static usbd_class_driver_t const _usbd_driver[] = .sof = NULL }, #endif + + #if CFG_TUD_NCM + { + DRIVER_NAME("NCM") + .init = ncmd_init, + .reset = ncmd_reset, + .open = ncmd_open, + .control_request = ncmd_control_request, + .control_complete = ncmd_control_complete, + .xfer_cb = ncmd_xfer_cb, + .sof = NULL + }, + #endif }; enum { BUILTIN_DRIVER_COUNT = TU_ARRAY_SIZE(_usbd_driver) }; diff --git a/src/device/usbd.h b/src/device/usbd.h index 0a446fdc2..45caa7871 100644 --- a/src/device/usbd.h +++ b/src/device/usbd.h @@ -671,6 +671,39 @@ TU_ATTR_WEAK bool tud_vendor_control_complete_cb(uint8_t rhport, tusb_control_re TUD_BTH_PRI_ITF(_itfnum, _stridx, _ep_evt, _ep_evt_size, _ep_evt_interval, _ep_in, _ep_out, _ep_size) \ TUD_BTH_ISO_ITFS(_itfnum + 1, _ep_in + 1, _ep_out + 1, __VA_ARGS__) + +//------------- CDC-NCM -------------// + +// Length of template descriptor +#define TUD_CDC_NCM_DESC_LEN (8+9+5+5+13+6+7+9+9+7+7) + +// CDC-ECM Descriptor Template +// Interface number, description string index, MAC address string index, EP notification address and size, EP data address (out, in), and size, max segment size. +#define TUD_CDC_NCM_DESCRIPTOR(_itfnum, _desc_stridx, _mac_stridx, _ep_notif, _ep_notif_size, _epout, _epin, _epsize, _maxsegmentsize) \ + /* Interface Association */\ + 8, TUSB_DESC_INTERFACE_ASSOCIATION, _itfnum, 2, TUSB_CLASS_CDC, CDC_COMM_SUBCLASS_NETWORK_CONTROL_MODEL, 0, 0,\ + /* CDC Control Interface */\ + 9, TUSB_DESC_INTERFACE, _itfnum, 0, 1, TUSB_CLASS_CDC, CDC_COMM_SUBCLASS_NETWORK_CONTROL_MODEL, 0, _desc_stridx,\ + /* CDC-NCM Header */\ + 5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_HEADER, U16_TO_U8S_LE(0x0110),\ + /* CDC-NCM Union */\ + 5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_UNION, _itfnum, (uint8_t)((_itfnum) + 1),\ + /* CDC-ECM Functional Descriptor */\ + 13, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_ETHERNET_NETWORKING, _mac_stridx, 0, 0, 0, 0, U16_TO_U8S_LE(_maxsegmentsize), U16_TO_U8S_LE(0), 0, \ + /* CDC-ECM Functional Descriptor */\ + 6, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_NCM, U16_TO_U8S_LE(0x0100), 0, \ + /* Endpoint Notification */\ + 7, TUSB_DESC_ENDPOINT, _ep_notif, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_ep_notif_size), 1,\ + /* CDC Data Interface (default inactive) */\ + 9, TUSB_DESC_INTERFACE, (uint8_t)((_itfnum)+1), 0, 0, TUSB_CLASS_CDC_DATA, 0, 1, 0,\ + /* CDC Data Interface (alternative active) */\ + 9, TUSB_DESC_INTERFACE, (uint8_t)((_itfnum)+1), 1, 2, TUSB_CLASS_CDC_DATA, 0, 1, 0,\ + /* Endpoint In */\ + 7, TUSB_DESC_ENDPOINT, _epin, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0,\ + /* Endpoint Out */\ + 7, TUSB_DESC_ENDPOINT, _epout, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0 + + #ifdef __cplusplus } #endif diff --git a/src/tusb.h b/src/tusb.h index 8b0dd103c..d4a692d4a 100644 --- a/src/tusb.h +++ b/src/tusb.h @@ -103,6 +103,10 @@ #if CFG_TUD_BTH #include "class/bth/bth_device.h" #endif + + #if CFG_TUD_NCM + #include "class/cdc/cdc_ncm_device.h" + #endif #endif -- cgit v1.3.1 From a3d6e8fc52db0d1272290a7d5cb7963909254ad5 Mon Sep 17 00:00:00 2001 From: Jacob Potter Date: Wed, 4 Nov 2020 21:18:44 -0700 Subject: Add default for CFG_TUD_NCM --- src/tusb_option.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/tusb_option.h b/src/tusb_option.h index 393940282..b1ce62768 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -237,6 +237,10 @@ #define CFG_TUD_BTH 0 #endif +#ifndef CFG_TUD_NCM + #define CFG_TUD_NCM 0 +#endif + //-------------------------------------------------------------------- // HOST OPTIONS //-------------------------------------------------------------------- -- cgit v1.3.1 From a3fdcbdf160a7780240e8b669826a917dce877f0 Mon Sep 17 00:00:00 2001 From: Jacob Potter Date: Wed, 4 Nov 2020 23:53:03 -0700 Subject: Just leave the endpoints open, instead of closing/reopening --- src/class/cdc/cdc_ncm_device.c | 46 ++++++++++++++---------------------------- 1 file changed, 15 insertions(+), 31 deletions(-) diff --git a/src/class/cdc/cdc_ncm_device.c b/src/class/cdc/cdc_ncm_device.c index e6d65171d..e1759ff2f 100644 --- a/src/class/cdc/cdc_ncm_device.c +++ b/src/class/cdc/cdc_ncm_device.c @@ -51,11 +51,6 @@ typedef struct uint8_t ep_in; uint8_t ep_out; - // Endpoint descriptor use to open/close when receving SetInterface - // TODO since configuration descriptor may not be long-lived memory, we should - // keep a copy of endpoint attribute instead - uint8_t const * ecm_desc_epdata; - enum { REPORT_SPEED, REPORT_CONNECTED, @@ -290,9 +285,7 @@ uint16_t ncmd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint1 // Pair of endpoints TU_ASSERT(TUSB_DESC_ENDPOINT == tu_desc_type(p_desc), 0); - // ECM by default is in-active, save the endpoint attribute - // to open later when receive_ntb setInterface - ncm_interface.ecm_desc_epdata = p_desc; + TU_ASSERT(usbd_open_edpt_pair(rhport, p_desc, 2, TUSB_XFER_BULK, &ncm_interface.ep_out, &ncm_interface.ep_in) ); drv_len += 2*sizeof(tusb_desc_endpoint_t); @@ -348,33 +341,22 @@ bool ncmd_control_request(uint8_t rhport, tusb_control_request_t const * request // Only valid for Data Interface with Alternate is either 0 or 1 TU_VERIFY(ncm_interface.itf_num + 1 == req_itfnum && req_alt < 2); - ncm_interface.itf_data_alt = req_alt; - - if ( ncm_interface.itf_data_alt ) - { - // TODO since we don't actually close endpoint - // hack here to not re-open it - if (ncm_interface.ep_in == 0 && ncm_interface.ep_out == 0) - { - TU_ASSERT(ncm_interface.ecm_desc_epdata); - TU_ASSERT( usbd_open_edpt_pair(rhport, ncm_interface.ecm_desc_epdata, 2, TUSB_XFER_BULK, &ncm_interface.ep_out, &ncm_interface.ep_in) ); + if (req_alt != ncm_interface.itf_data_alt) { + ncm_interface.itf_data_alt = req_alt; - // TODO set flag indicating tx allowed? - ncm_receive_renew(); // prepare for incoming datagrams - tud_ncm_link_state_cb(true); + if (ncm_interface.itf_data_alt) { + if (!usbd_edpt_busy(rhport, ncm_interface.ep_out)) { + ncm_receive_renew(); // prepare for incoming datagrams + } + if (!ncm_interface.report_pending) { + ncm_report(); + } } - } else { - // TODO close the endpoint pair - // For now pretend that we did, this should have no harm since host won't try to - // communicate with the endpoints again - // ncm_interface.ep_in = ncm_interface.ep_out = 0 - // ncm_interface.report_pending = 0; + + tud_ncm_link_state_cb(ncm_interface.itf_data_alt); } tud_control_status(rhport, request); - - if (!ncm_interface.report_pending) ncm_report(); - } break; @@ -445,7 +427,7 @@ bool ncmd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_ } // If there are datagrams queued up that we tried to send while this NTB was being emitted, send them now - if (ncm_interface.datagram_count) { + if (ncm_interface.datagram_count && ncm_interface.itf_data_alt == 1) { ncm_start_tx(); } } @@ -462,6 +444,8 @@ bool ncmd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_ bool tud_ncm_xmit(void *arg, uint16_t size, void (*flatten)(void *, uint8_t *, uint16_t)) { transmit_ntb_t *ntb = &transmit_ntb[ncm_interface.current_ntb]; + TU_VERIFY(ncm_interface.itf_data_alt == 1); + if (ncm_interface.datagram_count >= ncm_interface.max_datagrams_per_ntb) { return false; } -- cgit v1.3.1 From 377f8ce76f98ab199d808a263023432649266372 Mon Sep 17 00:00:00 2001 From: Jacob Potter Date: Thu, 5 Nov 2020 10:18:29 -0700 Subject: Log on full NTBs --- src/class/cdc/cdc_ncm_device.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/class/cdc/cdc_ncm_device.c b/src/class/cdc/cdc_ncm_device.c index e1759ff2f..4698fa9c2 100644 --- a/src/class/cdc/cdc_ncm_device.c +++ b/src/class/cdc/cdc_ncm_device.c @@ -447,11 +447,13 @@ bool tud_ncm_xmit(void *arg, uint16_t size, void (*flatten)(void *, uint8_t *, u TU_VERIFY(ncm_interface.itf_data_alt == 1); if (ncm_interface.datagram_count >= ncm_interface.max_datagrams_per_ntb) { + TU_LOG2("NTB full [by count]\r\n"); return false; } size_t next_datagram_offset = ncm_interface.next_datagram_offset; if (next_datagram_offset + size > ncm_interface.ntb_in_size) { + TU_LOG2("ntb full [by size]\r\n"); return false; } -- cgit v1.3.1 From 226efdcec0d880feb4af3995129b85fae9b8ddb8 Mon Sep 17 00:00:00 2001 From: Jacob Potter Date: Thu, 5 Nov 2020 18:14:56 -0700 Subject: Reduce excessive poll rate on interrupt endpoint --- src/device/usbd.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/device/usbd.h b/src/device/usbd.h index 45caa7871..c547ceeee 100644 --- a/src/device/usbd.h +++ b/src/device/usbd.h @@ -693,7 +693,7 @@ TU_ATTR_WEAK bool tud_vendor_control_complete_cb(uint8_t rhport, tusb_control_re /* CDC-ECM Functional Descriptor */\ 6, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_NCM, U16_TO_U8S_LE(0x0100), 0, \ /* Endpoint Notification */\ - 7, TUSB_DESC_ENDPOINT, _ep_notif, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_ep_notif_size), 1,\ + 7, TUSB_DESC_ENDPOINT, _ep_notif, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_ep_notif_size), 50,\ /* CDC Data Interface (default inactive) */\ 9, TUSB_DESC_INTERFACE, (uint8_t)((_itfnum)+1), 0, 0, TUSB_CLASS_CDC_DATA, 0, 1, 0,\ /* CDC Data Interface (alternative active) */\ -- cgit v1.3.1 From 3158b323d8d701f70b80dca986f8b0e8e60eba97 Mon Sep 17 00:00:00 2001 From: Jacob Potter Date: Sun, 3 Jan 2021 15:16:54 -0700 Subject: Adapt to new control xfer callback --- src/class/cdc/cdc_ncm_device.c | 12 +++--------- src/class/cdc/cdc_ncm_device.h | 3 +-- src/device/usbd.c | 3 +-- 3 files changed, 5 insertions(+), 13 deletions(-) diff --git a/src/class/cdc/cdc_ncm_device.c b/src/class/cdc/cdc_ncm_device.c index 4698fa9c2..a8983dd91 100644 --- a/src/class/cdc/cdc_ncm_device.c +++ b/src/class/cdc/cdc_ncm_device.c @@ -292,14 +292,6 @@ uint16_t ncmd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint1 return drv_len; } -// Invoked when class request DATA stage is finished. -bool ncmd_control_complete(uint8_t rhport, tusb_control_request_t const * request) -{ - (void) rhport; - (void) request; - return true; -} - static void ncm_report() { if (ncm_interface.report_state == REPORT_SPEED) { @@ -317,8 +309,10 @@ static void ncm_report() // Handle class control request // return false to stall control endpoint (e.g unsupported request) -bool ncmd_control_request(uint8_t rhport, tusb_control_request_t const * request) +bool ncmd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request) { + if ( stage != CONTROL_STAGE_SETUP ) return true; + switch ( request->bmRequestType_bit.type ) { case TUSB_REQ_TYPE_STANDARD: diff --git a/src/class/cdc/cdc_ncm_device.h b/src/class/cdc/cdc_ncm_device.h index 1c767cad2..e6c7237b1 100644 --- a/src/class/cdc/cdc_ncm_device.h +++ b/src/class/cdc/cdc_ncm_device.h @@ -77,8 +77,7 @@ void tud_ncm_link_state_cb(bool state); void ncmd_init (void); void ncmd_reset (uint8_t rhport); uint16_t ncmd_open (uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len); -bool ncmd_control_request (uint8_t rhport, tusb_control_request_t const * request); -bool ncmd_control_complete (uint8_t rhport, tusb_control_request_t const * request); +bool ncmd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t const * request); bool ncmd_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes); #ifdef __cplusplus diff --git a/src/device/usbd.c b/src/device/usbd.c index e2110b7a8..c6124263f 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -217,8 +217,7 @@ static usbd_class_driver_t const _usbd_driver[] = .init = ncmd_init, .reset = ncmd_reset, .open = ncmd_open, - .control_request = ncmd_control_request, - .control_complete = ncmd_control_complete, + .control_xfer_cb = ncmd_control_xfer_cb, .xfer_cb = ncmd_xfer_cb, .sof = NULL }, -- cgit v1.3.1 From 3ba72b53d88a5eb08004c9c3c4edf7101066eb3f Mon Sep 17 00:00:00 2001 From: zhangslice <1304224508@qq.com> Date: Wed, 2 Jun 2021 09:46:48 +0800 Subject: Add MM32 SDK and USB driver Signed-off-by: zhangslice <1304224508@qq.com> --- .../mm32f327x/CMSIS/IAR_Core/arm_common_tables.h | 121 + .../mm32f327x/CMSIS/IAR_Core/arm_const_structs.h | 66 + hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_math.h | 7122 ++++++++++++++++++++ hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_armcc.h | 796 +++ .../mm32/mm32f327x/CMSIS/IAR_Core/cmsis_armclang.h | 1735 +++++ .../mm32/mm32f327x/CMSIS/IAR_Core/cmsis_compiler.h | 231 + hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_gcc.h | 1900 ++++++ .../mm32/mm32f327x/CMSIS/IAR_Core/core_armv8mbl.h | 1813 +++++ .../mm32/mm32f327x/CMSIS/IAR_Core/core_armv8mml.h | 2821 ++++++++ hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm0.h | 850 +++ .../mm32/mm32f327x/CMSIS/IAR_Core/core_cm0plus.h | 975 +++ hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm23.h | 1813 +++++ hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm3.h | 1880 ++++++ hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm33.h | 2821 ++++++++ hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm4.h | 2061 ++++++ hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm7.h | 2592 +++++++ hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_sc000.h | 976 +++ hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_sc300.h | 1851 +++++ hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/tz_context.h | 69 + .../mm32f327x/CMSIS/KEIL_Core/arm_common_tables.h | 121 + .../mm32f327x/CMSIS/KEIL_Core/arm_const_structs.h | 66 + hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_math.h | 7122 ++++++++++++++++++++ .../mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_armcc.h | 796 +++ .../mm32f327x/CMSIS/KEIL_Core/cmsis_armclang.h | 1735 +++++ .../mm32f327x/CMSIS/KEIL_Core/cmsis_compiler.h | 231 + hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_gcc.h | 1900 ++++++ .../mm32/mm32f327x/CMSIS/KEIL_Core/core_armv8mbl.h | 1813 +++++ .../mm32/mm32f327x/CMSIS/KEIL_Core/core_armv8mml.h | 2821 ++++++++ hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm0.h | 850 +++ .../mm32/mm32f327x/CMSIS/KEIL_Core/core_cm0plus.h | 975 +++ hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm23.h | 1813 +++++ hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm3.h | 1880 ++++++ hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm33.h | 2821 ++++++++ hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm4.h | 2061 ++++++ hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm7.h | 2592 +++++++ hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_sc000.h | 976 +++ hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_sc300.h | 1851 +++++ hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/tz_context.h | 69 + .../mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/dtype.h | 33 + .../mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_adc.h | 341 + .../mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_bkp.h | 130 + .../mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_can.h | 340 + .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_comp.h | 228 + .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_conf.h | 62 + .../mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crc.h | 84 + .../mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crs.h | 46 + .../mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dac.h | 166 + .../mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dbg.h | 72 + .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_device.h | 41 + .../mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dma.h | 306 + .../mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_eth.h | 729 ++ .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_eth_conf.h | 68 + .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_exti.h | 181 + .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_flash.h | 230 + .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_fsmc.h | 147 + .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_gpio.h | 198 + .../mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_i2c.h | 255 + .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_iwdg.h | 130 + .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_misc.h | 128 + .../mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_pwr.h | 156 + .../mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rcc.h | 329 + .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_redefine.h | 102 + .../mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rtc.h | 114 + .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_sdio.h | 503 ++ .../mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_spi.h | 351 + .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_syscfg.h | 83 + .../mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_tim.h | 755 +++ .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_uart.h | 211 + .../mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_uid.h | 71 + .../mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_ver.h | 89 + .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_wwdg.h | 90 + .../mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_adc.c | 563 ++ .../mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_bkp.c | 231 + .../mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_can.c | 696 ++ .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_comp.c | 226 + .../mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_crc.c | 108 + .../mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_crs.c | 43 + .../mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dac.c | 184 + .../mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dbg.c | 53 + .../mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dma.c | 319 + .../mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_eth.c | 836 +++ .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_exti.c | 222 + .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_flash.c | 548 ++ .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_fsmc.c | 124 + .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_gpio.c | 344 + .../mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_i2c.c | 526 ++ .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_iwdg.c | 208 + .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_misc.c | 147 + .../mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_pwr.c | 215 + .../mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rcc.c | 995 +++ .../mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rtc.c | 234 + .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_sdio.c | 527 ++ .../mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_spi.c | 648 ++ .../mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_tim.c | 1875 ++++++ .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_uart.c | 502 ++ .../mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uid.c | 55 + .../mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_ver.c | 131 + .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_wwdg.c | 147 + .../mm32/mm32f327x/MM32F327x/Include/mm32_device.h | 23 + hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_reg.h | 71 + .../MM32F327x/Include/mm32_reg_redefine_v1.h | 1175 ++++ hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_adc.h | 953 +++ hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_bkp.h | 147 + hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_can.h | 532 ++ .../mm32/mm32f327x/MM32F327x/Include/reg_common.h | 643 ++ hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_comp.h | 228 + hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_crc.h | 102 + hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_crs.h | 152 + hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dac.h | 247 + hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dbg.h | 113 + hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dma.h | 325 + hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_eth.h | 730 ++ hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_exti.h | 544 ++ .../mm32/mm32f327x/MM32F327x/Include/reg_flash.h | 290 + hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_fsmc.h | 194 + hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_gpio.h | 706 ++ hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_i2c.h | 635 ++ hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_iwdg.h | 125 + hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_pwm.h | 72 + hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_pwr.h | 219 + hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_rcc.h | 654 ++ hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_rtc.h | 203 + hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_sdio.h | 391 ++ hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_spi.h | 359 + .../mm32/mm32f327x/MM32F327x/Include/reg_syscfg.h | 299 + hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_tim.h | 681 ++ hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_uart.h | 362 + .../mm32f327x/MM32F327x/Include/reg_usb_otg_fs.h | 923 +++ hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_wwdg.h | 133 + hw/mcu/mm32/mm32f327x/MM32F327x/Include/types.h | 105 + .../Source/GCC_StartAsm/startup_mm32m3ux_u_gcc.S | 440 ++ .../mm32f327x/MM32F327x/Source/system_mm32f327x.c | 866 +++ src/portable/mm32/dcd_mm32f327x_otg.c | 462 ++ 133 files changed, 96566 insertions(+) create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_common_tables.h create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_const_structs.h create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_math.h create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_armcc.h create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_armclang.h create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_compiler.h create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_gcc.h create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_armv8mbl.h create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_armv8mml.h create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm0.h create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm0plus.h create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm23.h create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm3.h create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm33.h create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm4.h create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm7.h create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_sc000.h create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_sc300.h create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/tz_context.h create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_common_tables.h create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_const_structs.h create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_math.h create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_armcc.h create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_armclang.h create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_compiler.h create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_gcc.h create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_armv8mbl.h create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_armv8mml.h create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm0.h create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm0plus.h create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm23.h create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm3.h create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm33.h create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm4.h create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm7.h create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_sc000.h create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_sc300.h create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/tz_context.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/dtype.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_adc.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_bkp.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_can.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_comp.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_conf.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crc.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crs.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dac.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dbg.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_device.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dma.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_eth.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_eth_conf.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_exti.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_flash.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_fsmc.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_gpio.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_i2c.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_iwdg.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_misc.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_pwr.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rcc.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_redefine.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rtc.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_sdio.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_spi.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_syscfg.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_tim.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_uart.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_uid.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_ver.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_wwdg.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_adc.c create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_bkp.c create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_can.c create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_comp.c create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_crc.c create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_crs.c create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dac.c create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dbg.c create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dma.c create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_eth.c create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_exti.c create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_flash.c create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_fsmc.c create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_gpio.c create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_i2c.c create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_iwdg.c create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_misc.c create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_pwr.c create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rcc.c create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rtc.c create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_sdio.c create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_spi.c create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_tim.c create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uart.c create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uid.c create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_ver.c create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_wwdg.c create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_device.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_reg.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_reg_redefine_v1.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_adc.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_bkp.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_can.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_common.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_comp.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_crc.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_crs.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dac.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dbg.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dma.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_eth.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_exti.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_flash.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_fsmc.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_gpio.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_i2c.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_iwdg.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_pwm.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_pwr.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_rcc.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_rtc.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_sdio.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_spi.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_syscfg.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_tim.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_uart.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_usb_otg_fs.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_wwdg.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/types.h create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Source/GCC_StartAsm/startup_mm32m3ux_u_gcc.S create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Source/system_mm32f327x.c create mode 100644 src/portable/mm32/dcd_mm32f327x_otg.c diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_common_tables.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_common_tables.h new file mode 100644 index 000000000..dfea7460e --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_common_tables.h @@ -0,0 +1,121 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_common_tables.h + * Description: Extern declaration for common tables + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +extern const float32_t twiddleCoef_16[32]; +extern const float32_t twiddleCoef_32[64]; +extern const float32_t twiddleCoef_64[128]; +extern const float32_t twiddleCoef_128[256]; +extern const float32_t twiddleCoef_256[512]; +extern const float32_t twiddleCoef_512[1024]; +extern const float32_t twiddleCoef_1024[2048]; +extern const float32_t twiddleCoef_2048[4096]; +extern const float32_t twiddleCoef_4096[8192]; +#define twiddleCoef twiddleCoef_4096 +extern const q31_t twiddleCoef_16_q31[24]; +extern const q31_t twiddleCoef_32_q31[48]; +extern const q31_t twiddleCoef_64_q31[96]; +extern const q31_t twiddleCoef_128_q31[192]; +extern const q31_t twiddleCoef_256_q31[384]; +extern const q31_t twiddleCoef_512_q31[768]; +extern const q31_t twiddleCoef_1024_q31[1536]; +extern const q31_t twiddleCoef_2048_q31[3072]; +extern const q31_t twiddleCoef_4096_q31[6144]; +extern const q15_t twiddleCoef_16_q15[24]; +extern const q15_t twiddleCoef_32_q15[48]; +extern const q15_t twiddleCoef_64_q15[96]; +extern const q15_t twiddleCoef_128_q15[192]; +extern const q15_t twiddleCoef_256_q15[384]; +extern const q15_t twiddleCoef_512_q15[768]; +extern const q15_t twiddleCoef_1024_q15[1536]; +extern const q15_t twiddleCoef_2048_q15[3072]; +extern const q15_t twiddleCoef_4096_q15[6144]; +extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_4096[4096]; + +/* floating-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20) +#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48) +#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56) +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) +#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800) +#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808) +#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH]; + +/* fixed-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12) +#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24) +#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56) +#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112) +#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240) +#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480) +#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992) +#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) +#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + +/* Tables for Fast Math Sine and Cosine */ +extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; +extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; +extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_const_structs.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_const_structs.h new file mode 100644 index 000000000..84ffe8b85 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_const_structs.h @@ -0,0 +1,66 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_const_structs.h + * Description: Constant structs that are initialized for user convenience. + * For example, some can be given as arguments to the arm_cfft_f32() function. + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; + +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; + +#endif diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_math.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_math.h new file mode 100644 index 000000000..9d678052b --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_math.h @@ -0,0 +1,7122 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_math.h + * Description: Public header file for CMSIS DSP Library + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * ------------ + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit) + * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit) + * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit) + * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on) + * - arm_cortexM7l_math.lib (Cortex-M7, Little endian) + * - arm_cortexM7b_math.lib (Cortex-M7, Big endian) + * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit) + * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit) + * - arm_cortexM4l_math.lib (Cortex-M4, Little endian) + * - arm_cortexM4b_math.lib (Cortex-M4, Big endian) + * - arm_cortexM3l_math.lib (Cortex-M3, Little endian) + * - arm_cortexM3b_math.lib (Cortex-M3, Big endian) + * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian) + * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian) + * - arm_ARMv8MBLl_math.lib (ARMv8M Baseline, Little endian) + * - arm_ARMv8MMLl_math.lib (ARMv8M Mainline, Little endian) + * - arm_ARMv8MMLlfsp_math.lib (ARMv8M Mainline, Little endian, Single Precision Floating Point Unit) + * - arm_ARMv8MMLld_math.lib (ARMv8M Mainline, Little endian, DSP instructions) + * - arm_ARMv8MMLldfsp_math.lib (ARMv8M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * For ARMv8M cores define pre processor MACRO ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML. + * Set Pre processor MACRO __DSP_PRESENT if ARMv8M Mainline core supports DSP instructions. + * + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library has been developed and tested with MDK-ARM version 5.14.0.0 + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * ------------ + * + * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM_math.uvprojx + * + * + * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. + * + * Pre-processor Macros + * ------------ + * + * Each library project have differant pre-processor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and + * ARM_MATH_CM7 for building the library on cortex-M7. + * + * - ARM_MATH_ARMV8MxL: + * + * Define macro ARM_MATH_ARMV8MBL for building the library on ARMv8M Baseline target, ARM_MATH_ARMV8MBL for building library + * on ARMv8M Mainline target. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries. + * + * - __DSP_PRESENT: + * + * Initialize macro __DSP_PRESENT = 1 when ARMv8M Mainline core supports DSP instructions. + * + *
+ * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | + * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | + * + *
+ * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + * + * Copyright Notice + * ------------ + * + * Copyright (C) 2010-2015 ARM Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +/* ignore some GCC warnings */ +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined(ARM_MATH_CM7) +#include "core_cm7.h" +#define ARM_MATH_DSP +#elif defined (ARM_MATH_CM4) +#include "core_cm4.h" +#define ARM_MATH_DSP +#elif defined (ARM_MATH_CM3) +#include "core_cm3.h" +#elif defined (ARM_MATH_CM0) +#include "core_cm0.h" +#define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_CM0PLUS) +#include "core_cm0plus.h" +#define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_ARMV8MBL) +#include "core_armv8mbl.h" +#define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_ARMV8MML) +#include "core_armv8mml.h" +#if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1)) +#define ARM_MATH_DSP +#endif +#else +#error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML" +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI +#define PI 3.14159265358979f +#endif + +/** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + +/** + * @brief Macros required for SINE and COSINE Controller functions + */ +/* 1.31(q31) Fixed value of 2/360 */ +/* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + +/** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE +#define ALIGN4 +#else +#if defined (__GNUC__) +#define ALIGN4 __attribute__((aligned(4))) +#else +#define ALIGN4 __align(4) +#endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + +/** + * @brief Error status returned by some functions in the library. + */ + +typedef enum { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ +} arm_status; + +/** + * @brief 8-bit fractional data type in 1.7 format. + */ +typedef int8_t q7_t; + +/** + * @brief 16-bit fractional data type in 1.15 format. + */ +typedef int16_t q15_t; + +/** + * @brief 32-bit fractional data type in 1.31 format. + */ +typedef int32_t q31_t; + +/** + * @brief 64-bit fractional data type in 1.63 format. + */ +typedef int64_t q63_t; + +/** + * @brief 32-bit floating-point type definition. + */ +typedef float float32_t; + +/** + * @brief 64-bit floating-point type definition. + */ +typedef double float64_t; + +/** + * @brief definition to read/write two 16 bit values. + */ +#if defined ( __CC_ARM ) +#define __SIMD32_TYPE int32_t __packed +#define CMSIS_UNUSED __attribute__((unused)) +#define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) +#define __SIMD32_TYPE int32_t +#define CMSIS_UNUSED __attribute__((unused)) +#define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __GNUC__ ) +#define __SIMD32_TYPE int32_t +#define CMSIS_UNUSED __attribute__((unused)) +#define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __ICCARM__ ) +#define __SIMD32_TYPE int32_t __packed +#define CMSIS_UNUSED +#define CMSIS_INLINE + +#elif defined ( __TI_ARM__ ) +#define __SIMD32_TYPE int32_t +#define CMSIS_UNUSED __attribute__((unused)) +#define CMSIS_INLINE + +#elif defined ( __CSMC__ ) +#define __SIMD32_TYPE int32_t +#define CMSIS_UNUSED +#define CMSIS_INLINE + +#elif defined ( __TASKING__ ) +#define __SIMD32_TYPE __unaligned int32_t +#define CMSIS_UNUSED +#define CMSIS_INLINE + +#else +#error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ +#if !defined (ARM_MATH_DSP) +/** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ +#endif /* !defined (ARM_MATH_DSP) */ + +/** +* @brief definition to pack four 8 bit values. +*/ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + +/** + * @brief Clips Q63 to Q31 values. + */ +CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31( + q63_t x) +{ + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; +} + +/** + * @brief Clips Q63 to Q15 values. + */ +CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15( + q63_t x) +{ + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); +} + +/** + * @brief Clips Q31 to Q7 values. + */ +CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7( + q31_t x) +{ + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; +} + +/** + * @brief Clips Q31 to Q15 values. + */ +CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15( + q31_t x) +{ + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; +} + +/** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + +CMSIS_INLINE __STATIC_INLINE q63_t mult32x64( + q63_t x, + q31_t y) +{ + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); +} + +/* + #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) + #define __CLZ __clz + #endif + */ +/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */ +#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ) +CMSIS_INLINE __STATIC_INLINE uint32_t __CLZ( + q31_t data); + +CMSIS_INLINE __STATIC_INLINE uint32_t __CLZ( + q31_t data) +{ + uint32_t count = 0; + uint32_t mask = 0x80000000; + + while ((data & mask) == 0) { + count += 1u; + mask = mask >> 1u; + } + + return (count); +} +#endif + +/** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + +CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t* dst, + q31_t* pRecipTable) +{ + q31_t out; + uint32_t tempVal; + uint32_t index, i; + uint32_t signBits; + + if (in > 0) { + signBits = ((uint32_t) (__CLZ( in) - 1)); + } + else { + signBits = ((uint32_t) (__CLZ(-in) - 1)); + } + + /* Convert input sample to 1.31 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 24); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) { + tempVal = (uint32_t) (((q63_t) in * out) >> 31); + tempVal = 0x7FFFFFFFu - tempVal; + /* 1.31 with exp 1 */ + /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ + out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1u); +} + + +/** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ +CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t* dst, + q15_t* pRecipTable) +{ + q15_t out = 0; + uint32_t tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if (in > 0) { + signBits = ((uint32_t)(__CLZ( in) - 17)); + } + else { + signBits = ((uint32_t)(__CLZ(-in) - 17)); + } + + /* Convert input sample to 1.15 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 8); + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) { + tempVal = (uint32_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFFu - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); +} + + +/* + * @brief C custom defined intrinisic function for only M0 processors + */ +#if defined(ARM_MATH_CM0_FAMILY) +CMSIS_INLINE __STATIC_INLINE q31_t __SSAT( + q31_t x, + uint32_t y) +{ + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + for (i = 0; i < (y - 1); i++) { + posMax = posMax * 2; + } + + if (x > 0) { + posMax = (posMax - 1); + + if (x > posMax) { + x = posMax; + } + } + else { + negMin = -posMax; + + if (x < negMin) { + x = negMin; + } + } + return (x); +} +#endif /* end of ARM_MATH_CM0_FAMILY */ + + +/* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ +#if !defined (ARM_MATH_DSP) + +/* + * @brief C custom defined QADD8 for M3 and M0 processors + */ +CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8( + uint32_t x, + uint32_t y) +{ + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); +} + + +/* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ +CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8( + uint32_t x, + uint32_t y) +{ + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); +} + + +/* + * @brief C custom defined QADD16 for M3 and M0 processors + */ +CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16( + uint32_t x, + uint32_t y) +{ + /* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ + q31_t r = 0, s = 0; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); +} + + +/* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ +CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16( + uint32_t x, + uint32_t y) +{ + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); +} + + +/* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ +CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16( + uint32_t x, + uint32_t y) +{ + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); +} + + +/* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ +CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16( + uint32_t x, + uint32_t y) +{ + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); +} + + +/* + * @brief C custom defined QASX for M3 and M0 processors + */ +CMSIS_INLINE __STATIC_INLINE uint32_t __QASX( + uint32_t x, + uint32_t y) +{ + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); +} + + +/* + * @brief C custom defined SHASX for M3 and M0 processors + */ +CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX( + uint32_t x, + uint32_t y) +{ + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); +} + + +/* + * @brief C custom defined QSAX for M3 and M0 processors + */ +CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX( + uint32_t x, + uint32_t y) +{ + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); +} + + +/* + * @brief C custom defined SHSAX for M3 and M0 processors + */ +CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX( + uint32_t x, + uint32_t y) +{ + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); +} + + +/* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ +CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX( + uint32_t x, + uint32_t y) +{ + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); +} + +/* + * @brief C custom defined SMUADX for M3 and M0 processors + */ +CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX( + uint32_t x, + uint32_t y) +{ + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); +} + + +/* + * @brief C custom defined QADD for M3 and M0 processors + */ +CMSIS_INLINE __STATIC_INLINE int32_t __QADD( + int32_t x, + int32_t y) +{ + return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); +} + + +/* + * @brief C custom defined QSUB for M3 and M0 processors + */ +CMSIS_INLINE __STATIC_INLINE int32_t __QSUB( + int32_t x, + int32_t y) +{ + return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); +} + + +/* + * @brief C custom defined SMLAD for M3 and M0 processors + */ +CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD( + uint32_t x, + uint32_t y, + uint32_t sum) +{ + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q31_t)sum ) ) )); +} + + +/* + * @brief C custom defined SMLADX for M3 and M0 processors + */ +CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX( + uint32_t x, + uint32_t y, + uint32_t sum) +{ + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); +} + + +/* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ +CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX( + uint32_t x, + uint32_t y, + uint32_t sum) +{ + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); +} + + +/* + * @brief C custom defined SMLALD for M3 and M0 processors + */ +CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD( + uint32_t x, + uint32_t y, + uint64_t sum) +{ + /* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q63_t)sum ) ) )); +} + + +/* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ +CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX( + uint32_t x, + uint32_t y, + uint64_t sum) +{ + /* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q63_t)sum ) ) )); +} + + +/* + * @brief C custom defined SMUAD for M3 and M0 processors + */ +CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD( + uint32_t x, + uint32_t y) +{ + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); +} + + +/* + * @brief C custom defined SMUSD for M3 and M0 processors + */ +CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD( + uint32_t x, + uint32_t y) +{ + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); +} + + +/* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ +CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16( + uint32_t x) +{ + return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | + ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); +} + +/* + * @brief C custom defined SMMLA for M3 and M0 processors + */ +CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA( + int32_t x, + int32_t y, + int32_t sum) +{ + return (sum + (int32_t) (((int64_t) x * y) >> 32)); +} + +#if 0 +/* + * @brief C custom defined PKHBT for unavailable DSP extension + */ +CMSIS_INLINE __STATIC_INLINE uint32_t __PKHBT( + uint32_t x, + uint32_t y, + uint32_t leftshift) +{ + return ( ((x ) & 0x0000FFFFUL) | + ((y << leftshift) & 0xFFFF0000UL) ); +} + +/* + * @brief C custom defined PKHTB for unavailable DSP extension + */ +CMSIS_INLINE __STATIC_INLINE uint32_t __PKHTB( + uint32_t x, + uint32_t y, + uint32_t rightshift) +{ + return ( ((x ) & 0xFFFF0000UL) | + ((y >> rightshift) & 0x0000FFFFUL) ); +} +#endif + +/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ +#endif /* !defined (ARM_MATH_DSP) */ + + +/** + * @brief Instance structure for the Q7 FIR filter. + */ +typedef struct { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ +} arm_fir_instance_q7; + +/** + * @brief Instance structure for the Q15 FIR filter. + */ +typedef struct { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ +} arm_fir_instance_q15; + +/** + * @brief Instance structure for the Q31 FIR filter. + */ +typedef struct { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ +} arm_fir_instance_q31; + +/** + * @brief Instance structure for the floating-point FIR filter. + */ +typedef struct { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ +} arm_fir_instance_f32; + + +/** + * @brief Processing function for the Q7 FIR filter. + * @param[in] S points to an instance of the Q7 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void arm_fir_q7( + const arm_fir_instance_q7* S, + q7_t* pSrc, + q7_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + */ +void arm_fir_init_q7( + arm_fir_instance_q7* S, + uint16_t numTaps, + q7_t* pCoeffs, + q7_t* pState, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q15 FIR filter. + * @param[in] S points to an instance of the Q15 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void arm_fir_q15( + const arm_fir_instance_q15* S, + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void arm_fir_fast_q15( + const arm_fir_instance_q15* S, + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ +arm_status arm_fir_init_q15( + arm_fir_instance_q15* S, + uint16_t numTaps, + q15_t* pCoeffs, + q15_t* pState, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q31 FIR filter. + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void arm_fir_q31( + const arm_fir_instance_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void arm_fir_fast_q31( + const arm_fir_instance_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ +void arm_fir_init_q31( + arm_fir_instance_q31* S, + uint16_t numTaps, + q31_t* pCoeffs, + q31_t* pState, + uint32_t blockSize); + + +/** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void arm_fir_f32( + const arm_fir_instance_f32* S, + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ +void arm_fir_init_f32( + arm_fir_instance_f32* S, + uint16_t numTaps, + float32_t* pCoeffs, + float32_t* pState, + uint32_t blockSize); + + +/** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ +typedef struct { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t* pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t* pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ +} arm_biquad_casd_df1_inst_q15; + +/** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ +typedef struct { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t* pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t* pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ +} arm_biquad_casd_df1_inst_q31; + +/** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ +typedef struct { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t* pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t* pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ +} arm_biquad_casd_df1_inst_f32; + + +/** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15* S, + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ +void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15* S, + uint8_t numStages, + q15_t* pCoeffs, + q15_t* pState, + int8_t postShift); + + +/** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15* S, + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ +void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31* S, + uint8_t numStages, + q31_t* pCoeffs, + q31_t* pState, + int8_t postShift); + + +/** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32* S, + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ +void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32* S, + uint8_t numStages, + float32_t* pCoeffs, + float32_t* pState); + + +/** + * @brief Instance structure for the floating-point matrix structure. + */ +typedef struct { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t* pData; /**< points to the data of the matrix. */ +} arm_matrix_instance_f32; + + +/** + * @brief Instance structure for the floating-point matrix structure. + */ +typedef struct { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t* pData; /**< points to the data of the matrix. */ +} arm_matrix_instance_f64; + +/** + * @brief Instance structure for the Q15 matrix structure. + */ +typedef struct { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t* pData; /**< points to the data of the matrix. */ +} arm_matrix_instance_q15; + +/** + * @brief Instance structure for the Q31 matrix structure. + */ +typedef struct { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t* pData; /**< points to the data of the matrix. */ +} arm_matrix_instance_q31; + + +/** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_add_f32( + const arm_matrix_instance_f32* pSrcA, + const arm_matrix_instance_f32* pSrcB, + arm_matrix_instance_f32* pDst); + + +/** + * @brief Q15 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_add_q15( + const arm_matrix_instance_q15* pSrcA, + const arm_matrix_instance_q15* pSrcB, + arm_matrix_instance_q15* pDst); + + +/** + * @brief Q31 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_add_q31( + const arm_matrix_instance_q31* pSrcA, + const arm_matrix_instance_q31* pSrcB, + arm_matrix_instance_q31* pDst); + + +/** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32* pSrcA, + const arm_matrix_instance_f32* pSrcB, + arm_matrix_instance_f32* pDst); + + +/** + * @brief Q15, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15* pSrcA, + const arm_matrix_instance_q15* pSrcB, + arm_matrix_instance_q15* pDst, + q15_t* pScratch); + + +/** + * @brief Q31, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31* pSrcA, + const arm_matrix_instance_q31* pSrcB, + arm_matrix_instance_q31* pDst); + + +/** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32* pSrc, + arm_matrix_instance_f32* pDst); + + +/** + * @brief Q15 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15* pSrc, + arm_matrix_instance_q15* pDst); + + +/** + * @brief Q31 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31* pSrc, + arm_matrix_instance_q31* pDst); + + +/** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32* pSrcA, + const arm_matrix_instance_f32* pSrcB, + arm_matrix_instance_f32* pDst); + + +/** + * @brief Q15 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15* pSrcA, + const arm_matrix_instance_q15* pSrcB, + arm_matrix_instance_q15* pDst, + q15_t* pState); + + +/** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15* pSrcA, + const arm_matrix_instance_q15* pSrcB, + arm_matrix_instance_q15* pDst, + q15_t* pState); + + +/** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31* pSrcA, + const arm_matrix_instance_q31* pSrcB, + arm_matrix_instance_q31* pDst); + + +/** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31* pSrcA, + const arm_matrix_instance_q31* pSrcB, + arm_matrix_instance_q31* pDst); + + +/** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32* pSrcA, + const arm_matrix_instance_f32* pSrcB, + arm_matrix_instance_f32* pDst); + + +/** + * @brief Q15 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15* pSrcA, + const arm_matrix_instance_q15* pSrcB, + arm_matrix_instance_q15* pDst); + + +/** + * @brief Q31 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31* pSrcA, + const arm_matrix_instance_q31* pSrcB, + arm_matrix_instance_q31* pDst); + + +/** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32* pSrc, + float32_t scale, + arm_matrix_instance_f32* pDst); + + +/** + * @brief Q15 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15* pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15* pDst); + + +/** + * @brief Q31 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31* pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31* pDst); + + +/** + * @brief Q31 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void arm_mat_init_q31( + arm_matrix_instance_q31* S, + uint16_t nRows, + uint16_t nColumns, + q31_t* pData); + + +/** + * @brief Q15 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void arm_mat_init_q15( + arm_matrix_instance_q15* S, + uint16_t nRows, + uint16_t nColumns, + q15_t* pData); + + +/** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void arm_mat_init_f32( + arm_matrix_instance_f32* S, + uint16_t nRows, + uint16_t nColumns, + float32_t* pData); + + + +/** + * @brief Instance structure for the Q15 PID Control. + */ +typedef struct { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#if !defined (ARM_MATH_DSP) + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ +} arm_pid_instance_q15; + +/** + * @brief Instance structure for the Q31 PID Control. + */ +typedef struct { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ +} arm_pid_instance_q31; + +/** + * @brief Instance structure for the floating-point PID Control. + */ +typedef struct { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ +} arm_pid_instance_f32; + + + +/** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ +void arm_pid_init_f32( + arm_pid_instance_f32* S, + int32_t resetStateFlag); + + +/** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + */ +void arm_pid_reset_f32( + arm_pid_instance_f32* S); + + +/** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ +void arm_pid_init_q31( + arm_pid_instance_q31* S, + int32_t resetStateFlag); + + +/** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + */ + +void arm_pid_reset_q31( + arm_pid_instance_q31* S); + + +/** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ +void arm_pid_init_q15( + arm_pid_instance_q15* S, + int32_t resetStateFlag); + + +/** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] S points to an instance of the q15 PID Control structure + */ +void arm_pid_reset_q15( + arm_pid_instance_q15* S); + + +/** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ +typedef struct { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t* pYData; /**< pointer to the table of Y values */ +} arm_linear_interp_instance_f32; + +/** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ +typedef struct { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t* pData; /**< points to the data table. */ +} arm_bilinear_interp_instance_f32; + +/** +* @brief Instance structure for the Q31 bilinear interpolation function. +*/ +typedef struct { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t* pData; /**< points to the data table. */ +} arm_bilinear_interp_instance_q31; + +/** +* @brief Instance structure for the Q15 bilinear interpolation function. +*/ +typedef struct { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t* pData; /**< points to the data table. */ +} arm_bilinear_interp_instance_q15; + +/** +* @brief Instance structure for the Q15 bilinear interpolation function. +*/ +typedef struct { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t* pData; /**< points to the data table. */ +} arm_bilinear_interp_instance_q7; + + +/** + * @brief Q7 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void arm_mult_q7( + q7_t* pSrcA, + q7_t* pSrcB, + q7_t* pDst, + uint32_t blockSize); + + +/** + * @brief Q15 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void arm_mult_q15( + q15_t* pSrcA, + q15_t* pSrcB, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Q31 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void arm_mult_q31( + q31_t* pSrcA, + q31_t* pSrcB, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void arm_mult_f32( + float32_t* pSrcA, + float32_t* pSrcB, + float32_t* pDst, + uint32_t blockSize); + + +/** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t* pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t* pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ +} arm_cfft_radix2_instance_q15; + +/* Deprecated */ +arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15* S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ +void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15* S, + q15_t* pSrc); + + +/** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t* pTwiddle; /**< points to the twiddle factor table. */ + uint16_t* pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ +} arm_cfft_radix4_instance_q15; + +/* Deprecated */ +arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15* S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ +void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15* S, + q15_t* pSrc); + +/** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t* pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t* pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ +} arm_cfft_radix2_instance_q31; + +/* Deprecated */ +arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31* S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ +void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31* S, + q31_t* pSrc); + +/** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t* pTwiddle; /**< points to the twiddle factor table. */ + uint16_t* pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ +} arm_cfft_radix4_instance_q31; + +/* Deprecated */ +void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31* S, + q31_t* pSrc); + +/* Deprecated */ +arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31* S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t* pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t* pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ +} arm_cfft_radix2_instance_f32; + +/* Deprecated */ +arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32* S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ +void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32* S, + float32_t* pSrc); + +/** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t* pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t* pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ +} arm_cfft_radix4_instance_f32; + +/* Deprecated */ +arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32* S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ +void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32* S, + float32_t* pSrc); + +/** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t* pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t* pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ +} arm_cfft_instance_q15; + +void arm_cfft_q15( + const arm_cfft_instance_q15* S, + q15_t* p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t* pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t* pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ +} arm_cfft_instance_q31; + +void arm_cfft_q31( + const arm_cfft_instance_q31* S, + q31_t* p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t* pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t* pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ +} arm_cfft_instance_f32; + +void arm_cfft_f32( + const arm_cfft_instance_f32* S, + float32_t* p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ +typedef struct { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t* pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t* pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q15* pCfft; /**< points to the complex FFT instance. */ +} arm_rfft_instance_q15; + +arm_status arm_rfft_init_q15( + arm_rfft_instance_q15* S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + +void arm_rfft_q15( + const arm_rfft_instance_q15* S, + q15_t* pSrc, + q15_t* pDst); + +/** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ +typedef struct { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t* pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t* pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q31* pCfft; /**< points to the complex FFT instance. */ +} arm_rfft_instance_q31; + +arm_status arm_rfft_init_q31( + arm_rfft_instance_q31* S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + +void arm_rfft_q31( + const arm_rfft_instance_q31* S, + q31_t* pSrc, + q31_t* pDst); + +/** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t* pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t* pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32* pCfft; /**< points to the complex FFT instance. */ +} arm_rfft_instance_f32; + +arm_status arm_rfft_init_f32( + arm_rfft_instance_f32* S, + arm_cfft_radix4_instance_f32* S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + +void arm_rfft_f32( + const arm_rfft_instance_f32* S, + float32_t* pSrc, + float32_t* pDst); + +/** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t* pTwiddleRFFT; /**< Twiddle factors real stage */ +} arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32* S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32* S, + float32_t* p, float32_t* pOut, + uint8_t ifftFlag); + +/** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ +typedef struct { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t* pTwiddle; /**< points to the twiddle factor table. */ + float32_t* pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32* pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32* pCfft; /**< points to the complex FFT instance. */ +} arm_dct4_instance_f32; + + +/** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ +arm_status arm_dct4_init_f32( + arm_dct4_instance_f32* S, + arm_rfft_instance_f32* S_RFFT, + arm_cfft_radix4_instance_f32* S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + +/** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ +void arm_dct4_f32( + const arm_dct4_instance_f32* S, + float32_t* pState, + float32_t* pInlineBuffer); + + +/** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ +typedef struct { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t* pTwiddle; /**< points to the twiddle factor table. */ + q31_t* pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31* pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31* pCfft; /**< points to the complex FFT instance. */ +} arm_dct4_instance_q31; + + +/** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ +arm_status arm_dct4_init_q31( + arm_dct4_instance_q31* S, + arm_rfft_instance_q31* S_RFFT, + arm_cfft_radix4_instance_q31* S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + +/** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] S points to an instance of the Q31 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ +void arm_dct4_q31( + const arm_dct4_instance_q31* S, + q31_t* pState, + q31_t* pInlineBuffer); + + +/** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ +typedef struct { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t* pTwiddle; /**< points to the twiddle factor table. */ + q15_t* pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15* pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15* pCfft; /**< points to the complex FFT instance. */ +} arm_dct4_instance_q15; + + +/** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ +arm_status arm_dct4_init_q15( + arm_dct4_instance_q15* S, + arm_rfft_instance_q15* S_RFFT, + arm_cfft_radix4_instance_q15* S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + +/** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] S points to an instance of the Q15 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ +void arm_dct4_q15( + const arm_dct4_instance_q15* S, + q15_t* pState, + q15_t* pInlineBuffer); + + +/** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void arm_add_f32( + float32_t* pSrcA, + float32_t* pSrcB, + float32_t* pDst, + uint32_t blockSize); + + +/** + * @brief Q7 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void arm_add_q7( + q7_t* pSrcA, + q7_t* pSrcB, + q7_t* pDst, + uint32_t blockSize); + + +/** + * @brief Q15 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void arm_add_q15( + q15_t* pSrcA, + q15_t* pSrcB, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Q31 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void arm_add_q31( + q31_t* pSrcA, + q31_t* pSrcB, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void arm_sub_f32( + float32_t* pSrcA, + float32_t* pSrcB, + float32_t* pDst, + uint32_t blockSize); + + +/** + * @brief Q7 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void arm_sub_q7( + q7_t* pSrcA, + q7_t* pSrcB, + q7_t* pDst, + uint32_t blockSize); + + +/** + * @brief Q15 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void arm_sub_q15( + q15_t* pSrcA, + q15_t* pSrcB, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Q31 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void arm_sub_q31( + q31_t* pSrcA, + q31_t* pSrcB, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_scale_f32( + float32_t* pSrc, + float32_t scale, + float32_t* pDst, + uint32_t blockSize); + + +/** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_scale_q7( + q7_t* pSrc, + q7_t scaleFract, + int8_t shift, + q7_t* pDst, + uint32_t blockSize); + + +/** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_scale_q15( + q15_t* pSrc, + q15_t scaleFract, + int8_t shift, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_scale_q31( + q31_t* pSrc, + q31_t scaleFract, + int8_t shift, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @brief Q7 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ +void arm_abs_q7( + q7_t* pSrc, + q7_t* pDst, + uint32_t blockSize); + + +/** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ +void arm_abs_f32( + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + + +/** + * @brief Q15 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ +void arm_abs_q15( + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Q31 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ +void arm_abs_q31( + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ +void arm_dot_prod_f32( + float32_t* pSrcA, + float32_t* pSrcB, + uint32_t blockSize, + float32_t* result); + + +/** + * @brief Dot product of Q7 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ +void arm_dot_prod_q7( + q7_t* pSrcA, + q7_t* pSrcB, + uint32_t blockSize, + q31_t* result); + + +/** + * @brief Dot product of Q15 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ +void arm_dot_prod_q15( + q15_t* pSrcA, + q15_t* pSrcB, + uint32_t blockSize, + q63_t* result); + + +/** + * @brief Dot product of Q31 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ +void arm_dot_prod_q31( + q31_t* pSrcA, + q31_t* pSrcB, + uint32_t blockSize, + q63_t* result); + + +/** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_shift_q7( + q7_t* pSrc, + int8_t shiftBits, + q7_t* pDst, + uint32_t blockSize); + + +/** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_shift_q15( + q15_t* pSrc, + int8_t shiftBits, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_shift_q31( + q31_t* pSrc, + int8_t shiftBits, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_offset_f32( + float32_t* pSrc, + float32_t offset, + float32_t* pDst, + uint32_t blockSize); + + +/** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_offset_q7( + q7_t* pSrc, + q7_t offset, + q7_t* pDst, + uint32_t blockSize); + + +/** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_offset_q15( + q15_t* pSrc, + q15_t offset, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_offset_q31( + q31_t* pSrc, + q31_t offset, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_negate_f32( + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + + +/** + * @brief Negates the elements of a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_negate_q7( + q7_t* pSrc, + q7_t* pDst, + uint32_t blockSize); + + +/** + * @brief Negates the elements of a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_negate_q15( + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Negates the elements of a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_negate_q31( + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void arm_copy_f32( + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + + +/** + * @brief Copies the elements of a Q7 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void arm_copy_q7( + q7_t* pSrc, + q7_t* pDst, + uint32_t blockSize); + + +/** + * @brief Copies the elements of a Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void arm_copy_q15( + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Copies the elements of a Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void arm_copy_q31( + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void arm_fill_f32( + float32_t value, + float32_t* pDst, + uint32_t blockSize); + + +/** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void arm_fill_q7( + q7_t value, + q7_t* pDst, + uint32_t blockSize); + + +/** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void arm_fill_q15( + q15_t value, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void arm_fill_q31( + q31_t value, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @brief Convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ +void arm_conv_f32( + float32_t* pSrcA, + uint32_t srcALen, + float32_t* pSrcB, + uint32_t srcBLen, + float32_t* pDst); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ +void arm_conv_opt_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst, + q15_t* pScratch1, + q15_t* pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ +void arm_conv_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst); + + +/** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ +void arm_conv_fast_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst); + + +/** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ +void arm_conv_fast_opt_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst, + q15_t* pScratch1, + q15_t* pScratch2); + + +/** + * @brief Convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ +void arm_conv_q31( + q31_t* pSrcA, + uint32_t srcALen, + q31_t* pSrcB, + uint32_t srcBLen, + q31_t* pDst); + + +/** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ +void arm_conv_fast_q31( + q31_t* pSrcA, + uint32_t srcALen, + q31_t* pSrcB, + uint32_t srcBLen, + q31_t* pDst); + + +/** +* @brief Convolution of Q7 sequences. +* @param[in] pSrcA points to the first input sequence. +* @param[in] srcALen length of the first input sequence. +* @param[in] pSrcB points to the second input sequence. +* @param[in] srcBLen length of the second input sequence. +* @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. +* @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. +* @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). +*/ +void arm_conv_opt_q7( + q7_t* pSrcA, + uint32_t srcALen, + q7_t* pSrcB, + uint32_t srcBLen, + q7_t* pDst, + q15_t* pScratch1, + q15_t* pScratch2); + + +/** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ +void arm_conv_q7( + q7_t* pSrcA, + uint32_t srcALen, + q7_t* pSrcB, + uint32_t srcBLen, + q7_t* pDst); + + +/** + * @brief Partial convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ +arm_status arm_conv_partial_f32( + float32_t* pSrcA, + uint32_t srcALen, + float32_t* pSrcB, + uint32_t srcBLen, + float32_t* pDst, + uint32_t firstIndex, + uint32_t numPoints); + + +/** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ +arm_status arm_conv_partial_opt_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t* pScratch1, + q15_t* pScratch2); + + +/** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ +arm_status arm_conv_partial_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst, + uint32_t firstIndex, + uint32_t numPoints); + + +/** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ +arm_status arm_conv_partial_fast_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst, + uint32_t firstIndex, + uint32_t numPoints); + + +/** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ +arm_status arm_conv_partial_fast_opt_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t* pScratch1, + q15_t* pScratch2); + + +/** + * @brief Partial convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ +arm_status arm_conv_partial_q31( + q31_t* pSrcA, + uint32_t srcALen, + q31_t* pSrcB, + uint32_t srcBLen, + q31_t* pDst, + uint32_t firstIndex, + uint32_t numPoints); + + +/** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ +arm_status arm_conv_partial_fast_q31( + q31_t* pSrcA, + uint32_t srcALen, + q31_t* pSrcB, + uint32_t srcBLen, + q31_t* pDst, + uint32_t firstIndex, + uint32_t numPoints); + + +/** + * @brief Partial convolution of Q7 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ +arm_status arm_conv_partial_opt_q7( + q7_t* pSrcA, + uint32_t srcALen, + q7_t* pSrcB, + uint32_t srcBLen, + q7_t* pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t* pScratch1, + q15_t* pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ +arm_status arm_conv_partial_q7( + q7_t* pSrcA, + uint32_t srcALen, + q7_t* pSrcB, + uint32_t srcBLen, + q7_t* pDst, + uint32_t firstIndex, + uint32_t numPoints); + + +/** + * @brief Instance structure for the Q15 FIR decimator. + */ +typedef struct { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ +} arm_fir_decimate_instance_q15; + +/** + * @brief Instance structure for the Q31 FIR decimator. + */ +typedef struct { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ +} arm_fir_decimate_instance_q31; + +/** + * @brief Instance structure for the floating-point FIR decimator. + */ +typedef struct { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ +} arm_fir_decimate_instance_f32; + + +/** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] S points to an instance of the floating-point FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ +void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32* S, + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ +arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32* S, + uint16_t numTaps, + uint8_t M, + float32_t* pCoeffs, + float32_t* pState, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ +void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15* S, + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ +void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15* S, + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ +arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15* S, + uint16_t numTaps, + uint8_t M, + q15_t* pCoeffs, + q15_t* pState, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ +void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + +/** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ +void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ +arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31* S, + uint16_t numTaps, + uint8_t M, + q31_t* pCoeffs, + q31_t* pState, + uint32_t blockSize); + + +/** + * @brief Instance structure for the Q15 FIR interpolator. + */ +typedef struct { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t* pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t* pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ +} arm_fir_interpolate_instance_q15; + +/** + * @brief Instance structure for the Q31 FIR interpolator. + */ +typedef struct { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t* pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t* pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ +} arm_fir_interpolate_instance_q31; + +/** + * @brief Instance structure for the floating-point FIR interpolator. + */ +typedef struct { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t* pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t* pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ +} arm_fir_interpolate_instance_f32; + + +/** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ +void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15* S, + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ +arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15* S, + uint8_t L, + uint16_t numTaps, + q15_t* pCoeffs, + q15_t* pState, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ +void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ +arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31* S, + uint8_t L, + uint16_t numTaps, + q31_t* pCoeffs, + q31_t* pState, + uint32_t blockSize); + + +/** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ +void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32* S, + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ +arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32* S, + uint8_t L, + uint16_t numTaps, + float32_t* pCoeffs, + float32_t* pState, + uint32_t blockSize); + + +/** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ +typedef struct { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t* pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t* pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ +} arm_biquad_cas_df1_32x64_ins_q31; + + +/** + * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ +void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + */ +void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31* S, + uint8_t numStages, + q31_t* pCoeffs, + q63_t* pState, + uint8_t postShift); + + +/** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ +typedef struct { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t* pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t* pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ +} arm_biquad_cascade_df2T_instance_f32; + +/** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ +typedef struct { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t* pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t* pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ +} arm_biquad_cascade_stereo_df2T_instance_f32; + +/** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ +typedef struct { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t* pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t* pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ +} arm_biquad_cascade_df2T_instance_f64; + + +/** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ +void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32* S, + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + + +/** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ +void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32* S, + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + + +/** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ +void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64* S, + float64_t* pSrc, + float64_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ +void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32* S, + uint8_t numStages, + float32_t* pCoeffs, + float32_t* pState); + + +/** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ +void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32* S, + uint8_t numStages, + float32_t* pCoeffs, + float32_t* pState); + + +/** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ +void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64* S, + uint8_t numStages, + float64_t* pCoeffs, + float64_t* pState); + + +/** + * @brief Instance structure for the Q15 FIR lattice filter. + */ +typedef struct { + uint16_t numStages; /**< number of filter stages. */ + q15_t* pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ +} arm_fir_lattice_instance_q15; + +/** + * @brief Instance structure for the Q31 FIR lattice filter. + */ +typedef struct { + uint16_t numStages; /**< number of filter stages. */ + q31_t* pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ +} arm_fir_lattice_instance_q31; + +/** + * @brief Instance structure for the floating-point FIR lattice filter. + */ +typedef struct { + uint16_t numStages; /**< number of filter stages. */ + float32_t* pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ +} arm_fir_lattice_instance_f32; + + +/** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ +void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15* S, + uint16_t numStages, + q15_t* pCoeffs, + q15_t* pState); + + +/** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15* S, + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ +void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31* S, + uint16_t numStages, + q31_t* pCoeffs, + q31_t* pState); + + +/** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ +void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ +void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32* S, + uint16_t numStages, + float32_t* pCoeffs, + float32_t* pState); + + +/** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ +void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32* S, + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + + +/** + * @brief Instance structure for the Q15 IIR lattice filter. + */ +typedef struct { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t* pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t* pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t* pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ +} arm_iir_lattice_instance_q15; + +/** + * @brief Instance structure for the Q31 IIR lattice filter. + */ +typedef struct { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t* pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t* pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t* pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ +} arm_iir_lattice_instance_q31; + +/** + * @brief Instance structure for the floating-point IIR lattice filter. + */ +typedef struct { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t* pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t* pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t* pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ +} arm_iir_lattice_instance_f32; + + +/** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32* S, + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + */ +void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32* S, + uint16_t numStages, + float32_t* pkCoeffs, + float32_t* pvCoeffs, + float32_t* pState, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + */ +void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31* S, + uint16_t numStages, + q31_t* pkCoeffs, + q31_t* pvCoeffs, + q31_t* pState, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the Q15 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15* S, + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + */ +void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15* S, + uint16_t numStages, + q15_t* pkCoeffs, + q15_t* pvCoeffs, + q15_t* pState, + uint32_t blockSize); + + +/** + * @brief Instance structure for the floating-point LMS filter. + */ +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ +} arm_lms_instance_f32; + + +/** + * @brief Processing function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ +void arm_lms_f32( + const arm_lms_instance_f32* S, + float32_t* pSrc, + float32_t* pRef, + float32_t* pOut, + float32_t* pErr, + uint32_t blockSize); + + +/** + * @brief Initialization function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ +void arm_lms_init_f32( + arm_lms_instance_f32* S, + uint16_t numTaps, + float32_t* pCoeffs, + float32_t* pState, + float32_t mu, + uint32_t blockSize); + + +/** + * @brief Instance structure for the Q15 LMS filter. + */ +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ +} arm_lms_instance_q15; + + +/** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ +void arm_lms_init_q15( + arm_lms_instance_q15* S, + uint16_t numTaps, + q15_t* pCoeffs, + q15_t* pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + +/** + * @brief Processing function for Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ +void arm_lms_q15( + const arm_lms_instance_q15* S, + q15_t* pSrc, + q15_t* pRef, + q15_t* pOut, + q15_t* pErr, + uint32_t blockSize); + + +/** + * @brief Instance structure for the Q31 LMS filter. + */ +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ +} arm_lms_instance_q31; + + +/** + * @brief Processing function for Q31 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ +void arm_lms_q31( + const arm_lms_instance_q31* S, + q31_t* pSrc, + q31_t* pRef, + q31_t* pOut, + q31_t* pErr, + uint32_t blockSize); + + +/** + * @brief Initialization function for Q31 LMS filter. + * @param[in] S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ +void arm_lms_init_q31( + arm_lms_instance_q31* S, + uint16_t numTaps, + q31_t* pCoeffs, + q31_t* pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + +/** + * @brief Instance structure for the floating-point normalized LMS filter. + */ +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ +} arm_lms_norm_instance_f32; + + +/** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ +void arm_lms_norm_f32( + arm_lms_norm_instance_f32* S, + float32_t* pSrc, + float32_t* pRef, + float32_t* pOut, + float32_t* pErr, + uint32_t blockSize); + + +/** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ +void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32* S, + uint16_t numTaps, + float32_t* pCoeffs, + float32_t* pState, + float32_t mu, + uint32_t blockSize); + + +/** + * @brief Instance structure for the Q31 normalized LMS filter. + */ +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t* recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ +} arm_lms_norm_instance_q31; + + +/** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ +void arm_lms_norm_q31( + arm_lms_norm_instance_q31* S, + q31_t* pSrc, + q31_t* pRef, + q31_t* pOut, + q31_t* pErr, + uint32_t blockSize); + + +/** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ +void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31* S, + uint16_t numTaps, + q31_t* pCoeffs, + q31_t* pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + +/** + * @brief Instance structure for the Q15 normalized LMS filter. + */ +typedef struct { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t* recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ +} arm_lms_norm_instance_q15; + + +/** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ +void arm_lms_norm_q15( + arm_lms_norm_instance_q15* S, + q15_t* pSrc, + q15_t* pRef, + q15_t* pOut, + q15_t* pErr, + uint32_t blockSize); + + +/** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ +void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15* S, + uint16_t numTaps, + q15_t* pCoeffs, + q15_t* pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + +/** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ +void arm_correlate_f32( + float32_t* pSrcA, + uint32_t srcALen, + float32_t* pSrcB, + uint32_t srcBLen, + float32_t* pDst); + + +/** +* @brief Correlation of Q15 sequences +* @param[in] pSrcA points to the first input sequence. +* @param[in] srcALen length of the first input sequence. +* @param[in] pSrcB points to the second input sequence. +* @param[in] srcBLen length of the second input sequence. +* @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. +* @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. +*/ +void arm_correlate_opt_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst, + q15_t* pScratch); + + +/** + * @brief Correlation of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + +void arm_correlate_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst); + + +/** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + +void arm_correlate_fast_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst); + + +/** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ +void arm_correlate_fast_opt_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst, + q15_t* pScratch); + + +/** + * @brief Correlation of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ +void arm_correlate_q31( + q31_t* pSrcA, + uint32_t srcALen, + q31_t* pSrcB, + uint32_t srcBLen, + q31_t* pDst); + + +/** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ +void arm_correlate_fast_q31( + q31_t* pSrcA, + uint32_t srcALen, + q31_t* pSrcB, + uint32_t srcBLen, + q31_t* pDst); + + +/** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ +void arm_correlate_opt_q7( + q7_t* pSrcA, + uint32_t srcALen, + q7_t* pSrcB, + uint32_t srcBLen, + q7_t* pDst, + q15_t* pScratch1, + q15_t* pScratch2); + + +/** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ +void arm_correlate_q7( + q7_t* pSrcA, + uint32_t srcALen, + q7_t* pSrcB, + uint32_t srcBLen, + q7_t* pDst); + + +/** + * @brief Instance structure for the floating-point sparse FIR filter. + */ +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t* pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t* pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ +} arm_fir_sparse_instance_f32; + +/** + * @brief Instance structure for the Q31 sparse FIR filter. + */ +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t* pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t* pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ +} arm_fir_sparse_instance_q31; + +/** + * @brief Instance structure for the Q15 sparse FIR filter. + */ +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t* pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t* pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ +} arm_fir_sparse_instance_q15; + +/** + * @brief Instance structure for the Q7 sparse FIR filter. + */ +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t* pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t* pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ +} arm_fir_sparse_instance_q7; + + +/** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] S points to an instance of the floating-point sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ +void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32* S, + float32_t* pSrc, + float32_t* pDst, + float32_t* pScratchIn, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ +void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32* S, + uint16_t numTaps, + float32_t* pCoeffs, + float32_t* pState, + int32_t* pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] S points to an instance of the Q31 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ +void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31* S, + q31_t* pSrc, + q31_t* pDst, + q31_t* pScratchIn, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ +void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31* S, + uint16_t numTaps, + q31_t* pCoeffs, + q31_t* pState, + int32_t* pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] S points to an instance of the Q15 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ +void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15* S, + q15_t* pSrc, + q15_t* pDst, + q15_t* pScratchIn, + q31_t* pScratchOut, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ +void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15* S, + uint16_t numTaps, + q15_t* pCoeffs, + q15_t* pState, + int32_t* pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] S points to an instance of the Q7 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ +void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7* S, + q7_t* pSrc, + q7_t* pDst, + q7_t* pScratchIn, + q31_t* pScratchOut, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ +void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7* S, + uint16_t numTaps, + q7_t* pCoeffs, + q7_t* pState, + int32_t* pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + +/** + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cos output. + */ +void arm_sin_cos_f32( + float32_t theta, + float32_t* pSinVal, + float32_t* pCosVal); + + +/** + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cosine output. + */ +void arm_sin_cos_q31( + q31_t theta, + q31_t* pSinVal, + q31_t* pCosVal); + + +/** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ +void arm_cmplx_conj_f32( + float32_t* pSrc, + float32_t* pDst, + uint32_t numSamples); + +/** + * @brief Q31 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ +void arm_cmplx_conj_q31( + q31_t* pSrc, + q31_t* pDst, + uint32_t numSamples); + + +/** + * @brief Q15 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ +void arm_cmplx_conj_q15( + q15_t* pSrc, + q15_t* pDst, + uint32_t numSamples); + + +/** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ +void arm_cmplx_mag_squared_f32( + float32_t* pSrc, + float32_t* pDst, + uint32_t numSamples); + + +/** + * @brief Q31 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ +void arm_cmplx_mag_squared_q31( + q31_t* pSrc, + q31_t* pDst, + uint32_t numSamples); + + +/** + * @brief Q15 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ +void arm_cmplx_mag_squared_q15( + q15_t* pSrc, + q15_t* pDst, + uint32_t numSamples); + + +/** + * @ingroup groupController + */ + +/** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+ *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+ *    A0 = Kp + Ki + Kd
+ *    A1 = (-Kp ) - (2 * Kd )
+ *    A2 = Kd
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + +/** + * @addtogroup PID + * @{ + */ + +/** + * @brief Process function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ +CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32( + arm_pid_instance_f32* S, + float32_t in) +{ + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + +} + +/** + * @brief Process function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ +CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31( + arm_pid_instance_q31* S, + q31_t in) +{ + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31u); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); +} + + +/** + * @brief Process function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ +CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15( + arm_pid_instance_q15* S, + q15_t in) +{ + q63_t acc; + q15_t out; + +#if defined (ARM_MATH_DSP) + __SIMD32_TYPE* vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t) * vstate, (uint64_t)acc); +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); +} + +/** + * @} end of PID group + */ + + +/** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ +arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32* src, + arm_matrix_instance_f32* dst); + + +/** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ +arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64* src, + arm_matrix_instance_f64* dst); + + + +/** + * @ingroup groupController + */ + +/** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + +/** + * @addtogroup clarke + * @{ + */ + +/** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + */ +CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t* pIalpha, + float32_t* pIbeta) +{ + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); +} + + +/** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ +CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t* pIalpha, + q31_t* pIbeta) +{ + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); +} + +/** + * @} end of clarke group + */ + +/** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void arm_q7_to_q31( + q7_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + + + +/** + * @ingroup groupController + */ + +/** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + +/** + * @addtogroup inv_clarke + * @{ + */ + +/** +* @brief Floating-point Inverse Clarke transform +* @param[in] Ialpha input two-phase orthogonal vector axis alpha +* @param[in] Ibeta input two-phase orthogonal vector axis beta +* @param[out] pIa points to output three-phase coordinate a +* @param[out] pIb points to output three-phase coordinate b +*/ +CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t* pIa, + float32_t* pIb) +{ + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; +} + + +/** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ +CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t* pIa, + q31_t* pIb) +{ + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); +} + +/** + * @} end of inv_clarke group + */ + +/** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void arm_q7_to_q15( + q7_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + + + +/** + * @ingroup groupController + */ + +/** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + +/** + * @addtogroup park + * @{ + */ + +/** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * The function implements the forward Park transform. + * + */ +CMSIS_INLINE __STATIC_INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t* pId, + float32_t* pIq, + float32_t sinVal, + float32_t cosVal) +{ + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; +} + + +/** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ +CMSIS_INLINE __STATIC_INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t* pId, + q31_t* pIq, + q31_t sinVal, + q31_t cosVal) +{ + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); +} + +/** + * @} end of park group + */ + +/** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ +void arm_q7_to_float( + q7_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + + +/** + * @ingroup groupController + */ + +/** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + +/** + * @addtogroup inv_park + * @{ + */ + +/** +* @brief Floating-point Inverse Park transform +* @param[in] Id input coordinate of rotor reference frame d +* @param[in] Iq input coordinate of rotor reference frame q +* @param[out] pIalpha points to output two-phase orthogonal vector axis alpha +* @param[out] pIbeta points to output two-phase orthogonal vector axis beta +* @param[in] sinVal sine value of rotation angle theta +* @param[in] cosVal cosine value of rotation angle theta +*/ +CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t* pIalpha, + float32_t* pIbeta, + float32_t sinVal, + float32_t cosVal) +{ + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; +} + + +/** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ +CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t* pIalpha, + q31_t* pIbeta, + q31_t sinVal, + q31_t cosVal) +{ + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); +} + +/** + * @} end of Inverse park group + */ + + +/** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ +void arm_q31_to_float( + q31_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + +/** + * @ingroup groupInterpolation + */ + +/** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+ *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+ *       where x0, x1 are nearest values of input x
+ *             y0, y1 are nearest values to output y
+ *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + +/** + * @addtogroup LinearInterpolate + * @{ + */ + +/** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ +CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32* S, + float32_t x) +{ + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t* pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if (i < 0) { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if ((uint32_t)i >= S->nValues) { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); +} + + +/** +* +* @brief Process function for the Q31 Linear Interpolation Function. +* @param[in] pYData pointer to Q31 Linear Interpolation table +* @param[in] x input sample to process +* @param[in] nValues number of table values +* @return y processed output sample. +* +* \par +* Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. +* This function can support maximum of table size 2^12. +* +*/ +CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31( + q31_t* pYData, + q31_t x, + uint32_t nValues) +{ + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (q31_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) { + return (pYData[nValues - 1]); + } + else if (index < 0) { + return (pYData[0]); + } + else { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1u); + } +} + + +/** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ +CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15( + q15_t* pYData, + q31_t x, + uint32_t nValues) +{ + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (int32_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) { + return (pYData[nValues - 1]); + } + else if (index < 0) { + return (pYData[0]); + } + else { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (q15_t) (y >> 20); + } +} + + +/** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ +CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7( + q7_t* pYData, + q31_t x, + uint32_t nValues) +{ + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + if (index >= (nValues - 1)) { + return (pYData[nValues - 1]); + } + else { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (q7_t) (y >> 20); + } +} + +/** + * @} end of LinearInterpolate group + */ + +/** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ +float32_t arm_sin_f32( + float32_t x); + + +/** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ +q31_t arm_sin_q31( + q31_t x); + + +/** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ +q15_t arm_sin_q15( + q15_t x); + + +/** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ +float32_t arm_cos_f32( + float32_t x); + + +/** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ +q31_t arm_cos_q31( + q31_t x); + + +/** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ +q15_t arm_cos_q15( + q15_t x); + + +/** + * @ingroup groupFastMath + */ + + +/** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+ *      x1 = x0 - f(x0)/f'(x0)
+ *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+ *     x0 = in/2                         [initial guess]
+ *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+ *
+ */ + + +/** + * @addtogroup SQRT + * @{ + */ + +/** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ +CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t* pOut) +{ + if (in >= 0.0f) { + +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined(__GNUC__) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) + __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } +} + + +/** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ +arm_status arm_sqrt_q31( + q31_t in, + q31_t* pOut); + + +/** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ +arm_status arm_sqrt_q15( + q15_t in, + q15_t* pOut); + +/** + * @} end of SQRT group + */ + + +/** + * @brief floating-point Circular write function. + */ +CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32( + int32_t* circBuffer, + int32_t L, + uint16_t* writeOffset, + int32_t bufferInc, + const int32_t* src, + int32_t srcInc, + uint32_t blockSize) +{ + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0u) { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; +} + + + +/** + * @brief floating-point Circular Read function. + */ +CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32( + int32_t* circBuffer, + int32_t L, + int32_t* readOffset, + int32_t bufferInc, + int32_t* dst, + int32_t* dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) +{ + uint32_t i = 0u; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0u) { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (int32_t*) dst_end) { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; +} + + +/** + * @brief Q15 Circular write function. + */ +CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15( + q15_t* circBuffer, + int32_t L, + uint16_t* writeOffset, + int32_t bufferInc, + const q15_t* src, + int32_t srcInc, + uint32_t blockSize) +{ + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0u) { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; +} + + +/** + * @brief Q15 Circular Read function. + */ +CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15( + q15_t* circBuffer, + int32_t L, + int32_t* readOffset, + int32_t bufferInc, + q15_t* dst, + q15_t* dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) +{ + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0u) { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (q15_t*) dst_end) { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; +} + + +/** + * @brief Q7 Circular write function. + */ +CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7( + q7_t* circBuffer, + int32_t L, + uint16_t* writeOffset, + int32_t bufferInc, + const q7_t* src, + int32_t srcInc, + uint32_t blockSize) +{ + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0u) { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; +} + + +/** + * @brief Q7 Circular Read function. + */ +CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7( + q7_t* circBuffer, + int32_t L, + int32_t* readOffset, + int32_t bufferInc, + q7_t* dst, + q7_t* dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) +{ + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0u) { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (q7_t*) dst_end) { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; +} + + +/** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_power_q31( + q31_t* pSrc, + uint32_t blockSize, + q63_t* pResult); + + +/** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_power_f32( + float32_t* pSrc, + uint32_t blockSize, + float32_t* pResult); + + +/** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_power_q15( + q15_t* pSrc, + uint32_t blockSize, + q63_t* pResult); + + +/** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_power_q7( + q7_t* pSrc, + uint32_t blockSize, + q31_t* pResult); + + +/** + * @brief Mean value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_mean_q7( + q7_t* pSrc, + uint32_t blockSize, + q7_t* pResult); + + +/** + * @brief Mean value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_mean_q15( + q15_t* pSrc, + uint32_t blockSize, + q15_t* pResult); + + +/** + * @brief Mean value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_mean_q31( + q31_t* pSrc, + uint32_t blockSize, + q31_t* pResult); + + +/** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_mean_f32( + float32_t* pSrc, + uint32_t blockSize, + float32_t* pResult); + + +/** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_var_f32( + float32_t* pSrc, + uint32_t blockSize, + float32_t* pResult); + + +/** + * @brief Variance of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_var_q31( + q31_t* pSrc, + uint32_t blockSize, + q31_t* pResult); + + +/** + * @brief Variance of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_var_q15( + q15_t* pSrc, + uint32_t blockSize, + q15_t* pResult); + + +/** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_rms_f32( + float32_t* pSrc, + uint32_t blockSize, + float32_t* pResult); + + +/** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_rms_q31( + q31_t* pSrc, + uint32_t blockSize, + q31_t* pResult); + + +/** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_rms_q15( + q15_t* pSrc, + uint32_t blockSize, + q15_t* pResult); + + +/** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_std_f32( + float32_t* pSrc, + uint32_t blockSize, + float32_t* pResult); + + +/** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_std_q31( + q31_t* pSrc, + uint32_t blockSize, + q31_t* pResult); + + +/** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_std_q15( + q15_t* pSrc, + uint32_t blockSize, + q15_t* pResult); + + +/** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ +void arm_cmplx_mag_f32( + float32_t* pSrc, + float32_t* pDst, + uint32_t numSamples); + + +/** + * @brief Q31 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ +void arm_cmplx_mag_q31( + q31_t* pSrc, + q31_t* pDst, + uint32_t numSamples); + + +/** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ +void arm_cmplx_mag_q15( + q15_t* pSrc, + q15_t* pDst, + uint32_t numSamples); + + +/** + * @brief Q15 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ +void arm_cmplx_dot_prod_q15( + q15_t* pSrcA, + q15_t* pSrcB, + uint32_t numSamples, + q31_t* realResult, + q31_t* imagResult); + + +/** + * @brief Q31 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ +void arm_cmplx_dot_prod_q31( + q31_t* pSrcA, + q31_t* pSrcB, + uint32_t numSamples, + q63_t* realResult, + q63_t* imagResult); + + +/** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ +void arm_cmplx_dot_prod_f32( + float32_t* pSrcA, + float32_t* pSrcB, + uint32_t numSamples, + float32_t* realResult, + float32_t* imagResult); + + +/** + * @brief Q15 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ +void arm_cmplx_mult_real_q15( + q15_t* pSrcCmplx, + q15_t* pSrcReal, + q15_t* pCmplxDst, + uint32_t numSamples); + + +/** + * @brief Q31 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ +void arm_cmplx_mult_real_q31( + q31_t* pSrcCmplx, + q31_t* pSrcReal, + q31_t* pCmplxDst, + uint32_t numSamples); + + +/** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ +void arm_cmplx_mult_real_f32( + float32_t* pSrcCmplx, + float32_t* pSrcReal, + float32_t* pCmplxDst, + uint32_t numSamples); + + +/** + * @brief Minimum value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ +void arm_min_q7( + q7_t* pSrc, + uint32_t blockSize, + q7_t* result, + uint32_t* index); + + +/** + * @brief Minimum value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ +void arm_min_q15( + q15_t* pSrc, + uint32_t blockSize, + q15_t* pResult, + uint32_t* pIndex); + + +/** + * @brief Minimum value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ +void arm_min_q31( + q31_t* pSrc, + uint32_t blockSize, + q31_t* pResult, + uint32_t* pIndex); + + +/** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ +void arm_min_f32( + float32_t* pSrc, + uint32_t blockSize, + float32_t* pResult, + uint32_t* pIndex); + + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ +void arm_max_q7( + q7_t* pSrc, + uint32_t blockSize, + q7_t* pResult, + uint32_t* pIndex); + + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ +void arm_max_q15( + q15_t* pSrc, + uint32_t blockSize, + q15_t* pResult, + uint32_t* pIndex); + + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ +void arm_max_q31( + q31_t* pSrc, + uint32_t blockSize, + q31_t* pResult, + uint32_t* pIndex); + + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ +void arm_max_f32( + float32_t* pSrc, + uint32_t blockSize, + float32_t* pResult, + uint32_t* pIndex); + + +/** + * @brief Q15 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ +void arm_cmplx_mult_cmplx_q15( + q15_t* pSrcA, + q15_t* pSrcB, + q15_t* pDst, + uint32_t numSamples); + + +/** + * @brief Q31 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ +void arm_cmplx_mult_cmplx_q31( + q31_t* pSrcA, + q31_t* pSrcB, + q31_t* pDst, + uint32_t numSamples); + + +/** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ +void arm_cmplx_mult_cmplx_f32( + float32_t* pSrcA, + float32_t* pSrcB, + float32_t* pDst, + uint32_t numSamples); + + +/** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + */ +void arm_float_to_q31( + float32_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + */ +void arm_float_to_q15( + float32_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + */ +void arm_float_to_q7( + float32_t* pSrc, + q7_t* pDst, + uint32_t blockSize); + + +/** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ +void arm_q31_to_q15( + q31_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ +void arm_q31_to_q7( + q31_t* pSrc, + q7_t* pDst, + uint32_t blockSize); + + +/** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ +void arm_q15_to_float( + q15_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + + +/** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ +void arm_q15_to_q31( + q15_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ +void arm_q15_to_q7( + q15_t* pSrc, + q7_t* pDst, + uint32_t blockSize); + + +/** + * @ingroup groupInterpolation + */ + +/** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+ *   typedef struct
+ *   {
+ *     uint16_t numRows;
+ *     uint16_t numCols;
+ *     float32_t *pData;
+ * } arm_bilinear_interp_instance_f32;
+ *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+ *     XF = floor(x)
+ *     YF = floor(y)
+ *
+ * \par + * The interpolated output point is computed as: + * 
+ *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+ *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+ *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+ *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+ *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + +/** + * @addtogroup BilinearInterpolate + * @{ + */ + + +/** +* +* @brief Floating-point bilinear interpolation. +* @param[in,out] S points to an instance of the interpolation structure. +* @param[in] X interpolation coordinate. +* @param[in] Y interpolation coordinate. +* @return out interpolated value. +*/ +CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32* S, + float32_t X, + float32_t Y) +{ + float32_t out; + float32_t f00, f01, f10, f11; + float32_t* pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); +} + + +/** +* +* @brief Q31 bilinear interpolation. +* @param[in,out] S points to an instance of the interpolation structure. +* @param[in] X interpolation coordinate in 12.20 format. +* @param[in] Y interpolation coordinate in 12.20 format. +* @return out interpolated value. +*/ +CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31* S, + q31_t X, + q31_t Y) +{ + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t* pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; + x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; + y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return ((q31_t)(acc << 2)); +} + + +/** +* @brief Q15 bilinear interpolation. +* @param[in,out] S points to an instance of the interpolation structure. +* @param[in] X interpolation coordinate in 12.20 format. +* @param[in] Y interpolation coordinate in 12.20 format. +* @return out interpolated value. +*/ +CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15* S, + q31_t X, + q31_t Y) +{ + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t* pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return ((q15_t)(acc >> 36)); +} + + +/** +* @brief Q7 bilinear interpolation. +* @param[in,out] S points to an instance of the interpolation structure. +* @param[in] X interpolation coordinate in 12.20 format. +* @param[in] Y interpolation coordinate in 12.20 format. +* @return out interpolated value. +*/ +CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7* S, + q31_t X, + q31_t Y) +{ + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t* pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return ((q7_t)(acc >> 40)); +} + +/** + * @} end of BilinearInterpolate group + */ + + +/* SMMLAR */ +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMLSR */ +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMULR */ +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +/* SMMLA */ +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +/* SMMLS */ +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +/* SMMUL */ +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) +/* Enter low optimization region - place directly above function definition */ +#if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) +#define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") +#else +#define LOW_OPTIMIZATION_ENTER +#endif + +/* Exit low optimization region - place directly after end of function definition */ +#if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) +#define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") +#else +#define LOW_OPTIMIZATION_EXIT +#endif + +/* Enter low optimization region - place directly above function definition */ +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER + +/* Exit low optimization region - place directly after end of function definition */ +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) +#define LOW_OPTIMIZATION_ENTER +#define LOW_OPTIMIZATION_EXIT +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __GNUC__ ) +#define LOW_OPTIMIZATION_ENTER \ + __attribute__(( optimize("-O1") )) +#define LOW_OPTIMIZATION_EXIT +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __ICCARM__ ) +/* Enter low optimization region - place directly above function definition */ +#if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) +#define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") +#else +#define LOW_OPTIMIZATION_ENTER +#endif + +/* Exit low optimization region - place directly after end of function definition */ +#define LOW_OPTIMIZATION_EXIT + +/* Enter low optimization region - place directly above function definition */ +#if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") +#else +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#endif + +/* Exit low optimization region - place directly after end of function definition */ +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TI_ARM__ ) +#define LOW_OPTIMIZATION_ENTER +#define LOW_OPTIMIZATION_EXIT +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __CSMC__ ) +#define LOW_OPTIMIZATION_ENTER +#define LOW_OPTIMIZATION_EXIT +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TASKING__ ) +#define LOW_OPTIMIZATION_ENTER +#define LOW_OPTIMIZATION_EXIT +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + +#ifdef __cplusplus +} +#endif + + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_armcc.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_armcc.h new file mode 100644 index 000000000..4617b1280 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_armcc.h @@ -0,0 +1,796 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (ARM compiler V5) header file + * @version V5.0.1 + * @date 03. February 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) +#error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) +#define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) +#define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) +#define __ARM_ARCH_7EM__ 1 +#endif + +/* __ARM_ARCH_8M_BASE__ not applicable */ +/* __ARM_ARCH_8M_MAIN__ not applicable */ + + +/* CMSIS compiler specific defines */ +#ifndef __ASM +#define __ASM __asm +#endif +#ifndef __INLINE +#define __INLINE __inline +#endif +#ifndef __STATIC_INLINE +#define __STATIC_INLINE static __inline +#endif +#ifndef __NO_RETURN +#define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED +#define __USED __attribute__((used)) +#endif +#ifndef __WEAK +#define __WEAK __attribute__((weak)) +#endif +#ifndef __UNALIGNED_UINT32 +#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __ALIGNED +#define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __PACKED +#define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT +#define __PACKED_STRUCT __packed struct +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) +#define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return(result); +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else +#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else +#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else +#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) +#define __STREXB(value, ptr) __strex(value, ptr) +#else +#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) +#define __STREXH(value, ptr) __strex(value, ptr) +#else +#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) +#define __STREXW(value, ptr) __strex(value, ptr) +#else +#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_armclang.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_armclang.h new file mode 100644 index 000000000..6b21a5bea --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_armclang.h @@ -0,0 +1,1735 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler ARMCLANG (ARM compiler V6) header file + * @version V5.0.1 + * @date 02. February 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for ARM Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM +#define __ASM __asm +#endif +#ifndef __INLINE +#define __INLINE __inline +#endif +#ifndef __STATIC_INLINE +#define __STATIC_INLINE static __inline +#endif +#ifndef __NO_RETURN +#define __NO_RETURN __attribute__((noreturn)) +#endif +#ifndef __USED +#define __USED __attribute__((used)) +#endif +#ifndef __WEAK +#define __WEAK __attribute__((weak)) +#endif +#ifndef __UNALIGNED_UINT32 +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wpacked" +struct __attribute__((packed)) T_UINT32 { + uint32_t v; +}; +#pragma clang diagnostic pop +#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __ALIGNED +#define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __PACKED +#define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT +#define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return(result); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Get Process Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + + return(result); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Get Main Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Set Main Stack Pointer Limit (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +/* #define __get_FPSCR __builtin_arm_get_fpscr */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +/* #define __set_FPSCR __builtin_arm_set_fpscr */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "memory"); +#else + (void)fpscr; +#endif +} + +#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF); + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF); + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF); + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __builtin_bswap32 + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16 __builtin_bswap16 /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */ +#if 0 +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} +#endif + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +/* ToDo ARMCLANG: check if __builtin_bswap16 could be used */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ + int32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +/* ToDo ARMCLANG: check if __builtin_arm_rbit is supported */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return(result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t* ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t* ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t* ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t* ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t* ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t* ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t* ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t* ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t* ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t* ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t* ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t* ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ + ({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_compiler.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_compiler.h new file mode 100644 index 000000000..89cd69027 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_compiler.h @@ -0,0 +1,231 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.0.1 + * @date 30. January 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * ARM Compiler 4/5 + */ +#if defined ( __CC_ARM ) +#include "cmsis_armcc.h" + + +/* + * ARM Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) +#include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + +#ifndef __ASM +#define __ASM __asm +#endif +#ifndef __INLINE +#define __INLINE inline +#endif +#ifndef __STATIC_INLINE +#define __STATIC_INLINE static inline +#endif + +#include + +#ifndef __NO_RETURN +#define __NO_RETURN __noreturn +#endif +#ifndef __USED +#define __USED __root +#endif +#ifndef __WEAK +#define __WEAK __weak +#endif +#ifndef __UNALIGNED_UINT32 +__packed struct T_UINT32 { + uint32_t v; +}; +#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __ALIGNED +#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. +#define __ALIGNED(x) +#endif +#ifndef __PACKED +#define __PACKED __packed +#endif +#ifndef __PACKED_STRUCT +#define __PACKED_STRUCT __packed struct +#endif + + +/* + * TI ARM Compiler + */ +#elif defined ( __TI_ARM__ ) +#include + +#ifndef __ASM +#define __ASM __asm +#endif +#ifndef __INLINE +#define __INLINE inline +#endif +#ifndef __STATIC_INLINE +#define __STATIC_INLINE static inline +#endif +#ifndef __NO_RETURN +#define __NO_RETURN __attribute__((noreturn)) +#endif +#ifndef __USED +#define __USED __attribute__((used)) +#endif +#ifndef __WEAK +#define __WEAK __attribute__((weak)) +#endif +#ifndef __UNALIGNED_UINT32 +struct __attribute__((packed)) T_UINT32 { + uint32_t v; +}; +#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __ALIGNED +#define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __PACKED +#define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT +#define __PACKED_STRUCT struct __attribute__((packed)) +#endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +#ifndef __ASM +#define __ASM __asm +#endif +#ifndef __INLINE +#define __INLINE inline +#endif +#ifndef __STATIC_INLINE +#define __STATIC_INLINE static inline +#endif +#ifndef __NO_RETURN +#define __NO_RETURN __attribute__((noreturn)) +#endif +#ifndef __USED +#define __USED __attribute__((used)) +#endif +#ifndef __WEAK +#define __WEAK __attribute__((weak)) +#endif +#ifndef __UNALIGNED_UINT32 +struct __packed__ T_UINT32 { + uint32_t v; +}; +#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __ALIGNED +#define __ALIGNED(x) __align(x) +#endif +#ifndef __PACKED +#define __PACKED __packed__ +#endif +#ifndef __PACKED_STRUCT +#define __PACKED_STRUCT struct __packed__ +#endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) +#include + +#ifndef __ASM +#define __ASM _asm +#endif +#ifndef __INLINE +#define __INLINE inline +#endif +#ifndef __STATIC_INLINE +#define __STATIC_INLINE static inline +#endif +#ifndef __NO_RETURN +// NO RETURN is automatically detected hence no warning here +#define __NO_RETURN +#endif +#ifndef __USED +#warning No compiler specific solution for __USED. __USED is ignored. +#define __USED +#endif +#ifndef __WEAK +#define __WEAK __weak +#endif +#ifndef __UNALIGNED_UINT32 +@packed struct T_UINT32 { + uint32_t v; +}; +#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __ALIGNED +#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. +#define __ALIGNED(x) +#endif +#ifndef __PACKED +#define __PACKED @packed +#endif +#ifndef __PACKED_STRUCT +#define __PACKED_STRUCT @packed struct +#endif + + +#else +#error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_gcc.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_gcc.h new file mode 100644 index 000000000..919f26d15 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_gcc.h @@ -0,0 +1,1900 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.0.1 + * @date 02. February 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* CMSIS compiler specific defines */ +#ifndef __ASM +#define __ASM __asm +#endif +#ifndef __INLINE +#define __INLINE inline +#endif +#ifndef __STATIC_INLINE +#define __STATIC_INLINE static inline +#endif +#ifndef __NO_RETURN +#define __NO_RETURN __attribute__((noreturn)) +#endif +#ifndef __USED +#define __USED __attribute__((used)) +#endif +#ifndef __WEAK +#define __WEAK __attribute__((weak)) +#endif +#ifndef __UNALIGNED_UINT32 +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpacked" +#pragma GCC diagnostic ignored "-Wattributes" +struct __attribute__((packed)) T_UINT32 { + uint32_t v; +}; +#pragma GCC diagnostic pop +#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __ALIGNED +#define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __PACKED +#define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT +#define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return(result); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Get Process Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + + return(result); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Get Main Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Set Main Stack Pointer Limit (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#else + (void)fpscr; +#endif +} + +#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +//__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) +//{ +// __ASM volatile ("nop"); +//} +#define __NOP() __ASM volatile ("nop") /* This implementation generates debug information */ + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +//__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) +//{ +// __ASM volatile ("wfi"); +//} +#define __WFI() __ASM volatile ("wfi") /* This implementation generates debug information */ + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +//__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) +//{ +// __ASM volatile ("wfe"); +//} +#define __WFE() __ASM volatile ("wfe") /* This implementation generates debug information */ + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +//__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) +//{ +// __ASM volatile ("sev"); +//} +#define __SEV() __ASM volatile ("sev") /* This implementation generates debug information */ + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF"::: "memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF"::: "memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF"::: "memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + int32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return(result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t* addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t* addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t* addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t* addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t* addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t* addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ + ({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t* ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t* ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t* ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t* ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t* ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t* ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t* ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t* ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t* ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t* ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t* ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t* ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAEXB(volatile uint8_t* ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAEXH(volatile uint16_t* ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDAEX(volatile uint32_t* ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t* ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t* ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEX(uint32_t value, volatile uint32_t* ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__ARM_FEATURE_DSP == 1) /* ToDo ARMCLANG: This should be ARCH >= ARMv7-M + SIMD */ + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ + ({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_armv8mbl.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_armv8mbl.h new file mode 100644 index 000000000..4e65d1d95 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_armv8mbl.h @@ -0,0 +1,1813 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS ARMv8MBL Core Peripheral Access Layer Header File + * @version V5.0.1 + * @date 25. November 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) +#pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +/* CMSIS cmGrebe definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) +#if defined __TARGET_FPU_VFP +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#if defined __ARM_PCS_VFP +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __ICCARM__ ) +#if defined __ARMVFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TI_ARM__ ) +#if defined __TI_VFP_SUPPORT__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TASKING__ ) +#if defined __FPU_VFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __CSMC__ ) +#if ( __CSMC__ & 0x400U) +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus +extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __ARMv8MBL_REV +#define __ARMv8MBL_REV 0x0000U +#warning "__ARMv8MBL_REV not defined in device header file; using default!" +#endif + +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 0U +#warning "__FPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0U +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __SAUREGION_PRESENT +#define __SAUREGION_PRESENT 0U +#warning "__SAUREGION_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __VTOR_PRESENT +#define __VTOR_PRESENT 0U +#warning "__VTOR_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 2U +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0U +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif + +#ifndef __ETM_PRESENT +#define __ETM_PRESENT 0U +#warning "__ETM_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __MTB_PRESENT +#define __MTB_PRESENT 0U +#warning "__MTB_PRESENT not defined in device header file; using default!" +#endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union { + struct { + uint32_t _reserved0: 28; /*!< bit: 0..27 Reserved */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */ + uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1: 3; /*!< bit: 25..27 Reserved */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union { + struct { + uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL: 1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct { + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct { + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct { + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct { + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct { + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct { + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct { + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct { + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ +#define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ +#define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ +#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ +#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ +#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + +#define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ +#define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ +#define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ +#define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ +#define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ +#endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifndef CMSIS_NVIC_VIRTUAL +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for ARMv8-M Baseline */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for ARMv8-M Baseline */ +#define NVIC_EnableIRQ __NVIC_EnableIRQ +#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ +#define NVIC_DisableIRQ __NVIC_DisableIRQ +#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ +#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ +#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +#define NVIC_GetActive __NVIC_GetActive +#define NVIC_SetPriority __NVIC_SetPriority +#define NVIC_GetPriority __NVIC_GetPriority +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifndef CMSIS_VECTAB_VIRTUAL +#define NVIC_SetVector __NVIC_SetVector +#define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t* vectors = (uint32_t*)SCB->VTOR; +#else + uint32_t* vectors = (uint32_t*)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t* vectors = (uint32_t*)SCB->VTOR; +#else + uint32_t* vectors = (uint32_t*)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) { /* wait until reset */ + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_armv8mml.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_armv8mml.h new file mode 100644 index 000000000..273c3849c --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_armv8mml.h @@ -0,0 +1,2821 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS ARMv8MML Core Peripheral Access Layer Header File + * @version V5.0.2 + * @date 07. December 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) +#pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +/* CMSIS ARMv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) +#if defined __TARGET_FPU_VFP +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#if defined __ARM_PCS_VFP +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __ICCARM__ ) +#if defined __ARMVFP__ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __TI_ARM__ ) +#if defined __TI_VFP_SUPPORT__ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __TASKING__ ) +#if defined __FPU_VFP__ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __CSMC__ ) +#if ( __CSMC__ & 0x400U) +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus +extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __ARMv8MML_REV +#define __ARMv8MML_REV 0x0000U +#warning "__ARMv8MML_REV not defined in device header file; using default!" +#endif + +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 0U +#warning "__FPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0U +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __SAUREGION_PRESENT +#define __SAUREGION_PRESENT 0U +#warning "__SAUREGION_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __DSP_PRESENT +#define __DSP_PRESENT 0U +#warning "__DSP_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 3U +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0U +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union { + struct { + uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 7; /*!< bit: 9..15 Reserved */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 4; /*!< bit: 20..23 Reserved */ + uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT: 2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union { + struct { + uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL: 1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA: 1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA: 1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1: 28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct { + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct { + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct { + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct { + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct { + __OM union { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct { + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct { + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct { + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct { + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct { + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct { + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ +#define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ +#define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ +#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ +#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ +#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + +#define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ +#define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ +#define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ +#define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ +#define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ +#define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ +#endif + +#define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ +#define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifndef CMSIS_NVIC_VIRTUAL +#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping +#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping +#define NVIC_EnableIRQ __NVIC_EnableIRQ +#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ +#define NVIC_DisableIRQ __NVIC_DisableIRQ +#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ +#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ +#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +#define NVIC_GetActive __NVIC_GetActive +#define NVIC_SetPriority __NVIC_SetPriority +#define NVIC_GetPriority __NVIC_GetPriority +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifndef CMSIS_VECTAB_VIRTUAL +#define NVIC_SetVector __NVIC_SetVector +#define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else { + SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) { + return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else { + return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t* vectors = (uint32_t*)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t* vectors = (uint32_t*)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) { /* wait until reset */ + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else { + SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { + return 1U; /* Single precision FPU */ + } + else { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) { /* ITM Port #0 enabled */ + while (ITM->PORT[0U].u32 == 0UL) { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } + else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm0.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm0.h new file mode 100644 index 000000000..d06d984b7 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm0.h @@ -0,0 +1,850 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.1 + * @date 25. November 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) +#pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) +#if defined __TARGET_FPU_VFP +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#if defined __ARM_PCS_VFP +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __ICCARM__ ) +#if defined __ARMVFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TI_ARM__ ) +#if defined __TI_VFP_SUPPORT__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TASKING__ ) +#if defined __FPU_VFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __CSMC__ ) +#if ( __CSMC__ & 0x400U) +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus +extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __CM0_REV +#define __CM0_REV 0x0000U +#warning "__CM0_REV not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 2U +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0U +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union { + struct { + uint32_t _reserved0: 28; /*!< bit: 0..27 Reserved */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */ + uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1: 3; /*!< bit: 25..27 Reserved */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union { + struct { + uint32_t _reserved0: 1; /*!< bit: 0 Reserved */ + uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct { + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct { + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct { + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifndef CMSIS_NVIC_VIRTUAL +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0 */ +#define NVIC_EnableIRQ __NVIC_EnableIRQ +#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ +#define NVIC_DisableIRQ __NVIC_DisableIRQ +#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ +#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ +#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ +#define NVIC_SetPriority __NVIC_SetPriority +#define NVIC_GetPriority __NVIC_GetPriority +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifndef CMSIS_VECTAB_VIRTUAL +#define NVIC_SetVector __NVIC_SetVector +#define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t* vectors = (uint32_t*)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t* vectors = (uint32_t*)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) { /* wait until reset */ + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm0plus.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm0plus.h new file mode 100644 index 000000000..ebc43f3a1 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm0plus.h @@ -0,0 +1,975 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.1 + * @date 25. November 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) +#pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) +#if defined __TARGET_FPU_VFP +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#if defined __ARM_PCS_VFP +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __ICCARM__ ) +#if defined __ARMVFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TI_ARM__ ) +#if defined __TI_VFP_SUPPORT__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TASKING__ ) +#if defined __FPU_VFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __CSMC__ ) +#if ( __CSMC__ & 0x400U) +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus +extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __CM0PLUS_REV +#define __CM0PLUS_REV 0x0000U +#warning "__CM0PLUS_REV not defined in device header file; using default!" +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0U +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __VTOR_PRESENT +#define __VTOR_PRESENT 0U +#warning "__VTOR_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 2U +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0U +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union { + struct { + uint32_t _reserved0: 28; /*!< bit: 0..27 Reserved */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */ + uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1: 3; /*!< bit: 25..27 Reserved */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union { + struct { + uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct { + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct { + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct { + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct { + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifndef CMSIS_NVIC_VIRTUAL +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0+ */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0+ */ +#define NVIC_EnableIRQ __NVIC_EnableIRQ +#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ +#define NVIC_DisableIRQ __NVIC_DisableIRQ +#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ +#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ +#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ +#define NVIC_SetPriority __NVIC_SetPriority +#define NVIC_GetPriority __NVIC_GetPriority +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifndef CMSIS_VECTAB_VIRTUAL +#define NVIC_SetVector __NVIC_SetVector +#define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t* vectors = (uint32_t*)SCB->VTOR; +#else + uint32_t* vectors = (uint32_t*)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t* vectors = (uint32_t*)SCB->VTOR; +#else + uint32_t* vectors = (uint32_t*)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; + +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) { /* wait until reset */ + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm23.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm23.h new file mode 100644 index 000000000..513635a58 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm23.h @@ -0,0 +1,1813 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.0.1 + * @date 25. November 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) +#pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +/* CMSIS cmGrebe definitions */ +#define __CM23_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) +#if defined __TARGET_FPU_VFP +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#if defined __ARM_PCS_VFP +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __ICCARM__ ) +#if defined __ARMVFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TI_ARM__ ) +#if defined __TI_VFP_SUPPORT__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TASKING__ ) +#if defined __FPU_VFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __CSMC__ ) +#if ( __CSMC__ & 0x400U) +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus +extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __CM23_REV +#define __CM23_REV 0x0000U +#warning "__CM23_REV not defined in device header file; using default!" +#endif + +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 0U +#warning "__FPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0U +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __SAUREGION_PRESENT +#define __SAUREGION_PRESENT 0U +#warning "__SAUREGION_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __VTOR_PRESENT +#define __VTOR_PRESENT 0U +#warning "__VTOR_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 2U +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0U +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif + +#ifndef __ETM_PRESENT +#define __ETM_PRESENT 0U +#warning "__ETM_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __MTB_PRESENT +#define __MTB_PRESENT 0U +#warning "__MTB_PRESENT not defined in device header file; using default!" +#endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union { + struct { + uint32_t _reserved0: 28; /*!< bit: 0..27 Reserved */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */ + uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1: 3; /*!< bit: 25..27 Reserved */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union { + struct { + uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL: 1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct { + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct { + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct { + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct { + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct { + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct { + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct { + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct { + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ +#define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ +#define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ +#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ +#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ +#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + +#define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ +#define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ +#define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ +#define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ +#define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ +#endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifndef CMSIS_NVIC_VIRTUAL +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ +#define NVIC_EnableIRQ __NVIC_EnableIRQ +#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ +#define NVIC_DisableIRQ __NVIC_DisableIRQ +#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ +#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ +#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +#define NVIC_GetActive __NVIC_GetActive +#define NVIC_SetPriority __NVIC_SetPriority +#define NVIC_GetPriority __NVIC_GetPriority +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifndef CMSIS_VECTAB_VIRTUAL +#define NVIC_SetVector __NVIC_SetVector +#define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t* vectors = (uint32_t*)SCB->VTOR; +#else + uint32_t* vectors = (uint32_t*)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t* vectors = (uint32_t*)SCB->VTOR; +#else + uint32_t* vectors = (uint32_t*)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) { /* wait until reset */ + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm3.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm3.h new file mode 100644 index 000000000..8cbf329b8 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm3.h @@ -0,0 +1,1880 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.0.1 + * @date 30. January 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) +#pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) +#if defined __TARGET_FPU_VFP +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#if defined __ARM_PCS_VFP +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __ICCARM__ ) +#if defined __ARMVFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TI_ARM__ ) +#if defined __TI_VFP_SUPPORT__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TASKING__ ) +#if defined __FPU_VFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __CSMC__ ) +#if ( __CSMC__ & 0x400U) +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus +extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __CM3_REV +#define __CM3_REV 0x0200U +#warning "__CM3_REV not defined in device header file; using default!" +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0U +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 3U +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0U +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union { + struct { + uint32_t _reserved0: 27; /*!< bit: 0..26 Reserved */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1: 6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1: 8; /*!< bit: 16..23 Reserved */ + uint32_t T: 1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2: 2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union { + struct { + uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct { + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct { + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct { + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct { + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct { + __OM union { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct { + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct { + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct { + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct { + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL +#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE +#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" +#endif +#include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping +#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping +#define NVIC_EnableIRQ __NVIC_EnableIRQ +#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ +#define NVIC_DisableIRQ __NVIC_DisableIRQ +#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ +#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ +#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +#define NVIC_GetActive __NVIC_GetActive +#define NVIC_SetPriority __NVIC_SetPriority +#define NVIC_GetPriority __NVIC_GetPriority +#define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL +#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" +#endif +#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else +#define NVIC_SetVector __NVIC_SetVector +#define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t* vectors = (uint32_t*)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t* vectors = (uint32_t*)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) { /* wait until reset */ + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) { /* ITM Port #0 enabled */ + while (ITM->PORT[0U].u32 == 0UL) { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } + else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm33.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm33.h new file mode 100644 index 000000000..00de7795e --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm33.h @@ -0,0 +1,2821 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.0.2 + * @date 07. December 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) +#pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) +#if defined __TARGET_FPU_VFP +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#if defined __ARM_PCS_VFP +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __ICCARM__ ) +#if defined __ARMVFP__ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __TI_ARM__ ) +#if defined __TI_VFP_SUPPORT__ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __TASKING__ ) +#if defined __FPU_VFP__ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __CSMC__ ) +#if ( __CSMC__ & 0x400U) +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus +extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __CM33_REV +#define __CM33_REV 0x0000U +#warning "__CM33_REV not defined in device header file; using default!" +#endif + +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 0U +#warning "__FPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0U +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __SAUREGION_PRESENT +#define __SAUREGION_PRESENT 0U +#warning "__SAUREGION_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __DSP_PRESENT +#define __DSP_PRESENT 0U +#warning "__DSP_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 3U +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0U +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union { + struct { + uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 7; /*!< bit: 9..15 Reserved */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 4; /*!< bit: 20..23 Reserved */ + uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT: 2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union { + struct { + uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL: 1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA: 1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA: 1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1: 28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct { + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct { + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct { + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct { + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct { + __OM union { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct { + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct { + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct { + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct { + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct { + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct { + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ +#define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ +#define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ +#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ +#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ +#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + +#define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ +#define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ +#define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ +#define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ +#define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ +#define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ +#endif + +#define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ +#define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifndef CMSIS_NVIC_VIRTUAL +#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping +#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping +#define NVIC_EnableIRQ __NVIC_EnableIRQ +#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ +#define NVIC_DisableIRQ __NVIC_DisableIRQ +#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ +#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ +#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +#define NVIC_GetActive __NVIC_GetActive +#define NVIC_SetPriority __NVIC_SetPriority +#define NVIC_GetPriority __NVIC_GetPriority +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifndef CMSIS_VECTAB_VIRTUAL +#define NVIC_SetVector __NVIC_SetVector +#define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else { + SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) { + return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else { + return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t* vectors = (uint32_t*)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t* vectors = (uint32_t*)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) { /* wait until reset */ + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else { + SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { + return 1U; /* Single precision FPU */ + } + else { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) { /* ITM Port #0 enabled */ + while (ITM->PORT[0U].u32 == 0UL) { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } + else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm4.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm4.h new file mode 100644 index 000000000..f4c8011f8 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm4.h @@ -0,0 +1,2061 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.0.1 + * @date 30. January 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) +#pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) +#if defined __TARGET_FPU_VFP +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#if defined __ARM_PCS_VFP +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __ICCARM__ ) +#if defined __ARMVFP__ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __TI_ARM__ ) +#if defined __TI_VFP_SUPPORT__ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __TASKING__ ) +#if defined __FPU_VFP__ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __CSMC__ ) +#if ( __CSMC__ & 0x400U) +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus +extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __CM4_REV +#define __CM4_REV 0x0000U +#warning "__CM4_REV not defined in device header file; using default!" +#endif + +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 0U +#warning "__FPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0U +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 3U +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0U +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union { + struct { + uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1: 6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 4; /*!< bit: 20..23 Reserved */ + uint32_t T: 1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2: 2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union { + struct { + uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA: 1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0: 29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct { + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct { + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct { + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct { + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct { + __OM union { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct { + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct { + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct { + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct { + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct { + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL +#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE +#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" +#endif +#include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping +#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping +#define NVIC_EnableIRQ __NVIC_EnableIRQ +#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ +#define NVIC_DisableIRQ __NVIC_DisableIRQ +#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ +#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ +#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +#define NVIC_GetActive __NVIC_GetActive +#define NVIC_SetPriority __NVIC_SetPriority +#define NVIC_GetPriority __NVIC_GetPriority +#define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL +#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" +#endif +#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else +#define NVIC_SetVector __NVIC_SetVector +#define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t* vectors = (uint32_t*)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t* vectors = (uint32_t*)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) { /* wait until reset */ + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { + return 1U; /* Single precision FPU */ + } + else { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) { /* ITM Port #0 enabled */ + while (ITM->PORT[0U].u32 == 0UL) { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } + else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm7.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm7.h new file mode 100644 index 000000000..c09acc824 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm7.h @@ -0,0 +1,2592 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.0.1 + * @date 25. November 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) +#pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) +#if defined __TARGET_FPU_VFP +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#if defined __ARM_PCS_VFP +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __ICCARM__ ) +#if defined __ARMVFP__ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __TI_ARM__ ) +#if defined __TI_VFP_SUPPORT__ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __TASKING__ ) +#if defined __FPU_VFP__ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __CSMC__ ) +#if ( __CSMC__ & 0x400U) +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus +extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __CM7_REV +#define __CM7_REV 0x0000U +#warning "__CM7_REV not defined in device header file; using default!" +#endif + +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 0U +#warning "__FPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0U +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __ICACHE_PRESENT +#define __ICACHE_PRESENT 0U +#warning "__ICACHE_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __DCACHE_PRESENT +#define __DCACHE_PRESENT 0U +#warning "__DCACHE_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __DTCM_PRESENT +#define __DTCM_PRESENT 0U +#warning "__DTCM_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 3U +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0U +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union { + struct { + uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1: 6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 4; /*!< bit: 20..23 Reserved */ + uint32_t T: 1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2: 2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union { + struct { + uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA: 1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0: 29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct { + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct { + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct { + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct { + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct { + __OM union { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct { + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct { + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct { + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct { + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct { + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifndef CMSIS_NVIC_VIRTUAL +#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping +#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping +#define NVIC_EnableIRQ __NVIC_EnableIRQ +#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ +#define NVIC_DisableIRQ __NVIC_DisableIRQ +#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ +#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ +#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +#define NVIC_GetActive __NVIC_GetActive +#define NVIC_SetPriority __NVIC_SetPriority +#define NVIC_GetPriority __NVIC_GetPriority +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifndef CMSIS_VECTAB_VIRTUAL +#define NVIC_SetVector __NVIC_SetVector +#define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else { + SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else { + return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t* vectors = (uint32_t*)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t* vectors = (uint32_t*)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) { /* wait until reset */ + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { + return 1U; /* Single precision FPU */ + } + else { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_INLINE void SCB_EnableICache (void) +{ +#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); +#endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_INLINE void SCB_DisableICache (void) +{ +#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); +#endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_INLINE void SCB_InvalidateICache (void) +{ +#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); +#endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_INLINE void SCB_EnableDCache (void) +{ +#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); +#if defined ( __CC_ARM ) + __schedule_barrier(); +#endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); +#endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_INLINE void SCB_DisableDCache (void) +{ +#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + register uint32_t ccsidr; + register uint32_t sets; + register uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); +#if defined ( __CC_ARM ) + __schedule_barrier(); +#endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); +#endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_INLINE void SCB_InvalidateDCache (void) +{ +#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); +#if defined ( __CC_ARM ) + __schedule_barrier(); +#endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); +#endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_INLINE void SCB_CleanDCache (void) +{ +#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); +#if defined ( __CC_ARM ) + __schedule_barrier(); +#endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); +#endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_INLINE void SCB_CleanInvalidateDCache (void) +{ +#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); +#if defined ( __CC_ARM ) + __schedule_barrier(); +#endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); +#endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t* addr, int32_t dsize) +{ +#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t)addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); +#endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t* addr, int32_t dsize) +{ +#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); +#endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t* addr, int32_t dsize) +{ +#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); +#endif +} + + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) { /* ITM Port #0 enabled */ + while (ITM->PORT[0U].u32 == 0UL) { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } + else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_sc000.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_sc000.h new file mode 100644 index 000000000..ed1063364 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_sc000.h @@ -0,0 +1,976 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.1 + * @date 25. November 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) +#pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) +#if defined __TARGET_FPU_VFP +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#if defined __ARM_PCS_VFP +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __ICCARM__ ) +#if defined __ARMVFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TI_ARM__ ) +#if defined __TI_VFP_SUPPORT__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TASKING__ ) +#if defined __FPU_VFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __CSMC__ ) +#if ( __CSMC__ & 0x400U) +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus +extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __SC000_REV +#define __SC000_REV 0x0000U +#warning "__SC000_REV not defined in device header file; using default!" +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0U +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 2U +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0U +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union { + struct { + uint32_t _reserved0: 28; /*!< bit: 0..27 Reserved */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */ + uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1: 3; /*!< bit: 25..27 Reserved */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union { + struct { + uint32_t _reserved0: 1; /*!< bit: 0 Reserved */ + uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct { + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct { + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct { + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct { + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct { + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifndef CMSIS_NVIC_VIRTUAL +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ +#define NVIC_EnableIRQ __NVIC_EnableIRQ +#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ +#define NVIC_DisableIRQ __NVIC_DisableIRQ +#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ +#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ +#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ +#define NVIC_SetPriority __NVIC_SetPriority +#define NVIC_GetPriority __NVIC_GetPriority +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifndef CMSIS_VECTAB_VIRTUAL +#define NVIC_SetVector __NVIC_SetVector +#define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t* vectors = (uint32_t*)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t* vectors = (uint32_t*)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) { /* wait until reset */ + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_sc300.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_sc300.h new file mode 100644 index 000000000..a1b17e1ce --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_sc300.h @@ -0,0 +1,1851 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.1 + * @date 25. November 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) +#pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) +#if defined __TARGET_FPU_VFP +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#if defined __ARM_PCS_VFP +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __ICCARM__ ) +#if defined __ARMVFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TI_ARM__ ) +#if defined __TI_VFP_SUPPORT__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TASKING__ ) +#if defined __FPU_VFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __CSMC__ ) +#if ( __CSMC__ & 0x400U) +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus +extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __SC300_REV +#define __SC300_REV 0x0000U +#warning "__SC300_REV not defined in device header file; using default!" +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0U +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 3U +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0U +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union { + struct { + uint32_t _reserved0: 27; /*!< bit: 0..26 Reserved */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1: 6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1: 8; /*!< bit: 16..23 Reserved */ + uint32_t T: 1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2: 2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union { + struct { + uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct { + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct { + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct { + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + uint32_t RESERVED1[1U]; +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct { + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct { + __OM union { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct { + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct { + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct { + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct { + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifndef CMSIS_NVIC_VIRTUAL +#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping +#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping +#define NVIC_EnableIRQ __NVIC_EnableIRQ +#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ +#define NVIC_DisableIRQ __NVIC_DisableIRQ +#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ +#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ +#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +#define NVIC_GetActive __NVIC_GetActive +#define NVIC_SetPriority __NVIC_SetPriority +#define NVIC_GetPriority __NVIC_GetPriority +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifndef CMSIS_VECTAB_VIRTUAL +#define NVIC_SetVector __NVIC_SetVector +#define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t* vectors = (uint32_t*)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t* vectors = (uint32_t*)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) { /* wait until reset */ + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) { /* ITM Port #0 enabled */ + while (ITM->PORT[0U].u32 == 0UL) { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } + else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/tz_context.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/tz_context.h new file mode 100644 index 000000000..cd6d8ab07 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/tz_context.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2015-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------------- + * + * $Date: 21. September 2016 + * $Revision: V1.0 + * + * Project: TrustZone for ARMv8-M + * Title: Context Management for ARMv8-M TrustZone + * + * Version 1.0 + * Initial Release + *---------------------------------------------------------------------------*/ + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_common_tables.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_common_tables.h new file mode 100644 index 000000000..dfea7460e --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_common_tables.h @@ -0,0 +1,121 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_common_tables.h + * Description: Extern declaration for common tables + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +extern const float32_t twiddleCoef_16[32]; +extern const float32_t twiddleCoef_32[64]; +extern const float32_t twiddleCoef_64[128]; +extern const float32_t twiddleCoef_128[256]; +extern const float32_t twiddleCoef_256[512]; +extern const float32_t twiddleCoef_512[1024]; +extern const float32_t twiddleCoef_1024[2048]; +extern const float32_t twiddleCoef_2048[4096]; +extern const float32_t twiddleCoef_4096[8192]; +#define twiddleCoef twiddleCoef_4096 +extern const q31_t twiddleCoef_16_q31[24]; +extern const q31_t twiddleCoef_32_q31[48]; +extern const q31_t twiddleCoef_64_q31[96]; +extern const q31_t twiddleCoef_128_q31[192]; +extern const q31_t twiddleCoef_256_q31[384]; +extern const q31_t twiddleCoef_512_q31[768]; +extern const q31_t twiddleCoef_1024_q31[1536]; +extern const q31_t twiddleCoef_2048_q31[3072]; +extern const q31_t twiddleCoef_4096_q31[6144]; +extern const q15_t twiddleCoef_16_q15[24]; +extern const q15_t twiddleCoef_32_q15[48]; +extern const q15_t twiddleCoef_64_q15[96]; +extern const q15_t twiddleCoef_128_q15[192]; +extern const q15_t twiddleCoef_256_q15[384]; +extern const q15_t twiddleCoef_512_q15[768]; +extern const q15_t twiddleCoef_1024_q15[1536]; +extern const q15_t twiddleCoef_2048_q15[3072]; +extern const q15_t twiddleCoef_4096_q15[6144]; +extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_4096[4096]; + +/* floating-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20) +#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48) +#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56) +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) +#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800) +#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808) +#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH]; + +/* fixed-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12) +#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24) +#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56) +#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112) +#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240) +#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480) +#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992) +#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) +#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + +/* Tables for Fast Math Sine and Cosine */ +extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; +extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; +extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_const_structs.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_const_structs.h new file mode 100644 index 000000000..84ffe8b85 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_const_structs.h @@ -0,0 +1,66 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_const_structs.h + * Description: Constant structs that are initialized for user convenience. + * For example, some can be given as arguments to the arm_cfft_f32() function. + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; + +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; + +#endif diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_math.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_math.h new file mode 100644 index 000000000..9d678052b --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_math.h @@ -0,0 +1,7122 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_math.h + * Description: Public header file for CMSIS DSP Library + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * ------------ + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit) + * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit) + * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit) + * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on) + * - arm_cortexM7l_math.lib (Cortex-M7, Little endian) + * - arm_cortexM7b_math.lib (Cortex-M7, Big endian) + * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit) + * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit) + * - arm_cortexM4l_math.lib (Cortex-M4, Little endian) + * - arm_cortexM4b_math.lib (Cortex-M4, Big endian) + * - arm_cortexM3l_math.lib (Cortex-M3, Little endian) + * - arm_cortexM3b_math.lib (Cortex-M3, Big endian) + * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian) + * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian) + * - arm_ARMv8MBLl_math.lib (ARMv8M Baseline, Little endian) + * - arm_ARMv8MMLl_math.lib (ARMv8M Mainline, Little endian) + * - arm_ARMv8MMLlfsp_math.lib (ARMv8M Mainline, Little endian, Single Precision Floating Point Unit) + * - arm_ARMv8MMLld_math.lib (ARMv8M Mainline, Little endian, DSP instructions) + * - arm_ARMv8MMLldfsp_math.lib (ARMv8M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * For ARMv8M cores define pre processor MACRO ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML. + * Set Pre processor MACRO __DSP_PRESENT if ARMv8M Mainline core supports DSP instructions. + * + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library has been developed and tested with MDK-ARM version 5.14.0.0 + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * ------------ + * + * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM_math.uvprojx + * + * + * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. + * + * Pre-processor Macros + * ------------ + * + * Each library project have differant pre-processor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and + * ARM_MATH_CM7 for building the library on cortex-M7. + * + * - ARM_MATH_ARMV8MxL: + * + * Define macro ARM_MATH_ARMV8MBL for building the library on ARMv8M Baseline target, ARM_MATH_ARMV8MBL for building library + * on ARMv8M Mainline target. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries. + * + * - __DSP_PRESENT: + * + * Initialize macro __DSP_PRESENT = 1 when ARMv8M Mainline core supports DSP instructions. + * + *
+ * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | + * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | + * + *
+ * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + * + * Copyright Notice + * ------------ + * + * Copyright (C) 2010-2015 ARM Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +/* ignore some GCC warnings */ +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined(ARM_MATH_CM7) +#include "core_cm7.h" +#define ARM_MATH_DSP +#elif defined (ARM_MATH_CM4) +#include "core_cm4.h" +#define ARM_MATH_DSP +#elif defined (ARM_MATH_CM3) +#include "core_cm3.h" +#elif defined (ARM_MATH_CM0) +#include "core_cm0.h" +#define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_CM0PLUS) +#include "core_cm0plus.h" +#define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_ARMV8MBL) +#include "core_armv8mbl.h" +#define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_ARMV8MML) +#include "core_armv8mml.h" +#if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1)) +#define ARM_MATH_DSP +#endif +#else +#error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML" +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI +#define PI 3.14159265358979f +#endif + +/** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + +/** + * @brief Macros required for SINE and COSINE Controller functions + */ +/* 1.31(q31) Fixed value of 2/360 */ +/* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + +/** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE +#define ALIGN4 +#else +#if defined (__GNUC__) +#define ALIGN4 __attribute__((aligned(4))) +#else +#define ALIGN4 __align(4) +#endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + +/** + * @brief Error status returned by some functions in the library. + */ + +typedef enum { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ +} arm_status; + +/** + * @brief 8-bit fractional data type in 1.7 format. + */ +typedef int8_t q7_t; + +/** + * @brief 16-bit fractional data type in 1.15 format. + */ +typedef int16_t q15_t; + +/** + * @brief 32-bit fractional data type in 1.31 format. + */ +typedef int32_t q31_t; + +/** + * @brief 64-bit fractional data type in 1.63 format. + */ +typedef int64_t q63_t; + +/** + * @brief 32-bit floating-point type definition. + */ +typedef float float32_t; + +/** + * @brief 64-bit floating-point type definition. + */ +typedef double float64_t; + +/** + * @brief definition to read/write two 16 bit values. + */ +#if defined ( __CC_ARM ) +#define __SIMD32_TYPE int32_t __packed +#define CMSIS_UNUSED __attribute__((unused)) +#define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) +#define __SIMD32_TYPE int32_t +#define CMSIS_UNUSED __attribute__((unused)) +#define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __GNUC__ ) +#define __SIMD32_TYPE int32_t +#define CMSIS_UNUSED __attribute__((unused)) +#define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __ICCARM__ ) +#define __SIMD32_TYPE int32_t __packed +#define CMSIS_UNUSED +#define CMSIS_INLINE + +#elif defined ( __TI_ARM__ ) +#define __SIMD32_TYPE int32_t +#define CMSIS_UNUSED __attribute__((unused)) +#define CMSIS_INLINE + +#elif defined ( __CSMC__ ) +#define __SIMD32_TYPE int32_t +#define CMSIS_UNUSED +#define CMSIS_INLINE + +#elif defined ( __TASKING__ ) +#define __SIMD32_TYPE __unaligned int32_t +#define CMSIS_UNUSED +#define CMSIS_INLINE + +#else +#error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ +#if !defined (ARM_MATH_DSP) +/** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ +#endif /* !defined (ARM_MATH_DSP) */ + +/** +* @brief definition to pack four 8 bit values. +*/ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + +/** + * @brief Clips Q63 to Q31 values. + */ +CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31( + q63_t x) +{ + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; +} + +/** + * @brief Clips Q63 to Q15 values. + */ +CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15( + q63_t x) +{ + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); +} + +/** + * @brief Clips Q31 to Q7 values. + */ +CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7( + q31_t x) +{ + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; +} + +/** + * @brief Clips Q31 to Q15 values. + */ +CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15( + q31_t x) +{ + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; +} + +/** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + +CMSIS_INLINE __STATIC_INLINE q63_t mult32x64( + q63_t x, + q31_t y) +{ + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); +} + +/* + #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) + #define __CLZ __clz + #endif + */ +/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */ +#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ) +CMSIS_INLINE __STATIC_INLINE uint32_t __CLZ( + q31_t data); + +CMSIS_INLINE __STATIC_INLINE uint32_t __CLZ( + q31_t data) +{ + uint32_t count = 0; + uint32_t mask = 0x80000000; + + while ((data & mask) == 0) { + count += 1u; + mask = mask >> 1u; + } + + return (count); +} +#endif + +/** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + +CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t* dst, + q31_t* pRecipTable) +{ + q31_t out; + uint32_t tempVal; + uint32_t index, i; + uint32_t signBits; + + if (in > 0) { + signBits = ((uint32_t) (__CLZ( in) - 1)); + } + else { + signBits = ((uint32_t) (__CLZ(-in) - 1)); + } + + /* Convert input sample to 1.31 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 24); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) { + tempVal = (uint32_t) (((q63_t) in * out) >> 31); + tempVal = 0x7FFFFFFFu - tempVal; + /* 1.31 with exp 1 */ + /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ + out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1u); +} + + +/** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ +CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t* dst, + q15_t* pRecipTable) +{ + q15_t out = 0; + uint32_t tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if (in > 0) { + signBits = ((uint32_t)(__CLZ( in) - 17)); + } + else { + signBits = ((uint32_t)(__CLZ(-in) - 17)); + } + + /* Convert input sample to 1.15 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 8); + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) { + tempVal = (uint32_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFFu - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); +} + + +/* + * @brief C custom defined intrinisic function for only M0 processors + */ +#if defined(ARM_MATH_CM0_FAMILY) +CMSIS_INLINE __STATIC_INLINE q31_t __SSAT( + q31_t x, + uint32_t y) +{ + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + for (i = 0; i < (y - 1); i++) { + posMax = posMax * 2; + } + + if (x > 0) { + posMax = (posMax - 1); + + if (x > posMax) { + x = posMax; + } + } + else { + negMin = -posMax; + + if (x < negMin) { + x = negMin; + } + } + return (x); +} +#endif /* end of ARM_MATH_CM0_FAMILY */ + + +/* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ +#if !defined (ARM_MATH_DSP) + +/* + * @brief C custom defined QADD8 for M3 and M0 processors + */ +CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8( + uint32_t x, + uint32_t y) +{ + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); +} + + +/* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ +CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8( + uint32_t x, + uint32_t y) +{ + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); +} + + +/* + * @brief C custom defined QADD16 for M3 and M0 processors + */ +CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16( + uint32_t x, + uint32_t y) +{ + /* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ + q31_t r = 0, s = 0; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); +} + + +/* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ +CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16( + uint32_t x, + uint32_t y) +{ + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); +} + + +/* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ +CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16( + uint32_t x, + uint32_t y) +{ + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); +} + + +/* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ +CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16( + uint32_t x, + uint32_t y) +{ + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); +} + + +/* + * @brief C custom defined QASX for M3 and M0 processors + */ +CMSIS_INLINE __STATIC_INLINE uint32_t __QASX( + uint32_t x, + uint32_t y) +{ + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); +} + + +/* + * @brief C custom defined SHASX for M3 and M0 processors + */ +CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX( + uint32_t x, + uint32_t y) +{ + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); +} + + +/* + * @brief C custom defined QSAX for M3 and M0 processors + */ +CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX( + uint32_t x, + uint32_t y) +{ + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); +} + + +/* + * @brief C custom defined SHSAX for M3 and M0 processors + */ +CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX( + uint32_t x, + uint32_t y) +{ + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); +} + + +/* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ +CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX( + uint32_t x, + uint32_t y) +{ + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); +} + +/* + * @brief C custom defined SMUADX for M3 and M0 processors + */ +CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX( + uint32_t x, + uint32_t y) +{ + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); +} + + +/* + * @brief C custom defined QADD for M3 and M0 processors + */ +CMSIS_INLINE __STATIC_INLINE int32_t __QADD( + int32_t x, + int32_t y) +{ + return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); +} + + +/* + * @brief C custom defined QSUB for M3 and M0 processors + */ +CMSIS_INLINE __STATIC_INLINE int32_t __QSUB( + int32_t x, + int32_t y) +{ + return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); +} + + +/* + * @brief C custom defined SMLAD for M3 and M0 processors + */ +CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD( + uint32_t x, + uint32_t y, + uint32_t sum) +{ + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q31_t)sum ) ) )); +} + + +/* + * @brief C custom defined SMLADX for M3 and M0 processors + */ +CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX( + uint32_t x, + uint32_t y, + uint32_t sum) +{ + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); +} + + +/* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ +CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX( + uint32_t x, + uint32_t y, + uint32_t sum) +{ + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); +} + + +/* + * @brief C custom defined SMLALD for M3 and M0 processors + */ +CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD( + uint32_t x, + uint32_t y, + uint64_t sum) +{ + /* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q63_t)sum ) ) )); +} + + +/* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ +CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX( + uint32_t x, + uint32_t y, + uint64_t sum) +{ + /* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q63_t)sum ) ) )); +} + + +/* + * @brief C custom defined SMUAD for M3 and M0 processors + */ +CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD( + uint32_t x, + uint32_t y) +{ + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); +} + + +/* + * @brief C custom defined SMUSD for M3 and M0 processors + */ +CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD( + uint32_t x, + uint32_t y) +{ + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); +} + + +/* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ +CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16( + uint32_t x) +{ + return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | + ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); +} + +/* + * @brief C custom defined SMMLA for M3 and M0 processors + */ +CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA( + int32_t x, + int32_t y, + int32_t sum) +{ + return (sum + (int32_t) (((int64_t) x * y) >> 32)); +} + +#if 0 +/* + * @brief C custom defined PKHBT for unavailable DSP extension + */ +CMSIS_INLINE __STATIC_INLINE uint32_t __PKHBT( + uint32_t x, + uint32_t y, + uint32_t leftshift) +{ + return ( ((x ) & 0x0000FFFFUL) | + ((y << leftshift) & 0xFFFF0000UL) ); +} + +/* + * @brief C custom defined PKHTB for unavailable DSP extension + */ +CMSIS_INLINE __STATIC_INLINE uint32_t __PKHTB( + uint32_t x, + uint32_t y, + uint32_t rightshift) +{ + return ( ((x ) & 0xFFFF0000UL) | + ((y >> rightshift) & 0x0000FFFFUL) ); +} +#endif + +/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ +#endif /* !defined (ARM_MATH_DSP) */ + + +/** + * @brief Instance structure for the Q7 FIR filter. + */ +typedef struct { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ +} arm_fir_instance_q7; + +/** + * @brief Instance structure for the Q15 FIR filter. + */ +typedef struct { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ +} arm_fir_instance_q15; + +/** + * @brief Instance structure for the Q31 FIR filter. + */ +typedef struct { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ +} arm_fir_instance_q31; + +/** + * @brief Instance structure for the floating-point FIR filter. + */ +typedef struct { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ +} arm_fir_instance_f32; + + +/** + * @brief Processing function for the Q7 FIR filter. + * @param[in] S points to an instance of the Q7 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void arm_fir_q7( + const arm_fir_instance_q7* S, + q7_t* pSrc, + q7_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + */ +void arm_fir_init_q7( + arm_fir_instance_q7* S, + uint16_t numTaps, + q7_t* pCoeffs, + q7_t* pState, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q15 FIR filter. + * @param[in] S points to an instance of the Q15 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void arm_fir_q15( + const arm_fir_instance_q15* S, + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void arm_fir_fast_q15( + const arm_fir_instance_q15* S, + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ +arm_status arm_fir_init_q15( + arm_fir_instance_q15* S, + uint16_t numTaps, + q15_t* pCoeffs, + q15_t* pState, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q31 FIR filter. + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void arm_fir_q31( + const arm_fir_instance_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void arm_fir_fast_q31( + const arm_fir_instance_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ +void arm_fir_init_q31( + arm_fir_instance_q31* S, + uint16_t numTaps, + q31_t* pCoeffs, + q31_t* pState, + uint32_t blockSize); + + +/** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void arm_fir_f32( + const arm_fir_instance_f32* S, + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ +void arm_fir_init_f32( + arm_fir_instance_f32* S, + uint16_t numTaps, + float32_t* pCoeffs, + float32_t* pState, + uint32_t blockSize); + + +/** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ +typedef struct { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t* pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t* pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ +} arm_biquad_casd_df1_inst_q15; + +/** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ +typedef struct { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t* pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t* pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ +} arm_biquad_casd_df1_inst_q31; + +/** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ +typedef struct { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t* pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t* pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ +} arm_biquad_casd_df1_inst_f32; + + +/** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15* S, + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ +void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15* S, + uint8_t numStages, + q15_t* pCoeffs, + q15_t* pState, + int8_t postShift); + + +/** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15* S, + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ +void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31* S, + uint8_t numStages, + q31_t* pCoeffs, + q31_t* pState, + int8_t postShift); + + +/** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32* S, + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ +void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32* S, + uint8_t numStages, + float32_t* pCoeffs, + float32_t* pState); + + +/** + * @brief Instance structure for the floating-point matrix structure. + */ +typedef struct { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t* pData; /**< points to the data of the matrix. */ +} arm_matrix_instance_f32; + + +/** + * @brief Instance structure for the floating-point matrix structure. + */ +typedef struct { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t* pData; /**< points to the data of the matrix. */ +} arm_matrix_instance_f64; + +/** + * @brief Instance structure for the Q15 matrix structure. + */ +typedef struct { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t* pData; /**< points to the data of the matrix. */ +} arm_matrix_instance_q15; + +/** + * @brief Instance structure for the Q31 matrix structure. + */ +typedef struct { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t* pData; /**< points to the data of the matrix. */ +} arm_matrix_instance_q31; + + +/** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_add_f32( + const arm_matrix_instance_f32* pSrcA, + const arm_matrix_instance_f32* pSrcB, + arm_matrix_instance_f32* pDst); + + +/** + * @brief Q15 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_add_q15( + const arm_matrix_instance_q15* pSrcA, + const arm_matrix_instance_q15* pSrcB, + arm_matrix_instance_q15* pDst); + + +/** + * @brief Q31 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_add_q31( + const arm_matrix_instance_q31* pSrcA, + const arm_matrix_instance_q31* pSrcB, + arm_matrix_instance_q31* pDst); + + +/** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32* pSrcA, + const arm_matrix_instance_f32* pSrcB, + arm_matrix_instance_f32* pDst); + + +/** + * @brief Q15, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15* pSrcA, + const arm_matrix_instance_q15* pSrcB, + arm_matrix_instance_q15* pDst, + q15_t* pScratch); + + +/** + * @brief Q31, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31* pSrcA, + const arm_matrix_instance_q31* pSrcB, + arm_matrix_instance_q31* pDst); + + +/** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32* pSrc, + arm_matrix_instance_f32* pDst); + + +/** + * @brief Q15 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15* pSrc, + arm_matrix_instance_q15* pDst); + + +/** + * @brief Q31 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31* pSrc, + arm_matrix_instance_q31* pDst); + + +/** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32* pSrcA, + const arm_matrix_instance_f32* pSrcB, + arm_matrix_instance_f32* pDst); + + +/** + * @brief Q15 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15* pSrcA, + const arm_matrix_instance_q15* pSrcB, + arm_matrix_instance_q15* pDst, + q15_t* pState); + + +/** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15* pSrcA, + const arm_matrix_instance_q15* pSrcB, + arm_matrix_instance_q15* pDst, + q15_t* pState); + + +/** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31* pSrcA, + const arm_matrix_instance_q31* pSrcB, + arm_matrix_instance_q31* pDst); + + +/** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31* pSrcA, + const arm_matrix_instance_q31* pSrcB, + arm_matrix_instance_q31* pDst); + + +/** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32* pSrcA, + const arm_matrix_instance_f32* pSrcB, + arm_matrix_instance_f32* pDst); + + +/** + * @brief Q15 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15* pSrcA, + const arm_matrix_instance_q15* pSrcB, + arm_matrix_instance_q15* pDst); + + +/** + * @brief Q31 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31* pSrcA, + const arm_matrix_instance_q31* pSrcB, + arm_matrix_instance_q31* pDst); + + +/** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32* pSrc, + float32_t scale, + arm_matrix_instance_f32* pDst); + + +/** + * @brief Q15 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15* pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15* pDst); + + +/** + * @brief Q31 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31* pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31* pDst); + + +/** + * @brief Q31 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void arm_mat_init_q31( + arm_matrix_instance_q31* S, + uint16_t nRows, + uint16_t nColumns, + q31_t* pData); + + +/** + * @brief Q15 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void arm_mat_init_q15( + arm_matrix_instance_q15* S, + uint16_t nRows, + uint16_t nColumns, + q15_t* pData); + + +/** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void arm_mat_init_f32( + arm_matrix_instance_f32* S, + uint16_t nRows, + uint16_t nColumns, + float32_t* pData); + + + +/** + * @brief Instance structure for the Q15 PID Control. + */ +typedef struct { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#if !defined (ARM_MATH_DSP) + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ +} arm_pid_instance_q15; + +/** + * @brief Instance structure for the Q31 PID Control. + */ +typedef struct { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ +} arm_pid_instance_q31; + +/** + * @brief Instance structure for the floating-point PID Control. + */ +typedef struct { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ +} arm_pid_instance_f32; + + + +/** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ +void arm_pid_init_f32( + arm_pid_instance_f32* S, + int32_t resetStateFlag); + + +/** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + */ +void arm_pid_reset_f32( + arm_pid_instance_f32* S); + + +/** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ +void arm_pid_init_q31( + arm_pid_instance_q31* S, + int32_t resetStateFlag); + + +/** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + */ + +void arm_pid_reset_q31( + arm_pid_instance_q31* S); + + +/** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ +void arm_pid_init_q15( + arm_pid_instance_q15* S, + int32_t resetStateFlag); + + +/** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] S points to an instance of the q15 PID Control structure + */ +void arm_pid_reset_q15( + arm_pid_instance_q15* S); + + +/** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ +typedef struct { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t* pYData; /**< pointer to the table of Y values */ +} arm_linear_interp_instance_f32; + +/** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ +typedef struct { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t* pData; /**< points to the data table. */ +} arm_bilinear_interp_instance_f32; + +/** +* @brief Instance structure for the Q31 bilinear interpolation function. +*/ +typedef struct { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t* pData; /**< points to the data table. */ +} arm_bilinear_interp_instance_q31; + +/** +* @brief Instance structure for the Q15 bilinear interpolation function. +*/ +typedef struct { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t* pData; /**< points to the data table. */ +} arm_bilinear_interp_instance_q15; + +/** +* @brief Instance structure for the Q15 bilinear interpolation function. +*/ +typedef struct { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t* pData; /**< points to the data table. */ +} arm_bilinear_interp_instance_q7; + + +/** + * @brief Q7 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void arm_mult_q7( + q7_t* pSrcA, + q7_t* pSrcB, + q7_t* pDst, + uint32_t blockSize); + + +/** + * @brief Q15 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void arm_mult_q15( + q15_t* pSrcA, + q15_t* pSrcB, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Q31 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void arm_mult_q31( + q31_t* pSrcA, + q31_t* pSrcB, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void arm_mult_f32( + float32_t* pSrcA, + float32_t* pSrcB, + float32_t* pDst, + uint32_t blockSize); + + +/** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t* pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t* pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ +} arm_cfft_radix2_instance_q15; + +/* Deprecated */ +arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15* S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ +void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15* S, + q15_t* pSrc); + + +/** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t* pTwiddle; /**< points to the twiddle factor table. */ + uint16_t* pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ +} arm_cfft_radix4_instance_q15; + +/* Deprecated */ +arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15* S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ +void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15* S, + q15_t* pSrc); + +/** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t* pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t* pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ +} arm_cfft_radix2_instance_q31; + +/* Deprecated */ +arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31* S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ +void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31* S, + q31_t* pSrc); + +/** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t* pTwiddle; /**< points to the twiddle factor table. */ + uint16_t* pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ +} arm_cfft_radix4_instance_q31; + +/* Deprecated */ +void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31* S, + q31_t* pSrc); + +/* Deprecated */ +arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31* S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t* pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t* pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ +} arm_cfft_radix2_instance_f32; + +/* Deprecated */ +arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32* S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ +void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32* S, + float32_t* pSrc); + +/** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t* pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t* pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ +} arm_cfft_radix4_instance_f32; + +/* Deprecated */ +arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32* S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ +void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32* S, + float32_t* pSrc); + +/** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t* pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t* pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ +} arm_cfft_instance_q15; + +void arm_cfft_q15( + const arm_cfft_instance_q15* S, + q15_t* p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t* pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t* pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ +} arm_cfft_instance_q31; + +void arm_cfft_q31( + const arm_cfft_instance_q31* S, + q31_t* p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t* pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t* pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ +} arm_cfft_instance_f32; + +void arm_cfft_f32( + const arm_cfft_instance_f32* S, + float32_t* p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ +typedef struct { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t* pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t* pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q15* pCfft; /**< points to the complex FFT instance. */ +} arm_rfft_instance_q15; + +arm_status arm_rfft_init_q15( + arm_rfft_instance_q15* S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + +void arm_rfft_q15( + const arm_rfft_instance_q15* S, + q15_t* pSrc, + q15_t* pDst); + +/** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ +typedef struct { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t* pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t* pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q31* pCfft; /**< points to the complex FFT instance. */ +} arm_rfft_instance_q31; + +arm_status arm_rfft_init_q31( + arm_rfft_instance_q31* S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + +void arm_rfft_q31( + const arm_rfft_instance_q31* S, + q31_t* pSrc, + q31_t* pDst); + +/** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t* pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t* pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32* pCfft; /**< points to the complex FFT instance. */ +} arm_rfft_instance_f32; + +arm_status arm_rfft_init_f32( + arm_rfft_instance_f32* S, + arm_cfft_radix4_instance_f32* S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + +void arm_rfft_f32( + const arm_rfft_instance_f32* S, + float32_t* pSrc, + float32_t* pDst); + +/** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t* pTwiddleRFFT; /**< Twiddle factors real stage */ +} arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32* S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32* S, + float32_t* p, float32_t* pOut, + uint8_t ifftFlag); + +/** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ +typedef struct { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t* pTwiddle; /**< points to the twiddle factor table. */ + float32_t* pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32* pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32* pCfft; /**< points to the complex FFT instance. */ +} arm_dct4_instance_f32; + + +/** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ +arm_status arm_dct4_init_f32( + arm_dct4_instance_f32* S, + arm_rfft_instance_f32* S_RFFT, + arm_cfft_radix4_instance_f32* S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + +/** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ +void arm_dct4_f32( + const arm_dct4_instance_f32* S, + float32_t* pState, + float32_t* pInlineBuffer); + + +/** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ +typedef struct { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t* pTwiddle; /**< points to the twiddle factor table. */ + q31_t* pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31* pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31* pCfft; /**< points to the complex FFT instance. */ +} arm_dct4_instance_q31; + + +/** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ +arm_status arm_dct4_init_q31( + arm_dct4_instance_q31* S, + arm_rfft_instance_q31* S_RFFT, + arm_cfft_radix4_instance_q31* S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + +/** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] S points to an instance of the Q31 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ +void arm_dct4_q31( + const arm_dct4_instance_q31* S, + q31_t* pState, + q31_t* pInlineBuffer); + + +/** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ +typedef struct { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t* pTwiddle; /**< points to the twiddle factor table. */ + q15_t* pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15* pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15* pCfft; /**< points to the complex FFT instance. */ +} arm_dct4_instance_q15; + + +/** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ +arm_status arm_dct4_init_q15( + arm_dct4_instance_q15* S, + arm_rfft_instance_q15* S_RFFT, + arm_cfft_radix4_instance_q15* S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + +/** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] S points to an instance of the Q15 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ +void arm_dct4_q15( + const arm_dct4_instance_q15* S, + q15_t* pState, + q15_t* pInlineBuffer); + + +/** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void arm_add_f32( + float32_t* pSrcA, + float32_t* pSrcB, + float32_t* pDst, + uint32_t blockSize); + + +/** + * @brief Q7 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void arm_add_q7( + q7_t* pSrcA, + q7_t* pSrcB, + q7_t* pDst, + uint32_t blockSize); + + +/** + * @brief Q15 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void arm_add_q15( + q15_t* pSrcA, + q15_t* pSrcB, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Q31 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void arm_add_q31( + q31_t* pSrcA, + q31_t* pSrcB, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void arm_sub_f32( + float32_t* pSrcA, + float32_t* pSrcB, + float32_t* pDst, + uint32_t blockSize); + + +/** + * @brief Q7 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void arm_sub_q7( + q7_t* pSrcA, + q7_t* pSrcB, + q7_t* pDst, + uint32_t blockSize); + + +/** + * @brief Q15 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void arm_sub_q15( + q15_t* pSrcA, + q15_t* pSrcB, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Q31 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void arm_sub_q31( + q31_t* pSrcA, + q31_t* pSrcB, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_scale_f32( + float32_t* pSrc, + float32_t scale, + float32_t* pDst, + uint32_t blockSize); + + +/** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_scale_q7( + q7_t* pSrc, + q7_t scaleFract, + int8_t shift, + q7_t* pDst, + uint32_t blockSize); + + +/** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_scale_q15( + q15_t* pSrc, + q15_t scaleFract, + int8_t shift, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_scale_q31( + q31_t* pSrc, + q31_t scaleFract, + int8_t shift, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @brief Q7 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ +void arm_abs_q7( + q7_t* pSrc, + q7_t* pDst, + uint32_t blockSize); + + +/** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ +void arm_abs_f32( + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + + +/** + * @brief Q15 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ +void arm_abs_q15( + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Q31 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ +void arm_abs_q31( + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ +void arm_dot_prod_f32( + float32_t* pSrcA, + float32_t* pSrcB, + uint32_t blockSize, + float32_t* result); + + +/** + * @brief Dot product of Q7 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ +void arm_dot_prod_q7( + q7_t* pSrcA, + q7_t* pSrcB, + uint32_t blockSize, + q31_t* result); + + +/** + * @brief Dot product of Q15 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ +void arm_dot_prod_q15( + q15_t* pSrcA, + q15_t* pSrcB, + uint32_t blockSize, + q63_t* result); + + +/** + * @brief Dot product of Q31 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ +void arm_dot_prod_q31( + q31_t* pSrcA, + q31_t* pSrcB, + uint32_t blockSize, + q63_t* result); + + +/** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_shift_q7( + q7_t* pSrc, + int8_t shiftBits, + q7_t* pDst, + uint32_t blockSize); + + +/** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_shift_q15( + q15_t* pSrc, + int8_t shiftBits, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_shift_q31( + q31_t* pSrc, + int8_t shiftBits, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_offset_f32( + float32_t* pSrc, + float32_t offset, + float32_t* pDst, + uint32_t blockSize); + + +/** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_offset_q7( + q7_t* pSrc, + q7_t offset, + q7_t* pDst, + uint32_t blockSize); + + +/** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_offset_q15( + q15_t* pSrc, + q15_t offset, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_offset_q31( + q31_t* pSrc, + q31_t offset, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_negate_f32( + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + + +/** + * @brief Negates the elements of a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_negate_q7( + q7_t* pSrc, + q7_t* pDst, + uint32_t blockSize); + + +/** + * @brief Negates the elements of a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_negate_q15( + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Negates the elements of a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_negate_q31( + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void arm_copy_f32( + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + + +/** + * @brief Copies the elements of a Q7 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void arm_copy_q7( + q7_t* pSrc, + q7_t* pDst, + uint32_t blockSize); + + +/** + * @brief Copies the elements of a Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void arm_copy_q15( + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Copies the elements of a Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void arm_copy_q31( + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void arm_fill_f32( + float32_t value, + float32_t* pDst, + uint32_t blockSize); + + +/** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void arm_fill_q7( + q7_t value, + q7_t* pDst, + uint32_t blockSize); + + +/** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void arm_fill_q15( + q15_t value, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void arm_fill_q31( + q31_t value, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @brief Convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ +void arm_conv_f32( + float32_t* pSrcA, + uint32_t srcALen, + float32_t* pSrcB, + uint32_t srcBLen, + float32_t* pDst); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ +void arm_conv_opt_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst, + q15_t* pScratch1, + q15_t* pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ +void arm_conv_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst); + + +/** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ +void arm_conv_fast_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst); + + +/** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ +void arm_conv_fast_opt_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst, + q15_t* pScratch1, + q15_t* pScratch2); + + +/** + * @brief Convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ +void arm_conv_q31( + q31_t* pSrcA, + uint32_t srcALen, + q31_t* pSrcB, + uint32_t srcBLen, + q31_t* pDst); + + +/** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ +void arm_conv_fast_q31( + q31_t* pSrcA, + uint32_t srcALen, + q31_t* pSrcB, + uint32_t srcBLen, + q31_t* pDst); + + +/** +* @brief Convolution of Q7 sequences. +* @param[in] pSrcA points to the first input sequence. +* @param[in] srcALen length of the first input sequence. +* @param[in] pSrcB points to the second input sequence. +* @param[in] srcBLen length of the second input sequence. +* @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. +* @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. +* @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). +*/ +void arm_conv_opt_q7( + q7_t* pSrcA, + uint32_t srcALen, + q7_t* pSrcB, + uint32_t srcBLen, + q7_t* pDst, + q15_t* pScratch1, + q15_t* pScratch2); + + +/** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ +void arm_conv_q7( + q7_t* pSrcA, + uint32_t srcALen, + q7_t* pSrcB, + uint32_t srcBLen, + q7_t* pDst); + + +/** + * @brief Partial convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ +arm_status arm_conv_partial_f32( + float32_t* pSrcA, + uint32_t srcALen, + float32_t* pSrcB, + uint32_t srcBLen, + float32_t* pDst, + uint32_t firstIndex, + uint32_t numPoints); + + +/** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ +arm_status arm_conv_partial_opt_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t* pScratch1, + q15_t* pScratch2); + + +/** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ +arm_status arm_conv_partial_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst, + uint32_t firstIndex, + uint32_t numPoints); + + +/** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ +arm_status arm_conv_partial_fast_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst, + uint32_t firstIndex, + uint32_t numPoints); + + +/** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ +arm_status arm_conv_partial_fast_opt_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t* pScratch1, + q15_t* pScratch2); + + +/** + * @brief Partial convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ +arm_status arm_conv_partial_q31( + q31_t* pSrcA, + uint32_t srcALen, + q31_t* pSrcB, + uint32_t srcBLen, + q31_t* pDst, + uint32_t firstIndex, + uint32_t numPoints); + + +/** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ +arm_status arm_conv_partial_fast_q31( + q31_t* pSrcA, + uint32_t srcALen, + q31_t* pSrcB, + uint32_t srcBLen, + q31_t* pDst, + uint32_t firstIndex, + uint32_t numPoints); + + +/** + * @brief Partial convolution of Q7 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ +arm_status arm_conv_partial_opt_q7( + q7_t* pSrcA, + uint32_t srcALen, + q7_t* pSrcB, + uint32_t srcBLen, + q7_t* pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t* pScratch1, + q15_t* pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ +arm_status arm_conv_partial_q7( + q7_t* pSrcA, + uint32_t srcALen, + q7_t* pSrcB, + uint32_t srcBLen, + q7_t* pDst, + uint32_t firstIndex, + uint32_t numPoints); + + +/** + * @brief Instance structure for the Q15 FIR decimator. + */ +typedef struct { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ +} arm_fir_decimate_instance_q15; + +/** + * @brief Instance structure for the Q31 FIR decimator. + */ +typedef struct { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ +} arm_fir_decimate_instance_q31; + +/** + * @brief Instance structure for the floating-point FIR decimator. + */ +typedef struct { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ +} arm_fir_decimate_instance_f32; + + +/** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] S points to an instance of the floating-point FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ +void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32* S, + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ +arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32* S, + uint16_t numTaps, + uint8_t M, + float32_t* pCoeffs, + float32_t* pState, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ +void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15* S, + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ +void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15* S, + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ +arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15* S, + uint16_t numTaps, + uint8_t M, + q15_t* pCoeffs, + q15_t* pState, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ +void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + +/** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ +void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ +arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31* S, + uint16_t numTaps, + uint8_t M, + q31_t* pCoeffs, + q31_t* pState, + uint32_t blockSize); + + +/** + * @brief Instance structure for the Q15 FIR interpolator. + */ +typedef struct { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t* pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t* pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ +} arm_fir_interpolate_instance_q15; + +/** + * @brief Instance structure for the Q31 FIR interpolator. + */ +typedef struct { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t* pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t* pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ +} arm_fir_interpolate_instance_q31; + +/** + * @brief Instance structure for the floating-point FIR interpolator. + */ +typedef struct { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t* pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t* pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ +} arm_fir_interpolate_instance_f32; + + +/** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ +void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15* S, + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ +arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15* S, + uint8_t L, + uint16_t numTaps, + q15_t* pCoeffs, + q15_t* pState, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ +void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ +arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31* S, + uint8_t L, + uint16_t numTaps, + q31_t* pCoeffs, + q31_t* pState, + uint32_t blockSize); + + +/** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ +void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32* S, + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ +arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32* S, + uint8_t L, + uint16_t numTaps, + float32_t* pCoeffs, + float32_t* pState, + uint32_t blockSize); + + +/** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ +typedef struct { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t* pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t* pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ +} arm_biquad_cas_df1_32x64_ins_q31; + + +/** + * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ +void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + */ +void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31* S, + uint8_t numStages, + q31_t* pCoeffs, + q63_t* pState, + uint8_t postShift); + + +/** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ +typedef struct { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t* pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t* pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ +} arm_biquad_cascade_df2T_instance_f32; + +/** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ +typedef struct { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t* pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t* pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ +} arm_biquad_cascade_stereo_df2T_instance_f32; + +/** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ +typedef struct { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t* pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t* pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ +} arm_biquad_cascade_df2T_instance_f64; + + +/** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ +void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32* S, + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + + +/** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ +void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32* S, + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + + +/** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ +void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64* S, + float64_t* pSrc, + float64_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ +void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32* S, + uint8_t numStages, + float32_t* pCoeffs, + float32_t* pState); + + +/** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ +void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32* S, + uint8_t numStages, + float32_t* pCoeffs, + float32_t* pState); + + +/** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ +void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64* S, + uint8_t numStages, + float64_t* pCoeffs, + float64_t* pState); + + +/** + * @brief Instance structure for the Q15 FIR lattice filter. + */ +typedef struct { + uint16_t numStages; /**< number of filter stages. */ + q15_t* pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ +} arm_fir_lattice_instance_q15; + +/** + * @brief Instance structure for the Q31 FIR lattice filter. + */ +typedef struct { + uint16_t numStages; /**< number of filter stages. */ + q31_t* pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ +} arm_fir_lattice_instance_q31; + +/** + * @brief Instance structure for the floating-point FIR lattice filter. + */ +typedef struct { + uint16_t numStages; /**< number of filter stages. */ + float32_t* pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ +} arm_fir_lattice_instance_f32; + + +/** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ +void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15* S, + uint16_t numStages, + q15_t* pCoeffs, + q15_t* pState); + + +/** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15* S, + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ +void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31* S, + uint16_t numStages, + q31_t* pCoeffs, + q31_t* pState); + + +/** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ +void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ +void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32* S, + uint16_t numStages, + float32_t* pCoeffs, + float32_t* pState); + + +/** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ +void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32* S, + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + + +/** + * @brief Instance structure for the Q15 IIR lattice filter. + */ +typedef struct { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t* pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t* pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t* pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ +} arm_iir_lattice_instance_q15; + +/** + * @brief Instance structure for the Q31 IIR lattice filter. + */ +typedef struct { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t* pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t* pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t* pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ +} arm_iir_lattice_instance_q31; + +/** + * @brief Instance structure for the floating-point IIR lattice filter. + */ +typedef struct { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t* pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t* pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t* pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ +} arm_iir_lattice_instance_f32; + + +/** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32* S, + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + */ +void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32* S, + uint16_t numStages, + float32_t* pkCoeffs, + float32_t* pvCoeffs, + float32_t* pState, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + */ +void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31* S, + uint16_t numStages, + q31_t* pkCoeffs, + q31_t* pvCoeffs, + q31_t* pState, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the Q15 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15* S, + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + */ +void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15* S, + uint16_t numStages, + q15_t* pkCoeffs, + q15_t* pvCoeffs, + q15_t* pState, + uint32_t blockSize); + + +/** + * @brief Instance structure for the floating-point LMS filter. + */ +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ +} arm_lms_instance_f32; + + +/** + * @brief Processing function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ +void arm_lms_f32( + const arm_lms_instance_f32* S, + float32_t* pSrc, + float32_t* pRef, + float32_t* pOut, + float32_t* pErr, + uint32_t blockSize); + + +/** + * @brief Initialization function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ +void arm_lms_init_f32( + arm_lms_instance_f32* S, + uint16_t numTaps, + float32_t* pCoeffs, + float32_t* pState, + float32_t mu, + uint32_t blockSize); + + +/** + * @brief Instance structure for the Q15 LMS filter. + */ +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ +} arm_lms_instance_q15; + + +/** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ +void arm_lms_init_q15( + arm_lms_instance_q15* S, + uint16_t numTaps, + q15_t* pCoeffs, + q15_t* pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + +/** + * @brief Processing function for Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ +void arm_lms_q15( + const arm_lms_instance_q15* S, + q15_t* pSrc, + q15_t* pRef, + q15_t* pOut, + q15_t* pErr, + uint32_t blockSize); + + +/** + * @brief Instance structure for the Q31 LMS filter. + */ +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ +} arm_lms_instance_q31; + + +/** + * @brief Processing function for Q31 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ +void arm_lms_q31( + const arm_lms_instance_q31* S, + q31_t* pSrc, + q31_t* pRef, + q31_t* pOut, + q31_t* pErr, + uint32_t blockSize); + + +/** + * @brief Initialization function for Q31 LMS filter. + * @param[in] S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ +void arm_lms_init_q31( + arm_lms_instance_q31* S, + uint16_t numTaps, + q31_t* pCoeffs, + q31_t* pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + +/** + * @brief Instance structure for the floating-point normalized LMS filter. + */ +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ +} arm_lms_norm_instance_f32; + + +/** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ +void arm_lms_norm_f32( + arm_lms_norm_instance_f32* S, + float32_t* pSrc, + float32_t* pRef, + float32_t* pOut, + float32_t* pErr, + uint32_t blockSize); + + +/** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ +void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32* S, + uint16_t numTaps, + float32_t* pCoeffs, + float32_t* pState, + float32_t mu, + uint32_t blockSize); + + +/** + * @brief Instance structure for the Q31 normalized LMS filter. + */ +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t* recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ +} arm_lms_norm_instance_q31; + + +/** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ +void arm_lms_norm_q31( + arm_lms_norm_instance_q31* S, + q31_t* pSrc, + q31_t* pRef, + q31_t* pOut, + q31_t* pErr, + uint32_t blockSize); + + +/** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ +void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31* S, + uint16_t numTaps, + q31_t* pCoeffs, + q31_t* pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + +/** + * @brief Instance structure for the Q15 normalized LMS filter. + */ +typedef struct { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t* recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ +} arm_lms_norm_instance_q15; + + +/** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ +void arm_lms_norm_q15( + arm_lms_norm_instance_q15* S, + q15_t* pSrc, + q15_t* pRef, + q15_t* pOut, + q15_t* pErr, + uint32_t blockSize); + + +/** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ +void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15* S, + uint16_t numTaps, + q15_t* pCoeffs, + q15_t* pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + +/** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ +void arm_correlate_f32( + float32_t* pSrcA, + uint32_t srcALen, + float32_t* pSrcB, + uint32_t srcBLen, + float32_t* pDst); + + +/** +* @brief Correlation of Q15 sequences +* @param[in] pSrcA points to the first input sequence. +* @param[in] srcALen length of the first input sequence. +* @param[in] pSrcB points to the second input sequence. +* @param[in] srcBLen length of the second input sequence. +* @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. +* @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. +*/ +void arm_correlate_opt_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst, + q15_t* pScratch); + + +/** + * @brief Correlation of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + +void arm_correlate_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst); + + +/** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + +void arm_correlate_fast_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst); + + +/** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ +void arm_correlate_fast_opt_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst, + q15_t* pScratch); + + +/** + * @brief Correlation of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ +void arm_correlate_q31( + q31_t* pSrcA, + uint32_t srcALen, + q31_t* pSrcB, + uint32_t srcBLen, + q31_t* pDst); + + +/** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ +void arm_correlate_fast_q31( + q31_t* pSrcA, + uint32_t srcALen, + q31_t* pSrcB, + uint32_t srcBLen, + q31_t* pDst); + + +/** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ +void arm_correlate_opt_q7( + q7_t* pSrcA, + uint32_t srcALen, + q7_t* pSrcB, + uint32_t srcBLen, + q7_t* pDst, + q15_t* pScratch1, + q15_t* pScratch2); + + +/** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ +void arm_correlate_q7( + q7_t* pSrcA, + uint32_t srcALen, + q7_t* pSrcB, + uint32_t srcBLen, + q7_t* pDst); + + +/** + * @brief Instance structure for the floating-point sparse FIR filter. + */ +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t* pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t* pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ +} arm_fir_sparse_instance_f32; + +/** + * @brief Instance structure for the Q31 sparse FIR filter. + */ +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t* pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t* pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ +} arm_fir_sparse_instance_q31; + +/** + * @brief Instance structure for the Q15 sparse FIR filter. + */ +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t* pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t* pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ +} arm_fir_sparse_instance_q15; + +/** + * @brief Instance structure for the Q7 sparse FIR filter. + */ +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t* pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t* pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ +} arm_fir_sparse_instance_q7; + + +/** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] S points to an instance of the floating-point sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ +void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32* S, + float32_t* pSrc, + float32_t* pDst, + float32_t* pScratchIn, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ +void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32* S, + uint16_t numTaps, + float32_t* pCoeffs, + float32_t* pState, + int32_t* pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] S points to an instance of the Q31 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ +void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31* S, + q31_t* pSrc, + q31_t* pDst, + q31_t* pScratchIn, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ +void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31* S, + uint16_t numTaps, + q31_t* pCoeffs, + q31_t* pState, + int32_t* pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] S points to an instance of the Q15 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ +void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15* S, + q15_t* pSrc, + q15_t* pDst, + q15_t* pScratchIn, + q31_t* pScratchOut, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ +void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15* S, + uint16_t numTaps, + q15_t* pCoeffs, + q15_t* pState, + int32_t* pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] S points to an instance of the Q7 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ +void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7* S, + q7_t* pSrc, + q7_t* pDst, + q7_t* pScratchIn, + q31_t* pScratchOut, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ +void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7* S, + uint16_t numTaps, + q7_t* pCoeffs, + q7_t* pState, + int32_t* pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + +/** + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cos output. + */ +void arm_sin_cos_f32( + float32_t theta, + float32_t* pSinVal, + float32_t* pCosVal); + + +/** + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cosine output. + */ +void arm_sin_cos_q31( + q31_t theta, + q31_t* pSinVal, + q31_t* pCosVal); + + +/** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ +void arm_cmplx_conj_f32( + float32_t* pSrc, + float32_t* pDst, + uint32_t numSamples); + +/** + * @brief Q31 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ +void arm_cmplx_conj_q31( + q31_t* pSrc, + q31_t* pDst, + uint32_t numSamples); + + +/** + * @brief Q15 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ +void arm_cmplx_conj_q15( + q15_t* pSrc, + q15_t* pDst, + uint32_t numSamples); + + +/** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ +void arm_cmplx_mag_squared_f32( + float32_t* pSrc, + float32_t* pDst, + uint32_t numSamples); + + +/** + * @brief Q31 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ +void arm_cmplx_mag_squared_q31( + q31_t* pSrc, + q31_t* pDst, + uint32_t numSamples); + + +/** + * @brief Q15 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ +void arm_cmplx_mag_squared_q15( + q15_t* pSrc, + q15_t* pDst, + uint32_t numSamples); + + +/** + * @ingroup groupController + */ + +/** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+ *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+ *    A0 = Kp + Ki + Kd
+ *    A1 = (-Kp ) - (2 * Kd )
+ *    A2 = Kd
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + +/** + * @addtogroup PID + * @{ + */ + +/** + * @brief Process function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ +CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32( + arm_pid_instance_f32* S, + float32_t in) +{ + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + +} + +/** + * @brief Process function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ +CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31( + arm_pid_instance_q31* S, + q31_t in) +{ + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31u); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); +} + + +/** + * @brief Process function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ +CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15( + arm_pid_instance_q15* S, + q15_t in) +{ + q63_t acc; + q15_t out; + +#if defined (ARM_MATH_DSP) + __SIMD32_TYPE* vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t) * vstate, (uint64_t)acc); +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); +} + +/** + * @} end of PID group + */ + + +/** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ +arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32* src, + arm_matrix_instance_f32* dst); + + +/** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ +arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64* src, + arm_matrix_instance_f64* dst); + + + +/** + * @ingroup groupController + */ + +/** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + +/** + * @addtogroup clarke + * @{ + */ + +/** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + */ +CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t* pIalpha, + float32_t* pIbeta) +{ + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); +} + + +/** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ +CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t* pIalpha, + q31_t* pIbeta) +{ + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); +} + +/** + * @} end of clarke group + */ + +/** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void arm_q7_to_q31( + q7_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + + + +/** + * @ingroup groupController + */ + +/** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + +/** + * @addtogroup inv_clarke + * @{ + */ + +/** +* @brief Floating-point Inverse Clarke transform +* @param[in] Ialpha input two-phase orthogonal vector axis alpha +* @param[in] Ibeta input two-phase orthogonal vector axis beta +* @param[out] pIa points to output three-phase coordinate a +* @param[out] pIb points to output three-phase coordinate b +*/ +CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t* pIa, + float32_t* pIb) +{ + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; +} + + +/** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ +CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t* pIa, + q31_t* pIb) +{ + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); +} + +/** + * @} end of inv_clarke group + */ + +/** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void arm_q7_to_q15( + q7_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + + + +/** + * @ingroup groupController + */ + +/** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + +/** + * @addtogroup park + * @{ + */ + +/** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * The function implements the forward Park transform. + * + */ +CMSIS_INLINE __STATIC_INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t* pId, + float32_t* pIq, + float32_t sinVal, + float32_t cosVal) +{ + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; +} + + +/** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ +CMSIS_INLINE __STATIC_INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t* pId, + q31_t* pIq, + q31_t sinVal, + q31_t cosVal) +{ + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); +} + +/** + * @} end of park group + */ + +/** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ +void arm_q7_to_float( + q7_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + + +/** + * @ingroup groupController + */ + +/** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + +/** + * @addtogroup inv_park + * @{ + */ + +/** +* @brief Floating-point Inverse Park transform +* @param[in] Id input coordinate of rotor reference frame d +* @param[in] Iq input coordinate of rotor reference frame q +* @param[out] pIalpha points to output two-phase orthogonal vector axis alpha +* @param[out] pIbeta points to output two-phase orthogonal vector axis beta +* @param[in] sinVal sine value of rotation angle theta +* @param[in] cosVal cosine value of rotation angle theta +*/ +CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t* pIalpha, + float32_t* pIbeta, + float32_t sinVal, + float32_t cosVal) +{ + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; +} + + +/** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ +CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t* pIalpha, + q31_t* pIbeta, + q31_t sinVal, + q31_t cosVal) +{ + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); +} + +/** + * @} end of Inverse park group + */ + + +/** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ +void arm_q31_to_float( + q31_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + +/** + * @ingroup groupInterpolation + */ + +/** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+ *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+ *       where x0, x1 are nearest values of input x
+ *             y0, y1 are nearest values to output y
+ *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + +/** + * @addtogroup LinearInterpolate + * @{ + */ + +/** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ +CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32* S, + float32_t x) +{ + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t* pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if (i < 0) { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if ((uint32_t)i >= S->nValues) { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); +} + + +/** +* +* @brief Process function for the Q31 Linear Interpolation Function. +* @param[in] pYData pointer to Q31 Linear Interpolation table +* @param[in] x input sample to process +* @param[in] nValues number of table values +* @return y processed output sample. +* +* \par +* Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. +* This function can support maximum of table size 2^12. +* +*/ +CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31( + q31_t* pYData, + q31_t x, + uint32_t nValues) +{ + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (q31_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) { + return (pYData[nValues - 1]); + } + else if (index < 0) { + return (pYData[0]); + } + else { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1u); + } +} + + +/** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ +CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15( + q15_t* pYData, + q31_t x, + uint32_t nValues) +{ + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (int32_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) { + return (pYData[nValues - 1]); + } + else if (index < 0) { + return (pYData[0]); + } + else { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (q15_t) (y >> 20); + } +} + + +/** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ +CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7( + q7_t* pYData, + q31_t x, + uint32_t nValues) +{ + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + if (index >= (nValues - 1)) { + return (pYData[nValues - 1]); + } + else { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (q7_t) (y >> 20); + } +} + +/** + * @} end of LinearInterpolate group + */ + +/** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ +float32_t arm_sin_f32( + float32_t x); + + +/** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ +q31_t arm_sin_q31( + q31_t x); + + +/** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ +q15_t arm_sin_q15( + q15_t x); + + +/** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ +float32_t arm_cos_f32( + float32_t x); + + +/** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ +q31_t arm_cos_q31( + q31_t x); + + +/** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ +q15_t arm_cos_q15( + q15_t x); + + +/** + * @ingroup groupFastMath + */ + + +/** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+ *      x1 = x0 - f(x0)/f'(x0)
+ *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+ *     x0 = in/2                         [initial guess]
+ *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+ *
+ */ + + +/** + * @addtogroup SQRT + * @{ + */ + +/** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ +CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t* pOut) +{ + if (in >= 0.0f) { + +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined(__GNUC__) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) + __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } +} + + +/** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ +arm_status arm_sqrt_q31( + q31_t in, + q31_t* pOut); + + +/** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ +arm_status arm_sqrt_q15( + q15_t in, + q15_t* pOut); + +/** + * @} end of SQRT group + */ + + +/** + * @brief floating-point Circular write function. + */ +CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32( + int32_t* circBuffer, + int32_t L, + uint16_t* writeOffset, + int32_t bufferInc, + const int32_t* src, + int32_t srcInc, + uint32_t blockSize) +{ + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0u) { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; +} + + + +/** + * @brief floating-point Circular Read function. + */ +CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32( + int32_t* circBuffer, + int32_t L, + int32_t* readOffset, + int32_t bufferInc, + int32_t* dst, + int32_t* dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) +{ + uint32_t i = 0u; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0u) { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (int32_t*) dst_end) { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; +} + + +/** + * @brief Q15 Circular write function. + */ +CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15( + q15_t* circBuffer, + int32_t L, + uint16_t* writeOffset, + int32_t bufferInc, + const q15_t* src, + int32_t srcInc, + uint32_t blockSize) +{ + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0u) { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; +} + + +/** + * @brief Q15 Circular Read function. + */ +CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15( + q15_t* circBuffer, + int32_t L, + int32_t* readOffset, + int32_t bufferInc, + q15_t* dst, + q15_t* dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) +{ + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0u) { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (q15_t*) dst_end) { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; +} + + +/** + * @brief Q7 Circular write function. + */ +CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7( + q7_t* circBuffer, + int32_t L, + uint16_t* writeOffset, + int32_t bufferInc, + const q7_t* src, + int32_t srcInc, + uint32_t blockSize) +{ + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0u) { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; +} + + +/** + * @brief Q7 Circular Read function. + */ +CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7( + q7_t* circBuffer, + int32_t L, + int32_t* readOffset, + int32_t bufferInc, + q7_t* dst, + q7_t* dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) +{ + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0u) { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (q7_t*) dst_end) { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; +} + + +/** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_power_q31( + q31_t* pSrc, + uint32_t blockSize, + q63_t* pResult); + + +/** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_power_f32( + float32_t* pSrc, + uint32_t blockSize, + float32_t* pResult); + + +/** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_power_q15( + q15_t* pSrc, + uint32_t blockSize, + q63_t* pResult); + + +/** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_power_q7( + q7_t* pSrc, + uint32_t blockSize, + q31_t* pResult); + + +/** + * @brief Mean value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_mean_q7( + q7_t* pSrc, + uint32_t blockSize, + q7_t* pResult); + + +/** + * @brief Mean value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_mean_q15( + q15_t* pSrc, + uint32_t blockSize, + q15_t* pResult); + + +/** + * @brief Mean value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_mean_q31( + q31_t* pSrc, + uint32_t blockSize, + q31_t* pResult); + + +/** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_mean_f32( + float32_t* pSrc, + uint32_t blockSize, + float32_t* pResult); + + +/** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_var_f32( + float32_t* pSrc, + uint32_t blockSize, + float32_t* pResult); + + +/** + * @brief Variance of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_var_q31( + q31_t* pSrc, + uint32_t blockSize, + q31_t* pResult); + + +/** + * @brief Variance of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_var_q15( + q15_t* pSrc, + uint32_t blockSize, + q15_t* pResult); + + +/** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_rms_f32( + float32_t* pSrc, + uint32_t blockSize, + float32_t* pResult); + + +/** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_rms_q31( + q31_t* pSrc, + uint32_t blockSize, + q31_t* pResult); + + +/** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_rms_q15( + q15_t* pSrc, + uint32_t blockSize, + q15_t* pResult); + + +/** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_std_f32( + float32_t* pSrc, + uint32_t blockSize, + float32_t* pResult); + + +/** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_std_q31( + q31_t* pSrc, + uint32_t blockSize, + q31_t* pResult); + + +/** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_std_q15( + q15_t* pSrc, + uint32_t blockSize, + q15_t* pResult); + + +/** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ +void arm_cmplx_mag_f32( + float32_t* pSrc, + float32_t* pDst, + uint32_t numSamples); + + +/** + * @brief Q31 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ +void arm_cmplx_mag_q31( + q31_t* pSrc, + q31_t* pDst, + uint32_t numSamples); + + +/** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ +void arm_cmplx_mag_q15( + q15_t* pSrc, + q15_t* pDst, + uint32_t numSamples); + + +/** + * @brief Q15 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ +void arm_cmplx_dot_prod_q15( + q15_t* pSrcA, + q15_t* pSrcB, + uint32_t numSamples, + q31_t* realResult, + q31_t* imagResult); + + +/** + * @brief Q31 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ +void arm_cmplx_dot_prod_q31( + q31_t* pSrcA, + q31_t* pSrcB, + uint32_t numSamples, + q63_t* realResult, + q63_t* imagResult); + + +/** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ +void arm_cmplx_dot_prod_f32( + float32_t* pSrcA, + float32_t* pSrcB, + uint32_t numSamples, + float32_t* realResult, + float32_t* imagResult); + + +/** + * @brief Q15 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ +void arm_cmplx_mult_real_q15( + q15_t* pSrcCmplx, + q15_t* pSrcReal, + q15_t* pCmplxDst, + uint32_t numSamples); + + +/** + * @brief Q31 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ +void arm_cmplx_mult_real_q31( + q31_t* pSrcCmplx, + q31_t* pSrcReal, + q31_t* pCmplxDst, + uint32_t numSamples); + + +/** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ +void arm_cmplx_mult_real_f32( + float32_t* pSrcCmplx, + float32_t* pSrcReal, + float32_t* pCmplxDst, + uint32_t numSamples); + + +/** + * @brief Minimum value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ +void arm_min_q7( + q7_t* pSrc, + uint32_t blockSize, + q7_t* result, + uint32_t* index); + + +/** + * @brief Minimum value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ +void arm_min_q15( + q15_t* pSrc, + uint32_t blockSize, + q15_t* pResult, + uint32_t* pIndex); + + +/** + * @brief Minimum value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ +void arm_min_q31( + q31_t* pSrc, + uint32_t blockSize, + q31_t* pResult, + uint32_t* pIndex); + + +/** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ +void arm_min_f32( + float32_t* pSrc, + uint32_t blockSize, + float32_t* pResult, + uint32_t* pIndex); + + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ +void arm_max_q7( + q7_t* pSrc, + uint32_t blockSize, + q7_t* pResult, + uint32_t* pIndex); + + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ +void arm_max_q15( + q15_t* pSrc, + uint32_t blockSize, + q15_t* pResult, + uint32_t* pIndex); + + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ +void arm_max_q31( + q31_t* pSrc, + uint32_t blockSize, + q31_t* pResult, + uint32_t* pIndex); + + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ +void arm_max_f32( + float32_t* pSrc, + uint32_t blockSize, + float32_t* pResult, + uint32_t* pIndex); + + +/** + * @brief Q15 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ +void arm_cmplx_mult_cmplx_q15( + q15_t* pSrcA, + q15_t* pSrcB, + q15_t* pDst, + uint32_t numSamples); + + +/** + * @brief Q31 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ +void arm_cmplx_mult_cmplx_q31( + q31_t* pSrcA, + q31_t* pSrcB, + q31_t* pDst, + uint32_t numSamples); + + +/** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ +void arm_cmplx_mult_cmplx_f32( + float32_t* pSrcA, + float32_t* pSrcB, + float32_t* pDst, + uint32_t numSamples); + + +/** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + */ +void arm_float_to_q31( + float32_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + */ +void arm_float_to_q15( + float32_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + */ +void arm_float_to_q7( + float32_t* pSrc, + q7_t* pDst, + uint32_t blockSize); + + +/** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ +void arm_q31_to_q15( + q31_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + + +/** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ +void arm_q31_to_q7( + q31_t* pSrc, + q7_t* pDst, + uint32_t blockSize); + + +/** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ +void arm_q15_to_float( + q15_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + + +/** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ +void arm_q15_to_q31( + q15_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + + +/** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ +void arm_q15_to_q7( + q15_t* pSrc, + q7_t* pDst, + uint32_t blockSize); + + +/** + * @ingroup groupInterpolation + */ + +/** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+ *   typedef struct
+ *   {
+ *     uint16_t numRows;
+ *     uint16_t numCols;
+ *     float32_t *pData;
+ * } arm_bilinear_interp_instance_f32;
+ *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+ *     XF = floor(x)
+ *     YF = floor(y)
+ *
+ * \par + * The interpolated output point is computed as: + * 
+ *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+ *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+ *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+ *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+ *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + +/** + * @addtogroup BilinearInterpolate + * @{ + */ + + +/** +* +* @brief Floating-point bilinear interpolation. +* @param[in,out] S points to an instance of the interpolation structure. +* @param[in] X interpolation coordinate. +* @param[in] Y interpolation coordinate. +* @return out interpolated value. +*/ +CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32* S, + float32_t X, + float32_t Y) +{ + float32_t out; + float32_t f00, f01, f10, f11; + float32_t* pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); +} + + +/** +* +* @brief Q31 bilinear interpolation. +* @param[in,out] S points to an instance of the interpolation structure. +* @param[in] X interpolation coordinate in 12.20 format. +* @param[in] Y interpolation coordinate in 12.20 format. +* @return out interpolated value. +*/ +CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31* S, + q31_t X, + q31_t Y) +{ + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t* pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; + x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; + y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return ((q31_t)(acc << 2)); +} + + +/** +* @brief Q15 bilinear interpolation. +* @param[in,out] S points to an instance of the interpolation structure. +* @param[in] X interpolation coordinate in 12.20 format. +* @param[in] Y interpolation coordinate in 12.20 format. +* @return out interpolated value. +*/ +CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15* S, + q31_t X, + q31_t Y) +{ + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t* pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return ((q15_t)(acc >> 36)); +} + + +/** +* @brief Q7 bilinear interpolation. +* @param[in,out] S points to an instance of the interpolation structure. +* @param[in] X interpolation coordinate in 12.20 format. +* @param[in] Y interpolation coordinate in 12.20 format. +* @return out interpolated value. +*/ +CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7* S, + q31_t X, + q31_t Y) +{ + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t* pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return ((q7_t)(acc >> 40)); +} + +/** + * @} end of BilinearInterpolate group + */ + + +/* SMMLAR */ +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMLSR */ +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMULR */ +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +/* SMMLA */ +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +/* SMMLS */ +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +/* SMMUL */ +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) +/* Enter low optimization region - place directly above function definition */ +#if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) +#define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") +#else +#define LOW_OPTIMIZATION_ENTER +#endif + +/* Exit low optimization region - place directly after end of function definition */ +#if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) +#define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") +#else +#define LOW_OPTIMIZATION_EXIT +#endif + +/* Enter low optimization region - place directly above function definition */ +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER + +/* Exit low optimization region - place directly after end of function definition */ +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) +#define LOW_OPTIMIZATION_ENTER +#define LOW_OPTIMIZATION_EXIT +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __GNUC__ ) +#define LOW_OPTIMIZATION_ENTER \ + __attribute__(( optimize("-O1") )) +#define LOW_OPTIMIZATION_EXIT +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __ICCARM__ ) +/* Enter low optimization region - place directly above function definition */ +#if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) +#define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") +#else +#define LOW_OPTIMIZATION_ENTER +#endif + +/* Exit low optimization region - place directly after end of function definition */ +#define LOW_OPTIMIZATION_EXIT + +/* Enter low optimization region - place directly above function definition */ +#if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") +#else +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#endif + +/* Exit low optimization region - place directly after end of function definition */ +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TI_ARM__ ) +#define LOW_OPTIMIZATION_ENTER +#define LOW_OPTIMIZATION_EXIT +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __CSMC__ ) +#define LOW_OPTIMIZATION_ENTER +#define LOW_OPTIMIZATION_EXIT +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TASKING__ ) +#define LOW_OPTIMIZATION_ENTER +#define LOW_OPTIMIZATION_EXIT +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + +#ifdef __cplusplus +} +#endif + + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_armcc.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_armcc.h new file mode 100644 index 000000000..4617b1280 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_armcc.h @@ -0,0 +1,796 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (ARM compiler V5) header file + * @version V5.0.1 + * @date 03. February 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) +#error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) +#define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) +#define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) +#define __ARM_ARCH_7EM__ 1 +#endif + +/* __ARM_ARCH_8M_BASE__ not applicable */ +/* __ARM_ARCH_8M_MAIN__ not applicable */ + + +/* CMSIS compiler specific defines */ +#ifndef __ASM +#define __ASM __asm +#endif +#ifndef __INLINE +#define __INLINE __inline +#endif +#ifndef __STATIC_INLINE +#define __STATIC_INLINE static __inline +#endif +#ifndef __NO_RETURN +#define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED +#define __USED __attribute__((used)) +#endif +#ifndef __WEAK +#define __WEAK __attribute__((weak)) +#endif +#ifndef __UNALIGNED_UINT32 +#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __ALIGNED +#define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __PACKED +#define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT +#define __PACKED_STRUCT __packed struct +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) +#define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return(result); +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else +#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else +#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else +#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) +#define __STREXB(value, ptr) __strex(value, ptr) +#else +#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) +#define __STREXH(value, ptr) __strex(value, ptr) +#else +#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) +#define __STREXW(value, ptr) __strex(value, ptr) +#else +#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_armclang.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_armclang.h new file mode 100644 index 000000000..6b21a5bea --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_armclang.h @@ -0,0 +1,1735 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler ARMCLANG (ARM compiler V6) header file + * @version V5.0.1 + * @date 02. February 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for ARM Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM +#define __ASM __asm +#endif +#ifndef __INLINE +#define __INLINE __inline +#endif +#ifndef __STATIC_INLINE +#define __STATIC_INLINE static __inline +#endif +#ifndef __NO_RETURN +#define __NO_RETURN __attribute__((noreturn)) +#endif +#ifndef __USED +#define __USED __attribute__((used)) +#endif +#ifndef __WEAK +#define __WEAK __attribute__((weak)) +#endif +#ifndef __UNALIGNED_UINT32 +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wpacked" +struct __attribute__((packed)) T_UINT32 { + uint32_t v; +}; +#pragma clang diagnostic pop +#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __ALIGNED +#define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __PACKED +#define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT +#define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return(result); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Get Process Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + + return(result); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Get Main Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Set Main Stack Pointer Limit (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +/* #define __get_FPSCR __builtin_arm_get_fpscr */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +/* #define __set_FPSCR __builtin_arm_set_fpscr */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "memory"); +#else + (void)fpscr; +#endif +} + +#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF); + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF); + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF); + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __builtin_bswap32 + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16 __builtin_bswap16 /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */ +#if 0 +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} +#endif + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +/* ToDo ARMCLANG: check if __builtin_bswap16 could be used */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ + int32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +/* ToDo ARMCLANG: check if __builtin_arm_rbit is supported */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return(result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t* ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t* ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t* ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t* ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t* ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t* ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t* ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t* ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t* ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t* ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t* ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t* ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ + ({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_compiler.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_compiler.h new file mode 100644 index 000000000..89cd69027 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_compiler.h @@ -0,0 +1,231 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.0.1 + * @date 30. January 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * ARM Compiler 4/5 + */ +#if defined ( __CC_ARM ) +#include "cmsis_armcc.h" + + +/* + * ARM Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) +#include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + +#ifndef __ASM +#define __ASM __asm +#endif +#ifndef __INLINE +#define __INLINE inline +#endif +#ifndef __STATIC_INLINE +#define __STATIC_INLINE static inline +#endif + +#include + +#ifndef __NO_RETURN +#define __NO_RETURN __noreturn +#endif +#ifndef __USED +#define __USED __root +#endif +#ifndef __WEAK +#define __WEAK __weak +#endif +#ifndef __UNALIGNED_UINT32 +__packed struct T_UINT32 { + uint32_t v; +}; +#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __ALIGNED +#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. +#define __ALIGNED(x) +#endif +#ifndef __PACKED +#define __PACKED __packed +#endif +#ifndef __PACKED_STRUCT +#define __PACKED_STRUCT __packed struct +#endif + + +/* + * TI ARM Compiler + */ +#elif defined ( __TI_ARM__ ) +#include + +#ifndef __ASM +#define __ASM __asm +#endif +#ifndef __INLINE +#define __INLINE inline +#endif +#ifndef __STATIC_INLINE +#define __STATIC_INLINE static inline +#endif +#ifndef __NO_RETURN +#define __NO_RETURN __attribute__((noreturn)) +#endif +#ifndef __USED +#define __USED __attribute__((used)) +#endif +#ifndef __WEAK +#define __WEAK __attribute__((weak)) +#endif +#ifndef __UNALIGNED_UINT32 +struct __attribute__((packed)) T_UINT32 { + uint32_t v; +}; +#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __ALIGNED +#define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __PACKED +#define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT +#define __PACKED_STRUCT struct __attribute__((packed)) +#endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +#ifndef __ASM +#define __ASM __asm +#endif +#ifndef __INLINE +#define __INLINE inline +#endif +#ifndef __STATIC_INLINE +#define __STATIC_INLINE static inline +#endif +#ifndef __NO_RETURN +#define __NO_RETURN __attribute__((noreturn)) +#endif +#ifndef __USED +#define __USED __attribute__((used)) +#endif +#ifndef __WEAK +#define __WEAK __attribute__((weak)) +#endif +#ifndef __UNALIGNED_UINT32 +struct __packed__ T_UINT32 { + uint32_t v; +}; +#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __ALIGNED +#define __ALIGNED(x) __align(x) +#endif +#ifndef __PACKED +#define __PACKED __packed__ +#endif +#ifndef __PACKED_STRUCT +#define __PACKED_STRUCT struct __packed__ +#endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) +#include + +#ifndef __ASM +#define __ASM _asm +#endif +#ifndef __INLINE +#define __INLINE inline +#endif +#ifndef __STATIC_INLINE +#define __STATIC_INLINE static inline +#endif +#ifndef __NO_RETURN +// NO RETURN is automatically detected hence no warning here +#define __NO_RETURN +#endif +#ifndef __USED +#warning No compiler specific solution for __USED. __USED is ignored. +#define __USED +#endif +#ifndef __WEAK +#define __WEAK __weak +#endif +#ifndef __UNALIGNED_UINT32 +@packed struct T_UINT32 { + uint32_t v; +}; +#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __ALIGNED +#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. +#define __ALIGNED(x) +#endif +#ifndef __PACKED +#define __PACKED @packed +#endif +#ifndef __PACKED_STRUCT +#define __PACKED_STRUCT @packed struct +#endif + + +#else +#error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_gcc.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_gcc.h new file mode 100644 index 000000000..919f26d15 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_gcc.h @@ -0,0 +1,1900 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.0.1 + * @date 02. February 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* CMSIS compiler specific defines */ +#ifndef __ASM +#define __ASM __asm +#endif +#ifndef __INLINE +#define __INLINE inline +#endif +#ifndef __STATIC_INLINE +#define __STATIC_INLINE static inline +#endif +#ifndef __NO_RETURN +#define __NO_RETURN __attribute__((noreturn)) +#endif +#ifndef __USED +#define __USED __attribute__((used)) +#endif +#ifndef __WEAK +#define __WEAK __attribute__((weak)) +#endif +#ifndef __UNALIGNED_UINT32 +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpacked" +#pragma GCC diagnostic ignored "-Wattributes" +struct __attribute__((packed)) T_UINT32 { + uint32_t v; +}; +#pragma GCC diagnostic pop +#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __ALIGNED +#define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __PACKED +#define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT +#define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return(result); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Get Process Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + + return(result); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Get Main Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Set Main Stack Pointer Limit (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#else + (void)fpscr; +#endif +} + +#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +//__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) +//{ +// __ASM volatile ("nop"); +//} +#define __NOP() __ASM volatile ("nop") /* This implementation generates debug information */ + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +//__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) +//{ +// __ASM volatile ("wfi"); +//} +#define __WFI() __ASM volatile ("wfi") /* This implementation generates debug information */ + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +//__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) +//{ +// __ASM volatile ("wfe"); +//} +#define __WFE() __ASM volatile ("wfe") /* This implementation generates debug information */ + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +//__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) +//{ +// __ASM volatile ("sev"); +//} +#define __SEV() __ASM volatile ("sev") /* This implementation generates debug information */ + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF"::: "memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF"::: "memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF"::: "memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + int32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return(result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t* addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t* addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t* addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t* addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t* addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t* addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ + ({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t* ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t* ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t* ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t* ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t* ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t* ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t* ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t* ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t* ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t* ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t* ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t* ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAEXB(volatile uint8_t* ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAEXH(volatile uint16_t* ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDAEX(volatile uint32_t* ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t* ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t* ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEX(uint32_t value, volatile uint32_t* ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__ARM_FEATURE_DSP == 1) /* ToDo ARMCLANG: This should be ARCH >= ARMv7-M + SIMD */ + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ + ({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_armv8mbl.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_armv8mbl.h new file mode 100644 index 000000000..4e65d1d95 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_armv8mbl.h @@ -0,0 +1,1813 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS ARMv8MBL Core Peripheral Access Layer Header File + * @version V5.0.1 + * @date 25. November 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) +#pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +/* CMSIS cmGrebe definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) +#if defined __TARGET_FPU_VFP +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#if defined __ARM_PCS_VFP +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __ICCARM__ ) +#if defined __ARMVFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TI_ARM__ ) +#if defined __TI_VFP_SUPPORT__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TASKING__ ) +#if defined __FPU_VFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __CSMC__ ) +#if ( __CSMC__ & 0x400U) +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus +extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __ARMv8MBL_REV +#define __ARMv8MBL_REV 0x0000U +#warning "__ARMv8MBL_REV not defined in device header file; using default!" +#endif + +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 0U +#warning "__FPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0U +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __SAUREGION_PRESENT +#define __SAUREGION_PRESENT 0U +#warning "__SAUREGION_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __VTOR_PRESENT +#define __VTOR_PRESENT 0U +#warning "__VTOR_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 2U +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0U +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif + +#ifndef __ETM_PRESENT +#define __ETM_PRESENT 0U +#warning "__ETM_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __MTB_PRESENT +#define __MTB_PRESENT 0U +#warning "__MTB_PRESENT not defined in device header file; using default!" +#endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union { + struct { + uint32_t _reserved0: 28; /*!< bit: 0..27 Reserved */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */ + uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1: 3; /*!< bit: 25..27 Reserved */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union { + struct { + uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL: 1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct { + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct { + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct { + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct { + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct { + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct { + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct { + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct { + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ +#define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ +#define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ +#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ +#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ +#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + +#define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ +#define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ +#define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ +#define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ +#define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ +#endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifndef CMSIS_NVIC_VIRTUAL +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for ARMv8-M Baseline */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for ARMv8-M Baseline */ +#define NVIC_EnableIRQ __NVIC_EnableIRQ +#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ +#define NVIC_DisableIRQ __NVIC_DisableIRQ +#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ +#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ +#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +#define NVIC_GetActive __NVIC_GetActive +#define NVIC_SetPriority __NVIC_SetPriority +#define NVIC_GetPriority __NVIC_GetPriority +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifndef CMSIS_VECTAB_VIRTUAL +#define NVIC_SetVector __NVIC_SetVector +#define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t* vectors = (uint32_t*)SCB->VTOR; +#else + uint32_t* vectors = (uint32_t*)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t* vectors = (uint32_t*)SCB->VTOR; +#else + uint32_t* vectors = (uint32_t*)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) { /* wait until reset */ + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_armv8mml.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_armv8mml.h new file mode 100644 index 000000000..273c3849c --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_armv8mml.h @@ -0,0 +1,2821 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS ARMv8MML Core Peripheral Access Layer Header File + * @version V5.0.2 + * @date 07. December 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) +#pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +/* CMSIS ARMv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) +#if defined __TARGET_FPU_VFP +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#if defined __ARM_PCS_VFP +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __ICCARM__ ) +#if defined __ARMVFP__ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __TI_ARM__ ) +#if defined __TI_VFP_SUPPORT__ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __TASKING__ ) +#if defined __FPU_VFP__ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __CSMC__ ) +#if ( __CSMC__ & 0x400U) +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus +extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __ARMv8MML_REV +#define __ARMv8MML_REV 0x0000U +#warning "__ARMv8MML_REV not defined in device header file; using default!" +#endif + +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 0U +#warning "__FPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0U +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __SAUREGION_PRESENT +#define __SAUREGION_PRESENT 0U +#warning "__SAUREGION_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __DSP_PRESENT +#define __DSP_PRESENT 0U +#warning "__DSP_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 3U +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0U +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union { + struct { + uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 7; /*!< bit: 9..15 Reserved */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 4; /*!< bit: 20..23 Reserved */ + uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT: 2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union { + struct { + uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL: 1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA: 1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA: 1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1: 28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct { + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct { + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct { + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct { + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct { + __OM union { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct { + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct { + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct { + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct { + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct { + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct { + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ +#define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ +#define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ +#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ +#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ +#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + +#define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ +#define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ +#define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ +#define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ +#define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ +#define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ +#endif + +#define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ +#define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifndef CMSIS_NVIC_VIRTUAL +#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping +#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping +#define NVIC_EnableIRQ __NVIC_EnableIRQ +#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ +#define NVIC_DisableIRQ __NVIC_DisableIRQ +#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ +#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ +#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +#define NVIC_GetActive __NVIC_GetActive +#define NVIC_SetPriority __NVIC_SetPriority +#define NVIC_GetPriority __NVIC_GetPriority +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifndef CMSIS_VECTAB_VIRTUAL +#define NVIC_SetVector __NVIC_SetVector +#define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else { + SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) { + return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else { + return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t* vectors = (uint32_t*)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t* vectors = (uint32_t*)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) { /* wait until reset */ + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else { + SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { + return 1U; /* Single precision FPU */ + } + else { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) { /* ITM Port #0 enabled */ + while (ITM->PORT[0U].u32 == 0UL) { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } + else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm0.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm0.h new file mode 100644 index 000000000..d06d984b7 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm0.h @@ -0,0 +1,850 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.1 + * @date 25. November 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) +#pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) +#if defined __TARGET_FPU_VFP +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#if defined __ARM_PCS_VFP +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __ICCARM__ ) +#if defined __ARMVFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TI_ARM__ ) +#if defined __TI_VFP_SUPPORT__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TASKING__ ) +#if defined __FPU_VFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __CSMC__ ) +#if ( __CSMC__ & 0x400U) +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus +extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __CM0_REV +#define __CM0_REV 0x0000U +#warning "__CM0_REV not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 2U +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0U +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union { + struct { + uint32_t _reserved0: 28; /*!< bit: 0..27 Reserved */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */ + uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1: 3; /*!< bit: 25..27 Reserved */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union { + struct { + uint32_t _reserved0: 1; /*!< bit: 0 Reserved */ + uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct { + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct { + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct { + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifndef CMSIS_NVIC_VIRTUAL +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0 */ +#define NVIC_EnableIRQ __NVIC_EnableIRQ +#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ +#define NVIC_DisableIRQ __NVIC_DisableIRQ +#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ +#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ +#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ +#define NVIC_SetPriority __NVIC_SetPriority +#define NVIC_GetPriority __NVIC_GetPriority +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifndef CMSIS_VECTAB_VIRTUAL +#define NVIC_SetVector __NVIC_SetVector +#define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t* vectors = (uint32_t*)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t* vectors = (uint32_t*)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) { /* wait until reset */ + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm0plus.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm0plus.h new file mode 100644 index 000000000..ebc43f3a1 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm0plus.h @@ -0,0 +1,975 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.1 + * @date 25. November 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) +#pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) +#if defined __TARGET_FPU_VFP +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#if defined __ARM_PCS_VFP +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __ICCARM__ ) +#if defined __ARMVFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TI_ARM__ ) +#if defined __TI_VFP_SUPPORT__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TASKING__ ) +#if defined __FPU_VFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __CSMC__ ) +#if ( __CSMC__ & 0x400U) +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus +extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __CM0PLUS_REV +#define __CM0PLUS_REV 0x0000U +#warning "__CM0PLUS_REV not defined in device header file; using default!" +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0U +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __VTOR_PRESENT +#define __VTOR_PRESENT 0U +#warning "__VTOR_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 2U +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0U +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union { + struct { + uint32_t _reserved0: 28; /*!< bit: 0..27 Reserved */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */ + uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1: 3; /*!< bit: 25..27 Reserved */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union { + struct { + uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct { + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct { + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct { + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct { + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifndef CMSIS_NVIC_VIRTUAL +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0+ */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0+ */ +#define NVIC_EnableIRQ __NVIC_EnableIRQ +#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ +#define NVIC_DisableIRQ __NVIC_DisableIRQ +#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ +#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ +#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ +#define NVIC_SetPriority __NVIC_SetPriority +#define NVIC_GetPriority __NVIC_GetPriority +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifndef CMSIS_VECTAB_VIRTUAL +#define NVIC_SetVector __NVIC_SetVector +#define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t* vectors = (uint32_t*)SCB->VTOR; +#else + uint32_t* vectors = (uint32_t*)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t* vectors = (uint32_t*)SCB->VTOR; +#else + uint32_t* vectors = (uint32_t*)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; + +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) { /* wait until reset */ + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm23.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm23.h new file mode 100644 index 000000000..513635a58 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm23.h @@ -0,0 +1,1813 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.0.1 + * @date 25. November 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) +#pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +/* CMSIS cmGrebe definitions */ +#define __CM23_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) +#if defined __TARGET_FPU_VFP +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#if defined __ARM_PCS_VFP +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __ICCARM__ ) +#if defined __ARMVFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TI_ARM__ ) +#if defined __TI_VFP_SUPPORT__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TASKING__ ) +#if defined __FPU_VFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __CSMC__ ) +#if ( __CSMC__ & 0x400U) +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus +extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __CM23_REV +#define __CM23_REV 0x0000U +#warning "__CM23_REV not defined in device header file; using default!" +#endif + +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 0U +#warning "__FPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0U +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __SAUREGION_PRESENT +#define __SAUREGION_PRESENT 0U +#warning "__SAUREGION_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __VTOR_PRESENT +#define __VTOR_PRESENT 0U +#warning "__VTOR_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 2U +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0U +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif + +#ifndef __ETM_PRESENT +#define __ETM_PRESENT 0U +#warning "__ETM_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __MTB_PRESENT +#define __MTB_PRESENT 0U +#warning "__MTB_PRESENT not defined in device header file; using default!" +#endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union { + struct { + uint32_t _reserved0: 28; /*!< bit: 0..27 Reserved */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */ + uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1: 3; /*!< bit: 25..27 Reserved */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union { + struct { + uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL: 1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct { + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct { + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct { + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct { + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct { + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct { + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct { + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct { + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ +#define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ +#define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ +#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ +#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ +#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + +#define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ +#define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ +#define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ +#define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ +#define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ +#endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifndef CMSIS_NVIC_VIRTUAL +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ +#define NVIC_EnableIRQ __NVIC_EnableIRQ +#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ +#define NVIC_DisableIRQ __NVIC_DisableIRQ +#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ +#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ +#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +#define NVIC_GetActive __NVIC_GetActive +#define NVIC_SetPriority __NVIC_SetPriority +#define NVIC_GetPriority __NVIC_GetPriority +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifndef CMSIS_VECTAB_VIRTUAL +#define NVIC_SetVector __NVIC_SetVector +#define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t* vectors = (uint32_t*)SCB->VTOR; +#else + uint32_t* vectors = (uint32_t*)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t* vectors = (uint32_t*)SCB->VTOR; +#else + uint32_t* vectors = (uint32_t*)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) { /* wait until reset */ + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm3.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm3.h new file mode 100644 index 000000000..8cbf329b8 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm3.h @@ -0,0 +1,1880 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.0.1 + * @date 30. January 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) +#pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) +#if defined __TARGET_FPU_VFP +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#if defined __ARM_PCS_VFP +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __ICCARM__ ) +#if defined __ARMVFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TI_ARM__ ) +#if defined __TI_VFP_SUPPORT__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TASKING__ ) +#if defined __FPU_VFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __CSMC__ ) +#if ( __CSMC__ & 0x400U) +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus +extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __CM3_REV +#define __CM3_REV 0x0200U +#warning "__CM3_REV not defined in device header file; using default!" +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0U +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 3U +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0U +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union { + struct { + uint32_t _reserved0: 27; /*!< bit: 0..26 Reserved */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1: 6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1: 8; /*!< bit: 16..23 Reserved */ + uint32_t T: 1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2: 2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union { + struct { + uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct { + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct { + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct { + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct { + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct { + __OM union { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct { + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct { + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct { + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct { + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL +#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE +#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" +#endif +#include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping +#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping +#define NVIC_EnableIRQ __NVIC_EnableIRQ +#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ +#define NVIC_DisableIRQ __NVIC_DisableIRQ +#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ +#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ +#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +#define NVIC_GetActive __NVIC_GetActive +#define NVIC_SetPriority __NVIC_SetPriority +#define NVIC_GetPriority __NVIC_GetPriority +#define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL +#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" +#endif +#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else +#define NVIC_SetVector __NVIC_SetVector +#define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t* vectors = (uint32_t*)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t* vectors = (uint32_t*)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) { /* wait until reset */ + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) { /* ITM Port #0 enabled */ + while (ITM->PORT[0U].u32 == 0UL) { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } + else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm33.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm33.h new file mode 100644 index 000000000..00de7795e --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm33.h @@ -0,0 +1,2821 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.0.2 + * @date 07. December 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) +#pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) +#if defined __TARGET_FPU_VFP +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#if defined __ARM_PCS_VFP +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __ICCARM__ ) +#if defined __ARMVFP__ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __TI_ARM__ ) +#if defined __TI_VFP_SUPPORT__ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __TASKING__ ) +#if defined __FPU_VFP__ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __CSMC__ ) +#if ( __CSMC__ & 0x400U) +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus +extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __CM33_REV +#define __CM33_REV 0x0000U +#warning "__CM33_REV not defined in device header file; using default!" +#endif + +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 0U +#warning "__FPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0U +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __SAUREGION_PRESENT +#define __SAUREGION_PRESENT 0U +#warning "__SAUREGION_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __DSP_PRESENT +#define __DSP_PRESENT 0U +#warning "__DSP_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 3U +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0U +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union { + struct { + uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 7; /*!< bit: 9..15 Reserved */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 4; /*!< bit: 20..23 Reserved */ + uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT: 2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union { + struct { + uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL: 1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA: 1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA: 1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1: 28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct { + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct { + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct { + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct { + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct { + __OM union { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct { + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct { + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct { + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct { + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct { + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct { + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ +#define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ +#define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ +#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ +#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ +#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + +#define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ +#define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ +#define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ +#define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ +#define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ +#define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ +#endif + +#define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ +#define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifndef CMSIS_NVIC_VIRTUAL +#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping +#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping +#define NVIC_EnableIRQ __NVIC_EnableIRQ +#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ +#define NVIC_DisableIRQ __NVIC_DisableIRQ +#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ +#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ +#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +#define NVIC_GetActive __NVIC_GetActive +#define NVIC_SetPriority __NVIC_SetPriority +#define NVIC_GetPriority __NVIC_GetPriority +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifndef CMSIS_VECTAB_VIRTUAL +#define NVIC_SetVector __NVIC_SetVector +#define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else { + SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) { + return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else { + return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t* vectors = (uint32_t*)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t* vectors = (uint32_t*)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) { /* wait until reset */ + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else { + SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { + return 1U; /* Single precision FPU */ + } + else { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) { /* ITM Port #0 enabled */ + while (ITM->PORT[0U].u32 == 0UL) { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } + else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm4.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm4.h new file mode 100644 index 000000000..f4c8011f8 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm4.h @@ -0,0 +1,2061 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.0.1 + * @date 30. January 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) +#pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) +#if defined __TARGET_FPU_VFP +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#if defined __ARM_PCS_VFP +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __ICCARM__ ) +#if defined __ARMVFP__ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __TI_ARM__ ) +#if defined __TI_VFP_SUPPORT__ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __TASKING__ ) +#if defined __FPU_VFP__ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __CSMC__ ) +#if ( __CSMC__ & 0x400U) +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus +extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __CM4_REV +#define __CM4_REV 0x0000U +#warning "__CM4_REV not defined in device header file; using default!" +#endif + +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 0U +#warning "__FPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0U +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 3U +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0U +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union { + struct { + uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1: 6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 4; /*!< bit: 20..23 Reserved */ + uint32_t T: 1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2: 2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union { + struct { + uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA: 1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0: 29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct { + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct { + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct { + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct { + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct { + __OM union { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct { + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct { + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct { + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct { + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct { + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL +#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE +#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" +#endif +#include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping +#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping +#define NVIC_EnableIRQ __NVIC_EnableIRQ +#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ +#define NVIC_DisableIRQ __NVIC_DisableIRQ +#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ +#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ +#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +#define NVIC_GetActive __NVIC_GetActive +#define NVIC_SetPriority __NVIC_SetPriority +#define NVIC_GetPriority __NVIC_GetPriority +#define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL +#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" +#endif +#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else +#define NVIC_SetVector __NVIC_SetVector +#define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t* vectors = (uint32_t*)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t* vectors = (uint32_t*)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) { /* wait until reset */ + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { + return 1U; /* Single precision FPU */ + } + else { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) { /* ITM Port #0 enabled */ + while (ITM->PORT[0U].u32 == 0UL) { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } + else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm7.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm7.h new file mode 100644 index 000000000..c09acc824 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm7.h @@ -0,0 +1,2592 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.0.1 + * @date 25. November 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) +#pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) +#if defined __TARGET_FPU_VFP +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#if defined __ARM_PCS_VFP +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __ICCARM__ ) +#if defined __ARMVFP__ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __TI_ARM__ ) +#if defined __TI_VFP_SUPPORT__ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __TASKING__ ) +#if defined __FPU_VFP__ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __CSMC__ ) +#if ( __CSMC__ & 0x400U) +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus +extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __CM7_REV +#define __CM7_REV 0x0000U +#warning "__CM7_REV not defined in device header file; using default!" +#endif + +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 0U +#warning "__FPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0U +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __ICACHE_PRESENT +#define __ICACHE_PRESENT 0U +#warning "__ICACHE_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __DCACHE_PRESENT +#define __DCACHE_PRESENT 0U +#warning "__DCACHE_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __DTCM_PRESENT +#define __DTCM_PRESENT 0U +#warning "__DTCM_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 3U +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0U +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union { + struct { + uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1: 6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 4; /*!< bit: 20..23 Reserved */ + uint32_t T: 1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2: 2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union { + struct { + uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA: 1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0: 29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct { + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct { + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct { + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct { + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct { + __OM union { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct { + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct { + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct { + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct { + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct { + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifndef CMSIS_NVIC_VIRTUAL +#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping +#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping +#define NVIC_EnableIRQ __NVIC_EnableIRQ +#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ +#define NVIC_DisableIRQ __NVIC_DisableIRQ +#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ +#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ +#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +#define NVIC_GetActive __NVIC_GetActive +#define NVIC_SetPriority __NVIC_SetPriority +#define NVIC_GetPriority __NVIC_GetPriority +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifndef CMSIS_VECTAB_VIRTUAL +#define NVIC_SetVector __NVIC_SetVector +#define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else { + SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else { + return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t* vectors = (uint32_t*)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t* vectors = (uint32_t*)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) { /* wait until reset */ + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { + return 1U; /* Single precision FPU */ + } + else { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_INLINE void SCB_EnableICache (void) +{ +#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); +#endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_INLINE void SCB_DisableICache (void) +{ +#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); +#endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_INLINE void SCB_InvalidateICache (void) +{ +#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); +#endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_INLINE void SCB_EnableDCache (void) +{ +#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); +#if defined ( __CC_ARM ) + __schedule_barrier(); +#endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); +#endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_INLINE void SCB_DisableDCache (void) +{ +#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + register uint32_t ccsidr; + register uint32_t sets; + register uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); +#if defined ( __CC_ARM ) + __schedule_barrier(); +#endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); +#endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_INLINE void SCB_InvalidateDCache (void) +{ +#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); +#if defined ( __CC_ARM ) + __schedule_barrier(); +#endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); +#endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_INLINE void SCB_CleanDCache (void) +{ +#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); +#if defined ( __CC_ARM ) + __schedule_barrier(); +#endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); +#endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_INLINE void SCB_CleanInvalidateDCache (void) +{ +#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); +#if defined ( __CC_ARM ) + __schedule_barrier(); +#endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); +#endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t* addr, int32_t dsize) +{ +#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t)addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); +#endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t* addr, int32_t dsize) +{ +#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); +#endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t* addr, int32_t dsize) +{ +#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); +#endif +} + + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) { /* ITM Port #0 enabled */ + while (ITM->PORT[0U].u32 == 0UL) { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } + else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_sc000.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_sc000.h new file mode 100644 index 000000000..ed1063364 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_sc000.h @@ -0,0 +1,976 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.1 + * @date 25. November 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) +#pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) +#if defined __TARGET_FPU_VFP +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#if defined __ARM_PCS_VFP +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __ICCARM__ ) +#if defined __ARMVFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TI_ARM__ ) +#if defined __TI_VFP_SUPPORT__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TASKING__ ) +#if defined __FPU_VFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __CSMC__ ) +#if ( __CSMC__ & 0x400U) +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus +extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __SC000_REV +#define __SC000_REV 0x0000U +#warning "__SC000_REV not defined in device header file; using default!" +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0U +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 2U +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0U +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union { + struct { + uint32_t _reserved0: 28; /*!< bit: 0..27 Reserved */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */ + uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1: 3; /*!< bit: 25..27 Reserved */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union { + struct { + uint32_t _reserved0: 1; /*!< bit: 0 Reserved */ + uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct { + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct { + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct { + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct { + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct { + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifndef CMSIS_NVIC_VIRTUAL +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ +#define NVIC_EnableIRQ __NVIC_EnableIRQ +#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ +#define NVIC_DisableIRQ __NVIC_DisableIRQ +#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ +#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ +#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ +#define NVIC_SetPriority __NVIC_SetPriority +#define NVIC_GetPriority __NVIC_GetPriority +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifndef CMSIS_VECTAB_VIRTUAL +#define NVIC_SetVector __NVIC_SetVector +#define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t* vectors = (uint32_t*)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t* vectors = (uint32_t*)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) { /* wait until reset */ + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_sc300.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_sc300.h new file mode 100644 index 000000000..a1b17e1ce --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_sc300.h @@ -0,0 +1,1851 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.1 + * @date 25. November 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) +#pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) +#if defined __TARGET_FPU_VFP +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#if defined __ARM_PCS_VFP +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __ICCARM__ ) +#if defined __ARMVFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TI_ARM__ ) +#if defined __TI_VFP_SUPPORT__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TASKING__ ) +#if defined __FPU_VFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __CSMC__ ) +#if ( __CSMC__ & 0x400U) +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus +extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __SC300_REV +#define __SC300_REV 0x0000U +#warning "__SC300_REV not defined in device header file; using default!" +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0U +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 3U +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0U +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union { + struct { + uint32_t _reserved0: 27; /*!< bit: 0..26 Reserved */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1: 6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1: 8; /*!< bit: 16..23 Reserved */ + uint32_t T: 1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2: 2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union { + struct { + uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct { + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct { + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct { + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + uint32_t RESERVED1[1U]; +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct { + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct { + __OM union { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct { + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct { + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct { + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct { + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifndef CMSIS_NVIC_VIRTUAL +#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping +#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping +#define NVIC_EnableIRQ __NVIC_EnableIRQ +#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ +#define NVIC_DisableIRQ __NVIC_DisableIRQ +#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ +#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ +#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +#define NVIC_GetActive __NVIC_GetActive +#define NVIC_SetPriority __NVIC_SetPriority +#define NVIC_GetPriority __NVIC_GetPriority +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifndef CMSIS_VECTAB_VIRTUAL +#define NVIC_SetVector __NVIC_SetVector +#define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) { + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t* vectors = (uint32_t*)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t* vectors = (uint32_t*)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) { /* wait until reset */ + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) { /* ITM Port #0 enabled */ + while (ITM->PORT[0U].u32 == 0UL) { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } + else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/tz_context.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/tz_context.h new file mode 100644 index 000000000..cd6d8ab07 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/tz_context.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2015-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------------- + * + * $Date: 21. September 2016 + * $Revision: V1.0 + * + * Project: TrustZone for ARMv8-M + * Title: Context Management for ARMv8-M TrustZone + * + * Version 1.0 + * Initial Release + *---------------------------------------------------------------------------*/ + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/dtype.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/dtype.h new file mode 100644 index 000000000..c77078936 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/dtype.h @@ -0,0 +1,33 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file: dtype.h +/// @author AE TEAM +/// @brief Define the data types to be used in the project, including the function +/// library and application code. Use the data types defined in this file. +//////////////////////////////////////////////////////////////////////////////// +#ifndef __DTYPE_H +#define __DTYPE_H //This is done to avoid including the header file repeatedly in the same file + + +//Defines the read and write characteristics of data, which is often used for storage limits of peripheral registers +#ifndef __I +#define __I volatile const //only read +#endif +#ifndef __O +#define __O volatile //only write +#endif +#ifndef __IO +#define __IO volatile //read write +#endif + +//Common data type definitions + +typedef unsigned char int8u; //haven't symbol8 bit integer variable +typedef signed char int8s; //have symbol8 bit integer variable +typedef unsigned short int16u; //haven't symbol16 bit integer variable +typedef signed short int16s; //have symbol16 bit integer variable +typedef unsigned int int32u; //haven't symbol32 bit integer variable +typedef signed int int32s; //have symbol32 bit integer variable +typedef float fp32; //Single-precision floating-point number (32-bit length) +typedef double fp64; //Double-precision floating-point number (64-bit length) + +#endif //__DTYPE_H diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_adc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_adc.h new file mode 100644 index 000000000..dc0aa3d67 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_adc.h @@ -0,0 +1,341 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_adc.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE ADC +/// FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#ifndef __HAL_ADC_H +#define __HAL_ADC_H + +// Files includes +#include "types.h" +#include "reg_adc.h" + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup ADC_HAL +/// @brief ADC HAL modules +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup ADC_Exported_Types +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ADC_Channels +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + ADC_Channel_0 = 0x00, ///< ADC Channel 0 + ADC_Channel_1 = 0x01, ///< ADC Channel 1 + ADC_Channel_2 = 0x02, ///< ADC Channel 2 + ADC_Channel_3 = 0x03, ///< ADC Channel 3 + ADC_Channel_4 = 0x04, ///< ADC Channel 4 + ADC_Channel_5 = 0x05, ///< ADC Channel 5 + ADC_Channel_6 = 0x06, ///< ADC Channel 6 + ADC_Channel_7 = 0x07, ///< ADC Channel 7 + + ADC_Channel_8 = 0x08, ///< ADC Channel 8 + ADC_Channel_9 = 0x09, ///< ADC Channel 9 + ADC_Channel_10 = 0x0A, ///< ADC Channel 10 + ADC_Channel_11 = 0x0B, ///< ADC Channel 11 + ADC_Channel_12 = 0x0C, ///< ADC Channel 12 + ADC_Channel_13 = 0x0D, ///< ADC Channel 13 + ADC_Channel_14 = 0x0E, ///< ADC Channel 14 + ADC_Channel_15 = 0x0F, ///< ADC Channel 15 + ADC_Channel_TempSensor = 0x0E, ///< Temperature sensor channel(ADC1) + ADC_Channel_VoltReference = 0x0F, ///< Internal reference voltage channel(ADC1) + ADC_Channel_Vrefint = 0x0F, ///< Internal reference voltage channel(ADC1) + +} ADCCHANNEL_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ADC_Sampling_Times +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + ADC_Samctl_1_5 = ADC_SMPR1_SAMCTL0_2_5, ///< ADC sample time select 1.5t + ADC_Samctl_2_5 = ADC_SMPR1_SAMCTL0_2_5, ///< ADC sample time select 2.5t + ADC_Samctl_3_5 = ADC_SMPR1_SAMCTL0_3_5, ///< ADC sample time select 3.5t + ADC_Samctl_4_5 = ADC_SMPR1_SAMCTL0_4_5, ///< ADC sample time select 4.5t + ADC_Samctl_5_5 = ADC_SMPR1_SAMCTL0_5_5, ///< ADC sample time select 5.5t + ADC_Samctl_6_5 = ADC_SMPR1_SAMCTL0_6_5, ///< ADC sample time select 6.5t + ADC_Samctl_7_5 = ADC_SMPR1_SAMCTL0_7_5, ///< ADC sample time select 7.5t + ADC_Samctl_8_5 = ADC_SMPR1_SAMCTL0_8_5, ///< ADC sample time select 7.5t + ADC_Samctl_13_5 = ADC_SMPR1_SAMCTL0_14_5, ///< ADC sample time select 13.5t + ADC_Samctl_14_5 = ADC_SMPR1_SAMCTL0_14_5, ///< ADC sample time select 14.5t + ADC_Samctl_28_5 = ADC_SMPR1_SAMCTL0_29_5, ///< ADC sample time select 28.5t + ADC_Samctl_29_5 = ADC_SMPR1_SAMCTL0_29_5, ///< ADC sample time select 29.5t + ADC_Samctl_41_5 = ADC_SMPR1_SAMCTL0_42_5, ///< ADC sample time select 41.5t + ADC_Samctl_42_5 = ADC_SMPR1_SAMCTL0_42_5, ///< ADC sample time select 42.5t + ADC_Samctl_55_5 = ADC_SMPR1_SAMCTL0_56_5, ///< ADC sample time select 55.5t + ADC_Samctl_56_5 = ADC_SMPR1_SAMCTL0_56_5, ///< ADC sample time select 56.5t + ADC_Samctl_71_5 = ADC_SMPR1_SAMCTL0_72_5, ///< ADC sample time select 71.5t + ADC_Samctl_72_5 = ADC_SMPR1_SAMCTL0_72_5, ///< ADC sample time select 72.5t + ADC_Samctl_239_5 = ADC_SMPR1_SAMCTL0_240_5, ///< ADC sample time select 239.5t + ADC_Samctl_240_5 = ADC_SMPR1_SAMCTL0_240_5 ///< ADC sample time select 240.5t +} ADCSAM_TypeDef; +//////////////////////////////////////////////////////////////////////////////// +/// @brief ADC_Resolution +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + ADC_Resolution_12b = ADC_CFGR_RSLTCTL_12, ///< ADC resolution select 12bit + ADC_Resolution_11b = ADC_CFGR_RSLTCTL_11, ///< ADC resolution select 11bit + ADC_Resolution_10b = ADC_CFGR_RSLTCTL_10, ///< ADC resolution select 10bit + ADC_Resolution_9b = ADC_CFGR_RSLTCTL_9, ///< ADC resolution select 9bit + ADC_Resolution_8b = ADC_CFGR_RSLTCTL_8 ///< ADC resolution select 8bit +} ADCRSL_TypeDef; +/// @brief ADC_Prescare +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + ADC_PCLK2_PRESCARE_3 = ADC_CFGR_PRE_3, ///< ADC preclk 3 + ADC_PCLK2_PRESCARE_5 = ADC_CFGR_PRE_5, ///< ADC preclk 5 + ADC_PCLK2_PRESCARE_7 = ADC_CFGR_PRE_7, ///< ADC preclk 7 + ADC_PCLK2_PRESCARE_9 = ADC_CFGR_PRE_9, ///< ADC preclk 9 + ADC_PCLK2_PRESCARE_11 = ADC_CFGR_PRE_11, ///< ADC preclk 11 + ADC_PCLK2_PRESCARE_13 = ADC_CFGR_PRE_13, ///< ADC preclk 13 + ADC_PCLK2_PRESCARE_15 = ADC_CFGR_PRE_15, ///< ADC preclk 15 + ADC_PCLK2_PRESCARE_17 = ADC_CFGR_PRE_17, ///< ADC preclk 17 + + ADC_PCLK2_PRESCARE_2 = ADC_CFGR_PRE_2, ///< ADC preclk 2 + ADC_PCLK2_PRESCARE_4 = ADC_CFGR_PRE_4, ///< ADC preclk 4 + ADC_PCLK2_PRESCARE_6 = ADC_CFGR_PRE_6, ///< ADC preclk 6 + ADC_PCLK2_PRESCARE_8 = ADC_CFGR_PRE_8, ///< ADC preclk 8 + ADC_PCLK2_PRESCARE_10 = ADC_CFGR_PRE_10, ///< ADC preclk 10 + ADC_PCLK2_PRESCARE_12 = ADC_CFGR_PRE_12, ///< ADC preclk 12 + ADC_PCLK2_PRESCARE_14 = ADC_CFGR_PRE_14, ///< ADC preclk 14 + ADC_PCLK2_PRESCARE_16 = ADC_CFGR_PRE_16 ///< ADC preclk 16 +} ADCPRE_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ADC_Conversion_Mode +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + ADC_Mode_Imm = ADC_CR_IMM, ///< ADC single convert mode + ADC_Mode_Scan = ADC_CR_SCAN, ///< ADC single period convert mode + ADC_Mode_Continue = ADC_CR_CONTINUE ///< ADC continue scan convert mode +} ADCMODE_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ADC_Extrenal_Trigger_Sources_For_Regular_Channels_Conversion +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + ADC1_ExternalTrigConv_T1_CC1 = ADC_CR_T1_CC1, + ADC1_ExternalTrigConv_T1_CC2 = ADC_CR_T1_CC2, + ADC1_ExternalTrigConv_T1_CC3 = ADC_CR_T1_CC3, + ADC1_ExternalTrigConv_T2_CC2 = ADC_CR_T2_CC2, + ADC1_ExternalTrigConv_T3_TRIG = ADC_CR_T3_TRIG, + ADC1_ExternalTrigConv_T3_CC1 = ADC_CR_T3_CC1, + ADC1_ExternalTrigConv_EXTI_11 = ADC_CR_EXTI_11, + ADC1_ExternalTrigConv_T1_CC4_CC5 = ADC_CR_T1_CC4_CC5, + ADC1_ExternalTrigConv_T1_TRIG = ADC_CR_T1_TRIG, + ADC1_ExternalTrigConv_T8_CC4 = ADC_CR_T8_CC4, + ADC1_ExternalTrigConv_T8_CC4_CC5 = ADC_CR_T8_CC4_CC5, + ADC1_ExternalTrigConv_T2_CC1 = ADC_CR_T2_CC1, + ADC1_ExternalTrigConv_T3_CC4 = ADC_CR_T3_CC4, + ADC1_ExternalTrigConv_T2_TRIG = ADC_CR_T2_TRIG, + ADC1_ExternalTrigConv_T8_CC5 = ADC_CR_T8_CC5, + ADC1_ExternalTrigConv_EXTI_15 = ADC_CR_EXTI_15, + ADC1_ExternalTrigConv_T1_CC4 = ADC_CR_TIM1_CC4, + ADC1_ExternalTrigConv_T1_CC5 = ADC_CR_TIM1_CC5 +} EXTERTRIG_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ADC_Data_Align +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + ADC_DataAlign_Right = ADC_CR_RIGHT, ///< ADC data left align + ADC_DataAlign_Left = ADC_CR_LEFT ///< ADC data right align +} ADCDATAALI_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ADC_Flags_Definition +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + ADC_IT_EOC = 1, ///< ADC conversion flag + ADC_FLAG_EOC = 1, + ADC_IT_AWD = 2, ///< ADC window comparator flag + ADC_FLAG_AWD = 2 +} ADCFLAG_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ADC_Trig_Edge +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + ADC_ADC_Trig_Edge_Dual = ADC_CR_TRG_EDGE_DUAL, ///< ADC trig edge dual mode down and up + ADC_ADC_Trig_Edge_Down = ADC_CR_TRG_EDGE_DOWN, ///< ADC trig edge single mode down + ADC_ADC_Trig_Edge_Up = ADC_CR_TRG_EDGE_UP, ///< ADC trig edge single mode up + ADC_ADC_Trig_Edge_Mask = ADC_CR_TRG_EDGE_MASK ///< ADC trig edge is mask, not allowed +} ADCTRIGEDGE_TypeDef; + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ADC_Scan_Direct +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + ADC_Scan_Direct_Up = ADC_CR_SCANDIR, ///< ADC scan from low channel to high channel + ADC_Scan_Direct_Down = 0 ///< ADC scan from High channel to low channel +} ADCSCANDIRECT_TypeDef; +//////////////////////////////////////////////////////////////////////////////// +/// @brief ADC_Trig_Shift +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + ADC_ADC_Trig_Shift_0 = ADC_CR_TRGSHIFT_0, ///< ADC trig shift bit is 0 + ADC_ADC_Trig_Shift_4 = ADC_CR_TRGSHIFT_4, ///< ADC trig shift bit is 4 + ADC_ADC_Trig_Shift_16 = ADC_CR_TRGSHIFT_16, ///< ADC trig shift bit is 16 + ADC_ADC_Trig_Shift_32 = ADC_CR_TRGSHIFT_32, ///< ADC trig shift bit is 32 + ADC_ADC_Trig_Shift_64 = ADC_CR_TRGSHIFT_64, ///< ADC trig shift bit is 64 + ADC_ADC_Trig_Shift_128 = ADC_CR_TRGSHIFT_128, ///< ADC trig shift bit is 128 + ADC_ADC_Trig_Shift_256 = ADC_CR_TRGSHIFT_256, ///< ADC trig shift bit is 256 + ADC_ADC_Trig_Shift_512 = ADC_CR_TRGSHIFT_512, ///< ADC trig shift bit is 512 +} ADCTRIGSHIFT_TypeDef; +//////////////////////////////////////////////////////////////////////////////// +/// @brief ADC_Inject_Sequence_Length the sequencer length for injected channels +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + ADC_Inject_Seqen_Len1 = 0, ///< ADC Injected Seqence length is 1 + ADC_Inject_Seqen_Len2 = 1, ///< ADC Injected Seqence length is 2 + ADC_Inject_Seqen_Len3 = 2, ///< ADC Injected Seqence length is 3 + ADC_Inject_Seqen_Len4 = 3, ///< ADC Injected Seqence length is 4 +} ADC_INJ_SEQ_LEN_TypeDef; +//////////////////////////////////////////////////////////////////////////////// +/// @brief ADC_Inject_Sequence_Length the sequencer length for injected channels +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + ADC_InjectedChannel_1 = 0x00, + ADC_InjectedChannel_2 = 0x04, + ADC_InjectedChannel_3 = 0x08, + ADC_InjectedChannel_4 = 0x0c, +} ADC_INJ_SEQ_Channel_TypeDef; +//////////////////////////////////////////////////////////////////////////////// +/// @brief ADC_Extrenal_Trigger_Sources_For_Regular_Channels_Conversion +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + ADC1_InjectExtTrigSrc_T1_TRGO = ADC_ANY_CR_JTRGSEL_TIM1_TRGO, ///< TIM1 TRGO + ADC1_InjectExtTrigSrc_T1_CC4 = ADC_ANY_CR_JTRGSEL_TIM1_CC4, ///< TIM1 CC4 + ADC1_InjectExtTrigSrc_T1_CC4_CC5 = ADC_ANY_CR_JTRGSEL_TIM1_CC4_CC5, ///< TIM1 CC4 and CC5 + ADC1_InjectExtTrigSrc_T2_CC1 = ADC_ANY_CR_JTRGSEL_TIM2_TIM4CC1, ///< TIM2 CC1 + ADC1_InjectExtTrigSrc_T3_CC4 = ADC_ANY_CR_JTRGSEL_TIM3_TIM5CC4, ///< TIM3 CC4 + ADC1_InjectExtTrigSrc_T8_CC4 = ADC_ANY_CR_JTRGSEL_TIM8_CC4, ///< TIM8 CC4 + ADC1_InjectExtTrigSrc_T8_CC4_CC5 = ADC_ANY_CR_JTRGSEL_TIM8_CC4_CC5, ///< TIM8 CC4 and CC5 + ADC1_InjectExtTrigSrc_EXTI_12 = ADC_ANY_CR_JTRGSEL_EXTI12, ///< EXTI12 + + ADC2_InjectExtTrigSrc_T1_TRGO = ADC_ANY_CR_JTRGSEL_TIM1_TRGO, ///< TIM1 TRGO + ADC2_InjectExtTrigSrc_T1_CC4 = ADC_ANY_CR_JTRGSEL_TIM1_CC4, ///< TIM1 CC4 + ADC2_InjectExtTrigSrc_T1_CC4_CC5 = ADC_ANY_CR_JTRGSEL_TIM1_CC4_CC5, ///< TIM1 CC4 and CC5 + ADC2_InjectExtTrigSrc_T2_CC1 = ADC_ANY_CR_JTRGSEL_TIM2_TIM4CC1, ///< TIM2 CC1 + ADC2_InjectExtTrigSrc_T3_CC4 = ADC_ANY_CR_JTRGSEL_TIM3_TIM5CC4, ///< TIM3 CC4 + ADC2_InjectExtTrigSrc_T8_CC4 = ADC_ANY_CR_JTRGSEL_TIM8_CC4, ///< TIM8 CC4 + ADC2_InjectExtTrigSrc_T8_CC4_CC5 = ADC_ANY_CR_JTRGSEL_TIM8_CC4_CC5, ///< TIM8 CC4 and CC5 + + ADC2_InjectExtTrigSrc_EXTI_12 = ADC_ANY_CR_JTRGSEL_EXTI12, ///< EXTI12 + ADC3_InjectExtTrigSrc_T1_TRGO = ADC_ANY_CR_JTRGSEL_TIM1_TRGO, ///< TIM1 TRGO + ADC3_InjectExtTrigSrc_T1_CC4 = ADC_ANY_CR_JTRGSEL_TIM1_CC4, ///< TIM1 CC4 + ADC3_InjectExtTrigSrc_T1_CC4_CC5 = ADC_ANY_CR_JTRGSEL_TIM1_CC4_CC5, ///< TIM1 CC4 and CC5 + ADC3_InjectExtTrigSrc_T4_CC1 = ADC_ANY_CR_JTRGSEL_TIM2_TIM4CC1, ///< TIM4 CC1 + ADC3_InjectExtTrigSrc_T5_CC4 = ADC_ANY_CR_JTRGSEL_TIM3_TIM5CC4, ///< TIM5 CC4 + ADC3_InjectExtTrigSrc_T8_CC4 = ADC_ANY_CR_JTRGSEL_TIM8_CC4, ///< TIM8 CC4 + ADC3_InjectExtTrigSrc_T8_CC4_CC5 = ADC_ANY_CR_JTRGSEL_TIM8_CC4_CC5, ///< TIM8 CC4 and CC5 + ADC3_InjectExtTrigSrc_EXTI_12 = ADC_ANY_CR_JTRGSEL_EXTI12, ///< EXTI12 +} EXTER_INJ_TRIG_TypeDef; + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ADC Init Structure definition +//////////////////////////////////////////////////////////////////////////////// +typedef struct { + u32 ADC_Resolution; ///< Convert data resolution + u32 ADC_PRESCARE; ///< Clock prescaler + u32 ADC_Mode; ///< ADC conversion mode + FunctionalState ADC_ContinuousConvMode; ///< Useless just for compatibility + u32 ADC_ExternalTrigConv; ///< External trigger source selection + u32 ADC_DataAlign; ///< Data alignmentn +} ADC_InitTypeDef; + +/// @} + + + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup ADC_Exported_Variables +/// @{ +#ifdef _HAL_ADC_C_ + +#define GLOBAL +#else +#define GLOBAL extern +#endif + +#undef GLOBAL +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup ADC_Exported_Functions +/// @{ +void ADC_DeInit(ADC_TypeDef* adc); +void ADC_Init(ADC_TypeDef* adc, ADC_InitTypeDef* init_struct); +void ADC_StructInit(ADC_InitTypeDef* init_struct); +void ADC_Cmd(ADC_TypeDef* adc, FunctionalState state); +void ADC_DMACmd(ADC_TypeDef* adc, FunctionalState state); +void ADC_ITConfig(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_interrupt, FunctionalState state); +void ADC_SoftwareStartConvCmd(ADC_TypeDef* adc, FunctionalState state); +void ADC_RegularChannelConfig(ADC_TypeDef* adc, u32 channel, u8 rank, u32 sample_time);//ADCSAM_TypeDef +void ADC_ExternalTrigConvCmd(ADC_TypeDef* adc, FunctionalState state); +void ADC_ExternalTrigConvConfig(ADC_TypeDef* adc, EXTERTRIG_TypeDef adc_external_trig_source); +#define ADC_ExternalTrigInjectedConvConfig ADC_ExternalTrigConvConfig +void ADC_AnalogWatchdogCmd(ADC_TypeDef* adc, FunctionalState state); +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* adc, u16 high_threshold, u16 low_threshold); +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* adc, ADCCHANNEL_TypeDef channel); +void ADC_TempSensorVrefintCmd(FunctionalState state); +void ADC_ClearITPendingBit(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_interrupt); +void ADC_ClearFlag(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_flag); + +u16 ADC_GetConversionValue(ADC_TypeDef* adc); + +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* adc); +FlagStatus ADC_GetFlagStatus(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_flag); +ITStatus ADC_GetITStatus(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_interrupt); +void ADC_TempSensorCmd(FunctionalState state); +void ADC_VrefintCmd(FunctionalState state); +void exADC_TempSensorVrefintCmd(u32 chs, FunctionalState state); +void ADC_ANY_CH_Config(ADC_TypeDef* adc, u8 rank, ADCCHANNEL_TypeDef adc_channel); +void ADC_ANY_NUM_Config(ADC_TypeDef* adc, u8 num); +void ADC_ANY_Cmd(ADC_TypeDef* adc, FunctionalState state); +void ADC_AutoInjectedConvCmd(ADC_TypeDef* adc, FunctionalState state); +void ADC_ExternalTrigInjectedConvertConfig(ADC_TypeDef* adc, EXTER_INJ_TRIG_TypeDef ADC_ExtInjTrigSource); +void ADC_InjectedConvCmd(ADC_TypeDef* adc, FunctionalState state); +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* adc, FunctionalState state); +void ADC_InjectedSequencerConfig(ADC_TypeDef* adc, u32 event, u32 sample_time); +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* adc, ADC_INJ_SEQ_LEN_TypeDef Length); +void ADC_InjectedSequencerChannelConfig(ADC_TypeDef* adc, ADC_INJ_SEQ_Channel_TypeDef off_addr, ADCCHANNEL_TypeDef channel); +u16 ADC_GetInjectedConversionValue(ADC_TypeDef* adc, ADC_INJ_SEQ_Channel_TypeDef off_addr); +u16 ADC_GetInjectedCurrentConvertedValue(ADC_TypeDef* adc); +void ADC_SetInjectedOffset(ADC_TypeDef* adc, ADC_INJ_SEQ_Channel_TypeDef off_addr, u16 value); +u16 ADC_GetChannelConvertedValue(ADC_TypeDef* adc, ADCCHANNEL_TypeDef channel); +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +#endif +//////////////////////////////////////////////////////////////////////////////// + diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_bkp.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_bkp.h new file mode 100644 index 000000000..26a93d4a0 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_bkp.h @@ -0,0 +1,130 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_bkp.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE BKP +/// FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#ifndef __HAL_BKP_H +#define __HAL_BKP_H + +// Files includes +#include "types.h" +#include "reg_bkp.h" + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup BKP_HAL +/// @brief BKP HAL modules +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup BKP_Exported_Types +/// @{ +//////////////////////////////////////////////////////////////////////////////// +/// @brief Data_Backup_Register +/// @anchor Data_Backup_Register + +typedef enum { + BKP_DR1 = 0x0010, + BKP_DR2 = 0x0014, + BKP_DR3 = 0x0018, + BKP_DR4 = 0x001C, + BKP_DR5 = 0x0020, + BKP_DR6 = 0x0024, + BKP_DR7 = 0x0028, + BKP_DR8 = 0x002C, + BKP_DR9 = 0x0030, + BKP_DR10 = 0x0034, + BKP_DR11 = 0x0038, + BKP_DR12 = 0x003C, + BKP_DR13 = 0x0040, + BKP_DR14 = 0x0044, + BKP_DR15 = 0x0048, + BKP_DR16 = 0x004C, + BKP_DR17 = 0x0050, + BKP_DR18 = 0x0054, + BKP_DR19 = 0x0058, + BKP_DR20 = 0x005C +} BKPDR_Typedef; + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Tamper_Pin_active_level +/// @anchor Tamper_Pin_active_level +typedef enum { + BKP_TamperPinLevel_High, ///< Tamper pin active on high level + BKP_TamperPinLevel_Low = BKP_CR_TPAL, ///< Tamper pin active on low level +} BKPTPAL_Typedef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief RTC_output_source_to_output_on_the_Tamper_pin +/// @anchor RTC_output_source_to_output_on_the_Tamper_pin +typedef enum { + BKP_RTCOutputSource_None = 0x0000, ///< No RTC output on the Tamper pin + BKP_RTCOutputSource_CalibClock = 0x0080, ///< Output the RTC clock with frequency divided by 64 on the Tamper pin + BKP_RTCOutputSource_Alarm = 0x0100, ///< Output the RTC Alarm pulse signal on the Tamper pin + BKP_RTCOutputSource_Second = 0x0300 ///< Output the RTC Second pulse signal on the Tamper pin +} BKPRTCOUTPUTSRC_Typedef; + + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup BKP_Exported_Variables +/// @{ +#ifdef _HAL_BKP_C_ +#define GLOBAL + +#else +#define GLOBAL extern +#endif + +#undef GLOBAL +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup BKP_Exported_Functions +/// @{ + +void BKP_WriteBackupRegister(BKPDR_Typedef bkp_dr, u16 data); +u16 BKP_ReadBackupRegister(BKPDR_Typedef bkp_dr); + +void BKP_DeInit(void); +void BKP_ClearFlag(void); +void BKP_ClearITPendingBit(void); +void BKP_TamperPinLevelConfig(BKPTPAL_Typedef tamper_pin_level); +void BKP_TamperPinCmd(FunctionalState state); +void BKP_ITConfig(FunctionalState state); +void BKP_RTCOutputConfig(BKPRTCOUTPUTSRC_Typedef rtc_output_source); +void BKP_SetRTCCalibrationValue(u8 calibration_value); + +ITStatus BKP_GetITStatus(void); +FlagStatus BKP_GetFlagStatus(void); +void exBKP_Init(void); +void exBKP_ImmWrite(BKPDR_Typedef bkp_dr, u16 data); +u16 exBKP_ImmRead(BKPDR_Typedef bkp_dr); +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +#endif // __HAL_BKP_H +//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_can.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_can.h new file mode 100644 index 000000000..b7e1d4b42 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_can.h @@ -0,0 +1,340 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_can.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE CAN +/// FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#ifndef __HAL_CAN_H +#define __HAL_CAN_H + +// Files includes +#include "types.h" +#include "reg_can.h" + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup CAN_HAL +/// @brief CAN HAL modules +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup CAN_Exported_Types +/// @{ + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief CAN_Initialization +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + CANINITFAILED = 0x00000000, ///< CAN initialization failed + CANINITOK = 0x00000001 ///< CAN initialization ok +} emCAN_INIT_Typedef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief CAN_sleep_constants +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + CANSLEEPFAILED = 0x00000000, ///< CAN did not enter the sleep mode + CANSLEEPOK = 0x00000001 ///< CAN entered the sleep mode +} emCAN_SLEEP_conts_Typedef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief CAN_wake_up_constants +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + CANWAKEUPFAILED = 0x00000000, ///< CAN did not leave the sleep mode + CANWAKEUPOK = 0x00000001 ///< CAN leaved the sleep mode +} emCAN_WAKE_conts_Typedef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief CAN_Mode +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + CAN_BASICMode = 0x00000000, + CAN_PELIMode = 0x00000080, + CAN_WorkMode = 0x00000080, + CAN_ResetMode = 0x00000001, + CAN_ListenOnlyMode = 0x00000002, + CAN_SeftTestMode = 0x00000004, + CAN_FilterMode_Singal = 0x00000008, + CAN_FilterMode_Double = 0x000000f7, + CAN_SleepMode = 0x00000010 +} emCAN_CAN_Mode_Typedef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief BASIC_CAN_interrupt +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + CAN_IT_RIE = CAN_CR_RIE, ///< Overflow interrupt enable + CAN_IT_TIE = CAN_CR_TIE, ///< Transmit interrupt enable + CAN_IT_EIE = CAN_CR_EIE, ///< Error interrupt enable + CAN_IT_OIE = CAN_CR_OIE ///< Receive interrupt enable +} emCAN_BASIC_IntEn_Typedef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief PELI_CAN_interrupt +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + CAN_IT_RI = CAN_IR_RI, ///< Overflow interrupt enable + CAN_IT_TI = CAN_IR_TI, ///< Transmit interrupt enable + CAN_IT_EI = CAN_IR_EI, ///< Error interrupt enable + CAN_IT_DOI = CAN_IR_DOI, ///< Receive interrupt enable + CAN_IT_WUI = 0x00001010, ///< Receive interrupt enable + CAN_IT_EPI = CAN_IR_EPI, ///< Receive interrupt enable + CAN_IT_ALI = CAN_IR_ALI, ///< Receive interrupt enable + CAN_IT_BEI = CAN_IR_BEI, ///< Receive interrupt enable + CAN_IT_ALL = 0xFFFF ///< Receive interrupt enable + +} emCAN_PELI_IntEn_Typedef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief CAN_Status +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + CAN_STATUS_RBS = CAN_SR_RBS, + CAN_STATUS_DOS = CAN_SR_DOS, + CAN_STATUS_TBS = CAN_SR_TBS, + CAN_STATUS_TCS = CAN_SR_TCS, + CAN_STATUS_RS = CAN_SR_RS, + CAN_STATUS_TS = CAN_SR_TS, + CAN_STATUS_ES = CAN_SR_ES, + CAN_STATUS_BS = CAN_SR_BS +} emCAN_Status_Typedef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief CAN_Command_register +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + CAN_TR = CAN_CMR_TR, ///< Transmission request + CAN_AT = CAN_CMR_AT, + CAN_RRB = CAN_CMR_RRB, + CAN_CDO = CAN_CMR_CDO +} emCAN_Command_Typedef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief CAN_Peli transmit frame definition +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + DataFrame = 0, ///< Data Frame + RemoteFrame = !DataFrame +} TransFrame; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief CAN_Basic init structure definition +//////////////////////////////////////////////////////////////////////////////// +typedef struct { + u8 SJW; + u8 BRP; + FlagStatus SAM; + u8 TESG2; + u8 TESG1; + FunctionalState GTS; + u8 CDCLK; + u8 CLOSE_OPEN_CLK; + u8 RXINTEN; + u8 CBP; +} CAN_Basic_InitTypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief CAN_Peli init structure definition +//////////////////////////////////////////////////////////////////////////////// +typedef struct { + u8 SJW; + u8 BRP; + FlagStatus SAM; + u8 TESG2; + u8 TESG1; + FunctionalState LOM; + FunctionalState STM; + FunctionalState SM; + FunctionalState SRR; + u32 EWLR; +} CAN_Peli_InitTypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief CAN_Basic filter init structure definition +//////////////////////////////////////////////////////////////////////////////// + +typedef struct { + u8 CAN_FilterId; ///< Specifies the filter identification number. This parameter can be a value between 0x00 and 0xFF. + u8 CAN_FilterMaskId; ///< Specifies the filter mask number or identification number, This parameter can be a value between + ///< 0x00 and 0xFF. +} CAN_Basic_FilterInitTypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief CAN_Peli filter init structure definition +//////////////////////////////////////////////////////////////////////////////// + +typedef struct { + u8 AFM; + u8 CAN_FilterId0; ///< Specifies the filter identification number, This parameter can be a value between 0x00 and 0xFF + u8 CAN_FilterId1; + u8 CAN_FilterId2; + u8 CAN_FilterId3; + u8 CAN_FilterMaskId0; ///< Specifies the filter mask number or identification number, This parameter can be a value between + ///< 0x00 and 0xFF + u8 CAN_FilterMaskId1; + u8 CAN_FilterMaskId2; + u8 CAN_FilterMaskId3; +} CAN_Peli_FilterInitTypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief CAN_Basic Tx message structure definition +//////////////////////////////////////////////////////////////////////////////// + +typedef struct { + u8 IDH; ///< Specifies the standard high identifier. This parameter can be a value between 0 to 0xFF. + u8 IDL; ///< Specifies the standard low identifier. This parameter can be a value between 0 to 0x7. + u8 RTR; ///< Specifies the type of frame for the message that will be transmitted. This parameter can be @TransFrame. + u8 DLC; ///< Specifies the length of the frame that will be transmitted. This parameter can be a value between 0 to 8. + u8 Data[8]; ///< Contains the data to be transmitted. It ranges from 0 to 0xFF. +} CanBasicTxMsg; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief CAN_Basic Rx message structure definition +//////////////////////////////////////////////////////////////////////////////// + +typedef struct { + u16 ID; ///< Specifies the standard identifier. This parameter can be a value between 0 to 0x7FF. + u8 RTR; ///< Specifies the type of frame for the received message. This parameter can be a value of @ref TransFrame + u8 DLC; ///< Specifies the length of the frame that will be received. This parameter can be a value between 0 to 8 + u8 Data[8]; ///< Contains the data to be received. It ranges from 0 to 0xFF. +} CanBasicRxMsg; + +/////////////////////////////////////////////////////////////////////////////// +/// @brief CAN_Peli_Tx message structure definition +/////////////////////////////////////////////////////////////////////////////// + +typedef struct { + u8 IDLL; ///< Specifies the extended identifier. + ///< This parameter can be a value between 0 to 0xFF. + u8 IDLH; + u8 IDHL; + u8 IDHH; + u8 FF; ///< Specifies the type of identifier for the message that will be transmitted. This parameter can be a value of @ref + ///< CAN_identifier_type + u8 RTR; ///< Specifies the type of frame for the message that will be transmitted. This parameter can be a value of @ref + ///< TransFrame. + u8 DLC; ///< Specifies the length of the frame that will be transmitted. This parameter can be a value between 0 to 8. + u8 Data[8]; ///< Contains the data to be transmitted. It ranges from 0 to 0xFF. +} CanPeliTxMsg; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief CAN Rx message structure definition +//////////////////////////////////////////////////////////////////////////////// +typedef struct { + u32 ID; ///< Specifies the extended identifier. This parameter can be a value between 0 to 0x1FFFFFFF. + u8 FF; ///< Specifies the type of identifier for the message that will be received. This parameter can be a value of @ref + ///< CAN_identifier_type. + u8 RTR; ///< Specifies the type of frame for the received message. This parameter can be a value of @ref TransFrame. + u8 DLC; ///< Specifies the length of the frame that will be received. This parameter can be a value between 0 to 8. + u8 Data[8]; ///< Contains the data to be received. It ranges from 0 to0xFF. +} CanPeliRxMsg; + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup CAN_Exported_Constants +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup parasmeter_of_CAN_transmission_register +/// @{ +#define CANTXFAILED (0x00U) ///< CAN transmission failed +#define CANTXOK (0x01U) ///< CAN transmission succeeded +#define CANTXPENDING (0x02U) ///< CAN transmission pending +#define CAN_NO_MB (0x04U) ///< CAN cell did not provide an empty mailbox +/// @} + + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup CAN_Exported_Variables +/// @{ +#ifdef _HAL_CAN_C_ + +#define GLOBAL +#else +#define GLOBAL extern +#endif + +#undef GLOBAL +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup CAN_Exported_Functions +/// @{ + +// Basic and Peli Work all need function --------------------------------------- + +void CAN_Mode_Cmd(CAN_TypeDef* can, u32 mode); +void CAN_ResetMode_Cmd(CAN_TypeDef* can, FunctionalState state); +void CAN_ClearDataOverflow(CAN_TypeDef* can); +void CAN_ClearITPendingBit(CAN_TypeDef* can); + +// Basic Work function --------------------------------------------------------- +void CAN_DeInit(CAN_TypeDef* can); +void CAN_FilterInit(CAN_Basic_FilterInitTypeDef* basic_filter_init_struct); +void CAN_StructInit(CAN_Basic_InitTypeDef* basic_init_struct); +void CAN_ITConfig(CAN_TypeDef* can, u32 it, FunctionalState state); +void CAN_CancelTransmit(CAN_TypeDef* can); +void CAN_FIFORelease(CAN_TypeDef* can); +void CAN_Receive(CAN_TypeDef* can, CanBasicRxMsg* basic_receive_message); + +u8 CAN_Transmit(CAN_TypeDef* can, CanBasicTxMsg* basic_transmit_message); +u8 CAN_Init(CAN_TypeDef* can, CAN_Basic_InitTypeDef* basic_init_struct); +u8 CAN_Sleep(CAN_TypeDef* can); +u8 CAN_WakeUp(CAN_TypeDef* can); + +FlagStatus CAN_GetFlagStatus(CAN_TypeDef* can, u32 flag); +ITStatus CAN_GetITStatus(CAN_TypeDef* can, u32 it); + +// Peli Work function ---------------------------------------------------------- +void CAN_Peli_SleepMode_Cmd(FunctionalState state); +void CAN_Peli_Init(CAN_Peli_InitTypeDef* init_struct); +void CAN_Peli_StructInit(CAN_Peli_InitTypeDef* peli_init_struct); +void CAN_Peli_FilterInit(CAN_Peli_FilterInitTypeDef* peli_filter_init_struct); +void CAN_Peli_FilterStructInit(CAN_Peli_FilterInitTypeDef* peli_filter_init_struct); +void CAN_Peli_Transmit(CanPeliTxMsg* peli_transmit_message); +void CAN_Peli_TransmitRepeat(CanPeliTxMsg* peli_transmit_message); +void CAN_Peli_Receive(CanPeliRxMsg* peli_receive_message); +void CAN_Peli_ITConfig(u32 it, FunctionalState state); +void CAN_AutoCfg_BaudParam(CAN_Peli_InitTypeDef* init_struct, u32 src_clk, u32 baud); + +u32 CAN_Peli_GetRxFIFOInfo(void); +u8 CAN_Peli_GetLastErrorCode(void); +u8 CAN_Peli_GetReceiveErrorCounter(void); +u8 CAN_Peli_GetLSBTransmitErrorCounter(void); + +ITStatus CAN_Peli_GetITStatus(u32 it); + + + +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +#endif +//////////////////////////////////////////////////////////////////////////////// + diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_comp.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_comp.h new file mode 100644 index 000000000..617318d53 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_comp.h @@ -0,0 +1,228 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_comp.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE COMP +/// FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

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+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#ifndef __HAL_COMP_H +#define __HAL_COMP_H + + +// Files includes +#include "reg_common.h" +#include "reg_comp.h" + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup COMP_HAL +/// @brief COMP HAL modules +/// @{ +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup COMP_Exported_Types +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @brief COMP_InvertingInput +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + COMP_InvertingInput_IO0 = COMP_CSR_INM_0, ///< INM0 as COMP inverting input + COMP_InvertingInput_IO1 = COMP_CSR_INM_1, ///< INM1 as COMP inverting input + COMP_InvertingInput_IO2 = COMP_CSR_INM_2, ///< INM2 as COMP inverting input + COMP_InvertingInput_CRV = COMP_CSR_INM_3, ///< INM3 as COMP inverting input + COMP_InvertingInput_IO3 = COMP_CSR_INM_3, ///< INM3 as COMP inverting input +} EM_COMP_InvertingInput; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief COMP_NonInvertingInput +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + COMP_NonInvertingInput_IO0 = COMP_CSR_INP_INP0, ///< INP0 as COMP non-inverting input + COMP_NonInvertingInput_IO1 = COMP_CSR_INP_INP1, ///< INP1 as COMP non-inverting input + COMP_NonInvertingInput_IO2 = COMP_CSR_INP_INP2, ///< INP2 as COMP non-inverting input + COMP_NonInvertingInput_IO3 = COMP_CSR_INP_INP3, ///< INP3 as COMP non-inverting input +} EM_COMP_NonInvertingInput; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief COMP_Output +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + COMP_Output_None = 0x00000000, ///< No output + COMP_Output_TIM1BKIN = COMP_CSR_OUT_TIM1_BRAKE, ///< Timer1 brake input + COMP_Output_TIM1OCREFCLR = COMP_CSR_OUT_TIM1_OCREFCLR, ///< Timer1 ocrefclear input + COMP_Output_TIM1IC1 = COMP_CSR_OUT_TIM1_CAPTURE1, ///< Timer1 input capture 1 + COMP_Output_TIM2IC4 = COMP_CSR_OUT_TIM2_CAPTURE4, ///< Timer2 input capture 4 + COMP_Output_TIM2OCREFCLR = COMP_CSR_OUT_TIM2_OCREFCLR, ///< Timer2 ocrefclear input + COMP_Output_TIM3IC1 = COMP_CSR_OUT_TIM3_CAPTURE1, ///< Timer3 input capture 1 + COMP_Output_TIM3OCREFCLR = COMP_CSR_OUT_TIM3_OCREFCLR ///< Timer3 ocrefclear input +} EM_COMP_Output; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief COMP_OutputPoloarity +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + COMP_NonInverted = 0x00000000, ///< COMP non-inverting output + COMP_OutputPol_NonInverted = 0x00000000, + COMP_Inverted = 0x00008000, ///< COMP inverting output + COMP_OutputPol_Inverted = 0x00008000 +} EM_COMP_OutputPol; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief COMP_Hysteresis +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + COMP_Hysteresis_No = COMP_CSR_HYST_0, ///< Hysteresis Voltage: 0mV + COMP_Hysteresis_Low = COMP_CSR_HYST_15, ///< Hysteresis Voltage: 15mV + COMP_Hysteresis_Medium = COMP_CSR_HYST_30, ///< Hysteresis Voltage: 30mV + COMP_Hysteresis_High = COMP_CSR_HYST_90 ///< Hysteresis Voltage: 90mV +} EM_COMP_Hysteresis; +typedef enum { + COMP_Filter_0_Period = COMP_CSR_OFLT_0, ///< filter is ((u32)0x00000000) + COMP_Filter_2_Period = COMP_CSR_OFLT_1, ///< filter is ((u32)0x00040000) + COMP_Filter_4_Period = COMP_CSR_OFLT_2, ///< filter is ((u32)0x00080000) + COMP_Filter_8_Period = COMP_CSR_OFLT_3, ///< filter is ((u32)0x000C0000) + COMP_Filter_16_Period = COMP_CSR_OFLT_4, ///< filter is ((u32)0x00100000) + COMP_Filter_32_Period = COMP_CSR_OFLT_5, ///< filter is ((u32)0x00140000) + COMP_Filter_64_Period = COMP_CSR_OFLT_6, ///< filter is ((u32)0x00180000) + COMP_Filter_128_Period = COMP_CSR_OFLT_7, ///< filter is ((u32)0x001C0000) +} EM_COMP_FILT; +//////////////////////////////////////////////////////////////////////////////// +/// @brief COMP_Mode +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + COMP_Mode_HighSpeed = COMP_CSR_MODE_HIGHRATE, ///< Comparator high rate mode + COMP_Mode_MediumSpeed = COMP_CSR_MODE_MEDIUMRATE, ///< Comparator medium rate mode + COMP_Mode_LowPower = COMP_CSR_MODE_LOWPOWER, ///< Comparator low power mode + COMP_Mode_UltraLowPower = COMP_CSR_MODE_LOWESTPOWER ///< Comparator lowest power mode +} EM_COMP_Mode; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief COMP_OutputLevel +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + COMP_OutputLevel_High = COMP_CSR_OUT, ///< High output + COMP_OutputLevel_Low = 0x00000000 ///< Low output +} EM_COMP_OutputLevel; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief COMP Init structure definition +//////////////////////////////////////////////////////////////////////////////// +typedef struct { + union { + u32 COMP_InvertingInput; + u32 Invert; ///< Selects the inverting input of the comparator. + }; + union { + u32 COMP_NonInvertingInput; + u32 NonInvert; ///< Selects the non inverting input of the comparator. + }; + union { + u32 COMP_Output; + u32 Output; ///< Selects the output redirection of the comparator. + u32 BlankingSrce; ///< Selects the output blanking source of the comparator. + }; + union { + u32 COMP_OutputPol; + u32 OutputPol; ///< Selects the output polarity of the comparator. + }; + union { + u32 COMP_Hysteresis; + u32 Hysteresis; ///< Selects the hysteresis voltage of the comparator. + }; + union { + u32 COMP_Mode; + u32 Mode; ///< Selects the operating mode of the comparator and allows + }; + union { + u32 COMP_Filter; + u32 OFLT; ///< to adjust the speed/consumption. + }; +} COMP_InitTypeDef; + + + +typedef struct { + + FunctionalState COMP_Poll_En; ///< Selects the inverting input of the comparator. + + u32 COMP_Poll_Ch; ///< Selects the non inverting input of the comparator. + u32 COMP_Poll_Fixn; ///< Selects the output redirection of the comparator. + u32 COMP_Poll_Period; ///< Selects the output polarity of the comparator. + u32 COMP_Poll_Pout; ///< Selects the hysteresis voltage of the comparator. + +} COMP_POLL_InitTypeDef; +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup COMP_Exported_Constants +/// @{ +//////////////////////////////////////////////////////////////////////////////// +/// @brief COMP Init structure definition +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + COMP1 = (0x00000C), ///< Select comparator 1 + COMP2 = (0x000010), ///< Select comparator 2 +} COMP_Selection_TypeDef; + +#define COMP_BlankingSrce_None ((u32)0x00000000) +#define COMP_CSR_CLEAR_MASK ((u32)0x00000003) + +#define COMP_CSR_COMPSW1 ((u32)0x00000002) + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +///@defgroup COMP_Exported_Variables +/// @{ +#ifdef _HAL_COMP_C_ + +#define GLOBAL +#else +#define GLOBAL extern +#endif + +#undef GLOBAL +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup COMP_Exported_Functions +/// @{ + + +void COMP_DeInit(COMP_Selection_TypeDef selection); +void COMP_Init(COMP_Selection_TypeDef selection, COMP_InitTypeDef* init_struct); +void COMP_StructInit(COMP_InitTypeDef* init_struct); +void COMP_Cmd(COMP_Selection_TypeDef selection, FunctionalState state); +void COMP_SwitchCmd(COMP_Selection_TypeDef selection, FunctionalState state); +void COMP_LockConfig(COMP_Selection_TypeDef selection); + +u32 COMP_GetOutputLevel(COMP_Selection_TypeDef selection); + +void COMP_SetCrv(u8 crv_select, u8 crv_level); +#define SET_COMP_CRV COMP_SetCrv + + +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +#endif //__HAL_COMP_H +//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_conf.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_conf.h new file mode 100644 index 000000000..758c7a618 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_conf.h @@ -0,0 +1,62 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_conf.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE GENERIC MICROCONTROLLER +/// FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

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+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#ifndef __HAL_CONF_H +#define __HAL_CONF_H +// Files includes +#include "mm32_device.h" + +#include "hal_adc.h" +#include "hal_bkp.h" +#include "hal_can.h" +#include "hal_comp.h" +#include "hal_crc.h" +#include "hal_crs.h" +#include "hal_dac.h" +#include "hal_dbg.h" +#include "hal_dma.h" +#include "hal_exti.h" +#include "hal_flash.h" +#include "hal_gpio.h" +#include "hal_i2c.h" +#include "hal_iwdg.h" +#include "hal_misc.h" +#include "hal_pwr.h" +#include "hal_rcc.h" +#include "hal_rtc.h" +#include "hal_spi.h" +#include "hal_syscfg.h" +#include "hal_tim.h" +#include "hal_uart.h" +#include "hal_uid.h" +#include "hal_wwdg.h" +#include "hal_redefine.h" +#include "hal_eth.h" +#include "hal_eth_conf.h" +#include "hal_fsmc.h" + +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +#endif //__HAL_CONF_H +//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crc.h new file mode 100644 index 000000000..f5f3d6054 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crc.h @@ -0,0 +1,84 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_crc.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE CRC +/// FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

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+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#ifndef __HAL_CRC_H +#define __HAL_CRC_H + +// Files includes +#include "types.h" +#include "reg_common.h" +#include "reg_crc.h" + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup CRC_HAL +/// @brief CRC HAL modules +/// @{ + + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup CRC_Exported_Types +/// @{ + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup CRC_Exported_Constants +/// @{ + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup CRC_Exported_Variables +/// @{ +#ifdef _HAL_CRC_C_ +#define GLOBAL + +#else +#define GLOBAL extern +#endif + +#undef GLOBAL +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup CRC_Exported_Functions +/// @{ +void CRC_ResetDR(void); +void CRC_SetIDRegister(u8 id_value); + +u32 CRC_CalcCRC(u32 data); +u32 CRC_CalcBlockCRC(u32* buffer, u32 length); +u32 CRC_GetCRC(void); + +u8 CRC_GetIDRegister(void); + +/// @} + +/// @} + +/// @} + + +//////////////////////////////////////////////////////////////////////////////// +#endif // __HAL_CRC_H +//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crs.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crs.h new file mode 100644 index 000000000..d3c2a6cc5 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crs.h @@ -0,0 +1,46 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_crs.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE CRS +/// FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

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+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#ifndef __HAL_CRS_H +#define __HAL_CRS_H + + +// Files includes +#include "types.h" +#include "reg_crs.h" + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup CRS_HAL +/// @brief CRS HAL modules +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup GPIO_Exported_Types +/// @{ + + + +//////////////////////////////////////////////////////////////////////////////// +#endif +//////////////////////////////////////////////////////////////////////////////// + diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dac.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dac.h new file mode 100644 index 000000000..e538b20b7 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dac.h @@ -0,0 +1,166 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_dac.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE DAC +/// FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#ifndef __HAL_DAC_H +#define __HAL_DAC_H + +// Files includes +#include "types.h" +#include "reg_dac.h" + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup DAC_HAL +/// @brief DAC HAL modules +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup DAC_Exported_Types +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @brief DAC_Trigger_Selection +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + DAC_Trigger_None = 0x00000000, + DAC_Trigger_T1_TRIG = (DAC_CR_TSEL1_TIM1_TRIG | DAC_CR_TEN1), + DAC_Trigger_T3_TRIG = (DAC_CR_TSEL1_TIM3_TRIG | DAC_CR_TEN1), + DAC_Trigger_T2_TRIG = (DAC_CR_TSEL1_TIM2_TRIG | DAC_CR_TEN1), + DAC_Trigger_T4_TRIG = (DAC_CR_TSEL1_TIM4_TRIG | DAC_CR_TEN1), + DAC_Trigger_Ext_IT9 = (DAC_CR_TSEL1_EXTI9 | DAC_CR_TEN1), + DAC_Trigger_Software = (DAC_CR_TSEL1_SOFTWARE) +} emDACTRIG_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief DAC_Wave_Generation +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + DAC_WaveGeneration_None = DAC_CR_WAVE1_NONE, + DAC_WaveGeneration_Noise = DAC_CR_WAVE1_NOISE, + DAC_WaveGeneration_Triangle = DAC_CR_WAVE1_TRIANGLE +} emDACWAVE_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief DAC_Mask_Amplitude +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + DAC_TriangleAmplitude_1 = DAC_CR_MAMP1_1, + DAC_TriangleAmplitude_3 = DAC_CR_MAMP1_3, + DAC_TriangleAmplitude_7 = DAC_CR_MAMP1_7, + DAC_TriangleAmplitude_15 = DAC_CR_MAMP1_15, + DAC_TriangleAmplitude_31 = DAC_CR_MAMP1_31, + DAC_TriangleAmplitude_63 = DAC_CR_MAMP1_63, + DAC_TriangleAmplitude_127 = DAC_CR_MAMP1_127, + DAC_TriangleAmplitude_255 = DAC_CR_MAMP1_255, + DAC_TriangleAmplitude_511 = DAC_CR_MAMP1_511, + DAC_TriangleAmplitude_1023 = DAC_CR_MAMP1_1023, + DAC_TriangleAmplitude_2047 = DAC_CR_MAMP1_2047, + DAC_TriangleAmplitude_4095 = DAC_CR_MAMP1_4095 +} emDACAMP_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief channel +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + DAC_Channel_1, ///< DAC channel 1 + DAC_Channel_2 = (u32)0x00000010 ///< DAC Channel 2 +} emDACCH_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief DAC_Data_Alignement +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + DAC_Align_12b_R = ((u32)0x00000000), + DAC_Align_12b_L = ((u32)0x00000004), + DAC_Align_8b_R = ((u32)0x00000008) +} emDACALIGN_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief DAC_Output_Buffer +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + DAC_OutputBuffer_Enable = 0x00000000, ///< DAC output buffer enable + DAC_OutputBuffer_Disable = DAC_CR_BOFF1 ///< DAC output buffer disable +} emDACBOFF_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief DAC Init structure definition +//////////////////////////////////////////////////////////////////////////////// +typedef struct { + emDACTRIG_TypeDef DAC_Trigger; + emDACWAVE_TypeDef DAC_WaveGeneration; + emDACAMP_TypeDef DAC_LFSRUnmask_TriangleAmplitude; + emDACBOFF_TypeDef DAC_OutputBuffer; +} DAC_InitTypeDef; + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup DAC_Exported_Constants +/// @{ +#define DHR12R1_Offset ((u32)0x00000008) +#define DHR12R2_Offset ((u32)0x00000014) +#define DHR12RD_Offset ((u32)0x00000020) +#define DOR_Offset ((u32)0x0000002C) + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup DAC_Exported_Variables +/// @{ +#ifdef _HAL_DAC_C_ +#define GLOBAL + +#else +#define GLOBAL extern +#endif + +#undef GLOBAL +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup DAC_Exported_Functions +/// @{ +void DAC_DeInit(void); +void DAC_Init(emDACCH_TypeDef channel, DAC_InitTypeDef* init_struct); +void DAC_StructInit(DAC_InitTypeDef* init_struct); +void DAC_Cmd(emDACCH_TypeDef channel, FunctionalState state); +void DAC_DMACmd(emDACCH_TypeDef channel, FunctionalState state); +void DAC_SoftwareTriggerCmd(emDACCH_TypeDef channel, FunctionalState state); +void DAC_DualSoftwareTriggerCmd(FunctionalState state); +void DAC_WaveGenerationCmd(emDACCH_TypeDef channel, emDACWAVE_TypeDef wave, FunctionalState state); +void DAC_SetChannel1Data(emDACALIGN_TypeDef alignement, u16 data); +void DAC_SetChannel2Data(emDACALIGN_TypeDef alignement, u16 data); +void DAC_SetDualChannelData(emDACALIGN_TypeDef alignement, u16 data2, u16 data1); + +u16 DAC_GetDataOutputValue(emDACCH_TypeDef channel); + +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +#endif // __HAL_DAC_H +//////////////////////////////////////////////////////////////////////////////// + diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dbg.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dbg.h new file mode 100644 index 000000000..0e9b41d1e --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dbg.h @@ -0,0 +1,72 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_dbg.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE DBG +/// FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#ifndef __HAL_DBG_H +#define __HAL_DBG_H + +// Files includes +#include "types.h" +#include "reg_common.h" +#include "reg_dbg.h" + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup DBG_HAL +/// @brief DBG HAL modules +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup DBG_Exported_Types +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup DIV_Exported_Variables +/// @{ +#ifdef _HAL_DBG_C_ + +#define GLOBAL +#else +#define GLOBAL extern +#endif + +#undef GLOBAL +/// @} + + + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup DBG_Exported_Functions +/// @{ +void DBGMCU_Configure(u32 periph, FunctionalState state); + +/// @} + + +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +#endif // __HAL_DBG_H +//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_device.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_device.h new file mode 100644 index 000000000..ff2133702 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_device.h @@ -0,0 +1,41 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_device.h +/// @author AE team +/// @brief CMSIS Cortex-M Peripheral Access Layer for MindMotion +/// microcontroller devices +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + + +// Define to prevent recursive inclusion +#ifndef __HAL_DEVICE_H +#define __HAL_DEVICE_H + + + + + +#include "mm32_device.h" + + +#endif // __HAL_device_H + +/// @} + + +/// @} + +/// @} + + + diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dma.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dma.h new file mode 100644 index 000000000..892e750b5 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dma.h @@ -0,0 +1,306 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_dma.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE DMA +/// FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#ifndef __HAL_DMA_H +#define __HAL_DMA_H +// Files includes +#include "types.h" +#include "reg_common.h" +#include "reg_dma.h" + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup DMA_HAL +/// @brief DMA HAL modules +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup DMA_Exported_Types +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @brief DMA data transfer direction Enumerate definition +/// @anchor DMA_data_transfer_direction +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + DMA_DIR_PeripheralSRC = 0U, + DMA_DIR_PeripheralDST = DMA_CCR_DIR // 0x00000010U +} DMA_data_transfer_direction_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief DMA peripheral incremented mode Enumerate definition +/// @anchor DMA_peripheral_incremented_mode +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + DMA_PeripheralInc_Disable = 0U, + DMA_PeripheralInc_Enable = DMA_CCR_PINC // 0x00000040U +} DMA_peripheral_incremented_mode_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief DMA memory incremented mode Enumerate definition +/// @anchor DMA_memory_incremented_mode +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + DMA_MemoryInc_Disable = 0U, + DMA_MemoryInc_Enable = DMA_CCR_MINC // 0x00000080U +} DMA_memory_incremented_mode_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief DMA peripheral data size Enumerate definition +/// @anchor DMA_peripheral_data_size +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + DMA_PeripheralDataSize_Byte = 0U, + DMA_PeripheralDataSize_HalfWord = DMA_CCR_PSIZE_HALFWORD, + DMA_PeripheralDataSize_Word = DMA_CCR_PSIZE_WORD +} DMA_peripheral_data_size_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief DMA memory data size Enumerate definition +/// @anchor DMA_memory_data_size +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + DMA_MemoryDataSize_Byte = 0U, + DMA_MemoryDataSize_HalfWord = DMA_CCR_MSIZE_HALFWORD, // 0x00000400U + DMA_MemoryDataSize_Word = DMA_CCR_MSIZE_WORD // 0x00000800U +} DMA_memory_data_size_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief DMA circular normal mode Enumerate definition +/// @anchor DMA_circular_normal_mode +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + DMA_Mode_Normal = 0U, + DMA_Mode_Circular = DMA_CCR_CIRC // 0x00000020U +} DMA_circular_normal_mode_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief DMA priority level Enumerate definition +/// @anchor DMA_priority_level +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + DMA_Priority_Low = 0U, + DMA_Priority_Medium = DMA_CCR_PL_Medium, // 0x00001000U + DMA_Priority_High = DMA_CCR_PL_High, // 0x00002000U + DMA_Priority_VeryHigh = DMA_CCR_PL_VeryHigh // 0x00003000U +} DMA_priority_level_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief DMA memory to memory Enumerate definition +/// @anchor DMA_memory_to_memory +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + DMA_M2M_Disable = 0U, + DMA_M2M_Enable = DMA_CCR_M2M // 0x00004000U +} DMA_memory_to_memory_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief DMA auto reload Enumerate definition +/// @anchor DMA_auto_reload +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + DMA_Auto_Reload_Disable = 0U, // + DMA_Auto_Reload_Enable = DMA_CCR_ARE +} DMA_auto_reload_TypeDef; +/// @brief DMA Interrupt Setting Enumerate definition +/// @anchor DMA_auto_reload +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + DMA_IT_TC = DMA_CCR_TCIE, //(0x00000002UL), + DMA_IT_HT = DMA_CCR_HTIE, //(0x00000004UL), + DMA_IT_TE = DMA_CCR_TEIE, //(0x00000008UL), +} DMA_Interrupt_EN_TypeDef; + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief DMA interrupts Enumerate definition +/// @anchor DMA_Flags +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + DMAx_IT_GLy = (0x00000001UL), + DMAx_IT_TCy = (0x00000002UL), + DMAx_IT_HTy = (0x00000004UL), + DMAx_IT_TEy = (0x00000008UL), + DMA1_IT_GL1 = (0x00000001UL), + DMA1_IT_TC1 = (0x00000002UL), + DMA1_IT_HT1 = (0x00000004UL), + DMA1_IT_TE1 = (0x00000008UL), + DMA1_IT_GL2 = (0x00000010UL), + DMA1_IT_TC2 = (0x00000020UL), + DMA1_IT_HT2 = (0x00000040UL), + DMA1_IT_TE2 = (0x00000080UL), + DMA1_IT_GL3 = (0x00000100UL), + DMA1_IT_TC3 = (0x00000200UL), + DMA1_IT_HT3 = (0x00000400UL), + DMA1_IT_TE3 = (0x00000800UL), + DMA1_IT_GL4 = (0x00001000UL), + DMA1_IT_TC4 = (0x00002000UL), + DMA1_IT_HT4 = (0x00004000UL), + DMA1_IT_TE4 = (0x00008000UL), + DMA1_IT_GL5 = (0x00010000UL), + DMA1_IT_TC5 = (0x00020000UL), + DMA1_IT_HT5 = (0x00040000UL), + DMA1_IT_TE5 = (0x00080000UL), + DMA1_IT_GL6 = (0x00100000UL), + DMA1_IT_TC6 = (0x00200000UL), + DMA1_IT_HT6 = (0x00400000UL), + DMA1_IT_TE6 = (0x00800000UL), + DMA1_IT_GL7 = (0x01000000UL), + DMA1_IT_TC7 = (0x02000000UL), + DMA1_IT_HT7 = (0x04000000UL), + DMA1_IT_TE7 = (0x08000000UL), + DMA2_IT_GL1 = (0x10000001UL), + DMA2_IT_TC1 = (0x10000002UL), + DMA2_IT_HT1 = (0x10000004UL), + DMA2_IT_TE1 = (0x10000008UL), + DMA2_IT_GL2 = (0x10000010UL), + DMA2_IT_TC2 = (0x10000020UL), + DMA2_IT_HT2 = (0x10000040UL), + DMA2_IT_TE2 = (0x10000080UL), + DMA2_IT_GL3 = (0x10000100UL), + DMA2_IT_TC3 = (0x10000200UL), + DMA2_IT_HT3 = (0x10000400UL), + DMA2_IT_TE3 = (0x10000800UL), + DMA2_IT_GL4 = (0x10001000UL), + DMA2_IT_TC4 = (0x10002000UL), + DMA2_IT_HT4 = (0x10004000UL), + DMA2_IT_TE4 = (0x10008000UL), + DMA2_IT_GL5 = (0x10010000UL), + DMA2_IT_TC5 = (0x10020000UL), + DMA2_IT_HT5 = (0x10040000UL), + DMA2_IT_TE5 = (0x10080000UL), +} DMA_Interrupts_TypeDef; +typedef enum { + DMAx_FLAG_GLy = (0x00000001UL), + DMAx_FLAG_TCy = (0x00000002UL), + DMAx_FLAG_HTy = (0x00000004UL), + DMAx_FLAG_TEy = (0x00000008UL), + DMA1_FLAG_GL1 = (0x00000001UL), + DMA1_FLAG_TC1 = (0x00000002UL), + DMA1_FLAG_HT1 = (0x00000004UL), + DMA1_FLAG_TE1 = (0x00000008UL), + DMA1_FLAG_GL2 = (0x00000010UL), + DMA1_FLAG_TC2 = (0x00000020UL), + DMA1_FLAG_HT2 = (0x00000040UL), + DMA1_FLAG_TE2 = (0x00000080UL), + DMA1_FLAG_GL3 = (0x00000100UL), + DMA1_FLAG_TC3 = (0x00000200UL), + DMA1_FLAG_HT3 = (0x00000400UL), + DMA1_FLAG_TE3 = (0x00000800UL), + DMA1_FLAG_GL4 = (0x00001000UL), + DMA1_FLAG_TC4 = (0x00002000UL), + DMA1_FLAG_HT4 = (0x00004000UL), + DMA1_FLAG_TE4 = (0x00008000UL), + DMA1_FLAG_GL5 = (0x00010000UL), + DMA1_FLAG_TC5 = (0x00020000UL), + DMA1_FLAG_HT5 = (0x00040000UL), + DMA1_FLAG_TE5 = (0x00080000UL), + DMA1_FLAG_GL6 = (0x00100000UL), + DMA1_FLAG_TC6 = (0x00200000UL), + DMA1_FLAG_HT6 = (0x00400000UL), + DMA1_FLAG_TE6 = (0x00800000UL), + DMA1_FLAG_GL7 = (0x01000000UL), + DMA1_FLAG_TC7 = (0x02000000UL), + DMA1_FLAG_HT7 = (0x04000000UL), + DMA1_FLAG_TE7 = (0x08000000UL), + DMA2_FLAG_GL1 = (0x10000001UL), + DMA2_FLAG_TC1 = (0x10000002UL), + DMA2_FLAG_HT1 = (0x10000004UL), + DMA2_FLAG_TE1 = (0x10000008UL), + DMA2_FLAG_GL2 = (0x10000010UL), + DMA2_FLAG_TC2 = (0x10000020UL), + DMA2_FLAG_HT2 = (0x10000040UL), + DMA2_FLAG_TE2 = (0x10000080UL), + DMA2_FLAG_GL3 = (0x10000100UL), + DMA2_FLAG_TC3 = (0x10000200UL), + DMA2_FLAG_HT3 = (0x10000400UL), + DMA2_FLAG_TE3 = (0x10000800UL), + DMA2_FLAG_GL4 = (0x10001000UL), + DMA2_FLAG_TC4 = (0x10002000UL), + DMA2_FLAG_HT4 = (0x10004000UL), + DMA2_FLAG_TE4 = (0x10008000UL), + DMA2_FLAG_GL5 = (0x10010000UL), + DMA2_FLAG_TC5 = (0x10020000UL), + DMA2_FLAG_HT5 = (0x10040000UL), + DMA2_FLAG_TE5 = (0x10080000UL), +} DMA_Flags_TypeDef; +//////////////////////////////////////////////////////////////////////////////// +/// @brief DMA Init structure definition +//////////////////////////////////////////////////////////////////////////////// +typedef struct { + u32 DMA_PeripheralBaseAddr; ///< the peripheral base address for DMA Channeln. + u32 DMA_MemoryBaseAddr; ///< the memory base address for DMA Channeln. + DMA_data_transfer_direction_TypeDef DMA_DIR; ///< the peripheral is the source or destination. + u32 DMA_BufferSize; ///< Specifies the buffer size, in data unit, of the Buffer size + DMA_peripheral_incremented_mode_TypeDef DMA_PeripheralInc; ///< Specifies whether the Peripheral address increment or not + DMA_memory_incremented_mode_TypeDef DMA_MemoryInc; ///< Specifies whether the memory address register is increment or not + DMA_peripheral_data_size_TypeDef DMA_PeripheralDataSize; ///< Specifies the Peripheral data width. + DMA_memory_data_size_TypeDef DMA_MemoryDataSize; ///< Specifies the Memory data width. + DMA_circular_normal_mode_TypeDef DMA_Mode; ///< Specifies the operation mode of the DMA Channeln circular or normal mode. + DMA_priority_level_TypeDef DMA_Priority; ///< Specifies the software priority for the DMA priority level + DMA_memory_to_memory_TypeDef DMA_M2M; ///< Specifies if the DMA Channeln will be used in memory-to-memory transfer. + DMA_auto_reload_TypeDef DMA_Auto_reload; ///< Specifies if the DMA Channeln will auto reload the CNDTR register +} DMA_InitTypeDef; + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup DMA_Exported_Variables +/// @{ +#ifdef _HAL_DMA_C_ + +#define GLOBAL +#else +#define GLOBAL extern +#endif + +#undef GLOBAL +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup DMA_Exported_Functions +/// @{ + +void DMA_DeInit(DMA_Channel_TypeDef* channel); +void DMA_Init(DMA_Channel_TypeDef* channel, DMA_InitTypeDef* init_struct); +void DMA_StructInit(DMA_InitTypeDef* init_struct); +void DMA_Cmd(DMA_Channel_TypeDef* channel, FunctionalState state); +void DMA_ITConfig(DMA_Channel_TypeDef* channel, DMA_Interrupt_EN_TypeDef it, FunctionalState state); +void DMA_ClearFlag(DMA_Flags_TypeDef flag); +void DMA_ClearITPendingBit(DMA_Interrupts_TypeDef it); +void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* channel, u16 length); +u16 DMA_GetCurrDataCounter(DMA_Channel_TypeDef* channel); +FlagStatus DMA_GetFlagStatus(DMA_Flags_TypeDef flag); +ITStatus DMA_GetITStatus(DMA_Interrupts_TypeDef it); + +void exDMA_SetPeripheralAddress(DMA_Channel_TypeDef* channel, u32 addr); +void exDMA_SetTransmitLen(DMA_Channel_TypeDef* channel, u16 len); +void exDMA_SetMemoryAddress(DMA_Channel_TypeDef* channel, u32 addr); + +/// @} + +/// @} + +/// @} +//////////////////////////////////////////////////////////////////////////////// +#endif //__HAL_DMA_H +//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_eth.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_eth.h new file mode 100644 index 000000000..4000bbaa5 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_eth.h @@ -0,0 +1,729 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file HAL_eth.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE HAL_eth.h EXAMPLES. +/// //////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +#ifndef __HAL_ETH_H +#define __HAL_ETH_H + +// Files includes +#include "types.h" +#include "mm32_device.h" +#include "HAL_eth_conf.h" +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup ETH_HAL +/// @brief ETH HAL modules +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup ETH_Exported_Types +/// @{ + + +//////////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////// +// ETH | Header | Extra | VLAN tag | Payload | CRC | +// Size | 14 | 2 | 4 | 46 ~ 1500 | 4 | +#define ETH_MAX_PACKET_SIZE 1524 +#define ETH_HEADER 14 ///< MAC Dest Addr 6 byte + MAC Src Addr 6 byte + Lenth/Type 2 byte +#define ETH_EXTRA 2 +#define VLAN_TAG 4 +#define ETH_PAYLOAD_MIN 46 +#define ETH_PAYLOAD_MAX 1500 +#define JUMBO_FRAME_PAYLOAD 9000 + +#ifndef ETH_RX_BUF_SIZE +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE +#endif + +#ifndef ETH_RX_BUF_NUM +#define ETH_RX_BUF_NUM 4 +#endif + +#ifndef ETH_TX_BUF_SIZE +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE +#endif + +#ifndef ETH_TX_BUF_NUM +#define ETH_TX_BUF_NUM 4 +#endif + +#define ETH_DMA_RDES_FL_Pos 16 ///< Ethernet DMA Received Frame Length Position + +#define ETH_WAKEUP_REGISTER_LENGTH 8 ///< ETHERNET Remote Wake-up frame register length + +#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17 ///< ETHERNET Missed frames counter Shift + +#define ETH_DMA_TDES_COLLISION_COUNTSHIFT 3 ///< ETHERNET DMA Tx descriptors Collision Count Shift +#define ETH_DMA_TDES_BUFFER2_SIZESHIFT 11 ///< ETHERNET DMA Tx descriptors Buffer2 Size Shift + +#define ETH_DMA_RDES_FRAME_LENGTHSHIFT 16 ///< ETHERNET DMA Rx descriptors Frame Length Shift +#define ETH_DMA_RDES_BUFFER2_SIZESHIFT 11 ///< ETHERNET DMA Rx descriptors Buffer2 Size Shift + +///< ETHERNET errors +#define ETH_ERROR ((u32)0) +#define ETH_SUCCESS ((u32)1) + + +#ifdef _HAL_ETH_C_ +#define GLOBAL + +#else +#define GLOBAL extern +#endif + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH Init Structure Definition +//////////////////////////////////////////////////////////////////////////////// +typedef struct { + __IO u32 ETH_AutoNegotiation; + __IO u32 ETH_Watchdog; + __IO u32 ETH_Jabber; + __IO u32 ETH_InterFrameGap; + __IO u32 ETH_CarrierSense; + __IO u32 ETH_Speed; + __IO u32 ETH_ReceiveOwn; + __IO u32 ETH_LoopbackMode; + __IO u32 ETH_Mode; + __IO u32 ETH_ChecksumOffload; + __IO u32 ETH_RetryTransmission; + __IO u32 ETH_AutomaticPadCRCStrip; + __IO u32 ETH_BackOffLimit; + __IO u32 ETH_DeferralCheck; + __IO u32 ETH_ReceiveAll; + __IO u32 ETH_SourceAddrFilter; + __IO u32 ETH_PassControlFrames; + __IO u32 ETH_BroadcastFramesReception; + __IO u32 ETH_DestinationAddrFilter; + __IO u32 ETH_PromiscuousMode; + __IO u32 ETH_MulticastFramesFilter; + __IO u32 ETH_UnicastFramesFilter; + __IO u32 ETH_HashTableHigh; + __IO u32 ETH_HashTableLow; + __IO u32 ETH_PauseTime; + __IO u32 ETH_ZeroQuantaPause; + __IO u32 ETH_PauseLowThreshold; + __IO u32 ETH_UnicastPauseFrameDetect; + __IO u32 ETH_ReceiveFlowControl; + __IO u32 ETH_TransmitFlowControl; + __IO u32 ETH_VLANTagComparison; + __IO u32 ETH_VLANTagIdentifier; + __IO u32 ETH_DropTCPIPChecksumErrorFrame; + __IO u32 ETH_ReceiveStoreForward; + __IO u32 ETH_FlushReceivedFrame; + __IO u32 ETH_TransmitStoreForward; + __IO u32 ETH_TransmitThresholdControl; + __IO u32 ETH_ForwardErrorFrames; + __IO u32 ETH_ForwardUndersizedGoodFrames; + __IO u32 ETH_ReceiveThresholdControl; + __IO u32 ETH_SecondFrameOperate; + __IO u32 ETH_AddressAlignedBeats; + __IO u32 ETH_FixedBurst; + __IO u32 ETH_RxDMABurstLength; + __IO u32 ETH_TxDMABurstLength; + __IO u32 ETH_DescriptorSkipLength; + __IO u32 ETH_DMAArbitration; +} ETH_InitTypeDef; + +typedef struct { + __IO u32 CS; ///< Control and Status + __IO u32 BL; ///< Buffer1, Buffer2 lengths + __IO u32 BUF1ADDR; ///< Buffer1 address pointer + __IO u32 BUF2NDADDR; ///< Buffer2 or next descriptor address pointer + +#ifdef USE_ENHANCED_DMA_DESCRIPTORS ///< Enhanced ETHERNET DMA PTP Descriptors + __IO u32 ExtendedStatus; ///< Extended status for PTP receive descriptor + __IO u32 Reserved1; ///< Reserved + __IO u32 TimeStampLow; ///< Time Stamp Low value for transmit and receive + __IO u32 TimeStampHigh; ///< Time Stamp High value for transmit and receive +#endif +} ETH_DMADESCTypeDef; + +typedef struct { + __IO u32 len; + __IO u32 buf; + __IO ETH_DMADESCTypeDef* ptrDesc; +} FrameTypeDef; + +typedef struct { + __IO ETH_DMADESCTypeDef* ptrFS_Rx_Desc; ///< First Segment Rx Desc + __IO ETH_DMADESCTypeDef* ptrLS_Rx_Desc; ///< Last Segment Rx Desc + __IO u32 cnt; ///< Segment count +} ETH_DMA_Rx_Frame_infos; + + + +#define ETH_DMA_TDES_OWN ((u32)0x80000000) ///< OWN bit: descriptor is owned by DMA engine +#define ETH_DMA_TDES_ES ((u32)0x00008000) ///< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT +#define ETH_DMA_TDES_JT ((u32)0x00004000) ///< Jabber Timeout +#define ETH_DMA_TDES_FF ((u32)0x00002000) ///< Frame Flushed: DMA/MTL flushed the frame due to SW flush +#define ETH_DMA_TDES_LCA ((u32)0x00000800) ///< Loss of Carrier: carrier lost during transmission +#define ETH_DMA_TDES_NC ((u32)0x00000400) ///< No Carrier: no carrier signal from the transceiver +#define ETH_DMA_TDES_LCO ((u32)0x00000200) ///< Late Collision: transmission aborted due to collision +#define ETH_DMA_TDES_EC ((u32)0x00000100) ///< Excessive Collision: transmission aborted after 16 collisions +#define ETH_DMA_TDES_VF ((u32)0x00000080) ///< VLAN Frame +#define ETH_DMA_TDES_CC ((u32)0x00000078) ///< Collision Count +#define ETH_DMA_TDES_ED ((u32)0x00000004) ///< Excessive Deferral +#define ETH_DMA_TDES_UF ((u32)0x00000002) ///< Underflow Error: late data arrival from the memory +#define ETH_DMA_TDES_DB ((u32)0x00000001) ///< Deferred Bit + +#define ETH_DMA_TDES_IC ((u32)0x80000000) ///< Interrupt on Completion +#define ETH_DMA_TDES_LS ((u32)0x40000000) ///< Last Segment +#define ETH_DMA_TDES_FS ((u32)0x20000000) ///< First Segment +#define ETH_DMA_TDES_DC ((u32)0x04000000) ///< Disable CRC +#define ETH_DMA_TDES_TER ((u32)0x02000000) ///< Transmit end of ring +#define ETH_DMA_TDES_TCH ((u32)0x01000000) ///< Second Address Chained +#define ETH_DMA_TDES_DP ((u32)0x00800000) ///< Disable Padding +#define ETH_DMA_TDES_TBS2 ((u32)0x003FF800) ///< Transmit Buffer 2 Size +#define ETH_DMA_TDES_TBS1 ((u32)0x000007FF) ///< Transmit Buffer 1 Size + +#define ETH_DMA_TDES_B1AP ((u32)0xFFFFFFFF) ///< Buffer 1 Address Pointer + +#define ETH_DMA_TDES_B2AP ((u32)0xFFFFFFFF) ///< Buffer 2 Address Pointer + +#if defined(USE_ENHANCED_DMA_DESCRIPTORS) +#define ETH_DMA_PTP_TDES_TTSL ((u32)0xFFFFFFFF) ///< Transmit Time Stamp Low +#define ETH_DMA_PTP_TDES_TTSH ((u32)0xFFFFFFFF) ///< Transmit Time Stamp High +#endif + +#define ETH_DMA_RDES_OWN ((u32)0x80000000) ///< OWN bit: descriptor is owned by DMA engine +#define ETH_DMA_RDES_AFM ((u32)0x40000000) ///< DA Filter Fail for the rx frame +#define ETH_DMA_RDES_FL ((u32)0x3FFF0000) ///< Receive descriptor frame length +#define ETH_DMA_RDES_ES ((u32)0x00008000) ///< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE +#define ETH_DMA_RDES_DE ((u32)0x00004000) ///< Descriptor error: no more descriptors for receive frame +#define ETH_DMA_RDES_SAF ((u32)0x00002000) ///< SA Filter Fail for the received frame +#define ETH_DMA_RDES_LE ((u32)0x00001000) ///< Frame size not matching with length field +#define ETH_DMA_RDES_OE ((u32)0x00000800) ///< Overflow Error: Frame was damaged due to buffer overflow +#define ETH_DMA_RDES_VLAN ((u32)0x00000400) ///< VLAN Tag: received frame is a VLAN frame +#define ETH_DMA_RDES_FS ((u32)0x00000200) ///< First descriptor of the frame +#define ETH_DMA_RDES_LS ((u32)0x00000100) ///< Last descriptor of the frame +#define ETH_DMA_RDES_IPV4HCE ((u32)0x00000080) ///< IPC Checksum Error: Rx Ipv4 header checksum error +#define ETH_DMA_RDES_LC ((u32)0x00000040) ///< Late collision occurred during reception +#define ETH_DMA_RDES_FT ((u32)0x00000020) ///< Frame type - Ethernet, otherwise 802.3 +#define ETH_DMA_RDES_RWT ((u32)0x00000010) ///< Receive Watchdog Timeout: watchdog timer expired during reception +#define ETH_DMA_RDES_RE ((u32)0x00000008) ///< Receive error: error reported by MII interface +#define ETH_DMA_RDES_DBE ((u32)0x00000004) ///< Dribble bit error: frame contains non int multiple of 8 bits +#define ETH_DMA_RDES_CE ((u32)0x00000002) ///< CRC error +#define ETH_DMA_RDES_MAMPCE ((u32)0x00000001) ///< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error + +#define ETH_DMA_RDES_DIC ((u32)0x80000000) ///< Disable Interrupt on Completion +#define ETH_DMA_RDES_RER ((u32)0x02000000) ///< Receive End of Ring +#define ETH_DMA_RDES_RCH ((u32)0x01000000) ///< Second Address Chained +#define ETH_DMA_RDES_RBS2 ((u32)0x003FF800) ///< Receive Buffer2 Size +#define ETH_DMA_RDES_RBS1 ((u32)0x000007FF) ///< Receive Buffer1 Size + +#define ETH_DMA_RDES_B1AP ((u32)0xFFFFFFFF) ///< Buffer 1 Address Pointer + +#define ETH_DMA_RDES_B2AP ((u32)0xFFFFFFFF) ///< Buffer 2 Address Pointer + + +#if defined(USE_ENHANCED_DMA_DESCRIPTORS) +#define ETH_DMA_PTP_RDES_PTPV ((u32)0x00002000) ///< PTP Version +#define ETH_DMA_PTP_RDES_PTPFT ((u32)0x00001000) ///< PTP Frame Type +#define ETH_DMA_PTP_RDES_PTPMT ((u32)0x00000F00) ///< PTP Message Type +#define ETH_DMA_PTP_RDES_PTPMT_Sync ((u32)0x00000100) ///< SYNC message (all clock types) +#define ETH_DMA_PTP_RDES_PTPMT_FollowUp ((u32)0x00000200) ///< FollowUp message (all clock types) +#define ETH_DMA_PTP_RDES_PTPMT_DelayReq ((u32)0x00000300) ///< DelayReq message (all clock types) +#define ETH_DMA_PTP_RDES_PTPMT_DelayResp ((u32)0x00000400) ///< DelayResp message (all clock types) +#define ETH_DMA_PTP_RDES_PTPMT_PdelayReq_Announce ((u32)0x00000500) ///< PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) +#define ETH_DMA_PTP_RDES_PTPMT_PdelayResp_Manag ((u32)0x00000600) ///< PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) +#define ETH_DMA_PTP_RDES_PTPMT_PdelayRespFollowUp_Signal ((u32)0x00000700) ///< PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) +#define ETH_DMA_PTP_RDES_IPV6PR ((u32)0x00000080) ///< IPv6 Packet Received +#define ETH_DMA_PTP_RDES_IPV4PR ((u32)0x00000040) ///< IPv4 Packet Received +#define ETH_DMA_PTP_RDES_IPCB ((u32)0x00000020) ///< IP Checksum Bypassed +#define ETH_DMA_PTP_RDES_IPPE ((u32)0x00000010) ///< IP Payload Error +#define ETH_DMA_PTP_RDES_IPHE ((u32)0x00000008) ///< IP Header Error +#define ETH_DMA_PTP_RDES_IPPT ((u32)0x00000007) ///< IP Payload Type +#define ETH_DMA_PTP_RDES_IPPT_UDP ((u32)0x00000001) ///< UDP payload encapsulated in the IP datagram +#define ETH_DMA_PTP_RDES_IPPT_TCP ((u32)0x00000002) ///< TCP payload encapsulated in the IP datagram +#define ETH_DMA_PTP_RDES_IPPT_ICMP ((u32)0x00000003) ///< ICMP payload encapsulated in the IP datagram + + + +#define ETH_DMA_PTP_RDES_TTSL ((u32)0xFFFFFFFF) ///< Receive Time Stamp Low +#define ETH_DMA_PTP_RDES_TTSH ((u32)0xFFFFFFFF) ///< Receive Time Stamp High +#endif + +//////////////////////////////////////////////////////////////////////////////// +#define PHY_READ_TIMEOUT ((u32)0x0004FFFF) +#define PHY_WRITE_TIMEOUT ((u32)0x0004FFFF) + +#define PHY_BCR 0 ///< Transceiver Basic Control Register +#define PHY_BSR 1 ///< Transceiver Basic Status Register + +#define PHY_Reset ((u16)0x8000) ///< PHY Reset +#define PHY_Loopback ((u16)0x4000) ///< Select loop-back mode +#define PHY_FULLDUPLEX_100M ((u16)0x2100) ///< Set the full-duplex mode at 100 Mb/s +#define PHY_HALFDUPLEX_100M ((u16)0x2000) ///< Set the half-duplex mode at 100 Mb/s +#define PHY_FULLDUPLEX_10M ((u16)0x0100) ///< Set the full-duplex mode at 10 Mb/s +#define PHY_HALFDUPLEX_10M ((u16)0x0000) ///< Set the half-duplex mode at 10 Mb/s +#define PHY_AutoNegotiation ((u16)0x1000) ///< Enable auto-negotiation function +#define PHY_Restart_AutoNegotiation ((u16)0x0200) ///< Restart auto-negotiation function +#define PHY_Powerdown ((u16)0x0800) ///< Select the power down mode +#define PHY_Isolate ((u16)0x0400) ///< Isolate PHY from MII + +#define PHY_AutoNego_Complete ((u16)0x0020) ///< Auto-Negotiation process completed +#define PHY_Linked_Status ((u16)0x0004) ///< Valid link established +#define PHY_Jabber_detection ((u16)0x0002) ///< Jabber condition detected + +//////////////////////////////////////////////////////////////////////////////// +#define ETH_AutoNegotiation_Enable ((u32)0x00000001) +#define ETH_AutoNegotiation_Disable ((u32)0x00000000) + +#define ETH_Watchdog_Enable ((u32)0x00000000) +#define ETH_Watchdog_Disable ((u32)0x00800000) + +#define ETH_Jabber_Enable ((u32)0x00000000) +#define ETH_Jabber_Disable ((u32)0x00400000) + +#define ETH_InterFrameGap_96Bit ((u32)0x00000000) ///< minimum IFG between frames during transmission is 96Bit +#define ETH_InterFrameGap_88Bit ((u32)0x00020000) ///< minimum IFG between frames during transmission is 88Bit +#define ETH_InterFrameGap_80Bit ((u32)0x00040000) ///< minimum IFG between frames during transmission is 80Bit +#define ETH_InterFrameGap_72Bit ((u32)0x00060000) ///< minimum IFG between frames during transmission is 72Bit +#define ETH_InterFrameGap_64Bit ((u32)0x00080000) ///< minimum IFG between frames during transmission is 64Bit +#define ETH_InterFrameGap_56Bit ((u32)0x000A0000) ///< minimum IFG between frames during transmission is 56Bit +#define ETH_InterFrameGap_48Bit ((u32)0x000C0000) ///< minimum IFG between frames during transmission is 48Bit +#define ETH_InterFrameGap_40Bit ((u32)0x000E0000) ///< minimum IFG between frames during transmission is 40Bit + +#define ETH_CarrierSense_Enable ((u32)0x00000000) +#define ETH_CarrierSense_Disable ((u32)0x00010000) + +#define ETH_Speed_10M ((u32)0x00000000) +#define ETH_Speed_100M ((u32)0x00004000) + +#define ETH_ReceiveOwn_Enable ((u32)0x00000000) +#define ETH_ReceiveOwn_Disable ((u32)0x00002000) + +#define ETH_LoopbackMode_Enable ((u32)0x00001000) +#define ETH_LoopbackMode_Disable ((u32)0x00000000) + +#define ETH_Mode_FullDuplex ((u32)0x00000800) +#define ETH_Mode_HalfDuplex ((u32)0x00000000) + +#define ETH_ChecksumOffload_Enable ((u32)0x00000400) +#define ETH_ChecksumOffload_Disable ((u32)0x00000000) + +#define ETH_RetryTransmission_Enable ((u32)0x00000000) +#define ETH_RetryTransmission_Disable ((u32)0x00000200) + +#define ETH_AutomaticPadCRCStrip_Enable ((u32)0x00000080) +#define ETH_AutomaticPadCRCStrip_Disable ((u32)0x00000000) + +#define ETH_BackOffLimit_10 ((u32)0x00000000) +#define ETH_BackOffLimit_8 ((u32)0x00000020) +#define ETH_BackOffLimit_4 ((u32)0x00000040) +#define ETH_BackOffLimit_1 ((u32)0x00000060) + +#define ETH_DeferralCheck_Enable ((u32)0x00000010) +#define ETH_DeferralCheck_Disable ((u32)0x00000000) + +#define ETH_ReceiveAll_Enable ((u32)0x80000000) +#define ETH_ReceiveAll_Disable ((u32)0x00000000) + +#define ETH_SourceAddrFilter_Normal_Enable ((u32)0x00000200) +#define ETH_SourceAddrFilter_Inverse_Enable ((u32)0x00000300) +#define ETH_SourceAddrFilter_Disable ((u32)0x00000000) + +#define ETH_PassControlFrames_BlockAll ((u32)0x00000040) ///< MAC filters all control frames from reaching the application +#define ETH_PassControlFrames_ForwardAll ((u32)0x00000080) ///< MAC forwards all control frames to application even if they fail the Address Filter +#define ETH_PassControlFrames_ForwardPassedAddrFilter ((u32)0x000000C0) ///< MAC forwards control frames that pass the Address Filter. + +#define ETH_BroadcastFramesReception_Enable ((u32)0x00000000) +#define ETH_BroadcastFramesReception_Disable ((u32)0x00000020) + +#define ETH_DestinationAddrFilter_Normal ((u32)0x00000000) +#define ETH_DestinationAddrFilter_Inverse ((u32)0x00000008) + +#define ETH_PromiscuousMode_Enable ((u32)0x00000001) +#define ETH_PromiscuousMode_Disable ((u32)0x00000000) + +#define ETH_MulticastFramesFilter_PerfectHashTable ((u32)0x00000404) +#define ETH_MulticastFramesFilter_HashTable ((u32)0x00000004) +#define ETH_MulticastFramesFilter_Perfect ((u32)0x00000000) +#define ETH_MulticastFramesFilter_None ((u32)0x00000010) + +#define ETH_UnicastFramesFilter_PerfectHashTable ((u32)0x00000402) +#define ETH_UnicastFramesFilter_HashTable ((u32)0x00000002) +#define ETH_UnicastFramesFilter_Perfect ((u32)0x00000000) + +#define ETH_ZeroQuantaPause_Enable ((u32)0x00000000) +#define ETH_ZeroQuantaPause_Disable ((u32)0x00000080) + +#define ETH_PauseLowThreshold_Minus4 ((u32)0x00000000) ///< Pause time minus 4 slot times +#define ETH_PauseLowThreshold_Minus28 ((u32)0x00000010) ///< Pause time minus 28 slot times +#define ETH_PauseLowThreshold_Minus144 ((u32)0x00000020) ///< Pause time minus 144 slot times +#define ETH_PauseLowThreshold_Minus256 ((u32)0x00000030) ///< Pause time minus 256 slot times + +#define ETH_UnicastPauseFrameDetect_Enable ((u32)0x00000008) +#define ETH_UnicastPauseFrameDetect_Disable ((u32)0x00000000) + +#define ETH_ReceiveFlowControl_Enable ((u32)0x00000004) +#define ETH_ReceiveFlowControl_Disable ((u32)0x00000000) + +#define ETH_TransmitFlowControl_Enable ((u32)0x00000002) +#define ETH_TransmitFlowControl_Disable ((u32)0x00000000) + +#define ETH_VLANTagComparison_12Bit ((u32)0x00010000) +#define ETH_VLANTagComparison_16Bit ((u32)0x00000000) + +#define ETH_MAC_FLAG_TST ((u32)0x00000200) ///< Time stamp trigger flag (on MAC) +#define ETH_MAC_FLAG_MMCT ((u32)0x00000040) ///< MMC transmit flag +#define ETH_MAC_FLAG_MMCR ((u32)0x00000020) ///< MMC receive flag +#define ETH_MAC_FLAG_MMC ((u32)0x00000010) ///< MMC flag (on MAC) +#define ETH_MAC_FLAG_PMT ((u32)0x00000008) ///< PMT flag (on MAC) + +#define ETH_MAC_IT_TST ((u32)0x00000200) ///< Time stamp trigger interrupt (on MAC) +#define ETH_MAC_IT_MMCT ((u32)0x00000040) ///< MMC transmit interrupt +#define ETH_MAC_IT_MMCR ((u32)0x00000020) ///< MMC receive interrupt +#define ETH_MAC_IT_MMC ((u32)0x00000010) ///< MMC interrupt (on MAC) +#define ETH_MAC_IT_PMT ((u32)0x00000008) ///< PMT interrupt (on MAC) + +#define ETH_MAC_Address0 ((u32)0x00000000) +#define ETH_MAC_Address1 ((u32)0x00000008) +#define ETH_MAC_Address2 ((u32)0x00000010) +#define ETH_MAC_Address3 ((u32)0x00000018) + +#define ETH_MAC_AddressFilter_SA ((u32)0x00000000) +#define ETH_MAC_AddressFilter_DA ((u32)0x00000008) + +#define ETH_MAC_AddressMask_Byte6 ((u32)0x20000000) ///< Mask MAC Address high reg bits [15:8] +#define ETH_MAC_AddressMask_Byte5 ((u32)0x10000000) ///< Mask MAC Address high reg bits [7:0] +#define ETH_MAC_AddressMask_Byte4 ((u32)0x08000000) ///< Mask MAC Address low reg bits [31:24] +#define ETH_MAC_AddressMask_Byte3 ((u32)0x04000000) ///< Mask MAC Address low reg bits [23:16] +#define ETH_MAC_AddressMask_Byte2 ((u32)0x02000000) ///< Mask MAC Address low reg bits [15:8] +#define ETH_MAC_AddressMask_Byte1 ((u32)0x01000000) ///< Mask MAC Address low reg bits [70] + +//////////////////////////////////////////////////////////////////////////////// +#define ETH_DMA_TDES_LastSegment ((u32)0x40000000) ///< Last Segment +#define ETH_DMA_TDES_FirstSegment ((u32)0x20000000) ///< First Segment + +#define ETH_DMA_TDES_ChecksumByPass ((u32)0x00000000) ///< Checksum engine bypass +#define ETH_DMA_TDES_ChecksumIPV4Header ((u32)0x00400000) ///< IPv4 header checksum insertion +#define ETH_DMA_TDES_ChecksumTCPUDPICMPSegment ((u32)0x00800000) ///< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present +#define ETH_DMA_TDES_ChecksumTCPUDPICMPFull ((u32)0x00C00000) ///< TCP/UDP/ICMP checksum fully in hardware including pseudo header + +#define ETH_DMA_RDES_Buffer1 ((u32)0x00000000) ///< DMA Rx Desc Buffer1 +#define ETH_DMA_RDES_Buffer2 ((u32)0x00000001) ///< DMA Rx Desc Buffer2 + +#define ETH_DropTCPIPChecksumErrorFrame_Enable ((u32)0x00000000) +#define ETH_DropTCPIPChecksumErrorFrame_Disable ((u32)0x04000000) + +#define ETH_ReceiveStoreForward_Enable ((u32)0x02000000) +#define ETH_ReceiveStoreForward_Disable ((u32)0x00000000) + +#define ETH_FlushReceivedFrame_Enable ((u32)0x00000000) +#define ETH_FlushReceivedFrame_Disable ((u32)0x01000000) + +#define ETH_TransmitStoreForward_Enable ((u32)0x00200000) +#define ETH_TransmitStoreForward_Disable ((u32)0x00000000) + +#define ETH_TransmitThresholdControl_64Bytes ((u32)0x00000000) ///< threshold level of the MTL Transmit FIFO is 64 Bytes +#define ETH_TransmitThresholdControl_128Bytes ((u32)0x00004000) ///< threshold level of the MTL Transmit FIFO is 128 Bytes +#define ETH_TransmitThresholdControl_192Bytes ((u32)0x00008000) ///< threshold level of the MTL Transmit FIFO is 192 Bytes +#define ETH_TransmitThresholdControl_256Bytes ((u32)0x0000C000) ///< threshold level of the MTL Transmit FIFO is 256 Bytes +#define ETH_TransmitThresholdControl_40Bytes ((u32)0x00010000) ///< threshold level of the MTL Transmit FIFO is 40 Bytes +#define ETH_TransmitThresholdControl_32Bytes ((u32)0x00014000) ///< threshold level of the MTL Transmit FIFO is 32 Bytes +#define ETH_TransmitThresholdControl_24Bytes ((u32)0x00018000) ///< threshold level of the MTL Transmit FIFO is 24 Bytes +#define ETH_TransmitThresholdControl_16Bytes ((u32)0x0001C000) ///< threshold level of the MTL Transmit FIFO is 16 Bytes + +#define ETH_ForwardErrorFrames_Enable ((u32)0x00000080) +#define ETH_ForwardErrorFrames_Disable ((u32)0x00000000) + +#define ETH_ForwardUndersizedGoodFrames_Enable ((u32)0x00000040) +#define ETH_ForwardUndersizedGoodFrames_Disable ((u32)0x00000000) + +#define ETH_ReceiveThresholdControl_64Bytes ((u32)0x00000000) ///< threshold level of the MTL Receive FIFO is 64 Bytes +#define ETH_ReceiveThresholdControl_32Bytes ((u32)0x00000008) ///< threshold level of the MTL Receive FIFO is 32 Bytes +#define ETH_ReceiveThresholdControl_96Bytes ((u32)0x00000010) ///< threshold level of the MTL Receive FIFO is 96 Bytes +#define ETH_ReceiveThresholdControl_128Bytes ((u32)0x00000018) ///< threshold level of the MTL Receive FIFO is 128 Bytes + +#define ETH_SecondFrameOperate_Enable ((u32)0x00000004) +#define ETH_SecondFrameOperate_Disable ((u32)0x00000000) + +#define ETH_AddressAlignedBeats_Enable ((u32)0x02000000) +#define ETH_AddressAlignedBeats_Disable ((u32)0x00000000) + +#define ETH_FixedBurst_Enable ((u32)0x00010000) +#define ETH_FixedBurst_Disable ((u32)0x00000000) + +#define ETH_RxDMABurstLength_1Beat ((u32)0x00020000) ///< maximum number of beats to be transferred in one RxDMA transaction is 1 +#define ETH_RxDMABurstLength_2Beat ((u32)0x00040000) ///< maximum number of beats to be transferred in one RxDMA transaction is 2 +#define ETH_RxDMABurstLength_4Beat ((u32)0x00080000) ///< maximum number of beats to be transferred in one RxDMA transaction is 4 +#define ETH_RxDMABurstLength_8Beat ((u32)0x00100000) ///< maximum number of beats to be transferred in one RxDMA transaction is 8 +#define ETH_RxDMABurstLength_16Beat ((u32)0x00200000) ///< maximum number of beats to be transferred in one RxDMA transaction is 16 +#define ETH_RxDMABurstLength_32Beat ((u32)0x00400000) ///< maximum number of beats to be transferred in one RxDMA transaction is 32 +#define ETH_RxDMABurstLength_4xPBL_4Beat ((u32)0x01020000) ///< maximum number of beats to be transferred in one RxDMA transaction is 4 +#define ETH_RxDMABurstLength_4xPBL_8Beat ((u32)0x01040000) ///< maximum number of beats to be transferred in one RxDMA transaction is 8 +#define ETH_RxDMABurstLength_4xPBL_16Beat ((u32)0x01080000) ///< maximum number of beats to be transferred in one RxDMA transaction is 16 +#define ETH_RxDMABurstLength_4xPBL_32Beat ((u32)0x01100000) ///< maximum number of beats to be transferred in one RxDMA transaction is 32 +#define ETH_RxDMABurstLength_4xPBL_64Beat ((u32)0x01200000) ///< maximum number of beats to be transferred in one RxDMA transaction is 64 +#define ETH_RxDMABurstLength_4xPBL_128Beat ((u32)0x01400000) ///< maximum number of beats to be transferred in one RxDMA transaction is 128 + +#define ETH_TxDMABurstLength_1Beat ((u32)0x00000100) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 +#define ETH_TxDMABurstLength_2Beat ((u32)0x00000200) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 +#define ETH_TxDMABurstLength_4Beat ((u32)0x00000400) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 +#define ETH_TxDMABurstLength_8Beat ((u32)0x00000800) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 +#define ETH_TxDMABurstLength_16Beat ((u32)0x00001000) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 +#define ETH_TxDMABurstLength_32Beat ((u32)0x00002000) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 +#define ETH_TxDMABurstLength_4xPBL_4Beat ((u32)0x01000100) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 +#define ETH_TxDMABurstLength_4xPBL_8Beat ((u32)0x01000200) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 +#define ETH_TxDMABurstLength_4xPBL_16Beat ((u32)0x01000400) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 +#define ETH_TxDMABurstLength_4xPBL_32Beat ((u32)0x01000800) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 +#define ETH_TxDMABurstLength_4xPBL_64Beat ((u32)0x01001000) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 +#define ETH_TxDMABurstLength_4xPBL_128Beat ((u32)0x01002000) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 + +#define ETH_DMAArbitration_RoundRobin_RxTx_1_1 ((u32)0x00000000) +#define ETH_DMAArbitration_RoundRobin_RxTx_2_1 ((u32)0x00004000) +#define ETH_DMAArbitration_RoundRobin_RxTx_3_1 ((u32)0x00008000) +#define ETH_DMAArbitration_RoundRobin_RxTx_4_1 ((u32)0x0000C000) +#define ETH_DMAArbitration_RxPriorTx ((u32)0x00000002) + +#define ETH_DMA_FLAG_TST ((u32)0x20000000) ///< Time-stamp trigger interrupt (on DMA) +#define ETH_DMA_FLAG_PMT ((u32)0x10000000) ///< PMT interrupt (on DMA) +#define ETH_DMA_FLAG_MMC ((u32)0x08000000) ///< MMC interrupt (on DMA) +#define ETH_DMA_FLAG_DataTransferError ((u32)0x00800000) ///< Error bits 0-Rx DMA, 1-Tx DMA +#define ETH_DMA_FLAG_ReadWriteError ((u32)0x01000000) ///< Error bits 0-write trnsf, 1-read transfr +#define ETH_DMA_FLAG_AccessError ((u32)0x02000000) ///< Error bits 0-data buffer, 1-desc. access +#define ETH_DMA_FLAG_NIS ((u32)0x00010000) ///< Normal interrupt summary flag +#define ETH_DMA_FLAG_AIS ((u32)0x00008000) ///< Abnormal interrupt summary flag +#define ETH_DMA_FLAG_ER ((u32)0x00004000) ///< Early receive flag +#define ETH_DMA_FLAG_FBE ((u32)0x00002000) ///< Fatal bus error flag +#define ETH_DMA_FLAG_ET ((u32)0x00000400) ///< Early transmit flag +#define ETH_DMA_FLAG_RWT ((u32)0x00000200) ///< Receive watchdog timeout flag +#define ETH_DMA_FLAG_RPS ((u32)0x00000100) ///< Receive process stopped flag +#define ETH_DMA_FLAG_RBU ((u32)0x00000080) ///< Receive buffer unavailable flag +#define ETH_DMA_FLAG_R ((u32)0x00000040) ///< Receive flag +#define ETH_DMA_FLAG_TU ((u32)0x00000020) ///< Underflow flag +#define ETH_DMA_FLAG_RO ((u32)0x00000010) ///< Overflow flag +#define ETH_DMA_FLAG_TJT ((u32)0x00000008) ///< Transmit jabber timeout flag +#define ETH_DMA_FLAG_TBU ((u32)0x00000004) ///< Transmit buffer unavailable flag +#define ETH_DMA_FLAG_TPS ((u32)0x00000002) ///< Transmit process stopped flag +#define ETH_DMA_FLAG_T ((u32)0x00000001) ///< Transmit flag + +#define ETH_DMA_IT_TST ((u32)0x20000000) ///< Time-stamp trigger interrupt (on DMA) +#define ETH_DMA_IT_PMT ((u32)0x10000000) ///< PMT interrupt (on DMA) +#define ETH_DMA_IT_MMC ((u32)0x08000000) ///< MMC interrupt (on DMA) +#define ETH_DMA_IT_NIS ((u32)0x00010000) ///< Normal interrupt summary +#define ETH_DMA_IT_AIS ((u32)0x00008000) ///< Abnormal interrupt summary +#define ETH_DMA_IT_ER ((u32)0x00004000) ///< Early receive interrupt +#define ETH_DMA_IT_FBE ((u32)0x00002000) ///< Fatal bus error interrupt +#define ETH_DMA_IT_ET ((u32)0x00000400) ///< Early transmit interrupt +#define ETH_DMA_IT_RWT ((u32)0x00000200) ///< Receive watchdog timeout interrupt +#define ETH_DMA_IT_RPS ((u32)0x00000100) ///< Receive process stopped interrupt +#define ETH_DMA_IT_RBU ((u32)0x00000080) ///< Receive buffer unavailable interrupt +#define ETH_DMA_IT_R ((u32)0x00000040) ///< Receive interrupt +#define ETH_DMA_IT_TU ((u32)0x00000020) ///< Underflow interrupt +#define ETH_DMA_IT_RO ((u32)0x00000010) ///< Overflow interrupt +#define ETH_DMA_IT_TJT ((u32)0x00000008) ///< Transmit jabber timeout interrupt +#define ETH_DMA_IT_TBU ((u32)0x00000004) ///< Transmit buffer unavailable interrupt +#define ETH_DMA_IT_TPS ((u32)0x00000002) ///< Transmit process stopped interrupt +#define ETH_DMA_IT_T ((u32)0x00000001) ///< Transmit interrupt + +#define ETH_DMA_TransmitProcess_Stopped ((u32)0x00000000) ///< Stopped - Reset or Stop Tx Command issued +#define ETH_DMA_TransmitProcess_Fetching ((u32)0x00100000) ///< Running - fetching the Tx descriptor +#define ETH_DMA_TransmitProcess_Waiting ((u32)0x00200000) ///< Running - waiting for status +#define ETH_DMA_TransmitProcess_Reading ((u32)0x00300000) ///< Running - reading the data from host memory +#define ETH_DMA_TransmitProcess_Suspended ((u32)0x00600000) ///< Suspended - Tx Descriptor unavailable +#define ETH_DMA_TransmitProcess_Closing ((u32)0x00700000) ///< Running - closing Rx descriptor + +#define ETH_DMA_ReceiveProcess_Stopped ((u32)0x00000000) ///< Stopped - Reset or Stop Rx Command issued +#define ETH_DMA_ReceiveProcess_Fetching ((u32)0x00020000) ///< Running - fetching the Rx descriptor +#define ETH_DMA_ReceiveProcess_Waiting ((u32)0x00060000) ///< Running - waiting for packet +#define ETH_DMA_ReceiveProcess_Suspended ((u32)0x00080000) ///< Suspended - Rx Descriptor unavailable +#define ETH_DMA_ReceiveProcess_Closing ((u32)0x000A0000) ///< Running - closing descriptor +#define ETH_DMA_ReceiveProcess_Queuing ((u32)0x000E0000) ///< Running - queuing the receive frame into host memory + +#define ETH_DMA_Overflow_RxFIFOCounter ((u32)0x10000000) ///< Overflow bit for FIFO overflow counter +#define ETH_DMA_Overflow_MissedFrameCounter ((u32)0x00010000) ///< Overflow bit for missed frame counter + +//////////////////////////////////////////////////////////////////////////////// +#define ETH_PMT_FLAG_WUFFRPR ((u32)0x80000000) ///< Wake-Up Frame Filter Register Pointer Reset +#define ETH_PMT_FLAG_WUFR ((u32)0x00000040) ///< Wake-Up Frame Received +#define ETH_PMT_FLAG_MPR ((u32)0x00000020) ///< Magic Packet Received + +//////////////////////////////////////////////////////////////////////////////// +#define ETH_MMC_IT_TGF ((u32)0x00200000) ///< When Tx good frame counter reaches half the maximum value +#define ETH_MMC_IT_TGFMSC ((u32)0x00008000) ///< When Tx good multi col counter reaches half the maximum value +#define ETH_MMC_IT_TGFSC ((u32)0x00004000) ///< When Tx good single col counter reaches half the maximum value + +#define ETH_MMC_IT_RGUF ((u32)0x10020000) ///< When Rx good unicast frames counter reaches half the maximum value +#define ETH_MMC_IT_RFAE ((u32)0x10000040) ///< When Rx alignment error counter reaches half the maximum value +#define ETH_MMC_IT_RFCE ((u32)0x10000020) ///< When Rx crc error counter reaches half the maximum value + +#define ETH_MMCCR ((u32)0x00000100) ///< MMC CR register +#define ETH_MMCRIR ((u32)0x00000104) ///< MMC RIR register +#define ETH_MMCTIR ((u32)0x00000108) ///< MMC TIR register +#define ETH_MMCRIMR ((u32)0x0000010C) ///< MMC RIMR register +#define ETH_MMCTIMR ((u32)0x00000110) ///< MMC TIMR register +#define ETH_MMCTGFSCCR ((u32)0x0000014C) ///< MMC TGFSCCR register +#define ETH_MMCTGFMSCCR ((u32)0x00000150) ///< MMC TGFMSCCR register +#define ETH_MMCTGFCR ((u32)0x00000168) ///< MMC TGFCR register +#define ETH_MMCRFCECR ((u32)0x00000194) ///< MMC RFCECR register +#define ETH_MMCRFAECR ((u32)0x00000198) ///< MMC RFAECR register +#define ETH_MMCRGUFCR ((u32)0x000001C4) ///< MMC RGUFCR register + +//////////////////////////////////////////////////////////////////////////////// +#define ETH_PTP_FineUpdate ((u32)0x00000001) ///< Fine Update method +#define ETH_PTP_CoarseUpdate ((u32)0x00000000) ///< Coarse Update method + +#define ETH_PTP_FLAG_TSARU ((u32)0x00000020) ///< Addend Register Update +#define ETH_PTP_FLAG_TSITE ((u32)0x00000010) ///< Time Stamp Interrupt Trigger +#define ETH_PTP_FLAG_TSSTU ((u32)0x00000008) ///< Time Stamp Update +#define ETH_PTP_FLAG_TSSTI ((u32)0x00000004) ///< Time Stamp Initialize + +#define ETH_PTP_FLAG_TSTTR ((u32)0x10000002) ///< Time stamp target time reached +#define ETH_PTP_FLAG_TSSO ((u32)0x10000001) ///< Time stamp seconds overflow + +#define ETH_PTP_PositiveTime ((u32)0x00000000) ///< Positive time value +#define ETH_PTP_NegativeTime ((u32)0x80000000) ///< Negative time value + +#define ETH_PTPTSCR ((u32)0x00000700) ///< PTP TSCR register +#define ETH_PTPSSIR ((u32)0x00000704) ///< PTP SSIR register +#define ETH_PTPTSHR ((u32)0x00000708) ///< PTP TSHR register +#define ETH_PTPTSLR ((u32)0x0000070C) ///< PTP TSLR register +#define ETH_PTPTSHUR ((u32)0x00000710) ///< PTP TSHUR register +#define ETH_PTPTSLUR ((u32)0x00000714) ///< PTP TSLUR register +#define ETH_PTPTSAR ((u32)0x00000718) ///< PTP TSAR register +#define ETH_PTPTTHR ((u32)0x0000071C) ///< PTP TTHR register +#define ETH_PTPTTLR ((u32)0x00000720) ///< PTP TTLR register + +#define ETH_PTPTSSR ((u32)0x00000728) ///< PTP TSSR register + +#define ETH_PTP_OrdinaryClock ((u32)0x00000000) ///< Ordinary Clock +#define ETH_PTP_BoundaryClock ((u32)0x00010000) ///< Boundary Clock +#define ETH_PTP_EndToEndTransparentClock ((u32)0x00020000) ///< End To End Transparent Clock +#define ETH_PTP_PeerToPeerTransparentClock ((u32)0x00030000) ///< Peer To Peer Transparent Clock + +#define ETH_PTP_SnapshotMasterMessage ((u32)0x00008000) ///< Time stamp snapshot for message relevant to master enable +#define ETH_PTP_SnapshotEventMessage ((u32)0x00004000) ///< Time stamp snapshot for event message enable +#define ETH_PTP_SnapshotIPV4Frames ((u32)0x00002000) ///< Time stamp snapshot for IPv4 frames enable +#define ETH_PTP_SnapshotIPV6Frames ((u32)0x00001000) ///< Time stamp snapshot for IPv6 frames enable +#define ETH_PTP_SnapshotPTPOverEthernetFrames ((u32)0x00000800) ///< Time stamp snapshot for PTP over ethernet frames enable +#define ETH_PTP_SnapshotAllReceivedFrames ((u32)0x00000100) ///< Time stamp snapshot for all received frames enable + +#define ETH_MAC_ADDR_HBASE (ETH_BASE + 0x40) ///< ETHERNET MAC address high offset +#define ETH_MAC_ADDR_LBASE (ETH_BASE + 0x44) ///< ETHERNET MAC address low offset + +#define MACMIIAR_CR_MASK ((u32)0xFFFFFFE3) + +#define MACCR_CLEAR_MASK ((u32)0xFF20810F) +#define MACFCR_CLEAR_MASK ((u32)0x0000FF41) +#define DMAOMR_CLEAR_MASK ((u32)0xF8DE3F23) + + + +GLOBAL __IO ETH_DMADESCTypeDef* DMATxDescToSet; +GLOBAL __IO ETH_DMADESCTypeDef* DMARxDescToGet; + +GLOBAL ETH_DMA_Rx_Frame_infos RX_Frame_Descriptor; +GLOBAL __IO ETH_DMA_Rx_Frame_infos* DMA_RX_FRAME_infos; +GLOBAL __IO u32 Frame_Rx_index; + +#undef GLOBAL + +void ETH_DeInit(void); +void ETH_StructInit(ETH_InitTypeDef* ptr); +u32 ETH_Init(ETH_InitTypeDef* ptr, u16 phy_addr); +void ETH_Start(void); +void ETH_Stop(void); +void ETH_MACTransmissionCmd(FunctionalState sta); +void ETH_MACReceptionCmd(FunctionalState sta); +FlagStatus ETH_GetFlowControlBusyStatus(void); +void ETH_InitiatePauseControlFrame(void); +void ETH_BackPressureActivationCmd(FunctionalState sta); +void ETH_MACAddressConfig(u32 reg_addr, u8* mac_addr); +void ETH_GetMACAddress(u32 reg_addr, u8* mac_addr); +void ETH_MACAddressPerfectFilterCmd(u32 reg_addr, FunctionalState sta); +void ETH_MACAddressFilterConfig(u32 reg_addr, u32 sta); +void ETH_MACAddressMaskBytesFilterConfig(u32 reg_addr, u32 mask_byte); +FrameTypeDef ETH_Get_Received_Frame(void); +FrameTypeDef ETH_Get_Received_Frame_interrupt(void); +u32 ETH_Prepare_Transmit_Descriptors(u16 len); +void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef* ptr_desc, u8* buf, u32 cnt); +u32 ETH_CheckFrameReceived(void); +void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef* ptr_desc, u8* buf, u32 cnt); +FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef* ptr_desc, u32 flag); +u32 ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef* ptr_desc); +void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef* ptr_desc); +void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta); +void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef* ptr_desc, u32 val); +void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef* ptr_desc, u32 val); +void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta); +void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta); +void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta); +void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef* ptr_desc, u32 buf1_size, u32 buf2_size); +FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef* ptr_desc, u32 flag); +void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef* ptr_desc); +u32 ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef* ptr_desc); +void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta); +u32 ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef* ptr_desc, u32 buf); +u32 ETH_GetRxPktSize(ETH_DMADESCTypeDef* ptr_desc); +void ETH_SoftwareReset(void); +FlagStatus ETH_GetSoftwareResetStatus(void); +FlagStatus ETH_GetDMAFlagStatus(u32 flag); +void ETH_DMAClearFlag(u32 flag); +void ETH_DMAITConfig(u32 it, FunctionalState sta); +ITStatus ETH_GetDMAITStatus(u32 it); +void ETH_DMAClearITPendingBit(u32 it); +u32 ETH_GetTransmitProcessState(void); +u32 ETH_GetReceiveProcessState(void); +void ETH_FlushTransmitFIFO(void); +FlagStatus ETH_GetFlushTransmitFIFOStatus(void); +void ETH_DMATransmissionCmd(FunctionalState sta); +void ETH_DMAReceptionCmd(FunctionalState sta); +FlagStatus ETH_GetDMAOverflowStatus(u32 val); +u32 ETH_GetRxOverflowMissedFrameCounter(void); +u32 ETH_GetBufferUnavailableMissedFrameCounter(void); +u32 ETH_GetCurrentTxDescStartAddress(void); +u32 ETH_GetCurrentRxDescStartAddress(void); +u32 ETH_GetCurrentTxBufferAddress(void); +u32 ETH_GetCurrentRxBufferAddress(void); +void ETH_ResumeDMATransmission(void); +void ETH_ResumeDMAReception(void); +void ETH_SetReceiveWatchdogTimer(u8 val); +u16 ETH_ReadPHYRegister(u16 addr, u16 reg); +u16 ETH_WritePHYRegister(u16 addr, u16 reg, u16 val); +u32 ETH_PHYLoopBackCmd(u16 addr, FunctionalState sta); +void ETH_ResetWakeUpFrameFilterRegisterPointer(void); +void ETH_SetWakeUpFrameFilterRegister(u32* buf); +void ETH_GlobalUnicastWakeUpCmd(FunctionalState sta); +FlagStatus ETH_GetPMTFlagStatus(u32 flag); +void ETH_WakeUpFrameDetectionCmd(FunctionalState sta); +void ETH_MagicPacketDetectionCmd(FunctionalState sta); +void ETH_PowerDownCmd(FunctionalState sta); +void ETH_MMCCounterFullPreset(void); +void ETH_MMCCounterHalfPreset(void); +void ETH_MMCCounterFreezeCmd(FunctionalState sta); +void ETH_MMCResetOnReadCmd(FunctionalState sta); +void ETH_MMCCounterRolloverCmd(FunctionalState sta); +void ETH_MMCCountersReset(void); +void ETH_MMCITConfig(u32 it, FunctionalState sta); +ITStatus ETH_GetMMCITStatus(u32 it); +u32 ETH_GetMMCRegister(u32 reg); + +/// @} + +/// @} + +/// @} +//////////////////////////////////////////////////////////////////////////////// +#endif //__HAL_ETH_H +//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_eth_conf.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_eth_conf.h new file mode 100644 index 000000000..f00e17e63 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_eth_conf.h @@ -0,0 +1,68 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_eth_conf.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE hal_eth_conf.h EXAMPLES. +/// //////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +#ifndef __HAL_ETH_CONF_H +#define __HAL_ETH_CONF_H +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup ETH_HAL +/// @brief ETH HAL modules +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup ETH_Exported_Types +/// @{ + + +// #define USE_ENHANCED_DMA_DESCRIPTORS +// #define CUSTOM_DRIVER_BUFFERS_CONFIG +#define DP83848 + +#ifdef CUSTOM_DRIVER_BUFFERS_CONFIG +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE +#define ETH_RX_BUF_NUM 4 +#define ETH_TX_BUF_NUM 4 +#endif + +//////////////////////////////////////////////////////////////////////////////// +#if defined(DP83848) +#define PHY_SR ((u16)0x10) +#define PHY_SR_LINKSTATUS ((u16)0x0001) +#define PHY_SPEED_STATUS ((u16)0x0002) +#define PHY_DUPLEX_STATUS ((u16)0x0004) + +#define PHY_MICR ((u16)0x11) +#define PHY_MICR_INT_EN ((u16)0x0002) +#define PHY_MICR_INT_OE ((u16)0x0001) + +#define PHY_MISR ((u16)0x12) +#define PHY_MISR_LINK_INT_EN ((u16)0x0020) +#define PHY_LINK_STATUS ((u16)0x2000) +#endif + +/// @} + +/// @} + +/// @} +//////////////////////////////////////////////////////////////////////////////// +#endif //__HAL_ETH_CONF_H +//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_exti.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_exti.h new file mode 100644 index 000000000..a90daff9c --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_exti.h @@ -0,0 +1,181 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_exti.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE EXTI +/// FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#ifndef __HAL_EXTI_H +#define __HAL_EXTI_H + +// Files includes +#include "types.h" +#include "reg_common.h" +#include "reg_exti.h" + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup EXTI_HAL +/// @brief EXTI HAL modules +/// @{ + + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup EXTI_Exported_Types +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @brief EXTI mode enumeration +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + EXTI_Mode_Interrupt = 0x00, ///< EXTI interrupt mode + EXTI_Mode_Event = 0x04 ///< EXTI event mode +} EXTIMode_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief EXTI Trigger enumeration +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + EXTI_Trigger_Rising = 0x08, ///< EXTI rising edge triggering + EXTI_Trigger_Falling = 0x0C, ///< EXTI falling edge triggering + EXTI_Trigger_Rising_Falling = 0x10 ///< EXTI rising and falling edge triggers +} EXTITrigger_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief EXTI Init Structure definition +//////////////////////////////////////////////////////////////////////////////// +typedef struct { + u32 EXTI_Line; ///< Specifies the EXTI lines to be enabled or disabled. + ///< This parameter can be any combination of @ref EXTI_Lines + EXTIMode_TypeDef EXTI_Mode; ///< Specifies the mode for the EXTI lines. + ///< This parameter can be a value of @ref EXTIMode_TypeDef + EXTITrigger_TypeDef EXTI_Trigger; ///< Specifies the trigger signal active edge for the EXTI lines. + ///< This parameter can be a value of @ref EXTIMode_TypeDef + FunctionalState EXTI_LineCmd; ///< Specifies the new state of the selected EXTI lines. + ///< This parameter can be set either to ENABLE or DISABLE +} EXTI_InitTypeDef; + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup EXTI_Exported_Constants +/// @{ + + + +#define EXTI_LineNone ((u32)0x0000000) ///< No interrupt selected +#define EXTI_Line0 ((u32)0x0000001) ///< External interrupt line 0 +#define EXTI_Line1 ((u32)0x0000002) ///< External interrupt line 1 +#define EXTI_Line2 ((u32)0x0000004) ///< External interrupt line 2 +#define EXTI_Line3 ((u32)0x0000008) ///< External interrupt line 3 +#define EXTI_Line4 ((u32)0x0000010) ///< External interrupt line 4 +#define EXTI_Line5 ((u32)0x0000020) ///< External interrupt line 5 +#define EXTI_Line6 ((u32)0x0000040) ///< External interrupt line 6 +#define EXTI_Line7 ((u32)0x0000080) ///< External interrupt line 7 +#define EXTI_Line8 ((u32)0x0000100) ///< External interrupt line 8 +#define EXTI_Line9 ((u32)0x0000200) ///< External interrupt line 9 +#define EXTI_Line10 ((u32)0x0000400) ///< External interrupt line 10 +#define EXTI_Line11 ((u32)0x0000800) ///< External interrupt line 11 +#define EXTI_Line12 ((u32)0x0001000) ///< External interrupt line 12 +#define EXTI_Line13 ((u32)0x0002000) ///< External interrupt line 13 +#define EXTI_Line14 ((u32)0x0004000) ///< External interrupt line 14 +#define EXTI_Line15 ((u32)0x0008000) ///< External interrupt line 15 +#define EXTI_Line16 ((u32)0x0010000) ///< External interrupt line 16 Connected to the PVD Output +#define EXTI_Line17 ((u32)0x0020000) ///< External interrupt line 17 Connected to the RTC Alarm event +#define EXTI_Line18 ((u32)0x0040000) ///< External interrupt line 18 Connected to the USB Wakeup from suspend event +#define EXTI_Line19 ((u32)0x0080000) ///< External interrupt line 19 +#define EXTI_Line20 ((u32)0x0100000) ///< External interrupt line 20 +#define EXTI_Line21 ((u32)0x0200000) ///< External interrupt line 21 +#define EXTI_Line22 ((u32)0x0400000) ///< External interrupt line 22 +#define EXTI_Line23 ((u32)0x0800000) ///< External interrupt line 23 +#define EXTI_Line24 ((u32)0x1000000) ///< External interrupt line 24 + +#define EXTI_PortSourceGPIOA (0x00U) +#define EXTI_PortSourceGPIOB (0x01U) +#define EXTI_PortSourceGPIOC (0x02U) +#define EXTI_PortSourceGPIOD (0x03U) +#define EXTI_PortSourceGPIOE (0x04U) +#define EXTI_PortSourceGPIOF (0x05U) + +#define EXTI_PinSource0 (0x00U) +#define EXTI_PinSource1 (0x01U) +#define EXTI_PinSource2 (0x02U) +#define EXTI_PinSource3 (0x03U) +#define EXTI_PinSource4 (0x04U) +#define EXTI_PinSource5 (0x05U) +#define EXTI_PinSource6 (0x06U) +#define EXTI_PinSource7 (0x07U) +#define EXTI_PinSource8 (0x08U) +#define EXTI_PinSource9 (0x09U) +#define EXTI_PinSource10 (0x0AU) +#define EXTI_PinSource11 (0x0BU) +#define EXTI_PinSource12 (0x0CU) +#define EXTI_PinSource13 (0x0DU) +#define EXTI_PinSource14 (0x0EU) +#define EXTI_PinSource15 (0x0FU) + + + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup EXTI_Exported_Variables +/// @{ + +#ifdef _HAL_EXTI_C_ + +#define GLOBAL +#else +#define GLOBAL extern +#endif + +#undef GLOBAL + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup EXTI_Exported_Functions +/// @{ + +FlagStatus EXTI_GetFlagStatus(u32 line); +ITStatus EXTI_GetITStatus(u32 line); + +void EXTI_DeInit(void); +void EXTI_Init(EXTI_InitTypeDef* init_struct); +void EXTI_StructInit(EXTI_InitTypeDef* init_struct); +void EXTI_GenerateSWInterrupt(u32 line); +void EXTI_ClearFlag(u32 line); +void EXTI_ClearITPendingBit(u32 line); +void exEXTI_LineDisable(u32 line); +u32 exEXTI_GetAllFlagStatus(void); + + +void EXTI_MemoryRemapConfig(u32 memory_remap); +void EXTI_LineConfig(u8 port_source_gpio, u8 pin_source); + + +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +#endif // __HAL_EXTI_H +//////////////////////////////////////////////////////////////////////////////// + + + diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_flash.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_flash.h new file mode 100644 index 000000000..ee313dee7 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_flash.h @@ -0,0 +1,230 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_flash.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE FLASH +/// FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#ifndef __HAL_FLASH_H +#define __HAL_FLASH_H + +// Files includes +#include "types.h" +#include "reg_common.h" +#include "reg_flash.h" + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup FLASH_HAL +/// @brief FLASH HAL modules +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup FLASH_Exported_Types +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @brief FLASH Status +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + FLASH_BUSY = 1, ///< FLASH busy status + FLASH_ERROR_PG, ///< FLASH programming error status + FLASH_ERROR_WRP, ///< FLASH write protection error status + FLASH_COMPLETE, ///< FLASH end of operation status + FLASH_TIMEOUT ///< FLASH Last operation timed out status +} FLASH_Status; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief FLASH Latency +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + FLASH_Latency_0 = FLASH_ACR_LATENCY_0, ///< FLASH Zero Latency cycle + FLASH_Latency_1 = FLASH_ACR_LATENCY_1, ///< FLASH One Latency cycle + FLASH_Latency_2 = FLASH_ACR_LATENCY_2, ///< FLASH Two Latency cycles + FLASH_Latency_3 = FLASH_ACR_LATENCY_3 ///< FLASH Three Latency cycles +} FLASH_Latency_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Half_Cycle_Enable_Disable +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + FLASH_HalfCycleAccess_Enable = FLASH_ACR_HLFCYA, ///< FLASH Half Cycle Enable + FLASH_HalfCycleAccess_Disable = (s32)~FLASH_ACR_HLFCYA ///< FLASH Half Cycle Disable +} FLASH_HalfCycleAccess_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Prefetch_Buffer_Enable_Disable +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + FLASH_PrefetchBuffer_Enable = FLASH_ACR_PRFTBE, ///< FLASH Prefetch Buffer Enable + FLASH_PrefetchBuffer_Disable = (s32)~FLASH_ACR_PRFTBE ///< FLASH Prefetch Buffer Disable +} FLASH_PrefetchBuffer_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Option_Bytes_IWatchdog +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + OB_IWDG_SW = 0x0001, ///< Software IWDG selected + OB_IWDG_HW = 0x0000 ///< Hardware IWDG selected +} OB_IWDG_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Option_Bytes_nRST_STOP +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + OB_STOP_NoRST = 0x0002, ///< No reset generated when entering in STOP + OB_STOP_RST = 0x0000 ///< Reset generated when entering in STOP +} OB_STOP_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Option_Bytes_nRST_STDBY +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + OB_STDBY_NoRST = 0x0004, ///< No reset generated when entering in STANDBY + OB_STDBY_RST = 0x0000 ///< Reset generated when entering in STANDBY +} OB_STDBY_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief FLASH_Interrupts +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + FLASH_IT_ERROR = FLASH_CR_ERRIE, ///< FPEC error interrupt source + FLASH_IT_EOP = FLASH_CR_EOPIE ///< End of FLASH Operation Interrupt source +} FLASH_IT_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief FLASH_Flags +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + FLASH_FLAG_EOP = FLASH_SR_EOP, ///< FLASH End of Operation flag + FLASH_FLAG_PGERR = FLASH_SR_PGERR, ///< FLASH Program error flag + FLASH_FLAG_WRPRTERR = FLASH_SR_WRPRTERR, ///< FLASH Write protected error flag + FLASH_FLAG_BSY = FLASH_SR_BUSY, ///< FLASH Busy flag + FLASH_FLAG_OPTERR = FLASH_OBR_OPTERR ///< FLASH Option Byte error flag +} FLASH_FLAG_TypeDef; + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup FLASH_Exported_Constants +/// @{ + + +#define RDP_Key ((u16)0x00A5) +#define FLASH_KEY1 ((u32)0x45670123) +#define FLASH_KEY2 ((u32)0xCDEF89AB) +#define EraseTimeout ((u32)0x00000FFF) +#define ProgramTimeout ((u32)0x0000000F) + +#define FLASH_WRProt_Pages0to3 ((u32)0x00000001) ///< Write protection of page 0 to 3 +#define FLASH_WRProt_Pages4to7 ((u32)0x00000002) ///< Write protection of page 4 to 7 +#define FLASH_WRProt_Pages8to11 ((u32)0x00000004) ///< Write protection of page 8 to 11 +#define FLASH_WRProt_Pages12to15 ((u32)0x00000008) ///< Write protection of page 12 to 15 +#define FLASH_WRProt_Pages16to19 ((u32)0x00000010) ///< Write protection of page 16 to 19 +#define FLASH_WRProt_Pages20to23 ((u32)0x00000020) ///< Write protection of page 20 to 23 +#define FLASH_WRProt_Pages24to27 ((u32)0x00000040) ///< Write protection of page 24 to 27 +#define FLASH_WRProt_Pages28to31 ((u32)0x00000080) ///< Write protection of page 28 to 31 +#define FLASH_WRProt_Pages32to35 ((u32)0x00000100) ///< Write protection of page 32 to 35 +#define FLASH_WRProt_Pages36to39 ((u32)0x00000200) ///< Write protection of page 36 to 39 +#define FLASH_WRProt_Pages40to43 ((u32)0x00000400) ///< Write protection of page 40 to 43 +#define FLASH_WRProt_Pages44to47 ((u32)0x00000800) ///< Write protection of page 44 to 47 +#define FLASH_WRProt_Pages48to51 ((u32)0x00001000) ///< Write protection of page 48 to 51 +#define FLASH_WRProt_Pages52to55 ((u32)0x00002000) ///< Write protection of page 52 to 55 +#define FLASH_WRProt_Pages56to59 ((u32)0x00004000) ///< Write protection of page 56 to 59 +#define FLASH_WRProt_Pages60to63 ((u32)0x00008000) ///< Write protection of page 60 to 63 +#define FLASH_WRProt_Pages64to67 ((u32)0x00010000) ///< Write protection of page 64 to 67 +#define FLASH_WRProt_Pages68to71 ((u32)0x00020000) ///< Write protection of page 68 to 71 +#define FLASH_WRProt_Pages72to75 ((u32)0x00040000) ///< Write protection of page 72 to 75 +#define FLASH_WRProt_Pages76to79 ((u32)0x00080000) ///< Write protection of page 76 to 79 +#define FLASH_WRProt_Pages80to83 ((u32)0x00100000) ///< Write protection of page 80 to 83 +#define FLASH_WRProt_Pages84to87 ((u32)0x00200000) ///< Write protection of page 84 to 87 +#define FLASH_WRProt_Pages88to91 ((u32)0x00400000) ///< Write protection of page 88 to 91 +#define FLASH_WRProt_Pages92to95 ((u32)0x00800000) ///< Write protection of page 92 to 95 +#define FLASH_WRProt_Pages96to99 ((u32)0x01000000) ///< Write protection of page 96 to 99 +#define FLASH_WRProt_Pages100to103 ((u32)0x02000000) ///< Write protection of page 100 to 103 +#define FLASH_WRProt_Pages104to107 ((u32)0x04000000) ///< Write protection of page 104 to 107 +#define FLASH_WRProt_Pages108to111 ((u32)0x08000000) ///< Write protection of page 108 to 111 +#define FLASH_WRProt_Pages112to115 ((u32)0x10000000) ///< Write protection of page 112 to 115 +#define FLASH_WRProt_Pages116to119 ((u32)0x20000000) ///< Write protection of page 115 to 119 +#define FLASH_WRProt_Pages120to123 ((u32)0x40000000) ///< Write protection of page 120 to 123 +#define FLASH_WRProt_Pages124to127 ((u32)0x80000000) ///< Write protection of page 124 to 127 + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup FLASH_Exported_Variables +/// @{ + +#ifdef _HAL_FLASH_C_ + +#define GLOBAL +#else +#define GLOBAL extern +#endif + +#undef GLOBAL + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup FLASH_Exported_Functions +/// @{ +void FLASH_SetLatency(FLASH_Latency_TypeDef latency); +void FLASH_HalfCycleAccessCmd(FLASH_HalfCycleAccess_TypeDef half_cycle_access); +void FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_TypeDef prefetch_buffer); +void FLASH_Unlock(void); +void FLASH_Lock(void); +void FLASH_OPTB_Enable(void); +void FLASH_ITConfig(FLASH_IT_TypeDef interrupt, FunctionalState state); +void FLASH_ClearFlag(u16 flag); +void exFLASH_EraseEE(u32 page_address); +void exFLASH_ProgramEE(u16* buf, u32 address, u16 len); +void exFLASH_WriteEE(u16* buf, u32 page_address, u16 len); +void* exFLASH_Locate(u32 page_address, u16 len); +void* exFLASH_ReadEE(u32 page_address, u16 len); + +u8 exFLASH_FindEmpty(u16* ptr, u16 len); +u32 FLASH_GetUserOptionByte(void); +u32 FLASH_GetWriteProtectionOptionByte(void); + +FLASH_Status FLASH_ErasePage(u32 page_address); +FLASH_Status FLASH_EraseAllPages(void); +FLASH_Status FLASH_EraseOptionBytes(void); +FLASH_Status FLASH_EraseProtect(void); +FLASH_Status FLASH_ProgramHalfWord(u32 address, u16 data); +FLASH_Status FLASH_ProgramWord(u32 address, u32 data); +FLASH_Status FLASH_ProgramOptionHalfWord(u32 address, u16 data); +FLASH_Status FLASH_ProgramOptionByteData(u32 address, u8 data); +FLASH_Status FLASH_ProgramProtect(u32 address, u16 data); +FLASH_Status FLASH_EnableWriteProtection(u32 page); +FLASH_Status FLASH_UserOptionByteConfig(OB_IWDG_TypeDef ob_iwdg, OB_STOP_TypeDef ob_stop, OB_STDBY_TypeDef ob_standby); +FLASH_Status FLASH_GetStatus(void); +FLASH_Status FLASH_WaitForLastOperation(u32 time_out); +FLASH_Status FLASH_ReadOutProtection(FunctionalState state); +FlagStatus FLASH_GetPrefetchBufferStatus(void); +FlagStatus FLASH_GetFlagStatus(u16 flag); + +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +#endif //__HAL_FLASH_H +//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_fsmc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_fsmc.h new file mode 100644 index 000000000..dbfe38166 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_fsmc.h @@ -0,0 +1,147 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_fsmc.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SDIO +/// FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#ifndef __HAL_FSMC_H +#define __HAL_FSMC_H + +// Files includes +#include "types.h" +#include "reg_common.h" +#include "reg_fsmc.h" + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup FSMC_HAL +/// @brief FSMC HAL modules +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup FSMC_Exported_Types +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @brief FSMC_interrupts_define +//////////////////////////////////////////////////////////////////////////////// + + + + + +// Timing parameter configuration register set selection register set0 register set1 register set2 + +#define FSMC_TimingRegSelect_0 ((u32)0x00000000) +#define FSMC_TimingRegSelect_1 ((u32)0x00000100) +#define FSMC_TimingRegSelect_2 ((u32)0x00000200) + +// Capacity of external device +#define FSMC_MemSize_None ((u32)0x00000000) +#define FSMC_MemSize_64KB ((u32)0x00000001) +#define FSMC_MemSize_128KB ((u32)0x00000002) +#define FSMC_MemSize_256KB ((u32)0x00000002) +#define FSMC_MemSize_512KB ((u32)0x00000004) +#define FSMC_MemSize_1MB ((u32)0x00000005) +#define FSMC_MemSize_2MB ((u32)0x00000006) +#define FSMC_MemSize_4MB ((u32)0x00000007) +#define FSMC_MemSize_8MB ((u32)0x00000008) +#define FSMC_MemSize_16MB ((u32)0x00000009) +#define FSMC_MemSize_32MB ((u32)0x0000000A) +#define FSMC_MemSize_64MB ((u32)0x0000000B) +#define FSMC_MemSize_128MB ((u32)0x0000000C) +#define FSMC_MemSize_256MB ((u32)0x0000000D) +#define FSMC_MemSize_512MB ((u32)0x0000000E) +#define FSMC_MemSize_1GB ((u32)0x0000000F) +#define FSMC_MemSize_2GB ((u32)0x00000010) +#define FSMC_MemSize_4GB ((u32)0x00000011) + + +// Memory data bus bit width setting +typedef enum { + FSMC_DataWidth_16bits = (0x0000), //16bits + FSMC_DataWidth_32bits = (0x0001), //32bits + FSMC_DataWidth_64bits = (0x0002), //64bits + FSMC_DataWidth_128bits = (0x0003), //128bits + FSMC_DataWidth_8bits = (0x0004), //8bits +} FSMC_NORSRAM_DataWidth_TypeDef; + +typedef enum { + FSMC_NORSRAM_BANK0 = 0, + FSMC_NORSRAM_BANK1 = 1, + FSMC_NORSRAM_BANK2 = 2, +} FSMC_NORSRAM_BANK_TypeDef; + +typedef struct { + u32 FSMC_SMReadPipe; //sm_read_pipe[1:0] The cycle of latching read data, that is, the cycle when ready_resp is pulled high + + u32 FSMC_ReadyMode; //Select whether the hready_resp signal comes from the FSMC IP internal or external DEVICE, only for writing and reading external DEVICE operations. + //0: Internal FSMC 1: External DEVICE (ie from FSMC_NWAIT) + u32 FSMC_WritePeriod; //Write cycle + + u32 FSMC_WriteHoldTime; //Address/data hold time during write operation + + u32 FSMC_AddrSetTime; //Address establishment time + + u32 FSMC_ReadPeriod; //Read cycle + + FSMC_NORSRAM_DataWidth_TypeDef FSMC_DataWidth; + +} FSMC_NORSRAM_Bank_InitTypeDef; + +typedef struct { + u32 FSMC_Mode; + u32 FSMC_TimingRegSelect; + u32 FSMC_MemSize; + u32 FSMC_MemType; + u32 FSMC_AddrDataMode; +} FSMC_InitTypeDef; + + +#define FSMC_MemType_SDRAM ((u32)0x0<<5) +#define FSMC_MemType_NorSRAM ((u32)0x1<<5) +#define FSMC_MemType_FLASH ((u32)0x2<<5) +#define FSMC_MemType_RESERVED ((u32)0x3<<5) +//SYSCFG_CFGR1 +#define FSMC_Mode_6800 ((u32)0x40000000) +#define FSMC_Mode_8080 ((u32)0x20000000) +#define FSMC_Mode_NorFlash ((u32)0x00000000) + +#define FSMC_AddrDataMUX ((u32)0x00000000) +#define FSMC_AddrDataDeMUX ((u32)0x10000000) + + + + +void FSMC_NORSRAMStructInit(FSMC_InitTypeDef* init_struct); +void FSMC_NORSRAM_BankStructInit(FSMC_NORSRAM_Bank_InitTypeDef* init_struct); +void FSMC_NORSRAMInit(FSMC_InitTypeDef* init_struct); +void FSMC_NORSRAM_Bank_Init(FSMC_NORSRAM_Bank_InitTypeDef* FSMC_Bank_InitStruct, FSMC_NORSRAM_BANK_TypeDef bank); + + + +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +#endif // __HAL_FSMC_H +//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_gpio.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_gpio.h new file mode 100644 index 000000000..b28afd839 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_gpio.h @@ -0,0 +1,198 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_gpio.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE GPIO +/// FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#ifndef __HAL_GPIO_H +#define __HAL_GPIO_H + +// Files includes +#include "types.h" +#include "reg_gpio.h" + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup GPIO_HAL +/// @brief GPIO HAL modules +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup GPIO_Exported_Types +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Output Maximum frequency selection +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + GPIO_Speed_50MHz = 1, ///< Maximum speed is 50MHz + GPIO_Speed_20MHz, ///< Maximum speed is 20MHz + GPIO_Speed_10MHz ///< Maximum speed is 10MHz +} GPIOSpeed_TypeDef; + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configuration Mode enumeration +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + GPIO_Mode_AIN = 0x00, ///< Analog input + GPIO_Mode_FLOATING = 0x04, ///< Floating input + GPIO_Mode_IPD = 0x28, ///< Pull down input + GPIO_Mode_IPU = 0x48, ///< Pull up input + GPIO_Mode_Out_OD = 0x14, ///< Universal open drain output + GPIO_Mode_Out_PP = 0x10, ///< Universal push-pull output + GPIO_Mode_AF_OD = 0x1C, ///< Multiplex open drain output + GPIO_Mode_AF_PP = 0x18 ///< Multiplexed push-pull output +} GPIOMode_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Bit_SET and Bit_RESET enumeration +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + Bit_RESET = 0, ///< bit reset + Bit_SET ///< bit set +} BitAction; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief GPIO Init structure definition +//////////////////////////////////////////////////////////////////////////////// +typedef struct { + u16 GPIO_Pin; ///< GPIO_Pin + GPIOSpeed_TypeDef GPIO_Speed; ///< GPIO_Speed + GPIOMode_TypeDef GPIO_Mode; ///< GPIO_Mode +} GPIO_InitTypeDef; + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup GPIO_Exported_Constants +/// @{ + +#define GPIO_Speed_2MHz GPIO_Speed_20MHz + +#define GPIO_Pin_0 (0x0001U) ///< Pin 0 selected +#define GPIO_Pin_1 (0x0002U) ///< Pin 1 selected +#define GPIO_Pin_2 (0x0004U) ///< Pin 2 selected +#define GPIO_Pin_3 (0x0008U) ///< Pin 3 selected +#define GPIO_Pin_4 (0x0010U) ///< Pin 4 selected +#define GPIO_Pin_5 (0x0020U) ///< Pin 5 selected +#define GPIO_Pin_6 (0x0040U) ///< Pin 6 selected +#define GPIO_Pin_7 (0x0080U) ///< Pin 7 selected +#define GPIO_Pin_8 (0x0100U) ///< Pin 8 selected +#define GPIO_Pin_9 (0x0200U) ///< Pin 9 selected +#define GPIO_Pin_10 (0x0400U) ///< Pin 10 selected +#define GPIO_Pin_11 (0x0800U) ///< Pin 11 selected +#define GPIO_Pin_12 (0x1000U) ///< Pin 12 selected +#define GPIO_Pin_13 (0x2000U) ///< Pin 13 selected +#define GPIO_Pin_14 (0x4000U) ///< Pin 14 selected +#define GPIO_Pin_15 (0x8000U) ///< Pin 15 selected +#define GPIO_Pin_All (0xFFFFU) ///< All pins selected + + +#define GPIO_AF_0 (0x00U) ///< Alternative function 0 +#define GPIO_AF_1 (0x01U) ///< Alternative function 1 +#define GPIO_AF_2 (0x02U) ///< Alternative function 2 +#define GPIO_AF_3 (0x03U) ///< Alternative function 3 +#define GPIO_AF_4 (0x04U) ///< Alternative function 4 +#define GPIO_AF_5 (0x05U) ///< Alternative function 5 +#define GPIO_AF_6 (0x06U) ///< Alternative function 6 +#define GPIO_AF_7 (0x07U) ///< Alternative function 7 +#define GPIO_AF_8 (0x08U) ///< Alternative function 8 +#define GPIO_AF_9 (0x09U) ///< Alternative function 9 +#define GPIO_AF_10 (0x0AU) ///< Alternative function 10 +#define GPIO_AF_11 (0x0BU) ///< Alternative function 11 +#define GPIO_AF_12 (0x0CU) ///< Alternative function 12 +#define GPIO_AF_13 (0x0DU) ///< Alternative function 13 +#define GPIO_AF_14 (0x0EU) ///< Alternative function 14 +#define GPIO_AF_15 (0x0FU) ///< Alternative function 15 +#define GPIO_PortSourceGPIOA (0x00U) +#define GPIO_PortSourceGPIOB (0x01U) +#define GPIO_PortSourceGPIOC (0x02U) +#define GPIO_PortSourceGPIOD (0x03U) + +#define GPIO_PinSource0 (0x00U) +#define GPIO_PinSource1 (0x01U) +#define GPIO_PinSource2 (0x02U) +#define GPIO_PinSource3 (0x03U) +#define GPIO_PinSource4 (0x04U) +#define GPIO_PinSource5 (0x05U) +#define GPIO_PinSource6 (0x06U) +#define GPIO_PinSource7 (0x07U) +#define GPIO_PinSource8 (0x08U) +#define GPIO_PinSource9 (0x09U) +#define GPIO_PinSource10 (0x0AU) +#define GPIO_PinSource11 (0x0BU) +#define GPIO_PinSource12 (0x0CU) +#define GPIO_PinSource13 (0x0DU) +#define GPIO_PinSource14 (0x0EU) +#define GPIO_PinSource15 (0x0FU) + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup GPIO_Exported_Variables +/// @{ + +#ifdef _HAL_GPIO_C_ + +#define GLOBAL +#else +#define GLOBAL extern +#endif + + + +#undef GLOBAL + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup GPIO_Exported_Functions +/// @{ +void GPIO_DeInit(GPIO_TypeDef* gpio); +void GPIO_AFIODeInit(void); +void GPIO_Init(GPIO_TypeDef* gpio, GPIO_InitTypeDef* init_struct); +void GPIO_StructInit(GPIO_InitTypeDef* init_struct); +void GPIO_SetBits(GPIO_TypeDef* gpio, u16 pin); +void GPIO_ResetBits(GPIO_TypeDef* gpio, u16 pin); +void GPIO_WriteBit(GPIO_TypeDef* gpio, u16 pin, BitAction value); +void GPIO_Write(GPIO_TypeDef* gpio, u16 value); +void GPIO_PinLock(GPIO_TypeDef* gpio, u16 pin, FunctionalState state); +void GPIO_PinLockConfig(GPIO_TypeDef* gpio, u16 pin); +bool GPIO_ReadInputDataBit(GPIO_TypeDef* gpio, u16 pin); +bool GPIO_ReadOutputDataBit(GPIO_TypeDef* gpio, u16 pin); + +u16 GPIO_ReadInputData(GPIO_TypeDef* gpio); +u16 GPIO_ReadOutputData(GPIO_TypeDef* gpio); + + +void GPIO_PinAFConfig(GPIO_TypeDef* gpio, u8 pin, u8 alternate_function); + +void exGPIO_PinAFConfig(GPIO_TypeDef* gpio, u16 pin, s32 remap, s8 alternate_function); + + +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +#endif // __HAL_GPIO_H +//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_i2c.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_i2c.h new file mode 100644 index 000000000..42a9ab55f --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_i2c.h @@ -0,0 +1,255 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_i2c.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE I2C +/// FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#ifndef __HAL_I2C_H +#define __HAL_I2C_H + +// Files includes +#include "types.h" +#include "reg_i2c.h" + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup I2C_HAL +/// @brief I2C HAL modules +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup I2C_Exported_Types +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup DRV_Exported_Constants +/// @{ + +#define I2C_OWN_ADDRESS 0x20 + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief I2C Init structure definition +//////////////////////////////////////////////////////////////////////////////// +typedef struct { + union { + u16 Mode; ///< Specifies the I2C mode. This parameter can be a value of I2C_mode. + u16 I2C_Mode; + }; + union { + u16 Speed; ///< Specifies the I2C speed. This parameter can be a value of I2C_speed. + u16 I2C_Speed; + }; + union { + u16 OwnAddress; ///< Specifies the first device own address. This parameter can be a 7-bit or 10-bit address. + u16 I2C_OwnAddress; + }; + + union { + u32 ClockSpeed; ///< Specifies the clock speed. + u32 I2C_ClockSpeed; + }; +} I2C_InitTypeDef; +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup I2C_Exported_Constants +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @brief I2C DMA Direction +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + RDMAE_SET = 1, // 1 - DMA read + TDMAE_SET // 2 - DMA transmit +} I2C_DMA_Dir_TypeDef; +//////////////////////////////////////////////////////////////////////////////// +/// @brief I2C Transfer Direction +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + I2C_Direction_Transmitter, // I2C Transmitter + I2C_Direction_Receiver // I2C Receiver +} I2C_Trans_Dir_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief I2C Acknowledged Address +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + I2C_AcknowledgedAddress_7bit = 0x4000, // 7-bit address + I2C_AcknowledgedAddress_10bit = 0xC000 // 10-bit address +} I2C_ACKaddr_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup I2C_Private_Defines +/// @{ +#define INTR_MASK ((u16)0xC000) +#define FLAG_Mask ((u32)0x00793FFF) +#define IC_TAR_ENDUAL_Set ((u16)0x1000) +#define IC_TAR_ENDUAL_Reset ((u16)0xEFFF) +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup I2C_modes +/// @{ +#define TX_EMPTY_CTRL I2C_CR_EMPINT +#define IC_SLAVE_DISABLE I2C_CR_SLAVEDIS +#define IC_RESTART_EN I2C_CR_REPEN +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup I2C_interrupts_definition +/// @{ +#define I2C_IT_RX_UNDER ((u16)0x0001) +#define I2C_IT_RX_OVER ((u16)0x0002) +#define I2C_IT_RX_FULL ((u16)0x0004) +#define I2C_IT_TX_OVER ((u16)0x0008) +#define I2C_IT_TX_EMPTY ((u16)0x0010) +#define I2C_IT_RD_REQ ((u16)0x0020) +#define I2C_IT_TX_ABRT ((u16)0x0040) +#define I2C_IT_RX_DONE ((u16)0x0080) +#define I2C_IT_ACTIVITY ((u16)0x0100) +#define I2C_IT_STOP_DET ((u16)0x0200) +#define I2C_IT_START_DET ((u16)0x0400) +#define I2C_IT_GEN_CALL ((u16)0x0800) +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup I2C_flags_definition +/// @{ +#define I2C_FLAG_RX_UNDER ((u16)0x0001) +#define I2C_FLAG_RX_OVER ((u16)0x0002) +#define I2C_FLAG_RX_FULL ((u16)0x0004) +#define I2C_FLAG_TX_OVER ((u16)0x0008) +#define I2C_FLAG_TX_EMPTY ((u16)0x0010) +#define I2C_FLAG_RD_REQ ((u16)0x0020) +#define I2C_FLAG_TX_ABRT ((u16)0x0040) +#define I2C_FLAG_RX_DONE ((u16)0x0080) +#define I2C_FLAG_ACTIVITY ((u16)0x0100) +#define I2C_FLAG_STOP_DET ((u16)0x0200) +#define I2C_FLAG_START_DET ((u16)0x0400) +#define I2C_FLAG_GEN_CALL ((u16)0x0800) +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup I2C_Events +/// @{ +#define I2C_EVENT_RX_UNDER ((u16)0x0001) +#define I2C_EVENT_RX_OVER ((u16)0x0002) +#define I2C_EVENT_RX_FULL ((u16)0x0004) +#define I2C_EVENT_TX_OVER ((u16)0x0008) +#define I2C_EVENT_TX_EMPTY ((u16)0x0010) +#define I2C_EVENT_RD_REQ ((u16)0x0020) +#define I2C_EVENT_TX_ABRT ((u16)0x0040) +#define I2C_EVENT_RX_DONE ((u16)0x0080) +#define I2C_EVENT_ACTIVITY ((u16)0x0100) +#define I2C_EVENT_STOP_DET ((u16)0x0200) +#define I2C_EVENT_START_DET ((u16)0x0400) +#define I2C_EVENT_GEN_CALL ((u16)0x0800) +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup I2C_Statusflags_definition +/// @{ +#define I2C_STATUS_FLAG_ACTIVITY ((u16)0x8001) +#define I2C_STATUS_FLAG_TFNF ((u16)0x8002) +#define I2C_STATUS_FLAG_TFE ((u16)0x8004) +#define I2C_STATUS_FLAG_RFNE ((u16)0x8008) +#define I2C_STATUS_FLAG_RFF ((u16)0x8010) +#define I2C_STATUS_FLAG_M_ACTIVITY ((u16)0x8020) +#define I2C_STATUS_FLAG_S_ACTIVITY ((u16)0x8040) +/// @} + + + +#define IC_SLAVE_ENABLE (0x0000<<6) +#define IC_7BITADDR_MASTER (0x0000<<4) +#define IC_7BITADDR_SLAVE (0x0000<<3) +#define I2C_Speed_STANDARD ((u16)0x0002) +#define I2C_Speed_FAST ((u16)0x0004) +#define I2C_Mode_MASTER ((u16)0x0001) +#define I2C_Mode_SLAVE ((u16)0x0000) +#define CMD_READ ((u16)0x0100) +#define CMD_WRITE ((u16)0x0000) +#define I2C_Mode_I2C ((u16)0x0000) + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup I2C_Exported_Variables +/// @{ +#ifdef _HAL_I2C_C_ + +#define GLOBAL + +static u8 I2C_CMD_DIR = 0; +u16 I2C_DMA_DIR = 0; + +#else +#define GLOBAL extern +#endif + +#undef GLOBAL +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup I2C_Exported_Functions +/// @{ +void I2C_DeInit(I2C_TypeDef* i2c); +void I2C_Init(I2C_TypeDef* i2c, I2C_InitTypeDef* init_struct); +void I2C_StructInit(I2C_InitTypeDef* init_struct); +void I2C_Cmd(I2C_TypeDef* i2c, FunctionalState state); +void I2C_DMACmd(I2C_TypeDef* i2c, FunctionalState state); +void I2C_GenerateSTART(I2C_TypeDef* i2c, FunctionalState state); +void I2C_GenerateSTOP(I2C_TypeDef* i2c, FunctionalState state); +void I2C_OwnAddress2Config(I2C_TypeDef* i2c, u8 addr); +void I2C_DualAddressCmd(I2C_TypeDef* i2c, FunctionalState state); +void I2C_GeneralCallCmd(I2C_TypeDef* i2c, FunctionalState state); +void I2C_ITConfig(I2C_TypeDef* i2c, u16 it, FunctionalState state); +void I2C_SendData(I2C_TypeDef* i2c, u8 dat); +void I2C_ReadCmd(I2C_TypeDef* i2c); +void I2C_Send7bitAddress(I2C_TypeDef* i2c, u8 addr, u8 dir); +void I2C_ClearFlag(I2C_TypeDef* i2c, u32 flag); +void I2C_ClearITPendingBit(I2C_TypeDef* i2c, u32 it); + +u8 I2C_ReceiveData(I2C_TypeDef* i2c); +u16 I2C_ReadRegister(I2C_TypeDef* i2c, u8 reg); +u32 I2C_GetLastEvent(I2C_TypeDef* i2c); + +ErrorStatus I2C_CheckEvent(I2C_TypeDef* i2c, u32 event); +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* i2c, u32 flag); +ITStatus I2C_GetITStatus(I2C_TypeDef* i2c, u32 it); + +//////////////////////////////////////////////////////////////////////////////// +// Extended function interface +//////////////////////////////////////////////////////////////////////////////// +void I2C_SendSlaveAddress(I2C_TypeDef* i2c, u8 addr); +void I2C_SlaveConfigure(I2C_TypeDef* i2c, FunctionalState state); +void I2C_DMAConfigure(I2C_TypeDef* i2c, u8 dir); + + +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +#endif //__HAL_I2C_H +//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_iwdg.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_iwdg.h new file mode 100644 index 000000000..e0b86d7b7 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_iwdg.h @@ -0,0 +1,130 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_iwdg.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE IWDG +/// FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#ifndef __HAL_IWDG_H +#define __HAL_IWDG_H + +// Files includes +#include "types.h" +#include "reg_iwdg.h" +#include "reg_common.h" + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup IWDG_HAL +/// @brief IWDG HAL modules +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup IWDG_Exported_Constants +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @brief IWDG prescaler +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + IWDG_Prescaler_4 = IWDG_PR_PRE_DIV4, + IWDG_Prescaler_8 = IWDG_PR_PRE_DIV8, + IWDG_Prescaler_16 = IWDG_PR_PRE_DIV16, + IWDG_Prescaler_32 = IWDG_PR_PRE_DIV32, + IWDG_Prescaler_64 = IWDG_PR_PRE_DIV64, + IWDG_Prescaler_128 = IWDG_PR_PRE_DIV128, + IWDG_Prescaler_256 = IWDG_PR_PRE_DIV256 +} IWDGPrescaler_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief IWDG flag +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + IWDG_FLAG_PVU = 0x0001, // IWDG prescaler value update flag + IWDG_FLAG_RVU = 0x0002 // IWDG counter reload value update flag +} IWDGFlag_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Write access to IWDG_PR and IWDG_RLR registers +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + IWDG_WriteAccess_Enable = 0x5555, // Enable write + IWDG_WriteAccess_Disable = 0x0000 // Disable write +} IWDGWriteAccess_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief IWDG Key Reload +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + KR_KEY_Reload = 0xAAAA, // Reload value + KR_KEY_Enable = 0xCCCC // Start IWDG +} IWDGKey_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief IWDG Overflow Configration +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + IWDG_Overflow_Reset = 0, // + IWDG_Overflow_Interrupt = IWDG_CR_IRQSEL // +} IWDGOverflowConfig_TypeDef; + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup IWDG_Exported_Variables +/// @{ +#ifdef _HAL_IWDG_C_ +#define GLOBAL + +#else +#define GLOBAL extern +#endif + + +#undef GLOBAL +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup IWDG_Exported_Functions +/// @{ +FlagStatus IWDG_GetFlagStatus(u16 flag); + +void IWDG_WriteAccessCmd(u16 write_access); +void IWDG_SetPrescaler(u8 prescaler); +void IWDG_SetReload(u16 reload); +u32 IWDG_GetReload(void); +void IWDG_ReloadCounter(void); +void IWDG_Enable(void); +void PVU_CheckStatus(void); +void RVU_CheckStatus(void); + +void IWDG_OverflowConfig(IWDGOverflowConfig_TypeDef overflow_config); +void IWDG_ClearITPendingBit(void); +void IWDG_EnableIT(void); +void IWDG_Reset(void); +void IWDG_ClearIT(void); + +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +#endif // __HAL_IWDG_H +//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_misc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_misc.h new file mode 100644 index 000000000..0b7429963 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_misc.h @@ -0,0 +1,128 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_misc.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE NVIC +/// FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#ifndef __HAL_MISC_H +#define __HAL_MISC_H + +// Files includes +#include "types.h" +#include "reg_common.h" + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup NVIC_HAL +/// @brief NVIC HAL modules +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup NVIC_Exported_Types +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @brief NVIC Init Structure definition +//////////////////////////////////////////////////////////////////////////////// +typedef struct { + u8 NVIC_IRQChannel; + u8 NVIC_IRQChannelPreemptionPriority; + u8 NVIC_IRQChannelSubPriority; + FunctionalState NVIC_IRQChannelCmd; +} NVIC_InitTypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief NVIC New Init Structure definition +//////////////////////////////////////////////////////////////////////////////// +typedef struct { + u8 NVIC_IRQChannel; + u8 NVIC_IRQChannelPreemptionPriority; // Cortex-M0 not used + u8 NVIC_IRQChannelSubPriority; + FunctionalState NVIC_IRQChannelCmd; +} exNVIC_Init_TypeDef; + +/// @} +//////////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup NVIC_Exported_Constants +/// @{ + +#define NVIC_VectTab_RAM (0x20000000U) +#define NVIC_VectTab_FLASH (0x08000000U) + +#define NVIC_LP_SEVONPEND (0x10U) +#define NVIC_LP_SLEEPDEEP (0x04U) +#define NVIC_LP_SLEEPONEXIT (0x02U) + +#define NVIC_PriorityGroup_0 (0x0700U) // 0 bits for pre-emption priority 4 bits for subpriority +#define NVIC_PriorityGroup_1 (0x0600U) // 1 bits for pre-emption priority 3 bits for subpriority +#define NVIC_PriorityGroup_2 (0x0500U) // 2 bits for pre-emption priority 2 bits for subpriority +#define NVIC_PriorityGroup_3 (0x0400U) // 3 bits for pre-emption priority 1 bits for subpriority +#define NVIC_PriorityGroup_4 (0x0300U) // 4 bits for pre-emption priority 0 bits for subpriority + +#define AIRCR_VECTKEY_MASK (0x05FA0000U) + +#define SysTick_CLKSource_HCLK_Div8 (0xFFFFFFFBU) + + +#define SysTick_CLKSource_EXTCLK (0xFFFFFFFBU) +#define SysTick_CLKSource_HCLK (0x00000004U) +/// @} + + + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup NVIC_Exported_Variables +/// @{ + +#ifdef _HAL_NVIC_C_ + +#define GLOBAL +#else +#define GLOBAL extern +#endif + +#undef GLOBAL + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup NVIC_Exported_Functions +/// @{ + +void NVIC_PriorityGroupConfig(u32 priority_group); +void NVIC_SetVectorTable(u32 vect_tab, u32 offset); + +void NVIC_SystemLPConfig(u8 low_power_mode, FunctionalState state); +void NVIC_Init(NVIC_InitTypeDef* init_struct); + +void SysTick_CLKSourceConfig(u32 systick_clk_source); + +void exNVIC_Init(exNVIC_Init_TypeDef* init_struct); + +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +#endif // __HAL_NVIC_H +//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_pwr.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_pwr.h new file mode 100644 index 000000000..f7837ca8d --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_pwr.h @@ -0,0 +1,156 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_pwr.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE PWR +/// FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#ifndef __HAL_PWR_H +#define __HAL_PWR_H + +// Files includes +#include "types.h" +#include "reg_pwr.h" +#include "reg_syscfg.h" +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup PWR_HAL +/// @brief PWR HAL modules +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup PWR_Exported_Types +/// @{ + +typedef enum { + emWUP_Pin1 = 0, + emWUP_Pin2 = 1, + emWUP_Pin3, + emWUP_Pin4, + emWUP_Pin5, + emWUP_Pin6, +} emWUP_Pin_Typedef; +//////////////////////////////////////////////////////////////////////////////// +/// @brief PVD_detection_level + +typedef enum { + emPVD_LEVEL0 = SYSCFG_PDETCSR_PLS_1V7, + emPVD_LEVEL1 = SYSCFG_PDETCSR_PLS_2V0, + emPVD_LEVEL2 = SYSCFG_PDETCSR_PLS_2V3, + emPVD_LEVEL3 = SYSCFG_PDETCSR_PLS_2V6, + emPVD_LEVEL4 = SYSCFG_PDETCSR_PLS_2V9, + emPVD_LEVEL5 = SYSCFG_PDETCSR_PLS_3V2, + emPVD_LEVEL6 = SYSCFG_PDETCSR_PLS_3V5, + emPVD_LEVEL7 = SYSCFG_PDETCSR_PLS_3V8, + emPVD_LEVEL8 = SYSCFG_PDETCSR_PLS_4V1, + emPVD_LEVEL9 = SYSCFG_PDETCSR_PLS_4V4, + emPVD_LEVEL10 = SYSCFG_PDETCSR_PLS_4V7 +} emPVD_Level_Typedef; +#define PWR_PVDLevel_1V7 SYSCFG_PDETCSR_PLS_1V7 +#define PWR_PVDLevel_2V0 SYSCFG_PDETCSR_PLS_2V0 +#define PWR_PVDLevel_2V3 SYSCFG_PDETCSR_PLS_2V3 +#define PWR_PVDLevel_2V6 SYSCFG_PDETCSR_PLS_2V6 +#define PWR_PVDLevel_2V9 SYSCFG_PDETCSR_PLS_2V9 +#define PWR_PVDLevel_3V2 SYSCFG_PDETCSR_PLS_3V2 +#define PWR_PVDLevel_3V5 SYSCFG_PDETCSR_PLS_3V5 +#define PWR_PVDLevel_3V8 SYSCFG_PDETCSR_PLS_3V8 +#define PWR_PVDLevel_4V1 SYSCFG_PDETCSR_PLS_4V1 +#define PWR_PVDLevel_4V4 SYSCFG_PDETCSR_PLS_4V4 +#define PWR_PVDLevel_4V7 SYSCFG_PDETCSR_PLS_4V7 +/// @brief Regulator_state_is_STOP_mode +typedef enum { + PWR_Regulator_ON = 0x00000000, + PWR_Regulator_LowPower = 0x00000001 + +} emPWR_Reg_Stop_mode_Typedef; + +/// @brief STOP_mode_entry +typedef enum { + PWR_STOPEntry_WFI = 0x00000001, + PWR_STOPEntry_WFE = 0x00000002 + +} emPWR_STOP_ModeEn_Typedef; + +/// @brief Low Power Mode +typedef enum { + LP_STOP_MODE = 0, + LP_SLEEP_MODE = 1, + LP_STANDBY_MODE = 2 +} emPWR_LP_Mode_Typedef; + +/// @brief Wait_for_mode +typedef enum { + LP_WFI, + LP_WFE +} emPWR_Wait_Mode_Typedef; +//typedef enum { +// PWR_FLAG_WU = PWR_CSR_WUF, +// PWR_FLAG_SB = PWR_CSR_SBF, + +// PWR_FLAG_PVDO = PWR_CSR_PVDO + + +//} emPWR_PWR_Flag_Typedef; + + +/// @} + +/////////////////////////////////////////////////////////////////////////////// +/// @defgroup PWR_Exported_Variables +/// @{ + +#ifdef _HAL_PWR_C_ + +#define GLOBAL +#else +#define GLOBAL extern +#endif + +#undef GLOBAL + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup PWR_Exported_Functions +/// @{ + +void PWR_DeInit(void); + +void PWR_BackupAccessCmd(FunctionalState state); + +void PWR_PVDCmd(FunctionalState state); +void PWR_PVDLevelConfig(emPVD_Level_Typedef pvd_level); +void PWR_WakeUpPinCmd(FunctionalState state); +void PWR_EnterSTOPMode(emPWR_Reg_Stop_mode_Typedef regulator, emPWR_STOP_ModeEn_Typedef stop_entry); +void PWR_EnterSTANDBYMode(void); + + +void PWR_ClearFlag(u32 flag); +FlagStatus PWR_GetFlagStatus(u32 flag); +FlagStatus PWR_GetPVDOFlagStatus(u32 flag); +void exPWR_EnterLowPowerMode(emPWR_LP_Mode_Typedef lp_mode, emPWR_Wait_Mode_Typedef wait_mode); + +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +#endif // __HAL_PWR_H +//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rcc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rcc.h new file mode 100644 index 000000000..deb916d4c --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rcc.h @@ -0,0 +1,329 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_rcc.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE RCC +/// FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#ifndef __HAL_RCC_H +#define __HAL_RCC_H + +// Files includes +#include "types.h" +#include "reg_common.h" +#include "mm32_reg.h" + + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup RCC_HAL +/// @brief RCC HAL modules +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup RCC_Exported_Types +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup RCC_Exported_Constants +/// @{ + + +/// @} + + + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup RCC_Exported_Enumeration +/// @{ + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief HSE configuration +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + RCC_HSE_OFF = 0, // HSE OFF + RCC_HSE_ON = RCC_CR_HSEON, // HSE ON + RCC_HSE_Bypass = RCC_CR_HSEBYP // HSE Bypass +} RCCHSE_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Used for flags +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + CR_REG_INDEX = 1, // + BDCR_REG_INDEX = 2, // + CSR_REG_INDEX = 3, // + RCC_FLAG_MASK = 0x1FU // +} RCC_RegisterFlag_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief RCC Flag +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + // Flags in the CR register + RCC_FLAG_HSIRDY = ((u8)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)), ///< Internal High Speed clock ready flag + RCC_FLAG_HSERDY = ((u8)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)), ///< External High Speed clock ready flag + + RCC_FLAG_PLLRDY = ((u8)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)), ///< PLL clock ready flag + + // Flags in the CSR register + RCC_FLAG_LSIRDY = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)), ///< Internal Low Speed oscillator Ready + RCC_FLAG_PINRST = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)), ///< PIN reset flag + RCC_FLAG_PORRST = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_Pos)), ///< POR/PDR reset flag + RCC_FLAG_SFTRST = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)), ///< Software Reset flag + RCC_FLAG_IWDGRST = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)), ///< Independent Watchdog reset flag + RCC_FLAG_WWDGRST = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)), ///< Window watchdog reset flag + + // Flags in the BDCR register + RCC_FLAG_LSERDY = ((u8)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)) ///< External Low Speed oscillator Ready +} RCC_FLAG_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief System clock source +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + RCC_HSI = 0, // Set HSI as systemCLOCK + RCC_HSE = 1, // Set HSE as systemCLOCK + RCC_PLL = 2, // Set PLL as systemCLOCK + RCC_LSI = 3 // Set LSI as systemCLOCK +} SYSCLK_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief PLL entry clock source +//////////////////////////////////////////////////////////////////////////////// + +typedef enum { + RCC_HSI_Div4 = 0, + RCC_HSI_Div = 0, + RCC_HSE_Div1 = RCC_PLLCFGR_PLLSRC, + RCC_HSE_Div2 = (RCC_PLLCFGR_PLLXTPRE | RCC_PLLCFGR_PLLSRC), +} RCC_PLLSource_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief PLL multiplication factor +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + RCC_PLLMul_2 = 0x00000000U, + RCC_PLLMul_3 = 0x00040000U, + RCC_PLLMul_4 = 0x00080000U, + RCC_PLLMul_5 = 0x000C0000U, + RCC_PLLMul_6 = 0x00100000U, + RCC_PLLMul_7 = 0x00140000U, + RCC_PLLMul_8 = 0x00180000U, + RCC_PLLMul_9 = 0x001C0000U, + RCC_PLLMul_10 = 0x00200000U, + RCC_PLLMul_11 = 0x00240000U, + RCC_PLLMul_12 = 0x00280000U, + RCC_PLLMul_13 = 0x002C0000U, + RCC_PLLMul_14 = 0x00300000U, + RCC_PLLMul_15 = 0x00340000U, + RCC_PLLMul_16 = 0x00380000U +} RCC_PLLMul_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief AHB clock source +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + RCC_SYSCLK_Div1 = RCC_CFGR_HPRE_DIV1, + RCC_SYSCLK_Div2 = RCC_CFGR_HPRE_DIV2, + RCC_SYSCLK_Div4 = RCC_CFGR_HPRE_DIV4, + RCC_SYSCLK_Div8 = RCC_CFGR_HPRE_DIV8, + RCC_SYSCLK_Div16 = RCC_CFGR_HPRE_DIV16, + RCC_SYSCLK_Div64 = RCC_CFGR_HPRE_DIV64, + RCC_SYSCLK_Div128 = RCC_CFGR_HPRE_DIV128, + RCC_SYSCLK_Div256 = RCC_CFGR_HPRE_DIV256, + RCC_SYSCLK_Div512 = RCC_CFGR_HPRE_DIV512 +} RCC_AHB_CLK_TypeDef; +//////////////////////////////////////////////////////////////////////////////// +/// @brief APB1 and APB2clock source +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + RCC_HCLK_Div1 = RCC_CFGR_PPRE1_DIV1, + RCC_HCLK_Div2 = RCC_CFGR_PPRE1_DIV2, + RCC_HCLK_Div4 = RCC_CFGR_PPRE1_DIV4, + RCC_HCLK_Div8 = RCC_CFGR_PPRE1_DIV8, + RCC_HCLK_Div16 = RCC_CFGR_PPRE1_DIV16 +} RCC_APB1_APB2_CLK_TypeDef; +//////////////////////////////////////////////////////////////////////////////// +/// @brief USB Device clock source +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + RCC_USBCLKSource_PLLCLK_Div1 = 0, + RCC_USBCLKSource_PLLCLK_Div2 = 1, + RCC_USBCLKSource_PLLCLK_Div3 = 2, + RCC_USBCLKSource_PLLCLK_Div4 = 3 +} RCC_USBCLKSOURCE_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ADC clock source +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + RCC_PCLK2_Div2 = (0x00000000), + RCC_PCLK2_Div4 = (0x00004000), + RCC_PCLK2_Div6 = (0x00008000), + RCC_PCLK2_Div8 = (0x0000C000) +} RCC_ADCCLKSOURCE_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief LSE configuration +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + RCC_LSE_OFF = 0, // LSE OFF + RCC_LSE_ON = RCC_BDCR_LSEON, // LSE ON + RCC_LSE_Bypass = RCC_BDCR_LSEBYP // LSE Bypass +} RCC_LSE_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief RTC clock source +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + RCC_RTCCLKSource_LSE = RCC_BDCR_RTCSEL_LSE, + RCC_RTCCLKSource_LSI = RCC_BDCR_RTCSEL_LSI, + RCC_RTCCLKSource_HSE_Div128 = RCC_BDCR_RTCSEL_HSE +} RCC_RTCCLKSOURCE_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Clock source to output on MCO pin +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + RCC_MCO_NoClock = RCC_CFGR_MCO_NOCLOCK, + RCC_MCO_LSI = RCC_CFGR_MCO_LSI, + RCC_MCO_LSE = RCC_CFGR_MCO_LSE, + RCC_MCO_SYSCLK = RCC_CFGR_MCO_SYSCLK, + RCC_MCO_HSI = RCC_CFGR_MCO_HSI, + RCC_MCO_HSE = RCC_CFGR_MCO_HSE, + RCC_MCO_PLLCLK_Div2 = RCC_CFGR_MCO_PLL +} RCC_MCO_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief RCC Interrupt source +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + RCC_IT_LSIRDY = RCC_CIR_LSIRDYF, + RCC_IT_LSERDY = RCC_CIR_LSERDYF, + RCC_IT_HSIRDY = RCC_CIR_HSIRDYF, + RCC_IT_HSERDY = RCC_CIR_HSERDYF, + RCC_IT_PLLRDY = RCC_CIR_PLLRDYF, + RCC_IT_CSS = RCC_CIR_CSSF +} RCC_IT_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief RCC clock frequency type definition +//////////////////////////////////////////////////////////////////////////////// +typedef struct { + u32 SYSCLK_Frequency; ///< returns SYSCLK clock frequency. + u32 HCLK_Frequency; ///< returns hclk clock frequency. + u32 PCLK1_Frequency; ///< returns PCLK1 clock frequency. + u32 PCLK2_Frequency; ///< returns PCLK2 clock frequency. + u32 ADCCLK_Frequency; ///< returns ADCCLK clock frequency. +} RCC_ClocksTypeDef; +/// @} + +/// @} + + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup RCC_Exported_Variables +/// @{ +#ifdef _HAL_RCC_C_ + +#define GLOBAL +#else +#define GLOBAL extern +#endif + +#undef GLOBAL +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup RCC_Exported_Functions +/// @{ +void RCC_DeInit(void); +void RCC_HSEConfig(RCCHSE_TypeDef state); +void RCC_HSICmd(FunctionalState state); +void RCC_SYSCLKConfig(SYSCLK_TypeDef sys_clk_src); +void RCC_PLLDMDNConfig(u32 plldn, u32 plldm); +void RCC_PLLConfig(RCC_PLLSource_TypeDef pll_src, RCC_PLLMul_TypeDef pll_mul); +void RCC_PLLCmd(FunctionalState state); +void RCC_HCLKConfig(RCC_AHB_CLK_TypeDef sys_clk); +void RCC_PCLK1Config(RCC_APB1_APB2_CLK_TypeDef hclk); +void RCC_PCLK2Config(RCC_APB1_APB2_CLK_TypeDef hclk); +void RCC_USBCLKConfig(RCC_USBCLKSOURCE_TypeDef usb_clk_src); +void RCC_ADCCLKConfig(RCC_ADCCLKSOURCE_TypeDef pclk2); +void RCC_LSICmd(FunctionalState state); + +void RCC_RTCCLKCmd(FunctionalState state); +void RCC_LSEConfig(RCC_LSE_TypeDef state); +void RCC_RTCCLKConfig(RCC_RTCCLKSOURCE_TypeDef rtc_clk_src); +void RCC_BackupResetCmd(FunctionalState state); + +void RCC_GetClocksFreq(RCC_ClocksTypeDef* clk); +void RCC_AHBPeriphClockCmd(u32 ahb_periph, FunctionalState state); +void RCC_AHB2PeriphClockCmd(u32 ahb_periph, FunctionalState state); +void RCC_AHB3PeriphClockCmd(u32 ahb_periph, FunctionalState state); +void RCC_AHBPeriphResetCmd(u32 ahb_periph, FunctionalState state); +void RCC_AHB2PeriphResetCmd(u32 ahb_periph, FunctionalState state); +void RCC_AHB3PeriphResetCmd(u32 ahb_periph, FunctionalState state); +void RCC_APB2PeriphClockCmd(u32 apb2_periph, FunctionalState state); +void RCC_APB1PeriphClockCmd(u32 apb1_periph, FunctionalState state); +void RCC_APB2PeriphResetCmd(u32 apb2_periph, FunctionalState state); +void RCC_APB1PeriphResetCmd(u32 apb1_periph, FunctionalState state); + +void RCC_ClockSecuritySystemCmd(FunctionalState state); +void RCC_MCOConfig(RCC_MCO_TypeDef mco_src); +void RCC_ClearFlag(void); +void RCC_ITConfig(RCC_IT_TypeDef it, FunctionalState state); +void RCC_ClearITPendingBit(u8 it); + +u8 RCC_GetSYSCLKSource(void); +u32 RCC_GetSysClockFreq(void); +u32 RCC_GetHCLKFreq(void); + +u32 RCC_GetPCLK1Freq(void); +u32 RCC_GetPCLK2Freq(void); +FlagStatus RCC_GetFlagStatus(RCC_FLAG_TypeDef flag); +ErrorStatus RCC_WaitForHSEStartUp(void); +ErrorStatus RCC_WaitForFlagStartUp(RCC_FLAG_TypeDef flag); +ITStatus RCC_GetITStatus(RCC_IT_TypeDef it); + +//////////////////////////////////////////////////////////////////////////////// +// Extended function interface +//////////////////////////////////////////////////////////////////////////////// +//ErrorStatus exRCC_Init(RCCInitStruct_TypeDef* para); +void exRCC_SystickDisable(void); +void exRCC_SystickEnable(u32 sys_tick_period); +void exRCC_APB1PeriphReset(u32 apb1_periph); +void exRCC_APB2PeriphReset(u32 apb2_periph); +void exRCC_BackupReset(void); +void RCC_ADC_ClockCmd(ADC_TypeDef* peripheral, FunctionalState state); +void RCC_GPIO_ClockCmd(GPIO_TypeDef* peripheral, FunctionalState state); +/// @} + +/// @} + +/// @} + + + + +//////////////////////////////////////////////////////////////////////////////// +#endif // __HAL_RCC_H +//////////////////////////////////////////////////////////////////////////////// + + diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_redefine.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_redefine.h new file mode 100644 index 000000000..da5295c78 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_redefine.h @@ -0,0 +1,102 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_redefine.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE REDEFINE +/// FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

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+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#ifndef __HAL_REDEFINE_H +#define __HAL_REDEFINE_H + +// Files includes + + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +/////////////////////////////////////1/////////////////////////////////////////// +/// @defgroup REDEFINE_HAL +/// @brief REDEFINE HAL modules +/// @{ + + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup REDEFINE_Exported_Types +/// @{ +/// + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup REDEFINE_Exported_Constants +/// @{ +//Lib redefine + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief HAL_lib Version compatibility definition +//////////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM compatibility definition +//////////////////////////////////////////////////////////////////////////////// + +#define TIM_TRGOSource_Reset TIM_TRIGSource_Reset +#define TIM_TRGOSource_Enable TIM_TRIGSource_Enable +#define TIM_TRGOSource_Update TIM_TRIGSource_Update +#define TIM_TRGOSource_OC1 TIM_TRIGSource_OC1 +#define TIM_TRGOSource_OC1Ref TIM_TRIGSource_OC1Ref +#define TIM_TRGOSource_OC2Ref TIM_TRIGSource_OC2Ref +#define TIM_TRGOSource_OC3Ref TIM_TRIGSource_OC3Ref +#define TIM_TRGOSource_OC4Ref TIM_TRIGSource_OC4Ref +///< The UG bit in the TIM_EGR register is used as the trigger output (TRIG). +///< The Counter Enable CEN is used as the trigger output (TRIG). +///< The update event is used as the trigger output (TRIG). +///< The trigger output sends a positive pulse when the CC1IF flag ///< is to be set, as soon as a capture or compare match occurs (TRIG). +///< OC1REF signal is used as the trigger output (TRIG). +///< OC2REF signal is used as the trigger output (TRIG). +///< OC3REF signal is used as the trigger output (TRIG). +///< OC4REF signal is used as the trigger output (TRIG). +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup REDEFINE_Exported_Variables +/// @{ +#ifdef _HAL_REDEFINE_C_ + +#define GLOBAL +#else +#define GLOBAL extern +#endif + +#undef GLOBAL +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup REDEFINE_Exported_Functions +/// @{ + + + +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +#endif // __HAL_REDEFINE_H +//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rtc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rtc.h new file mode 100644 index 000000000..fcf48d569 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rtc.h @@ -0,0 +1,114 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_rtc.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE RTC +/// FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#ifndef __HAL_RTC_H +#define __HAL_RTC_H + +// Files includes +#include "types.h" +#include "reg_common.h" +#include "reg_rtc.h" + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup RTC_HAL +/// @brief RTC HAL modules +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup RTC_Exported_Types +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @brief RTC_interrupts_define +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + RTC_IT_OW = RTC_CR_OWIE, ///< Overflow interrupt + RTC_IT_ALR = RTC_CR_ALRIE, ///< Alarm interrupt + RTC_IT_SEC = RTC_CR_SECIE ///< Second interrupt +} RTC_IT_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief RTC_interrupts_flags +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + RTC_FLAG_RTOFF = RTC_CSR_RTOFF, ///< RTC Operation OFF flag + RTC_FLAG_RSF = RTC_CSR_RSF, ///< Registers Synchronized flag + RTC_FLAG_OW = RTC_CSR_OWF, ///< Overflow flag + RTC_FLAG_ALR = RTC_CSR_ALRF, ///< Alarm flag + RTC_FLAG_SEC = RTC_CSR_SECF ///< Second flag +} RTC_FLAG_TypeDef; +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup RTC_Exported_Constants +/// @{ + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup RTC_Exported_Variables +/// @{ + +#ifdef _HAL_RTC_C_ + +#define GLOBAL +#else +#define GLOBAL extern +#endif + +GLOBAL bool accessRTC; + + +#undef GLOBAL + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup RTC_Exported_Functions +/// @{ +void RTC_ITConfig(RTC_IT_TypeDef it, FunctionalState state); +void RTC_ClearFlag(RTC_FLAG_TypeDef flag); +void RTC_ClearITPendingBit(RTC_IT_TypeDef it); +void RTC_EnterConfigMode(void); +void RTC_SetCounter(u32 count); +void RTC_SetPrescaler(u32 prescaler); +void RTC_SetAlarm(u32 alarm); +void RTC_ExitConfigMode(void); +void RTC_WaitForLastTask(void); +void RTC_WaitForSynchro(void); + +u32 RTC_GetCounter(void); +u32 RTC_GetDivider(void); + +FlagStatus RTC_GetFlagStatus(RTC_FLAG_TypeDef flag); +ITStatus RTC_GetITStatus(RTC_IT_TypeDef it); + +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +#endif // __HAL_RTC_H +//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_sdio.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_sdio.h new file mode 100644 index 000000000..199ccc4c6 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_sdio.h @@ -0,0 +1,503 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_gpio.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE GPIO +/// FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#ifndef __HAL_SDIO_H +#define __HAL_SDIO_H + +// Files includes +#include "mm32_reg.h" + + + +#ifdef __cplusplus +extern "C" { +#endif +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup GPIO_HAL +/// @brief GPIO HAL modules +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup GPIO_Exported_Types +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Output Maximum frequency selection +//////////////////////////////////////////////////////////////////////////////// +#define SDIO_FLAG_CCRCFAIL ((u32)0x00000001) +#define SDIO_FLAG_DCRCFAIL ((u32)0x00000002) +#define SDIO_FLAG_CTIMEOUT ((u32)0x00000004) +#define SDIO_FLAG_DTIMEOUT ((u32)0x00000008) +#define SDIO_FLAG_TXUNDERR ((u32)0x00000010) +#define SDIO_FLAG_RXOVERR ((u32)0x00000020) +#define SDIO_FLAG_CMDREND ((u32)0x00000040) +#define SDIO_FLAG_CMDSENT ((u32)0x00000080) +#define SDIO_FLAG_DATAEND ((u32)0x00000100) +#define SDIO_FLAG_STBITERR ((u32)0x00000200) +#define SDIO_FLAG_DBCKEND ((u32)0x00000400) +#define SDIO_FLAG_CMDACT ((u32)0x00000800) +#define SDIO_FLAG_TXACT ((u32)0x00001000) +#define SDIO_FLAG_RXACT ((u32)0x00002000) +#define SDIO_FLAG_TXFIFOHE ((u32)0x00004000) +#define SDIO_FLAG_RXFIFOHF ((u32)0x00008000) +#define SDIO_FLAG_TXFIFOF ((u32)0x00010000) +#define SDIO_FLAG_RXFIFOF ((u32)0x00020000) +#define SDIO_FLAG_TXFIFOE ((u32)0x00040000) +#define SDIO_FLAG_RXFIFOE ((u32)0x00080000) +#define SDIO_FLAG_TXDAVL ((u32)0x00100000) +#define SDIO_FLAG_RXDAVL ((u32)0x00200000) +#define SDIO_FLAG_SDIOIT ((u32)0x00400000) +#define SDIO_FLAG_CEATAEND ((u32)0x00800000) + + + +//////////////////////////////////////////////////////////////////////////////////////////////////// +//SDIO working mode define ,SDIO working mode definition, set through the SD_SetDevice Mode function. +#define SD_POLLING_MODE 0 /// Query mode. In this mode, it is recommended to increase the setting of SDIO_TRANSFER_CLK_DIV if there are problems with reading and writing. +#define SD_DMA_MODE 1 /// In DMA mode, it is recommended to increase the setting of SDIO_TRANSFER_CLK_DIV if there are problems with reading and writing. + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SDIO Various error enumeration definitions +//////////////////////////////////////////////////////////////////////////////// + +typedef enum { + SD_CMD_CRC_FAIL = 1, ///< Command response received (but CRC check failed) + SD_DATA_CRC_FAIL, ///< Data bock sent/received (CRC check Failed) + SD_CMD_RSP_TIMEOUT, ///< Command response timeout + SD_DATA_TIMEOUT, ///< Data time out + SD_TX_UNDERRUN, ///< Transmit FIFO under-run + SD_RX_OVERRUN, ///< Receive FIFO over-run + SD_START_BIT_ERR, ///< Start bit not detected on all data signals in widE bus mode + SD_CMD_OUT_OF_RANGE, ///< CMD's argument was out of range. + SD_ADDR_MISALIGNED, ///< Misaligned address + SD_BLOCK_LEN_ERR, ///< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length + SD_ERASE_SEQ_ERR, ///< An error in the sequence of erase command occurs. + SD_BAD_ERASE_PARAM, ///< An Invalid selection for erase groups + SD_WRITE_PROT_VIOLATION, ///< Attempt to program a write protect block + SD_LOCK_UNLOCK_FAILED, ///< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card + SD_COM_CRC_FAILED, ///< CRC check of the previous command failed + SD_ILLEGAL_CMD, ///< Command is not legal for the card state + SD_CARD_ECC_FAILED, ///< Card internal ECC was applied but failed to correct the data + SD_CC_ERROR, ///< Internal card controller error + SD_GENERAL_UNKNOWN_ERROR, ///< General or Unknown error + SD_STREAM_READ_UNDERRUN, ///< The card could not sustain data transfer in stream read operation. + SD_STREAM_WRITE_OVERRUN, ///< The card could not sustain data programming in stream mode + SD_CID_CSD_OVERWRITE, ///< CID/CSD overwrite error + SD_WP_ERASE_SKIP, ///< only partial address space was erased + SD_CARD_ECC_DISABLED, ///< Command has been executed without using internal ECC + SD_ERASE_RESET, ///< Erase sequence was cleared before executing because an out of erase sequence command was received + SD_AKE_SEQ_ERROR, ///< Error in sequence of authentication. + SD_INVALID_VOLTRANGE, ///< SD invalid voltage range, + SD_ADDR_OUT_OF_RANGE, ///< SD addresses are out of range, + SD_SWITCH_ERROR, ///< SD switch error, + SD_SDIO_DISABLED, ///< SD SDIO disability, + SD_SDIO_FUNCTION_BUSY, ///< SD SDIO function busy, + SD_SDIO_FUNCTION_FAILED, ///< SD SDIO failed, + SD_SDIO_UNKNOWN_FUNCTION, ///< SDIO unknown function, + SD_INTERNAL_ERROR, ///< SD internal error, + SD_NOT_CONFIGURED, ///< SD is not configured, + SD_REQUEST_PENDING, ///< The SD request waits, + SD_REQUEST_NOT_APPLICABLE, ///< The SD requirement does not apply, + SD_INVALID_PARAMETER, ///< Invalid SD parameter, + SD_UNSUPPORTED_FEATURE, ///< Features not supported by SD, + SD_UNSUPPORTED_HW, ///< HW not supported by SD, + SD_ERROR, ///< SD error + SD_OK = 0 ///< SD OK +} SD_Error; +//////////////////////////////////////////////////////////////////////////////// +/// @brief SD card CSD register data +//////////////////////////////////////////////////////////////////////////////// +typedef struct { + u8 CSDStruct; ///< CSD structure + u8 SysSpecVersion; ///< System specification version + u8 Reserved1; ///< Reserved + u8 TAAC; ///< Data read access-time 1 + u8 NSAC; ///< Data read access-time 2 in CLK cycles + u8 MaxBusClkFrec; ///< Max. bus clock frequency + u16 CardComdClasses; ///< Card command classes + u8 RdBlockLen; ///< Max. read data block length + u8 PartBlockRead; ///< Partial blocks for read allowed + u8 WrBlockMisalign; ///< Write block misalignment + u8 RdBlockMisalign; ///< Read block misalignment + u8 DSRImpl; ///< DSR implemented + u8 Reserved2; ///< Reserved + u32 DeviceSize; ///< Device Size + u8 MaxRdCurrentVDDMin; ///< Max. read current @ VDD min + u8 MaxRdCurrentVDDMax; ///< Max. read current @ VDD max + u8 MaxWrCurrentVDDMin; ///< Max. write current @ VDD min + u8 MaxWrCurrentVDDMax; ///< Max. write current @ VDD max + u8 DeviceSizeMul; ///< Device size multiplier + u8 EraseGrSize; ///< Erase group size + u8 EraseGrMul; ///< Erase group size multiplier + u8 WrProtectGrSize; ///< Write protect group size + u8 WrProtectGrEnable; ///< Write protect group enable + u8 ManDeflECC; ///< Manufacturer default ECC + u8 WrSpeedFact; ///< Write speed factor + u8 MaxWrBlockLen; ///< Max. write data block length + u8 WriteBlockPaPartial; ///< Partial blocks for write allowed + u8 Reserved3; ///< Reserded + u8 ContentProtectAppli; ///< Content protection application + u8 FileFormatGrouop; ///< File format group + u8 CopyFlag; ///< Copy flag (OTP) + u8 PermWrProtect; ///< Permanent write protection + u8 TempWrProtect; ///< Temporary write protection + u8 FileFormat; ///< File Format + u8 ECC; ///< ECC code + u8 CSD_CRC; ///< CSD CRC + u8 Reserved4; ///< always 1 +} SD_CSD; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SD card CID register data +//////////////////////////////////////////////////////////////////////////////// +typedef struct { + u8 ManufacturerID; ///< ManufacturerID + u16 OEM_AppliID; ///< OEM/Application ID + u32 ProdName1; ///< Product Name part1 + u8 ProdName2; ///< Product Name part2 + u8 ProdRev; ///< Product Revision + u32 ProdSN; ///< Product Serial Number + u8 Reserved1; ///< Reserved1 + u16 ManufactDate; ///< Manufacturing Date + u8 CID_CRC; ///< CID CRC + u8 Reserved2; ///< always 1 +} SD_CID; +//////////////////////////////////////////////////////////////////////////////// +/// @brief SD state +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + SD_CARD_READY = ((u32)0x00000001), + SD_CARD_IDENTIFICATION = ((u32)0x00000002), + SD_CARD_STANDBY = ((u32)0x00000003), + SD_CARD_TRANSFER = ((u32)0x00000004), + SD_CARD_SENDING = ((u32)0x00000005), + SD_CARD_RECEIVING = ((u32)0x00000006), + SD_CARD_PROGRAMMING = ((u32)0x00000007), + SD_CARD_DISCONNECTED = ((u32)0x00000008), + SD_CARD_ERROR = ((u32)0x000000FF) +} SDCardState; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SD message ,include CSD,CID data +//////////////////////////////////////////////////////////////////////////////// +typedef struct { + SD_CSD SD_csd; + SD_CID SD_cid; + long long CardCapacity; + u32 CardBlockSize; + u16 RCA; + u8 CardType; +} SD_CardInfo; +//////////////////////////////////////////////////////////////////////////////// +/// @brief SDIO init +//////////////////////////////////////////////////////////////////////////////// +typedef struct { + u8 SDIO_MDEN; + u8 SDIO_DATWT; + u8 SDIO_SelPTSM; + u8 SDIO_CLKSP; + u8 SDIO_OUTM; + u8 SDIO_SelSM; + u8 SDIO_OPMSel; +} SDIO_InitTypeDef; + +typedef struct { + u32 SDIO_Argument; ///Specifies the SDIO command argument which is sent + ///to a card as part of a command message. If a command + ///contains an argument, it must be loaded into this register + ///before writing the command to the command register + + u32 SDIO_CmdIndex; ///Specifies the SDIO command index. It must be lower than 0x40. + + u32 SDIO_Response; ///Specifies the SDIO response type. + ///This parameter can be a value of @ref SDIO_Response_Type + + u32 SDIO_Wait; ///Specifies whether SDIO wait-for-interrupt request is enabled or disabled. + ///This parameter can be a value of @ref SDIO_Wait_Interrupt_State + +/// u32 SDIO_CPSM; ///Specifies whether SDIO Command path state machine (CPSM) + ///is enabled or disabled. + ///This parameter can be a value of @ref SDIO_CPSM_State +} SDIO_CmdInitTypeDef; +typedef struct { + u32 SDIO_DataTimeOut; // < Specifies the data timeout period in card bus clock periods. + // + u32 SDIO_DataLength; // < Specifies the number of data bytes to be transferred. + // + u32 SDIO_DataBlockSize; // < Specifies the data block size for block transfer. + // This parameter can be a value of @ref SDIO_Data_Block_Size + // + u32 SDIO_TransferDir; // < Specifies the data transfer direction, whether the transfer + // is a read or write. + // This parameter can be a value of @ref SDIO_Transfer_Direction + // +// u32 SDIO_TransferMode; // < Specifies whether data transfer is in stream or block mode. +// // This parameter can be a value of @ref SDIO_Transfer_Type +// // +// u32 SDIO_DPSM; // < Specifies whether SDIO Data path state machine (DPSM) +// // is enabled or disabled. +// // This parameter can be a value of @ref SDIO_DPSM_State +} SDIO_DataInitTypeDef; + + + +extern SD_CardInfo SDCardInfo; +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup SDIO ָinstruction set +/// @{ +#define SD_CMD_GO_IDLE_STATE ((u8)0) +#define SD_CMD_SEND_OP_COND ((u8)1) +#define SD_CMD_ALL_SEND_CID ((u8)2) +#define SD_CMD_SET_REL_ADDR ((u8)3) +#define SD_CMD_SET_DSR ((u8)4) +#define SD_CMD_SDIO_SEN_OP_COND ((u8)5) +#define SD_CMD_HS_SWITCH ((u8)6) +#define SD_CMD_SEL_DESEL_CARD ((u8)7) +#define SD_CMD_HS_SEND_EXT_CSD ((u8)8) +#define SD_CMD_SEND_CSD ((u8)9) +#define SD_CMD_SEND_CID ((u8)10) +#define SD_CMD_READ_DAT_UNTIL_STOP ((u8)11) +#define SD_CMD_STOP_TRANSMISSION ((u8)12) +#define SD_CMD_SEND_STATUS ((u8)13) +#define SD_CMD_HS_BUSTEST_READ ((u8)14) +#define SD_CMD_GO_INACTIVE_STATE ((u8)15) +#define SD_CMD_SET_BLOCKLEN ((u8)16) +#define SD_CMD_READ_SINGLE_BLOCK ((u8)17) +#define SD_CMD_READ_MULT_BLOCK ((u8)18) +#define SD_CMD_HS_BUSTEST_WRITE ((u8)19) +#define SD_CMD_WRITE_DAT_UNTIL_STOP ((u8)20) +#define SD_CMD_SET_BLOCK_COUNT ((u8)23) +#define SD_CMD_WRITE_SINGLE_BLOCK ((u8)24) +#define SD_CMD_WRITE_MULT_BLOCK ((u8)25) +#define SD_CMD_PROG_CID ((u8)26) +#define SD_CMD_PROG_CSD ((u8)27) +#define SD_CMD_SET_WRITE_PROT ((u8)28) +#define SD_CMD_CLR_WRITE_PROT ((u8)29) +#define SD_CMD_SEND_WRITE_PROT ((u8)30) +#define SD_CMD_SD_ERASE_GRP_START ((u8)32) +#define SD_CMD_SD_ERASE_GRP_END ((u8)33) +#define SD_CMD_ERASE_GRP_START ((u8)35) +#define SD_CMD_ERASE_GRP_END ((u8)36) +#define SD_CMD_ERASE ((u8)38) +#define SD_CMD_FAST_IO ((u8)39) +#define SD_CMD_GO_IRQ_STATE ((u8)40) +#define SD_CMD_LOCK_UNLOCK ((u8)42) +#define SD_CMD_APP_CMD ((u8)55) +#define SD_CMD_GEN_CMD ((u8)56) +#define SD_CMD_NO_CMD ((u8)64) +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup Following commands are SD Card Specific commands. +/// @{ +#define SD_CMD_APP_SD_SET_BUSWIDTH ((u8)6) +#define SD_CMD_SD_APP_STAUS ((u8)13) +#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((u8)22) +#define SD_CMD_SD_APP_OP_COND ((u8)41) +#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((u8)42) +#define SD_CMD_SD_APP_SEND_SCR ((u8)51) +#define SD_CMD_SDIO_RW_DIRECT ((u8)52) +#define SD_CMD_SDIO_RW_EXTENDED ((u8)53) + +#define SD_CMD_SD_APP_GET_MKB ((u8)43) +#define SD_CMD_SD_APP_GET_MID ((u8)44) +#define SD_CMD_SD_APP_SET_CER_RN1 ((u8)45) +#define SD_CMD_SD_APP_GET_CER_RN2 ((u8)46) +#define SD_CMD_SD_APP_SET_CER_RES2 ((u8)47) +#define SD_CMD_SD_APP_GET_CER_RES1 ((u8)48) +#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((u8)18) +#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((u8)25) +#define SD_CMD_SD_APP_SECURE_ERASE ((u8)38) +#define SD_CMD_SD_APP_CHANGE_SECURE_AREA ((u8)49) +#define SD_CMD_SD_APP_SECURE_WRITE_MKB ((u8)48) +/// @} +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup SD support define. +/// @{ +#define SDIO_STD_CAPACITY_SD_CARD_V1_1 ((u32)0x00000000) +#define SDIO_STD_CAPACITY_SD_CARD_V2_0 ((u32)0x00000001) +#define SDIO_HIGH_CAPACITY_SD_CARD ((u32)0x00000002) +#define SDIO_MULTIMEDIA_CARD ((u32)0x00000003) +#define SDIO_SECURE_DIGITAL_IO_CARD ((u32)0x00000004) +#define SDIO_HIGH_SPEED_MULTIMEDIA_CARD ((u32)0x00000005) +#define SDIO_SECURE_DIGITAL_IO_COMBO_CARD ((u32)0x00000006) +#define SDIO_HIGH_CAPACITY_MMC_CARD ((u32)0x00000007) +/// @} + +#ifndef NULL +#define NULL 0 +#endif +#define SDIO_STATIC_FLAGS ((u32)0x000005FF) +#define SDIO_CMD0TIMEOUT ((u32)0x00010000) +#define SDIO_DATATIMEOUT ((u32)0xFFFFFFFF) +#define SDIO_FIFO_Address ((u32)0x40018080) + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup Mask for errors Card Status R1 (OCR Register) +/// @{ +#define SD_OCR_ADDR_OUT_OF_RANGE ((u32)0x80000000) +#define SD_OCR_ADDR_MISALIGNED ((u32)0x40000000) +#define SD_OCR_BLOCK_LEN_ERR ((u32)0x20000000) +#define SD_OCR_ERASE_SEQ_ERR ((u32)0x10000000) +#define SD_OCR_BAD_ERASE_PARAM ((u32)0x08000000) +#define SD_OCR_WRITE_PROT_VIOLATION ((u32)0x04000000) +#define SD_OCR_LOCK_UNLOCK_FAILED ((u32)0x01000000) +#define SD_OCR_COM_CRC_FAILED ((u32)0x00800000) +#define SD_OCR_ILLEGAL_CMD ((u32)0x00400000) +#define SD_OCR_CARD_ECC_FAILED ((u32)0x00200000) +#define SD_OCR_CC_ERROR ((u32)0x00100000) +#define SD_OCR_GENERAL_UNKNOWN_ERROR ((u32)0x00080000) +#define SD_OCR_STREAM_READ_UNDERRUN ((u32)0x00040000) +#define SD_OCR_STREAM_WRITE_OVERRUN ((u32)0x00020000) +#define SD_OCR_CID_CSD_OVERWRIETE ((u32)0x00010000) +#define SD_OCR_WP_ERASE_SKIP ((u32)0x00008000) +#define SD_OCR_CARD_ECC_DISABLED ((u32)0x00004000) +#define SD_OCR_ERASE_RESET ((u32)0x00002000) +#define SD_OCR_AKE_SEQ_ERROR ((u32)0x00000008) +#define SD_OCR_ERRORBITS ((u32)0xFDFFE008) +/// @} +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup Masks for R6 Response +/// @{ +#define SD_R6_GENERAL_UNKNOWN_ERROR ((u32)0x00002000) +#define SD_R6_ILLEGAL_CMD ((u32)0x00004000) +#define SD_R6_COM_CRC_FAILED ((u32)0x00008000) +/// @} +#define SD_VOLTAGE_WINDOW_SD ((u32)0x80100000) +#define SD_HIGH_CAPACITY ((u32)0x40000000) +#define SD_STD_CAPACITY ((u32)0x00000000) +#define SD_CHECK_PATTERN ((u32)0x000001AA) +#define SD_VOLTAGE_WINDOW_MMC ((u32)0x80FF8000) + +#define SD_MAX_VOLT_TRIAL ((u32)0x0000FFFF) +#define SD_ALLZERO ((u32)0x00000000) + +#define SD_WIDE_BUS_SUPPORT ((u32)0x00040000) +#define SD_SINGLE_BUS_SUPPORT ((u32)0x00010000) +#define SD_CARD_LOCKED ((u32)0x02000000) +#define SD_CARD_PROGRAMMING ((u32)0x00000007) +#define SD_CARD_RECEIVING ((u32)0x00000006) +#define SD_DATATIMEOUT ((u32)0xFFFFFFFF) +#define SD_0TO7BITS ((u32)0x000000FF) +#define SD_8TO15BITS ((u32)0x0000FF00) +#define SD_16TO23BITS ((u32)0x00FF0000) +#define SD_24TO31BITS ((u32)0xFF000000) +#define SD_MAX_DATA_LENGTH ((u32)0x01FFFFFF) + +#define SD_HALFFIFO ((u32)0x00000008) +#define SD_HALFFIFOBYTES ((u32)0x00000020) + +#define SD_CCCC_LOCK_UNLOCK ((u32)0x00000080) +#define SD_CCCC_WRITE_PROT ((u32)0x00000040) +#define SD_CCCC_ERASE ((u32)0x00000020) + + +#define SDIO_SEND_IF_COND ((u32)0x00000008) + +#define SDIO_Response_No ((u32)0x00) +#define SDIO_Response_Short ((u32)0x01) +#define SDIO_Response_Long ((u32)0x03) + +#define SDIO_DataBlockSize_1b ((u32)0x00000000) +#define SDIO_DataBlockSize_2b ((u32)0x00000001) +#define SDIO_DataBlockSize_4b ((u32)0x00000002) +#define SDIO_DataBlockSize_8b ((u32)0x00000003) +#define SDIO_DataBlockSize_16b ((u32)0x00000004) +#define SDIO_DataBlockSize_32b ((u32)0x00000005) +#define SDIO_DataBlockSize_64b ((u32)0x00000006) +#define SDIO_DataBlockSize_128b ((u32)0x00000007) +#define SDIO_DataBlockSize_256b ((u32)0x00000008) +#define SDIO_DataBlockSize_512b ((u32)0x00000009) +#define SDIO_DataBlockSize_1024b ((u32)0x0000000A) +#define SDIO_DataBlockSize_2048b ((u32)0x0000000B) +#define SDIO_DataBlockSize_4096b ((u32)0x0000000C) +#define SDIO_DataBlockSize_8192b ((u32)0x0000000D) +#define SDIO_DataBlockSize_16384b ((u32)0x0000000E) +//Define the data block length when the block data transfer mode is selected: +//0000: (0 decimal) lock length = 2^0 = 1 byte +//0001: (1 decimal) lock length = 2^1 = 2 bytes +//0010: (2 decimal) lock length = 2^2 = 4 bytes +//0011: (3 decimal) lock length = 2^3 = 8 bytes +//0100: (4 decimal) lock length = 2^4 = 16 bytes +//0101: (5 decimal) lock length = 2^5 = 32 bytes +//0110: (6 decimal) lock length = 2^6 = 64 bytes +//0111: (7 decimal) lock length = 2^7 = 128 bytes +//1000: (8 decimal) lock length = 2^8 = 256 bytes +//1001: (9 decimal) lock length = 2^9 = 512 bytes +//1010: (10 decimal) lock length = 2^10 = 1024 bytes +//1011: (11 decimal) lock length = 2^11 = 2048 bytes +//1100: (12 decimal) lock length = 2^12 = 4096 bytes +//1101: (13 decimal) lock length = 2^13 = 8192 bytes +//1110: (14 decimal) lock length = 2^14 = 16384 bytes +//1111: (15 decimal) reserved + + +#define SDIO_TransferDir_ToCard ((u32)0x00000000) +#define SDIO_TransferDir_ToSDIO ((u32)0x00000002) + +#define SDIO_Wait_No ((u32)0x00000000) // SDIO No Wait, TimeOut is enabled +#define SDIO_Wait_IT ((u32)0x00000100) //SDIO Wait Interrupt Request +#define SDIO_Wait_Pend ((u32)0x00000200) // SDIO Wait End of transfer + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup I2C_Exported_Functions +/// @{ +void SDIO_DeInit(void); +void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct); +void SDIO_ClockSet(u32 value); +void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct); +void SDIO_ITConfig(u32 SDIO_IT, FunctionalState state); +void SDIO_CRCConfig(u32 SDIO_CRC, FunctionalState state); +void SDIO_Clock_Set(u8 clkdiv); +void SDIO_Send_Cmd(u8 cmdindex, u8 waitrsp, u32 arg); +SD_Error SD_PowerOFF(void); +SD_Error CmdError(void); +SD_Error CmdResp2Error(void); +SD_Error CmdResp3Error(void); +SD_Error CmdResp6Error(u8 cmd, u16* prca); +SD_Error CmdResp7Error(void); +SD_Error CmdResp1Error(u8 cmd); +void SDIO_Send_Data_Cfg(u32 datatimeout, u32 datalen, u8 blksize, u8 dir); +void SDIO_ClearITPendingBit(u32 SDIO_IT); +FlagStatus SDIO_GetFlagStatus(u32 SDIO_FLAG); +u32 SDIO_GetTimeOutCounter(void); +u32 SDIO_ReadData(void); +void SDIO_WriteData(u32 tempbuff); +void SDIO_DMACmd(FunctionalState state); +/// @} + + +#ifdef __cplusplus +} +#endif + + +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +#endif +//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_spi.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_spi.h new file mode 100644 index 000000000..db1a9aa30 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_spi.h @@ -0,0 +1,351 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_spi.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SPI +/// FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#ifndef __HAL_SPI_H +#define __HAL_SPI_H + +// Files includes +#include "types.h" +#include "reg_spi.h" + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup SPI_HAL +/// @brief SPI HAL modules +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup SPI_Exported_Types +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SPI mode enum definition +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + SPI_Mode_Slave = 0x0000, ///< SPI slave mode + SPI_Mode_Master = SPI_GCR_MODE ///< SPI master mode +} SPI_Mode_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SPI data size enum definition +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + SPI_DataSize_8b = 0x0000, ///< 8 bits valid data + SPI_DataSize_32b = SPI_GCR_DWSEL ///< 32 bits valid data +} SPI_DataSize_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SPI clock polarity enum definition +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + SPI_CPOL_Low = 0x0000, ///< The clock is low in idle state. + SPI_CPOL_High = SPI_CCR_CPOL ///< The clock is high in idle state. +} SPI_CPOL_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SPI clock phase enum definition +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + SPI_CPHA_2Edge = 0x0000, ///< Data sampling starts from the second clock edge. + SPI_CPHA_1Edge = SPI_CCR_CPHA ///< Data sampling starts from the first clock edge. +} SPI_CPHA_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SPI nss control mode enum definition +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + SPI_NSS_Soft = 0x0000, + SPI_NSS_Hard = SPI_GCR_NSS +} SPI_NSS_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SPI baud rate prescaler enum definition +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + SPI_BaudRatePrescaler_2 = 0x0002, ///< SCK clock devide by 2 + SPI_BaudRatePrescaler_4 = 0x0004, ///< SCK clock devide by 4 + SPI_BaudRatePrescaler_8 = 0x0008, ///< SCK clock devide by 7 + SPI_BaudRatePrescaler_16 = 0x0010, ///< SCK clock devide by 16 + SPI_BaudRatePrescaler_32 = 0x0020, ///< SCK clock devide by 32 + SPI_BaudRatePrescaler_64 = 0x0040, ///< SCK clock devide by 64 + SPI_BaudRatePrescaler_128 = 0x0080, ///< SCK clock devide by 128 + SPI_BaudRatePrescaler_256 = 0x0100 ///< SCK clock devide by 256 +} SPI_BaudRatePrescaler_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SPI first bit enum definition +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + SPI_FirstBit_MSB = 0x0000, ///< Data transfers start from MSB + SPI_FirstBit_LSB = SPI_CCR_LSBFE ///< Data transfers start from LSB +} SPI_FirstBit_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SPI FIFO trigger level enum definition +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + SPI_RXTLF = SPI_GCR_RXTLF_Half, ///< RX FIFO trigger level + SPI_TXTLF = SPI_GCR_TXTLF_Half ///< TX FIFO trigger level +} SPI_TLF_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SPI bit derection enum definition +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + SPI_Direction_Rx, ///< Receive enable + SPI_Direction_Tx, ///< Transmit enable + SPI_Disable_Rx, ///< Receive disable + SPI_Disable_Tx ///< Transmit disable +} SPI_Direction_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SPI flag enum definition +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + SPI_FLAG_RXAVL = SPI_SR_RXAVL, ///< Receive 1 byte available data flag + SPI_FLAG_TXEPT = SPI_SR_TXEPT, ///< Transmitter empty flag + SPI_FLAG_TXFULL = SPI_SR_TXFULL, ///< Transmitter FIFO full status flag + SPI_FLAG_RXAVL_4BYTE = SPI_SR_RXAVL_4BYTE ///< Receive 4 bytes available data flag +} SPI_FLAG_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SPI slave mode data edge adjust enum definition +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + SPI_SlaveAdjust_LOW, ///< SPI slave mode data edge adjust in low speed mode + SPI_SlaveAdjust_FAST ///< SPI slave mode data edge adjust in fast speed mode +} SPI_SlaveAdjust_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SPI data edge adjust enum definition +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + SPI_DataEdgeAdjust_LOW, ///< SPI data edge adjust in low speed mode + SPI_DataEdgeAdjust_FAST ///< SPI data edge adjust in fast speed mode +} SPI_DataEdgeAdjust_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SPI interruput enum definition +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + SPI_IT_TXEPT = 0x40, ///< Transmitter empty interrupt + SPI_IT_RXFULL = 0x20, ///< RX FIFO full interrupt + SPI_IT_RXMATCH = 0x10, ///< Receive data match the RXDNR number interrut + SPI_IT_RXOERR = 0x08, ///< Receive overrun error interrupt + SPI_IT_UNDERRUN = 0x04, ///< Underrun interrupt + SPI_IT_RX = 0x02, ///< Receive available data interrupt + SPI_IT_TX = 0x01 ///< Transmit FIFO available interrupt +} SPI_IT_TypeDef; + + +typedef enum { + I2S_Standard_Phillips = 0x0000, + I2S_Standard_MSB = 0x0010, + I2S_Standard_LSB = 0x0020, + I2S_Standard_PCMShort = 0x0030, + I2S_Standard_PCMLong = 0x00B0, +} SPI_I2S_STANDARD_TypeDef; + + +typedef enum { + I2S_DataFormat_16b = 0x0000, + I2S_DataFormat_16bextended = 0x0001, + I2S_DataFormat_24b = 0x0003, + I2S_DataFormat_32b = 0x0005, +} SPI_I2S_DATAFORMAT_TypeDef; +typedef enum { + I2S_AudioFreq_192k = (192000), + I2S_AudioFreq_96k = (96000), + I2S_AudioFreq_48k = (48000), + I2S_AudioFreq_44k = (44100), + I2S_AudioFreq_32k = (32000), + I2S_AudioFreq_24k = (24000), + I2S_AudioFreq_22k = (22050), + I2S_AudioFreq_16k = (16000), + I2S_AudioFreq_11k = (11025), + I2S_AudioFreq_12k = (12000), + I2S_AudioFreq_8k = (8000), + I2S_AudioFreq_4k = (4000), + I2S_AudioFreq_Default = (2), +} SPI_I2S_AUDIO_FREQ_TypeDef; +typedef enum { + I2S_Mode_SlaveTx = 0x0000, + I2S_Mode_SlaveRx = 0x0100, + I2S_Mode_MasterTx = 0x0200, + I2S_Mode_MasterRx = 0x0300, +} SPI_I2S_TRANS_MODE_TypeDef; + +typedef enum { + I2S_MCLKOutput_Enable = 0x0800, + I2S_MCLKOutput_Disable = 0x0000, +} SPI_I2S_MCLK_OUTPUT_TypeDef; + +typedef enum { + I2S_CPOL_Low = 0x0000, ///< The clock is low in idle state. + I2S_CPOL_High = SPI_CCR_CPOL ///< The clock is high in idle state. +} SPI_I2S_CPOL_TypeDef; + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SPI Init structure definition +//////////////////////////////////////////////////////////////////////////////// +typedef struct { + SPI_Mode_TypeDef SPI_Mode; ///< Specifies the SPI operating mode + SPI_DataSize_TypeDef SPI_DataSize; ///< Specifies the SPI available data size + u8 SPI_DataWidth; ///< SPI data length + SPI_CPOL_TypeDef SPI_CPOL; ///< Specifies the serial clock steady state + SPI_CPHA_TypeDef SPI_CPHA; ///< Specifies the clock active edge for the bit capture + SPI_NSS_TypeDef SPI_NSS; ///< Specifies whether the NSS signal is managed by hardware or by software + SPI_BaudRatePrescaler_TypeDef SPI_BaudRatePrescaler; ///< Specifies the Baud Rate prescaler value which will be + ///< used to configure the transmit and receive SCK clock + SPI_FirstBit_TypeDef SPI_FirstBit; ///< Specifies whether data transfers start from MSB or LSB bit + // u16 SPI_length; +} SPI_InitTypeDef; +//////////////////////////////////////////////////////////////////////////////// +/// @brief I2S Init structure definition +//////////////////////////////////////////////////////////////////////////////// +typedef struct { + SPI_I2S_TRANS_MODE_TypeDef I2S_Mode; ///< Specifies the I2S operating mode. + SPI_I2S_STANDARD_TypeDef I2S_Standard; ///< Specifies the standard used for the I2S communication. + SPI_I2S_DATAFORMAT_TypeDef I2S_DataFormat; ///< Specifies the data format for the I2S communication. + SPI_I2S_MCLK_OUTPUT_TypeDef I2S_MCLKOutput; ///< Specifies whether the I2S MCLK output is enabled or not. + SPI_I2S_AUDIO_FREQ_TypeDef I2S_AudioFreq; ///< Specifies the frequency selected for the I2S communication. + SPI_I2S_CPOL_TypeDef I2S_CPOL; ///< Specifies the idle state of the I2S clock. +} I2S_InitTypeDef; +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup SPI_Exported_Constants +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup SPI_Register_Mask +/// @{ + +#define GCR_Mask ((u32)0x0FFF) +#define CCR_Mask ((u32)0x003F) +#define BRR_Mask ((u32)0xFFFF) +#define ECR_Mask ((u32)0x001F) + +/// @} + + +// SPI_7bit_8bit data width +#define SPI_DataWidth_1b ((u16)0x0001) +#define SPI_DataWidth_2b ((u16)0x0002) +#define SPI_DataWidth_3b ((u16)0x0003) +#define SPI_DataWidth_4b ((u16)0x0004) +#define SPI_DataWidth_5b ((u16)0x0005) +#define SPI_DataWidth_6b ((u16)0x0006) +#define SPI_DataWidth_7b ((u16)0x0007) +#define SPI_DataWidth_8b ((u16)0x0008) +#define SPI_DataWidth_9b ((u16)0x0009) +#define SPI_DataWidth_10b ((u16)0x000a) +#define SPI_DataWidth_11b ((u16)0x000b) +#define SPI_DataWidth_12b ((u16)0x000c) +#define SPI_DataWidth_13b ((u16)0x000d) +#define SPI_DataWidth_14b ((u16)0x000e) +#define SPI_DataWidth_15b ((u16)0x000f) +#define SPI_DataWidth_16b ((u16)0x0010) +#define SPI_DataWidth_17b ((u16)0x0011) +#define SPI_DataWidth_18b ((u16)0x0012) +#define SPI_DataWidth_19b ((u16)0x0013) +#define SPI_DataWidth_20b ((u16)0x0014) +#define SPI_DataWidth_21b ((u16)0x0015) +#define SPI_DataWidth_22b ((u16)0x0016) +#define SPI_DataWidth_23b ((u16)0x0017) +#define SPI_DataWidth_24b ((u16)0x0018) +#define SPI_DataWidth_25b ((u16)0x0019) +#define SPI_DataWidth_26b ((u16)0x001a) +#define SPI_DataWidth_27b ((u16)0x001b) +#define SPI_DataWidth_28b ((u16)0x001c) +#define SPI_DataWidth_29b ((u16)0x001d) +#define SPI_DataWidth_30b ((u16)0x001e) +#define SPI_DataWidth_31b ((u16)0x001f) +#define SPI_DataWidth_32b ((u16)0x0000) + + + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup SPI_Exported_Variables +/// @{ + +#ifdef _HAL_SPI_C_ +#define GLOBAL +#else +#define GLOBAL extern +#endif + +#undef GLOBAL + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup SPI_Exported_Functions +/// @{ + +void SPI_DeInit(SPI_TypeDef* spi); +void SPI_Init(SPI_TypeDef* spi, SPI_InitTypeDef* init_struct); +void SPI_StructInit(SPI_InitTypeDef* init_struct); +void SPI_Cmd(SPI_TypeDef* spi, FunctionalState state); +void SPI_ITConfig(SPI_TypeDef* spi, u8 interrupt, FunctionalState state); +void SPI_DMACmd(SPI_TypeDef* spi, FunctionalState state); +void SPI_FifoTrigger(SPI_TypeDef* spi, SPI_TLF_TypeDef fifo_trigger_value, FunctionalState state); +void SPI_SendData(SPI_TypeDef* spi, u32 data); +void SPI_CSInternalSelected(SPI_TypeDef* spi, FunctionalState state); +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* spi, SPI_NSS_TypeDef nss); + +void SPI_BiDirectionalLineConfig(SPI_TypeDef* spi, SPI_Direction_TypeDef direction); +void SPI_ClearITPendingBit(SPI_TypeDef* spi, SPI_IT_TypeDef interrupt); +void SPI_RxBytes(SPI_TypeDef* spi, u16 number); +void SPI_SlaveAdjust(SPI_TypeDef* spi, SPI_SlaveAdjust_TypeDef adjust_value); + +bool SPI_DataSizeConfig(SPI_TypeDef* spi, u8 data_size); +void SPI_DataSizeTypeConfig(SPI_TypeDef* spi, SPI_DataSize_TypeDef SPI_DataSize); +u32 SPI_ReceiveData(SPI_TypeDef* spi); + +FlagStatus SPI_GetFlagStatus(SPI_TypeDef* spi, SPI_FLAG_TypeDef flag); + +ITStatus SPI_GetITStatus(SPI_TypeDef* spi, SPI_IT_TypeDef interrupt); + +//////////////////////////////////////////////////////////////////////////////// +// Extended function interface +//////////////////////////////////////////////////////////////////////////////// +void exSPI_ITCmd(SPI_TypeDef* spi, FunctionalState state); +void exSPI_ITConfig(SPI_TypeDef* spi, SPI_IT_TypeDef interrput, FunctionalState state); +void exSPI_DMACmd(SPI_TypeDef* spi, FunctionalState state); +void exSPI_CSInternalSelected(SPI_TypeDef* spi, FunctionalState state); +void exSPI_DataEdgeAdjust(SPI_TypeDef* spi, SPI_DataEdgeAdjust_TypeDef adjust_value); +void I2S_Cmd(SPI_TypeDef* spi, FunctionalState state); +void I2S_Init(SPI_TypeDef* spi, I2S_InitTypeDef* I2S_InitStruct); +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +#endif //__HAL_SPI_H +//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_syscfg.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_syscfg.h new file mode 100644 index 000000000..e034f9626 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_syscfg.h @@ -0,0 +1,83 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_syscfg.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE EXTI +/// FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#ifndef __HAL_SYSCFG_H +#define __HAL_SYSCFG_H + +// Files includes +#include "types.h" +#include "mm32_device.h" +#include "hal_EXTI.H" +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup SYSCFG_HAL +/// @brief SYSCFG HAL modules +/// @{ + + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup SYSCFG_Exported_Types +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SYSCFG mode enumeration +//////////////////////////////////////////////////////////////////////////////// +// @defgroup SYSCFG_Memory_Remap_Config +#define SYSCFG_MemoryRemap_Flash ((u8)0x00) +#define SYSCFG_MemoryRemap_SystemMemory ((u8)0x01) +#define SYSCFG_MemoryRemap_SRAM ((u8)0x03) + + + + +/// +/// @} +/// + + + + +// Exported macro ------------------------------------------------------------ +// Exported functions ------------------------------------------------------- + +// Function used to set the SYSCFG configuration to the default reset state +#define SYSCFG_DeInit EXTI_DeInit +#define SYSCFG_MemoryRemapConfig EXTI_MemoryRemapConfig +#define SYSCFG_EXTILineConfig EXTI_LineConfig +u32 SYSCFG_GetPendingIT(u32 ITSourceLine); +void SYSCFG_BreakConfig(u32 SYSCFG_Break); +FlagStatus SYSCFG_GetFlagStatus(u32 SYSCFG_Flag); +void SYSCFG_ClearFlag(u32 SYSCFG_Flag); + + +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +#endif //__HAL_SYSCFG_H +//////////////////////////////////////////////////////////////////////////////// + + + diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_tim.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_tim.h new file mode 100644 index 000000000..4e57960dd --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_tim.h @@ -0,0 +1,755 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_tim.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE TIM +/// FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#ifndef __HAL_TIM_H +#define __HAL_TIM_H + +// Files includes +#include "types.h" +#include "reg_tim.h" + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup TIM_HAL +/// @brief TIM HAL modules +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup TIM_Exported_Types +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_Channel +/// @anchor TIM_Channel +typedef enum { + TIM_Channel_1 = 0x0000, ///< TIM Channel 1 + TIM_Channel_2 = 0x0004, ///< TIM Channel 2 + TIM_Channel_3 = 0x0008, ///< TIM Channel 3 + TIM_Channel_4 = 0x000C, ///< TIM Channel 4 + TIM_Channel_5 = 0x0010 ///< TIM Channel 5 +} TIMCHx_Typedef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_Counter_Mode +/// @anchor TIM_Counter_Mode +typedef enum { + TIM_CounterMode_Up = 0x0000, ///< TIM Up Counting Mode + TIM_CounterMode_Down = TIM_CR1_DIR, ///< TIM Down Counting Mode + TIM_CounterMode_CenterAligned1 = TIM_CR1_CMS_CENTERALIGNED1, ///< TIM Center Aligned Mode1 + TIM_CounterMode_CenterAligned2 = TIM_CR1_CMS_CENTERALIGNED2, ///< TIM Center Aligned Mode2 + TIM_CounterMode_CenterAligned3 = TIM_CR1_CMS_CENTERALIGNED3 ///< TIM Center Aligned Mode3 +} TIMCOUNTMODE_Typedef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_Output_Compare_and_PWM_modes_and_Forced_Action +/// @anchor TIM_Output_Compare_and_PWM_modes_and_Forced_Action +typedef enum { + TIM_OCMode_Timing = 0x0000, ///< Output compare mode: Timing + TIM_OCMode_Active = 0x0010, ///< Output compare mode: Active + TIM_OCMode_Inactive = 0x0020, ///< Output compare mode: Inactive + TIM_OCMode_Toggle = 0x0030, ///< Output compare mode: Toggle + TIM_OCMode_PWM1 = 0x0060, ///< Output compare mode: PWM1 + TIM_OCMode_PWM2 = 0x0070, ///< Output compare mode: PWM2 + TIM_ForcedAction_Active = 0x0050, ///< Force active level on OCnREF + TIM_ForcedAction_InActive = 0x0040 ///< Force inactive level on OCnREF +} TIMOCMODE_Typedef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_Clock_Division_CKD +/// @anchor TIM_Clock_Division_CKD +typedef enum { + TIM_CKD_DIV1 = TIM_CR1_CKD_DIV1, ///< TDTS = Tck_tim + TIM_CKD_DIV2 = TIM_CR1_CKD_DIV2, ///< TDTS = 2 * Tck_tim + TIM_CKD_DIV4 = TIM_CR1_CKD_DIV4 ///< TDTS = 4 * Tck_tim +} TIMCKD_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_Internal_Trigger_Selection +/// @anchor TIM_Internal_Trigger_Selection +typedef enum { + TIM_TS_ITR0 = TIM_SMCR_TS_ITR0, ///< Internal Trigger 0 + TIM_TS_ITR1 = TIM_SMCR_TS_ITR1, ///< Internal Trigger 1 + TIM_TS_ITR2 = TIM_SMCR_TS_ITR2, ///< Internal Trigger 2 + TIM_TS_ITR3 = TIM_SMCR_TS_ITR3, ///< Internal Trigger 3 + TIM_TS_TI1F_ED = TIM_SMCR_TS_TI1F_ED, ///< TI1 Edge Detector + TIM_TS_TI1FP1 = TIM_SMCR_TS_TI1FP1, ///< Filtered Timer Input 1 + TIM_TS_TI2FP2 = TIM_SMCR_TS_TI2FP2, ///< Filtered Timer Input 2 + TIM_TS_ETRF = TIM_SMCR_TS_ETRF ///< TI1 Edge Detector +} TIMTS_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_Trigger_Output_Source +/// @anchor TIM_Trigger_Output_Source +typedef enum { + TIM_TRIGSource_Reset = TIM_CR2_MMS_RESET, ///< The UG bit in the TIM_EGR register is used as the trigger output (TRIG). + TIM_TRIGSource_Enable = TIM_CR2_MMS_ENABLE, ///< The Counter Enable CEN is used as the trigger output (TRIG). + TIM_TRIGSource_Update = TIM_CR2_MMS_UPDATE, ///< The update event is used as the trigger output (TRIG). + TIM_TRIGSource_OC1 = TIM_CR2_MMS_OC1, ///< The trigger output sends a positive pulse when the CC1IF flag + ///< is to be set, as soon as a capture or compare match occurs (TRIG). + TIM_TRIGSource_OC1Ref = TIM_CR2_MMS_OC1REF, ///< OC1REF signal is used as the trigger output (TRIG). + TIM_TRIGSource_OC2Ref = TIM_CR2_MMS_OC2REF, ///< OC2REF signal is used as the trigger output (TRIG). + TIM_TRIGSource_OC3Ref = TIM_CR2_MMS_OC3REF, ///< OC3REF signal is used as the trigger output (TRIG). + TIM_TRIGSource_OC4Ref = TIM_CR2_MMS_OC4REF ///< OC4REF signal is used as the trigger output (TRIG). +} TIMMMS_Typedef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_Slave_Mode +/// @anchor TIM_Slave_Mode +typedef enum { + TIM_SlaveMode_Reset = TIM_SMCR_SMS_RESET, ///< Rising edge of the selected trigger signal (TRGI) re-initializes + ///< the counter and triggers an update of the registers. + TIM_SlaveMode_Gated = TIM_SMCR_SMS_GATED, ///< The counter clock is enabled when the trigger signal (TRGI) is high. + TIM_SlaveMode_Trigger = TIM_SMCR_SMS_TRIGGER, ///< The counter starts at a rising edge of the trigger TRGI. + TIM_SlaveMode_External1 = TIM_SMCR_SMS_EXTERNAL1 ///< Rising edges of the selected trigger (TRGI) clock the counter. +} TIMSMSMODE_Typedef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_Event_Source +/// @anchor TIM_Event_Source +typedef enum { + TIM_EventSource_Update = TIM_EGR_UG, ///< Timer update Event source + TIM_EventSource_CC1 = TIM_EGR_CC1G, ///< Timer Capture Compare 1 Event source + TIM_EventSource_CC2 = TIM_EGR_CC2G, ///< Timer Capture Compare 2 Event source + TIM_EventSource_CC3 = TIM_EGR_CC3G, ///< Timer Capture Compare 3 Event source + TIM_EventSource_CC4 = TIM_EGR_CC4G, ///< Timer Capture Compare 4 Event source + TIM_EventSource_COM = TIM_EGR_COMG, ///< Timer COM event source + TIM_EventSource_Trigger = TIM_EGR_TG, ///< Timer Trigger Event source + TIM_EventSource_Break = TIM_EGR_BG, ///< Timer Break event source + TIM_EventSource_CC5 = (s32)0x00010000, ///< Timer Capture Compare 5 Event source +} TIMEGR_Typedef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_External_Trigger_Prescaler +/// @anchor TIM_External_Trigger_Prescaler +typedef enum { + TIM_ExtTRGPSC_OFF = TIM_SMCR_ETPS_OFF, ///< ETRP Prescaler OFF + TIM_ExtTRGPSC_DIV2 = TIM_SMCR_ETPS_DIV2, ///< ETRP frequency divided by 2 + TIM_ExtTRGPSC_DIV4 = TIM_SMCR_ETPS_DIV4, ///< ETRP frequency divided by 4 + TIM_ExtTRGPSC_DIV8 = TIM_SMCR_ETPS_DIV8 ///< ETRP frequency divided by 8 +} TIMEXTTRGPSC_Typedef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_TIx_External_Clock_Source +/// @anchor TIM_TIx_External_Clock_Source +typedef enum { + TIM_TIxExternalCLK1Source_TI1 = TIM_SMCR_TS_TI1FP1, ///< Filtered Timer Input 1 + TIM_TIxExternalCLK1Source_TI2 = TIM_SMCR_TS_TI2FP2, ///< Filtered Timer Input 2 + TIM_TIxExternalCLK1Source_TI1ED = TIM_SMCR_TS_TI1F_ED ///< TI1 Edge Detector +} TIM_TIEXTCLKSRC_Typedef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Lock_level +/// @anchor Lock_level +typedef enum { + TIM_LOCKLevel_OFF = TIM_BDTR_LOCK_OFF, ///< No bit is write protected. + TIM_LOCKLevel_1 = TIM_BDTR_LOCK_1, ///< DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 + ///< register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written. + TIM_LOCKLevel_2 = TIM_BDTR_LOCK_2, ///< LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER + ///< register, as s32 as the related channel is configured in output through the CCxS + ///< bits) as well as OSSR and OSSI bits can no longer be written. + TIM_LOCKLevel_3 = TIM_BDTR_LOCK_3 ///< LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, + ///< as s32 as the related channel is configured in output through the CCxS bits) + ///< can no longer be written. +} TIMLOCKLEVEL_Typedef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_One_Pulse_Mode +/// @anchor TIM_One_Pulse_Mode +typedef enum { + TIM_OPMode_Repetitive = 0, ///< Counter is not stopped at update event + TIM_OPMode_Single = TIM_CR1_OPM ///< Counter stops counting at the next update event (clearing the bit CEN) +} TIMOPMODE_Typedef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_Output_Compare_Polarity +/// @anchor TIM_Output_Compare_Polarity +typedef enum { + TIM_OCPolarity_High, ///< Output Compare active high + TIM_OCPolarity_Low = TIM_CCER_CC1P ///< Output Compare active low +} TIMCCxP_Typedef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_Output_Compare_N_Polarity +/// @anchor TIM_Output_Compare_N_Polarity +typedef enum { + TIM_OCNPolarity_High, ///< Output Compare active high + TIM_OCNPolarity_Low = TIM_CCER_CC1NP ///< Output Compare active low +} TIMCCxNP_Typedef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_Output_Compare_state +/// @anchor TIM_Output_Compare_state +typedef enum { + TIM_OutputState_Disable = 0, ///< Output Compare Disable + TIM_OutputState_Enable = TIM_CCER_CC1EN ///< Output Compare Enable +} TIMOUTPUTSTATE_Typedef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_Output_Compare_N_state +/// @anchor TIM_Output_Compare_N_state +typedef enum { + TIM_OutputNState_Disable = 0, ///< Output Compare N Disable + TIM_OutputNState_Enable = TIM_CCER_CC1NEN ///< Output Compare N Enable +} TIMOUTPUTNSTATE_Typedef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_Capture_Compare_state +/// @anchor TIM_Capture_Compare_state +typedef enum { + TIM_CCx_Disable = 0, ///< Capture/Compare Enable + TIM_CCx_Enable = TIM_CCER_CC1EN ///< Capture/Compare Enable +} TIMCCxE_Typedef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_Capture_Compare_N_state +/// @anchor TIM_Capture_Compare_N_state +typedef enum { + TIM_CCxN_Disable = 0, ///< Capture/Compare N Enable + TIM_CCxN_Enable = TIM_CCER_CC1NEN ///< Capture/Compare N Enable +} TIMCCxNE_Typedef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Break_Input_enable_disable +/// @anchor Break_Input_enable_disable +typedef enum { + TIM_Break_Disable = 0, ///< Break inputs (BRK and CSS clock failure event) disabled + TIM_Break_Enable = TIM_BDTR_BKEN ///< Break inputs (BRK and CSS clock failure event) enabled +} TIMBKE_Typedef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Break_Polarity +/// @anchor Break_Polarity +typedef enum { + TIM_BreakPolarity_Low = 0, ///< Break input BRK is active low + TIM_BreakPolarity_High = TIM_BDTR_BKP ///< Break input BRK is active high +} TIMBKP_Typedef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_AOE_Bit_Set_Reset +/// @anchor TIM_AOE_Bit_Set_Reset +typedef enum { + TIM_AutomaticOutput_Disable = 0, ///< MOE can be set only by software. + TIM_AutomaticOutput_Enable = TIM_BDTR_AOEN ///< MOE can be set by software or automatically at the next + ///< update event (if the break input is not be active). +} TIMAOE_Typedef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_DOE_Bit_Set_Reset +/// @anchor TIM_DOE_Bit_Set_Reset +typedef enum { + TIM_DirectOutput_Disable = 0, ///< Direct output disable, output waiting for dead time + TIM_DirectOutput_Enable = TIM_BDTR_DOEN ///< Direct output enable, no longer waiting for output after dead time +} TIMDOE_Typedef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief OSSI_Off_State_Selection_for_Idle_mode_state +/// @anchor OSSI_Off_State_Selection_for_Idle_mode_state +typedef enum { + TIM_OSSIState_Disable = 0, ///< When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0). + TIM_OSSIState_Enable = TIM_BDTR_OSSI ///< When inactive, OC/OCN outputs are forced first with their idle level + ///< as soon as CCxE=1 or CCxNE=1. OC/OCN enable output signal=1). +} TIMOSSI_Typedef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief OSSR_Off_State_Selection_for_Run_mode_state +/// @anchor OSSR_Off_State_Selection_for_Run_mode_state +typedef enum { + TIM_OSSRState_Disable = 0, ///< When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0). + TIM_OSSRState_Enable = TIM_BDTR_OSSR ///< When inactive, OC/OCN outputs are enabled with their inactive level + ///< as soon as CCxE=1 or CCxNE=1. Then, OC/OCN enable output signal=1. +} TIMOSSR_Typedef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_Output_Compare_Idle_State +/// @anchor TIM_Output_Compare_Idle_State +typedef enum { + TIM_OCIdleState_Reset = 0, ///< OCn=0 (after a dead-time if OCnN is implemented) when MOE=0.(n= 0 : 4) + TIM_OCIdleState_Set = TIM_CR2_OIS1 ///< OCn=1 (after a dead-time if OCnN is implemented) when MOE=0.(n= 0 : 4) +} TIMOIS_Typedef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_Output_Compare_N_Idle_State +/// @anchor TIM_Output_Compare_N_Idle_State +typedef enum { + TIM_OCNIdleState_Reset = 0, ///< OCnN=0 after a dead-time when MOE=0.(n= 0 : 4) + TIM_OCNIdleState_Set = TIM_CR2_OIS1N ///< OCnN=1 after a dead-time when MOE=0.(n= 0 : 4) +} TIMOISN_Typedef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_Input_Capture_Selection +/// @anchor TIM_Input_Capture_Selection +typedef enum { + TIM_ICSelection_DirectTI = TIM_CCMR1_CC1S_DIRECTTI, + TIM_ICSelection_IndirectTI = TIM_CCMR1_CC1S_INDIRECTTI, + TIM_ICSelection_TRC = TIM_CCMR1_CC1S_TRC ///< TIM Input is selected to be connected to TRC. +} TIMICSEL_Typedef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_Input_Capture_Prescaler +/// @anchor TIM_Input_Capture_Prescaler +typedef enum { + TIM_ICPSC_DIV1 = 0x0000, ///< no prescaler + TIM_ICPSC_DIV2 = 0x0004, ///< capture is done once every 2 events + TIM_ICPSC_DIV4 = 0x0008, ///< capture is done once every 4 events + TIM_ICPSC_DIV8 = 0x000C ///< capture is done once every 8 events +} TIMICPSC_Typedef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_Input_Capture_Polarity +/// @anchor TIM_Input_Capture_Polarity +typedef enum { + TIM_ICPolarity_Rising = 0, ///< IC Rising edge + TIM_ICPolarity_Falling = TIM_CCER_CC1P, ///< IC Falling edge + TIM_ICPolarity_BothEdge = TIM_CCER_CC1P | TIM_CCER_CC1NP +} TIMICP_Typedef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_External_Trigger_Polarity +/// @anchor TIM_External_Trigger_Polarity +typedef enum { + TIM_ExtTRGPolarity_NonInverted = 0, ///< Active high or rising edge active + TIM_ExtTRGPolarity_Inverted = TIM_SMCR_ETP ///< Active low or falling edge active +} TIMETP_Typedef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_Prescaler_Reload_Mode +/// @anchor TIM_Prescaler_Reload_Mode +typedef enum { + TIM_PSCReloadMode_Update = 0, ///< The Prescaler is loaded at the update event + TIM_PSCReloadMode_Immediate = TIM_EGR_UG ///< The Prescaler is loaded immediately +} TIMUG_Typedef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_Encoder_Mode +/// @anchor TIM_Encoder_Mode +typedef enum { + TIM_EncoderMode_TI1 = TIM_SMCR_SMS_ENCODER1, ///< Counter counts on TI1FP1 edge depending on TI2FP2 level. + TIM_EncoderMode_TI2 = TIM_SMCR_SMS_ENCODER2, ///< Counter counts on TI2FP2 edge depending on TI1FP1 level. + TIM_EncoderMode_TI12 = TIM_SMCR_SMS_ENCODER3 ///< Counter counts on both TI1FP1 and TI2FP2 edges depending + ///< on the level of the other input. +} TIMSMSENCODER_Typedef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_Update_Source +/// @anchor TIM_Update_Source +typedef enum { + TIM_UpdateSource_Global = 0, ///< Source of update is counter overflow/underflow. + TIM_UpdateSource_Regular = TIM_CR1_URS ///< Source of update is the counter overflow/underflow + ///< or the setting of UG bit, or an update generation + ///< through the slave mode controller. +} TIMURS_Typedef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_Output_Compare_Preload_State +/// @anchor TIM_Output_Compare_Preload_State +typedef enum { + TIM_OCPreload_Disable = 0, ///< TIM output compare preload disable + TIM_OCPreload_Enable = TIM_CCMR1_OC1PEN ///< TIM output compare preload enable +} TIMOCPE_Typedef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_Output_Compare_Fast_State +/// @anchor TIM_Output_Compare_Fast_State +typedef enum { + TIM_OCFast_Disable = 0, ///< TIM output compare fast disable + TIM_OCFast_Enable = TIM_CCMR1_OC1FEN, ///< TIM output compare fast enable +} TIMOCFE_Typedef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_Output_Compare_Clear_State +/// @anchor TIM_Output_Compare_Clear_State +typedef enum { + TIM_OCClear_Disable = 0, ///< TIM Output clear disable + TIM_OCClear_Enable = TIM_CCMR1_OC1CEN ///< TIM Output clear enable +} TIMOCCE_Typedef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_Master_Slave_Mode +/// @anchor TIM_Master_Slave_Mode +typedef enum { + TIM_MasterSlaveMode_Disable = 0, ///< No action + TIM_MasterSlaveMode_Enable = TIM_SMCR_MSM ///< synchronization between the current timer and its slaves (through TRIG) +} TIMMSM_Typedef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_interrupt_sources +/// @anchor TIM_Master_Slave_Mode +typedef enum { + TIM_IT_Update = TIM_DIER_UI, ///< TIM update Interrupt source + TIM_IT_CC1 = TIM_DIER_CC1I, ///< TIM Capture Compare 1 Interrupt source + TIM_IT_CC2 = TIM_DIER_CC2I, ///< TIM Capture Compare 2 Interrupt source + TIM_IT_CC3 = TIM_DIER_CC3I, ///< TIM Capture Compare 3 Interrupt source + TIM_IT_CC4 = TIM_DIER_CC4I, ///< TIM Capture Compare 4 Interrupt source + TIM_IT_COM = TIM_DIER_COMI, ///< TIM Commutation Interrupt source + TIM_IT_Trigger = TIM_DIER_TI, ///< TIM Trigger Interrupt source + TIM_IT_Break = TIM_DIER_BI ///< TIM Break Interrupt source + , TIM_IT_CC5 = TIM_DIER_CC5I ///< TIM Capture Compare 5 Interrupt source +} TIMIT_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_Flags +/// @anchor TIM_Flags +typedef enum { + TIM_FLAG_Update = TIM_SR_UI, ///< TIM update Flag + TIM_FLAG_CC1 = TIM_SR_CC1I, ///< TIM Capture Compare 1 Flag + TIM_FLAG_CC2 = TIM_SR_CC2I, ///< TIM Capture Compare 2 Flag + TIM_FLAG_CC3 = TIM_SR_CC3I, ///< TIM Capture Compare 3 Flag + TIM_FLAG_CC4 = TIM_SR_CC4I, ///< TIM Capture Compare 4 Flag + TIM_FLAG_COM = TIM_SR_COMI, ///< TIM Commutation Flag + TIM_FLAG_Trigger = TIM_SR_TI, ///< TIM Trigger Flag + TIM_FLAG_Break = TIM_SR_BI, ///< TIM Break Flag + TIM_FLAG_CC1OF = TIM_SR_CC1O, ///< TIM Capture Compare 1 overcapture Flag + TIM_FLAG_CC2OF = TIM_SR_CC2O, ///< TIM Capture Compare 2 overcapture Flag + TIM_FLAG_CC3OF = TIM_SR_CC3O, ///< TIM Capture Compare 3 overcapture Flag + TIM_FLAG_CC4OF = TIM_SR_CC4O ///< TIM Capture Compare 4 overcapture Flag + , TIM_FLAG_CC5 = TIM_SR_CC5I ///< TIM Capture Compare 5 Flag +} TIMFLAG_Typedef; +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_DMA_sources +/// @anchor TIM_DMA_sources +typedef enum { + TIM_DMA_Update = TIM_DIER_UD, ///< TIM update Interrupt source + TIM_DMA_CC1 = TIM_DIER_CC1D, ///< TIM Capture Compare 1 DMA source + TIM_DMA_CC2 = TIM_DIER_CC2D, ///< TIM Capture Compare 2 DMA source + TIM_DMA_CC3 = TIM_DIER_CC3D, ///< TIM Capture Compare 3 DMA source + TIM_DMA_CC4 = TIM_DIER_CC4D, ///< TIM Capture Compare 4 DMA source + TIM_DMA_COM = TIM_DIER_COMD, ///< TIM Commutation DMA source + TIM_DMA_Trigger = TIM_DIER_TD ///< TIM Trigger DMA source +} TIMDMASRC_Typedef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_DMA_Base_address +/// @anchor TIM_DMA_Base_address +typedef enum { + TIM_DMABase_CR1 = 0x0000, + TIM_DMABase_CR2 = 0x0001, + TIM_DMABase_SMCR = 0x0002, + TIM_DMABase_DIER = 0x0003, + TIM_DMABase_SR = 0x0004, + TIM_DMABase_EGR = 0x0005, + TIM_DMABase_CCMR1 = 0x0006, + TIM_DMABase_CCMR2 = 0x0007, + TIM_DMABase_CCER = 0x0008, + TIM_DMABase_CNT = 0x0009, + TIM_DMABase_PSC = 0x000A, + TIM_DMABase_ARR = 0x000B, + TIM_DMABase_RCR = 0x000C, + TIM_DMABase_CCR1 = 0x000D, + TIM_DMABase_CCR2 = 0x000E, + TIM_DMABase_CCR3 = 0x000F, + TIM_DMABase_CCR4 = 0x0010, + TIM_DMABase_BDTR = 0x0011, + TIM_DMABase_DCR = 0x0012 +} TIMDMABASE_Typedef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_DMA_Burst_Length +/// @anchor TIM_DMA_Burst_Length +typedef enum { + TIM_DMABurstLength_1Byte = 0x0000, + TIM_DMABurstLength_2Bytes = 0x0100, + TIM_DMABurstLength_3Bytes = 0x0200, + TIM_DMABurstLength_4Bytes = 0x0300, + TIM_DMABurstLength_5Bytes = 0x0400, + TIM_DMABurstLength_6Bytes = 0x0500, + TIM_DMABurstLength_7Bytes = 0x0600, + TIM_DMABurstLength_8Bytes = 0x0700, + TIM_DMABurstLength_9Bytes = 0x0800, + TIM_DMABurstLength_10Bytes = 0x0900, + TIM_DMABurstLength_11Bytes = 0x0A00, + TIM_DMABurstLength_12Bytes = 0x0B00, + TIM_DMABurstLength_13Bytes = 0x0C00, + TIM_DMABurstLength_14Bytes = 0x0D00, + TIM_DMABurstLength_15Bytes = 0x0E00, + TIM_DMABurstLength_16Bytes = 0x0F00, + TIM_DMABurstLength_17Bytes = 0x1000, + TIM_DMABurstLength_18Bytes = 0x1100 +} TIMDMABURSTLENGTH_Typedef; +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM Time Base Init structure definition +/// @note This structure is used with all tim. +//////////////////////////////////////////////////////////////////////////////// +typedef struct { + u16 TIM_Prescaler; ///< Specifies the prescaler value used to divide the TIM clock. + ///< This parameter can be a number between 0x0000 and 0xFFFF + TIMCOUNTMODE_Typedef TIM_CounterMode; ///< Specifies the counter mode. + ///< This parameter can be a value of @ref TIM_Counter_Mode + u32 TIM_Period; ///< Specifies the period value to be loaded into the active + ///< Auto-Reload Register at the next update event. + ///< This parameter must be a number between 0x0000 and 0xFFFF/0xFFFFFFFF. + ///< @note 0xFFFFFFFF is valid only for MM32 32bit Timers: eg.TIM2 or TIM5. + TIMCKD_TypeDef TIM_ClockDivision; ///< Specifies the clock division. + ///< This parameter can be a value of @ref TIM_Clock_Division_CKD + u8 TIM_RepetitionCounter; ///< Specifies the repetition counter value. Each time the RCR downcounter + ///< reaches zero, an update event is generated and counting restarts + ///< from the RCR value (N). + ///< This means in PWM mode that (N+1) corresponds to: + ///< - the number of PWM periods in edge-aligned mode + ///< - the number of half PWM period in center-aligned mode + ///< This parameter must be a number between 0x00 and 0xFF. + ///< @note This parameter is valid only for TIM1 and TIM8. +} TIM_TimeBaseInitTypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM Output Compare Init structure definition +//////////////////////////////////////////////////////////////////////////////// +typedef struct { + TIMOCMODE_Typedef TIM_OCMode; ///< Specifies the TIM mode. + ///< This parameter can be a value of TIM_Output_Compare_and_PWM_modes + TIMOUTPUTSTATE_Typedef TIM_OutputState; ///< Specifies the TIM Output Compare state. + ///< This parameter can be a value of TIM_Output_Compare_state + TIMOUTPUTNSTATE_Typedef TIM_OutputNState; ///< Specifies the TIM complementary Output Compare state. + ///< This parameter can be a value of TIM_Output_Compare_N_state + ///< @note This parameter is valid only for TIM1 and TIM8. + u32 TIM_Pulse; ///< Specifies the pulse value to be loaded into the Capture Compare Register. + ///< This parameter can be a number between 0x0000 and 0xFFFF/0xFFFFFFFF + ///< @note 0xFFFFFFFF is valid only for MM32 32bit Timers: eg.TIM2 or TIM5. + TIMCCxP_Typedef TIM_OCPolarity; ///< Specifies the output polarity. + ///< This parameter can be a value of @ref TIM_Output_Compare_Polarity + TIMCCxNP_Typedef TIM_OCNPolarity; ///< Specifies the complementary output polarity. + ///< This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + ///< @note This parameter is valid only for TIM1 and TIM8. + TIMOIS_Typedef TIM_OCIdleState; ///< Specifies the TIM Output Compare pin state during Idle state. + ///< This parameter can be a value of @ref TIM_Output_Compare_Idle_State + ///< @note This parameter is valid only for TIM1 and TIM8. + TIMOISN_Typedef TIM_OCNIdleState; ///< Specifies the TIM Output Compare pin state during Idle state. + ///< This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + ///< @note This parameter is valid only for TIM1 and TIM8. +} TIM_OCInitTypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM Input Capture Init structure definition +//////////////////////////////////////////////////////////////////////////////// +typedef struct { + TIMCHx_Typedef TIM_Channel; ///< Specifies the TIM channel. + ///< This parameter can be a value of @ref TIM_Channel + TIMICP_Typedef TIM_ICPolarity; ///< Specifies the active edge of the input signal. + ///< This parameter can be a value of @ref TIM_Input_Capture_Polarity + TIMICSEL_Typedef TIM_ICSelection; ///< Specifies the input. + ///< This parameter can be a value of @ref TIM_Input_Capture_Selection + TIMICPSC_Typedef TIM_ICPrescaler; ///< Specifies the Input Capture Prescaler. + ///< This parameter can be a value of @ref TIM_Input_Capture_Prescaler + u16 TIM_ICFilter; ///< Specifies the input capture filter. + ///< This parameter can be a number between 0x0 and 0xF +} TIM_ICInitTypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief BDTR structure definition +/// @note This structure is used only with TIM1 and TIM8. +//////////////////////////////////////////////////////////////////////////////// +typedef struct { + TIMOSSR_Typedef TIM_OSSRState; ///< Specifies the Off-State selection used in Run mode. + ///< This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state + TIMOSSI_Typedef TIM_OSSIState; ///< Specifies the Off-State used in Idle state. + ///< This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state + TIMLOCKLEVEL_Typedef TIM_LOCKLevel; ///< Specifies the LOCK level parameters. + ///< This parameter can be a value of @ref Lock_level + u16 TIM_DeadTime; ///< Specifies the delay time between the switching-off and + ///< the switching-on of the outputs. + ///< This parameter can be a number between 0x00 and 0xFF + TIMBKE_Typedef TIM_Break; ///< Specifies whether the TIM Break input is enabled or not. + ///< This parameter can be a value of @ref Break_Input_enable_disable + TIMBKP_Typedef TIM_BreakPolarity; ///< Specifies the TIM Break Input pin polarity. + ///< This parameter can be a value of @ref Break_Polarity + TIMAOE_Typedef TIM_AutomaticOutput; ///< Specifies whether the TIM Automatic Output feature is enabled or not. + ///< This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset +} TIM_BDTRInitTypeDef; +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup TIM_Exported_Variables +/// @{ +#ifdef _HAL_TIM_C_ +#define GLOBAL + +static void TI1_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter); +static void TI2_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter); +static void TI3_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter); +static void TI4_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter); + + +#else +#define GLOBAL extern +#endif + +#undef GLOBAL +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup TIM_Exported_Functions +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +//================= TimeBase management ====================================== +void TIM_DeInit(TIM_TypeDef* tim); +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* init_struct); +void TIM_TimeBaseInit(TIM_TypeDef* tim, TIM_TimeBaseInitTypeDef* init_struct); +void TIM_PrescalerConfig(TIM_TypeDef* tim, u16 prescaler, TIMUG_Typedef reload_mode); +void TIM_CounterModeConfig(TIM_TypeDef* tim, TIMCOUNTMODE_Typedef counter_mode); +void TIM_SetCounter(TIM_TypeDef* tim, u32 counter); +void TIM_SetAutoreload(TIM_TypeDef* tim, u16 auto_reload); +void TIM_UpdateDisableConfig(TIM_TypeDef* tim, FunctionalState state); +void TIM_UpdateRequestConfig(TIM_TypeDef* tim, TIMURS_Typedef source); +void TIM_ARRPreloadConfig(TIM_TypeDef* tim, FunctionalState state); +void TIM_SelectOnePulseMode(TIM_TypeDef* tim, TIMOPMODE_Typedef mode); +void TIM_SetClockDivision(TIM_TypeDef* tim, TIMCKD_TypeDef clock_div); +void TIM_Cmd(TIM_TypeDef* tim, FunctionalState state); + +u32 TIM_GetCounter(TIM_TypeDef* tim); +u16 TIM_GetPrescaler(TIM_TypeDef* tim); + +//================= Advanced-control timers specific features ================ +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* init_struct); +void TIM_BDTRConfig(TIM_TypeDef* tim, TIM_BDTRInitTypeDef* init_struct); +void TIM_CtrlPWMOutputs(TIM_TypeDef* tim, FunctionalState state); + +//================= Output Compare management ================================ +void TIM_OCStructInit(TIM_OCInitTypeDef* init_struct); +void TIM_OC1Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct); +void TIM_OC2Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct); +void TIM_OC3Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct); +void TIM_OC4Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct); +void TIM_SelectOCxM(TIM_TypeDef* tim, TIMCHx_Typedef channel, TIMOCMODE_Typedef mode); +void TIM_SetCompare1(TIM_TypeDef* tim, u32 compare); +void TIM_SetCompare2(TIM_TypeDef* tim, u32 compare); +void TIM_SetCompare3(TIM_TypeDef* tim, u32 compare); +void TIM_SetCompare4(TIM_TypeDef* tim, u32 compare); +void TIM_ForcedOC1Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action); +void TIM_ForcedOC2Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action); +void TIM_ForcedOC3Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action); +void TIM_ForcedOC4Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action); +void TIM_CCPreloadControl(TIM_TypeDef* tim, FunctionalState state); +void TIM_OC1PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload); +void TIM_OC2PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload); +void TIM_OC3PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload); +void TIM_OC4PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload); +void TIM_OC1FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast); +void TIM_OC2FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast); +void TIM_OC3FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast); +void TIM_OC4FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast); +void TIM_ClearOC1Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear); +void TIM_ClearOC2Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear); +void TIM_ClearOC3Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear); +void TIM_ClearOC4Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear); +void TIM_OC1PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity); +void TIM_OC1NPolarityConfig(TIM_TypeDef* tim, TIMCCxNP_Typedef polarity); +void TIM_OC2PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity); +void TIM_OC2NPolarityConfig(TIM_TypeDef* tim, TIMCCxNP_Typedef polarity); +void TIM_OC3PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity); +void TIM_OC3NPolarityConfig(TIM_TypeDef* tim, TIMCCxNP_Typedef polarity); +void TIM_OC4PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity); +void TIM_CCxCmd(TIM_TypeDef* tim, TIMCHx_Typedef channel, TIMCCxE_Typedef ccx_en); +void TIM_CCxNCmd(TIM_TypeDef* tim, TIMCHx_Typedef channel, TIMCCxNE_Typedef ccxn_en); +void TIM_SelectCOM(TIM_TypeDef* tim, FunctionalState state); + +//================= Input Capture management ================================= +void TIM_ICStructInit(TIM_ICInitTypeDef* init_struct); +void TIM_ICInit(TIM_TypeDef* tim, TIM_ICInitTypeDef* init_struct); +void TIM_PWMIConfig(TIM_TypeDef* tim, TIM_ICInitTypeDef* init_struct); +void TIM_SetIC1Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc); +void TIM_SetIC2Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc); +void TIM_SetIC3Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc); +void TIM_SetIC4Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc); + +u32 TIM_GetCapture1(TIM_TypeDef* tim); +u32 TIM_GetCapture2(TIM_TypeDef* tim); +u32 TIM_GetCapture3(TIM_TypeDef* tim); +u32 TIM_GetCapture4(TIM_TypeDef* tim); + +//================= Interrupts, DMA and flags management ===================== +void TIM_ITConfig(TIM_TypeDef* tim, u32 it, FunctionalState state);//TIMIT_TypeDef +void TIM_GenerateEvent(TIM_TypeDef* tim, TIMEGR_Typedef source); +void TIM_ClearFlag(TIM_TypeDef* tim, TIMFLAG_Typedef flag); +void TIM_ClearITPendingBit(TIM_TypeDef* tim, u32 it);//TIMIT_TypeDef +void TIM_DMAConfig(TIM_TypeDef* tim, TIMDMABASE_Typedef dma_base, TIMDMABURSTLENGTH_Typedef length); +void TIM_DMACmd(TIM_TypeDef* tim, TIMDMASRC_Typedef source, FunctionalState state); +void TIM_SelectCCDMA(TIM_TypeDef* tim, FunctionalState state); +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* tim, TIMFLAG_Typedef flag); +ITStatus TIM_GetITStatus(TIM_TypeDef* tim, TIMIT_TypeDef it); + +//================= Clocks management ======================================== +void TIM_InternalClockConfig(TIM_TypeDef* tim); +void TIM_ITRxExternalClockConfig(TIM_TypeDef* tim, TIMTS_TypeDef source); +void TIM_TIxExternalClockConfig(TIM_TypeDef* tim, TIM_TIEXTCLKSRC_Typedef source, TIMICP_Typedef polarity, u16 filter); +void TIM_ETRClockMode1Config(TIM_TypeDef* tim, TIMEXTTRGPSC_Typedef psc, TIMETP_Typedef polarity, u16 filter); +void TIM_ETRClockMode2Config(TIM_TypeDef* tim, TIMEXTTRGPSC_Typedef psc, TIMETP_Typedef polarity, u16 filter); + +//================= Synchronization management =============================== +void TIM_SelectInputTrigger(TIM_TypeDef* tim, TIMTS_TypeDef source); +void TIM_SelectOutputTrigger(TIM_TypeDef* tim, TIMMMS_Typedef source); +void TIM_SelectSlaveMode(TIM_TypeDef* tim, TIMSMSMODE_Typedef mode); +void TIM_SelectMasterSlaveMode(TIM_TypeDef* tim, TIMMSM_Typedef mode); +void TIM_ETRConfig(TIM_TypeDef* tim, TIMEXTTRGPSC_Typedef psc, TIMETP_Typedef polarity, u16 filter); + +//================= Specific interface management ============================ +void TIM_EncoderInterfaceConfig(TIM_TypeDef* tim, + TIMSMSENCODER_Typedef encoder_mode, + TIMICP_Typedef ic1_polarity, + TIMICP_Typedef iC2_polarity); +void TIM_SelectHallSensor(TIM_TypeDef* tim, FunctionalState state); + +//================= extend Channel IC management ============================== +void TIM_SetIC1Plority(TIM_TypeDef* tim, TIMICP_Typedef pol); +void TIM_SetIC2Plority(TIM_TypeDef* tim, TIMICP_Typedef pol); +void TIM_SetIC3Plority(TIM_TypeDef* tim, TIMICP_Typedef pol); +void TIM_SetIC4Plority(TIM_TypeDef* tim, TIMICP_Typedef pol); + +#define exTIM_SetIC1Plority TIM_SetIC1Plority +#define exTIM_SetIC2Plority TIM_SetIC2Plority +#define exTIM_SetIC3Plority TIM_SetIC3Plority +#define exTIM_SetIC4Plority TIM_SetIC4Plority +//================= extend Channel 5 management ============================== + +void TIM_SetCompare5(TIM_TypeDef* tim, u32 compare); +void TIM_OC5Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct); +void TIM_OC5PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload); +void TIM_OC5PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity); +void TIM_OC5FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast); +void TIM_ClearOC5Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear); +u32 TIM_GetCapture5(TIM_TypeDef* tim); + +#define exTIM_SetCompare5 TIM_SetCompare5 +#define exTIM_OC5Init TIM_OC5Init +#define exTIM_OC5PreloadConfig TIM_OC5PreloadConfig +#define exTIM_OC5PolarityConfig TIM_OC5PolarityConfig +#define exTIM_OC5FastConfig TIM_OC5FastConfig +#define exTIM_ClearOC5Ref TIM_ClearOC5Ref +#define exTIM_GetCapture5 TIM_GetCapture5 + +//============= extend Advanced-control timers specific features ============== +void TIM_DirectOutput(TIM_TypeDef* tim, FunctionalState state); +#define exTIM_DirectOutput TIM_DirectOutput +void TIM_PWMShiftConfig(TIM_TypeDef* tim, u32 it, FunctionalState state); +void TIM_SetCCR1FALL(TIM_TypeDef* tim, u32 shift); +void TIM_SetCCR2FALL(TIM_TypeDef* tim, u32 shift); +void TIM_SetCCR3FALL(TIM_TypeDef* tim, u32 shift); +void TIM_SetCCR4FALL(TIM_TypeDef* tim, u32 shift); +void TIM_SetCCR5FALL(TIM_TypeDef* tim, u32 shift); +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +#endif // __HAL_TIM_H +//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_uart.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_uart.h new file mode 100644 index 000000000..a46f234e0 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_uart.h @@ -0,0 +1,211 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_uart.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE UART +/// FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

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+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#ifndef __HAL_UART_H +#define __HAL_UART_H + +// Files includes +#include "reg_uart.h" + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +/////////////////////////////////////1/////////////////////////////////////////// +/// @defgroup UART_HAL +/// @brief UART HAL modules +/// @{ + + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup UART_Exported_Types +/// @{ +/// + +//////////////////////////////////////////////////////////////////////////////// +/// @brief UART Word Length Enumerate definition +/// @anchor UART_Word_Length +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + UART_WordLength_5b = 0U, + UART_WordLength_6b = 1U << UART_CCR_CHAR_Pos, + UART_WordLength_7b = 2U << UART_CCR_CHAR_Pos, + UART_WordLength_8b = 3U << UART_CCR_CHAR_Pos +} UART_WordLength_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief UART Stop Bits Enumerate definition +/// @anchor UART_Stop_Bits +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + UART_StopBits_1 = 0U, + UART_StopBits_2 = UART_CCR_SPB, + + UART_StopBits_0_5 = UART_CCR_SPB1, + UART_StopBits_1_5 = UART_CCR_SPB1 | UART_CCR_SPB0, +} UART_Stop_Bits_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief UART Parity Enumerate definition +/// @anchor UART_Parity +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + UART_Parity_No = 0U, + UART_Parity_Even = UART_CCR_PEN | UART_CCR_PSEL, + UART_Parity_Odd = UART_CCR_PEN +} UART_Parity_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief UART Hardware Flow Control Enumerate definition +/// @anchor UART_Hardware_Flow_Control +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + UART_HWFlowControl_None = 0U, + + // UART_HWFlowControl_RTS = UART_GCR_AUTOFLOW, + // UART_HWFlowControl_CTS = UART_GCR_AUTOFLOW, + + UART_HWFlowControl_RTS_CTS = UART_GCR_AUTOFLOW +} UART_HW_FLOWCONTROL_TypeDef; + +typedef enum { + UART_WakeUp_IdleLine = 0U, // + UART_WakeUp_AddressMark = UART_CCR_WAKE +} UART_WakeUp_TypeDef; + +typedef enum { + UART_9bit_Polarity_Low = 0U, // + UART_9bit_Polarity_High = UART_CCR_B8POL +} UART_9bit_Polarity_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief UART Auto BaudRate definition +//////////////////////////////////////////////////////////////////////////////// +typedef enum { + Data_F8 = 0, + Data_FE, + ABRMODE_FALLING_TO_RISINGEDGE1BIT, + ABRMODE_FALLING_TO_RISINGEDGE2BIT, + ABRMODE_FALLING_TO_RISINGEDGE4BIT, + ABRMODE_FALLING_TO_RISINGEDGE8BIT, + ABRMODE_FALLING_TO_FALLINGEDGE2BIT, + ABRMODE_FALLING_TO_FALLINGEDGE4BIT, + ABRMODE_FALLING_TO_FALLINGEDGE8BIT, + ABRMODE_STARTBIT, + ABRMODE_VALUE0X55, + ABRMODE_VALUE0x7F, + ABRMODE_VALUE0X80, + ABRMODE_VALUE0XF7, + ABRMODE_VALUE0XF8 = Data_F8, + ABRMODE_VALUE0XFE = Data_FE, + ABRMODE_VALUE0XFF, +} UART_AutoBaud_TypeDef; +//////////////////////////////////////////////////////////////////////////////// +/// @brief UART Init Structure definition +//////////////////////////////////////////////////////////////////////////////// +typedef struct { + union { + u32 BaudRate; ///< This member configures the UART communication baud rate. + u32 UART_BaudRate; + }; + union { + UART_WordLength_TypeDef WordLength; ///< Specifies the number of data bits transmitted or received in a frame. + u16 UART_WordLength; + }; + union { + UART_Stop_Bits_TypeDef StopBits; ///< Specifies the number of stop bits transmitted. + u16 UART_StopBits; + }; + union { + UART_Parity_TypeDef Parity; ///< Specifies the parity mode. + u16 UART_Parity; + }; + union { + u16 Mode; ///< Specifies wether the Receive or Transmit mode is + u16 UART_Mode; + }; + union { + UART_HW_FLOWCONTROL_TypeDef HWFlowControl; ///< Specifies wether the hardware flow control mode is enabled or disabled. + u16 UART_HardwareFlowControl; + }; +} UART_InitTypeDef; + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup UART_Exported_Constants +/// @{ + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup UART_Exported_Variables +/// @{ +#ifdef _HAL_UART_C_ + +#define GLOBAL +#else +#define GLOBAL extern +#endif + +#undef GLOBAL +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup UART_Exported_Functions +/// @{ +void UART_DeInit(UART_TypeDef* uart); +void UART_Init(UART_TypeDef* uart, UART_InitTypeDef* init_struct); +void UART_StructInit(UART_InitTypeDef* init_struct); +void UART_Cmd(UART_TypeDef* uart, FunctionalState state); +void UART_ITConfig(UART_TypeDef* uart, u16 it, FunctionalState state); +void UART_DMACmd(UART_TypeDef* uart, u16 dma_request, FunctionalState state); +void UART_SendData(UART_TypeDef* uart, u16 Data); +void UART_ClearITPendingBit(UART_TypeDef* uart, u16 it); + +u16 UART_ReceiveData(UART_TypeDef* uart); +FlagStatus UART_GetFlagStatus(UART_TypeDef* uart, u16 flag); + +ITStatus UART_GetITStatus(UART_TypeDef* uart, u16 it); + +void UART_WakeUpConfig(UART_TypeDef* uart, UART_WakeUp_TypeDef mode); +void UART_ReceiverWakeUpCmd(UART_TypeDef* uart, FunctionalState state); +void UART_SetRXAddress(UART_TypeDef* uart, u8 address); +void UART_SetRXMASK(UART_TypeDef* uart, u8 address); +void UART_Enable9bit(UART_TypeDef* uart, FunctionalState state); +void UART_Set9bitLevel(UART_TypeDef* uart, FunctionalState state); +void UART_Set9bitPolarity(UART_TypeDef* uart, UART_9bit_Polarity_TypeDef polarity); +void UART_Set9bitAutomaticToggle(UART_TypeDef* uart, FunctionalState state); +void UART_HalfDuplexCmd(UART_TypeDef* uart, FunctionalState state); +void UART_SetGuardTime(UART_TypeDef* uart, u8 guard_time); +void UART_SmartCardCmd(UART_TypeDef* uart, FunctionalState state); +void UART_SmartCardNACKCmd(UART_TypeDef* uart, FunctionalState state); +void UART_SendBreak(UART_TypeDef* uart); +void UART_AutoBaudRateCmd(UART_TypeDef* uart, FunctionalState state); +void UART_AutoBaudRateSet(UART_TypeDef* uart, UART_AutoBaud_TypeDef value, FunctionalState state); + +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +#endif // __HAL_UART_H +//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_uid.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_uid.h new file mode 100644 index 000000000..2dba789d2 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_uid.h @@ -0,0 +1,71 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_uid.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE UID +/// FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#ifndef __HAL_UID_H +#define __HAL_UID_H + +// Files includes +#include "types.h" +#include "reg_common.h" + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup UID_HAL +/// @brief UID HAL modules +/// @{ + + +/////////////////////////////////////1/////////////////////////////////////////// +/// @defgroup UID_Exported_Variables +/// @{ +#ifdef _HAL_UID_C_ +#define GLOBAL + +#else +#define GLOBAL extern + + +#endif +GLOBAL u8 device_id_data[12]; + +#undef GLOBAL + + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup UID_Exported_Functions +/// @{ +void GetChipUID(void); + +/// @} + + + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +#endif // __HAL_UID_H +//////////////////////////////////////////////////////////////////////////////// + diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_ver.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_ver.h new file mode 100644 index 000000000..773af5631 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_ver.h @@ -0,0 +1,89 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_ver.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE UART +/// FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#ifndef __HAL_VER_H +#define __HAL_VER_H + +// Files includes +#include "reg_common.h" +#include "reg_dbg.h" + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +/////////////////////////////////////1/////////////////////////////////////////// +/// @defgroup UART_HAL +/// @brief UART HAL modules +/// @{ + + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup UART_Exported_Types +/// @{ +/// + +//////////////////////////////////////////////////////////////////////////////// +/// @brief UART Word Length Enumerate definition +/// @anchor UART_Word_Length +//////////////////////////////////////////////////////////////////////////////// + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup UART_Exported_Constants +/// @{ + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup UART_Exported_Variables +/// @{ +#ifdef _HAL_VER_C_ + +#define GLOBAL +#else +#define GLOBAL extern +#endif + +#undef GLOBAL +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup UART_Exported_Functions +/// @{ + +u32 Get_MM32LibVersion(void); +u32 Get_ChipsetREVID(void); +u32 Get_ChipsetDEVID(void); +u32 Get_ChipsetUIDw0(void); +u32 Get_ChipsetUIDw1(void); +u32 Get_ChipsetUIDw2(void); + + + +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +#endif // __HAL_VER_H +//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_wwdg.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_wwdg.h new file mode 100644 index 000000000..287ddd5c8 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_wwdg.h @@ -0,0 +1,90 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_wwdg.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE WWDG +/// FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT O +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDER +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#ifndef __HAL_WWDG_H +#define __HAL_WWDG_H + +// Files includes +#include "types.h" +#include "reg_wwdg.h" + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup WWDG_HAL +/// @brief WWDG HAL modules +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup WWDG_Exported_Types +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @brief WWDG_Prescaler +/// @anchor WWDG_Prescaler + +typedef enum { + WWDG_Prescaler_1 = WWDG_CFGR_WDGTB_1, + WWDG_Prescaler_2 = WWDG_CFGR_WDGTB_2, + WWDG_Prescaler_4 = WWDG_CFGR_WDGTB_4, + WWDG_Prescaler_8 = WWDG_CFGR_WDGTB_8 +} WWDG_Prescaler_Typedef; + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup WWDG_Exported_Variables +/// @{ + +#ifdef _HAL_WWDG_C_ + +#define GLOBAL +#else +#define GLOBAL extern +#endif + +#undef GLOBAL + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup WWDG_Exported_Functions +/// @{ + +void WWDG_DeInit(void); +void WWDG_SetPrescaler(u32 prescaler); +void WWDG_SetWindowValue(u8 window_value); +void WWDG_EnableIT(void); +void WWDG_SetCounter(u8 count); +u32 WWDG_GetCounter(void); +void WWDG_Enable(u8 count); +FlagStatus WWDG_GetFlagStatus(void); +void WWDG_ClearFlag(void); + +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +#endif // __HAL_WWDG_H +//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_adc.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_adc.c new file mode 100644 index 000000000..503e91a67 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_adc.c @@ -0,0 +1,563 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_adc.c +/// @author AE TEAM +/// @brief THIS FILE PROVIDES ALL THE ADC FIRMWARE FUNCTIONS. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#define _HAL_ADC_C_ + +// Files includes +#include "hal_adc.h" +#include "hal_rcc.h" + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup ADC_HAL +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup ADC_Exported_Functions +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Deinitializes the adc peripheral registers to their default +/// reset values. +/// @param adc: select the ADC peripheral. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void ADC_DeInit(ADC_TypeDef* adc) +{ + + switch (*(vu32*)&adc) { + + case ADC1_BASE: + exRCC_APB2PeriphReset(RCC_APB2ENR_ADC1); + break; + case ADC2_BASE: + exRCC_APB2PeriphReset(RCC_APB2ENR_ADC2); + break; + case ADC3_BASE: + exRCC_APB2PeriphReset(RCC_APB2ENR_ADC3); + break; + default: + break; + } +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Initializes the adc peripheral according to the specified parameters +/// in the init_struct, Please use this function if you want to be +/// compatible with older versions of the library. +/// @param adc: select the ADC peripheral. +/// @param init_struct: pointer to an ADC_InitTypeDef structure that contains +/// the configuration information for the specified ADC peripheral. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void ADC_Init(ADC_TypeDef* adc, ADC_InitTypeDef* init_struct) +{ + adc->ADCFG &= ~(ADC_CFGR_PRE | ADC_CFGR_RSLTCTL); + adc->ADCFG |= (u32)(init_struct->ADC_PRESCARE) | init_struct->ADC_Resolution; + + adc->ADCR &= ~(ADC_CR_ALIGN | ADC_CR_MODE | ADC_CR_TRGSEL); + adc->ADCR |= ((u32)init_struct->ADC_DataAlign) | init_struct->ADC_ExternalTrigConv | ((u32)init_struct->ADC_Mode); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Fills each init_struct member with its default value. +/// @param init_struct : pointer to an ADC_InitTypeDef structure which will be +/// initialized. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void ADC_StructInit(ADC_InitTypeDef* init_struct) +{ + init_struct->ADC_Resolution = ADC_Resolution_12b; + init_struct->ADC_PRESCARE = ADC_PCLK2_PRESCARE_2; + init_struct->ADC_Mode = ADC_CR_IMM; //ADC_Mode_Single; + init_struct->ADC_ContinuousConvMode = DISABLE; // useless + init_struct->ADC_ExternalTrigConv = ADC1_ExternalTrigConv_T1_CC1; + init_struct->ADC_DataAlign = ADC_DataAlign_Right; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the specified ADC peripheral. +/// @param adc:select the ADC peripheral. +/// @param state: new state of the adc peripheral. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void ADC_Cmd(ADC_TypeDef* adc, FunctionalState state) +{ + (state) ? (adc->ADCFG |= ADC_CFGR_ADEN) : (adc->ADCFG &= ~ADC_CFGR_ADEN); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the specified ADC DMA request. +/// @param adc: select the ADC peripheral. +/// @param state: New state of the selected ADC DMA transfer. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void ADC_DMACmd(ADC_TypeDef* adc, FunctionalState state) +{ + (state) ? (adc->ADCR |= ADC_CR_DMAEN) : (adc->ADCR &= ~ADC_CR_DMAEN); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the specified ADC interrupts. +/// @param adc: select the ADC peripheral. +/// @param adc_interrupt: specifies the ADC interrupt sources to be enabled or disabled. +/// @param state: New state of the specified ADC interrupts. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void ADC_ITConfig(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_interrupt, FunctionalState state) +{ + if (adc_interrupt == ADC_IT_EOC) + (state) ? (adc->ADCR |= ADC_CR_ADIE) : (adc->ADCR &= ~ADC_CR_ADIE); + else + (state) ? (adc->ADCR |= ADC_CR_ADWIE) : (adc->ADCR &= ~ADC_CR_ADWIE); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the selected ADC software start conversion . +/// @param adc: select the ADC peripheral. +/// @param state: New state of the selected ADC software start conversion. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void ADC_SoftwareStartConvCmd(ADC_TypeDef* adc, FunctionalState state) +{ + (state) ? (adc->ADCR |= ADC_CR_ADST) : (adc->ADCR &= ~ADC_CR_ADST); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Gets the selected ADC Software start conversion Status. +/// @param adc: select the ADC peripheral. +/// @retval The new state of ADC software start conversion (SET or RESET). +//////////////////////////////////////////////////////////////////////////////// +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* adc) +{ + return (((adc->ADCR & ADC_CR_ADST) != (u32)RESET) ? SET : RESET); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enable the selected ADC channel and configure its sample time. Please +/// use this function if you want to be compatible with older versions +/// of the library. +/// @param adc: select the ADC peripheral. +/// @param channel: the ADC channel to configure. +/// @param sample_time: the ADC Channel n Sample time to configure. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void ADC_RegularChannelConfig(ADC_TypeDef* adc, u32 channel, u8 rank, u32 sample_time) //ADCSAM_TypeDef +{ + + u32 tempchan; + sample_time = sample_time & 0xF; + tempchan = channel; + if(tempchan > 8) { + tempchan = tempchan & 0xF; + tempchan = tempchan - 8; + adc->SMPR2 &= ~(0xF << tempchan); + adc->SMPR2 |= (sample_time << tempchan); + } + else { + adc->SMPR1 &= ~(0xF << tempchan); + adc->SMPR1 |= (sample_time << tempchan); + } + adc->ADCHS &= ~(1 << channel); + adc->ADCHS |= (1 << channel); + + if (channel & ADC_CHSR_CHT) + ADC_TempSensorVrefintCmd(ENABLE); + else if (channel & ADC_CHSR_CHV) + ADC_TempSensorVrefintCmd(ENABLE); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the adc conversion through external trigger. +/// @param adc: select the ADC peripheral. +/// @param state: New state of the selected ADC external trigger. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void ADC_ExternalTrigConvCmd(ADC_TypeDef* adc, FunctionalState state) +{ + (state) ? (adc->ADCR |= ADC_CR_TRGEN) : (adc->ADCR &= ~ADC_CR_TRGEN); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the adc external trigger for injected channels conversion. +/// @param adc: select the ADC peripheral. +/// @param adc_external_trig_source: Configuring the external trigger source +/// for the ADC. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void ADC_ExternalTrigConvConfig(ADC_TypeDef* adc, EXTERTRIG_TypeDef adc_external_trig_source) +{ + adc->ADCR &= ~ADC_CR_TRGSEL; + adc->ADCR |= adc_external_trig_source; +} + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Returns the last adc conversion result data for regular channel. +/// @param adc: select the ADC peripheral. +/// @retval The data conversion value. +//////////////////////////////////////////////////////////////////////////////// +u16 ADC_GetConversionValue(ADC_TypeDef* adc) +{ + return (u16)adc->ADDATA; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Returns the last ADC conversion result data in dual mode. +/// @param None +/// @retval The Data conversion value. +//////////////////////////////////////////////////////////////////////////////// +u32 ADC_GetDualModeConversionValue() +{ + return (*(vu32*)ADC1_BASE); +} + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the analog watchdog. +/// @param adc: to select the ADC peripheral. +/// @param state: New state of the selected ADC analog watchdog. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void ADC_AnalogWatchdogCmd(ADC_TypeDef* adc, FunctionalState state) +{ + (state) ? (adc->ADCFG |= ADC_CFGR_ADWEN) : (adc->ADCFG &= ~ADC_CFGR_ADWEN); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the high and low thresholds of the analog watchdog. +/// @param adc: select the ADC peripheral. +/// @param high_threshold: the ADC analog watchdog High threshold value. +/// This parameter must be a 12bit value. +/// @param low_threshold: the ADC analog watchdog Low threshold value. +/// This parameter must be a 12bit value. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* adc, u16 high_threshold, u16 low_threshold) +{ + u32 tempThreshold; + tempThreshold = high_threshold; + adc->ADCMPR = (tempThreshold << 16) | low_threshold; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the analog watchdog guarded single channel +/// @param adc: select the ADC peripheral. +/// @param channel: the ADC channel to configure for the analog watchdog. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* adc, ADCCHANNEL_TypeDef channel) +{ + adc->ADCR &= ~ADC_CR_CMPCH; + adc->ADCR |= (channel << ADC_CR_CMPCH_Pos); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the temperature sensor and Vrefint channel. +/// @param state: New state of the temperature sensor. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void ADC_TempSensorVrefintCmd(FunctionalState state) +{ + (state) ? (ADC1->ADCFG |= (ADC_CFGR_TEN | ADC_CFGR_VEN)) + : (ADC1->ADCFG &= ~(ADC_CFGR_TEN | ADC_CFGR_VEN)); +} + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the temperature sensor . +/// @param state: New state of the temperature sensor. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void ADC_TempSensorCmd(FunctionalState state) +{ + ADC_TempSensorVrefintCmd(state); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the Vrefint channel. +/// @param state: New state of the Vrefint channel. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void ADC_VrefintCmd(FunctionalState state) +{ + ADC_TempSensorVrefintCmd(state); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the temperature sensor and Vrefint channel. +/// @param chs: temperature sensor bit & Vrefint bit. +/// @param state: New state of the temperature sensor. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void exADC_TempSensorVrefintCmd(u32 chs, FunctionalState state) +{ + if (chs & ADC_CHSR_CHT) { + (state) ? (ADC1->ADCFG |= ADC_CFGR_TEN) + : (ADC1->ADCFG &= ~ADC_CFGR_TEN); + } + else if (chs & ADC_CHSR_CHV) { + (state) ? (ADC1->ADCFG |= ADC_CFGR_VEN) + : (ADC1->ADCFG &= ~ADC_CFGR_VEN); + } + +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Checks whether the specified ADC flag is set or not. +/// @param adc: select the ADC peripheral. +/// @param adc_flag: specifies the flag to check. +/// @retval The New state of adc_flag (SET or RESET). +//////////////////////////////////////////////////////////////////////////////// +FlagStatus ADC_GetFlagStatus(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_flag) +{ + return (adc_flag == ADC_IT_EOC) ? ((adc->ADSTA & ADC_SR_ADIF) ? SET : RESET) : ((adc->ADSTA & ADC_SR_ADWIF) ? SET : RESET); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Clears the adc's pending flags. +/// @param adc: select the ADC peripheral. +/// @param adc_flag: specifies the flag to clear. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void ADC_ClearFlag(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_flag) +{ + (adc_flag == ADC_IT_EOC) ? (adc->ADSTA |= ADC_SR_ADIF) : (adc->ADSTA |= ADC_SR_ADWIF); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Checks whether the specified adc's interrupt has occurred or not. +/// @param adc: select the ADC peripheral. +/// @param adc_interrupt: specifies the ADC interrupt source to check. +/// @retval The new state of adc_interrupt (SET or RESET). +//////////////////////////////////////////////////////////////////////////////// +ITStatus ADC_GetITStatus(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_interrupt) +{ + return (adc_interrupt == ADC_IT_EOC) ? ((adc->ADSTA & ADC_SR_ADIF) ? SET : RESET) : ((adc->ADSTA & ADC_SR_ADWIF) ? SET : RESET); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Clears the adc's interrupt pending bits. +/// @param adc: select the ADC peripheral. +/// @param adc_interrupt: specifies the ADC interrupt pending bit to clear. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void ADC_ClearITPendingBit(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_interrupt) +{ + (adc_interrupt == ADC_IT_EOC) ? (adc->ADSTA |= ADC_SR_ADIF) : (adc->ADSTA |= ADC_SR_ADWIF); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the adc any channels conversion rank and channel. +/// @param adc: select the ADC peripheral. +/// @param rank: rank can be 0x0~0xf for the convert sequence. +/// @param adc_channel: Configuring the target channel to be converted. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void ADC_ANY_CH_Config(ADC_TypeDef* adc, u8 rank, ADCCHANNEL_TypeDef adc_channel) +{ + rank = rank & 0xF; + if(rank < 8) { + adc->CHANY0 &= ~(0x0F << (4 * rank)); + adc->CHANY0 |= (adc_channel << (4 * rank)); + } + else { + adc->CHANY1 &= ~(0x0F << (4 * (rank - 8))); + adc->CHANY1 |= (adc_channel << (4 * (rank - 8))); + } +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the adc any channels conversion Max rank number +/// @param adc: select the ADC peripheral. +/// @param num: Configuring the max rank number for the ADC. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void ADC_ANY_NUM_Config(ADC_TypeDef* adc, u8 num) +{ + if(num > 15) num = 15; //15 ? 16 need to be confirmed + adc->ANYCFG = num; +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the ANY channel converter. +/// @param state: enable or disable the ANY channel converter mode. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void ADC_ANY_Cmd(ADC_TypeDef* adc, FunctionalState state) +{ + (state) ? (adc->ANYCR |= ADC1_CHANY_CR_MDEN) : (adc->ANYCR &= ~ADC1_CHANY_CR_MDEN); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the selected ADC automatic injected group +/// conversion after regular one. +/// @param adc: where x can be 1, 2 or 3 to select the ADC peripheral. +/// @param state: new state of the selected ADC auto injected conversion +/// This parameter can be: ENABLE or DISABLE. +/// @retval None +//////////////////////////////////////////////////////////////////////////////// +void ADC_AutoInjectedConvCmd(ADC_TypeDef* adc, FunctionalState state) +{ + (state) ? (adc->ANYCR |= ADC_ANY_CR_JAUTO) : (adc->ANYCR &= ~ADC_ANY_CR_JAUTO); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the adc external trigger for injected channels conversion. +/// @param adc: where x can be 1, 2 or 3 to select the ADC peripheral. +/// @param ADC_ExtInjTrigSource: specifies the ADC trigger to start injected conversion. + +/// @retval None +//////////////////////////////////////////////////////////////////////////////// +void ADC_ExternalTrigInjectedConvertConfig(ADC_TypeDef* adc, EXTER_INJ_TRIG_TypeDef ADC_ExtInjTrigSource) +{ + u32 tmpreg = 0; + // Get the old register value + tmpreg = adc->ANYCR; + // Clear the old external event selection for injected group + tmpreg &= ADC_ANY_CR_JTRGSEL; + // Set the external event selection for injected group + tmpreg |= ADC_ExtInjTrigSource; + // Store the new register value + adc->ANYCR = tmpreg; +} + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the adc injected channels conversion through +/// external trigger +/// @param adc: where x can be 1, 2 or 3 to select the ADC peripheral. +/// @param state: new state of the selected ADC external trigger start of +/// injected conversion. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None +//////////////////////////////////////////////////////////////////////////////// +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* adc, FunctionalState state) +{ + (state) ? (adc->ANYCR |= ADC_ANY_CR_JTRGEN) : (adc->ANYCR &= ~ADC_ANY_CR_JTRGEN); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the selected ADC start of the injected +/// channels conversion. +/// @param adc: where x can be 1, 2 or 3 to select the ADC peripheral. +/// @param state: new state of the selected ADC software start injected conversion. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None +//////////////////////////////////////////////////////////////////////////////// +void ADC_InjectedConvCmd(ADC_TypeDef* adc, FunctionalState state) +{ + (state) ? (adc->ANYCR |= ADC_ANY_CR_JCEN) : (adc->ANYCR &= ~ADC_ANY_CR_JCEN); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the selected ADC start of the injected +/// channels conversion. +/// @param adc: where x can be 1, 2 or 3 to select the ADC peripheral. +/// @param NewState: new state of the selected ADC software start injected conversion. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None +//////////////////////////////////////////////////////////////////////////////// +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* adc, FunctionalState state) +{ + (state) ? (adc->ANYCR |= ADC_ANY_CR_JADST) : (adc->ANYCR &= ~ADC_ANY_CR_JADST); +} + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enable the selected ADC channel and configure its sample time. Please +/// use this function if you want to be compatible with older versions +/// of the library. +/// @param adc: select the ADC peripheral. +/// @param event: the ADC external event to configure. +/// @param sample_time: the ADC Channel n Sample time to configure. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void ADC_InjectedSequencerConfig(ADC_TypeDef* adc, u32 event, u32 sample_time) +{ + adc->ANYCR &= ~(ADC_ANY_CR_JCEN | ADC_ANY_CR_CHANY_MDEN | ADC_ANY_CR_JTRGSEL_EXTI12 \ + | ADC_ANY_CR_JTRGSHIFT_512 | ADC_ANY_CR_JTRGEN); + adc->ANYCR |= (ADC_ANY_CR_JCEN | ADC_ANY_CR_CHANY_MDEN | sample_time | event | ADC_ANY_CR_JTRGEN); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Injection channel length configuration. +/// @param adc: select the ADC peripheral. +/// @param Length: Injection channel length. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* adc, ADC_INJ_SEQ_LEN_TypeDef Length) +{ + adc->JSQR &= ~(0x03 << ADC_JSQR_JL_Pos); + adc->JSQR |= Length << ADC_JSQR_JL_Pos; +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Injection channel configuration. +/// @param adc : select the ADC peripheral. +/// @param off_addr : Injection channel offset address. +/// @param channel: The sampling channel. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void ADC_InjectedSequencerChannelConfig(ADC_TypeDef* adc, ADC_INJ_SEQ_Channel_TypeDef off_addr, ADCCHANNEL_TypeDef channel) +{ + adc->JSQR &= ~(0x1F << (off_addr >> 2) * 5); + adc->JSQR |= (channel << (off_addr >> 2) * 5); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Injection channel converted value. +/// @param adc : select the ADC peripheral. +/// @param off_addr : Injection channel offset address. +/// @retval value. +//////////////////////////////////////////////////////////////////////////////// +u16 ADC_GetInjectedConversionValue(ADC_TypeDef* adc, ADC_INJ_SEQ_Channel_TypeDef off_addr) +{ + u32 value; + value = (*(vu32*)(*(vu32*)&adc + 0xB0 + off_addr)) - (*(vu32*)(*(vu32*)&adc + 0x7C + off_addr)); + + return (u16)value; +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Injection current converted value. +/// @param adc : select the ADC peripheral. +/// @retval value. Returns the last adc conversion result data for injected channel. +//////////////////////////////////////////////////////////////////////////////// +u16 ADC_GetInjectedCurrentConvertedValue(ADC_TypeDef* adc) +{ + return (u16)adc->JDATA; +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Injection channel compensation configuration. +/// @param adc : select the ADC peripheral. +/// @param off_addr : Injection channel. +/// @param value : compensation value. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void ADC_SetInjectedOffset(ADC_TypeDef* adc, ADC_INJ_SEQ_Channel_TypeDef off_addr, u16 value) +{ + *(vu32*)(*(vu32*)&adc + 0x7C + off_addr) = value; +} + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Get channel convertion result. +/// @param adc : select the ADC peripheral. +/// @param channel : Converted channel. +/// @retval The Data conversion value. +//////////////////////////////////////////////////////////////////////////////// +u16 ADC_GetChannelConvertedValue(ADC_TypeDef* adc, ADCCHANNEL_TypeDef channel) +{ + return (u16)(*(vu32*) ((u32)adc + 0x18 + ((u32)channel << 2))); +} + +/// @} + +/// @} + +/// @} + diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_bkp.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_bkp.c new file mode 100644 index 000000000..323971dd3 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_bkp.c @@ -0,0 +1,231 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_bkp.c +/// @author AE TEAM +/// @brief THIS FILE PROVIDES ALL THE BKP FIRMWARE FUNCTIONS. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#define _HAL_BKP_C_ + +// Files includes +#include "types.h" +#include "hal_pwr.h" +#include "hal_rcc.h" +#include "hal_bkp.h" + + + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup BKP_HAL +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup BKP_Exported_Functions +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Deinitializes the BKP peripheral registers to their default reset +/// values. +/// @param None. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void BKP_DeInit(void) +{ + RCC_BackupResetCmd(ENABLE); + RCC_BackupResetCmd(DISABLE); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the Tamper Pin active level. +/// @param tamper_pin_level: specifies the Tamper Pin active level. +/// This parameter can be one of the following values: +/// @arg BKP_TamperPinLevel_High: Tamper pin active on high level +/// @arg BKP_TamperPinLevel_Low: Tamper pin active on low level +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void BKP_TamperPinLevelConfig(BKPTPAL_Typedef tamper_pin_level) +{ + BKP->CR = tamper_pin_level; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the Tamper Pin activation. +/// @param state: new state of the Tamper Pin activation. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void BKP_TamperPinCmd(FunctionalState state) +{ + (state) ? SET_BIT(BKP->CR, BKP_CR_TPE) : CLEAR_BIT(BKP->CR, BKP_CR_TPE); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the Tamper Pin Interrupt. +/// @param state: new state of the Tamper Pin Interrupt. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void BKP_ITConfig(FunctionalState state) +{ + (state) ? SET_BIT(BKP->CSR, BKP_CSR_TPIE) : CLEAR_BIT(BKP->CSR, BKP_CSR_TPIE); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Select the RTC output source to output on the Tamper pin. +/// @param rtc_output_source: specifies the RTC output source. +/// This parameter can be one of the following values: +/// @arg BKP_RTCOutputSource_None: no RTC output on the Tamper pin. +/// @arg BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency +/// divided by 64 on the Tamper pin. +/// @arg BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on +/// the Tamper pin. +/// @arg BKP_RTCOutputSource_Second: output the RTC Second pulse signal on +/// the Tamper pin. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void BKP_RTCOutputConfig(BKPRTCOUTPUTSRC_Typedef rtc_output_source) +{ + MODIFY_REG(BKP->RTCCR, BKP_RTCCR_CCO | BKP_RTCCR_ASOE | BKP_RTCCR_ASOS, rtc_output_source); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Sets RTC Clock Calibration value. +/// @param calibration_value: specifies the RTC Clock Calibration value. +/// This parameter must be a number between 0 and 0x7F. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void BKP_SetRTCCalibrationValue(u8 calibration_value) +{ + MODIFY_REG(BKP->RTCCR, BKP_RTCCR_CAL, calibration_value); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Checks whether the Tamper Pin Event flag is set or not. +/// @param None. +/// @retval State: The new state of the Tamper Pin Event flag (SET or RESET). +//////////////////////////////////////////////////////////////////////////////// +FlagStatus BKP_GetFlagStatus(void) +{ + return ((BKP->CSR & BKP_CSR_TEF) ? SET : RESET); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Clears Tamper Pin Event pending flag. +/// @param None. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void BKP_ClearFlag(void) +{ + SET_BIT(BKP->CSR, BKP_CSR_CTE); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Checks whether the Tamper Pin Interrupt has occurred or not. +/// @param None. +/// @retval State: The new state of the Tamper Pin Interrupt (SET or RESET). +//////////////////////////////////////////////////////////////////////////////// +ITStatus BKP_GetITStatus(void) +{ + return ((BKP->CSR & BKP_CSR_TIF) ? SET : RESET); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Clears Tamper Pin Interrupt pending bit. +/// @param None. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void BKP_ClearITPendingBit(void) +{ + SET_BIT(BKP->CSR, BKP_CSR_CTI); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Writes user data to the specified data Backup Register. +/// @param bkp_dr: specifies the data Backup Register. +/// This parameter can be BKP_DRx where x:[1, 10] +/// @param data: data to write +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void BKP_WriteBackupRegister(BKPDR_Typedef bkp_dr, u16 data) +{ + *(vu16*)(BKP_BASE + bkp_dr) = data; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Reads data from the specified data Backup Register. +/// @param bkp_dr: specifies the data Backup Register. +/// This parameter can be BKP_DRx where x:[1, 10] +/// @retval data: The content of the specified data Backup Register +//////////////////////////////////////////////////////////////////////////////// +u16 BKP_ReadBackupRegister(BKPDR_Typedef bkp_dr) +{ + return (*(vu16*)(BKP_BASE + bkp_dr)); +} +//////////////////////////////////////////////////////////////////////////////// +// Extended function interface +//////////////////////////////////////////////////////////////////////////////// +/// @brief Initializes the BKP peripheral, enable access to the backup +/// registers. +/// @param None. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void exBKP_Init(void) +{ + RCC_APB1PeriphClockCmd(RCC_APB1ENR_PWR, ENABLE); + //COMMON_EnableIpClock(emCLOCK_PWR); + RCC_APB1PeriphClockCmd(RCC_APB1ENR_BKP, ENABLE); + //COMMON_EnableIpClock(emCLOCK_BKP); + + RCC->BDCR |= RCC_BDCR_DBP; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Writes user data to the specified data Backup Register immediately. +/// @param bkp_dr: specifies the data Backup Register. +/// This parameter can be BKP_DRx where x:[1, 10] +/// @param data: data to write +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void exBKP_ImmWrite(BKPDR_Typedef bkp_dr, u16 dat) +{ + RCC->BDCR |= RCC_BDCR_DBP; + *(vu16*)(BKP_BASE + bkp_dr) = dat; + RCC->BDCR &= ~RCC_BDCR_DBP; + +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Reads data from the specified data Backup Register immediately. +/// @param bkp_dr: specifies the data Backup Register. +/// This parameter can be BKP_DRx where x:[1, 10] +/// @retval data: The content of the specified data Backup Register +//////////////////////////////////////////////////////////////////////////////// +u16 exBKP_ImmRead(BKPDR_Typedef bkp_dr) +{ + u16 dat; + RCC->BDCR |= RCC_BDCR_DBP; + dat = (*(vu16*)(BKP_BASE + bkp_dr)); + RCC->BDCR &= ~RCC_BDCR_DBP; + return dat; +} + +/// @} + +/// @} + +/// @} diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_can.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_can.c new file mode 100644 index 000000000..9dd85df29 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_can.c @@ -0,0 +1,696 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_can.c +/// @author AE TEAM +/// @brief THIS FILE PROVIDES ALL THE CAN FIRMWARE FUNCTIONS. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#define __HAL_CAN_C + +// Files includes +#include "hal_can.h" +#include "hal_rcc.h" + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup CAN_HAL +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup CAN_Exported_Functions +/// @{ + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Deinitializes the CAN peripheral registers to their default reset +/// values. +/// @param can: select the CAN peripheral. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void CAN_DeInit(CAN_TypeDef* can) +{ + exRCC_APB1PeriphReset(RCC_APB1ENR_CAN); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Initializes the CAN peripheral according to the specified +/// parameters in the CAN_InitStruct. +/// @param can: select the CAN peripheral. +/// @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that +/// contains the configuration information for the CAN peripheral. +/// @retval Constant indicates initialization succeed which will be +/// CANINITFAILED or CANINITOK. +//////////////////////////////////////////////////////////////////////////////// +u8 CAN_Init(CAN_TypeDef* can, CAN_Basic_InitTypeDef* init_struct) +{ + u8 InitStatus = CANINITFAILED; + + can->BTR0 = ((u32)(init_struct->SJW) << 6) | ((u32)(init_struct->BRP)); + can->BTR1 = ((u32)(init_struct->SAM) << 7) | ((u32)(init_struct->TESG2) << 4) | ((u32)(init_struct->TESG1)); + + if (init_struct->GTS == ENABLE) { + can->CMR |= (u32)CAN_SleepMode; + InitStatus = CANINITFAILED; + } + else { + can->CMR &= ~(u32)CAN_SleepMode; + InitStatus = CANINITOK; + } + + (init_struct->GTS == ENABLE) ? (can->CMR |= (u32)CAN_SleepMode) : (can->CMR &= ~(u32)CAN_SleepMode); + + can->CDR |= + ((init_struct->CBP) << 6) | ((init_struct->RXINTEN) << 5) | ((init_struct->CLOSE_OPEN_CLK) << 3) | (init_struct->CDCLK); + + return InitStatus; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the CAN_Basic reception filter according to the specified +/// parameters in the basic_filter_init_struct. +/// @param basic_filter_init_struct: pointer to a CAN_Basic_FilterInitTypeDef +/// structure that contains the configuration information. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void CAN_FilterInit(CAN_Basic_FilterInitTypeDef* basic_filter_init_struct) +{ + // Filter Mode + CAN1->ACR = basic_filter_init_struct->CAN_FilterId; + CAN1->AMR = basic_filter_init_struct->CAN_FilterMaskId; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Fills each init_struct member with its default value. +/// @param init_struct : pointer to a CAN_Basic_InitTypeDef structure which will be initialized. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void CAN_StructInit(CAN_Basic_InitTypeDef* init_struct) +{ + // Reset CAN_Basic init structure parameters values + + // initialize the BRP member(where can be set with (0..63)) + init_struct->BRP = 0x0; + // initialize the SJW member(where can be set with (0..3)) + init_struct->SJW = 0x0; + // Initialize the TESG1 member(where can be set with (0..15)) + init_struct->TESG1 = 0x0; + // Initialize the TESG2 member(where can be set with(0..7)) + init_struct->TESG2 = 0x0; + // Initialize the SAM member(where can be set (SET or RESET)) + init_struct->SAM = RESET; + // Initialize the GTS member to Sleep Mode(where can be set (ENABLE or + // DISABLE)) + init_struct->GTS = DISABLE; + // Initialize the external pin CLKOUT frequence + init_struct->CDCLK = 0x0; + // Initialize the external clk is open or close + init_struct->CLOSE_OPEN_CLK = 0x0; + // Initialize the TX1 pin work as rx interrupt output + init_struct->RXINTEN = 0x0; + // Initialize the CBP of CDR register + init_struct->CBP = 0x0; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the specified CAN interrupts. +/// @param can: select the CAN peripheral. +/// @param it: specifies the CAN interrupt sources to be enabled or +/// disabled. +/// This parameter can be: CAN_IT_OIE, CAN_IT_EIE, CAN_IT_TIE, +/// CAN_IT_RIE. +/// @param state: new state of the CAN interrupts. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void CAN_ITConfig(CAN_TypeDef* can, u32 it, FunctionalState state) +{ + (state) ? (can->CR |= it) : (can->CR &= ~it); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Initiates and transmits a CAN frame message. +/// @param can:select the CAN peripheral. +/// @param TxMessage: pointer to a structure which contains CAN Id, CAN DLC and +/// CAN data. +/// @retval CANTXOK if the CAN driver transmits the message +//////////////////////////////////////////////////////////////////////////////// +u8 CAN_Transmit(CAN_TypeDef* can, CanBasicTxMsg* basic_transmit_message) +{ + can->TXID0 = (basic_transmit_message->IDH); + can->TXID1 = (basic_transmit_message->IDL << 5) | (basic_transmit_message->RTR << 4) | (basic_transmit_message->DLC); + if ((FunctionalState)(basic_transmit_message->RTR) != ENABLE) { + can->TXDR0 = basic_transmit_message->Data[0]; + can->TXDR1 = basic_transmit_message->Data[1]; + can->TXDR2 = basic_transmit_message->Data[2]; + can->TXDR3 = basic_transmit_message->Data[3]; + can->TXDR4 = basic_transmit_message->Data[4]; + can->TXDR5 = basic_transmit_message->Data[5]; + can->TXDR6 = basic_transmit_message->Data[6]; + can->TXDR7 = basic_transmit_message->Data[7]; + } + + can->CMR = CAN_CMR_TR; + + return (can->SR & 0x01); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Cancels a transmit request. +/// @param can: select the CAN peripheral. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void CAN_CancelTransmit(CAN_TypeDef* can) +{ + // abort transmission + can->CMR = CAN_AT; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Releases the specified receive FIFO. +/// @param can: select the CAN peripheral. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void CAN_FIFORelease(CAN_TypeDef* can) +{ + // Release FIFO + can->CMR |= (u32)CAN_RRB; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Receives a correct CAN frame. +/// @param can: select the CAN peripheral. +/// @param RxMessage: pointer to a structure receive frame which contains CAN +/// Id,CAN DLC, CAN data and FMI number. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void CAN_Receive(CAN_TypeDef* can, CanBasicRxMsg* basic_receive_message) +{ + u16 tempid; + + basic_receive_message->RTR = (u8)((can->RXID1) >> 4) & 0x1; + basic_receive_message->DLC = (u8)((can->RXID1) & 0xf); + tempid = (u16)(((can->RXID1) & 0xe0) >> 5); + tempid |= (u16)(can->RXID0 << 3); + basic_receive_message->ID = tempid; + basic_receive_message->Data[0] = CAN1->RXDR0; + basic_receive_message->Data[1] = CAN1->RXDR1; + basic_receive_message->Data[2] = CAN1->RXDR2; + basic_receive_message->Data[3] = CAN1->RXDR3; + basic_receive_message->Data[4] = CAN1->RXDR4; + basic_receive_message->Data[5] = CAN1->RXDR5; + basic_receive_message->Data[6] = CAN1->RXDR6; + basic_receive_message->Data[7] = CAN1->RXDR7; + CAN_FIFORelease(can); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Select the Sleep mode or not in Basic workmode +/// @param state to go into the Sleep mode or go out +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +u8 CAN_Sleep(CAN_TypeDef* can) +{ + can->CMR |= CAN_SleepMode; + // At this step, sleep mode status + return (u8)((can->CMR & 0x10) == CAN_SleepMode) ? CANSLEEPOK : CANSLEEPFAILED; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Wakes the CAN up. +/// @param can: where x can be 1 to select the CAN peripheral. +/// @retval CANWAKEUPOK if sleep mode left, CANWAKEUPFAILED in an other case. +//////////////////////////////////////////////////////////////////////////////// +u8 CAN_WakeUp(CAN_TypeDef* can) +{ + // Wake up request + can->CMR &= ~CAN_SleepMode; + return (u8)((can->CMR & 0x01) == 0) ? CANWAKEUPOK : CANWAKEUPFAILED; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Checks whether the specified CAN flag is set or not. +/// @param can: select the CAN peripheral. +/// @param flag: specifies the flag to check. +/// This parameter can be one of the following values: +/// @arg CAN_STATUS_RBS: Receive buffer status +/// @arg CAN_STATUS_DOS: Data overflow status +/// @arg CAN_STATUS_TBS: Transmit buffer status +/// @arg CAN_STATUS_TCS: Transmit complete status +/// @arg CAN_STATUS_RS: Receiving status +/// @arg CAN_STATUS_TS: Transmiting status +/// @arg CAN_STATUS_ES: Error status +/// @arg CAN_STATUS_BS: bus status, close or open +/// @retval The new state of CAN_FLAG (SET or RESET). +//////////////////////////////////////////////////////////////////////////////// +FlagStatus CAN_GetFlagStatus(CAN_TypeDef* can, u32 flag) +{ + return (FlagStatus)(((can->SR & flag) == flag) ? SET : RESET); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Checks whether the specified CAN interrupt has occurred or not. +/// @param can: where x can be 1 to select the CAN peripheral. +/// @param it: specifies the CAN interrupt source to check. +/// This parameter can be one of the following values: +/// @arg CAN_IT_RI: Receive FIFO not empty Interrupt +/// @arg CAN_IT_TI: Transmit Interrupt +/// @arg CAN_IT_EI: ERROR Interrupt +/// @arg CAN_IT_DOI: Data voerflow Interrupt +/// @arg CAN_IT_WUI: Wakeup Interrupt +/// @arg CAN_IT_ALL: use it can enble all Interrupt +/// @retval The current state of it (SET or RESET). +//////////////////////////////////////////////////////////////////////////////// +ITStatus CAN_GetITStatus(CAN_TypeDef* can, u32 it) +{ + return (ITStatus)((can->IR & it) != it) ? RESET : SET; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Select the can work as peli mode or basic mode +/// @param can: where x can be 1 or 2 to to select the CAN peripheral. +/// @param CAN_MODE: specifies the work mode:CAN_BASICMode,CAN_PELIMode +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void CAN_Mode_Cmd(CAN_TypeDef* can, u32 mode) +{ + can->CDR |= mode; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Select the Reset mode or not +/// @param can: where x can be 1 or 2 to to select the CAN peripheral. +/// @param state to go into the Reset mode or go out +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void CAN_ResetMode_Cmd(CAN_TypeDef* can, FunctionalState state) +{ + (state == ENABLE) ? (can->CR |= CAN_ResetMode) : (can->CR &= ~CAN_ResetMode); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Clear the data overflow. +/// @param can: where x can be 1 or 2 to to select the CAN peripheral. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void CAN_ClearDataOverflow(CAN_TypeDef* can) +{ + can->CMR |= (u32)CAN_CDO; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Clears the CAN's IT pending. +/// @param can: where x can be 1 or 2 to to select the CAN peripheral. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void CAN_ClearITPendingBit(CAN_TypeDef* can) +{ + u32 temp = 0; + temp = temp; + temp = can->IR; // read this register clear all interrupt +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Select the Sleep mode or not in Peli workmode +/// @param state to go into the Sleep mode or go out +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void CAN_Peli_SleepMode_Cmd(FunctionalState state) +{ + (state == ENABLE) ? (CAN1_PELI->MOD |= CAN_SleepMode) : (CAN1_PELI->MOD &= ~CAN_SleepMode); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Fills each CAN1_PELI_InitStruct member with its default value. +/// @param init_struct : pointer to a CAN_Peli_InitTypeDef structure +/// which will be initialized. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void CAN_Peli_StructInit(CAN_Peli_InitTypeDef* init_struct) +{ + //--------------- Reset CAN_Peli init structure parameters values + //--------------- + init_struct->BRP = 0x0; // initialize the BRP member(where can be set with (0..63)) + init_struct->SJW = 0x0; // initialize the SJW member(where can be set with (0..3)) + init_struct->TESG1 = 0x0; // Initialize the TESG1 member(where can be set with (0..15)) + init_struct->TESG2 = 0x0; // Initialize the TESG2 member(where can be set with(0..7)) + init_struct->SAM = RESET; // Initialize the SAM member(where can be set (SET or RESET)) + init_struct->LOM = DISABLE; // Initialize the LOM member + init_struct->STM = DISABLE; // Initialize the STM member + init_struct->SM = DISABLE; // Initialize the SM member + init_struct->SRR = DISABLE; + init_struct->EWLR = 0x96; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Initializes the CAN_Peli peripheral according to the specified +/// parameters in the init_struct. +/// @param init_struct: pointer to a CAN_Peli_InitTypeDef structure that +/// contains the configuration information for the CAN peripheral in the peli workmode. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void CAN_Peli_Init(CAN_Peli_InitTypeDef* init_struct) +{ + CAN1_PELI->BTR0 = ((u32)init_struct->SJW << 6) | ((u32)init_struct->BRP); + CAN1_PELI->BTR1 = ((u32)init_struct->SAM << 7) | ((u32)init_struct->TESG2 << 4) | ((u32)init_struct->TESG1); + if (init_struct->LOM == ENABLE) + CAN1_PELI->MOD |= (u32)CAN_ListenOnlyMode; + else + CAN1_PELI->MOD &= ~(u32)CAN_ListenOnlyMode; + if (init_struct->STM == ENABLE) + CAN1_PELI->MOD |= (u32)CAN_SeftTestMode; + else + CAN1_PELI->MOD &= ~(u32)CAN_SeftTestMode; + if (init_struct->SM == ENABLE) + CAN1_PELI->MOD |= (u32)CAN_SleepMode; + else + CAN1_PELI->MOD &= ~(u32)CAN_SleepMode; + CAN1_PELI->EWLR = (u32)init_struct->EWLR; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the CAN_Peli reception filter according to the specified +/// parameters in the peli_filter_init_struct. +/// @param peli_filter_init_struct: pointer to a CAN_Peli_FilterInitTypeDef +/// structure that contains the configuration information. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void CAN_Peli_FilterInit(CAN_Peli_FilterInitTypeDef* peli_filter_init_struct) +{ + (peli_filter_init_struct->AFM == CAN_FilterMode_Singal) ? (CAN1_PELI->MOD |= (u32)CAN_FilterMode_Singal) + : (CAN1_PELI->MOD &= (u32)CAN_FilterMode_Double); + + CAN1_PELI->FF = peli_filter_init_struct->CAN_FilterId0; + CAN1_PELI->ID0 = peli_filter_init_struct->CAN_FilterId1; + CAN1_PELI->ID1 = peli_filter_init_struct->CAN_FilterId2; + CAN1_PELI->DATA0 = peli_filter_init_struct->CAN_FilterId3; + + CAN1_PELI->DATA1 = peli_filter_init_struct->CAN_FilterMaskId0; + CAN1_PELI->DATA2 = peli_filter_init_struct->CAN_FilterMaskId1; + CAN1_PELI->DATA3 = peli_filter_init_struct->CAN_FilterMaskId2; + CAN1_PELI->DATA4 = peli_filter_init_struct->CAN_FilterMaskId3; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Fills each peli_filter_init_struct member with its default value. +/// @param peli_filter_init_struct: pointer to a CAN_InitTypeDef structure +/// which ill be initialized. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void CAN_Peli_FilterStructInit(CAN_Peli_FilterInitTypeDef* peli_filter_init_struct) +{ + peli_filter_init_struct->CAN_FilterId0 = 0; + peli_filter_init_struct->CAN_FilterId1 = 0; + peli_filter_init_struct->CAN_FilterId2 = 0; + peli_filter_init_struct->CAN_FilterId3 = 0; + + peli_filter_init_struct->CAN_FilterMaskId0 = 0; + peli_filter_init_struct->CAN_FilterMaskId1 = 0; + peli_filter_init_struct->CAN_FilterMaskId2 = 0; + peli_filter_init_struct->CAN_FilterMaskId3 = 0; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Initiates and transmits a CAN frame message. +/// @param TxMessage: pointer to a structure which contains CAN Id, CAN DLC and +/// CAN data. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void CAN_Peli_Transmit(CanPeliTxMsg* peli_transmit_message) +{ + CAN1_PELI->FF = (peli_transmit_message->FF << 7) | (peli_transmit_message->RTR << 6) | (peli_transmit_message->DLC); + if (((FunctionalState)peli_transmit_message->FF) != ENABLE) { + CAN1_PELI->ID0 = (peli_transmit_message->IDHH); + + CAN1_PELI->ID1 = (peli_transmit_message->IDHL & 0xE0); + if ((FunctionalState)(peli_transmit_message->RTR) != ENABLE) { + CAN1_PELI->DATA0 = peli_transmit_message->Data[0]; + CAN1_PELI->DATA1 = peli_transmit_message->Data[1]; + CAN1_PELI->DATA2 = peli_transmit_message->Data[2]; + CAN1_PELI->DATA3 = peli_transmit_message->Data[3]; + CAN1_PELI->DATA4 = peli_transmit_message->Data[4]; + CAN1_PELI->DATA5 = peli_transmit_message->Data[5]; + CAN1_PELI->DATA6 = peli_transmit_message->Data[6]; + CAN1_PELI->DATA7 = peli_transmit_message->Data[7]; + } + } + else { + CAN1_PELI->ID0 = peli_transmit_message->IDHH; + CAN1_PELI->ID1 = peli_transmit_message->IDHL; + CAN1_PELI->DATA0 = peli_transmit_message->IDLH; + CAN1_PELI->DATA1 = peli_transmit_message->IDLL; + if ((FunctionalState)(peli_transmit_message->RTR) != ENABLE) { + CAN1_PELI->DATA2 = peli_transmit_message->Data[0]; + CAN1_PELI->DATA3 = peli_transmit_message->Data[1]; + CAN1_PELI->DATA4 = peli_transmit_message->Data[2]; + CAN1_PELI->DATA5 = peli_transmit_message->Data[3]; + CAN1_PELI->DATA6 = peli_transmit_message->Data[4]; + CAN1_PELI->DATA7 = peli_transmit_message->Data[5]; + CAN1_PELI->DATA8 = peli_transmit_message->Data[6]; + CAN1_PELI->DATA9 = peli_transmit_message->Data[7]; + } + } + + (CAN1_PELI->MOD & CAN_MOD_STM) ? (CAN1->CMR = CAN_CMR_GTS | CAN_CMR_AT) : (CAN1->CMR = CAN_CMR_TR | CAN_CMR_AT); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Initiates and transmits a CAN frame message. +/// @param TxMessage: pointer to a structure which contains CAN Id, CAN DLC and +/// CAN data. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void CAN_Peli_TransmitRepeat(CanPeliTxMsg* peli_transmit_message) +{ + CAN1_PELI->FF = (peli_transmit_message->FF << 7) | (peli_transmit_message->RTR << 6) | (peli_transmit_message->DLC); + if (((FunctionalState)peli_transmit_message->FF) != ENABLE) { + CAN1_PELI->ID0 = (peli_transmit_message->IDHH); + + CAN1_PELI->ID1 = (peli_transmit_message->IDHL & 0xE0); + if ((FunctionalState)(peli_transmit_message->RTR) != ENABLE) { + CAN1_PELI->DATA0 = peli_transmit_message->Data[0]; + CAN1_PELI->DATA1 = peli_transmit_message->Data[1]; + CAN1_PELI->DATA2 = peli_transmit_message->Data[2]; + CAN1_PELI->DATA3 = peli_transmit_message->Data[3]; + CAN1_PELI->DATA4 = peli_transmit_message->Data[4]; + CAN1_PELI->DATA5 = peli_transmit_message->Data[5]; + CAN1_PELI->DATA6 = peli_transmit_message->Data[6]; + CAN1_PELI->DATA7 = peli_transmit_message->Data[7]; + } + } + else { + CAN1_PELI->ID0 = peli_transmit_message->IDHH; + CAN1_PELI->ID1 = peli_transmit_message->IDHL; + CAN1_PELI->DATA0 = peli_transmit_message->IDLH; + CAN1_PELI->DATA1 = peli_transmit_message->IDLL; + if ((FunctionalState)(peli_transmit_message->RTR) != ENABLE) { + CAN1_PELI->DATA2 = peli_transmit_message->Data[0]; + CAN1_PELI->DATA3 = peli_transmit_message->Data[1]; + CAN1_PELI->DATA4 = peli_transmit_message->Data[2]; + CAN1_PELI->DATA5 = peli_transmit_message->Data[3]; + CAN1_PELI->DATA6 = peli_transmit_message->Data[4]; + CAN1_PELI->DATA7 = peli_transmit_message->Data[5]; + CAN1_PELI->DATA8 = peli_transmit_message->Data[6]; + CAN1_PELI->DATA9 = peli_transmit_message->Data[7]; + } + } + + (CAN1_PELI->MOD & CAN_MOD_STM) ? (CAN1->CMR = CAN_CMR_GTS | CAN_CMR_AT) : (CAN1->CMR = CAN_CMR_TR); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Receives a correct CAN frame. +/// @param RxMessage: pointer to a structure receive frame which contains CAN +/// Id,CAN DLC, CAN data and FMI number. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void CAN_Peli_Receive(CanPeliRxMsg* peli_receive_message) +{ + u32 tempid; + peli_receive_message->FF = (CAN1_PELI->FF) >> 7; + peli_receive_message->RTR = ((CAN1_PELI->FF) >> 6) & 0x1; + peli_receive_message->DLC = (CAN1_PELI->FF) & 0xf; + + if (((FunctionalState)peli_receive_message->FF) != ENABLE) { + tempid = (u32)(CAN1_PELI->ID1 >> 5); + tempid |= (u32)(CAN1_PELI->ID0 << 3); + peli_receive_message->ID = tempid; + peli_receive_message->Data[0] = CAN1_PELI->DATA0; + peli_receive_message->Data[1] = CAN1_PELI->DATA1; + peli_receive_message->Data[2] = CAN1_PELI->DATA2; + peli_receive_message->Data[3] = CAN1_PELI->DATA3; + peli_receive_message->Data[4] = CAN1_PELI->DATA4; + peli_receive_message->Data[5] = CAN1_PELI->DATA5; + peli_receive_message->Data[6] = CAN1_PELI->DATA6; + peli_receive_message->Data[7] = CAN1_PELI->DATA7; + } + else { + tempid = (u32)((CAN1_PELI->DATA1 & 0xf8) >> 3); + tempid |= (u32)(CAN1_PELI->DATA0 << 5); + tempid |= (u32)(CAN1_PELI->ID1 << 13); + tempid |= (u32)(CAN1_PELI->ID0 << 21); + peli_receive_message->ID = tempid; + peli_receive_message->Data[0] = CAN1_PELI->DATA2; + peli_receive_message->Data[1] = CAN1_PELI->DATA3; + peli_receive_message->Data[2] = CAN1_PELI->DATA4; + peli_receive_message->Data[3] = CAN1_PELI->DATA5; + peli_receive_message->Data[4] = CAN1_PELI->DATA6; + peli_receive_message->Data[5] = CAN1_PELI->DATA7; + peli_receive_message->Data[6] = CAN1_PELI->DATA8; + peli_receive_message->Data[7] = CAN1_PELI->DATA9; + } + CAN_FIFORelease(CAN1); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Get available current informatoin in receive FIFO only in Peli +/// workmode. +/// @retval The value in reg RMC +//////////////////////////////////////////////////////////////////////////////// +u32 CAN_Peli_GetRxFIFOInfo(void) +{ + return CAN1_PELI->RMC; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Returns the CAN's last error code (LEC). +/// @retval Error code: +/// - CAN_ERRORCODE_NoErr: No Error +/// - CAN_ERRORCODE_StuffErr: Stuff Error +/// - CAN_ERRORCODE_FormErr: Form Error +/// - CAN_ERRORCODE_ACKErr : Acknowledgment Error +/// - CAN_ERRORCODE_BitRecessiveErr: Bit Recessive Error +/// - CAN_ERRORCODE_BitDominantErr: Bit Dominant Error +/// - CAN_ERRORCODE_CRCErr: CRC Error +/// - CAN_ERRORCODE_SoftwareSetErr: Software Set Error +//////////////////////////////////////////////////////////////////////////////// +u8 CAN_Peli_GetLastErrorCode(void) +{ + // Return the error code + return (u8)CAN1_PELI->ECC; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Returns the CAN Receive Error Counter (REC). +/// @note In case of an error during reception, this counter is incremented +/// by 1 or by 8 depending on the error condition as defined by the CAN +/// standard. After every successful reception, the counter is +/// decremented by 1 or reset to 120 if its value was higher than 128. +/// When the counter value exceeds 127, the CAN controller enters the +/// error passive state. +/// @retval CAN Receive Error Counter. +//////////////////////////////////////////////////////////////////////////////// +u8 CAN_Peli_GetReceiveErrorCounter(void) +{ + // Return the Receive Error Counter + return (u8)(CAN1_PELI->RXERR); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Returns the LSB of the 9-bit can Transmit Error Counter(TEC). +/// @retval LSB of the 8-bit CAN Transmit Error Counter. +//////////////////////////////////////////////////////////////////////////////// +u8 CAN_Peli_GetLSBTransmitErrorCounter(void) +{ + // Return the LSB of the 8-bit CAN Transmit Error Counter(TEC) + return (u8)(CAN1_PELI->TXERR); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the specified CAN interrupts in peli workmode. +/// @param it: specifies the CAN interrupt sources to be enabled or +/// disabled. +/// This parameter can be: +/// @arg CAN_IT_RI: Receive FIFO not empty Interrupt +/// @arg CAN_IT_TI: Transmit Interrupt +/// @arg CAN_IT_EI: ERROR Interrupt +/// @arg CAN_IT_DOI: Data voerflow Interrupt +/// @arg CAN_IT_WUI: Wakeup Interrupt +/// @arg CAN_IT_EPI(only Peli): passive error Interrupt +/// @arg CAN_IT_ALI(only Peli): arbiter lose Interrupt +/// @arg CAN_IT_BEI(only Peli): bus error Interrupt +/// @arg CAN_IT_ALL: use it can enble all Interrupt +/// @param state: new state of the CAN interrupts. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void CAN_Peli_ITConfig(u32 it, FunctionalState state) +{ + (state) ? (CAN1_PELI->IER |= it) : (CAN1_PELI->IER &= ~it); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Checks whether the specified CAN interrupt has occurred or not. +/// @param it: specifies the CAN interrupt source to check. +/// This parameter can be one of the following values: +/// @arg CAN_IT_RI: Receive FIFO not empty Interrupt +/// @arg CAN_IT_TI: Transmit Interrupt +/// @arg CAN_IT_EI: ERROR Interrupt +/// @arg CAN_IT_DOI: Data voerflow Interrupt +/// @arg CAN_IT_WUI: Wakeup Interrupt +/// @arg CAN_IT_EPI(only Peli): passive error Interrupt +/// @arg CAN_IT_ALI(only Peli): arbiter lose Interrupt +/// @arg CAN_IT_BEI(only Peli): bus error Interrupt +/// @arg CAN_IT_ALL: use it can enble all Interrupt +/// @retval The current state of it (SET or RESET). +//////////////////////////////////////////////////////////////////////////////// +ITStatus CAN_Peli_GetITStatus(u32 it) +{ + return (ITStatus)(((CAN1_PELI->IR & it) != it) ? RESET : SET); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Config CAN_Peli_InitTypeDef baud parameter. +/// @param CAN_Peli_InitTypeDef: CAN struct. +/// @param src_clk: CAN module clock. +/// @param baud: specified baud. +/// @retval The current state of it (SET or RESET). +//////////////////////////////////////////////////////////////////////////////// +void CAN_AutoCfg_BaudParam(CAN_Peli_InitTypeDef* init_struct, u32 src_clk, u32 baud) +{ + u32 i, value = baud, record = 1; + u32 remain = 0, sumPrescaler = 0; + while ((baud == 0) || (src_clk == 0)) + ; + sumPrescaler = src_clk / baud; + sumPrescaler = sumPrescaler / 2; + for (i = 25; i > 3; i--) { + remain = sumPrescaler - ((sumPrescaler / i) * i); + if (remain == 0) { + record = i; + break; + } + else { + if (remain < value) { + value = remain; + record = i; + } + } + } + init_struct->SJW = 0; + init_struct->BRP = (sumPrescaler / record) - 1; + init_struct->TESG2 = (record - 3) / 3; + init_struct->TESG1 = (record - 3) - init_struct->TESG2; +} + +/// @} + +/// @} + +/// @} + + + diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_comp.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_comp.c new file mode 100644 index 000000000..b55558263 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_comp.c @@ -0,0 +1,226 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_comp.c +/// @author AE TEAM +/// @brief THIS FILE PROVIDES ALL THE COMP FIRMWARE FUNCTIONS. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

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+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#define _HAL_COMP_C_ + +// Files includes +#include "hal_comp.h" + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup COMP_HAL +/// @{ + + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup COMP_Exported_Functions +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Deinitializes COMP peripheral registers to their default reset +/// values. +/// @param selection: the selected comparator. +/// select the COMP peripheral. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void COMP_DeInit(COMP_Selection_TypeDef selection) +{ + *(vu32*)(COMP_BASE + selection) = 0; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Initializes the COMP peripheral according to the specified +/// @param selection: the selected comparator. +/// select the COMP peripheral. +/// @param init_struct: pointer to an COMP_InitTypeDef structure that +/// contains the configuration information for the specified COMP +/// peripheral. +/// - COMP_InvertingInput specifies the inverting input of COMP +/// - COMP_NonInvertingInput specifies the non inverting input of COMP +/// - COMP_Output connect COMP output to selected timer +/// input (Input capture / Output Compare Reference Clear / Break +/// Input) +/// - COMP_BlankingSrce specifies the blanking source of COMP +/// - COMP_OutputPol select output polarity +/// - COMP_Hysteresis configures COMP hysteresis value +/// - COMP_Mode configures COMP power mode +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void COMP_Init(COMP_Selection_TypeDef selection, COMP_InitTypeDef* init_struct) +{ + *(vu32*)(COMP_BASE + selection) = init_struct->Invert | + init_struct->NonInvert | + init_struct->Output | + init_struct->OutputPol | + init_struct->BlankingSrce | + init_struct->Hysteresis | + init_struct->Mode | + init_struct->OFLT; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Fills each init_struct member with its default value. +/// @param init_struct: pointer to an COMP_InitTypeDef structure which will +/// be initialized. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void COMP_StructInit(COMP_InitTypeDef* init_struct) +{ + + init_struct->Invert = COMP_InvertingInput_IO1; + init_struct->NonInvert = COMP_NonInvertingInput_IO1; + init_struct->Output = COMP_Output_None; + init_struct->BlankingSrce = COMP_BlankingSrce_None; + init_struct->OutputPol = COMP_NonInverted; + init_struct->Hysteresis = COMP_Hysteresis_No; + init_struct->Mode = COMP_Mode_UltraLowPower; + init_struct->OFLT = COMP_Filter_4_Period; ///< to adjust the speed/consumption. +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enable or disable the COMP peripheral. +/// @param selection: the selected comparator. +/// select the COMP peripheral. +/// @param NewState: new state of the COMP peripheral. +/// This parameter can be: ENABLE or DISABLE. +/// When enabled, the comparator compares the non inverting input with +/// the inverting input and the comparison result is available on +/// comparator output. +/// When disabled, the comparator doesn't perform comparison and the +/// output level is low. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void COMP_Cmd(COMP_Selection_TypeDef selection, FunctionalState state) +{ + (state) ? (*(vu32*)(COMP_BASE + selection) |= COMP_CSR_EN) : + (*(vu32*)(COMP_BASE + selection) &= ~COMP_CSR_EN); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Select CRV param. +/// @param crv_select: Select source for CRV. +/// @param crv_level: Set level for CRV. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void COMP_SetCrv(u8 crv_select, u8 crv_level) +{ + u32 temreg = 0; + temreg = COMP->CRV; + temreg &= ~COMP_CRV_MASK; + // Load config to CRV and enable + temreg |= crv_select | crv_level | (1 << 4); + COMP->CRV = temreg; +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Close or Open the SW1 switch. +/// @param selection: the selected comparator. +/// select the COMP peripheral. +/// @param state: new state of the COMP peripheral. +/// This parameter can be: ENABLE or DISABLE. +/// When enabled, the comparator compares the non inverting input with +/// the inverting input and the comparison result is available on +/// comparator output. +/// When disabled, the comparator doesn't perform comparison and the +/// output level is low. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void COMP_SwitchCmd(COMP_Selection_TypeDef selection, FunctionalState state) +{ + (state) ? + (*(vu32*)(COMP_BASE + selection) |= COMP_CSR_COMPSW1) : + (*(vu32*)(COMP_BASE + selection) &= ~COMP_CSR_COMPSW1); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Return the output level (high or low) of the selected comparator. +/// The output level depends on the selected polarity. +/// If the polarity is not inverted: +/// - Comparator output is low when the non-inverting input is at a +/// lower voltage than the inverting input +/// - Comparator output is high when the non-inverting input is at a +/// higher voltage than the inverting input +/// If the polarity is inverted: +/// - Comparator output is high when the non-inverting input is at a +/// lower voltage than the inverting input +/// - Comparator output is low when the non-inverting input is at a +/// higher voltage than the inverting input +/// @param comp: the selected comparator. +/// select the COMP peripheral. +/// @retval The selected comparator output level: low or high. +//////////////////////////////////////////////////////////////////////////////// +u32 COMP_GetOutputLevel(COMP_Selection_TypeDef selection) +{ + return (((*(vu32*)(COMP_BASE + selection) & COMP_CSR_STA) != 0) ? + COMP_OutputLevel_High : + COMP_OutputLevel_Low ); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Lock the selected comparator (COMP1/COMP2) configuration. +/// @param selection: the selected comparator. +/// select the COMP peripheral. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void COMP_LockConfig(COMP_Selection_TypeDef selection) +{ + *(vu32*)(COMP_BASE + selection) |= COMP_CSR_LOCK; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enable or disable the COMP register. +/// @param state: new state of the COMP peripheral. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void exCOMP_CrvCmd(FunctionalState state) +{ + (state) ? (COMP->CRV |= COMP_CRV_EN_ENABLE) : (COMP->CRV &= ~COMP_CRV_EN_ENABLE); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Select comparator external reference voltage. +/// @param selection: the selected external reference voltage. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void exCOMP_SwitchCrv(u32 crv) +{ + COMP->CRV |= crv; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Select comparator external reference voltage source. +/// @param selection: the selected external reference voltage source. +/// This parameter can be: COMP_CRV_SRC_AVDD or COMP_CRV_SRC_VREF. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void exCOMP_CrvSrc(u32 src) +{ + COMP->CRV |= src; +} + + + + + +/// @} + +/// @} + +/// @} diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_crc.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_crc.c new file mode 100644 index 000000000..817698bf5 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_crc.c @@ -0,0 +1,108 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_crc.c +/// @author AE TEAM +/// @brief THIS FILE PROVIDES ALL THE CRC FIRMWARE FUNCTIONS. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

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+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#define _HAL_CRC_C_ + +// Files includes +#include "hal_crc.h" + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup CRC_HAL +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup CRC_Exported_Functions +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Resets the CRC Data register (DR). +/// @param None. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void CRC_ResetDR() +{ + CRC->CR = CRC_CR_RESET; +} +//#pragma optimize(0) +//////////////////////////////////////////////////////////////////////////////// +/// @brief Computes the 32-bit CRC of a given data word(32-bit). +/// @param Data: data word(32-bit) to compute its CRC +/// @retval 32-bit CRC +//////////////////////////////////////////////////////////////////////////////// +u32 CRC_CalcCRC(u32 data) +{ + CRC->DR = data; + return (CRC->DR); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). +/// @param buffer: pointer to the buffer containing the data to be computed +/// @param length: length of the buffer to be computed +/// @retval 32-bit CRC +//////////////////////////////////////////////////////////////////////////////// +u32 CRC_CalcBlockCRC(u32* buffer, u32 length) +{ + u32 i; + for (i = 0; i < length; i++) { + CRC->DR = buffer[i]; + } + return (CRC->DR); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Returns the current CRC value. +/// @param None. +/// @retval 32-bit CRC +//////////////////////////////////////////////////////////////////////////////// +u32 CRC_GetCRC(void) +{ + return (CRC->DR); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Stores a 8-bit data in the Independent Data(ID) register. +/// @param id_value: 8-bit value to be stored in the ID register +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void CRC_SetIDRegister(u8 id_value) +{ + CRC->IDR = id_value; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Returns the 8-bit data stored in the Independent Data(ID) register +/// @param None. +/// @retval 8-bit value of the ID register +//////////////////////////////////////////////////////////////////////////////// +u8 CRC_GetIDRegister() +{ + return (CRC->IDR); +} + +/// @} + +/// @} + +/// @} + + diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_crs.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_crs.c new file mode 100644 index 000000000..10b26d353 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_crs.c @@ -0,0 +1,43 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_crs.c +/// @author AE TEAM +/// @brief THIS FILE PROVIDES ALL THE CRS FIRMWARE FUNCTIONS. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

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+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#define _HAL_CRS_C_ + +// Files includes +#include "hal_rcc.h" +#include "hal_crs.h" + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup CRS_HAL +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup CRS_Exported_Functions +/// @{ + +/// @} + +/// @} + +/// @} + + diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dac.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dac.c new file mode 100644 index 000000000..b3583f155 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dac.c @@ -0,0 +1,184 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_dac.c +/// @author AE TEAM +/// @brief THIS FILE PROVIDES ALL THE DAC FIRMWARE FUNCTIONS. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#define _HAL_DAC_C_ + +// Files includes +#include "hal_dac.h" +#include "hal_rcc.h" + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup DAC_HAL +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup DAC_Exported_Functions +/// @{ + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Deinitializes the DAC peripheral registers to their default reset values. +/// @param None. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void DAC_DeInit(void) +{ + exRCC_APB1PeriphReset(RCC_APB1ENR_DAC); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Initializes the DAC peripheral according to the specified parameters in the DAC_InitStruct. +/// @param channel: the selected DAC channel. +/// @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that contains the configuration information for the specified +/// DAC channel. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void DAC_Init(emDACCH_TypeDef channel, DAC_InitTypeDef* init_struct) +{ + DAC->CR &= ~((DAC_CR_BOFF1 | DAC_CR_TEN1 | DAC_CR_TSEL1 | DAC_CR_WAVE1 | DAC_CR_MAMP1) << channel); + DAC->CR |= (((u32)(init_struct->DAC_Trigger) | (u32)(init_struct->DAC_WaveGeneration) | + (u32)(init_struct->DAC_LFSRUnmask_TriangleAmplitude) | (u32)(init_struct->DAC_OutputBuffer)) + << channel); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Fills each DAC_InitStruct member with its default value. +/// @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will be initialized. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void DAC_StructInit(DAC_InitTypeDef* init_struct) +{ + init_struct->DAC_Trigger = DAC_Trigger_None; + init_struct->DAC_WaveGeneration = DAC_WaveGeneration_None; + init_struct->DAC_LFSRUnmask_TriangleAmplitude = DAC_TriangleAmplitude_1; + init_struct->DAC_OutputBuffer = DAC_OutputBuffer_Enable; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the specified DAC channel. +/// @param channel: the selected DAC channel. +/// @param state: new state of the DAC channel. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void DAC_Cmd(emDACCH_TypeDef channel, FunctionalState state) +{ + (state) ? (DAC->CR |= DAC_CR_EN1 << channel) : (DAC->CR &= ~(DAC_CR_EN1 << channel)); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the specified DAC channel DMA request. +/// @param channel: the selected DAC channel. +/// @param state: new state of the selected DAC channel DMA request. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void DAC_DMACmd(emDACCH_TypeDef channel, FunctionalState state) +{ + (state) ? (DAC->CR |= DAC_CR_DMAEN1 << channel) : (DAC->CR &= ~(DAC_CR_DMAEN1 << channel)); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the selected DAC channel software trigger. +/// @param channel: the selected DAC channel. +/// @param state: new state of the selected DAC channel software trigger. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void DAC_SoftwareTriggerCmd(emDACCH_TypeDef channel, FunctionalState state) +{ + (state) ? (DAC->SWTRIGR |= (DAC_SWTRIGR_SWTRIG1 << (channel >> 4))) + : (DAC->SWTRIGR &= ~(DAC_SWTRIGR_SWTRIG1 << (channel >> 4))); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables simultaneously the two DAC channels software triggers. +/// @param state: new state of the DAC channels software triggers. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void DAC_DualSoftwareTriggerCmd(FunctionalState state) +{ + (state) ? (DAC->SWTRIGR |= (DAC_SWTRIGR_SWTRIG1 | DAC_SWTRIGR_SWTRIG2)) + : (DAC->SWTRIGR &= ~(DAC_SWTRIGR_SWTRIG1 | DAC_SWTRIGR_SWTRIG2)); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the selected DAC channel wave generation. +/// @param channel: the selected DAC channel. +/// @param wave: Specifies the wave type to enable or disable. +/// @param state: new state of the selected DAC channel wave generation. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void DAC_WaveGenerationCmd(emDACCH_TypeDef channel, emDACWAVE_TypeDef wave, FunctionalState state) +{ + (state) ? (DAC->CR |= wave << channel) : (DAC->CR &= ~(wave << channel)); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Set the specified data holding register value for DAC channel1. +/// @param alignement: Specifies the data alignement for DAC channel1. +/// @param data : data to be loaded in the selected data holding register. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void DAC_SetChannel1Data(emDACALIGN_TypeDef alignement, u16 data) +{ + *((u32*)(DAC_BASE + DHR12R1_Offset + alignement)) = data; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Set the specified data holding register value for DAC channel2. +/// @param alignement: Specifies the data alignement for DAC channel2. +/// @param data : data to be loaded in the selected data holding +/// register. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void DAC_SetChannel2Data(emDACALIGN_TypeDef alignement, u16 data) +{ + *((u32*)(DAC_BASE + DHR12R2_Offset + alignement)) = data; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Set the specified data holding register value for dual channel DAC. +/// @param alignement: Specifies the data alignement for dual channel DAC. +/// @param data2: data for DAC Channel2 to be loaded in the selected data holding register. +/// @param data1: data for DAC Channel1 to be loaded in the selected data holding register. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void DAC_SetDualChannelData(emDACALIGN_TypeDef alignement, u16 data2, u16 data1) +{ + u32 data = ((alignement == DAC_Align_8b_R) ? ((data2 << 8) | data1) : ((data2 << 16) | data1)); + *((u32*)(DAC_BASE + DHR12RD_Offset + alignement)) = data; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Returns the last data output value of the selected DAC cahnnel. +/// @param channel: the selected DAC channel. +/// @retval The selected DAC channel data output value. +//////////////////////////////////////////////////////////////////////////////// +u16 DAC_GetDataOutputValue(emDACCH_TypeDef channel) +{ + return (*(vu32*)(DAC_BASE + DOR_Offset + (channel >> 2))); +} +/// @} + +/// @} + +/// @} + + diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dbg.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dbg.c new file mode 100644 index 000000000..b51d13214 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dbg.c @@ -0,0 +1,53 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_dbg.c +/// @author AE TEAM +/// @brief THIS FILE PROVIDES ALL THE DBG FIRMWARE FUNCTIONS. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#define _HAL_DBG_C + +// Files includes +#include "types.h" +#include "hal_dbg.h" + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup DBG_HAL +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup DBG_Exported_Functions +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the specified DBG peripheral. +/// @param periph: DBG peripheral. +/// @param state: new state of the specified DBG peripheral. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void DBGMCU_Configure(u32 periph, FunctionalState state) +{ + (state) ? (DBGMCU->CR |= periph) : (DBGMCU->CR &= ~periph); +} + +/// @} + +/// @} + +/// @} diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dma.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dma.c new file mode 100644 index 000000000..5ec0dc95a --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dma.c @@ -0,0 +1,319 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_dma.c +/// @author AE TEAM +/// @brief THIS FILE PROVIDES ALL THE DMA FIRMWARE FUNCTIONS. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + + + + + + +// Define to prevent recursive inclusion +#define _HAL_DMA_C_ + +// Files includes +#include "types.h" +#include "hal_dma.h" + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup DMA_HAL +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup DMA_Exported_Functions +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Deinitializes the DMA Channeln registers to their default reset +/// values. +/// @param select the DMA Channel. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void DMA_DeInit(DMA_Channel_TypeDef* channel) +{ + channel->CCR &= ~DMA_CCR_EN; + channel->CCR = 0; + channel->CNDTR = 0; + channel->CPAR = 0; + channel->CMAR = 0; + if((*(vu32*)&channel) >= (*(vu32*)DMA2_Channel1_BASE)) { + DMA2->IFCR |= (u32)0x0F << (((*(vu32*)&channel & (u32)0xff) - 8) / 5); + } + else { + DMA1->IFCR |= (u32)0x0F << (((*(vu32*)&channel & (u32)0xff) - 8) / 5); + } +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Initializes the DMA Channeln according to the specified +/// parameters in the init_struct. +/// @param select the DMA Channel. +/// @param init_struct: pointer to a DMA_InitTypeDef structure that +/// contains the configuration information for the specified DMA +/// Channel. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void DMA_Init(DMA_Channel_TypeDef* channel, DMA_InitTypeDef* init_struct) +{ + MODIFY_REG( + channel->CCR, + (DMA_CCR_DIR | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL | DMA_CCR_M2M), + ((u32)init_struct->DMA_DIR | (u32)init_struct->DMA_Mode | (u32)init_struct->DMA_PeripheralInc | + (u32)init_struct->DMA_MemoryInc | (u32)init_struct->DMA_PeripheralDataSize | (u32)init_struct->DMA_MemoryDataSize | + (u32)init_struct->DMA_Priority | (u32)init_struct->DMA_M2M)); + + MODIFY_REG(channel->CCR, DMA_CCR_ARE, init_struct->DMA_Auto_reload); + channel->CNDTR = init_struct->DMA_BufferSize; + channel->CPAR = init_struct->DMA_PeripheralBaseAddr; + channel->CMAR = init_struct->DMA_MemoryBaseAddr; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Fills each init_struct member with its default value. +/// @param init_struct : pointer to a DMA_InitTypeDef structure which will +/// be initialized. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void DMA_StructInit(DMA_InitTypeDef* init_struct) +{ + init_struct->DMA_PeripheralBaseAddr = 0; + init_struct->DMA_MemoryBaseAddr = 0; + init_struct->DMA_DIR = DMA_DIR_PeripheralSRC; + init_struct->DMA_BufferSize = 0; + init_struct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; + init_struct->DMA_MemoryInc = DMA_MemoryInc_Disable; + init_struct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + init_struct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + init_struct->DMA_Mode = DMA_Mode_Normal; + init_struct->DMA_Priority = DMA_Priority_Low; + init_struct->DMA_M2M = DMA_M2M_Disable; + + init_struct->DMA_Auto_reload = DMA_Auto_Reload_Disable; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the specified DMA Channeln. +/// @param channel: select the DMA Channel. +/// @param state: new state of the DMA Channeln. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void DMA_Cmd(DMA_Channel_TypeDef* channel, FunctionalState state) +{ + MODIFY_REG(channel->CCR, DMA_CCR_EN, state << DMA_CCR_EN_Pos); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the specified DMA Channeln interrupts. +/// @param channel: select the DMA Channel. +/// @param it: specifies the DMA interrupts sources to be enabled +/// or disabled. +/// This parameter can be any combination of the following values: +/// @arg DMA_IT_TC: Transfer complete interrupt mask +/// @arg DMA_IT_HT: Half transfer interrupt mask +/// @arg DMA_IT_TE: Transfer error interrupt mask +/// @param state: new state of the specified DMA interrupts. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void DMA_ITConfig(DMA_Channel_TypeDef* channel, DMA_Interrupt_EN_TypeDef it, FunctionalState state) +{ + (state) ? (channel->CCR |= it) : (channel->CCR &= ~it); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Sets the number of data units in the select the DMA Channel . +/// @param channel: select the DMA Channel +/// @param DataNumber: The number of data units in the current DMAy Channelx +/// transfer. +/// @note This function can only be used when the DMAy_Channelx is disabled. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* channel, u16 length) +{ + channel->CNDTR = length; +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Returns the number of remaining data units in the current +/// DMA Channeln transfer. +/// @param channel: select the DMA Channel. +/// @retval The number of remaining data units in the current DMA Channeln +/// transfer. +//////////////////////////////////////////////////////////////////////////////// +u16 DMA_GetCurrDataCounter(DMA_Channel_TypeDef* channel) +{ + return channel->CNDTR; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Checks whether the specified DMA Channeln flag is set or not. +/// @param flag: specifies the flag to check. +/// This parameter can be one of the following values: +/// @arg DMA1_FLAG_GLn: DMA1 Channeln global flag(n = 1..7). +/// @arg DMA1_FLAG_TCn: DMA1 Channeln transfer complete flag(n = 1..7). +/// @arg DMA1_FLAG_HTn: DMA1 Channeln half transfer flag(n = 1..7). +/// @arg DMA1_FLAG_TEn: DMA1 Channeln transfer error flag(n = 1..7). +/// @arg DMA2_FLAG_GLn: DMA1 Channeln global flag(n = 1..5). +/// @arg DMA2_FLAG_TCn: DMA1 Channeln transfer complete flag(n = 1..5). +/// @arg DMA2_FLAG_HTn: DMA1 Channeln half transfer flag(n = 1..5). +/// @arg DMA2_FLAG_TEn: DMA1 Channeln transfer error flag(n = 1..5). +/// @retval The new state of DMAy_FLAG (SET or RESET). +//////////////////////////////////////////////////////////////////////////////// +FlagStatus DMA_GetFlagStatus(DMA_Flags_TypeDef flag) +{ + if(flag >= DMA2_FLAG_GL1 ) { + return (DMA2->ISR & flag) ? SET : RESET; + } + return (DMA1->ISR & flag) ? SET : RESET; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Clears the DMA Channeln's pending flags. +/// @param flag: specifies the flag to clear. +/// This parameter can be any combination (for the same DMA) of the +/// following values: +/// @arg DMA1_FLAG_GLn: DMA1 Channeln global flag(n = 1..7). +/// @arg DMA1_FLAG_TCn: DMA1 Channeln transfer complete flag(n = 1..7). +/// @arg DMA1_FLAG_HTn: DMA1 Channeln half transfer flag(n = 1..7). +/// @arg DMA1_FLAG_TEn: DMA1 Channeln transfer error flag(n = 1..7). +/// @arg DMA2_FLAG_GLn: DMA1 Channeln global flag(n = 1..5). +/// @arg DMA2_FLAG_TCn: DMA1 Channeln transfer complete flag(n = 1..5). +/// @arg DMA2_FLAG_HTn: DMA1 Channeln half transfer flag(n = 1..5). +/// @arg DMA2_FLAG_TEn: DMA1 Channeln transfer error flag(n = 1..5). +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void DMA_ClearFlag(DMA_Flags_TypeDef flag) +{ + if(flag >= DMA2_FLAG_GL1 ) { + DMA2->IFCR = flag; + return ; + } + DMA1->IFCR = flag; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Checks whether the specified DMA Channeln interrupt has occurred or +/// not. +/// @param it: specifies the DMA interrupt source to check. +/// This parameter can be one of the following values: +/// @arg DMA1_IT_GLn: DMA1 Channeln global interrupt(n = 1..7). +/// @arg DMA1_IT_TCn: DMA1 Channeln transfer complete interrupt(n = 1..7). +/// @arg DMA1_IT_HTn: DMA1 Channeln half transfer interrupt(n = 1..7). +/// @arg DMA1_IT_TEn: DMA1 Channeln transfer error interrupt(n = 1..7). +/// @arg DMA2_IT_GLn: DMA1 Channeln global flag(n = 1..5). +/// @arg DMA2_IT_TCn: DMA1 Channeln transfer complete flag(n = 1..5). +/// @arg DMA2_IT_HTn: DMA1 Channeln half transfer flag(n = 1..5). +/// @arg DMA2_IT_TEn: DMA1 Channeln transfer error flag(n = 1..5). +/// @retval The new state of DMAy_IT (SET or RESET). +//////////////////////////////////////////////////////////////////////////////// +ITStatus DMA_GetITStatus(DMA_Interrupts_TypeDef it) +{ + if(it >= DMA2_IT_GL1 ) { + return (DMA2->ISR & it) ? SET : RESET; + } + return (DMA1->ISR & it) ? SET : RESET; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Clears the DMA Channeln's interrupt pending bits. +/// @param it: specifies the DMA interrupt pending bit to clear. +/// This parameter can be any combination (for the same DMA) of the +/// following values: +/// @arg DMA1_IT_GLn: DMA1 Channeln global interrupt(n = 1..7). +/// @arg DMA1_IT_TCn: DMA1 Channeln transfer complete interrupt(n = 1..7). +/// @arg DMA1_IT_HTn: DMA1 Channeln half transfer interrupt(n = 1..7). +/// @arg DMA1_IT_TEn: DMA1 Channeln transfer error interrupt(n = 1..7). +/// @arg DMA2_IT_GLn: DMA1 Channeln global flag(n = 1..5). +/// @arg DMA2_IT_TCn: DMA1 Channeln transfer complete flag(n = 1..5). +/// @arg DMA2_IT_HTn: DMA1 Channeln half transfer flag(n = 1..5). +/// @arg DMA2_IT_TEn: DMA1 Channeln transfer error flag(n = 1..5). +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void DMA_ClearITPendingBit(DMA_Interrupts_TypeDef it) +{ + if(it >= DMA2_IT_GL1 ) { + DMA2->IFCR = it; + return ; + } + DMA1->IFCR = it; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Set the DMA Channeln's Peripheral address. +/// @param channel : where n can be 1 to 7 for DMA1 to select the DMA Channel. +/// @param address : DMA Peripheral address. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void exDMA_SetPeripheralAddress(DMA_Channel_TypeDef* channel, u32 address) +{ + channel->CPAR = address; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Set the DMA Channeln's Peripheral address. +/// @param channel : select the DMA Channel. +/// @param length : Transmit lengths. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void exDMA_SetTransmitLen(DMA_Channel_TypeDef* channel, u16 length) +{ + channel->CNDTR = length; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Set the DMA Channeln's Peripheral address. +/// @param channel :select the DMA Channel. +/// @param address : DMA memery address. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void exDMA_SetMemoryAddress(DMA_Channel_TypeDef* channel, u32 address) +{ + channel->CMAR = address; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Clears the DMA Channeln's interrupt pending bits. +/// @param it: specifies the DMA interrupt pending bit to clear. +/// This parameter can be any combination (for the same DMA) of the +/// following values: +/// @arg DMA1_IT_GLn: DMA1 Channeln global interrupt(n = 1..7). +/// @arg DMA1_IT_TCn: DMA1 Channeln transfer complete interrupt(n = 1..7). +/// @arg DMA1_IT_HTn: DMA1 Channeln half transfer interrupt(n = 1..7). +/// @arg DMA1_IT_TEn: DMA1 Channeln transfer error interrupt(n = 1..7). +/// @arg DMA2_IT_GLn: DMA1 Channeln global flag(n = 1..5). +/// @arg DMA2_IT_TCn: DMA1 Channeln transfer complete flag(n = 1..5). +/// @arg DMA2_IT_HTn: DMA1 Channeln half transfer flag(n = 1..5). +/// @arg DMA2_IT_TEn: DMA1 Channeln transfer error flag(n = 1..5). +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void exDMA_ClearITPendingBit(DMA_Channel_TypeDef* channel, u32 it) +{ + if(it >= DMA2_IT_GL1 ) { + DMA2->IFCR |= (u32)0x0F << (((*(vu32*)&channel & (u32)0xff) - 8) / 5); + DMA2->IFCR = it; + return ; + } + DMA1->IFCR |= (u32)0x0F << (((*(vu32*)&channel & (u32)0xff) - 8) / 5); + DMA1->IFCR = it; +} +/// @} + +/// @} + +/// @} diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_eth.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_eth.c new file mode 100644 index 000000000..ca662e978 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_eth.c @@ -0,0 +1,836 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_eth.c +/// @author AE TEM +/// @brief THIS FILE PROVIDES ALL THE HAL_eth.c EXAMPLE. +/// //////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +#define _HAL_ETH_C_ +#include "hal_rcc.h" +#include "hal_eth.h" +#include "reg_eth.h" + + +void ETH_DeInit(void) +{ + RCC_AHBPeriphResetCmd(RCC_AHBENR_ETHMAC, ENABLE); + RCC_AHBPeriphResetCmd(RCC_AHBENR_ETHMAC, DISABLE); +} + +void ETH_StructInit(ETH_InitTypeDef* ptr) +{ + ptr->ETH_AutoNegotiation = ETH_AutoNegotiation_Enable; ///< PHY Auto-negotiation enabled + ptr->ETH_Watchdog = ETH_Watchdog_Enable; ///< MAC watchdog enabled: cuts off long frame + ptr->ETH_Jabber = ETH_Jabber_Enable; ///< MAC Jabber enabled in Half-duplex mode + ptr->ETH_InterFrameGap = ETH_InterFrameGap_96Bit; ///< Ethernet interframe gap set to 96 bits + ptr->ETH_CarrierSense = ETH_CarrierSense_Enable; ///< Carrier Sense Enabled in Half-Duplex mode + ptr->ETH_Speed = ETH_Speed_100M; ///< PHY speed configured to 100Mbit/s + ptr->ETH_ReceiveOwn = ETH_ReceiveOwn_Enable; ///< Receive own Frames in Half-Duplex mode enabled + ptr->ETH_LoopbackMode = ETH_LoopbackMode_Disable; ///< MAC MII loopback disabled + ptr->ETH_Mode = ETH_Mode_FullDuplex; ///< Full-Duplex mode selected + ptr->ETH_ChecksumOffload = ETH_ChecksumOffload_Disable; ///< IPv4 and TCP/UDP/ICMP frame Checksum Offload disabled + ptr->ETH_RetryTransmission = ETH_RetryTransmission_Enable; ///< Retry Transmission enabled for half-duplex mode + ptr->ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable; ///< Automatic PAD/CRC strip disable + ptr->ETH_BackOffLimit = ETH_BackOffLimit_10; ///< half-duplex mode retransmission Backoff time_limit = 10 slot time + ptr->ETH_DeferralCheck = ETH_DeferralCheck_Disable; ///< half-duplex mode Deferral check disabled + ptr->ETH_ReceiveAll = ETH_ReceiveAll_Disable; ///< Receive all frames disabled + ptr->ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable; ///< Source address filtering (on the optional MAC addresses) disabled + ptr->ETH_PassControlFrames = ETH_PassControlFrames_BlockAll; ///< Do not forward control frames that do not pass the address filtering + ptr->ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable; ///< Disable reception of Broadcast frames + ptr->ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal; ///< Normal Destination address filtering (not reverse addressing) + ptr->ETH_PromiscuousMode = ETH_PromiscuousMode_Disable; ///< Promiscuous address filtering mode disabled + ptr->ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect; ///< Perfect address filtering for multicast addresses + ptr->ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect; ///< Perfect address filtering for unicast addresses + ptr->ETH_HashTableHigh = 0x0; ///< Initialize hash table high and low regs + ptr->ETH_HashTableLow = 0x0; + ptr->ETH_PauseTime = 0x0; ///< Flow control config (flow control disabled) + ptr->ETH_ZeroQuantaPause = ETH_ZeroQuantaPause_Enable; + ptr->ETH_PauseLowThreshold = ETH_PauseLowThreshold_Minus4; + ptr->ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable; + ptr->ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable; + ptr->ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable; + ptr->ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit; ///< VLANtag config (VLAN field not checked) + ptr->ETH_VLANTagIdentifier = 0x0; + + ptr->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable; ///< Drops frames with with TCP/IP checksum errors + ptr->ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable; ///< Store and forward mode enabled for receive + ptr->ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Enable; ///< Flush received frame that created FIFO overflow + ptr->ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable; ///< Store and forward mode enabled for transmit + ptr->ETH_TransmitThresholdControl = ETH_ReceiveThresholdControl_64Bytes; ///< Threshold TXFIFO level set to 64 bytes (used when threshold mode is enabled) + ptr->ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable; ///< Disable forwarding frames with errors (short frames, CRC,...) + ptr->ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable; ///< Disable undersized good frames + ptr->ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes; ///< Threshold RXFIFO level set to 64 bytes (used when Cut through mode is enabled) + ptr->ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable; ///< Disable Operate on second frame (transmit a second frame to FIFO without waiting status of previous frame + ptr->ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable; ///< DMA works on 32-bit aligned start source and destinations addresses + ptr->ETH_FixedBurst = ETH_FixedBurst_Enable; ///< Enabled Fixed Burst Mode (mix of INC4, INC8, INC16 and SINGLE DMA transactions + ptr->ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat; ///< DMA transfer max burst length = 32 beats = 32 x 32bits + ptr->ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat; + ptr->ETH_DescriptorSkipLength = 0x0; ///< DMA Ring mode skip length = 0 + ptr->ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_1_1; ///< Equal priority (round-robin) between transmit and receive DMA engines +} + +u32 ETH_Init(ETH_InitTypeDef* ptr, u16 phy_addr) +{ + u32 hclk = RCC_GetHCLKFreq(); + u32 reg = ETH->MACMIIAR & MACMIIAR_CR_MASK; + u32 temp_val = 0; + hclk = 100000000; + //////////////////////////////////////////////////////////////////////////// + if (hclk >= 20000000 && hclk < 35000000) { + reg |= ETH_MACMIIAR_CR_Div16; ///< HCLK 20 ~ 35 MHz, /16 + } + else if (hclk >= 35000000 && hclk < 60000000) { + reg |= ETH_MACMIIAR_CR_Div26; ///< HCLK 35 ~ 60 MHz, /26 + } + else if (hclk >= 60000000 && hclk < 100000000) { + reg |= ETH_MACMIIAR_CR_Div42; ///< HCLK 60 ~ 100 MHz, /42 + } + else if (hclk >= 100000000 && hclk < 150000000) { + reg |= ETH_MACMIIAR_CR_Div62; ///< HCLK 100 ~ 150 MHz, /62 + } + else { + reg |= ETH_MACMIIAR_CR_Div102; ///< HCLK 150 ~ 168 MHz, /102 + } + + ETH->MACMIIAR = reg; + + //////////////////////////////////////////////////////////////////////////// + ETH_WritePHYRegister(phy_addr, PHY_BCR, PHY_Reset); + if (ptr->ETH_AutoNegotiation != ETH_AutoNegotiation_Disable) { + // Wait for linked status + while (!(ETH_ReadPHYRegister(phy_addr, PHY_BSR) & PHY_Linked_Status)); + ETH_WritePHYRegister(phy_addr, PHY_BCR, PHY_AutoNegotiation); + // Enable Auto-Negitation + while (!(ETH_ReadPHYRegister(phy_addr, PHY_BSR) & PHY_AutoNego_Complete)) { + + } + // Read the result of the Auto-Negitation + temp_val = ETH_ReadPHYRegister(phy_addr, 31); + + if ((temp_val & 0x1C) == 0x4) { + ptr->ETH_Speed = ETH_Speed_10M; + ptr->ETH_Mode = ETH_Mode_HalfDuplex; + SYSCFG->CFGR2 &= ~(1 << 21); + } + else if((temp_val & 0x1C) == 0x14) { + ptr->ETH_Speed = ETH_Speed_10M; + ptr->ETH_Mode = ETH_Mode_FullDuplex; + SYSCFG->CFGR2 |= 1 << 21; + } + else if((temp_val & 0x1C) == 0x8) { + ptr->ETH_Speed = ETH_Speed_100M; + ptr->ETH_Mode = ETH_Mode_HalfDuplex; + SYSCFG->CFGR2 &= ~(1 << 21); + } + else if((temp_val & 0x1C) == 0x18) { + ptr->ETH_Speed = ETH_Speed_100M; + ptr->ETH_Mode = ETH_Mode_FullDuplex; + SYSCFG->CFGR2 |= 1 << 21; + } + } + else { + ETH_WritePHYRegister(phy_addr, PHY_BCR, ((u16)(ptr->ETH_Mode >> 3) | + (u16)(ptr->ETH_Speed >> 1))); + if(ptr->ETH_Speed == ETH_Speed_10M) { + SYSCFG->CFGR2 &= ~(1 << 21); + } + else { + SYSCFG->CFGR2 |= 1 << 21; + } + } + + //////////////////////////////////////////////////////////////////////////// + ETH->MACCR = ETH->MACCR & MACCR_CLEAR_MASK | (ptr->ETH_Watchdog | + ptr->ETH_Jabber | + ptr->ETH_InterFrameGap | + ptr->ETH_CarrierSense | + ptr->ETH_Speed | + ptr->ETH_ReceiveOwn | + ptr->ETH_LoopbackMode | + ptr->ETH_Mode | + ptr->ETH_ChecksumOffload | + ptr->ETH_RetryTransmission | + ptr->ETH_AutomaticPadCRCStrip | + ptr->ETH_DeferralCheck); + + ETH->MACFFR = ptr->ETH_ReceiveAll | + ptr->ETH_SourceAddrFilter | + ptr->ETH_PassControlFrames | + ptr->ETH_BroadcastFramesReception | + ptr->ETH_DestinationAddrFilter | + ptr->ETH_PromiscuousMode | + ptr->ETH_MulticastFramesFilter | + ptr->ETH_UnicastFramesFilter; + + ETH->MACHTHR = ptr->ETH_HashTableHigh; + ETH->MACHTLR = ptr->ETH_HashTableLow; + + ETH->MACFCR = ETH->MACFCR & MACFCR_CLEAR_MASK | ((ptr->ETH_PauseTime << ETH_MACFCR_PT_Pos) | + ptr->ETH_ZeroQuantaPause | + ptr->ETH_PauseLowThreshold | + ptr->ETH_UnicastPauseFrameDetect | + ptr->ETH_ReceiveFlowControl | + ptr->ETH_TransmitFlowControl); + + ETH->MACVLANTR = ptr->ETH_VLANTagComparison | ptr->ETH_VLANTagIdentifier; + + ETH->DMAOMR = 0x00200004; + ETH->DMAIER = 0x0001A040; + ETH->DMABMR = ( ptr->ETH_AddressAlignedBeats | + ptr->ETH_FixedBurst | + ptr->ETH_RxDMABurstLength | // !! if 4xPBL is selected for Tx or Rx it is applied for the other + ptr->ETH_TxDMABurstLength | + ptr->ETH_DescriptorSkipLength << 2 | + ptr->ETH_DMAArbitration);// | +// ETH_DMABMR_USP); // Enable use of separate PBL for Rx and Tx + + return ETH_SUCCESS; +} + +void ETH_Start(void) +{ + ETH_MACTransmissionCmd(ENABLE); + ETH_MACReceptionCmd(ENABLE); + ETH_FlushTransmitFIFO(); + ETH_DMATransmissionCmd(ENABLE); + ETH_DMAReceptionCmd(ENABLE); +} + +void ETH_Stop(void) +{ + ETH_DMATransmissionCmd(DISABLE); + ETH_DMAReceptionCmd(DISABLE); + ETH_MACReceptionCmd(DISABLE); + ETH_FlushTransmitFIFO(); + ETH_MACTransmissionCmd(DISABLE); +} + +void ETH_MACTransmissionCmd(FunctionalState sta) +{ + sta ? (ETH->MACCR |= ETH_MACCR_TE) : (ETH->MACCR &= ~ETH_MACCR_TE); +} + +void ETH_MACReceptionCmd(FunctionalState sta) +{ + sta ? (ETH->MACCR |= ETH_MACCR_RE) : (ETH->MACCR &= ~ETH_MACCR_RE); +} + +FlagStatus ETH_GetFlowControlBusyStatus(void) +{ + return (FlagStatus)(ETH->MACFCR & ETH_MACFCR_FCBBPA); +} + +void ETH_InitiatePauseControlFrame(void) +{ + ETH->MACFCR |= ETH_MACFCR_FCBBPA; +} + +void ETH_BackPressureActivationCmd(FunctionalState sta) +{ + sta ? (ETH->MACFCR |= ETH_MACFCR_FCBBPA) : (ETH->MACFCR &= ~ETH_MACFCR_FCBBPA); +} + +void ETH_MACAddressConfig(u32 reg_addr, u8* mac_addr) +{ + *(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr) = + (u32)mac_addr[5] << 8 | + (u32)mac_addr[4]; + + *(__IO u32*)(ETH_MAC_ADDR_LBASE + reg_addr) = + (u32)mac_addr[3] << 24 | + (u32)mac_addr[2] << 16 | + (u32)mac_addr[1] << 8 | + (u32)mac_addr[0]; +} + +void ETH_GetMACAddress(u32 reg_addr, u8* mac_addr) +{ + mac_addr[5] = *(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr) >> 8 & 0xFF; + mac_addr[4] = *(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr) & 0xFF; + mac_addr[3] = *(__IO u32*)(ETH_MAC_ADDR_LBASE + reg_addr) >> 24 & 0xFF; + mac_addr[2] = *(__IO u32*)(ETH_MAC_ADDR_LBASE + reg_addr) >> 16 & 0xFF; + mac_addr[1] = *(__IO u32*)(ETH_MAC_ADDR_LBASE + reg_addr) >> 8 & 0xFF; + mac_addr[0] = *(__IO u32*)(ETH_MAC_ADDR_LBASE + reg_addr) & 0xFF; +} + +void ETH_MACAddressPerfectFilterCmd(u32 reg_addr, FunctionalState sta) +{ + sta ? ((*(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr)) |= ETH_MACA1HR_AE) : + ((*(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr)) &= ~ETH_MACA1HR_AE); +} + +void ETH_MACAddressFilterConfig(u32 reg_addr, u32 sta) +{ + sta ? ((*(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr)) |= ETH_MACA1HR_SA) : + ((*(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr)) |= ETH_MACA1HR_SA); +} + +void ETH_MACAddressMaskBytesFilterConfig(u32 reg_addr, u32 mask_byte) +{ + (*(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr)) &= ~ETH_MACA1HR_MBC; + + (*(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr)) |= mask_byte; +} + +FrameTypeDef ETH_Get_Received_Frame(void) +{ + FrameTypeDef frame; + + frame.len = ((DMARxDescToGet->CS & ETH_DMA_RDES_FL) >> ETH_DMA_RDES_FL_Pos) - 4; + frame.buf = (DMA_RX_FRAME_infos->ptrFS_Rx_Desc)->BUF1ADDR; + frame.ptrDesc = DMA_RX_FRAME_infos->ptrFS_Rx_Desc; + + + DMARxDescToGet = (ETH_DMADESCTypeDef*)(DMARxDescToGet->BUF2NDADDR); + + return frame; +} + +FrameTypeDef ETH_Get_Received_Frame_interrupt(void) +{ + FrameTypeDef frame = {0}; + __IO u32 desc_cnt = 0; + + while(!(DMARxDescToGet->CS & ETH_DMA_RDES_OWN) && desc_cnt < ETH_RX_BUF_NUM) { + desc_cnt++; + + if ( (DMARxDescToGet->CS & ETH_DMA_RDES_FS) && + !(DMARxDescToGet->CS & ETH_DMA_RDES_LS)) { + DMA_RX_FRAME_infos->ptrFS_Rx_Desc = DMARxDescToGet; + DMA_RX_FRAME_infos->cnt = 1; + DMARxDescToGet = (ETH_DMADESCTypeDef*)(DMARxDescToGet->BUF2NDADDR); + + } + else if ( (DMARxDescToGet->CS & ETH_DMA_RDES_FS) && + (DMARxDescToGet->CS & ETH_DMA_RDES_LS)) { + DMA_RX_FRAME_infos->cnt++; + DMARxDescToGet = (ETH_DMADESCTypeDef*)(DMARxDescToGet->BUF2NDADDR); + } + else { + DMA_RX_FRAME_infos->ptrLS_Rx_Desc = DMARxDescToGet; + DMA_RX_FRAME_infos->cnt++; + + if (DMA_RX_FRAME_infos->cnt == 1) + DMA_RX_FRAME_infos->ptrFS_Rx_Desc = DMARxDescToGet; + + frame.len = ((DMARxDescToGet->CS & ETH_DMA_RDES_FL) >> ETH_DMA_RDES_FL_Pos) - 4; + + frame.buf = (DMA_RX_FRAME_infos->cnt > 1) ? + (DMA_RX_FRAME_infos->ptrFS_Rx_Desc->BUF1ADDR) : + (DMARxDescToGet->BUF1ADDR); + + frame.ptrDesc = DMA_RX_FRAME_infos->ptrFS_Rx_Desc; + + DMARxDescToGet = (ETH_DMADESCTypeDef*)(DMARxDescToGet->BUF2NDADDR); + + return frame; + } + } + + return frame; +} + +u32 ETH_Prepare_Transmit_Descriptors(u16 len) +{ + u32 cnt = 0, i = 0; + __IO ETH_DMADESCTypeDef* temp_desc = DMATxDescToSet; + + if (DMATxDescToSet->CS & ETH_DMA_TDES_OWN) + return ETH_ERROR; + + if(len > ETH_TX_BUF_SIZE) { + cnt = len / ETH_TX_BUF_SIZE; + + if (len % ETH_TX_BUF_SIZE) + cnt++; + } + else { + cnt = 1; + } + + if (cnt == 1) { + temp_desc->BL &= ~(ETH_DMA_TDES_FS | ETH_DMA_TDES_LS | ETH_DMA_TDES_TBS1); + + temp_desc->BL |= ETH_DMA_TDES_FS | + ETH_DMA_TDES_LS | + (len & ETH_DMA_TDES_TBS1); + + temp_desc->CS |= ETH_DMA_TDES_OWN; + temp_desc = (ETH_DMADESCTypeDef*)(temp_desc->BUF2NDADDR); + } + else { + for (i = 0; i < cnt; i++) { + temp_desc->BL &= ~(ETH_DMA_TDES_FS | ETH_DMA_TDES_LS); + + if (i == 0) + temp_desc->BL |= ETH_DMA_TDES_FS; + + temp_desc->BL = ETH_TX_BUF_SIZE & ETH_DMA_TDES_TBS1; + + if (i == (cnt - 1)) { + temp_desc->BL &= ~ETH_DMA_TDES_TBS1; + temp_desc->BL |= ETH_DMA_TDES_LS | + ((len - (cnt - 1) * ETH_TX_BUF_SIZE) & ETH_DMA_TDES_TBS1); + } + + temp_desc->CS |= ETH_DMA_TDES_OWN; + temp_desc = (ETH_DMADESCTypeDef*)(temp_desc->BUF2NDADDR); + } + } + + DMATxDescToSet = temp_desc; + + if (ETH->DMASR & ETH_DMASR_TBUS) { + ETH->DMASR = ETH_DMASR_TBUS; + ETH->DMATPDR = 0; + } + + return ETH_SUCCESS; +} + +void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef* ptr_desc, u8* buf, u32 cnt) +{ + u32 i = 0; + ETH_DMADESCTypeDef* temp_desc; + + DMARxDescToGet = ptr_desc; + + for (i = 0; i < cnt; i++) { + temp_desc = ptr_desc + i; + temp_desc->CS = ETH_DMA_RDES_OWN; + temp_desc->BL = ETH_DMA_RDES_RCH | ETH_RX_BUF_SIZE; + temp_desc->BUF1ADDR = (u32)&buf[i * ETH_RX_BUF_SIZE]; + + if (i < cnt - 1) { + temp_desc->BUF2NDADDR = (u32)(ptr_desc + i + 1); + } + else { + temp_desc->BUF2NDADDR = (u32)(ptr_desc); + } + } + + ETH->DMARDLAR = (u32)ptr_desc; + + DMA_RX_FRAME_infos = &RX_Frame_Descriptor; +} + +u32 ETH_CheckFrameReceived(void) +{ + if(!(DMARxDescToGet->CS & ETH_DMA_RDES_OWN) && + (DMARxDescToGet->CS & ETH_DMA_RDES_LS)) { + + DMA_RX_FRAME_infos->cnt++; + + if (DMA_RX_FRAME_infos->cnt == 1) { + DMA_RX_FRAME_infos->ptrFS_Rx_Desc = DMARxDescToGet; + } + DMA_RX_FRAME_infos->ptrLS_Rx_Desc = DMARxDescToGet; + return 1; + } + else if ( !(DMARxDescToGet->CS & ETH_DMA_RDES_OWN) && + !(DMARxDescToGet->CS & ETH_DMA_RDES_LS) && + (DMARxDescToGet->CS & ETH_DMA_RDES_FS)) { + DMA_RX_FRAME_infos->ptrFS_Rx_Desc = DMARxDescToGet; + DMA_RX_FRAME_infos->ptrLS_Rx_Desc = (void*)0; + DMA_RX_FRAME_infos->cnt = 1; + } + else if ( !(DMARxDescToGet->CS & ETH_DMA_RDES_OWN) && + !(DMARxDescToGet->CS & ETH_DMA_RDES_LS) && + !(DMARxDescToGet->CS & ETH_DMA_RDES_FS)) { + DMA_RX_FRAME_infos->cnt++; + DMARxDescToGet = (ETH_DMADESCTypeDef*)(DMARxDescToGet->BUF2NDADDR); + } + + return 0; +} + +void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef* ptr_desc, u8* buf, u32 cnt) +{ + u32 i = 0; + ETH_DMADESCTypeDef* temp_desc; + + DMATxDescToSet = ptr_desc; + + for (i = 0; i < cnt; i++) { + temp_desc = ptr_desc + i; + temp_desc->BL = ETH_DMA_TDES_TCH; + temp_desc->BUF1ADDR = (u32)(&buf[i * ETH_TX_BUF_SIZE]); + + if (i < cnt - 1) { + temp_desc->BUF2NDADDR = (u32)(ptr_desc + i + 1); + } + else { + temp_desc->BUF2NDADDR = (u32)(ptr_desc); + } + } + + ETH->DMATDLAR = (u32)ptr_desc; +} + +FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef* ptr_desc, u32 flag) +{ + return (FlagStatus)(ptr_desc->CS & flag); +} + +u32 ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef* ptr_desc) +{ + return (ptr_desc->CS & ETH_DMA_TDES_CC) >> ETH_DMA_TDES_COLLISION_COUNTSHIFT; +} + +void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef* ptr_desc) +{ + ptr_desc->CS |= ETH_DMA_TDES_OWN; +} + +void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta) +{ + sta ? (ptr_desc->BL |= ETH_DMA_TDES_IC) : (ptr_desc->BL &= ~ETH_DMA_TDES_IC); +} + +void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef* ptr_desc, u32 val) +{ + ptr_desc->CS |= val; +} + +void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef* ptr_desc, u32 val) +{ + ptr_desc->CS |= val; +} + +void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta) +{ + sta ? (ptr_desc->BL &= ~ETH_DMA_TDES_DC) : (ptr_desc->BL |= ETH_DMA_TDES_DC); +} + +void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta) +{ + sta ? (ptr_desc->BL |= ETH_DMA_TDES_TCH) : (ptr_desc->BL &= ~ETH_DMA_TDES_TCH); +} + +void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta) +{ + sta ? (ptr_desc->BL &= ~ETH_DMA_TDES_DP) : (ptr_desc->BL |= ETH_DMA_TDES_DP); +} + +void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef* ptr_desc, u32 buf1_size, u32 buf2_size) +{ + ptr_desc->BL |= buf1_size | (buf2_size << ETH_DMA_TDES_BUFFER2_SIZESHIFT); +} + +FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef* ptr_desc, u32 flag) +{ + return (FlagStatus)(ptr_desc->CS & flag); +} + +void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef* ptr_desc) +{ + ptr_desc->CS |= ETH_DMA_RDES_OWN; +} + +u32 ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef* ptr_desc) +{ + return (ptr_desc->CS & ETH_DMA_RDES_FL) >> ETH_DMA_RDES_FRAME_LENGTHSHIFT; +} + +void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta) +{ + sta ? (ptr_desc->CS &= ~ETH_DMA_RDES_DIC) : (ptr_desc->CS |= ETH_DMA_RDES_DIC); +} + +u32 ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef* ptr_desc, u32 buf) +{ + return (buf != ETH_DMA_RDES_Buffer1 ? + ((ptr_desc->BL & ETH_DMA_RDES_RBS2) >> ETH_DMA_RDES_BUFFER2_SIZESHIFT) : + (ptr_desc->BL & ETH_DMA_RDES_RBS1)); +} + +u32 ETH_GetRxPktSize(ETH_DMADESCTypeDef* ptr_desc) +{ + u32 len = 0; + + if ( !(ptr_desc->CS & ETH_DMA_RDES_OWN) && + !(ptr_desc->CS & ETH_DMA_RDES_ES) && + (ptr_desc->CS & ETH_DMA_RDES_LS)) { + len = ETH_GetDMARxDescFrameLength(ptr_desc); + } + + return len; +} + +//////////////////////////////////////////////////////////////////////////////// +void ETH_SoftwareReset(void) +{ + ETH->DMABMR |= ETH_DMABMR_SR; +} + +FlagStatus ETH_GetSoftwareResetStatus(void) +{ + return (FlagStatus)(ETH->DMABMR & ETH_DMABMR_SR); +} + +FlagStatus ETH_GetDMAFlagStatus(u32 flag) +{ + return (FlagStatus)(ETH->DMASR & flag); +} + +void ETH_DMAClearFlag(u32 flag) +{ + ETH->DMASR = flag; +} + +void ETH_DMAITConfig(u32 it, FunctionalState sta) +{ + sta ? (ETH->DMAIER |= it) : (ETH->DMAIER &= ~it); +} + +ITStatus ETH_GetDMAITStatus(u32 it) +{ + return (ITStatus)(ETH->DMASR & it); +} + +void ETH_DMAClearITPendingBit(u32 it) +{ + ETH->DMASR = it; +} + +u32 ETH_GetTransmitProcessState(void) +{ + return ETH->DMASR & ETH_DMASR_TS; +} + +u32 ETH_GetReceiveProcessState(void) +{ + return ETH->DMASR & ETH_DMASR_RS; +} + +void ETH_FlushTransmitFIFO(void) +{ + ETH->DMAOMR |= ETH_DMAOMR_FTF; +} + +FlagStatus ETH_GetFlushTransmitFIFOStatus(void) +{ + return (FlagStatus)(ETH->DMAOMR & ETH_DMAOMR_FTF); +} + +void ETH_DMATransmissionCmd(FunctionalState sta) +{ + sta ? (ETH->DMAOMR |= ETH_DMAOMR_ST) : (ETH->DMAOMR &= ~ETH_DMAOMR_ST); +} + +void ETH_DMAReceptionCmd(FunctionalState sta) +{ + sta ? (ETH->DMAOMR |= ETH_DMAOMR_SR) : (ETH->DMAOMR &= ~ETH_DMAOMR_SR); +} + +FlagStatus ETH_GetDMAOverflowStatus(u32 val) +{ + return (FlagStatus)(ETH->DMAMFBOCR & val); +} + +u32 ETH_GetRxOverflowMissedFrameCounter(void) +{ + return (ETH->DMAMFBOCR & ETH_DMAMFBOCR_MFA) >> + ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT; +} + +u32 ETH_GetBufferUnavailableMissedFrameCounter(void) +{ + return ETH->DMAMFBOCR & ETH_DMAMFBOCR_MFC; +} + +u32 ETH_GetCurrentTxDescStartAddress(void) +{ + return ETH->DMACHTDR; +} + +u32 ETH_GetCurrentRxDescStartAddress(void) +{ + return ETH->DMACHRDR; +} + +u32 ETH_GetCurrentTxBufferAddress(void) +{ + return ETH->DMACHTBAR; +} + +u32 ETH_GetCurrentRxBufferAddress(void) +{ + return ETH->DMACHRBAR; +} + +void ETH_ResumeDMATransmission(void) +{ + ETH->DMATPDR = 0; +} + +void ETH_ResumeDMAReception(void) +{ + ETH->DMARPDR = 0; +} + +void ETH_SetReceiveWatchdogTimer(u8 val) +{ + ETH->DMARSWTR = val; +} + +//////////////////////////////////////////////////////////////////////////////// +u16 ETH_ReadPHYRegister(u16 addr, u16 reg) +{ + u32 dat; + // Set phy address and reg address, clear write flag + ETH->MACMIIAR = (((ETH->MACMIIAR & ~MACMIIAR_CR_MASK) | + (addr << ETH_MACMIIAR_PA_Pos & ETH_MACMIIAR_PA) | + (reg << ETH_MACMIIAR_MR_Pos & ETH_MACMIIAR_MR)) & + (~ETH_MACMIIAR_MW)) | ETH_MACMIIAR_MB; + + // Check busy flag + while(ETH->MACMIIAR & ETH_MACMIIAR_MB); + dat = (u16)ETH->MACMIIDR; + if(dat == 0xFFFF) { + dat = 0; + } + return dat; +} + +u16 ETH_WritePHYRegister(u16 addr, u16 reg, u16 val) +{ + // Load data + ETH->MACMIIDR = val; + + // Set phy address, reg address and write flag + ETH->MACMIIAR = (ETH->MACMIIAR & ~MACMIIAR_CR_MASK) | + (addr << ETH_MACMIIAR_PA_Pos & ETH_MACMIIAR_PA) | + (reg << ETH_MACMIIAR_MR_Pos & ETH_MACMIIAR_MR) | + ETH_MACMIIAR_MW | + ETH_MACMIIAR_MB; + + // Check busy flag + while(ETH->MACMIIAR & ETH_MACMIIAR_MB); + + return ETH->MACMIIDR; +} + +u32 ETH_PHYLoopBackCmd(u16 addr, FunctionalState sta) +{ + u16 temp_val = ETH_ReadPHYRegister(addr, PHY_BCR); + + sta ? (temp_val |= PHY_Loopback) : (temp_val &= ~PHY_Loopback); + + if(ETH_WritePHYRegister(addr, PHY_BCR, temp_val)) + return ETH_SUCCESS; + + return ETH_ERROR; +} + +//////////////////////////////////////////////////////////////////////////////// + +void ETH_ResetWakeUpFrameFilterRegisterPointer(void) +{ + ETH->MACPMTCSR |= ETH_MACPMTCSR_WFFRPR; +} + +void ETH_SetWakeUpFrameFilterRegister(u32* buf) +{ + u32 i = 0; + + for (i = 0; i < ETH_WAKEUP_REGISTER_LENGTH; i++) { + ETH->MACRWUFFR = buf[i]; + } +} + +void ETH_GlobalUnicastWakeUpCmd(FunctionalState sta) +{ + sta ? (ETH->MACPMTCSR |= ETH_MACPMTCSR_GU) : (ETH->MACPMTCSR &= ~ETH_MACPMTCSR_GU); +} + +FlagStatus ETH_GetPMTFlagStatus(u32 flag) +{ + return (FlagStatus)(ETH->MACPMTCSR & flag); +} + +void ETH_WakeUpFrameDetectionCmd(FunctionalState sta) +{ + sta ? (ETH->MACPMTCSR |= ETH_MACPMTCSR_WFE) : (ETH->MACPMTCSR &= ~ETH_MACPMTCSR_WFE); +} + +void ETH_MagicPacketDetectionCmd(FunctionalState sta) +{ + sta ? (ETH->MACPMTCSR |= ETH_MACPMTCSR_MPE) : (ETH->MACPMTCSR &= ~ETH_MACPMTCSR_MPE); +} + +void ETH_PowerDownCmd(FunctionalState sta) +{ + sta ? (ETH->MACPMTCSR |= ETH_MACPMTCSR_PD) : (ETH->MACPMTCSR &= ~ETH_MACPMTCSR_PD); +} + +//////////////////////////////////////////////////////////////////////////////// + +void ETH_MMCCounterFullPreset(void) +{ + ETH->MMCCR |= ETH_MMCCR_MCFHP | ETH_MMCCR_MCP; +} + +void ETH_MMCCounterHalfPreset(void) +{ + ETH->MMCCR &= ~ETH_MMCCR_MCFHP; + + ETH->MMCCR |= ETH_MMCCR_MCP; +} + +void ETH_MMCCounterFreezeCmd(FunctionalState sta) +{ + sta ? (ETH->MMCCR |= ETH_MMCCR_MCF) : (ETH->MMCCR &= ~ETH_MMCCR_MCF); +} + +void ETH_MMCResetOnReadCmd(FunctionalState sta) +{ + sta ? (ETH->MMCCR |= ETH_MMCCR_ROR) : (ETH->MMCCR &= ~ETH_MMCCR_ROR); +} + +void ETH_MMCCounterRolloverCmd(FunctionalState sta) +{ + sta ? (ETH->MMCCR &= ~ETH_MMCCR_CSR) : (ETH->MMCCR |= ETH_MMCCR_CSR); +} + +void ETH_MMCCountersReset(void) +{ + ETH->MMCCR |= ETH_MMCCR_CR; +} + +void ETH_MMCITConfig(u32 it, FunctionalState sta) +{ + if (it & 0x10000000) { + it &= 0xEFFFFFFF; + + sta ? (ETH->MMCRIMR &= ~it) : (ETH->MMCRIMR |= it); + } + else { + sta ? (ETH->MMCTIMR &= ~it) : (ETH->MMCTIMR |= it); + } +} + +ITStatus ETH_GetMMCITStatus(u32 it) +{ + if (it & 0x10000000) { + return (ITStatus)((ETH->MMCRIR & it) && !(ETH->MMCRIMR & it)); + } + else { + return (ITStatus)((ETH->MMCTIR & it) && !(ETH->MMCTIMR & it)); + } +} + +u32 ETH_GetMMCRegister(u32 reg) +{ + return *(vu32*)(ETH_BASE + reg); +} diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_exti.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_exti.c new file mode 100644 index 000000000..409d84d80 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_exti.c @@ -0,0 +1,222 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_exti.c +/// @author AE TEAM +/// @brief THIS FILE PROVIDES ALL THE EXTI FIRMWARE FUNCTIONS. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#define _HAL_EXTI_C_ + +// Files includes +#include "hal_exti.h" + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup EXTI_HAL +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup EXTI_Exported_Functions +/// @{ + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Deinitializes the EXTI peripheral registers to their default reset +/// values. +/// @param None. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Deinitializes the EXTI registers to their default reset values. +/// @param None. +/// @retval None. +/// @note MEM_MODE bits are not affected by APB reset. +/// @note MEM_MODE bits took the value from the user option bytes. +/// @note CFGR2 register is not affected by APB reset. +/// @note CLABBB configuration bits are locked when set. +/// @note To unlock the configuration, perform a system reset. +//////////////////////////////////////////////////////////////////////////////// +void EXTI_DeInit(void) +{ + u16 i; + // Clear all + exEXTI_LineDisable(~0x00000000); + + // rc_w1 + EXTI->PR = EXTI->PR; + + // Set EXTI_CFGR1 register to reset value without affecting MEM_MODE bits + EXTI->CFGR &= EXTI_CFGR_MEMMODE; + + // Set EXTICRx registers to reset value + for (i = 0; i < 4; i++) { + EXTI->CR[i] = 0; + } +} + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Selects the GPIO pin used as EXTI Line. +/// @param port_source_gpio: selects the GPIO port to be used as source for EXTI lines . +/// @param pin_source: specifies the EXTI line to be configured. +/// @note This parameter can be pin_source where x can be: +/// For MCU: (0..15) for GPIOA, GPIOB, (13..15) for GPIOC and (0..1, 6..7) for GPIOD. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void EXTI_LineConfig(u8 port_source_gpio, u8 pin_source) +{ + EXTI->CR[pin_source >> 0x02] &= ~(0x0F << (0x04 * (pin_source & 0x03))); + EXTI->CR[pin_source >> 0x02] |= ((port_source_gpio) << (0x04 * (pin_source & 0x03))); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Initializes the EXTI peripheral according to the specified +/// parameters in the init_struct. +/// @param init_struct: pointer to a EXTI_InitTypeDef structure that +/// contains the configuration information for the EXTI peripheral. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void EXTI_Init(EXTI_InitTypeDef* init_struct) +{ + if (init_struct->EXTI_LineCmd != DISABLE) { + EXTI->IMR &= ~init_struct->EXTI_Line; + EXTI->EMR &= ~init_struct->EXTI_Line; + if (init_struct->EXTI_Mode == EXTI_Mode_Interrupt) { + EXTI->IMR |= init_struct->EXTI_Line; + } + else { + EXTI->EMR |= init_struct->EXTI_Line; + } + EXTI->RTSR &= ~init_struct->EXTI_Line; + EXTI->FTSR &= ~init_struct->EXTI_Line; + if (init_struct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) { + EXTI->RTSR |= init_struct->EXTI_Line; + EXTI->FTSR |= init_struct->EXTI_Line; // Rising and Faling afio + } + else if (init_struct->EXTI_Trigger == EXTI_Trigger_Rising) { + EXTI->RTSR |= init_struct->EXTI_Line; + } + else { + EXTI->FTSR |= init_struct->EXTI_Line; + } + } + else { + if (init_struct->EXTI_Mode == EXTI_Mode_Interrupt) { + EXTI->IMR &= ~init_struct->EXTI_Line; + } + else { + EXTI->EMR &= ~init_struct->EXTI_Line; + } + } +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Fills each init_struct member with its reset value. +/// @param init_struct: pointer to a EXTI_InitTypeDef structure which will +/// be initialized. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void EXTI_StructInit(EXTI_InitTypeDef* init_struct) +{ + init_struct->EXTI_Line = EXTI_LineNone; + init_struct->EXTI_Mode = EXTI_Mode_Interrupt; + init_struct->EXTI_Trigger = EXTI_Trigger_Falling; + init_struct->EXTI_LineCmd = DISABLE; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Generates a Software interrupt on selected EXTI line. +/// @param line: specifies the EXTI line on which the software interrupt +/// will be generated. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void EXTI_GenerateSWInterrupt(u32 line) +{ + EXTI->SWIER |= line; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Checks whether the specified EXTI line flag is set or not. +/// @param line: specifies the EXTI line flag to check. +/// @retval The new state of line (SET or RESET). +//////////////////////////////////////////////////////////////////////////////// +FlagStatus EXTI_GetFlagStatus(u32 line) +{ + return (EXTI->PR & line) ? SET : RESET; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Clears the EXTI's line pending flags. +/// @param line: specifies the EXTI lines flags to clear. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void EXTI_ClearFlag(u32 line) +{ + EXTI->PR = line; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Checks whether the specified EXTI line is asserted or not. +/// @param line: specifies the EXTI line to check. +/// @retval The new state of line (SET or RESET). +//////////////////////////////////////////////////////////////////////////////// +ITStatus EXTI_GetITStatus(u32 line) +{ + return ((EXTI->PR & line) && (EXTI->IMR & line)) ? SET : RESET; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Clears the EXTI's line pending bits. +/// @param line: specifies the EXTI lines to clear. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void EXTI_ClearITPendingBit(u32 line) +{ + EXTI->PR = line; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief EXTI Line Disable +/// @param line: specifies the EXTI lines to clear. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void exEXTI_LineDisable(u32 line) +{ + EXTI->IMR &= ~line; + EXTI->EMR &= ~line; + EXTI->RTSR &= ~line; + EXTI->FTSR &= ~line; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Clears the EXTI's line all pending bits. +/// @param None. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +u32 exEXTI_GetAllFlagStatus(void) +{ + return EXTI->PR; +} + +/// @} + +/// @} + +/// @} + diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_flash.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_flash.c new file mode 100644 index 000000000..ecdc8be3a --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_flash.c @@ -0,0 +1,548 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_flash.c +/// @author AE TEAM +/// @brief THIS FILE PROVIDES ALL THE FLASH FIRMWARE FUNCTIONS. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#define _HAL_FLASH_C_ + +// Files includes +#include "hal_flash.h" + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup FLASH_HAL +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup FLASH_Exported_Functions +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Sets the code latency value. +/// @note This function can be used for all MM32 devices. +/// @param latency: specifies the FLASH Latency value. +/// This parameter can be one of the following values: +/// @arg FLASH_Latency_0: FLASH Zero Latency cycle +/// @arg FLASH_Latency_1: FLASH One Latency cycle +/// @arg FLASH_Latency_2: FLASH Two Latency cycles +/// @arg FLASH_Latency_3: FLASH Three Latency cycles +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void FLASH_SetLatency(FLASH_Latency_TypeDef latency) +{ + FLASH->ACR = (FLASH->ACR & (~FLASH_ACR_LATENCY)) | latency; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the Half cycle flash access. +/// @note This function can be used for all MM32 devices. +/// @param half_cycle_access: specifies the FLASH Half cycle Access mode. +/// This parameter can be one of the following values: +/// @arg FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable +/// @arg FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void FLASH_HalfCycleAccessCmd(FLASH_HalfCycleAccess_TypeDef half_cycle_access) +{ + FLASH->ACR &= ~FLASH_ACR_HLFCYA; + FLASH->ACR |= half_cycle_access; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the Prefetch Buffer. +/// @note This function can be used for all MM32 devices. +/// @param prefetch_buffer: specifies the Prefetch buffer status. +/// This parameter can be one of the following values: +/// @arg FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable +/// @arg FLASH_PrefetchBuffer_Disable: FLASH Prefetch Buffer Disable +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_TypeDef prefetch_buffer) +{ + FLASH->ACR &= ~FLASH_ACR_PRFTBE; + FLASH->ACR |= prefetch_buffer; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Locks the FLASH Program Erase Controller. +/// @note This function can be used for all MM32 devices. +/// @param None. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void FLASH_Lock(void) +{ + FLASH->CR |= FLASH_CR_LOCK; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Unlocks the FLASH Program Erase Controller. +/// @note This function can be used for all MM32 devices. +/// @param None. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void FLASH_Unlock() +{ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enable to program the FLASH Option Byte. +/// @note This function can be used for all MM32 devices. +/// @param None. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void FLASH_OPTB_Enable(void) +{ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Erases a specified FLASH page. +/// @note This function can be used for all MM32 devices. +/// @param page_address: The page address to be erased. +/// @retval FLASH Status: The returned value can be: FLASH_BUSY, +/// FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. +//////////////////////////////////////////////////////////////////////////////// +FLASH_Status FLASH_ErasePage(u32 page_address) +{ + FLASH->CR |= FLASH_CR_PER; + FLASH->AR = page_address; + FLASH->CR |= FLASH_CR_STRT; + return FLASH_WaitForLastOperation(EraseTimeout); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Erases all FLASH pages. +/// @note This function can be used for all MM32 devices. +/// @param None. +/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, +/// FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. +//////////////////////////////////////////////////////////////////////////////// +FLASH_Status FLASH_EraseAllPages() +{ + FLASH->AR = FLASH_BASE; + FLASH->CR |= (FLASH_CR_MER | FLASH_CR_STRT); + return FLASH_WaitForLastOperation(EraseTimeout); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Erases the FLASH option bytes. +/// @note This function can be used for all MM32 devices. +/// @param None. +/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, +/// FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. +//////////////////////////////////////////////////////////////////////////////// +FLASH_Status FLASH_EraseOptionBytes() +{ + FLASH_OPTB_Enable(); + FLASH->AR = OB_BASE; + FLASH->CR |= (FLASH_CR_OPTER | FLASH_CR_STRT); + return FLASH_WaitForLastOperation(EraseTimeout); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Programs a half word at a specified address. +/// @note This function can be used for all MM32 devices. +/// @param address: specifies the address to be programmed. +/// @param data: specifies the data to be programmed. +/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, +/// FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. +//////////////////////////////////////////////////////////////////////////////// +FLASH_Status FLASH_ProgramHalfWord(u32 address, u16 data) +{ + FLASH->CR |= FLASH_CR_PG; + + *(vu16*)address = data; + + + return FLASH_WaitForLastOperation(ProgramTimeout); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Programs a word at a specified address. +/// @note This function can be used for all MM32 devices. +/// @param address: specifies the address to be programmed. +/// @param data: specifies the data to be programmed. +/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, +/// FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. +//////////////////////////////////////////////////////////////////////////////// +FLASH_Status FLASH_ProgramWord(u32 address, u32 data) +{ + FLASH_Status ret = FLASH_ProgramHalfWord(address, data); + if (ret == FLASH_COMPLETE) { + ret = FLASH_ProgramHalfWord(address + 2, data >> 16); + } + return ret; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Programs a byte at a specified Option Byte Data address. +/// @note This function can be used for all MM32 devices. +/// @param address: specifies the address to be programmed. +/// This parameter can be 0x1FFFF804 or 0x1FFFF806. +/// @param data: specifies the data to be programmed. +/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, +/// FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. +//////////////////////////////////////////////////////////////////////////////// +FLASH_Status FLASH_ProgramOptionByteData(u32 address, u8 data) +{ + FLASH_Status ret; + __IO u16 temp; + FLASH_OPTB_Enable(); + FLASH->CR |= FLASH_CR_OPTPG; + temp = (u16)(~data); + temp = (temp << 8) & 0xFF00; + temp = temp | (u16)data; + address = address & (~0x1); + *(vu16*)address = temp; + ret = FLASH_WaitForLastOperation(ProgramTimeout); + + return ret; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Programs a half word at a specified Option Byte Data address. +/// @note This function can be used for all MM32 devices. +/// @param address: specifies the address to be programmed. +/// This parameter can be 0x1FFFF804 or 0x1FFFF806. +/// @param data: specifies the data to be programmed. +/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, +/// FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. +//////////////////////////////////////////////////////////////////////////////// +FLASH_Status FLASH_ProgramOptionHalfWord(u32 address, u16 data) +{ + FLASH_Status ret; + FLASH_OPTB_Enable(); + FLASH->CR |= FLASH_CR_OPTPG; + *(vu16*)address = data; + ret = FLASH_WaitForLastOperation(ProgramTimeout); + + return ret; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Read protection for the specified address +/// @note This function can be used for all MM32 devices. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +FLASH_Status FLASH_ProgramProtect(u32 address, u16 data) +{ + return FLASH_ProgramOptionHalfWord(address, data); + +// FLASH_Status ret; +// ret = FLASH_ProgramOptionHalfWord(address, 0x7F80); +// +// if (ret == FLASH_COMPLETE) { +// ret = FLASH_ProgramOptionHalfWord(address + 2, 0xFF00); +// } +// return ret; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Write protection for the specified address +/// @note This function can be used for all MM32 devices. +/// @param page: specifies the address of the pages to be write +/// protected. +/// This parameter is (0x01 << ((Absolute address - 0x08000000)/0x1000)) +/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, +/// FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. +//////////////////////////////////////////////////////////////////////////////// +FLASH_Status FLASH_EnableWriteProtection(u32 page) +{ + FLASH_Status ret; + u8 i; + for (i = 0; i < 4; i++) { + ret = FLASH_ProgramOptionHalfWord((OB_BASE + 8 + i * 2), ~(page >> (i * 8))); + if (ret != FLASH_COMPLETE) { + break; + } + } + return ret; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. +/// @note This function can be used for all MM32 devices. +/// @param ob_iwdg: Selects the IWDG mode +/// @param ob_stop: Reset event when entering STOP mode. +/// @param standby: Reset event when entering Standby mode. +/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, +/// FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. +//////////////////////////////////////////////////////////////////////////////// +FLASH_Status FLASH_UserOptionByteConfig(OB_IWDG_TypeDef ob_iwdg, OB_STOP_TypeDef ob_stop, OB_STDBY_TypeDef standby) +{ + FLASH_OPTB_Enable(); + FLASH->CR |= FLASH_CR_OPTPG; + OB->USER = ob_iwdg; + OB->USER |= ob_stop; + OB->USER |= standby; + OB->USER |= 0xF8; + // OB->USER = iwdg | stop | stdby | 0xF8; + return FLASH_WaitForLastOperation(ProgramTimeout); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Returns the FLASH User Option Bytes values. +/// @note This function can be used for all MM32 devices. +/// @param None. +/// @retval The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1) +/// and RST_STDBY(Bit2). +//////////////////////////////////////////////////////////////////////////////// +u32 FLASH_GetUserOptionByte() +{ + return (FLASH->OBR >> 2); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Returns the FLASH Write Protection Option Bytes Register value. +/// @note This function can be used for all MM32 devices. +/// @param None. +/// @retval The FLASH Write Protection Option Bytes Register value. +//////////////////////////////////////////////////////////////////////////////// +u32 FLASH_GetWriteProtectionOptionByte() +{ + return (FLASH->WRPR); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Checks whether the FLASH Prefetch Buffer status is set or not. +/// @note This function can be used for all MM32 devices. +/// @param None. +/// @retval FLASH Prefetch Buffer Status (SET or RESET). +//////////////////////////////////////////////////////////////////////////////// +FlagStatus FLASH_GetPrefetchBufferStatus(void) +{ + return (FLASH->ACR & FLASH_ACR_PRFTBS) ? SET : RESET; +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the specified FLASH interrupts. +/// @note This function can be used for all MM32 devices. +/// @param interrupt: specifies the FLASH interrupt sources to be enabled or +/// disabled. +/// @param state: new state of the specified Flash interrupts. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void FLASH_ITConfig(FLASH_IT_TypeDef interrupt, FunctionalState state) +{ + (state) ? (FLASH->CR |= interrupt) : (FLASH->CR &= ~interrupt); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Checks whether the specified FLASH flag is set or not. +/// @note This function can be used for all MM32 devices. +/// @param flag: specifies the FLASH flags to clear. +/// This parameter can be one of the following values: +/// @arg FLASH_FLAG_BSY: FLASH Busy flag +/// @arg FLASH_FLAG_PGERR: FLASH Program error flag +/// @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag +/// @arg FLASH_FLAG_EOP: FLASH End of Operation flag +/// @arg FLASH_FLAG_OPTERR: FLASH Option Byte error flag +/// @retval The new state of FLASH_FLAG (SET or RESET). +//////////////////////////////////////////////////////////////////////////////// +FlagStatus FLASH_GetFlagStatus(u16 flag) +{ + return ((flag == FLASH_FLAG_OPTERR) ? (FLASH->OBR & FLASH_FLAG_OPTERR) : (FLASH->SR & flag)) ? SET : RESET; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Clears the FLASH's pending flags. +/// @note This function can be used for all MM32 devices. +/// @param flag: specifies the FLASH flags to clear. +/// This parameter can be any combination of the following values: +/// @arg FLASH_FLAG_PGERR: FLASH Program error flag +/// @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag +/// @arg FLASH_FLAG_EOP: FLASH End of Operation flag +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void FLASH_ClearFlag(u16 flag) +{ + FLASH->SR = flag; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Returns the FLASH Status. +/// @note This function can be used for all MM32 devices. +/// @param None. +/// @retval FLASH Status: The returned value can be: FLASH_BUSY, +/// FLASH_ERROR_PG, FLASH_ERROR_WRP or FLASH_COMPLETE. +//////////////////////////////////////////////////////////////////////////////// +FLASH_Status FLASH_GetStatus() +{ + return (FLASH_Status)((FLASH->SR & FLASH_FLAG_BSY)) + ? FLASH_BUSY + : ((FLASH->SR & FLASH_FLAG_PGERR) ? FLASH_ERROR_PG + : ((FLASH->SR & FLASH_FLAG_WRPRTERR) ? FLASH_ERROR_WRP : FLASH_COMPLETE)); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Waits for a Flash operation to complete or a TIMEOUT to occur. +/// @note This function can be used for all MM32 devices +/// @param time_out: FLASH programming time_out +/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, +/// FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. +//////////////////////////////////////////////////////////////////////////////// +FLASH_Status FLASH_WaitForLastOperation(u32 time_out) +{ + u32 i; + FLASH_Status ret; + do { + ret = FLASH_GetStatus(); + time_out--; + for (i = 0xFF; i != 0; i--) + ; + } while ((ret == FLASH_BUSY) && (time_out != 0x00)); + + FLASH->CR = 0; + FLASH->SR = FLASH_SR_EOP | FLASH_SR_WRPRTERR | FLASH_SR_PGERR; + return (FLASH_Status)((time_out == 0x00) ? FLASH_TIMEOUT : ret); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Erases a specified FLASH page. +/// @note This function can be used for all MM32 devices. +/// @param Page_Address: The page address to be erased. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void exFLASH_EraseEE(u32 page_address) +{ + FLASH_Unlock(); + FLASH_ErasePage(page_address); + FLASH_Lock(); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Programs a buffer at a specified address. +/// @note This function can be used for all MM32 devices. +/// @param *buf: the pointer of the buffer to be programmed. +/// @param addr: specifies the address to be programmed. +/// @param len: the number of bytes in the buffer. +/// This parameter can only be even. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void exFLASH_ProgramEE(u16* buf, u32 addr, u16 len) +{ + u16 i; + FLASH_Unlock(); + for (i = 0; i < len / 2; i++) { + FLASH_ProgramHalfWord(addr, *buf); + addr += 2; + buf++; + } + FLASH_Lock(); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Determine if the data that at the ptr address with the length is len +/// is empty. +/// @note This function can be used for all MM32 devices. +/// @param *ptr: the pointer of the starting address. +/// @param len: the number of bytes. +/// This parameter can only be even. +/// @retval 1 presents the data is empty, +/// 0 presents the data has been written. +//////////////////////////////////////////////////////////////////////////////// +u8 exFLASH_FindEmpty(u16* ptr, u16 len) +{ + u16 i; + for (i = 0; i < (len / 2); i++) { + if (*(ptr + i) != 0xffff) + return 0; + } + return 1; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Locate the writable area on the specified address. +/// @note This function can be used for all MM32 devices. +/// @param page_address: specifies the beginning of the EEprom. +/// The EEprom can be some continuously pages in the flash. +/// @param len: the number of bytes to be written. +/// This parameter can only be even. +/// @retval the pointer of the starting address. +//////////////////////////////////////////////////////////////////////////////// +void* exFLASH_Locate(u32 page_address, u16 len) +{ + u16 i; + u16* ptr = (u16*)page_address; + for (i = 0; i < (0x0800 / len); i++) { + if (exFLASH_FindEmpty(ptr, len)) { + if (i == 0) + return 0; + break; + } + ptr += len / 2; + } + return ptr; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Programs a buffer at a specified address. +/// @note This function can be used for all MM32 devices. +/// @param *buf: the pointer of the buffer to be programmed. +/// @param page_address: specifies the beginning of the EEprom. +/// The EEprom can be some continuously pages in the flash. +/// @param len: the number of bytes in the buffer. +/// This parameter can only be even. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void exFLASH_WriteEE(u16* buf, u32 page_address, u16 len) +{ + u16* ptr = exFLASH_Locate(page_address, len); + if (ptr == 0) { + exFLASH_EraseEE(page_address + 0x000); + exFLASH_EraseEE(page_address + 0x400); + exFLASH_ProgramEE(buf, page_address, len); + } + else { + if (ptr == (u16*)(page_address + ((0x0400 / len) - 1) * len)) { + exFLASH_EraseEE(page_address + 0x400); + exFLASH_ProgramEE(buf, (u32)ptr, len); + } + else if (ptr == (u16*)(page_address + 0x0800)) { + exFLASH_EraseEE(page_address + 0x000); + exFLASH_ProgramEE(buf, (u32)page_address, len); + } + else { + exFLASH_ProgramEE(buf, (u32)ptr, len); + } + } +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Read the beginning address of the last written data. +/// @note This function can be used for all MM32 devices. +/// @param page_address: specifies the beginning of the EEprom. +/// The EEprom can be some continuously pages in the flash. +/// @param len: the number of bytes have been written. +/// This parameter can only be even. +/// @retval the beginning address of the last written data. +/// 0 presents that this is the first time to use this as EEprom. +//////////////////////////////////////////////////////////////////////////////// +void* exFLASH_ReadEE(u32 page_address, u16 len) +{ + u16* ptr = exFLASH_Locate(page_address, len); + return (ptr == 0) ? 0 : (ptr - len / 2); +} + +/// @} + +/// @} + +/// @} diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_fsmc.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_fsmc.c new file mode 100644 index 000000000..b4b665a0b --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_fsmc.c @@ -0,0 +1,124 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_fsmc.c +/// @author AE TEAM +/// @brief THIS FILE PROVIDES ALL THE FSMC FIRMWARE FUNCTIONS. +/// Interface with SRAM, PSRAM, NOR memories +/// Interrupts and flags management +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#define _HAL_FSMC_C_ + +// Files includes +#include "reg_rcc.h" +#include "reg_syscfg.h" +#include "hal_fsmc.h" + + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup FSMC_HAL +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup FSMC_Exported_Functions +/// @{ + + +void FSMC_NORSRAMStructInit(FSMC_InitTypeDef* init_struct) +{ + init_struct->FSMC_Mode = FSMC_Mode_NorFlash; + init_struct->FSMC_AddrDataMode = FSMC_AddrDataDeMUX; + + init_struct->FSMC_TimingRegSelect = FSMC_TimingRegSelect_0; + init_struct->FSMC_MemSize = FSMC_MemSize_64MB; + init_struct->FSMC_MemType = FSMC_MemType_NorSRAM; +} +void FSMC_NORSRAM_BankStructInit(FSMC_NORSRAM_Bank_InitTypeDef* init_struct) +{ + + init_struct->FSMC_SMReadPipe = 0; + init_struct->FSMC_ReadyMode = 0; + init_struct->FSMC_WritePeriod = 0x2; + init_struct->FSMC_WriteHoldTime = 1; + init_struct->FSMC_AddrSetTime = 3; + init_struct->FSMC_ReadPeriod = 0x1; + init_struct->FSMC_DataWidth = FSMC_DataWidth_16bits; +} +void FSMC_NORSRAMInit(FSMC_InitTypeDef* init_struct) +{ + SYSCFG->CFGR &= ~(SYSCFG_CFGR_FSMC_MODE | SYSCFG_CFGR_FSMC_AF_ADDR | SYSCFG_CFGR_FSMC_SYNC_EN); + SYSCFG->CFGR |= (u32)init_struct->FSMC_Mode | \ + (u32)init_struct->FSMC_AddrDataMode; + + FSMC->SMSKR = (u32)init_struct->FSMC_TimingRegSelect | \ + (u32)init_struct->FSMC_MemSize | \ + (u32)init_struct->FSMC_MemType; +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Initialize the FSMC_NORSRAM Timing according to the specified +/// parameters in the FSMC_NORSRAM_TimingTypeDef +/// @param FSMC_Bank_InitStruct: Timing Pointer to NORSRAM Timing structure +/// @param Bank: NORSRAM bank number +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void FSMC_NORSRAM_Bank_Init(FSMC_NORSRAM_Bank_InitTypeDef* FSMC_Bank_InitStruct, FSMC_NORSRAM_BANK_TypeDef bank) +{ + // Set FSMC_NORSRAM device timing parameters + if(bank == FSMC_NORSRAM_BANK0) { + FSMC->SMTMGR_SET0 = (u32)(FSMC_Bank_InitStruct->FSMC_SMReadPipe << FSMC_SMTMGR_SET_SM_READ_PIPE_Pos) | \ + (u32)(FSMC_Bank_InitStruct->FSMC_ReadyMode << FSMC_SMTMGR_SET_READ_MODE_Pos) | \ + (u32)(FSMC_Bank_InitStruct->FSMC_WritePeriod << FSMC_SMTMGR_SET_T_WP_Pos) | \ + (u32)(FSMC_Bank_InitStruct->FSMC_WriteHoldTime << FSMC_SMTMGR_SET_T_WR_Pos) | \ + (u32)(FSMC_Bank_InitStruct->FSMC_AddrSetTime << FSMC_SMTMGR_SET_T_AS_Pos) | \ + (u32)(FSMC_Bank_InitStruct->FSMC_ReadPeriod << FSMC_SMTMGR_SET_T_RC_Pos ) ; + FSMC->SMCTLR &= ~FSMC_SMCTLR_SM_DATA_WIDTH_SET0; + FSMC->SMCTLR |= (FSMC_Bank_InitStruct->FSMC_DataWidth) << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos; + } + else if(bank == FSMC_NORSRAM_BANK1) { + FSMC->SMTMGR_SET1 = (u32)(FSMC_Bank_InitStruct->FSMC_SMReadPipe << FSMC_SMTMGR_SET_SM_READ_PIPE_Pos) | \ + (u32)(FSMC_Bank_InitStruct->FSMC_ReadyMode << FSMC_SMTMGR_SET_READ_MODE_Pos) | \ + (u32)(FSMC_Bank_InitStruct->FSMC_WritePeriod << FSMC_SMTMGR_SET_T_WP_Pos) | \ + (u32)(FSMC_Bank_InitStruct->FSMC_WriteHoldTime << FSMC_SMTMGR_SET_T_WR_Pos) | \ + (u32)(FSMC_Bank_InitStruct->FSMC_AddrSetTime << FSMC_SMTMGR_SET_T_AS_Pos) | \ + (u32)(FSMC_Bank_InitStruct->FSMC_ReadPeriod << FSMC_SMTMGR_SET_T_RC_Pos ) ; + FSMC->SMCTLR &= ~FSMC_SMCTLR_SM_DATA_WIDTH_SET1; + FSMC->SMCTLR |= (FSMC_Bank_InitStruct->FSMC_DataWidth) << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos; + } + else if(bank == FSMC_NORSRAM_BANK2) { + FSMC->SMTMGR_SET2 = (u32)(FSMC_Bank_InitStruct->FSMC_SMReadPipe << FSMC_SMTMGR_SET_SM_READ_PIPE_Pos) | \ + (u32)(FSMC_Bank_InitStruct->FSMC_ReadyMode << FSMC_SMTMGR_SET_READ_MODE_Pos) | \ + (u32)(FSMC_Bank_InitStruct->FSMC_WritePeriod << FSMC_SMTMGR_SET_T_WP_Pos) | \ + (u32)(FSMC_Bank_InitStruct->FSMC_WriteHoldTime << FSMC_SMTMGR_SET_T_WR_Pos) | \ + (u32)(FSMC_Bank_InitStruct->FSMC_AddrSetTime << FSMC_SMTMGR_SET_T_AS_Pos) | \ + (u32)(FSMC_Bank_InitStruct->FSMC_ReadPeriod << FSMC_SMTMGR_SET_T_RC_Pos ) ; + FSMC->SMCTLR &= ~FSMC_SMCTLR_SM_DATA_WIDTH_SET2; + FSMC->SMCTLR |= (FSMC_Bank_InitStruct->FSMC_DataWidth) << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos; + } +} + + + + +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_gpio.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_gpio.c new file mode 100644 index 000000000..4363338f3 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_gpio.c @@ -0,0 +1,344 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_gpio.c +/// @author AE TEAM +/// @brief THIS FILE PROVIDES ALL THE GPIO FIRMWARE FUNCTIONS. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#define _HAL_GPIO_C_ + +// Files includes +#include "reg_exti.h" +#include "hal_rcc.h" +#include "hal_gpio.h" + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup GPIO_HAL +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup GPIO_Exported_Functions +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Deinitializes the gpio peripheral registers to their default reset +/// values. +/// @param gpio: select the GPIO peripheral. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void GPIO_DeInit(GPIO_TypeDef* gpio) +{ + switch (*(vu32*)&gpio) { + case (u32)GPIOA: + RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOA, DISABLE); + break; + case (u32)GPIOB: + RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOB, DISABLE); + break; + case (u32)GPIOC: + RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOC, DISABLE); + break; + case (u32)GPIOD: + RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOD, DISABLE); + break; + case (u32)GPIOE: + RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOE, DISABLE); + break; + default: + break; + } +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Deinitializes the Alternate Functions (remap, event control +/// and EXTI configuration) registers to their default reset values. +/// @param None. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void GPIO_AFIODeInit() +{ + GPIOA->AFRL = 0xFFFFFFFF; + GPIOA->AFRH = 0xF00FFFFF; // PA14:SWCLK, PA13:PSWDIO + GPIOB->AFRL = 0xFFFFFFFF; + GPIOB->AFRH = 0xFFFFFFFF; + GPIOC->AFRL = 0xFFFFFFFF; + GPIOC->AFRH = 0xFFFFFFFF; + GPIOD->AFRL = 0xFFFFFFFF; + GPIOD->AFRH = 0xFFFFFFFF; + GPIOE->AFRL = 0xFFFFFFFF; + GPIOE->AFRH = 0xFFFFFFFF; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Initializes the gpio peripheral according to the specified +/// parameters in the init_struct. +/// @param gpio: select the GPIO peripheral. +/// @param init_struct: pointer to a GPIO_InitTypeDef structure that +/// contains the configuration information for the specified GPIO +/// peripheral. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void GPIO_Init(GPIO_TypeDef* gpio, GPIO_InitTypeDef* init_struct) +{ + u8 idx; + u8 i; + u32 tmp; + __IO u32* reg ; + + // 1x + u32 dat = init_struct->GPIO_Mode & 0x0F; + if (init_struct->GPIO_Mode & 0x10) + dat |= init_struct->GPIO_Speed; + + // 0x + reg = &gpio->CRL; + for (i = 0; i < 8; i++) { + idx = i * 4; + if ((init_struct->GPIO_Pin) & (1 << i)) { + *reg = (*reg & ~(0xF << idx)) | (dat << idx); + } + } + + reg = &gpio->CRH; + tmp = init_struct->GPIO_Pin >> 8; + for (i = 0; i < 8; i++) { + idx = i * 4; + if (tmp & (1 << i)) { + *reg = (*reg & ~(0xF << idx)) | (dat << idx); + } + } + + // 2x,4x + if (init_struct->GPIO_Mode == GPIO_Mode_IPD) + gpio->BRR |= init_struct->GPIO_Pin; + else if (init_struct->GPIO_Mode == GPIO_Mode_IPU) + gpio->BSRR |= init_struct->GPIO_Pin; +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Fills each init_struct member with its default value. +/// @param init_struct : pointer to a GPIO_InitTypeDef structure +/// which will be initialized. +/// @retval : None +//////////////////////////////////////////////////////////////////////////////// +void GPIO_StructInit(GPIO_InitTypeDef* init_struct) +{ + // Reset GPIO init structure parameters values + init_struct->GPIO_Pin = GPIO_Pin_All; + init_struct->GPIO_Speed = GPIO_Speed_2MHz; + init_struct->GPIO_Mode = GPIO_Mode_FLOATING; +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Reads the input data of specified GPIO port pin. +/// @param gpio: select the GPIO peripheral. +/// @param pin: specifies the port pin to be read. +/// This parameter can be GPIO_Pin_x where x can be (0..15). +/// @retval The input port pin value. +//////////////////////////////////////////////////////////////////////////////// +bool GPIO_ReadInputDataBit(GPIO_TypeDef* gpio, u16 pin) +{ + return ((gpio->IDR & pin)) ? Bit_SET : Bit_RESET; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Reads all GPIO port pins input data. +/// @param gpio: select the GPIO peripheral. +/// @retval GPIO port input data value. +//////////////////////////////////////////////////////////////////////////////// +u16 GPIO_ReadInputData(GPIO_TypeDef* gpio) +{ + return gpio->IDR; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Reads the output data of specified GPIO port pin. +/// @param gpio: select the GPIO peripheral. +/// @param pin: specifies the port bit to be read. +/// This parameter can be GPIO_Pin_x where x can be (0..15). +/// @retval The output port pin value. +//////////////////////////////////////////////////////////////////////////////// +bool GPIO_ReadOutputDataBit(GPIO_TypeDef* gpio, u16 pin) +{ + return (gpio->ODR & pin) ? Bit_SET : Bit_RESET; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Reads all GPIO port pins output data. +/// @param gpio: select the GPIO peripheral. +/// @retval GPIO port output data value. +//////////////////////////////////////////////////////////////////////////////// +u16 GPIO_ReadOutputData(GPIO_TypeDef* gpio) +{ + return gpio->ODR; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Sets the selected GPIO port pin. +/// @param gpio: where x can be (A..D) to select the GPIO peripheral. +/// @param pin: specifies the port pins to be written. +/// This parameter can be any combination of GPIO_Pin_x where x can be +/// (0..15). +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void GPIO_SetBits(GPIO_TypeDef* gpio, u16 pin) +{ + gpio->BSRR = pin; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Clears the selected GPIO port bit. +/// @param gpio: where x can be (A..D) to select the GPIO peripheral. +/// @param pin: specifies the port pins to be written. +/// This parameter can be any combination of GPIO_Pin_x where x can be +/// (0..15). +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void GPIO_ResetBits(GPIO_TypeDef* gpio, u16 pin) +{ + gpio->BRR = pin; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Sets or clears the selected GPIO port pin. +/// @param gpio: select the GPIO peripheral. +/// @param pin: specifies the port bit to be written. +/// This parameter can be one of GPIO_Pin_x where x can be (0..15). +/// @param value: specifies the value to be written to the selected bit. +/// This parameter can be one of the BitAction enum values: +/// @arg Bit_RESET: to clear the port pin +/// @arg Bit_SET: to set the port pin +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void GPIO_WriteBit(GPIO_TypeDef* gpio, u16 pin, BitAction value) +{ + (value) ? (gpio->BSRR = pin) : (gpio->BRR = pin); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Writes data to all GPIO port pins. +/// @param gpio: where x can be (A..D) to select the GPIO peripheral. +/// @param value: specifies the value to be written to the port output data +/// register. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void GPIO_Write(GPIO_TypeDef* gpio, u16 value) +{ + gpio->ODR = value; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Locks GPIO Pins configuration. +/// @param gpio: to select the GPIO peripheral. +/// @param pin: specifies the port bit to be written. +/// This parameter can be any combination of GPIO_Pin_x where x can be +/// (0..15). +/// @param state: new lock state of the port pin. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void GPIO_PinLock(GPIO_TypeDef* gpio, u16 pin, FunctionalState state) +{ + (state) ? (gpio->LCKR |= pin) : (gpio->LCKR &= ~pin); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Locks GPIO Pins configuration registers until next system reset. +/// @param gpio: to select the GPIO peripheral. +/// @param pin: specifies the port bit to be written. +/// This parameter can be any combination of GPIO_Pin_x where x can be +/// (0..15). +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void GPIO_PinLockConfig(GPIO_TypeDef* gpio, u16 pin) +{ + gpio->LCKR = GPIO_LCKR_LCKK | pin; + gpio->LCKR = pin; + gpio->LCKR = GPIO_LCKR_LCKK | pin; + gpio->LCKR; + gpio->LCKR; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the port pin remapping. +/// @param remap: selects the pin to remap. +/// @param mask: the corresponding remapping mask of the remapping pin. +/// @param state: new state of the port pin remapping. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Writes data to the specified GPIO data port. +/// @param gpio: select the GPIO peripheral. +/// @param pin: specifies the pin for the Alternate function. +/// This parameter can be GPIO_PinSourcex where x can be (0..15) for +/// GPIOA, GPIOB, GPIOD and (0..12) for GPIOC . +/// @param alternate_function: selects the pin to used as Alternate function. +/// This parameter can be the GPIO_AF_x where x can be (0..7). +/// @note The pin should be used for Digital IP. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void GPIO_PinAFConfig(GPIO_TypeDef* gpio, u8 pin, u8 alternate_function) +{ + u8 shift = (pin & 0x07) * 4; + u32* ptr = (pin < 8) ? (u32*)&gpio->AFRL : (u32*)&gpio->AFRH; + *ptr = (*ptr & ~(0x0F << shift)) | (alternate_function << shift); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Set the remap function and AF function of the GPIO pin. +/// @param gpio:select the GPIO peripheral. +/// @param pin: specifies the pin for the Alternate function. +/// This parameter can be GPIO_Pin_x where x can be (0..15) for +/// GPIOA, GPIOB, GPIOD and (0..12) for GPIOC . +/// @param remap: selects the pin to remap. +/// @param alternate_function: selects the pin to used as Alternate function. +/// This parameter can be the GPIO_AF_x where x can be (0..7). +/// @note The pin should be used for Digital IP. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void exGPIO_PinAFConfig(GPIO_TypeDef* gpio, u16 pin, s32 remap, s8 alternate_function) +{ + u8 i; + u8 shift; + u32* ptr; + + if (alternate_function >= 0) { + for (i = 0; i < 32; i++) { + if (pin & 0x01) { + pin = i; + break; + } + pin >>= 1; + } + + shift = (pin & 0x07) * 4; + ptr = (pin < 8) ? (u32*)&gpio->AFRL : (u32*)&gpio->AFRH; + *ptr = (*ptr & ~(0x0F << shift)) | (alternate_function << shift); + } +} + + +/// @} + +/// @} + +/// @} + diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_i2c.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_i2c.c new file mode 100644 index 000000000..855236a63 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_i2c.c @@ -0,0 +1,526 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_i2c.c +/// @author AE TEAM +/// @brief THIS FILE PROVIDES ALL THE I2C FIRMWARE FUNCTIONS. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#define _HAL_I2C_C_ + +// Files includes +#include "hal_i2c.h" +#include "hal_rcc.h" + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup I2C_HAL +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup I2C_Exported_Functions +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Deinitializes the i2c peripheral registers to their default +/// reset values. +/// @param i2c: where n can be 1 or 2 to select the I2C peripheral. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void I2C_DeInit(I2C_TypeDef* i2c) +{ + switch (*(vu32*)&i2c) { + case (u32)I2C1: // I2C1_BASE: + exRCC_APB1PeriphReset(RCC_APB1ENR_I2C1); + break; + case (u32)I2C2: // I2C2_BASE: + exRCC_APB1PeriphReset(RCC_APB1ENR_I2C2); + break; + default: + break; + } +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Initializes the i2c peripheral according to the specified +/// parameters in the init_struct. +/// @param i2c: select the I2C peripheral. +/// @param init_struct: pointer to a I2C_InitTypeDef structure that +/// contains the configuration information for the specified +/// I2C peripheral. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void I2C_Init(I2C_TypeDef* i2c, I2C_InitTypeDef* init_struct) +{ + u32 pclk1 = HSI_VALUE; + u32 minSclLowTime = 0; + u32 i2cPeriod = 0; + u32 pclk1Period = 0; + + + i2c->IC_ENABLE &= ~I2C_ENR_ENABLE; + + + pclk1 = RCC_GetPCLK1Freq(); + pclk1Period = 1000000000 / pclk1; + i2cPeriod = 1000000000 / init_struct->I2C_ClockSpeed; + + minSclLowTime = pclk1 / init_struct->I2C_ClockSpeed ; + i2cPeriod = 82 / pclk1Period; + + if (init_struct->I2C_ClockSpeed <= 100000) { + i2c->IC_SS_SCL_LCNT = (minSclLowTime - 13 - i2cPeriod) / 2; + i2c->IC_SS_SCL_HCNT = (minSclLowTime - 13 - i2cPeriod - i2c->IC_SS_SCL_LCNT); + } + else { + i2c->IC_FS_SCL_LCNT = (minSclLowTime - 13 - i2cPeriod ) / 2 + 4; + i2c->IC_FS_SCL_HCNT = (minSclLowTime - 13 - i2c->IC_FS_SCL_LCNT - i2cPeriod); + } + + i2c->IC_CON &= ~(I2C_CR_EMPINT | \ + I2C_CR_SLAVEDIS | \ + I2C_CR_REPEN | \ + I2C_CR_MASTER10 | \ + I2C_CR_SLAVE10 | \ + I2C_CR_FAST | \ + I2C_CR_MASTER); + + i2c->IC_CON = I2C_CR_EMPINT | \ + I2C_CR_REPEN | \ + ((init_struct->I2C_Speed == I2C_CR_FAST) ? I2C_CR_FAST : I2C_CR_STD) | \ + ((init_struct->I2C_Mode) ? I2C_CR_MASTER : 0x00); + i2c->IC_INTR_MASK &= INTR_MASK; + + i2c->IC_RX_TL = 0x00; + i2c->IC_TX_TL = 0x00; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Fills each init_struct member with its default value. +/// @param init_struct: pointer to an I2C_InitTypeDef structure +/// which will be initialized. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void I2C_StructInit(I2C_InitTypeDef* init_struct) +{ + init_struct->I2C_Mode = I2C_CR_MASTER; + init_struct->I2C_OwnAddress = I2C_OWN_ADDRESS; + init_struct->I2C_Speed = I2C_CR_STD; + init_struct->I2C_ClockSpeed = 100000; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the specified I2C peripheral. +/// @param i2c: select the I2C peripheral. +/// @param state: new state of the i2c peripheral. This parameter +/// can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void I2C_Cmd(I2C_TypeDef* i2c, FunctionalState state) +{ + (state) ? (i2c->IC_ENABLE |= I2C_ENR_ENABLE) : (i2c->IC_ENABLE &= ~I2C_ENR_ENABLE); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the specified I2C DMA requests. +/// @param i2c: select the I2C peripheral. +/// @param state: new state of the I2C DMA transfer. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void I2C_DMACmd(I2C_TypeDef* i2c, FunctionalState state) +{ + if (state) { + if (I2C_DMA_DIR == TDMAE_SET) + i2c->IC_DMA_CR |= TDMAE_SET; + + else + i2c->IC_DMA_CR |= RDMAE_SET; + } + else + i2c->IC_DMA_CR &= ~(I2C_DMA_RXEN | I2C_DMA_TXEN); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Generates i2c communication START condition. +/// @param i2c: select the I2C peripheral. +/// @param state: new state of the I2C START condition generation. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void I2C_GenerateSTART(I2C_TypeDef* i2c, FunctionalState state) +{ + (state) ? (i2c->IC_CON |= I2C_CR_REPEN) : (i2c->IC_CON &= ~I2C_CR_REPEN); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Generates i2c communication STOP condition. +/// @param i2c: select the I2C peripheral. +/// @param state: new state of the I2C STOP condition generation. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void I2C_GenerateSTOP(I2C_TypeDef* i2c, FunctionalState state) +{ + u16 overTime = 3000; + + i2c->IC_ENABLE |= I2C_ENR_ABORT; + + while (i2c->IC_ENABLE & I2C_ENR_ABORT) { + if (overTime-- == 0) + break; + } + i2c->IC_CLR_TX_ABRT; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the specified I2C own address2. +/// @param i2c: select the I2C peripheral. +/// @param addr: specifies the 7bit I2C own address2. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void I2C_OwnAddress2Config(I2C_TypeDef* i2c, u8 addr) +{ + MODIFY_REG(i2c->IC_TAR, (u16)I2C_TAR_ADDR, (u16)(addr >> 1)); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the specified I2C dual addressing mode. +/// @param i2c: select the I2C peripheral. +/// @param state: new state of the I2C dual addressing mode. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void I2C_DualAddressCmd(I2C_TypeDef* i2c, FunctionalState state) +{ + (state) ? (i2c->IC_TAR |= IC_TAR_ENDUAL_Set) : (i2c->IC_TAR &= IC_TAR_ENDUAL_Reset); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the specified I2C general call feature. +/// @param i2c: select the I2C peripheral. +/// @param state: new state of the I2C General call. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void I2C_GeneralCallCmd(I2C_TypeDef* i2c, FunctionalState state) +{ + (state) ? (i2c->IC_TAR |= I2C_TAR_SPECIAL) : (i2c->IC_TAR &= ~I2C_TAR_SPECIAL); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the specified I2C interrupts. +/// @param i2c: select the I2C peripheral. +/// @param it: specifies the I2C interrupts sources to be enabled +/// or disabled. +/// This parameter can be any combination of the following values: +/// @arg I2C_IT_RX_UNDER : Rx Buffer is empty interrupt mask +/// @arg I2C_IT_RX_OVER : RX Buffer Overrun interrupt mask +/// @arg I2C_IT_RX_FULL : Rx buffer full interrupt mask +/// @arg I2C_IT_TX_OVER : TX Buffer Overrun interrupt mask +/// @arg I2C_IT_TX_EMPTY : TX_FIFO empty interrupt mask +/// @arg I2C_IT_RD_REQ : I2C work as slave or master interrupt mask +/// @arg I2C_IT_TX_ABRT : TX error interrupt mask(Master mode) +/// @arg I2C_IT_RX_DONE : Master not ack interrupt mask(slave mode) +/// @arg I2C_IT_ACTIVITY : I2C activity interrupt mask +/// @arg I2C_IT_STOP_DET : stop condition interrupt mask +/// @arg I2C_IT_START_DET : start condition interrupt mask +/// @arg I2C_IT_GEN_CALL : a general call address and ack interrupt mask +/// @param state: new state of the specified I2C interrupts. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void I2C_ITConfig(I2C_TypeDef* i2c, u16 it, FunctionalState state) +{ + if (it == I2C_IT_RX_FULL) + I2C_ReadCmd(i2c); + (state) ? SET_BIT(i2c->IC_INTR_MASK, it) : CLEAR_BIT(i2c->IC_INTR_MASK, (u16)it); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Sends a data byte through the i2c peripheral. +/// @param i2c: select the I2C peripheral. +/// @param dat: Byte to be transmitted.. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void I2C_SendData(I2C_TypeDef* i2c, u8 dat) +{ + i2c->IC_DATA_CMD = dat; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Returns the most recent received data by the i2c peripheral. +/// @param i2c: select the I2C peripheral. +/// @retval The value of the received data. +//////////////////////////////////////////////////////////////////////////////// +void I2C_ReadCmd(I2C_TypeDef* i2c) +{ + i2c->IC_DATA_CMD = I2C_DR_CMD; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Returns the most recent received data by the i2c peripheral. +/// @param i2c: select the I2C peripheral. +/// @retval The value of the received data. +//////////////////////////////////////////////////////////////////////////////// +u8 I2C_ReceiveData(I2C_TypeDef* i2c) +{ + I2C_CMD_DIR = 0; + return (u8)i2c->IC_DATA_CMD; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Transmits the address byte to select the slave device. +/// @param i2c: select the I2C peripheral. +/// @param addr: specifies the slave address which will be transmitted +/// @param dir: specifies whether the I2C device will be a +/// Transmitter or a Receiver. +/// This parameter can be one of the following values +/// @arg I2C_Direction_Transmitter: Transmitter mode +/// @arg I2C_Direction_Receiver: Receiver mode +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void I2C_Send7bitAddress(I2C_TypeDef* i2c, u8 addr, u8 dir) +{ + i2c->IC_TAR = addr >> 1; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Reads the specified I2C register and returns its value. +/// @param i2c: select the I2C peripheral. +/// @param reg: specifies the register to read. +/// This parameter can be one of the following values: +/// @retval The value of the read register. +//////////////////////////////////////////////////////////////////////////////// +u16 I2C_ReadRegister(I2C_TypeDef* i2c, u8 reg) +{ + return (*(vu16*)(*((u32*)&i2c) + reg)); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Returns the last i2c Event. +/// @param i2c: select the I2C peripheral. +/// @retval The last event +//////////////////////////////////////////////////////////////////////////////// +u32 I2C_GetLastEvent(I2C_TypeDef* i2c) +{ + return (u32)i2c->IC_RAW_INTR_STAT & FLAG_Mask; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Checks whether the last i2c Event is equal to the one passed +/// as parameter. +/// @param i2c: select the I2C peripheral. +/// @param event: specifies the event to be checked. +/// This parameter can be one of the following values: +/// @arg I2C_EVENT_RX_UNDER : Rx Buffer is empty event +/// @arg I2C_EVENT_RX_OVER : RX Buffer Overrun event +/// @arg I2C_EVENTT_RX_FULL : Rx buffer full event +/// @arg I2C_EVENT_TX_OVER : TX Buffer Overrun event +/// @arg I2C_EVENT_TX_EMPTY : TX_FIFO empty event +/// @arg I2C_EVENT_RD_REQ : I2C work as slave or master event +/// @arg I2C_EVENT_TX_ABRT : TX error event(Master mode) +/// @arg I2C_EVENT_RX_DONE : Master not ack event(slave mode) +/// @arg I2C_EVENT_ACTIVITY : I2C activity event +/// @arg I2C_EVENT_STOP_DET : stop condition event +/// @arg I2C_EVENT_START_DET: start condition event +/// @arg I2C_EVENT_GEN_CALL : a general call address and ack event +/// - SUCCESS: Last event is equal to the I2C_EVENT +/// - ERROR: Last event is different from the I2C_EVENT +//////////////////////////////////////////////////////////////////////////////// +ErrorStatus I2C_CheckEvent(I2C_TypeDef* i2c, u32 event) +{ + if ((event == I2C_EVENT_RX_FULL) && (I2C_CMD_DIR == 0)) { + i2c->IC_DATA_CMD = I2C_DR_CMD; + I2C_CMD_DIR = 1; + } + + return (ErrorStatus)((i2c->IC_RAW_INTR_STAT & event) == event); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Checks whether the specified I2C flag is set or not. +/// @param i2c: select the I2C peripheral. +/// @param flag: specifies the flag to check. +/// This parameter can be one of the following values: +/// @arg I2C_FLAG_RX_UNDER : Rx Buffer is empty flag +/// @arg I2C_FLAG_RX_OVER : RX Buffer Overrun flag +/// @arg I2C_FLAG_RX_FULL : Rx buffer full flag +/// @arg I2C_FLAG_TX_OVER : TX Buffer Overrun flag +/// @arg I2C_FLAG_TX_EMPTY : TX_FIFO empty flag +/// @arg I2C_FLAG_RD_REQ : I2C work as slave or master flag +/// @arg I2C_FLAG_TX_ABRT : TX error flag(Master mode) +/// @arg I2C_FLAG_RX_DONE : Master not ack flag(slave mode) +/// @arg I2C_FLAG_ACTIVITY : I2C activity flag +/// @arg I2C_FLAG_STOP_DET : stop condition flag +/// @arg I2C_FLAG_START_DET: start condition flag +/// @arg I2C_FLAG_GEN_CALL : a general call address and ack flag +/// @retval The new state of I2C_FLAG (SET or RESET). +//////////////////////////////////////////////////////////////////////////////// +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* i2c, u32 flag) +{ + if (flag & 0x8000) + return ((i2c->IC_STATUS & flag) ? SET : RESET); + + if ((flag == I2C_FLAG_RX_FULL) && (I2C_CMD_DIR == 0)) { + i2c->IC_DATA_CMD = I2C_DR_CMD; + I2C_CMD_DIR = 1; + } + return (((i2c->IC_RAW_INTR_STAT & flag)) ? SET : RESET); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Clears the i2c's pending flags. +/// @param i2c: select the I2C peripheral. +/// @param flag: specifies the flag to clear. +/// This parameter can be any combination of the following values: +/// @arg I2C_FLAG_RX_UNDER : Rx Buffer is empty flag +/// @arg I2C_FLAG_RX_OVER : RX Buffer Overrun flag +/// @arg I2C_FLAG_RX_FULL : Rx buffer full flag +/// @arg I2C_FLAG_TX_OVER : TX Buffer Overrun flag +/// @arg I2C_FLAG_TX_EMPTY : TX_FIFO empty flag +/// @arg I2C_FLAG_RD_REQ : I2C work as slave or master flag +/// @arg I2C_FLAG_TX_ABRT : TX error flag(Master mode) +/// @arg I2C_FLAG_RX_DONE : Master not ack flag(slave mode) +/// @arg I2C_FLAG_ACTIVITY : I2C activity flag +/// @arg I2C_FLAG_STOP_DET : stop condition flag +/// @arg I2C_FLAG_START_DET: start condition flag +/// @arg I2C_FLAG_GEN_CALL : a general call address and ack flag +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void I2C_ClearFlag(I2C_TypeDef* i2c, u32 flag) +{ + if ((flag & I2C_FLAG_RX_UNDER) == I2C_FLAG_RX_UNDER) + i2c->IC_CLR_RX_UNDER; + if ((flag & I2C_FLAG_RX_OVER) == I2C_FLAG_RX_OVER) + i2c->IC_CLR_RX_OVER; + if ((flag & I2C_FLAG_TX_OVER) == I2C_FLAG_TX_OVER) + i2c->IC_CLR_TX_OVER; + if ((flag & I2C_FLAG_RD_REQ) == I2C_FLAG_RD_REQ) + i2c->IC_CLR_RD_REQ; + if ((flag & I2C_FLAG_TX_ABRT) == I2C_FLAG_TX_ABRT) + i2c->IC_CLR_TX_ABRT; + if ((flag & I2C_FLAG_RX_DONE) == I2C_FLAG_RX_DONE) + i2c->IC_CLR_RX_DONE; + if ((flag & I2C_FLAG_ACTIVITY) == I2C_FLAG_ACTIVITY) + i2c->IC_CLR_ACTIVITY; + if ((flag & I2C_FLAG_STOP_DET) == I2C_FLAG_STOP_DET) + i2c->IC_CLR_STOP_DET; + if ((flag & I2C_FLAG_START_DET) == I2C_FLAG_START_DET) + i2c->IC_CLR_START_DET; + if ((flag & I2C_FLAG_GEN_CALL) == I2C_FLAG_GEN_CALL) + i2c->IC_CLR_GEN_CALL; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Checks whether the specified I2C interrupt has occurred or not. +/// @param i2c: select the I2C peripheral. +/// @param it: specifies the interrupt source to check. +/// This parameter can be one of the following values: +/// @arg I2C_IT_RX_UNDER : Rx Buffer is empty interrupt +/// @arg I2C_IT_RX_OVER : RX Buffer Overrun interrupt +/// @arg I2C_IT_RX_FULL : Rx buffer full interrupt +/// @arg I2C_IT_TX_OVER : TX Buffer Overrun interrupt +/// @arg I2C_IT_TX_EMPTY : TX_FIFO empty interrupt +/// @arg I2C_IT_RD_REQ : I2C work as slave or master interrupt +/// @arg I2C_IT_TX_ABRT : TX error interrupt (Master mode) +/// @arg I2C_IT_RX_DONE : Master not ack interrupt (slave mode) +/// @arg I2C_IT_ACTIVITY : I2C activity interrupt +/// @arg I2C_IT_STOP_DET : stop condition interrupt +/// @arg I2C_IT_START_DET: start condition interrupt +/// @arg I2C_IT_GEN_CALL : a general call address and ack interrupt +/// @retval The new state of I2C_IT (SET or RESET). +//////////////////////////////////////////////////////////////////////////////// +ITStatus I2C_GetITStatus(I2C_TypeDef* i2c, u32 it) +{ + return ((i2c->IC_RAW_INTR_STAT & it) ? SET : RESET); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Clears the i2c interrupt pending bits. +/// @param i2c: select the I2C peripheral. +/// @param it: specifies the interrupt pending bit to clear. +/// This parameter can be any combination of the following values: +/// @arg I2C_IT_RX_UNDER : Rx Buffer is empty interrupt +/// @arg I2C_IT_RX_OVER : RX Buffer Overrun interrupt +/// @arg I2C_IT_RX_FULL : Rx buffer full interrupt +/// @arg I2C_IT_TX_OVER : TX Buffer Overrun interrupt +/// @arg I2C_IT_TX_EMPTY : TX_FIFO empty interrupt +/// @arg I2C_IT_RD_REQ : I2C work as slave or master interrupt +/// @arg I2C_IT_TX_ABRT : TX error interrupt (Master mode) +/// @arg I2C_IT_RX_DONE : Master not ack interrupt (slave mode) +/// @arg I2C_IT_ACTIVITY : I2C activity interrupt +/// @arg I2C_IT_STOP_DET : stop condition interrupt +/// @arg I2C_IT_START_DET: start condition interrupt +/// @arg I2C_IT_GEN_CALL : a general call address and ack interrupt +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void I2C_ClearITPendingBit(I2C_TypeDef* i2c, u32 it) +{ + if ((it & I2C_IT_RX_UNDER) == I2C_FLAG_RX_UNDER) + i2c->IC_CLR_RX_UNDER; + if ((it & I2C_IT_RX_OVER) == I2C_FLAG_RX_OVER) + i2c->IC_CLR_RX_OVER; + if ((it & I2C_IT_TX_OVER) == I2C_FLAG_TX_OVER) + i2c->IC_CLR_TX_OVER; + if ((it & I2C_IT_RD_REQ) == I2C_FLAG_RD_REQ) + i2c->IC_CLR_RD_REQ; + if ((it & I2C_IT_TX_ABRT) == I2C_FLAG_TX_ABRT) + i2c->IC_CLR_TX_ABRT; + if ((it & I2C_IT_RX_DONE) == I2C_FLAG_RX_DONE) + i2c->IC_CLR_RX_DONE; + if ((it & I2C_IT_ACTIVITY) == I2C_FLAG_ACTIVITY) + i2c->IC_CLR_ACTIVITY; + if ((it & I2C_IT_STOP_DET) == I2C_FLAG_STOP_DET) + i2c->IC_CLR_STOP_DET; + if ((it & I2C_IT_START_DET) == I2C_FLAG_START_DET) + i2c->IC_CLR_START_DET; + if ((it & I2C_IT_GEN_CALL) == I2C_FLAG_GEN_CALL) + i2c->IC_CLR_GEN_CALL; +} + +//////////////////////////////////////////////////////////////////////////////// +// +// New Function Interface +// +//////////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures slave address. +/// @param i2c: select the I2C peripheral. +/// @param addr: specifies the slave address which will be transmitted +/// This parameter can be one of the following values +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void I2C_SendSlaveAddress(I2C_TypeDef* i2c, u8 addr) +{ + WRITE_REG(i2c->IC_SAR, addr >> 1); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the I2C slave mode. +/// @param i2c: select the I2C peripheral. +/// @param state: new state of the specified I2C interrupts. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void I2C_SlaveConfigure(I2C_TypeDef* i2c, FunctionalState state) +{ + (state) ? CLEAR_BIT(i2c->IC_CON, I2C_CR_SLAVEDIS) : SET_BIT(i2c->IC_CON, I2C_CR_SLAVEDIS); +} +/// @} + +/// @} + +/// @} diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_iwdg.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_iwdg.c new file mode 100644 index 000000000..06b49fb24 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_iwdg.c @@ -0,0 +1,208 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_iwdg.c +/// @author AE TEAM +/// @brief THIS FILE PROVIDES ALL THE IWDG FIRMWARE FUNCTIONS. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#define _HAL_IWDG_C_ + +// Files includes +#include "hal_iwdg.h" + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup IWDG_HAL +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup IWDG_Exported_Functions +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables write access to IWDG_PR and IWDG_RLR +/// registers. +/// @param write_access: new state of write access to IWDG_PR and +/// IWDG_RLR registers. +/// This parameter can be one of the following values: +/// @arg IWDG_WriteAccess_Enable: Enable write access to +/// IWDG_PR and IWDG_RLR registers +/// @arg IWDG_WriteAccess_Disable: Disable write access to +/// IWDG_PR and IWDG_RLR registers +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void IWDG_WriteAccessCmd(u16 write_access) +{ + IWDG->KR = write_access; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Sets IWDG Prescaler value. +/// @param prescaler: specifies the IWDG Prescaler value. +/// This parameter can be one of the following values: +/// @arg IWDG_Prescaler_4: IWDG prescaler set to 4 +/// @arg IWDG_Prescaler_8: IWDG prescaler set to 8 +/// @arg IWDG_Prescaler_16: IWDG prescaler set to 16 +/// @arg IWDG_Prescaler_32: IWDG prescaler set to 32 +/// @arg IWDG_Prescaler_64: IWDG prescaler set to 64 +/// @arg IWDG_Prescaler_128: IWDG prescaler set to 128 +/// @arg IWDG_Prescaler_256: IWDG prescaler set to 256 +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void IWDG_SetPrescaler(u8 prescaler) +{ + IWDG->PR = prescaler; + PVU_CheckStatus(); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Set IWDG reload value. +/// @param reload: specifies the IWDG reload value. +/// This parameter must be a number between 0 and 0x0FFF. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void IWDG_SetReload(u16 reload) +{ + IWDG->RLR = reload; + RVU_CheckStatus(); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Get IWDG reload value. +/// @param None. +/// @retval reload: specifies the IWDG reload value. +//////////////////////////////////////////////////////////////////////////////// +u32 IWDG_GetReload(void) +{ + return IWDG->RLR; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Reloads IWDG counter with value defined in the reload register +/// (write access to IWDG_PR and IWDG_RLR registers disabled). +/// @param None. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void IWDG_ReloadCounter(void) +{ + IWDG->KR = KR_KEY_Reload; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers +/// disabled). +/// @param None. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void IWDG_Enable(void) +{ + IWDG->KR = KR_KEY_Enable; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Checks whether the specified IWDG flag is set or not. +/// @param flag: specifies the flag to check. +/// This parameter can be one of the following values: +/// @arg IWDG_FLAG_PVU: Prescaler Value Update on going +/// @arg IWDG_FLAG_RVU: reload Value Update on going +/// @retval The new state of flag (SET or RESET). +//////////////////////////////////////////////////////////////////////////////// +FlagStatus IWDG_GetFlagStatus(u16 flag) +{ + return ((IWDG->SR & flag) != (u32)RESET) ? SET : RESET; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Checks prescaler value has been updated. +/// @param None. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void PVU_CheckStatus(void) +{ + while (IWDG_GetFlagStatus(IWDG_FLAG_PVU) == SET); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Checks count relead value has been updated. +/// @param None. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RVU_CheckStatus(void) +{ + while (IWDG_GetFlagStatus(IWDG_FLAG_RVU) == SET); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief IWDG overflow configuration. +/// @param overflow_config +/// @arg IWDG_Overflow_Interrupt: Interrupt after overflow. +/// @arg IWDG_Overflow_Reset: Reset after overflow. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void IWDG_OverflowConfig(IWDGOverflowConfig_TypeDef overflow_config) +{ + IWDG->CR &= ~IWDG_CR_IRQSEL; + IWDG->CR |= overflow_config; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Clear interrupt flag +/// @param None. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void IWDG_ClearITPendingBit(void) +{ + IWDG->CR |= IWDG_CR_IRQCLR;//write 1 clear interrupt Flag +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Clear interrupt flag +/// @param None. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void IWDG_ClearIT(void) +{ + IWDG->CR |= IWDG_CR_IRQCLR;//write 1 clear interrupt Flag +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enable IWDG interrupt function +/// @param None. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void IWDG_EnableIT(void) +{ + IWDG->CR |= IWDG_CR_IRQSEL; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Disable IWDG interrupt function +/// @param None. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void IWDG_Reset(void) +{ + IWDG->CR &= ~IWDG_CR_IRQSEL; +} + + + +/// @} + +/// @} + +/// @} diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_misc.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_misc.c new file mode 100644 index 000000000..598d6d07e --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_misc.c @@ -0,0 +1,147 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_misc.c +/// @author AE TEAM +/// @brief THIS FILE PROVIDES ALL THE MSIC FIRMWARE FUNCTIONS. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#define _HAL_MISC_C_ + +// Files includes +#include "hal_misc.h" + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MSIC_HAL +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MISC_Exported_Functions +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Set the NVIC interrupt vector table. +/// @param vect_tab +/// This parameter can be any combination of the following values: +/// @arg NVIC_VectTab_RAM +/// @arg NVIC_VectTab_FLASH +/// @param offset +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void NVIC_SetVectorTable(u32 vect_tab, u32 offset) +{ + SCB->VTOR = vect_tab | (offset & (u32)0x1FFFFF80); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Set the NVIC interrupt priority group. +/// @param priority_group +/// This parameter can be any combination of the following values: +/// @arg NVIC_PriorityGroup_0 +/// @arg NVIC_PriorityGroup_1 +/// @arg NVIC_PriorityGroup_2 +/// @arg NVIC_PriorityGroup_3 +/// @arg NVIC_PriorityGroup_4 +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void NVIC_PriorityGroupConfig(u32 priority_group) +{ + SCB->AIRCR = AIRCR_VECTKEY_MASK | priority_group; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief NVIC initialization. +/// @param init_struct +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void NVIC_Init(NVIC_InitTypeDef* init_struct) +{ + if (init_struct->NVIC_IRQChannelCmd != DISABLE) { + u32 pri = (SCB_AIRCR_PRIGROUP & ~(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk)) >> SCB_AIRCR_PRIGROUP_Pos; + + pri = (((u32)init_struct->NVIC_IRQChannelPreemptionPriority << (0x4 - pri)) | + (init_struct->NVIC_IRQChannelSubPriority & (0x0F >> pri))) + << 0x04; + + NVIC->IP[init_struct->NVIC_IRQChannel] = pri; + NVIC->ISER[init_struct->NVIC_IRQChannel >> 0x05] = 0x01 << (init_struct->NVIC_IRQChannel & 0x1F); + } + else { + NVIC->ICER[init_struct->NVIC_IRQChannel >> 0x05] = 0x01 << (init_struct->NVIC_IRQChannel & 0x1F); + } + +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief NVIC initialized extension function. +/// @param init_struct +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void exNVIC_Init(exNVIC_Init_TypeDef* init_struct) +{ + u32 pri; + + if (init_struct->NVIC_IRQChannelCmd != DISABLE) { + pri = (SCB_AIRCR_PRIGROUP & ~(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk)) >> SCB_AIRCR_PRIGROUP_Pos; + + pri = (((u32)init_struct->NVIC_IRQChannelPreemptionPriority << (0x4 - pri)) | + (init_struct->NVIC_IRQChannelSubPriority & (0x0F >> pri))) << 0x04; + + NVIC->IP[init_struct->NVIC_IRQChannel] = pri; + NVIC->ISER[init_struct->NVIC_IRQChannel >> 0x05] = 0x01 << (init_struct->NVIC_IRQChannel & 0x1F); + } + else { + NVIC->ICER[init_struct->NVIC_IRQChannel >> 0x05] = 0x01 << (init_struct->NVIC_IRQChannel & 0x1F); + } + +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief System low power mode configuration. +/// @param low_power_mode +/// This parameter can be any combination of the following values: +/// @arg NVIC_LP_SEVONPEND +/// @arg NVIC_LP_SLEEPDEEP +/// @arg NVIC_LP_SLEEPONEXIT +/// @param state: new state of the low power mode. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void NVIC_SystemLPConfig(u8 low_power_mode, FunctionalState state) +{ + (state) ? (SCB->SCR |= low_power_mode) : (SCB->SCR &= ~(u32)low_power_mode); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SysTick clock source configuration. +/// @param systick_clk_source +/// This parameter can be any combination of the following values: +/// @arg SysTick_CLKSource_EXTCLK +/// @arg SysTick_CLKSource_HCLK +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void SysTick_CLKSourceConfig(u32 systick_clk_source) +{ + (systick_clk_source == SysTick_CLKSource_HCLK) ? (SysTick->CTRL |= SysTick_CLKSource_HCLK) \ + : (SysTick->CTRL &= ~SysTick_CLKSource_HCLK); +} + +/// @} + +/// @} + +/// @} diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_pwr.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_pwr.c new file mode 100644 index 000000000..e39bf3f31 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_pwr.c @@ -0,0 +1,215 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_pwr.c +/// @author AE TEAM +/// @brief THIS FILE PROVIDES ALL THE PWR FIRMWARE FUNCTIONS. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#define __HAL_PWR_C_ + +// Files includes +#include "hal_pwr.h" +#include "hal_rcc.h" +#include "hal_syscfg.h" +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup PWR_HAL +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup PWR_Exported_Functions +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Deinitializes the PWR peripheral registers to their default reset +/// values. +/// @param None. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void PWR_DeInit(void) +{ + exRCC_APB1PeriphReset(RCC_APB1ENR_PWR); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables access to the RTC and backup registers. +/// @param state: new state of the access to the RTC and backup +/// registers. This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void PWR_BackupAccessCmd(FunctionalState state) +{ + (state) ? (RCC->BDCR |= RCC_BDCR_DBP) : (RCC->BDCR &= ~RCC_BDCR_DBP); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the Power Voltage Detector(PVD). +/// @param state: new state of the PVD. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void PWR_PVDCmd(FunctionalState state) +{ + (state) ? (SYSCFG->PDETCSR |= SYSCFG_PDETCSR_PVDE) : (SYSCFG->PDETCSR &= ~SYSCFG_PDETCSR_PVDE); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the voltage threshold detected by the Power Voltage +/// Detector(PVD). +/// @param pvd_level: specifies the PVD detection level +/// This parameter can be one of the following values: +/// @arg emPVD_LEVEL0 : PVD detection level set to 1.7V +/// @arg emPVD_LEVEL1 : PVD detection level set to 2.0V +/// @arg emPVD_LEVEL2 : PVD detection level set to 2.3V +/// @arg emPVD_LEVEL3 : PVD detection level set to 2.6V +/// @arg emPVD_LEVEL4 : PVD detection level set to 2.9V +/// @arg emPVD_LEVEL5 : PVD detection level set to 3.2V +/// @arg emPVD_LEVEL6 : PVD detection level set to 3.5V +/// @arg emPVD_LEVEL7 : PVD detection level set to 3.8V +/// @arg emPVD_LEVEL8 : PVD detection level set to 4.1V +/// @arg emPVD_LEVEL9 : PVD detection level set to 4.4V +/// @arg emPVD_LEVEL10: PVD detection level set to 4.7V +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void PWR_PVDLevelConfig(emPVD_Level_Typedef pvd_level) +{ + SYSCFG->PDETCSR = (SYSCFG->PDETCSR & (~SYSCFG_PDETCSR_PLS)) | pvd_level; +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the WakeUp Pin functionality. +/// @param state: new state of the WakeUp Pin functionality. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void PWR_WakeUpPinCmd(FunctionalState state) +{ + (state != DISABLE) ? (PWR->CR2 |= PWR_CR2_EWUP1) : (PWR->CSR &= ~PWR_CR2_EWUP1); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the WakeUp Pin functionality. +/// @param state: new state of the WakeUp Pin functionality. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void PWR_WakeUpPinXCmd(emWUP_Pin_Typedef pin, FunctionalState state) +{ + (state != DISABLE) ? (PWR->CR2 |= (PWR_CR2_EWUP1 << pin)) : (PWR->CSR &= ~(PWR_CR2_EWUP1 << pin)); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enters STOP mode. +/// @param regulator: specifies the regulator state in STOP mode. +/// This parameter can be one of the following values: +/// @arg PWR_Regulator_ON: STOP mode with regulator ON +/// @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode. +/// @param stop_entry: specifies if STOP mode in entered with WFI or WFE +/// instruction. +/// This parameter can be one of the following values: +/// @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction +/// @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void PWR_EnterSTOPMode(emPWR_Reg_Stop_mode_Typedef regulator, emPWR_STOP_ModeEn_Typedef stop_entry) +{ + + MODIFY_REG(PWR->CR, PWR_CR_LDPS, regulator); + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + if(stop_entry == PWR_STOPEntry_WFI) { + __WFI(); + } + else { + __WFE(); + } +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enters STANDBY mode. +/// @param None. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void PWR_EnterSTANDBYMode(void) +{ + PWR->CR |= PWR_CR_PDDS; + PWR->SCR |= PWR_SCR_CWUF1 | PWR_SCR_CWUF2 | PWR_SCR_CWUF3 | PWR_SCR_CWUF4 | PWR_SCR_CWUF5 | PWR_SCR_CWUF6; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + +#if defined(__CC_ARM) + __force_stores(); +#endif + __WFI(); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Checks whether the specified PWR flag is set or not. +/// @param flag: specifies the flag to check. +/// This parameter can be one of the following values: +/// @arg PWR_FLAG_WU: Wake Up flag +/// @arg PWR_FLAG_SB: StandBy flag +/// @arg PWR_FLAG_PVDO: PVD Output +/// @retval The new state of PWR_FLAG (SET or RESET). +//////////////////////////////////////////////////////////////////////////////// +FlagStatus PWR_GetPVDOFlagStatus(u32 flag) +{ + return (FlagStatus)(SYSCFG->PDETCSR & flag); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Clears the PWR's pending flags. +/// @param flag: specifies the flag to clear. +/// This parameter can be one of the following values: +/// @arg PWR_FLAG_WU: Wake Up flag +/// @arg PWR_FLAG_SB: StandBy flag +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void PWR_ClearPVDOFlag(u32 flag) +{ + PWR->CR |= flag << 2; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Checks whether the specified PWR flag is set or not. +/// @param flag: specifies the flag to check. +/// This parameter can be one of the following values: +/// @arg PWR_FLAG_WU: Wake Up flag +/// @arg PWR_FLAG_SB: StandBy flag +/// @arg PWR_FLAG_PVDO: PVD Output +/// @retval The new state of PWR_FLAG (SET or RESET). +//////////////////////////////////////////////////////////////////////////////// +FlagStatus PWR_GetFlagStatus(u32 flag) +{ + return (FlagStatus)(PWR->CSR & flag); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Clears the PWR's pending flags. +/// @param flag: specifies the flag to clear. +/// This parameter can be one of the following values: +/// @arg PWR_FLAG_WU: Wake Up flag +/// @arg PWR_FLAG_SB: StandBy flag +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void PWR_ClearFlag(u32 flag) +{ + PWR->CR |= flag << 2; +} + +/// @} + +/// @} + +/// @} diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rcc.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rcc.c new file mode 100644 index 000000000..5e2bd1a85 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rcc.c @@ -0,0 +1,995 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_rcc.c +/// @author AE TEAM +/// @brief THIS FILE PROVIDES ALL THE RCC FIRMWARE FUNCTIONS. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#define _HAL_RCC_C_ + +// Files includes +#include "mm32_reg.h" +#include "hal_rcc.h" + + + +u8 tbPresc[] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup RCC_HAL +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup RCC_Exported_Functions +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Resets the RCC clock configuration to default state. +/// @param None. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RCC_DeInit() +{ + SET_BIT(RCC->CR, RCC_CR_HSION); + CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW); + CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON ); + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL_DN | RCC_PLLCFGR_PLL_DP); + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); + CLEAR_REG(RCC->CFGR); + CLEAR_REG(RCC->CIR); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the External High Speed oscillator (HSE). +/// @param state: specifies the new state of HSE. +/// This parameter can be one of the following values: +/// @arg RCC_HSE_OFF: HSE oscillator OFF +/// @arg RCC_HSE_ON: HSE oscillator ON +/// @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RCC_HSEConfig(RCCHSE_TypeDef state) +{ + RCC->CR &= ~(RCC_CR_HSEBYP | RCC_CR_HSEON); + switch (state) { + case RCC_HSE_Bypass: + RCC->CR |= RCC_CR_HSEBYP; + RCC->CR |= RCC_CR_HSEON; + break; + case RCC_HSE_ON: + RCC->CR |= RCC_CR_HSEON; + break; + default: + break; + } +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Checks whether the specified RCC flag is set or not. +/// @param flag: specifies the flag to check. +/// This parameter can be one of the following values: +/// @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready +/// @arg RCC_FLAG_HSERDY: HSE oscillator clock ready +/// @arg RCC_FLAG_PLLRDY: PLL clock ready +/// @arg RCC_FLAG_LSERDY: LSE oscillator clock ready +/// @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready +/// @arg RCC_FLAG_PINRST: Pin reset +/// @arg RCC_FLAG_PORRST: POR/PDR reset +/// @arg RCC_FLAG_SFTRST: Software reset +/// @arg RCC_FLAG_IWDGRST: Independent Watchdog reset +/// @arg RCC_FLAG_WWDGRST: Window Watchdog reset +/// @arg RCC_FLAG_LPWRRST: Low Power reset +/// @retval The new state of flag (SET or RESET). +//////////////////////////////////////////////////////////////////////////////// +FlagStatus RCC_GetFlagStatus(RCC_FLAG_TypeDef flag) +{ + return ((((flag >> 5) == CR_REG_INDEX) ? RCC->CR : (((flag >> 5) == BDCR_REG_INDEX) ? RCC->BDCR : RCC->CSR)) & + (1 << (flag & 0x1F))) + ? SET : RESET; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Waits for HSE start-up. +/// @param None. +/// @retval An ErrorStatus enumuration value: +/// - SUCCESS: HSE oscillator is stable and ready to use +/// - ERROR: HSE oscillator not yet ready +//////////////////////////////////////////////////////////////////////////////// +ErrorStatus RCC_WaitForHSEStartUp(void) +{ + u32 StartUpCounter = 0; + + FlagStatus HSEStatus; + + do { + HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); + StartUpCounter++; + } while ((HSEStatus == RESET) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + return (ErrorStatus)(RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) ? SUCCESS : ERROR; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Waits for flag start-up. +/// @param flag: specifies the flag to check. +/// This parameter can be one of the following values: +/// @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready +/// @arg RCC_FLAG_HSERDY: HSE oscillator clock ready +/// @arg RCC_FLAG_PLLRDY: PLL clock ready +/// @arg RCC_FLAG_LSERDY: LSE oscillator clock ready +/// @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready +/// @arg RCC_FLAG_PINRST: Pin reset +/// @arg RCC_FLAG_PORRST: POR/PDR reset +/// @arg RCC_FLAG_SFTRST: Software reset +/// @arg RCC_FLAG_IWDGRST: Independent Watchdog reset +/// @arg RCC_FLAG_WWDGRST: Window Watchdog reset +/// @retval An ErrorStatus enumuration value: +/// - SUCCESS: HSE oscillator is stable and ready to use +/// - ERROR: HSE oscillator not yet ready +//////////////////////////////////////////////////////////////////////////////// +ErrorStatus RCC_WaitForFlagStartUp(RCC_FLAG_TypeDef flag) +{ + u32 StartUpCounter = 0; + + while (RCC_GetFlagStatus(flag) == RESET) { + if (StartUpCounter++ > HSE_STARTUP_TIMEOUT) { + return ERROR; + } + } + return SUCCESS; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the Internal High Speed oscillator (HSI). +/// @param state: new state of the HSI. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RCC_HSICmd(FunctionalState state) +{ + MODIFY_REG(RCC->CR, RCC_CR_HSION, (state << RCC_CR_HSION_Pos)); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the system clock (SYSCLK). +/// @param sys_clk_source: specifies the clock source used as system +/// clock. This parameter can be one of the following values: +/// @arg RCC_HSI: specifies HSI as system clock +/// @arg RCC_HSE: specifies HSE as system clock +/// @arg RCC_PLL: specifies PLL as system clock +/// @arg RCC_LSI: specifies LSI as system clock +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RCC_SYSCLKConfig(SYSCLK_TypeDef sys_clk_source) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (sys_clk_source << RCC_CFGR_SW_Pos)); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the PLL clock source and DM DN factor. +/// This function must be used only when the PLL is disabled. +/// @param plldn: specifies the PLL multiplication factor. +/// This parameter can be RCC_PLLMul_x where x:[31:26] +/// @param plldm: specifies the PLL Divsior factor. +/// This parameter can be RCC_Divsior_x where x:[22:20] +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RCC_PLLDMDNConfig(u32 plldn, u32 plldm) +{ + MODIFY_REG(RCC->PLLCFGR, (RCC_PLLCFGR_PLL_DN | RCC_PLLCFGR_PLL_DP), ((plldn << RCC_PLLCFGR_PLL_DN_Pos) | (plldm << RCC_PLLCFGR_PLL_DP_Pos))); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the PLL. +/// The PLL can not be disabled if it is used as system clock. +/// @param state: new state of the PLL. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RCC_PLLCmd(FunctionalState state) +{ + MODIFY_REG(RCC->CR, RCC_CR_PLLON, (state << RCC_CR_PLLON_Pos)); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the PLL clock source and multiplication factor. +/// This function must be used only when the PLL is disabled. +/// @param pll_src: specifies the PLL entry clock source. +/// This parameter can be one of the following values: +/// @arg RCC_HSI_Div4: HSI oscillator clock divided +/// by 4 selected as PLL clock entry +/// @arg RCC_HSE_Div1: HSE oscillator clock selected +/// as PLL clock entry +/// @arg RCC_HSE_Div2: HSE oscillator clock divided +/// by 2 selected as PLL clock entry +/// @param pll_mul: specifies the PLL multiplication factor. +/// This parameter can be RCC_PLLMul_x where x:[31:26][22:20] +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RCC_PLLConfig(RCC_PLLSource_TypeDef pll_src, RCC_PLLMul_TypeDef pll_mul) +{ + const u8 DNDM_Item[] = {0x07, 0x03, 0x05, 0x01, 0x07, 0x01, 0x09, 0x01, // Frclk*8/4 ; Frclk*6/2 ; Frclk*8/2 ; Frclk*10/2; + 0x0B, 0x01, 0x0D, 0x01, 0x0F, 0x01, 0x11, 0x01, // Frclk*12/2; Frclk*14/2; Frclk*16/2; Frclk*18/2; + 0x13, 0x01, 0x15, 0x01, 0x17, 0x01, 0x19, 0x01, // Frclk*20/2; Frclk*22/2; Frclk*24/2; Frclk*26/2; + 0x1B, 0x01, 0x1D, 0x01, 0x1F, 0x01 + }; // Frclk*28/2; Frclk*30/2; // Frclk*32/2; + MODIFY_REG(RCC->PLLCFGR, (RCC_PLLCFGR_PLLXTPRE | RCC_PLLCFGR_PLLSRC), pll_src); + RCC_PLLDMDNConfig((u32)DNDM_Item[pll_mul >> 17], (u32)DNDM_Item[(pll_mul >> 17) + 1]); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the USB clock (USBCLK). +/// @param usb_clk_src: specifies the USB clock source. +/// This clock is derived from the PLL output. +/// This parameter can be one of the following values: +/// @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source +/// @arg RCC_USBCLKSource_PLLCLK_Div2: PLL clock divided by 2 selected as USB +/// clock source +/// @arg RCC_USBCLKSource_PLLCLK_Div3: PLL clock divided by 3 selected as USB +/// clock source +/// @arg RCC_USBCLKSource_PLLCLK_Div4: PLL clock divided by 4 selected as USB +/// clock source +/// @arg RCC_USBCLKSource_PLLCLK_Div5: PLL clock divided by 5 selected as USB +/// clock source +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RCC_USBCLKConfig(RCC_USBCLKSOURCE_TypeDef usb_clk_src) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (usb_clk_src << RCC_CFGR_USBPRE_Pos)); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Returns the clock source used as system clock. +/// @param None. +/// @retval The clock source used as system clock. The returned value can +/// be one of the following: +/// - 0x00: HSI/6 used as system clock +/// - 0x04: HSE used as system clock +/// - 0x08: PLL used as system clock +//////////////////////////////////////////////////////////////////////////////// +u8 RCC_GetSYSCLKSource(void) +{ + return ((u8)READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the AHB clock (hclk). +/// @param sys_clk: defines the AHB clock divider. This clock is derived +/// from the system clock (SYSCLK). +/// This parameter can be one of the following values: +/// @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK +/// @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2 +/// @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4 +/// @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8 +/// @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16 +/// @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64 +/// @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128 +/// @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 +/// @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512 +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RCC_HCLKConfig(RCC_AHB_CLK_TypeDef sys_clk) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, sys_clk); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the Low Speed APB clock (pclk1). +/// @param hclk: defines the APB1 clock divider. This clock is derived from +/// the AHB clock (hclk). +/// This parameter can be one of the following values: +/// @arg RCC_HCLK_Div1: APB1 clock = hclk +/// @arg RCC_HCLK_Div2: APB1 clock = hclk/2 +/// @arg RCC_HCLK_Div4: APB1 clock = hclk/4 +/// @arg RCC_HCLK_Div8: APB1 clock = hclk/8 +/// @arg RCC_HCLK_Div16: APB1 clock = hclk/16 +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RCC_PCLK1Config(RCC_APB1_APB2_CLK_TypeDef hclk) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, hclk); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the High Speed APB clock (pclk2). +/// @param hclk: defines the APB2 clock divider. This clock is derived from +/// the AHB clock (hclk). +/// This parameter can be one of the following values: +/// @arg RCC_HCLK_Div1: APB2 clock = hclk +/// @arg RCC_HCLK_Div2: APB2 clock = hclk/2 +/// @arg RCC_HCLK_Div4: APB2 clock = hclk/4 +/// @arg RCC_HCLK_Div8: APB2 clock = hclk/8 +/// @arg RCC_HCLK_Div16: APB2 clock = hclk/16 +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RCC_PCLK2Config(RCC_APB1_APB2_CLK_TypeDef hclk) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (hclk << 3)); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the ADC clock (ADCCLK). +/// @param pclk2: defines the ADC clock divider. This clock is derived from +/// the APB2 clock (pclk2). +/// This parameter can be one of the following values: +/// @arg RCC_PCLK2_Div2: ADC clock = pclk2/2 +/// @arg RCC_PCLK2_Div4: ADC clock = pclk2/4 +/// @arg RCC_PCLK2_Div6: ADC clock = pclk2/6 +/// @arg RCC_PCLK2_Div8: ADC clock = pclk2/8 +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RCC_ADCCLKConfig(RCC_ADCCLKSOURCE_TypeDef pclk2) +{ + MODIFY_REG(RCC->CFGR, ADC_CFGR_PRE, pclk2); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the External Low Speed oscillator (LSE). +/// @param state: specifies the new state of the LSE. +/// This parameter can be one of the following values: +/// @arg RCC_LSE_OFF: LSE oscillator OFF +/// @arg RCC_LSE_ON: LSE oscillator ON +/// @arg RCC_LSE_Bypass: LSE oscillator bypassed with external +/// clock +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RCC_LSEConfig(RCC_LSE_TypeDef state) +{ + RCC->BDCR &= ~(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON); + + switch (state) { + case RCC_LSE_Bypass: + RCC->BDCR |= RCC_BDCR_LSEBYP; + RCC->BDCR |= RCC_BDCR_LSEON; + break; + case RCC_LSE_ON: + RCC->BDCR |= RCC_BDCR_LSEON; + break; + default: + break; + } +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the RTC clock (RTCCLK). +/// Once the RTC clock is selected it can be changed unless the +/// Backup domain is reset. +/// @param rtc_clk_src: specifies the RTC clock source. +/// This parameter can be one of the following values: +/// @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock +/// @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock +/// @arg RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 +/// selected as RTC clock +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RCC_RTCCLKConfig(RCC_RTCCLKSOURCE_TypeDef rtc_clk_src) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, rtc_clk_src); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the RTC clock. +/// This function must be used only after the RTC clock was +/// selected using the RCC_RTCCLKConfig function. +/// @param state: new state of the RTC clock. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RCC_RTCCLKCmd(FunctionalState state) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCEN, (state << RCC_BDCR_RTCEN_Pos)); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the Internal Low Speed oscillator (LSI). +/// LSI can not be disabled if the IWDG is running. +/// @param state: new state of the LSI. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RCC_LSICmd(FunctionalState state) +{ +// u32 j; + MODIFY_REG(RCC->CSR, RCC_CSR_LSION | RCC_CSR_LSIOENLV, RCC_CSR_LSIOENLV | (state << RCC_CSR_LSION_Pos)); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Returns the clock frequency of different on chip clocks. +/// @param None. +/// @retval sys_clk : System clock frequency +//////////////////////////////////////////////////////////////////////////////// +u32 RCC_GetSysClockFreq(void) +{ + u32 result; + u32 clock, mul, div; + switch (RCC->CFGR & RCC_CFGR_SWS) { + case RCC_CFGR_SWS_LSI: + result = LSI_VALUE; + break; + + case RCC_CFGR_SWS_HSE: + result = HSE_VALUE; + break; + + case RCC_CFGR_SWS_PLL: + clock = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC) ? (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLXTPRE) ? (HSE_VALUE >> 1) : HSE_VALUE) + : HSI_VALUE_PLL_ON; + mul = ((RCC->PLLCFGR & (u32)RCC_PLLCFGR_PLL_DN) >> RCC_PLLCFGR_PLL_DN_Pos) + 1; + div = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL_DP) >> RCC_PLLCFGR_PLL_DP_Pos) + 1; + + result = clock * mul / div; + break; + default: + result = HSI_VALUE; + break; + } + return result; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Returns the hclk frequency of different on chip clocks. +/// @param None. +/// @retval hclk frequency +//////////////////////////////////////////////////////////////////////////////// +u32 RCC_GetHCLKFreq(void) +{ + return (RCC_GetSysClockFreq() >> tbPresc[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Returns the pclk1 frequency of different on chip clocks. +/// @param None. +/// @retval pclk1 frequency +//////////////////////////////////////////////////////////////////////////////// +u32 RCC_GetPCLK1Freq(void) +{ + return (RCC_GetHCLKFreq() >> tbPresc[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Returns the pclk2 frequency of different on chip clocks. +/// @param None. +/// @retval pclk2 frequency +//////////////////////////////////////////////////////////////////////////////// +u32 RCC_GetPCLK2Freq(void) +{ + return (RCC_GetHCLKFreq() >> tbPresc[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Returns the frequency of different on chip clocks. +/// @param clk: pointer to a RCC_ClocksTypeDef structure which +/// will hold the clocks frequency. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RCC_GetClocksFreq(RCC_ClocksTypeDef* clk) +{ + u8 tbADCPresc[] = {2, 4, 6, 8}; + + clk->SYSCLK_Frequency = RCC_GetSysClockFreq(); + clk->HCLK_Frequency = RCC_GetHCLKFreq(); + clk->PCLK1_Frequency = RCC_GetPCLK1Freq(); + clk->PCLK2_Frequency = RCC_GetPCLK2Freq(); + + clk->ADCCLK_Frequency = clk->PCLK2_Frequency / tbADCPresc[(RCC->CFGR & ADC_CFGR_PRE) >> ADC_CFGR_PRE_Pos]; + +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the AHB peripheral clock. +/// @param ahb_periph: specifies the AHB peripheral to gates its clock. +/// This parameter can be any combination of the following values: +/// @param state: new state of the specified peripheral clock. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RCC_AHBPeriphClockCmd(u32 ahb_periph, FunctionalState state) +{ + (state) ? (RCC->AHBENR |= ahb_periph) : (RCC->AHBENR &= ~ahb_periph); +} +/// @param state: new state of the specified peripheral clock. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RCC_AHB2PeriphClockCmd(u32 ahb_periph, FunctionalState state) +{ + (state) ? (RCC->AHB2ENR |= ahb_periph) : (RCC->AHB2ENR &= ~ahb_periph); +} +/// @param state: new state of the specified peripheral clock. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RCC_AHB3PeriphClockCmd(u32 ahb_periph, FunctionalState state) +{ + (state) ? (RCC->AHB3ENR |= ahb_periph) : (RCC->AHB3ENR &= ~ahb_periph); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the High Speed APB (APB2) peripheral clock. +/// @param apb2_periph: specifies the APB2 peripheral to gates its +/// clock. +/// This parameter can be any combination of the following values: +/// @param state: new state of the specified peripheral clock. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RCC_APB2PeriphClockCmd(u32 apb2_periph, FunctionalState state) +{ + (state) ? (RCC->APB2ENR |= apb2_periph) : (RCC->APB2ENR &= ~apb2_periph); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the Low Speed APB (APB1) peripheral clock. +/// @param apb1_periph: specifies the APB1 peripheral to gates its +/// clock. +/// This parameter can be any combination of the following values: +/// @param state: new state of the specified peripheral clock. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RCC_APB1PeriphClockCmd(u32 apb1_periph, FunctionalState state) +{ + (state) ? (RCC->APB1ENR |= apb1_periph) : (RCC->APB1ENR &= ~apb1_periph); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Forces or releases High Speed APB (APB2) peripheral reset. +/// @param apb2_periph: specifies the APB2 peripheral to reset. +/// This parameter can be any combination of the following values: +/// @param state: new state of the specified peripheral reset. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RCC_APB2PeriphResetCmd(u32 apb2_periph, FunctionalState state) +{ + (state) ? (RCC->APB2RSTR |= apb2_periph) : (RCC->APB2RSTR &= ~apb2_periph); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Forces or releases Low Speed APB (APB1) peripheral reset. +/// @param apb1_periph: specifies the APB1 peripheral to reset. +/// This parameter can be any combination of the following values: +/// @param state: new state of the specified peripheral clock. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RCC_APB1PeriphResetCmd(u32 apb1_periph, FunctionalState state) +{ + (state) ? (RCC->APB1RSTR |= apb1_periph) : (RCC->APB1RSTR &= ~apb1_periph); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Forces or releases Low Speed AHB peripheral reset. +/// @param ahb_periph: specifies the AHB peripheral to reset. +/// This parameter can be any combination of the following values: +/// @param state: new state of the specified peripheral clock. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RCC_AHBPeriphResetCmd(u32 ahb_periph, FunctionalState state) +{ + (state) ? (RCC->AHBRSTR |= ahb_periph) : (RCC->AHBRSTR &= ~ahb_periph); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Forces or releases Low Speed AHB2 peripheral reset. +/// @param ahb_periph: specifies the AHB peripheral to reset. +/// This parameter can be any combination of the following values: +/// @param state: new state of the specified peripheral clock. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RCC_AHB2PeriphResetCmd(u32 ahb_periph, FunctionalState state) +{ + (state) ? (RCC->AHB2RSTR |= ahb_periph) : (RCC->AHB2RSTR &= ~ahb_periph); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Forces or releases Low Speed AHB2 peripheral reset. +/// @param ahb_periph: specifies the AHB peripheral to reset. +/// This parameter can be any combination of the following values: +/// @param state: new state of the specified peripheral clock. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RCC_AHB3PeriphResetCmd(u32 ahb_periph, FunctionalState state) +{ + (state) ? (RCC->AHB3RSTR |= ahb_periph) : (RCC->AHB3RSTR &= ~ahb_periph); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Forces or releases the Backup domain reset. +/// @param state: new state of the Backup domain reset. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RCC_BackupResetCmd(FunctionalState state) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_BDRST, (state << RCC_BDCR_BDRST_Pos)); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the Clock Security System. +/// @param state: new state of the Clock Security System.. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RCC_ClockSecuritySystemCmd(FunctionalState state) +{ + MODIFY_REG(RCC->CR, RCC_CR_CSSON, (state << RCC_CR_CSSON_Pos)); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Selects the clock source to output on MCO pin. +/// @param mco_src: specifies the clock source to output. +/// This parameter can be one of the following values: +/// @arg RCC_MCO_NoClock: No clock selected +/// @arg RCC_MCO_LSI: LSI oscillator clock selected +/// @arg RCC_MCO_LSE: LSE oscillator clock selected +/// @arg RCC_MCO_SYSCLK: System clock selected +/// @arg RCC_MCO_HSI: HSI oscillator clock selected +/// @arg RCC_MCO_HSE: HSE oscillator clock selected +/// @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RCC_MCOConfig(RCC_MCO_TypeDef mco_src) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, mco_src); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Clears the RCC reset flags. +/// The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, +/// RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, +/// RCC_FLAG_LPWRRST +/// @param None. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RCC_ClearFlag(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_RMVF); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the specified RCC interrupts. +/// @param it: specifies the RCC interrupt sources to be enabled or +/// disabled. +/// This parameter can be any combination of the following values: +/// @arg RCC_IT_LSIRDY: LSI ready interrupt +/// @arg RCC_IT_LSERDY: LSE ready interrupt +/// @arg RCC_IT_HSIRDY: HSI ready interrupt +/// @arg RCC_IT_HSERDY: HSE ready interrupt +/// @arg RCC_IT_PLLRDY: PLL ready interrupt +/// @param state: new state of the specified RCC interrupts. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RCC_ITConfig(RCC_IT_TypeDef it, FunctionalState state) +{ + (state) ? SET_BIT(RCC->CIR, it << RCC_CIR_LSIRDYIE_Pos) : CLEAR_BIT(RCC->CIR, it << RCC_CIR_LSIRDYIE_Pos); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Checks whether the specified RCC interrupt has occurred or not. +/// @param it: specifies the RCC interrupt source to check. +/// This parameter can be one of the following values: +/// @arg RCC_IT_LSIRDY: LSI ready interrupt +/// @arg RCC_IT_LSERDY: LSE ready interrupt +/// @arg RCC_IT_HSIRDY: HSI ready interrupt +/// @arg RCC_IT_HSERDY: HSE ready interrupt +/// @arg RCC_IT_PLLRDY: PLL ready interrupt +/// @arg RCC_IT_CSS: Clock Security System interrupt +/// @retval The new state of it (SET or RESET). +//////////////////////////////////////////////////////////////////////////////// +ITStatus RCC_GetITStatus(RCC_IT_TypeDef it) +{ + return (ITStatus)READ_BIT(RCC->CIR, (it << RCC_CIR_LSIRDYF_Pos)); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Clears the RCC�?interrupt pending bits. +/// @param it: specifies the interrupt pending bit to clear. +/// This parameter can be any combination of the following values: +/// @arg RCC_IT_LSIRDY: LSI ready interrupt +/// @arg RCC_IT_LSERDY: LSE ready interrupt +/// @arg RCC_IT_HSIRDY: HSI ready interrupt +/// @arg RCC_IT_HSERDY: HSE ready interrupt +/// @arg RCC_IT_PLLRDY: PLL ready interrupt +/// @arg RCC_IT_CSS: Clock Security System interrupt +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RCC_ClearITPendingBit(u8 it) +{ + SET_BIT(RCC->CIR, (it << RCC_CIR_LSIRDYC_Pos)); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Forces or releases Low Speed APB (APB1) peripheral reset. +/// @param apb1_periph: specifies the APB1 peripheral to reset. +/// This parameter can be any combination of the following values: +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RCC_APB1PeriphReset(u32 apb1_periph) +{ + RCC->APB1RSTR |= apb1_periph; + RCC->APB1RSTR &= ~apb1_periph; +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Forces or releases Low Speed APB (APB2) peripheral reset. +/// @param apb2_periph: specifies the APB2 peripheral to reset. +/// This parameter can be any combination of the following values: +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RCC_APB2PeriphReset(u32 apb2_periph) +{ + RCC->APB2RSTR |= apb2_periph; + RCC->APB2RSTR &= ~apb2_periph; +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Forces or releases High Speed AHB (AHB1) peripheral reset. +/// @param ahb1_periph: specifies the AHB1 peripheral to reset. +/// This parameter can be any combination of the following values: +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RCC_AHBPeriphReset(u32 ahb1_periph) +{ + RCC->AHBRSTR |= ahb1_periph; + RCC->AHBRSTR &= ~ahb1_periph; +} +//////////////////////////////////////////////////////////////////////////////// +// +// New Function Interface +// +//////////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Forces or releases Low Speed APB (APB1) peripheral reset. +/// @param apb1_periph: specifies the APB1 peripheral to reset. +/// This parameter can be any combination of the following values: +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void exRCC_APB1PeriphReset(u32 apb1_periph) +{ + RCC->APB1RSTR |= apb1_periph; + RCC->APB1RSTR &= ~apb1_periph; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief +/// @param +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void exRCC_BackupReset() +{ +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Forces or releases High Speed APB (APB2) peripheral reset. +/// @param apb2_periph: specifies the APB2 peripheral to reset. +/// This parameter can be any combination of the following values: +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void exRCC_APB2PeriphReset(u32 apb2_periph) +{ + RCC->APB2RSTR |= apb2_periph; + RCC->APB2RSTR &= ~apb2_periph; +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Forces or releases High Speed AHB (AHB1) peripheral reset. +/// @param ahb1_periph: specifies the AHB1 peripheral to reset. +/// This parameter can be any combination of the following values: +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void exRCC_AHBPeriphReset(u32 ahb1_periph) +{ + RCC->AHBRSTR |= ahb1_periph; + RCC->AHBRSTR &= ~ahb1_periph; +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Disable systick +/// @param None. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void exRCC_SystickDisable() +{ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enable systick +/// @param None. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void exRCC_SystickEnable(u32 sys_tick_period) +{ + SysTick_Config(RCC_GetHCLKFreq() / 1000000 * sys_tick_period); +} + +/* +(state) ? (RCC->AHBENR |= ahb_periph) : (RCC->AHBENR &= ~ahb_periph); +(state) ? (RCC->APB1ENR |= apb1_periph) : (RCC->APB1ENR &= ~apb1_periph); +(state) ? (RCC->APB2ENR |= apb2_periph) : (RCC->APB2ENR &= ~apb2_periph); +*/ + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the specified ADC peripheral Clock. +/// @param peripheral:select the ADC peripheral. +/// @param state: new state of the ADC peripheral. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RCC_ADC_ClockCmd(ADC_TypeDef* peripheral, FunctionalState state) +{ + switch (*(vu32*)&peripheral) { + + case ADC1_BASE: + (state) ? (RCC->APB2ENR |= RCC_APB2ENR_ADC1) : (RCC->APB2ENR &= ~RCC_APB2ENR_ADC1); + break; + case ADC2_BASE: + (state) ? (RCC->APB2ENR |= RCC_APB2ENR_ADC2) : (RCC->APB2ENR &= ~RCC_APB2ENR_ADC2); + break; + case ADC3_BASE: + (state) ? (RCC->APB2ENR |= RCC_APB2ENR_ADC3) : (RCC->APB2ENR &= ~RCC_APB2ENR_ADC3); + break; + default: + break; + } + +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the specified BKP peripheral Clock. +/// @param peripheral:select the BKP peripheral. +/// @param state: new state of the BKP peripheral. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RCC_BKP_ClockCmd(BKP_TypeDef* peripheral, FunctionalState state) +{ + if(BKP == peripheral) { + (state) ? (RCC->APB1ENR |= RCC_APB1ENR_BKP) : (RCC->APB1ENR &= ~RCC_APB1ENR_BKP); + (state) ? (RCC->APB1ENR |= RCC_APB1ENR_PWR) : (RCC->APB1ENR &= ~RCC_APB1ENR_PWR); + } +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the specified CAN peripheral Clock. +/// @param peripheral:select the CAN peripheral. +/// @param state: new state of the CAN peripheral. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RCC_CAN_ClockCmd(CAN_TypeDef* peripheral, FunctionalState state) +{ + if(CAN1 == peripheral) { + (state) ? (RCC->APB1ENR |= RCC_APB1ENR_CAN) : (RCC->APB1ENR &= ~RCC_APB1ENR_CAN); + } +} + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the specified COMP peripheral Clock. +/// @param peripheral:select the COMP peripheral. +/// @param state: new state of the COMP peripheral. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RCC_COMP_ClockCmd(COMP_TypeDef* peripheral, FunctionalState state) +{ + if(COMP == peripheral) { + (state) ? (RCC->APB2ENR |= RCC_APB2ENR_COMP) : (RCC->APB2ENR &= ~RCC_APB2ENR_COMP); + } +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the specified CRC peripheral Clock. +/// @param peripheral:select the CRC peripheral. +/// @param state: new state of the CRC peripheral. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RCC_CRC_ClockCmd(CRC_TypeDef* peripheral, FunctionalState state) +{ + if(CRC == peripheral) { + (state) ? (RCC->AHBENR |= RCC_AHBENR_CRC) : (RCC->AHBENR &= ~RCC_AHBENR_CRC); + } +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the specified DAC peripheral Clock. +/// @param peripheral:select the DAC peripheral. +/// @param state: new state of the DAC peripheral. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RCC_DAC_ClockCmd(DAC_TypeDef* peripheral, FunctionalState state) +{ + if(DAC == peripheral) { + (state) ? (RCC->APB1ENR |= RCC_APB1ENR_DAC) : (RCC->APB1ENR &= ~RCC_APB1ENR_DAC); + } +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the specified DMA peripheral Clock. +/// @param peripheral:select the DMA peripheral. +/// @param state: new state of the DMA peripheral. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RCC_DMA_ClockCmd(DMA_TypeDef* peripheral, FunctionalState state) +{ + if(DMA1 == peripheral) { + (state) ? (RCC->AHBENR |= RCC_AHBENR_DMA1) : (RCC->AHBENR &= ~RCC_AHBENR_DMA1); + } + if(DMA2 == peripheral) { + (state) ? (RCC->AHBENR |= RCC_AHBENR_DMA2) : (RCC->AHBENR &= ~RCC_AHBENR_DMA2); + } +} + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the specified GPIO peripheral Clock. +/// @param peripheral:select the GPIO peripheral. +/// @param state: new state of the GPIO peripheral. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RCC_GPIO_ClockCmd(GPIO_TypeDef* peripheral, FunctionalState state) +{ + switch (*(vu32*)&peripheral) { + case (u32)GPIOA: + (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOA) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOA); + break; + case (u32)GPIOB: + (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOB) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOB); + break; + case (u32)GPIOC: + (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOC) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOC); + break; + case (u32)GPIOD: + (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOD) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOD); + break; + case (u32)GPIOE: + (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOE) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOE); + break; + case (u32)GPIOF: + (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOF) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOF); + break; + case (u32)GPIOG: + (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOG) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOG); + break; + case (u32)GPIOH: + (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOH) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOH); + break; + default: + break; + } +} + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Deinitializes the uart peripheral registers to their +/// default reset values. +/// @param peripheral: Select the UART or the UART peripheral. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RCC_UART_ClockCmd(UART_TypeDef* peripheral, FunctionalState state) +{ + if(UART2 == peripheral) { + (state) ? (RCC->APB1ENR |= RCC_APB1ENR_UART2) : (RCC->APB1ENR &= ~RCC_APB1ENR_UART2);//exRCC_APB1PeriphReset(RCC_APB1ENR_UART2); + } + if(UART1 == peripheral) { + (state) ? (RCC->APB2ENR |= RCC_APB2ENR_UART1) : (RCC->APB2ENR &= ~RCC_APB2ENR_UART1);//exRCC_APB2PeriphReset(RCC_APB2ENR_UART1); + } + if(UART3 == peripheral) { + (state) ? (RCC->APB1ENR |= RCC_APB1ENR_UART3) : (RCC->APB1ENR &= ~RCC_APB1ENR_UART3);//exRCC_APB1PeriphReset(RCC_APB1ENR_UART3); + } + if(UART4 == peripheral) { + (state) ? (RCC->APB1ENR |= RCC_APB1ENR_UART4) : (RCC->APB1ENR &= ~RCC_APB1ENR_UART4);//exRCC_APB1PeriphReset(RCC_APB1ENR_UART4); + } + if(UART5 == peripheral) { + (state) ? (RCC->APB1ENR |= RCC_APB1ENR_UART5) : (RCC->APB1ENR &= ~RCC_APB1ENR_UART5);//exRCC_APB1PeriphReset(RCC_APB1ENR_UART5); + } + if(UART6 == peripheral) { + (state) ? (RCC->APB2ENR |= RCC_APB2ENR_UART6) : (RCC->APB2ENR &= ~RCC_APB2ENR_UART6);//exRCC_APB2PeriphReset(RCC_APB2ENR_UART6); + } + if(UART7 == peripheral) { + (state) ? (RCC->APB1ENR |= RCC_APB1ENR_UART7) : (RCC->APB1ENR &= ~RCC_APB1ENR_UART7);//exRCC_APB1PeriphReset(RCC_APB1ENR_UART7); + } + if(UART8 == peripheral) { + (state) ? (RCC->APB1ENR |= RCC_APB1ENR_UART8) : (RCC->APB1ENR &= ~RCC_APB1ENR_UART8);//exRCC_APB1PeriphReset(RCC_APB1ENR_UART8); + } +} +/// @} + +/// @} + +/// @} diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rtc.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rtc.c new file mode 100644 index 000000000..b02c6750b --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rtc.c @@ -0,0 +1,234 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_rtc.c +/// @author AE TEAM +/// @brief THIS FILE PROVIDES ALL THE RTC FIRMWARE FUNCTIONS. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#define _HAL_RTC_C_ + +// Files includes +#include "hal_rtc.h" + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup RTC_HAL +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup RTC_Exported_Functions +/// @{ + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the specified RTC interrupts. +/// @param it: specifies the RTC interrupts sources to be enabled or +/// disabled. +/// This parameter can be any combination of the following values: +/// @arg RTC_IT_OW: Overflow interrupt +/// @arg RTC_IT_ALR: Alarm interrupt +/// @arg RTC_IT_SEC: Second interrupt +/// @param state: new state of the specified RTC interrupts. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RTC_ITConfig(RTC_IT_TypeDef it, FunctionalState state) +{ + (state == ENABLE) ? (RTC->CR |= it) : (RTC->CR &= (u16)~it); +// RTC_WaitForLastTask(); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enters the RTC configuration mode. +/// @param None. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RTC_EnterConfigMode(void) +{ +// PWR->CR |= PWR_CR_DBP; + RTC->CSR |= RTC_CSR_CNF; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Exits from the RTC configuration mode. +/// @param None. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RTC_ExitConfigMode(void) +{ + RTC->CSR &= ~RTC_CSR_CNF; + while (!(RTC->CSR & RTC_CSR_RTOFF)); +// PWR->CR &= ~PWR_CR_DBP; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Gets the RTC counter value. +/// @param None. +/// @retval RTC counter value. +//////////////////////////////////////////////////////////////////////////////// +u32 RTC_GetCounter(void) +{ + u32 dat = RTC->CNTH << 16; + return (RTC->CNTL | dat); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Sets the RTC counter value. +/// @param count: RTC counter new value. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RTC_SetCounter(u32 count) +{ + RTC_EnterConfigMode();//RTC->CSR |= RTC_CSR_CNF; + RTC->CNTH = count >> 16; + RTC->CNTL = count; + RTC_ExitConfigMode();//RTC->CSR &= ~RTC_CSR_CNF; +// while (!(RTC->CSR & RTC_CSR_RTOFF)); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Sets the RTC prescaler value. +/// @param prescaler: RTC prescaler new value. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RTC_SetPrescaler(u32 prescaler) +{ + RTC_EnterConfigMode();//RTC->CSR |= RTC_CSR_CNF; + RTC->PRLH = prescaler >> 16; + RTC->PRLL = prescaler; + RTC_ExitConfigMode();//RTC->CSR &= ~RTC_CSR_CNF; +// while (!(RTC->CSR & RTC_CSR_RTOFF)); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Sets the RTC alarm value. +/// @param alarm: RTC alarm new value. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RTC_SetAlarm(u32 alarm) +{ + RTC_EnterConfigMode();//RTC->CSR |= RTC_CSR_CNF; + RTC->ALRH = alarm >> 16; + RTC->ALRL = alarm; + RTC_ExitConfigMode();//RTC->CSR &= ~RTC_CSR_CNF; +// while (!(RTC->CSR & RTC_CSR_RTOFF)); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Gets the RTC divider value. +/// @param None. +/// @retval RTC Divider value. +//////////////////////////////////////////////////////////////////////////////// +u32 RTC_GetDivider(void) +{ + u32 dat = ((u32)(RTC->DIVH & RTC_DIVH_DIV) << 16); + return (RTC->DIVL | dat); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Waits until last write operation on RTC registers has finished. +/// @note This function must be called before any write to RTC registers. +/// @param None. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RTC_WaitForLastTask(void) +{ + while (!(RTC->CSR & RTC_CSR_RTOFF)); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL) +/// are synchronized with RTC APB clock. +/// @note This function must be called before any read operation after an APB +/// reset or an APB clock stop. +/// @param None. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RTC_WaitForSynchro(void) +{ + RTC->CSR &= ~RTC_CSR_RSF; + while (!(RTC->CSR & RTC_CSR_RSF)); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Checks whether the specified RTC flag is set or not. +/// @param flag: specifies the flag to check. +/// This parameter can be one the following values: +/// @arg RTC_FLAG_RTOFF: RTC Operation OFF flag +/// @arg RTC_FLAG_RSF: Registers Synchronized flag +/// @arg RTC_FLAG_OW: Overflow flag +/// @arg RTC_FLAG_ALR: Alarm flag +/// @arg RTC_FLAG_SEC: Second flag +/// @retval The state of RTC_FLAG (SET or RESET). +///////////////////////////////////////////////////////////////////////////////// +FlagStatus RTC_GetFlagStatus(RTC_FLAG_TypeDef flag) +{ + return (FlagStatus)(RTC->CSR & flag); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Clears the RTC's pending flags. +/// @param flag: specifies the flag to clear. +/// This parameter can be any combination of the following values: +/// @arg RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only +/// after an APB reset or an APB Clock stop. +/// @arg RTC_FLAG_OW: Overflow flag +/// @arg RTC_FLAG_ALR: Alarm flag +/// @arg RTC_FLAG_SEC: Second flag +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RTC_ClearFlag(RTC_FLAG_TypeDef flag) +{ + RTC->CSR &= ~flag; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Checks whether the specified RTC interrupt has occurred or not. +/// @param it: specifies the RTC interrupts sources to check. +/// This parameter can be one of the following values: +/// @arg RTC_IT_OW: Overflow interrupt +/// @arg RTC_IT_ALR: Alarm interrupt +/// @arg RTC_IT_SEC: Second interrupt +/// @retval The state of the RTC_IT (SET or RESET). +//////////////////////////////////////////////////////////////////////////////// +ITStatus RTC_GetITStatus(RTC_IT_TypeDef it) +{ + return (ITStatus)(RTC->CSR & it); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Clears the RTC's interrupt pending bits. +/// @param it: specifies the interrupt pending bit to clear. +/// This parameter can be any combination of the following values: +/// @arg RTC_IT_OW: Overflow interrupt +/// @arg RTC_IT_ALR: Alarm interrupt +/// @arg RTC_IT_SEC: Second interrupt +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void RTC_ClearITPendingBit(RTC_IT_TypeDef it) +{ +// RTC_EnterConfigMode();//RTC->CSR |= RTC_CSR_CNF; + RTC->CSR &= ~it; +// RTC_ExitConfigMode();//RTC->CSR &= ~RTC_CSR_CNF; +} + + +/// @} + +/// @} + +/// @} diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_sdio.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_sdio.c new file mode 100644 index 000000000..4b1bd70ee --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_sdio.c @@ -0,0 +1,527 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_sdio.c +/// @author AE TEAM +/// @brief THIS FILE PROVIDES ALL THE SDIO FIRMWARE FUNCTIONS. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#define _HAL_SDIO_C_ +#include "reg_sdio.h" +#include "hal_sdio.h" +#include "hal_rcc.h" + + + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup SDIO_HAL +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup SDIO_Exported_Functions +/// @{ +//////////////////////////////////////////////////////////////////////////////// +/// @brief Deinitializes the SDIO peripheral registers to their default reset +/// values. +/// @param None. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void SDIO_DeInit(void) +{ + RCC_AHBPeriphResetCmd(RCC_AHBRSTR_SDIO, ENABLE); + RCC_AHBPeriphResetCmd(RCC_AHBRSTR_SDIO, DISABLE); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Fills each SDIO_InitStruct member with its default value. +/// @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which +/// will be initialized. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct) +{ + // SDIO_InitStruct members default value + SDIO_InitStruct->SDIO_MDEN = 0; + SDIO_InitStruct->SDIO_DATWT = 0; + SDIO_InitStruct->SDIO_SelPTSM = 0; + SDIO_InitStruct->SDIO_CLKSP = 0; + SDIO_InitStruct->SDIO_OUTM = 0; + SDIO_InitStruct->SDIO_SelSM = 0; + SDIO_InitStruct->SDIO_OPMSel = 0; +} + + +/// +/// @brief Fills each SDIO_DataInitStruct member with its default value. +/// @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure which +/// will be initialized. +/// @retval None +/// +void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct) +{ + /* SDIO_DataInitStruct members default value */ + SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF; + SDIO_DataInitStruct->SDIO_DataLength = 0x00; + SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b; + SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard; +// SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block; +// SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable; +} + +/// +/// @brief Initializes the SDIO data path according to the specified +/// parameters in the SDIO_DataInitStruct. +/// @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that +/// contains the configuration information for the SDIO command. +/// @retval None +/// +//void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct) +//{ +// u32 tmpreg = 0; + +// /*---------------------------- SDIO DTIMER Configuration ---------------------*/ +// /* Set the SDIO Data TimeOut value */ +// SDIO->MMC_TIMEOUTCNT = SDIO_DataInitStruct->SDIO_DataTimeOut; + +// /*---------------------------- SDIO DLEN Configuration -----------------------*/ +// /* Set the SDIO DataLength value */ +// SDIO->MMC_BYTECNTL = SDIO_DataInitStruct->SDIO_DataLength; + +// /*---------------------------- SDIO DCTRL Configuration ----------------------*/ +// /* Get the SDIO DCTRL value */ +// tmpreg = SDIO->DCTRL; +// /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */ +// tmpreg &= DCTRL_CLEAR_MASK; +// /* Set DEN bit according to SDIO_DPSM value */ +// /* Set DTMODE bit according to SDIO_TransferMode value */ +// /* Set DTDIR bit according to SDIO_TransferDir value */ +// /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */ +// tmpreg |= (u32)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir;// +// //| SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM; + +// /* Write to SDIO DCTRL */ +// SDIO->DCTRL = tmpreg; +//} +//////////////////////////////////////////////////////////////////////////////// +/// @brief The frequency division factor is configured to generate the SDIO clock. +/// @param value : 1MHz = Fhclk/((mmc_cardsel[5 : 0] + 1) × 2) +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void SDIO_ClockSet(u32 value) +{ +// SDIO->MMC_CARDSEL &= ~SDIO_MMC_CARDSEL_MASK; + SDIO->MMC_CARDSEL = (SDIO_MMC_CARDSEL_CTREN | SDIO_MMC_CARDSEL_ENPCLK | (value & 0x3F)); +// SDIO->MMC_CARDSEL = 0xC0+0x2F;//0xdf; +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Initializes the SDIO peripheral according to the specified +/// parameters in the SDIO_InitStruct. +/// @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure +/// that contains the configuration information for the SDIO peripheral. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct) +{ + SDIO->MMC_CTRL &= 0x700; + SDIO->MMC_CTRL |= (SDIO_InitStruct->SDIO_OPMSel | SDIO_InitStruct->SDIO_SelSM | + SDIO_InitStruct->SDIO_OUTM | SDIO_InitStruct->SDIO_CLKSP | + SDIO_InitStruct->SDIO_SelPTSM | SDIO_InitStruct->SDIO_DATWT | + SDIO_InitStruct->SDIO_MDEN); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the SDIO interrupts. +/// @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled. +/// state : new state of the specified SDIO interrupts. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void SDIO_ITConfig(u32 SDIO_IT, FunctionalState state) +{ + (state) ? (SDIO->MMC_INT_MASK |= SDIO_IT) : (SDIO->MMC_INT_MASK &= ~SDIO_IT); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the SDIO CRC. +/// @param SDIO_CRC: specifies the SDIO CRC sources to be enabled or disabled. +/// state : new state of the specified SDIO CRC. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void SDIO_CRCConfig(u32 SDIO_CRC, FunctionalState state) +{ + (state) ? (SDIO->MMC_CRCCTL |= SDIO_CRC) : (SDIO->MMC_CRCCTL &= ~SDIO_CRC); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Port transfer speed mode. +/// @param clkdiv : High/low speed. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void SDIO_Clock_Set(u8 clkdiv) +{ + SDIO->MMC_CTRL &= ~SDIO_MMC_CTRL_SelPTSM; + (clkdiv) ? (SDIO->MMC_CTRL |= SDIO_MMC_CTRL_SelPTSM) : (SDIO->MMC_CTRL &= ~SDIO_MMC_CTRL_SelPTSM); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Turn off the SDIO switch. +/// @param None. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +SD_Error SD_PowerOFF(void) +{ + SDIO->MMC_CARDSEL &= ~(SDIO_MMC_CARDSEL_ENPCLK | SDIO_MMC_CARDSEL_CTREN); + return SD_OK; +} +/// +/// @brief Fills each SDIO_CmdInitStruct member with its default value. +/// @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef +/// structure which will be initialized. +/// @retval None +/// +void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct) +{ + /* SDIO_CmdInitStruct members default value */ + SDIO_CmdInitStruct->SDIO_Argument = 0x00; + SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00; + SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No; + SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No; +// SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SDIO sends command functions. +/// @param cmdindex : Type the command. +/// waitrsp : Expected correspondence. +/// arg : parameter. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void SDIO_Send_Cmd(u8 cmdindex, u8 waitrsp, u32 arg) +{ + SDIO->CMD_BUF0 = (arg >> 0) & 0xFF; + SDIO->CMD_BUF1 = (arg >> 8) & 0xFF; + SDIO->CMD_BUF2 = (arg >> 16) & 0xFF; + SDIO->CMD_BUF3 = (arg >> 24) & 0xFF; + SDIO->CMD_BUF4 = 0x40 | cmdindex; + SDIO->CLR_MMC_INT |= 0; + SDIO->MMC_IO = SDIO_MMC_IO_AUTOTR; + while(1) { + if(SDIO->CLR_MMC_INT & SDIO_CLR_MMC_INT_CMDDMC) { + SDIO->CLR_MMC_INT |= SDIO_CLR_MMC_INT_CMDDMC; + break; + } + } + if(waitrsp == SDIO_Response_Short) { + SDIO->MMC_IO = SDIO_MMC_IO_AUTOCLKG | \ + SDIO_MMC_IO_AUTOTR | \ + SDIO_MMC_IO_RESPCMDSEL; + } + else if(waitrsp == SDIO_Response_Long) { + SDIO->MMC_IO = SDIO_MMC_IO_AUTOCLKG | \ + SDIO_MMC_IO_AUTOTR | \ + SDIO_MMC_IO_RESPCMDSEL | \ + SDIO_MMC_IO_CID_CSDRD; + } + else { + } +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Check the execution status of CMD0. +/// @param None. +/// @retval card error code. +//////////////////////////////////////////////////////////////////////////////// +SD_Error CmdError(void) +{ + SD_Error errorstatus = SD_OK; + u32 timeout = SDIO_CMD0TIMEOUT; + while (timeout--) { + if(((SDIO->MMC_IO & SDIO_MMC_IO_RESPCMDSEL) == 0) && ((SDIO->MMC_IO & SDIO_MMC_IO_AUTOTR) == 0)) + break; + } + if (timeout == 0) + return SD_CMD_RSP_TIMEOUT; + SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_MASK; + return errorstatus; +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Check the error status of the R1 response. +/// @param cmd : Current command. +/// @retval card error code. +//////////////////////////////////////////////////////////////////////////////// +SD_Error CmdResp1Error(u8 cmd) +{ + u32 status; + u32 response; + while(1) { + status = SDIO->CLR_MMC_INT ; + if(status & (SDIO_CLR_MMC_INT_CRCEMC | SDIO_CLR_MMC_INT_CRNTMC | SDIO_CLR_MMC_INT_CMDDMC)) + break; + } + if(status & SDIO_CLR_MMC_INT_CRNTMC) { + SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRNTMC; + return SD_CMD_RSP_TIMEOUT; + } + if(status & (SDIO_CLR_MMC_INT_CRCEMC)) { + SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRCEMC; + return SD_CMD_CRC_FAIL; + } + SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_MASK; + + if((SDIO->CMD_BUF4 & 0x3F) != cmd) { + return SD_ILLEGAL_CMD; + } + response = SDIO->CMD_BUF3 << 24 | SDIO->CMD_BUF2 << 16 | SDIO->CMD_BUF1 << 8 | SDIO->CMD_BUF0; + return (SD_Error)(response & SD_OCR_ERRORBITS); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Check the execution status of CMD2. +/// @param None. +/// @retval card error code. +//////////////////////////////////////////////////////////////////////////////// +SD_Error CmdResp2Error(void) +{ + SD_Error errorstatus = SD_OK; + u32 status; + u32 timeout = SDIO_CMD0TIMEOUT; + while(timeout--) { + status = SDIO->CLR_MMC_INT ; + if(status & (SDIO_CLR_MMC_INT_CRCEMC | SDIO_CLR_MMC_INT_CRNTMC | SDIO_CLR_MMC_INT_CMDDMC)) + break; + } + if((timeout == 0) || (status & SDIO_CLR_MMC_INT_CRNTMC)) { + errorstatus = SD_CMD_RSP_TIMEOUT; + SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRNTMC; + return errorstatus; + } + if(status & SDIO_CLR_MMC_INT_CRCEMC) { + errorstatus = SD_CMD_CRC_FAIL; + SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRCEMC; + } + SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_MASK; + return errorstatus; +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Check the execution status of CMD3. +/// @param None. +/// @retval card error code. +//////////////////////////////////////////////////////////////////////////////// +SD_Error CmdResp3Error(void) +{ + u32 status; + while(1) { + status = SDIO->CLR_MMC_INT ; + if(status & (SDIO_CLR_MMC_INT_CRCEMC | SDIO_CLR_MMC_INT_CRNTMC | SDIO_CLR_MMC_INT_CMDDMC)) + break; + } + if(status & SDIO_CLR_MMC_INT_CRNTMC) { + SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRNTMC; + return SD_CMD_RSP_TIMEOUT; + } + SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_MASK; + return SD_OK; +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Check the execution status of CMD6. +/// @param None. +/// @retval card error code. +//////////////////////////////////////////////////////////////////////////////// +SD_Error CmdResp6Error(u8 cmd, u16* prca) +{ + SD_Error errorstatus = SD_OK; + u32 status; + u32 rspr1; + while(1) { + status = SDIO->CLR_MMC_INT ; + if(status & (SDIO_CLR_MMC_INT_CRCEMC | SDIO_CLR_MMC_INT_CRNTMC | SDIO_CLR_MMC_INT_CMDDMC)) + break; + } + if(status & SDIO_CLR_MMC_INT_CRNTMC) { + SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRNTMC; + return SD_CMD_RSP_TIMEOUT; + } + if(status & SDIO_CLR_MMC_INT_CRCEMC) { + SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRCEMC; + return SD_CMD_CRC_FAIL; + } + if((SDIO->CMD_BUF4 & 0x3F) != cmd) { + return SD_ILLEGAL_CMD; + } + SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_MASK; + rspr1 = SDIO->CMD_BUF3 << 24 | SDIO->CMD_BUF2 << 16 | SDIO->CMD_BUF1 << 8 | SDIO->CMD_BUF0; + if(SD_ALLZERO == (rspr1 & (SD_R6_GENERAL_UNKNOWN_ERROR | SD_R6_ILLEGAL_CMD | SD_R6_COM_CRC_FAILED))) { + *prca = (u16)(rspr1 >> 16); + return errorstatus; + } + if(rspr1 & SD_R6_GENERAL_UNKNOWN_ERROR) { + return SD_GENERAL_UNKNOWN_ERROR; + } + if(rspr1 & SD_R6_ILLEGAL_CMD) { + return SD_ILLEGAL_CMD; + } + if(rspr1 & SD_R6_COM_CRC_FAILED) { + return SD_COM_CRC_FAILED; + } + return errorstatus; +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Check the execution status of CMD7. +/// @param None. +/// @retval card error code. +//////////////////////////////////////////////////////////////////////////////// +SD_Error CmdResp7Error(void) +{ + SD_Error errorstatus = SD_OK; + u32 status; + u32 timeout = SDIO_CMD0TIMEOUT; + while(timeout--) { + status = SDIO->CLR_MMC_INT ; + if(status & (SDIO_CLR_MMC_INT_CRCEMC | SDIO_CLR_MMC_INT_CRNTMC | SDIO_CLR_MMC_INT_CMDDMC)) + break; + } + if((timeout == 0) || (status & SDIO_CLR_MMC_INT_CRNTMC)) { //timeout + errorstatus = SD_CMD_RSP_TIMEOUT; + SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRNTMC; + return errorstatus; + } + if(status & SDIO_CLR_MMC_INT_CMDDMC) { + errorstatus = SD_OK; + SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CMDDMC; + } + return errorstatus; +} + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Write data direction block size configuration. +/// @param datatimeout : maximum latency. +/// datalen : data len +/// blksize : block count. +/// dir : direction +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void SDIO_Send_Data_Cfg(u32 datatimeout, u32 datalen, u8 blksize, u8 dir) +{ + u32 tmpreg, tmpreg1, tmpreg2 = 0; + tmpreg = SDIO->MMC_IO_MBCTL; + tmpreg1 = SDIO->MMC_IO; + tmpreg &= ~(SDIO_MMC_IO_MBCTL_BTSSel | SDIO_MMC_IO_MBCTL_SPMBDTR | SDIO_MMC_IO_MBCTL_SMBDTD); + if (datatimeout < 100) { + SDIO->MMC_TIMEOUTCNT = datatimeout; + } + else if (datatimeout < 10000) { + SDIO->MMC_TIMEOUTCNT = datatimeout / 100; + tmpreg |= SDIO_MMC_IO_MBCTL_BTSSel; + } + else if (datatimeout < 1000000) { + SDIO->MMC_TIMEOUTCNT = datatimeout / 10000; + tmpreg |= SDIO_MMC_IO_MBCTL_BTSSel_2; + } + else { + SDIO->MMC_TIMEOUTCNT = datatimeout / 1000000; + tmpreg |= SDIO_MMC_IO_MBCTL_BTSSel; + } + SDIO->MMC_BYTECNTL = datalen & 0x1FFFFFF; ; + SDIO->MMC_BLOCKCNT = blksize; + if (dir == 0) { + tmpreg |= SDIO_MMC_IO_MBCTL_SMBDTD; + tmpreg1 |= SDIO_MMC_IO_TRANSFDIR; + tmpreg2 |= SDIO_BUF_CTLL_SBAD; + } + else { + tmpreg &= ~(SDIO_MMC_IO_MBCTL_SMBDTD); + tmpreg1 &= ~(SDIO_MMC_IO_TRANSFDIR); + tmpreg2 &= ~(SDIO_BUF_CTLL_SBAD); + } + SDIO->MMC_IO_MBCTL = tmpreg; + SDIO->MMC_IO = tmpreg1; + SDIO->BUF_CTL = tmpreg2; +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Clears the SDIO's Flag pending bits. +/// @param SDIO_IT: specifies the flag pending bit to clear. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void SDIO_ClearFlag(u32 SDIO_FLAG) +{ + SDIO->CLR_MMC_INT |= SDIO_FLAG; +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Clears the SDIO's interrupt pending bits. +/// @param SDIO_IT: specifies the interrupt pending bit to clear. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void SDIO_ClearITPendingBit(u32 SDIO_IT) +{ + SDIO->CLR_MMC_INT |= SDIO_IT; +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Checks whether the specified SDIO flag is set or not. +/// @param SDIO_FLAG: specifies the flag to check. +/// @retval The new state of SDIO_FLAG (SET or RESET). +//////////////////////////////////////////////////////////////////////////////// +FlagStatus SDIO_GetFlagStatus(u32 SDIO_FLAG) +{ + return ((SDIO->CLR_MMC_INT & SDIO_FLAG) ? SET : RESET); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Reads the value of the data transfer timeout count +/// @param None. +/// @retval timeout count. +//////////////////////////////////////////////////////////////////////////////// +u32 SDIO_GetTimeOutCounter(void) +{ + return (SDIO->MMC_TIMEOUTCNT & 0xFF); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Read one data word from FIFO. +/// @param None. +/// @retval Data received. +//////////////////////////////////////////////////////////////////////////////// +u32 SDIO_ReadData(void) +{ + return SDIO->FIFO; +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Write one data word to FIFO. +/// @param tempbuff : Write data. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void SDIO_WriteData(u32 tempbuff) +{ + SDIO->FIFO = tempbuff; +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Returns number of remaining data bytes to be transferred. +/// @param None +/// @retval Number of remaining data bytes to be transferred +//////////////////////////////////////////////////////////////////////////////// +u32 SDIO_GetDataCounter(void) +{ + return SDIO->MMC_BYTECNTL; +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enable or Dsiable DMA . +/// @param tempbuff : Write data. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void SDIO_DMACmd(FunctionalState state) +{ + (state) ? ((SDIO->BUF_CTL |= SDIO_BUF_CTLL_DMAHEN), SDIO->BUF_CTL &= (~(SDIO_BUF_CTLL_DRM))) : (SDIO->BUF_CTL &= ~SDIO_BUF_CTLL_DMAHEN); +} + + +/// @} + +/// @} + +/// @} + diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_spi.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_spi.c new file mode 100644 index 000000000..3d8c286a3 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_spi.c @@ -0,0 +1,648 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_spi.c +/// @author AE TEAM +/// @brief THIS FILE PROVIDES ALL THE SPI FIRMWARE FUNCTIONS. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#define _HAL_SPI_C_ +#include +// Files includes +#include "hal_spi.h" +#include "hal_rcc.h" + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup SPI_HAL +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +///@addtogroup SPI_Exported_Functions +///@{ + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Deinitializes the spi peripheral registers to their +/// default reset values. +/// @param spi: Select the SPI peripheral. +/// This parameter can be one of the following values: +/// SPI1, SPI2. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void SPI_DeInit(SPI_TypeDef* spi) +{ + switch (*(vu32*)&spi) { + case (u32)SPI2: // SPI2_BASE: + RCC_APB1PeriphResetCmd(RCC_APB1ENR_SPI2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1ENR_SPI2, DISABLE); + break; + case (u32)SPI3: // SPI3_BASE: + RCC_APB1PeriphResetCmd(RCC_APB1ENR_SPI3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1ENR_SPI3, DISABLE); + break; + case (u32)SPI1: // SPI1_BASE: + RCC_APB2PeriphResetCmd(RCC_APB2ENR_SPI1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2ENR_SPI1, DISABLE); + break; + default: + break; + } +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Initializes the spi peripheral according to the specified +/// parameters in the init_struct . +/// @param spi: Select the SPI peripheral. +/// This parameter can be one of the following values: +/// SPI1, SPI2. +/// @param init_struct: pointer to a SPI_InitTypeDef structure +/// that contains the configuration information for the +/// specified SPI peripheral. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void SPI_Init(SPI_TypeDef* spi, SPI_InitTypeDef* init_struct) +{ + if (init_struct->SPI_DataSize == SPI_DataSize_32b) { + SET_BIT(spi->GCR, SPI_GCR_DWSEL); + } + else { + CLEAR_BIT(spi->GCR, SPI_GCR_DWSEL); + } + MODIFY_REG(spi->GCR, SPI_GCR_NSS, init_struct->SPI_NSS); + MODIFY_REG(spi->GCR, SPI_GCR_MODE, init_struct->SPI_Mode); + MODIFY_REG(spi->CCR, SPI_CCR_LSBFE, init_struct->SPI_FirstBit); + MODIFY_REG(spi->CCR, SPI_CCR_CPOL, init_struct->SPI_CPOL); + MODIFY_REG(spi->CCR, SPI_CCR_CPHA, init_struct->SPI_CPHA); + + SET_BIT(spi->CCR, SPI_CCR_SPILEN); + + MODIFY_REG(spi->BRR, BRR_Mask, init_struct->SPI_BaudRatePrescaler); + + if (init_struct->SPI_DataWidth >= 32) { + MODIFY_REG(spi->ECR, ECR_Mask, 0); + } + else { + MODIFY_REG(spi->ECR, ECR_Mask, init_struct->SPI_DataWidth); + } +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Fills each init_struct member with its default value. +/// @param init_struct: pointer to a SPI_InitTypeDef structure +/// which will be initialized. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void SPI_StructInit(SPI_InitTypeDef* init_struct) +{ + init_struct->SPI_Mode = SPI_Mode_Slave; + init_struct->SPI_DataSize = SPI_DataSize_8b; + init_struct->SPI_DataWidth = 8; + init_struct->SPI_CPOL = SPI_CPOL_Low; + init_struct->SPI_CPHA = SPI_CPHA_1Edge; + init_struct->SPI_NSS = SPI_NSS_Soft; + init_struct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; + init_struct->SPI_FirstBit = SPI_FirstBit_MSB; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the specified SPI peripheral. +/// @param spi: Select the SPI peripheral. +/// This parameter can be one of the following values: +/// SPI1, SPI2. +/// @param state: new state of the spi peripheral. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void SPI_Cmd(SPI_TypeDef* spi, FunctionalState state) +{ + (state) ? SET_BIT(spi->GCR, SPI_GCR_SPIEN) : CLEAR_BIT(spi->GCR, SPI_GCR_SPIEN); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the specified SPI interrupts. +/// @param spi: Select the SPI peripheral. +/// This parameter can be one of the following values:SPI1, SPI2. +/// @param interrupt: specifies the SPI interrupt sources to be +/// enabled or disabled. +/// This parameter can be one of the following values: +/// @arg SPI_IT_TXEPT: Transmitter empty interrupt +/// @arg SPI_IT_RXFULL: RX FIFO full interrupt +/// @arg SPI_IT_RXMATCH: Receive data match the RXDNR number interrupt +/// @arg SPI_IT_RXOERR: Receive overrun error interrupt +/// @arg SPI_IT_UNDERRUN: underrun interrupt +/// @arg SPI_IT_RX: Receive data available interrupt +/// @arg SPI_IT_TX: Transmit FIFO available interrupt +/// @param state: new state of the specified spi interrupts. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void SPI_ITConfig(SPI_TypeDef* spi, u8 interrupt, FunctionalState state) +{ + if (state) { + SET_BIT(spi->GCR, (u32)SPI_GCR_IEN); + SET_BIT(spi->IER, (u32)interrupt); + } + else { + CLEAR_BIT(spi->IER, interrupt); + CLEAR_BIT(spi->GCR, SPI_GCR_IEN); + } +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the SPI DMA interface. +/// @param spi: Select the SPI peripheral. +/// This parameter can be one of the following values: +/// SPI1, SPI2. +/// @param state: new state of the DMA Request sources. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void SPI_DMACmd(SPI_TypeDef* spi, FunctionalState state) +{ + (state) ? SET_BIT(spi->GCR, SPI_GCR_DMAEN) : CLEAR_BIT(spi->GCR, SPI_GCR_DMAEN); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief configure tn Fifo trigger level bit. +/// @param spi: Select the SPI peripheral. +/// This parameter can be one of the following values: +/// SPI1, SPI2. +/// @param fifo_trigger_value: specifies the Fifo trigger level +/// This parameter can be any combination of the following values: +/// SPI_TXTLF : SPI TX FIFO Trigger value set +/// SPI_RXTLF : SPI RX FIFO Trigger value set +/// @param state: new state of the selected SPI transfer request. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void SPI_FifoTrigger(SPI_TypeDef* spi, SPI_TLF_TypeDef fifo_trigger_value, FunctionalState state) +{ + (state) ? SET_BIT(spi->GCR, (u32)fifo_trigger_value) : CLEAR_BIT(spi->GCR, (u32)fifo_trigger_value); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Transmits a Data through the spi peripheral. +/// @param spi: Select the SPI peripheral. +/// This parameter can be one of the following values: +/// SPI1, SPI2. +/// @param data : Data to be transmitted. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void SPI_SendData(SPI_TypeDef* spi, u32 data) +{ + u16 templen; + __asm volatile("cpsid i"); + + WRITE_REG(spi->TDR, data); + + templen = READ_REG(spi->ECR); + if(templen == 0) + templen = 32; + if (templen > 8) + WRITE_REG(spi->TDR, data >> 8); + if (templen > 16) + WRITE_REG(spi->TDR, data >> 16); + if (templen > 24) + WRITE_REG(spi->TDR, data >> 24); + __asm volatile("cpsie i"); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Returns the most recent received data by the spi peripheral. +/// @param spi: Select the SPI peripheral. +/// This parameter can be one of the following values: +/// SPI1, SPI2. +/// @retval The value of the received data. +//////////////////////////////////////////////////////////////////////////////// +u32 SPI_ReceiveData(SPI_TypeDef* spi) +{ + u32 temp; + u8 templen; + __asm volatile("cpsid i"); + + temp = READ_REG(spi->RDR); + + templen = READ_REG(spi->ECR); + if(templen == 0) + templen = 32; + if (templen > 8) + temp |= (u32)(READ_REG(spi->RDR) << 8); + if (templen > 16) + temp |= (u32)(READ_REG(spi->RDR) << 16); + if (templen > 24) + temp |= (u32)(READ_REG(spi->RDR) << 24); + + __asm volatile("cpsie i"); + + return temp; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Slave chip csn single by selected +/// @param spi: Select the SPI peripheral. +/// This parameter can be one of the following values: +/// SPI1, SPI2. +/// @param state: new state of the selected SPI CS pin +/// request. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void SPI_CSInternalSelected(SPI_TypeDef* spi, FunctionalState state) +{ + (state) ? CLEAR_BIT(spi->NSSR, SPI_NSSR_NSS) : SET_BIT(spi->NSSR, SPI_NSSR_NSS); // illogical +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the NSS pin control mode for the selected SPI. +/// @param spi: Select the SPI peripheral. +/// This parameter can be one of the following values: +/// SPI1, SPI2. +/// @param nss: specifies the SPI NSS internal state. +/// This parameter can be one of the following values: +/// @arg SPI_NSS_Soft: NSS pin control by software +/// @arg SPI_NSS_Hard: NSS pin control by hardware +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* spi, SPI_NSS_TypeDef nss) +{ + (nss != SPI_NSS_Soft) ? SET_BIT(spi->GCR, SPI_NSS_Hard) : CLEAR_BIT(spi->GCR, SPI_NSS_Hard); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the data size for the selected SPI. +/// @param spi: Select the SPI peripheral. +/// This parameter can be one of the following values: +/// SPI1, SPI2. +/// @param data_size: specifies the SPI data size. +/// This parameter can be one of the following values: +/// 0 to 31, 0 = 32b, 1 = 1b, 2 = 2b +/// @arg DataSize : 0 to 31 +/// @retval None. +/// @retval None. +bool SPI_DataSizeConfig(SPI_TypeDef* spi, u8 data_size) +{ + if (data_size > 32) + return false; + data_size &= 0x1F; + WRITE_REG(spi->ECR, data_size); + return true; +} + +////////////////////////////////////////////////////////////////////////////////// +void SPI_DataSizeTypeConfig(SPI_TypeDef* spi, SPI_DataSize_TypeDef SPI_DataSize) +{ + CLEAR_BIT(spi->GCR, (u32)SPI_DataSize_32b); + SET_BIT(spi->GCR, (u32)SPI_DataSize); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Selects the data transfer direction in bi-directional mode +/// for the specified SPI. +/// @param spi: Select the SPI peripheral. +/// This parameter can be one of the following values: +/// SPI1, SPI2. +/// @param direction: specifies the data transfer direction in +/// bi-directional mode. +/// This parameter can be one of the following values: +/// @arg SPI_Direction_Tx: Selects Tx transmission direction +/// @arg SPI_Direction_Rx: Selects Rx receive direction +/// @arg SPI_Disable_Tx: Selects Rx receive direction +/// @arg SPI_Disable_Rx: Selects Rx receive direction +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void SPI_BiDirectionalLineConfig(SPI_TypeDef* spi, SPI_Direction_TypeDef direction) +{ + switch (direction) { + case SPI_Direction_Rx: + SET_BIT(spi->GCR, SPI_GCR_RXEN); + break; + case SPI_Direction_Tx: + SET_BIT(spi->GCR, SPI_GCR_TXEN); + break; + case SPI_Disable_Rx: + CLEAR_BIT(spi->GCR, SPI_GCR_RXEN); + break; + case SPI_Disable_Tx: + CLEAR_BIT(spi->GCR, SPI_GCR_TXEN); + break; + default: + break; + } +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Checks whether the specified SPI flag is set or not. +/// @param spi: Select the SPI peripheral. +/// This parameter can be one of the following values: +/// SPI1, SPI2. +/// @param flag: specifies the SPI flag to check. +/// This parameter can be one of the following values: +/// @arg SPI_FLAG_RXAVL: Rx buffer has bytes flag +/// @arg SPI_FLAG_TXEPT: Tx buffer and tx shifter empty flag +/// @arg SPI_FLAG_TXFULL: Tx buffer full flag +/// @arg SPI_FLAG_RXAVL_4BYTE: Receive available 4 byte data message flag. +/// @retval The new state of SPI_FLAG (SET or RESET). +//////////////////////////////////////////////////////////////////////////////// +FlagStatus SPI_GetFlagStatus(SPI_TypeDef* spi, SPI_FLAG_TypeDef flag) +{ +// u8 number; + return (spi->SR & flag) ? SET : RESET; +// if (spi->ECR == 8 || spi->ECR == 0) +// return (spi->SR & SPI_FLAG) ? SET : RESET; +// else { +// if ((spi->ECR > 0) && (spi->ECR <= 8)) +// number = 1; +// else if ((spi->ECR) <= 16) +// number = 2; +// else if ((spi->ECR) <= 24) +// number = 3; +// else if (((spi->ECR) <= 31) || (spi->ECR == 0)) +// number = 4; +// return (((spi->SR & 0xf00) >> 8) >= number) ? SET : RESET; +// } +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Checks whether the specified SPI interrupt has occurred or not. +/// @param spi: Select the SPI peripheral. +/// This parameter can be one of the following values: +/// SPI1, SPI2. +/// @param interrupt: specifies the SPI interrupt source to check. +/// This parameter can be one of the following values: +/// @arg SPI_IT_TX: Tx buffer empty interrupt +/// @arg SPI_IT_RX: Rx buffer interrupt +/// @arg SPI_IT_UNDERRUN: under Error interrupt in slave mode +/// @arg SPI_IT_RXOVER: RX OVER Error interrupt +/// @arg SPI_IT_RXMATCH: spectials rx data numbers interrupt +/// @arg SPI_IT_RXFULL: Rx buffer full interrupt +/// @arg SPI_IT_TXEPT: Tx buffer and tx shifter empty interrupt +/// @retval The new state of SPI_IT (SET or RESET). +//////////////////////////////////////////////////////////////////////////////// +ITStatus SPI_GetITStatus(SPI_TypeDef* spi, SPI_IT_TypeDef interrupt) +{ + return (spi->ISR & interrupt) ? SET : RESET; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Clears the spi interrupt pending bit. +/// @param spi: Select the SPI peripheral. +/// This parameter can be one of the following values: +/// SPI1, SPI2. +/// @param interrupt: specifies the SPI interrupt pending bit to clear. +/// @arg SPI_IT_TX: Tx buffer empty interrupt +/// @arg SPI_IT_RX: Rx buffer interrupt +/// @arg SPI_IT_UNDERRUN: under Error interrupt in slave mode +/// @arg SPI_IT_RXOVER: RX OVER Error interrupt +/// @arg SPI_IT_RXMATCH: spectials rx data numbers interrupt +/// @arg SPI_IT_RXFULL: Rx buffer full interrupt +/// @arg SPI_IT_TXEPT: Tx buffer and tx shifter empty interrupt +/// This function clears only ERR intetrrupt pending bit. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void SPI_ClearITPendingBit(SPI_TypeDef* spi, SPI_IT_TypeDef interrupt) +{ + SET_BIT(spi->ICR, interrupt); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SPI Hole a count Received bytes in next receive process. +/// @param spi: Select the SPI peripheral. +/// This parameter can be one of the following values: +/// SPI1, SPI2. +/// @param number: specifies the SPI receive Number. +/// This parament can be 1-65535. +/// This function can use only in SPI master single receive mode. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void SPI_RxBytes(SPI_TypeDef* spi, u16 number) +{ + WRITE_REG(spi->RDNR, number); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief slave mode tx data transmit phase adjust set. +/// @param spi: Select the SPI peripheral. +/// This parameter can be one of the following values: +/// SPI1, SPI2. +/// @param adjust_value: slave mode tx data transmit phase adjust enum. +/// This parament can be : +/// SPI_SlaveAdjust_FAST: fast speed use +/// SPI_SlaveAdjust_LOW: low speed use +/// This function can use only in SPI master single receive mode. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void SPI_SlaveAdjust(SPI_TypeDef* spi, SPI_SlaveAdjust_TypeDef adjust_value) +{ + (adjust_value) ? SET_BIT(spi->CCR, SPI_CCR_RXEDGE) : CLEAR_BIT(spi->CCR, SPI_CCR_RXEDGE); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables all SPI interrupts. +/// @param spi: Select the SPI peripheral. +/// This parameter can be one of the following values: +/// SPI1, SPI2. +/// @param state: new state of all spi interrupts. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void exSPI_ITCmd(SPI_TypeDef* spi, FunctionalState state) +{ + (state) ? SET_BIT(spi->IER, (u32)SPI_GCR_IEN) : CLEAR_BIT(spi->IER, (u32)SPI_GCR_IEN); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the specified SPI interrupts. +/// @param spi: Select the SPI peripheral. +/// This parameter can be one of the following values: +/// SPI1, SPI2. +/// @param interrupt: specifies the SPI interrupt sources to be enabled or disabled. +/// This parameter can be one of the following values: +/// @arg SPI_IT_TXEPT: Transmitter empty interrupt +/// @arg SPI_IT_RXFULL: RX FIFO full interrupt +/// @arg SPI_IT_RXMATCH: Receive data match the RXDNR number interrupt +/// @arg SPI_IT_RXOERR: Receive overrun error interrupt +/// @arg SPI_IT_UNDERRUN: underrun interrupt +/// @arg SPI_IT_RX: Receive data available interrupt +/// @arg SPI_IT_TX: Transmit FIFO available interrupt +/// @param state: new state of the specified spi interrupts. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void exSPI_ITConfig(SPI_TypeDef* spi, SPI_IT_TypeDef interrupt, FunctionalState state) +{ + (state) ? SET_BIT(spi->IER, (u32)interrupt) : CLEAR_BIT(spi->IER, (u32)interrupt); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the SPI DMA request. +/// @param spi: Select the SPI peripheral. +/// This parameter can be one of the following values: +/// SPI1, SPI2. +/// @param state: new state of the DMA Request. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void exSPI_DMACmd(SPI_TypeDef* spi, FunctionalState state) +{ + (state) ? SET_BIT(spi->GCR, SPI_GCR_DMAEN) : CLEAR_BIT(spi->GCR, SPI_GCR_DMAEN); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Set or reset Slave chip csn signal output +/// @param spi: Select the SPI peripheral. +/// This parameter can be one of the following values: +/// SPI1, SPI2. +/// @param state: new state of Slave chip csn signal output. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void exSPI_CSInternalSelected(SPI_TypeDef* spi, FunctionalState state) +{ + (state) ? CLEAR_BIT(spi->NSSR, SPI_NSSR_NSS) : SET_BIT(spi->NSSR, SPI_NSSR_NSS); // illogical +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief tx data and rx data phase adjust. +/// @param spi: Select the SPI peripheral. +/// This parameter can be one of the following values: +/// SPI1, SPI2. +/// @param adjust_value: choose adjust mode. +/// This parament can be : +/// SPI_DataEdgeAdjust_LOW, +/// SPI_DataEdgeAdjust_FAST +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void exSPI_DataEdgeAdjust(SPI_TypeDef* spi, SPI_DataEdgeAdjust_TypeDef adjust_value) +{ + // master mode + if (spi->GCR & SPI_GCR_MODE) { + adjust_value ? SET_BIT(spi->CCR, SPI_CCR_RXEDGE) : CLEAR_BIT(spi->CCR, SPI_CCR_RXEDGE); + } + // slave mode + else { + adjust_value ? SET_BIT(spi->CCR, SPI_CCR_TXEDGE) : CLEAR_BIT(spi->CCR, SPI_CCR_TXEDGE); + } +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Set or reset i2s +/// @param spi: Select the SPI peripheral. +/// This parameter can be one of the following values: +/// SPI1, SPI2, SPI3. +/// @param state: new state of Slave chip csn signal output. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void I2S_Cmd(SPI_TypeDef* spi, FunctionalState state) +{ + (state) ? SET_BIT(spi->CFGR, I2S_CFGR_SPI_I2S) : CLEAR_BIT(spi->CFGR, I2S_CFGR_SPI_I2S); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief i2s Config +/// @param spi: Select the SPI peripheral. +/// This parameter can be one of the following values: +/// SPI1, SPI2, SPI3. +/// @param state: new state of Slave chip csn signal output. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void I2S_Init(SPI_TypeDef* spi, I2S_InitTypeDef* I2S_InitStruct) +{ + u32 i2sdiv = 2; + u32 tmpreg = 0; + u32 packetlength = 1; + u32 result = 0, yushu = 0; + u32 sourceclock = 0; + RCC_ClocksTypeDef RCC_Clocks; + + if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) { + i2sdiv = 2; + } + else { + if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) { + packetlength = 1; + } + else { + packetlength = 2; + } + RCC_GetClocksFreq(&RCC_Clocks); + + if((SPI2 == spi) || (SPI3 == spi)) { + sourceclock = RCC_Clocks.PCLK1_Frequency; + } + else { + sourceclock = RCC_Clocks.PCLK2_Frequency; + } + if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) { + result = (sourceclock) / (256 * (I2S_InitStruct->I2S_AudioFreq)); + yushu = (sourceclock) % (256 * (I2S_InitStruct->I2S_AudioFreq)); + if(yushu > (128 * (I2S_InitStruct->I2S_AudioFreq))) { + result = result + 1; + } + i2sdiv = result; + if ((i2sdiv < 2) || (i2sdiv > 0x1FF)) { + i2sdiv = 2; + } + } + else { + result = (sourceclock) / (16 * 2 * packetlength * (I2S_InitStruct->I2S_AudioFreq)); + yushu = (sourceclock) % (16 * 2 * packetlength * (I2S_InitStruct->I2S_AudioFreq)); + if(yushu > ((16 * packetlength * (I2S_InitStruct->I2S_AudioFreq)))) { + result = result + 1; + } + if ((i2sdiv < 1) || (i2sdiv > 0x1FF)) { + i2sdiv = 1; + } + } + } + if(I2S_CPOL_High == I2S_InitStruct->I2S_CPOL) { + spi->CCTL |= SPI_CCR_CPOL; + } + else { + spi->CCTL &= ~SPI_CCR_CPOL; + } + + spi->CFGR = 0x2 << I2S_CFGR_I2SDIV_Pos; + + if((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterTx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_MasterRx)) { + spi->GCTL |= SPI_GCR_MODE; + } + else { + spi->GCTL &= ~SPI_GCR_MODE; + } + if((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterTx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveTx)) { + spi->GCTL |= SPI_GCR_TXEN; + spi->GCTL &= ~SPI_GCR_RXEN; + } + else { + spi->GCTL &= ~SPI_GCR_TXEN; + spi->GCTL |= SPI_GCR_RXEN; + } +// tmpreg = spi->GCTL; +// tmpreg &= ~(1 << 2); +// tmpreg |= (u16)(I2S_InitStruct->I2S_Mode); +// spi->GCTL = tmpreg; +// + tmpreg = 0; + tmpreg |= (i2sdiv << I2S_CFGR_I2SDIV_Pos) | \ + (I2S_InitStruct->I2S_MCLKOutput) | \ + (I2S_CFGR_SPI_I2S) | \ + (I2S_InitStruct->I2S_Standard) | \ + (I2S_InitStruct->I2S_DataFormat); + spi->CFGR &= ~I2S_CFGR_I2SDIV; + spi->CFGR |= tmpreg; + +} +/// @} + +/// @} + +/// @} diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_tim.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_tim.c new file mode 100644 index 000000000..e798bc46a --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_tim.c @@ -0,0 +1,1875 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_tim.c +/// @author AE TEAM +/// @brief THIS FILE PROVIDES ALL THE TIM FIRMWARE FUNCTIONS. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#define _HAL_TIM_C_ + +// Files includes +#include "hal_rcc.h" +#include "hal_tim.h" + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup TIM_HAL +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup TIM_Exported_Functions +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Deinitializes the tim peripheral registers to their default reset values. +/// @param tim: select the TIM peripheral. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_DeInit(TIM_TypeDef* tim) +{ + switch (*(vu32*)&tim) { + case (u32)TIM1: + exRCC_APB2PeriphReset(RCC_APB2ENR_TIM1); + break; + case (u32)TIM2: + exRCC_APB1PeriphReset(RCC_APB1ENR_TIM2); + break; + case (u32)TIM3: + exRCC_APB1PeriphReset(RCC_APB1ENR_TIM3); + break; + case (u32)TIM4: + exRCC_APB1PeriphReset(RCC_APB1ENR_TIM4); + break; + + case (u32)TIM5: + exRCC_APB1PeriphReset(RCC_APB1ENR_TIM5); + break; + case (u32)TIM6: + exRCC_APB1PeriphReset(RCC_APB1ENR_TIM6); + break; + case (u32)TIM7: + exRCC_APB1PeriphReset(RCC_APB1ENR_TIM7); + break; + + case (u32)TIM8: + exRCC_APB2PeriphReset(RCC_APB2ENR_TIM8); + break; + + default: + break; + } +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Initializes the tim Time Base Unit peripheral according to +/// the specified parameters in the init_struct. +/// @param tim: select the TIM peripheral. +/// @param init_struct: pointer to a TIM_TimeBaseInitTypeDef +/// structure that contains the configuration information for the +/// specified TIM peripheral. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_TimeBaseInit(TIM_TypeDef* tim, TIM_TimeBaseInitTypeDef* init_struct) +{ + MODIFY_REG(tim->CR1, TIM_CR1_CKD, init_struct->TIM_ClockDivision); + + if ((tim == TIM1) || (tim == TIM2) || (tim == TIM3) || (tim == TIM4) || (tim == TIM5) || (tim == TIM8)) + MODIFY_REG(tim->CR1, TIM_CR1_CMS | TIM_CR1_DIR, init_struct->TIM_CounterMode); + + if ((tim == TIM1) || (tim == TIM8) ) + + MODIFY_REG(tim->RCR, TIM_RCR_REP, init_struct->TIM_RepetitionCounter); + + WRITE_REG(tim->ARR, init_struct->TIM_Period); + WRITE_REG(tim->PSC, init_struct->TIM_Prescaler); + WRITE_REG(tim->EGR, TIM_PSCReloadMode_Immediate); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Initializes the tim Channel1 according to the specified +/// parameters in the init_struct. +/// @param tim: select the TIM peripheral. +/// @param init_struct: pointer to a TIM_OCInitTypeDef structure that +/// contains the configuration information for the specified TIM peripheral. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_OC1Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct) +{ + MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC1M, init_struct->TIM_OCMode); + MODIFY_REG(tim->CCER, TIM_CCER_CC1P | TIM_CCER_CC1EN, \ + ((u32)init_struct->TIM_OCPolarity) | ((u32)init_struct->TIM_OutputState)); + WRITE_REG(tim->CCR1, init_struct->TIM_Pulse); + + if ((tim == TIM1) || (tim == TIM8)) { + MODIFY_REG(tim->CCER, TIM_CCER_CC1NP | TIM_CCER_CC1NEN, \ + ((u32)init_struct->TIM_OCNPolarity) | ((u32)init_struct->TIM_OutputNState)); + MODIFY_REG(tim->CR2, TIM_CR2_OIS1 | TIM_CR2_OIS1N, \ + ((u32)init_struct->TIM_OCIdleState) | ((u32)init_struct->TIM_OCNIdleState)); + } +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Initializes the tim Channel2 according to the specified +/// parameters in the init_struct. +/// @param tim: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. +/// @param init_struct: pointer to a TIM_OCInitTypeDef structure that +/// contains the configuration information for the specified TIM peripheral. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_OC2Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct) +{ + MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC2M, init_struct->TIM_OCMode << 8); + MODIFY_REG(tim->CCER, TIM_CCER_CC2EN | TIM_CCER_CC2P, \ + (init_struct->TIM_OCPolarity << 4) | (init_struct->TIM_OutputState << 4)); + WRITE_REG(tim->CCR2, init_struct->TIM_Pulse); + + if ((tim == TIM1) || (tim == TIM8)) { + MODIFY_REG(tim->CCER, TIM_CCER_CC2NP | TIM_CCER_CC2NEN, \ + (init_struct->TIM_OCNPolarity << 4) | (init_struct->TIM_OutputNState << 4)); + MODIFY_REG(tim->CR2, TIM_CR2_OIS2 | TIM_CR2_OIS2N, \ + (init_struct->TIM_OCIdleState << 2) | (init_struct->TIM_OCNIdleState << 2)); + } +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Initializes the tim Channel3 according to the specified +/// parameters in the init_struct. +/// @param tim: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. +/// @param init_struct: pointer to a TIM_OCInitTypeDef structure that +/// contains the configuration information for the specified TIM peripheral. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_OC3Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct) +{ + MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC3M, init_struct->TIM_OCMode); + MODIFY_REG(tim->CCER, TIM_CCER_CC3EN | TIM_CCER_CC3P, \ + (init_struct->TIM_OCPolarity << 8) | (init_struct->TIM_OutputState << 8)); + WRITE_REG(tim->CCR3, init_struct->TIM_Pulse); + + if ((tim == TIM1) || (tim == TIM8)) { + MODIFY_REG(tim->CCER, TIM_CCER_CC3NP | TIM_CCER_CC3NEN, \ + (init_struct->TIM_OCNPolarity << 8) | (init_struct->TIM_OutputNState << 8)); + MODIFY_REG(tim->CR2, TIM_CR2_OIS3 | TIM_CR2_OIS3N, \ + (init_struct->TIM_OCIdleState << 4) | (init_struct->TIM_OCNIdleState << 4)); + } +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Initializes the tim Channel4 according to the specified +/// parameters in the init_struct. +/// @param tim:select the TIM peripheral. +/// @param init_struct: pointer to a TIM_OCInitTypeDef structure that +/// contains the configuration information for the specified TIM peripheral. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_OC4Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct) +{ + MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC4M, (init_struct->TIM_OCMode) << 8); + MODIFY_REG(tim->CCER, TIM_CCER_CC4EN | TIM_CCER_CC4P, \ + (init_struct->TIM_OCPolarity << 12) | (init_struct->TIM_OutputState << 12)); + WRITE_REG(tim->CCR4, init_struct->TIM_Pulse); + + if ((tim == TIM1) || (tim == TIM8)) + MODIFY_REG(tim->CR2, TIM_CR2_OIS4, init_struct->TIM_OCIdleState << 6); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Initializes the TIM peripheral according to the specified +/// parameters in the init_struct. +/// @param tim: select the TIM peripheral. +/// @param init_struct: pointer to a TIM_ICInitTypeDef structure that +/// contains the configuration information for the specified TIM peripheral. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_ICInit(TIM_TypeDef* tim, TIM_ICInitTypeDef* init_struct) +{ + switch (init_struct->TIM_Channel) { + case TIM_Channel_1: + TI1_Configure(tim, init_struct->TIM_ICPolarity, init_struct->TIM_ICSelection, init_struct->TIM_ICFilter); + TIM_SetIC1Prescaler(tim, init_struct->TIM_ICPrescaler); + break; + case TIM_Channel_2: + TI2_Configure(tim, init_struct->TIM_ICPolarity, init_struct->TIM_ICSelection, init_struct->TIM_ICFilter); + TIM_SetIC2Prescaler(tim, init_struct->TIM_ICPrescaler); + break; + case TIM_Channel_3: + TI3_Configure(tim, init_struct->TIM_ICPolarity, init_struct->TIM_ICSelection, init_struct->TIM_ICFilter); + TIM_SetIC3Prescaler(tim, init_struct->TIM_ICPrescaler); + break; + case TIM_Channel_4: + TI4_Configure(tim, init_struct->TIM_ICPolarity, init_struct->TIM_ICSelection, init_struct->TIM_ICFilter); + TIM_SetIC4Prescaler(tim, init_struct->TIM_ICPrescaler); + break; + default: + break; + } +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the TIM peripheral according to the specified +/// parameters in the init_struct to measure an external PWM signal. +/// @param tim: select the TIM peripheral. +/// @param init_struct: pointer to a TIM_ICInitTypeDef structure that +/// contains the configuration information for the specified TIM peripheral. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_PWMIConfig(TIM_TypeDef* tim, TIM_ICInitTypeDef* init_struct) +{ + u16 icoppositepolarity = TIM_ICPolarity_Rising; + u16 icoppositeselection = TIM_ICSelection_DirectTI; + icoppositepolarity = (init_struct->TIM_ICPolarity == TIM_ICPolarity_Rising) ? TIM_ICPolarity_Falling : TIM_ICPolarity_Rising; + icoppositeselection = + (init_struct->TIM_ICSelection == TIM_ICSelection_DirectTI) ? TIM_ICSelection_IndirectTI : TIM_ICSelection_DirectTI; + if (init_struct->TIM_Channel == TIM_Channel_1) { + TI1_Configure(tim, init_struct->TIM_ICPolarity, init_struct->TIM_ICSelection, init_struct->TIM_ICFilter); + TIM_SetIC1Prescaler(tim, init_struct->TIM_ICPrescaler); + TI2_Configure(tim, icoppositepolarity, icoppositeselection, init_struct->TIM_ICFilter); + TIM_SetIC2Prescaler(tim, init_struct->TIM_ICPrescaler); + } + else { + TI2_Configure(tim, init_struct->TIM_ICPolarity, init_struct->TIM_ICSelection, init_struct->TIM_ICFilter); + TIM_SetIC2Prescaler(tim, init_struct->TIM_ICPrescaler); + TI1_Configure(tim, icoppositepolarity, icoppositeselection, init_struct->TIM_ICFilter); + TIM_SetIC1Prescaler(tim, init_struct->TIM_ICPrescaler); + } +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the: Break feature, dead time, Lock level, the OSSI, +/// the OSSR State and the AOE(automatic output enable). +/// @param tim: select the TIM +/// @param init_struct: pointer to a TIM_BDTRInitTypeDef structure that +/// contains the BDTR Register configuration information for the TIM peripheral. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_BDTRConfig(TIM_TypeDef* tim, TIM_BDTRInitTypeDef* init_struct) +{ + tim->BDTR = (u32)init_struct->TIM_OSSRState | init_struct->TIM_OSSIState | init_struct->TIM_LOCKLevel | + init_struct->TIM_DeadTime | init_struct->TIM_Break | init_struct->TIM_BreakPolarity | + init_struct->TIM_AutomaticOutput; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Fills each init_struct member with its default value. +/// @param init_struct : pointer to a TIM_TimeBaseInitTypeDef +/// structure which will be initialized. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* init_struct) +{ + init_struct->TIM_Period = 0xFFFFFFFF; + init_struct->TIM_Prescaler = 0x0000; + init_struct->TIM_ClockDivision = TIM_CKD_DIV1; + init_struct->TIM_CounterMode = TIM_CounterMode_Up; + init_struct->TIM_RepetitionCounter = 0x00; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Fills each init_struct member with its default value. +/// @param init_struct : pointer to a TIM_OCInitTypeDef structure which will +/// be initialized. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_OCStructInit(TIM_OCInitTypeDef* init_struct) +{ + init_struct->TIM_OCMode = TIM_OCMode_Timing; + init_struct->TIM_OutputState = TIM_OutputState_Disable; + init_struct->TIM_OutputNState = TIM_OutputNState_Disable; + init_struct->TIM_Pulse = 0x00000000; + init_struct->TIM_OCPolarity = TIM_OCPolarity_High; + init_struct->TIM_OCNPolarity = TIM_OCNPolarity_High; + init_struct->TIM_OCIdleState = TIM_OCIdleState_Reset; + init_struct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Fills each init_struct member with its default value. +/// @param init_struct: pointer to a TIM_ICInitTypeDef structure which will +/// be initialized. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_ICStructInit(TIM_ICInitTypeDef* init_struct) +{ + init_struct->TIM_Channel = TIM_Channel_1; + init_struct->TIM_ICPolarity = TIM_ICPolarity_Rising; + init_struct->TIM_ICSelection = TIM_ICSelection_DirectTI; + init_struct->TIM_ICPrescaler = TIM_ICPSC_DIV1; + init_struct->TIM_ICFilter = 0x00; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Fills each init_struct member with its default value. +/// @param init_struct: pointer to a TIM_BDTRInitTypeDef structure which +/// will be initialized. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* init_struct) +{ + init_struct->TIM_OSSRState = TIM_OSSRState_Disable; + init_struct->TIM_OSSIState = TIM_OSSIState_Disable; + init_struct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; + init_struct->TIM_DeadTime = 0x00; + init_struct->TIM_Break = TIM_Break_Disable; + init_struct->TIM_BreakPolarity = TIM_BreakPolarity_Low; + init_struct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the specified TIM peripheral. +/// @param tim: where x can be 1 to 17 to select the tim peripheral. +/// @param state: new state of the tim peripheral. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_Cmd(TIM_TypeDef* tim, FunctionalState state) +{ + (state) ? SET_BIT(tim->CR1, TIM_CR1_CEN) : CLEAR_BIT(tim->CR1, TIM_CR1_CEN); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the TIM peripheral Main Outputs. +/// @param tim: where x can be 1, 8, 16 or 17 to select the tim peripheral. +/// @param state: new state of the TIM peripheral Main Outputs. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_CtrlPWMOutputs(TIM_TypeDef* tim, FunctionalState state) +{ + (state) ? SET_BIT(tim->BDTR, TIM_BDTR_MOEN) : CLEAR_BIT(tim->BDTR, TIM_BDTR_MOEN); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the specified TIM interrupts. +/// @param tim: select the tim peripheral. +/// @param it: specifies the TIM interrupts sources to be enabled or disabled. +/// This parameter can be any combination of the following values: +/// @arg TIM_IT_Update: TIM update Interrupt source +/// @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source +/// @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source +/// @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source +/// @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source +/// @arg TIM_IT_COM: TIM Commutation Interrupt source +/// @arg TIM_IT_Trigger: TIM Trigger Interrupt source +/// @arg TIM_IT_Break: TIM Break Interrupt source +/// @note +/// - Partial timer can have TIM_IT_Update or TIM_IT_CC1. +/// - TIM_IT_Break is used only with partial timer. +/// - TIM_IT_COM is used only with partial timer. +/// @param state: new state of the TIM interrupts. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_ITConfig(TIM_TypeDef* tim, u32 it, FunctionalState state) //TIMIT_TypeDef +{ + (state) ? SET_BIT(tim->DIER, it) : CLEAR_BIT(tim->DIER, it); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the tim event to be generate by software. +/// @param tim: select the TIM peripheral. +/// @param source: specifies the event source. +/// This parameter can be one or more of the following values: +/// @arg TIM_EventSource_Update: Timer update Event source +/// @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source +/// @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source +/// @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source +/// @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source +/// @arg TIM_EventSource_COM: Timer COM event source +/// @arg TIM_EventSource_Trigger: Timer Trigger Event source +/// @arg TIM_EventSource_Break: Timer Break event source +/// @note +/// - TIM_EventSource_COM and TIM_EventSource_Break are used only with partial timer. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_GenerateEvent(TIM_TypeDef* tim, TIMEGR_Typedef source) +{ + WRITE_REG(tim->EGR, source); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the tim's DMA interface. +/// @param tim: select the TIM peripheral. +/// @param dma_base: DMA Base address. +/// This parameter can be one of the following values: +/// @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR, +/// TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR, +/// TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER, +/// TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR, +/// TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2, +/// TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR, +/// TIM_DMABase_DCR. +/// @param length: DMA Burst length. +/// This parameter can be one value between: +/// TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_DMAConfig(TIM_TypeDef* tim, TIMDMABASE_Typedef dma_base, TIMDMABURSTLENGTH_Typedef length) +{ + WRITE_REG(tim->DCR, ((u32)dma_base) | ((u32)length)); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the tim's DMA Requests. +/// @param tim: select the TIM peripheral. +/// @param source: specifies the DMA Request sources. +/// This parameter can be any combination of the following values: +/// @arg TIM_DMA_Update: TIM update Interrupt source +/// @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source +/// @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source +/// @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source +/// @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source +/// @arg TIM_DMA_COM: TIM Commutation DMA source +/// @arg TIM_DMA_Trigger: TIM Trigger DMA source +/// @param state: new state of the DMA Request sources. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_DMACmd(TIM_TypeDef* tim, TIMDMASRC_Typedef source, FunctionalState state) +{ + (state) ? SET_BIT(tim->DIER, source) : CLEAR_BIT(tim->DIER, source); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the tim internal Clock +/// @param tim: select the TIM peripheral. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_InternalClockConfig(TIM_TypeDef* tim) +{ + CLEAR_BIT(tim->SMCR, TIM_SMCR_SMS); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the tim Internal Trigger as External Clock +/// @param tim: select the TIM peripheral. +/// @param source: Trigger source. +/// This parameter can be one of the following values: +/// @arg TIM_TS_ITR0: Internal Trigger 0 +/// @arg TIM_TS_ITR1: Internal Trigger 1 +/// @arg TIM_TS_ITR2: Internal Trigger 2 +/// @arg TIM_TS_ITR3: Internal Trigger 3 +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_ITRxExternalClockConfig(TIM_TypeDef* tim, TIMTS_TypeDef source) +{ + TIM_SelectInputTrigger(tim, source); + SET_BIT(tim->SMCR, TIM_SlaveMode_External1); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the tim Trigger as External Clock +/// @param tim: select the TIM peripheral. +/// @param source: Trigger source. +/// This parameter can be one of the following values: +/// @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector +/// @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1 +/// @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2 +/// @param polarity: specifies the TIx Polarity. +/// This parameter can be one of the following values: +/// @arg TIM_ICPolarity_Rising +/// @arg TIM_ICPolarity_Falling +/// @param filter : specifies the filter value. +/// This parameter must be a value between 0x0 and 0xF. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_TIxExternalClockConfig(TIM_TypeDef* tim, TIM_TIEXTCLKSRC_Typedef source, TIMICP_Typedef polarity, u16 filter) +{ + (source == TIM_TIxExternalCLK1Source_TI2) ? (TI2_Configure(tim, polarity, TIM_ICSelection_DirectTI, filter)) + : (TI1_Configure(tim, polarity, TIM_ICSelection_DirectTI, filter)); + TIM_SelectInputTrigger(tim, (TIMTS_TypeDef)source); + SET_BIT(tim->SMCR, TIM_SlaveMode_External1); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the tim External Trigger (ETR). +/// @param tim: select the TIM peripheral. +/// @param psc: The external Trigger Prescaler. +/// This parameter can be one of the following values: +/// @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. +/// @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. +/// @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. +/// @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. +/// @param polarity: The external Trigger Polarity. +/// This parameter can be one of the following values: +/// @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. +/// @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. +/// @param filter: External Trigger Filter. +/// This parameter must be a value between 0x00 and 0x0F +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_ETRConfig(TIM_TypeDef* tim, TIMEXTTRGPSC_Typedef psc, TIMETP_Typedef polarity, u16 filter) +{ + CLEAR_BIT(tim->SMCR, TIM_SMCR_ECEN); + MODIFY_REG(tim->SMCR, TIM_SMCR_ETP, polarity); + MODIFY_REG(tim->SMCR, TIM_SMCR_ETPS, psc); + MODIFY_REG(tim->SMCR, TIM_SMCR_ETF, filter << 8); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the External clock Mode1 +/// @param tim: select the TIM peripheral. +/// @param psc: The external Trigger Prescaler. +/// This parameter can be one of the following values: +/// @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. +/// @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. +/// @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. +/// @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. +/// @param polarity: The external Trigger Polarity. +/// This parameter can be one of the following values: +/// @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. +/// @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. +/// @param filter: External Trigger Filter. +/// This parameter must be a value between 0x00 and 0x0F +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_ETRClockMode1Config(TIM_TypeDef* tim, TIMEXTTRGPSC_Typedef psc, TIMETP_Typedef polarity, u16 filter) +{ + TIM_ETRConfig(tim, psc, polarity, filter); + MODIFY_REG(tim->SMCR, TIM_SMCR_TS | TIM_SMCR_SMS, ((u32)TIM_TS_ETRF) | ((u32)TIM_SlaveMode_External1)); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the External clock Mode2 +/// @param tim: select the TIM peripheral. +/// @param psc: The external Trigger Prescaler. +/// This parameter can be one of the following values: +/// @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. +/// @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. +/// @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. +/// @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. +/// @param polarity: The external Trigger Polarity. +/// This parameter can be one of the following values: +/// @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. +/// @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. +/// @param filter: External Trigger Filter. +/// This parameter must be a value between 0x00 and 0x0F +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_ETRClockMode2Config(TIM_TypeDef* tim, TIMEXTTRGPSC_Typedef psc, TIMETP_Typedef polarity, u16 filter) +{ + TIM_ETRConfig(tim, psc, polarity, filter); + SET_BIT(tim->SMCR, TIM_SMCR_ECEN); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the tim Prescaler. +/// @param tim: select the TIM peripheral. +/// @param prescaler: specifies the Prescaler Register value +/// @param reloadMode: specifies the TIM Prescaler Reload mode +/// This parameter can be one of the following values: +/// @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event. +/// @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediately. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_PrescalerConfig(TIM_TypeDef* tim, u16 prescaler, TIMUG_Typedef reloadMode) +{ + WRITE_REG(tim->PSC, prescaler); + WRITE_REG(tim->EGR, reloadMode); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Specifies the tim Counter Mode to be used. +/// @param tim:select the TIM peripheral. +/// @param counter_mode: specifies the Counter Mode to be used +/// This parameter can be one of the following values: +/// @arg TIM_CounterMode_Up: TIM Up Counting Mode +/// @arg TIM_CounterMode_Down: TIM Down Counting Mode +/// @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 +/// @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 +/// @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_CounterModeConfig(TIM_TypeDef* tim, TIMCOUNTMODE_Typedef counter_mode) +{ + MODIFY_REG(tim->CR1, TIM_CR1_CMS | TIM_CR1_DIR, counter_mode); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Selects the Input Trigger source +/// @param tim: select the TIM peripheral. +/// @param source: The Input Trigger source. +/// This parameter can be one of the following values: +/// @arg TIM_TS_ITR0: Internal Trigger 0 +/// @arg TIM_TS_ITR1: Internal Trigger 1 +/// @arg TIM_TS_ITR2: Internal Trigger 2 +/// @arg TIM_TS_ITR3: Internal Trigger 3 +/// @arg TIM_TS_TI1F_ED: TI1 Edge Detector +/// @arg TIM_TS_TI1FP1: Filtered Timer Input 1 +/// @arg TIM_TS_TI2FP2: Filtered Timer Input 2 +/// @arg TIM_TS_ETRF: External Trigger input +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_SelectInputTrigger(TIM_TypeDef* tim, TIMTS_TypeDef source) +{ + MODIFY_REG(tim->SMCR, TIM_SMCR_TS, source); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the tim Encoder Interface. +/// @param tim: select the TIM peripheral. +/// @param encoder_mode: specifies the tim Encoder Mode. +/// This parameter can be one of the following values: +/// @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level. +/// @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level. +/// @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending +/// on the level of the other input. +/// @param ic1_polarity: specifies the IC1 Polarity +/// This parameter can be one of the following values: +/// @arg TIM_ICPolarity_Falling: IC Falling edge. +/// @arg TIM_ICPolarity_Rising: IC Rising edge. +/// @param ic2_polarity: specifies the IC2 Polarity +/// This parameter can be one of the following values: +/// @arg TIM_ICPolarity_Falling: IC Falling edge. +/// @arg TIM_ICPolarity_Rising: IC Rising edge. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_EncoderInterfaceConfig(TIM_TypeDef* tim, + TIMSMSENCODER_Typedef encoder_mode, + TIMICP_Typedef ic1_polarity, + TIMICP_Typedef ic2_polarity) +{ + MODIFY_REG(tim->SMCR, TIM_SMCR_SMS, encoder_mode); + MODIFY_REG(tim->CCMR1, TIM_CCMR1_CC1S | TIM_CCMR1_CC2S, TIM_CCMR1_CC1S_DIRECTTI | TIM_CCMR1_CC2S_DIRECTTI); + MODIFY_REG(tim->CCER, TIM_CCER_CC1P | TIM_CCER_CC2P, ic1_polarity | (ic2_polarity << 4)); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Forces the tim output 1 waveform to active or inactive level. +/// @param tim: select the TIM peripheral. +/// @param forced_action: specifies the forced Action to be set to the output waveform. +/// This parameter can be one of the following values: +/// @arg TIM_ForcedAction_Active: Force active level on OC1REF +/// @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_ForcedOC1Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action) +{ + MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC1M, forced_action); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Forces the tim output 2 waveform to active or inactive level. +/// @param tim: select the TIM peripheral. +/// @param forced_action: specifies the forced Action to be set to the output waveform. +/// This parameter can be one of the following values: +/// @arg TIM_ForcedAction_Active: Force active level on OC2REF +/// @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_ForcedOC2Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action) +{ + MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC2M, forced_action << 8); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Forces the tim output 3 waveform to active or inactive level. +/// @param tim: select the TIM peripheral. +/// @param forced_action: specifies the forced Action to be set to the output waveform. +/// This parameter can be one of the following values: +/// @arg TIM_ForcedAction_Active: Force active level on OC3REF +/// @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_ForcedOC3Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action) +{ + MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC3M, forced_action); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Forces the tim output 4 waveform to active or inactive level. +/// @param tim: select the TIM peripheral. +/// @param forced_action: specifies the forced Action to be set to the output waveform. +/// This parameter can be one of the following values: +/// @arg TIM_ForcedAction_Active: Force active level on OC4REF +/// @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_ForcedOC4Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action) +{ + MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC4M, forced_action << 8); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables tim peripheral Preload register on ARR. +/// @param tim: select the TIM peripheral. +/// @param state: new state of the tim peripheral Preload register +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_ARRPreloadConfig(TIM_TypeDef* tim, FunctionalState state) +{ + (state) ? SET_BIT(tim->CR1, TIM_CR1_ARPEN) : CLEAR_BIT(tim->CR1, TIM_CR1_ARPEN); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Selects the TIM peripheral Commutation event. +/// @param tim: select the tim peripheral. +/// @param state: new state of the Commutation event. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_SelectCOM(TIM_TypeDef* tim, FunctionalState state) +{ + (state) ? SET_BIT(tim->CR2, TIM_CR2_CCUS) : CLEAR_BIT(tim->CR2, TIM_CR2_CCUS); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Selects the tim peripheral Capture Compare DMA source. +/// @param tim: select the TIM peripheral. +/// @param state: new state of the Capture Compare DMA source +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_SelectCCDMA(TIM_TypeDef* tim, FunctionalState state) +{ + (state) ? SET_BIT(tim->CR2, TIM_CR2_CCDS) : CLEAR_BIT(tim->CR2, TIM_CR2_CCDS); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit. +/// @param tim: select the tim peripheral. +/// @param state: new state of the Capture Compare Preload Control bit +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_CCPreloadControl(TIM_TypeDef* tim, FunctionalState state) +{ + (state) ? SET_BIT(tim->CR2, TIM_CR2_CCPC) : CLEAR_BIT(tim->CR2, TIM_CR2_CCPC); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the tim peripheral Preload register on CCR1. +/// @param tim: select the TIM peripheral. +/// @param preload: new state of the tim peripheral Preload register +/// This parameter can be one of the following values: +/// @arg TIM_OCPreload_Enable +/// @arg TIM_OCPreload_Disable +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_OC1PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload) +{ + MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC1PEN, preload); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the tim peripheral Preload register on CCR2. +/// @param tim: select the TIM peripheral. +/// @param preload: new state of the tim peripheral Preload register +/// This parameter can be one of the following values: +/// @arg TIM_OCPreload_Enable +/// @arg TIM_OCPreload_Disable +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_OC2PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload) +{ + MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC2PEN, preload << 8); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the tim peripheral Preload register on CCR3. +/// @param tim: select the TIM peripheral. +/// @param preload: new state of the tim peripheral Preload register +/// This parameter can be one of the following values: +/// @arg TIM_OCPreload_Enable +/// @arg TIM_OCPreload_Disable +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_OC3PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload) +{ + MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC3PEN, preload); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the tim peripheral Preload register on CCR4. +/// @param tim: select the TIM peripheral. +/// @param preload: new state of the tim peripheral Preload register +/// This parameter can be one of the following values: +/// @arg TIM_OCPreload_Enable +/// @arg TIM_OCPreload_Disable +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_OC4PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload) +{ + MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC4PEN, preload << 8); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the tim Output Compare 1 Fast feature. +/// @param tim: select the TIM peripheral. +/// @param fast: new state of the Output Compare Fast Enable Bit. +/// This parameter can be one of the following values: +/// @arg TIM_OCFast_Enable: TIM output compare fast enable +/// @arg TIM_OCFast_Disable: TIM output compare fast disable +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_OC1FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast) +{ + MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC1FEN, fast); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the tim Output Compare 2 Fast feature. +/// @param tim: select the TIM peripheral. +/// @param fast: new state of the Output Compare Fast Enable Bit. +/// This parameter can be one of the following values: +/// @arg TIM_OCFast_Enable: TIM output compare fast enable +/// @arg TIM_OCFast_Disable: TIM output compare fast disable +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_OC2FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast) +{ + MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC2FEN, fast << 8); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the tim Output Compare 3 Fast feature. +/// @param tim: select the TIM peripheral. +/// @param fast: new state of the Output Compare Fast Enable Bit. +/// This parameter can be one of the following values: +/// @arg TIM_OCFast_Enable: TIM output compare fast enable +/// @arg TIM_OCFast_Disable: TIM output compare fast disable +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_OC3FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast) +{ + MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC3FEN, fast); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the tim Output Compare 4 Fast feature. +/// @param tim: select the TIM peripheral. +/// @param fast: new state of the Output Compare Fast Enable Bit. +/// This parameter can be one of the following values: +/// @arg TIM_OCFast_Enable: TIM output compare fast enable +/// @arg TIM_OCFast_Disable: TIM output compare fast disable +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_OC4FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast) +{ + MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC4FEN, fast << 8); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Clears or safeguards the OCREF1 signal on an external event +/// @param tim: select the TIM peripheral. +/// @param clear: new state of the Output Compare Clear Enable Bit. +/// This parameter can be one of the following values: +/// @arg TIM_OCClear_Enable: TIM Output clear enable +/// @arg TIM_OCClear_Disable: TIM Output clear disable +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_ClearOC1Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear) +{ + MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC1CEN, clear); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Clears or safeguards the OCREF2 signal on an external event +/// @param tim: select the TIM peripheral. +/// @param clear: new state of the Output Compare Clear Enable Bit. +/// This parameter can be one of the following values: +/// @arg TIM_OCClear_Enable: TIM Output clear enable +/// @arg TIM_OCClear_Disable: TIM Output clear disable +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_ClearOC2Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear) +{ + MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC2CEN, clear << 8); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Clears or safeguards the OCREF3 signal on an external event +/// @param tim: select the TIM peripheral. +/// @param clear: new state of the Output Compare Clear Enable Bit. +/// This parameter can be one of the following values: +/// @arg TIM_OCClear_Enable: TIM Output clear enable +/// @arg TIM_OCClear_Disable: TIM Output clear disable +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_ClearOC3Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear) +{ + MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC3CEN, clear); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Clears or safeguards the OCREF4 signal on an external event +/// @param tim: select the TIM peripheral. +/// @param clear: new state of the Output Compare Clear Enable Bit. +/// This parameter can be one of the following values: +/// @arg TIM_OCClear_Enable: TIM Output clear enable +/// @arg TIM_OCClear_Disable: TIM Output clear disable +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_ClearOC4Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear) +{ + MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC4CEN, clear << 8); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the tim channel 1 polarity. +/// @param tim: select the TIM peripheral. +/// @param polarity: specifies the OC1 Polarity +/// This parameter can be one of the following values: +/// @arg TIM_OCPolarity_High: Output Compare active high +/// @arg TIM_OCPolarity_Low: Output Compare active low +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_OC1PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity) +{ + MODIFY_REG(tim->CCER, TIM_CCER_CC1P, polarity); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the tim Channel 1N polarity. +/// @param tim: select the TIM peripheral. +/// @param polarity: specifies the OC1N Polarity +/// This parameter can be one of the following values: +/// @arg TIM_OCNPolarity_High: Output Compare active high +/// @arg TIM_OCNPolarity_Low: Output Compare active low +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_OC1NPolarityConfig(TIM_TypeDef* tim, TIMCCxNP_Typedef polarity) +{ + MODIFY_REG(tim->CCER, TIM_CCER_CC1NP, polarity); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the tim channel 2 polarity. +/// @param tim: select the TIM peripheral. +/// @param polarity: specifies the OC2 Polarity +/// This parameter can be one of the following values: +/// @arg TIM_OCPolarity_High: Output Compare active high +/// @arg TIM_OCPolarity_Low: Output Compare active low +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_OC2PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity) +{ + MODIFY_REG(tim->CCER, TIM_CCER_CC2P, polarity << 4); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the tim Channel 2N polarity. +/// @param tim: select the TIM peripheral. +/// @param polarity: specifies the OC2N Polarity +/// This parameter can be one of the following values: +/// @arg TIM_OCNPolarity_High: Output Compare active high +/// @arg TIM_OCNPolarity_Low: Output Compare active low +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_OC2NPolarityConfig(TIM_TypeDef* tim, TIMCCxNP_Typedef polarity) +{ + MODIFY_REG(tim->CCER, TIM_CCER_CC2NP, polarity << 4); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the tim channel 3 polarity. +/// @param tim: select the TIM peripheral. +/// @param polarity: specifies the OC3 Polarity +/// This parameter can be one of the following values: +/// @arg TIM_OCPolarity_High: Output Compare active high +/// @arg TIM_OCPolarity_Low: Output Compare active low +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_OC3PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity) +{ + MODIFY_REG(tim->CCER, TIM_CCER_CC3P, polarity << 8); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the tim Channel 3N polarity. +/// @param tim: select the TIM peripheral. +/// @param polarity: specifies the OC3N Polarity +/// This parameter can be one of the following values: +/// @arg TIM_OCNPolarity_High: Output Compare active high +/// @arg TIM_OCNPolarity_Low: Output Compare active low +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_OC3NPolarityConfig(TIM_TypeDef* tim, TIMCCxNP_Typedef polarity) +{ + MODIFY_REG(tim->CCER, TIM_CCER_CC3NP, polarity << 8); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the tim channel 4 polarity. +/// @param tim: select the TIM peripheral. +/// @param polarity: specifies the OC4 Polarity +/// This parameter can be one of the following values: +/// @arg TIM_OCPolarity_High: Output Compare active high +/// @arg TIM_OCPolarity_Low: Output Compare active low +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_OC4PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity) +{ + MODIFY_REG(tim->CCER, TIM_CCER_CC4P, polarity << 12); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the TIM Capture Compare Channel x. +/// @param tim: select the TIM peripheral. +/// @param channel: specifies the TIM Channel +/// This parameter can be one of the following values: +/// @arg TIM_Channel_1: TIM Channel 1 +/// @arg TIM_Channel_2: TIM Channel 2 +/// @arg TIM_Channel_3: TIM Channel 3 +/// @arg TIM_Channel_4: TIM Channel 4 +/// @arg TIM_Channel_5: TIM Channel 5(Only for some MM32 TIM1/8) +/// @param TIM_CCx: specifies the TIM Channel CCxE bit new state. +/// This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_CCxCmd(TIM_TypeDef* tim, TIMCHx_Typedef channel, TIMCCxE_Typedef ccx_en) +{ + MODIFY_REG(tim->CCER, TIM_CCER_CC1EN << channel, ccx_en << channel); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the TIM Capture Compare Channel xN. +/// @param tim: select the TIM peripheral. +/// @param channel: specifies the TIM Channel +/// This parameter can be one of the following values: +/// @arg TIM_Channel_1: TIM Channel 1 +/// @arg TIM_Channel_2: TIM Channel 2 +/// @arg TIM_Channel_3: TIM Channel 3 +/// @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state. +/// This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_CCxNCmd(TIM_TypeDef* tim, TIMCHx_Typedef channel, TIMCCxNE_Typedef ccxn_en) +{ + if (channel != TIM_Channel_4) + MODIFY_REG(tim->CCER, TIM_CCER_CC1NEN << channel, ccxn_en << channel); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Selects the TIM Output Compare Mode. +/// @note This function disables the selected channel before changing the Output +/// Compare Mode. +/// User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions. +/// @param tim: select the TIM peripheral. +/// @param channel: specifies the TIM Channel +/// This parameter can be one of the following values: +/// @arg TIM_Channel_1: TIM Channel 1 +/// @arg TIM_Channel_2: TIM Channel 2 +/// @arg TIM_Channel_3: TIM Channel 3 +/// @arg TIM_Channel_4: TIM Channel 4 +/// @param mode: specifies the TIM Output Compare Mode. +/// This parameter can be one of the following values: +/// @arg TIM_OCMode_Timing +/// @arg TIM_OCMode_Active +/// @arg TIM_OCMode_Toggle +/// @arg TIM_OCMode_PWM1 +/// @arg TIM_OCMode_PWM2 +/// @arg TIM_ForcedAction_Active +/// @arg TIM_ForcedAction_InActive +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_SelectOCxM(TIM_TypeDef* tim, TIMCHx_Typedef channel, TIMOCMODE_Typedef mode) +{ + CLEAR_BIT(tim->CCER, TIM_CCER_CC1EN << channel); + switch (channel) { + case TIM_Channel_1: + MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC1M, mode); + break; + case TIM_Channel_2: + MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC2M, mode << 8); + break; + case TIM_Channel_3: + MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC3M, mode); + break; + case TIM_Channel_4: + MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC4M, mode << 8); + break; + default: + break; + } +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or Disables the tim Update event. +/// @param tim: select the TIM peripheral. +/// @param state: new state of the tim UDIS bit +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_UpdateDisableConfig(TIM_TypeDef* tim, FunctionalState state) +{ + (state) ? SET_BIT(tim->CR1, TIM_CR1_UDIS) : CLEAR_BIT(tim->CR1, TIM_CR1_UDIS); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the tim Update Request Interrupt source. +/// @param tim: select the TIM peripheral. +/// @param source: specifies the Update source. +/// This parameter can be one of the following values: +/// @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow +/// or the setting of UG bit, or an update generation +/// through the slave mode controller. +/// @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_UpdateRequestConfig(TIM_TypeDef* tim, TIMURS_Typedef source) +{ + MODIFY_REG(tim->CR1, TIM_CR1_URS, source); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the tim's Hall sensor interface. +/// @param tim: select the TIM peripheral. +/// @param state: new state of the tim Hall sensor interface. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_SelectHallSensor(TIM_TypeDef* tim, FunctionalState state) +{ + (state) ? SET_BIT(tim->CR2, TIM_CR2_TI1S) : CLEAR_BIT(tim->CR2, TIM_CR2_TI1S); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Selects the tim's One Pulse Mode. +/// @param tim: select the TIM peripheral. +/// @param mode: specifies the OPM Mode to be used. +/// This parameter can be one of the following values: +/// @arg TIM_OPMode_Single +/// @arg TIM_OPMode_Repetitive +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_SelectOnePulseMode(TIM_TypeDef* tim, TIMOPMODE_Typedef mode) +{ + MODIFY_REG(tim->CR1, TIM_CR1_OPM, mode); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Selects the tim Trigger Output Mode. +/// @param tim:select the TIM peripheral. +/// @param source: specifies the Trigger Output source. +/// This paramter can be one of the following values: +/// - For all tim +/// @arg TIM_TRIGSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRIG). +/// @arg TIM_TRIGSource_Enable: The Counter Enable CEN is used as the trigger output (TRIG). +/// @arg TIM_TRIGSource_Update: The update event is selected as the trigger output (TRIG). +/// @arg TIM_TRIGSource_OC1: The trigger output sends a positive pulse when the CC1IF flag +/// is to be set, as soon as a capture or compare match occurs (TRIG). +/// @arg TIM_TRIGSource_OC1Ref: OC1REF signal is used as the trigger output (TRIG). +/// @arg TIM_TRIGSource_OC2Ref: OC2REF signal is used as the trigger output (TRIG). +/// @arg TIM_TRIGSource_OC3Ref: OC3REF signal is used as the trigger output (TRIG). +/// @arg TIM_TRIGSource_OC4Ref: OC4REF signal is used as the trigger output (TRIG). +/// +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_SelectOutputTrigger(TIM_TypeDef* tim, TIMMMS_Typedef source) +{ + MODIFY_REG(tim->CR2, TIM_CR2_MMS, source); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Selects the tim Slave Mode. +/// @param tim: select the TIM peripheral. +/// @param mode: specifies the Timer Slave Mode. +/// This parameter can be one of the following values: +/// @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes +/// the counter and triggers an update of the registers. +/// @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high. +/// @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI. +/// @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_SelectSlaveMode(TIM_TypeDef* tim, TIMSMSMODE_Typedef mode) +{ + MODIFY_REG(tim->SMCR, TIM_SMCR_SMS, mode); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Sets or Resets the tim Master/Slave Mode. +/// @param tim: select the TIM peripheral. +/// @param mode: specifies the Timer Master Slave Mode. +/// This parameter can be one of the following values: +/// @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer +/// and its slaves (through TRIG). +/// @arg TIM_MasterSlaveMode_Disable: No action +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_SelectMasterSlaveMode(TIM_TypeDef* tim, TIMMSM_Typedef mode) +{ + MODIFY_REG(tim->SMCR, TIM_SMCR_MSM, mode); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Sets the tim Counter Register value +/// @param tim: select the TIM peripheral. +/// @param auto_reload: specifies the Counter register new value. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_SetAutoreload(TIM_TypeDef* tim, u16 auto_reload) +{ + WRITE_REG(tim->ARR, auto_reload); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Sets the tim Input Capture 1 prescaler. +/// @param tim: select the TIM peripheral. +/// @param psc: specifies the Input Capture1 prescaler new value. +/// This parameter can be one of the following values: +/// @arg TIM_ICPSC_DIV1: no prescaler +/// @arg TIM_ICPSC_DIV2: capture is done once every 2 events +/// @arg TIM_ICPSC_DIV4: capture is done once every 4 events +/// @arg TIM_ICPSC_DIV8: capture is done once every 8 events +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_SetIC1Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc) +{ + MODIFY_REG(tim->CCMR1, TIM_CCMR1_IC1PSC, psc); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Sets the tim Input Capture 2 prescaler. +/// @param tim: select the TIM peripheral. +/// @param psc: specifies the Input Capture2 prescaler new value. +/// This parameter can be one of the following values: +/// @arg TIM_ICPSC_DIV1: no prescaler +/// @arg TIM_ICPSC_DIV2: capture is done once every 2 events +/// @arg TIM_ICPSC_DIV4: capture is done once every 4 events +/// @arg TIM_ICPSC_DIV8: capture is done once every 8 events +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_SetIC2Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc) +{ + MODIFY_REG(tim->CCMR1, TIM_CCMR1_IC2PSC, psc << 8); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Sets the tim Input Capture 3 prescaler. +/// @param tim: select the TIM peripheral. +/// @param psc: specifies the Input Capture3 prescaler new value. +/// This parameter can be one of the following values: +/// @arg TIM_ICPSC_DIV1: no prescaler +/// @arg TIM_ICPSC_DIV2: capture is done once every 2 events +/// @arg TIM_ICPSC_DIV4: capture is done once every 4 events +/// @arg TIM_ICPSC_DIV8: capture is done once every 8 events +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_SetIC3Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc) +{ + MODIFY_REG(tim->CCMR2, TIM_CCMR2_IC3PSC, psc); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Sets the tim Input Capture 4 prescaler. +/// @param tim: select the TIM peripheral. +/// @param psc: specifies the Input Capture4 prescaler new value. +/// This parameter can be one of the following values: +/// @arg TIM_ICPSC_DIV1: no prescaler +/// @arg TIM_ICPSC_DIV2: capture is done once every 2 events +/// @arg TIM_ICPSC_DIV4: capture is done once every 4 events +/// @arg TIM_ICPSC_DIV8: capture is done once every 8 events +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_SetIC4Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc) +{ + MODIFY_REG(tim->CCMR2, TIM_CCMR2_IC4PSC, psc << 8); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Sets the tim Clock Division value. +/// @param tim: select +/// the TIM peripheral. +/// @param clock_div: specifies the clock division value. +/// This parameter can be one of the following value: +/// @arg TIM_CKD_DIV1: TDTS = Tck_tim +/// @arg TIM_CKD_DIV2: TDTS = 2 * Tck_tim +/// @arg TIM_CKD_DIV4: TDTS = 4 * Tck_tim +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_SetClockDivision(TIM_TypeDef* tim, TIMCKD_TypeDef clock_div) +{ + MODIFY_REG(tim->CR1, TIM_CR1_CKD, clock_div); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Sets the tim Counter Register value +/// @param tim: select the TIM peripheral. +/// @param counter: specifies the Counter register new value. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_SetCounter(TIM_TypeDef* tim, u32 counter) +{ + if ((tim == TIM2) || (tim == TIM5)) + WRITE_REG(tim->CNT, (u32)counter); + else + WRITE_REG(tim->CNT, (u16)counter); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Sets the tim Capture Compare1 Register value +/// @param tim: select the TIM peripheral. +/// @param compare: specifies the Capture Compare1 register new value. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_SetCompare1(TIM_TypeDef* tim, u32 compare) +{ + if ((tim == TIM2) || (tim == TIM5)) + WRITE_REG(tim->CCR1, (u32)compare); + else + WRITE_REG(tim->CCR1, (u16)compare); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Sets the tim Capture Compare2 Register value +/// @param tim: select the TIM peripheral. +/// @param compare: specifies the Capture Compare2 register new value. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_SetCompare2(TIM_TypeDef* tim, u32 compare) +{ + if ((tim == TIM2) || (tim == TIM5)) + WRITE_REG(tim->CCR2, (u32)compare); + else + WRITE_REG(tim->CCR2, (u16)compare); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Sets the tim Capture Compare3 Register value +/// @param tim: select the TIM peripheral. +/// @param compare: specifies the Capture Compare3 register new value. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_SetCompare3(TIM_TypeDef* tim, u32 compare) +{ + if ((tim == TIM2) || (tim == TIM5)) + WRITE_REG(tim->CCR3, (u32)compare); + else + WRITE_REG(tim->CCR3, (u16)compare); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Sets the tim Capture Compare4 Register value +/// @param tim: select the TIM peripheral. +/// @param compare: specifies the Capture Compare4 register new value. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_SetCompare4(TIM_TypeDef* tim, u32 compare) +{ + if ((tim == TIM2) || (tim == TIM5)) + WRITE_REG(tim->CCR4, (u32)compare); + else + WRITE_REG(tim->CCR4, (u16)compare); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Gets the tim Input Capture 1 value. +/// @param tim: select the TIM peripheral. +/// @retval Value: Capture Compare 1 Register value. +//////////////////////////////////////////////////////////////////////////////// +u32 TIM_GetCapture1(TIM_TypeDef* tim) +{ + return tim->CCR1; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Gets the tim Input Capture 2 value. +/// @param tim: select the TIM peripheral. +/// @retval Value: Capture Compare 2 Register value. +//////////////////////////////////////////////////////////////////////////////// +u32 TIM_GetCapture2(TIM_TypeDef* tim) +{ + return tim->CCR2; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Gets the tim Input Capture 3 value. +/// @param tim: select the TIM peripheral. +/// @retval Value: Capture Compare 3 Register value. +//////////////////////////////////////////////////////////////////////////////// +u32 TIM_GetCapture3(TIM_TypeDef* tim) +{ + return tim->CCR3; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Gets the tim Input Capture 4 value. +/// @param tim: select the TIM peripheral. +/// @retval Value: Capture Compare 4 Register value. +//////////////////////////////////////////////////////////////////////////////// +u32 TIM_GetCapture4(TIM_TypeDef* tim) +{ + return tim->CCR4; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Gets the tim Counter value. +/// @param tim: select the TIM peripheral. +/// @retval Value: Counter Register value. +//////////////////////////////////////////////////////////////////////////////// +u32 TIM_GetCounter(TIM_TypeDef* tim) +{ + return tim->CNT; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Gets the tim Prescaler value. +/// @param tim: select the TIM peripheral. +/// @retval Value: Prescaler Register value. +//////////////////////////////////////////////////////////////////////////////// +u16 TIM_GetPrescaler(TIM_TypeDef* tim) +{ + return tim->PSC; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Checks whether the specified TIM flag is set or not. +/// @param tim: select the TIM peripheral. +/// @param flag: specifies the flag to check. +/// This parameter can be one of the following values: +/// @arg TIM_FLAG_Update: TIM update Flag +/// @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag +/// @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag +/// @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag +/// @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag +/// @arg TIM_FLAG_COM: TIM Commutation Flag +/// @arg TIM_FLAG_Trigger: TIM Trigger Flag +/// @arg TIM_FLAG_Break: TIM Break Flag +/// @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag +/// @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag +/// @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag +/// @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag +/// @note +/// - TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. +/// - TIM_FLAG_Break is used only with TIM1 and TIM8. +/// - TIM_FLAG_COM is used only with TIM1, TIM8, TIM16 and TIM17. +/// @retval State: The new state of TIM_FLAG (SET or RESET). +//////////////////////////////////////////////////////////////////////////////// +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* tim, TIMFLAG_Typedef flag) +{ + return ((tim->SR & flag) ? SET : RESET); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Clears the tim's pending flags. +/// @param tim: select the TIM peripheral. +/// @param flag: specifies the flag bit to clear. +/// This parameter can be any combination of the following values: +/// @arg TIM_FLAG_Update: TIM update Flag +/// @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag +/// @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag +/// @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag +/// @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag +/// @arg TIM_FLAG_COM: TIM Commutation Flag +/// @arg TIM_FLAG_Trigger: TIM Trigger Flag +/// @arg TIM_FLAG_Break: TIM Break Flag +/// @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag +/// @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag +/// @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag +/// @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag +/// @note +/// - TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. +/// - TIM_FLAG_Break is used only with TIM1 and TIM8. +/// - TIM_FLAG_COM is used only with TIM1, TIM8, TIM16 and TIM17. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_ClearFlag(TIM_TypeDef* tim, TIMFLAG_Typedef flag) +{ + CLEAR_BIT(tim->SR, flag); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Checks whether the TIM interrupt has occurred or not. +/// @param tim: select the TIM peripheral. +/// @param it: specifies the TIM interrupt source to check. +/// This parameter can be one of the following values: +/// @arg TIM_IT_Update: TIM update Interrupt source +/// @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source +/// @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source +/// @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source +/// @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source +/// @arg TIM_IT_COM: TIM Commutation Interrupt source +/// @arg TIM_IT_Trigger: TIM Trigger Interrupt source +/// @arg TIM_IT_Break: TIM Break Interrupt source +/// @note +/// - TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. +/// - TIM_IT_Break is used only with TIM1 and TIM8. +/// - TIM_IT_COM is used only with TIM1, TIM8, TIM16 and TIM17. +/// @retval State: The new state of the TIM_IT(SET or RESET). +//////////////////////////////////////////////////////////////////////////////// +ITStatus TIM_GetITStatus(TIM_TypeDef* tim, TIMIT_TypeDef it) +{ + return (((tim->SR & it) && (tim->DIER & it)) ? SET : RESET); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Clears the tim's interrupt pending bits. +/// @param tim: select the TIM peripheral. +/// @param it: specifies the pending bit to clear. +/// This parameter can be any combination of the following values: +/// @arg TIM_IT_Update: TIM1 update Interrupt source +/// @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source +/// @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source +/// @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source +/// @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source +/// @arg TIM_IT_COM: TIM Commutation Interrupt source +/// @arg TIM_IT_Trigger: TIM Trigger Interrupt source +/// @arg TIM_IT_Break: TIM Break Interrupt source +/// @note +/// - TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. +/// - TIM_IT_Break is used only with TIM1 and TIM8. +/// - TIM_IT_COM is used only with TIM1, TIM8, TIM16 and TIM17. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_ClearITPendingBit(TIM_TypeDef* tim, u32 it) //TIMIT_TypeDef +{ + CLEAR_BIT(tim->SR, it); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the tim channel 1 polarity. +/// @param tim: select the TIM peripheral. +/// @param polarity: specifies the IC1 Polarity +/// This parameter can be one of the following values: +/// @arg TIM_ICPolarity_Rising +/// @arg TIM_ICPolarity_Falling +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_SetIC1Plority(TIM_TypeDef* tim, TIMICP_Typedef pol) +{ + (pol) ? SET_BIT(tim->CCER, TIM_CCER_CC1P) : CLEAR_BIT(tim->CCER, TIM_CCER_CC1P); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the tim channel 2 polarity. +/// @param tim: select the TIM peripheral. +/// @param polarity: specifies the IC2 Polarity +/// This parameter can be one of the following values: +/// @arg TIM_ICPolarity_Rising +/// @arg TIM_ICPolarity_Falling +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_SetIC2Plority(TIM_TypeDef* tim, TIMICP_Typedef pol) +{ + (pol) ? SET_BIT(tim->CCER, TIM_CCER_CC2P) : CLEAR_BIT(tim->CCER, TIM_CCER_CC2P); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the tim channel 3 polarity. +/// @param tim: select the TIM peripheral. +/// @param polarity: specifies the IC3 Polarity +/// This parameter can be one of the following values: +/// @arg TIM_ICPolarity_Rising +/// @arg TIM_ICPolarity_Falling +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_SetIC3Plority(TIM_TypeDef* tim, TIMICP_Typedef pol) +{ + (pol) ? SET_BIT(tim->CCER, TIM_CCER_CC3P) : CLEAR_BIT(tim->CCER, TIM_CCER_CC3P); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the tim channel 4 polarity. +/// @param tim: select the TIM peripheral. +/// @param polarity: specifies the IC4 Polarity +/// This parameter can be one of the following values: +/// @arg TIM_ICPolarity_Rising +/// @arg TIM_ICPolarity_Falling +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_SetIC4Plority(TIM_TypeDef* tim, TIMICP_Typedef pol) +{ + (pol) ? SET_BIT(tim->CCER, TIM_CCER_CC4P) : CLEAR_BIT(tim->CCER, TIM_CCER_CC4P); +} + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Sets the tim Capture Compare 5 Register value +/// @param tim: select the TIM peripheral. +/// @param compare: specifies the Capture Compare5 register new value. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_SetCompare5(TIM_TypeDef* tim, u32 compare) +{ + WRITE_REG(tim->CCR5, (u16)compare); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Gets the tim Input Capture 5 value. +/// @param tim: select the TIM peripheral. +/// @retval Value: Capture Compare 5 Register value. +//////////////////////////////////////////////////////////////////////////////// +u32 TIM_GetCapture5(TIM_TypeDef* tim) +{ + return tim->CCR5; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Initializes the tim Channel5 according to the specified +/// parameters in the init_struct. +/// @param tim: select the TIM peripheral. +/// @param init_struct: pointer to a TIM_OCInitTypeDef structure that +/// contains the configuration information for the specified TIM peripheral. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_OC5Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct) +{ + MODIFY_REG(tim->CCMR3, TIM_CCMR3_OC5M, (init_struct->TIM_OCMode) << 4); + MODIFY_REG(tim->CCER, TIM_CCER_CC5EN | TIM_CCER_CC5P, + (init_struct->TIM_OCPolarity << 16) | (init_struct->TIM_OutputState << 16)); + WRITE_REG(tim->CCR4, init_struct->TIM_Pulse); + + if ((tim == TIM1) || (tim == TIM8)) + MODIFY_REG(tim->CR2, TIM_CR2_OIS5, init_struct->TIM_OCIdleState << 8); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the tim peripheral Preload register on CCR5. +/// @param tim: select the TIM peripheral. +/// @param preload: new state of the tim peripheral Preload register +/// This parameter can be one of the following values: +/// @arg TIM_OCPreload_Enable +/// @arg TIM_OCPreload_Disable +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_OC5PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload) +{ + MODIFY_REG(tim->CCMR3, TIM_CCMR3_OC5PEN, preload); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the tim channel 5 polarity. +/// @param tim: select the TIM peripheral. +/// @param polarity: specifies the OC5 Polarity +/// This parameter can be one of the following values: +/// @arg TIM_OCPolarity_High: Output Compare active high +/// @arg TIM_OCPolarity_Low: Output Compare active low +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_OC5PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity) +{ + MODIFY_REG(tim->CCER, TIM_CCER_CC5P, polarity << 16); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configures the tim Output Compare 5 Fast feature. +/// @param tim: select the TIM peripheral. +/// @param fast: new state of the Output Compare Fast Enable Bit. +/// This parameter can be one of the following values: +/// @arg TIM_OCFast_Enable: TIM output compare fast enable +/// @arg TIM_OCFast_Disable: TIM output compare fast disable +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_OC5FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast) +{ + MODIFY_REG(tim->CCMR3, TIM_CCMR3_OC5FEN, fast); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Clears or safeguards the OCREF4 signal on an external event +/// @param tim: select the TIM peripheral. +/// @param clear: new state of the Output Compare Clear Enable Bit. +/// This parameter can be one of the following values: +/// @arg TIM_OCClear_Enable: TIM Output clear enable +/// @arg TIM_OCClear_Disable: TIM Output clear disable +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_ClearOC5Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear) +{ + MODIFY_REG(tim->CCMR3, TIM_CCMR3_OC5CEN, clear); +} + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the tim complementary PWM output Status after Break. +/// @param tim: select the TIM peripheral. +/// @param state: new state of the tim complementary PWM output. +/// This parameter can be: ENABLE or DISABLE. +/// @arg ENABLE: Direct output enable, no longer waiting for output after dead time. +/// @arg DISABLE: Direct output disable, output waiting for dead time. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_DirectOutput(TIM_TypeDef* tim, FunctionalState state) +{ + (state) ? SET_BIT(tim->BDTR, TIM_BDTR_DOEN) : CLEAR_BIT(tim->BDTR, TIM_BDTR_DOEN); +} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup TIM_Private_Functions +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configure the TI1 as Input. +/// @param tim: select the TIM peripheral. +/// @param polarity : The Input Polarity. +/// This parameter can be one of the following values: +/// @arg TIM_ICPolarity_Rising +/// @arg TIM_ICPolarity_Falling +/// @param selection: specifies the input to be used. +/// This parameter can be one of the following values: +/// @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. +/// @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. +/// @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. +/// @param filter: Specifies the Input Capture Filter. +/// This parameter must be a value between 0x00 and 0x0F. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +static void TI1_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter) +{ + MODIFY_REG(tim->CCMR1, TIM_CCMR1_CC1S | TIM_CCMR1_IC1F, (filter << 4) | selection); + MODIFY_REG(tim->CCER, TIM_CCER_CC1EN | TIM_CCER_CC1P, polarity | TIM_CCER_CC1EN); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configure the TI2 as Input. +/// @param tim: select the TIM peripheral. +/// @param polarity : The Input Polarity. +/// This parameter can be one of the following values: +/// @arg TIM_ICPolarity_Rising +/// @arg TIM_ICPolarity_Falling +/// @param selection: specifies the input to be used. +/// This parameter can be one of the following values: +/// @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. +/// @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. +/// @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. +/// @param filter: Specifies the Input Capture Filter. +/// This parameter must be a value between 0x00 and 0x0F. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +static void TI2_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter) +{ + MODIFY_REG(tim->CCMR1, TIM_CCMR1_CC2S | TIM_CCMR1_IC2F, (filter << 12) | (selection << 8)); + MODIFY_REG(tim->CCER, TIM_CCER_CC2EN | TIM_CCER_CC2P, (polarity << 4) | TIM_CCER_CC2EN); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configure the TI3 as Input. +/// @param tim: select the TIM peripheral. +/// @param polarity : The Input Polarity. +/// This parameter can be one of the following values: +/// @arg TIM_ICPolarity_Rising +/// @arg TIM_ICPolarity_Falling +/// @param selection: specifies the input to be used. +/// This parameter can be one of the following values: +/// @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. +/// @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. +/// @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. +/// @param filter: Specifies the Input Capture Filter. +/// This parameter must be a value between 0x00 and 0x0F. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +static void TI3_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter) +{ + MODIFY_REG(tim->CCMR2, TIM_CCMR2_CC3S | TIM_CCMR2_IC3F, (filter << 4) | selection); + MODIFY_REG(tim->CCER, TIM_CCER_CC3EN | TIM_CCER_CC3P, (polarity << 8) | TIM_CCER_CC3EN); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Configure the TI4 as Input. +/// @param tim: select the TIM peripheral. +/// @param polarity : The Input Polarity. +/// This parameter can be one of the following values: +/// @arg TIM_ICPolarity_Rising +/// @arg TIM_ICPolarity_Falling +/// @param selection: specifies the input to be used. +/// This parameter can be one of the following values: +/// @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. +/// @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. +/// @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. +/// @param filter: Specifies the Input Capture Filter. +/// This parameter must be a value between 0x00 and 0x0F. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +static void TI4_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter) +{ + MODIFY_REG(tim->CCMR2, TIM_CCMR2_CC4S | TIM_CCMR2_IC4F, (filter << 12) | (selection << 8)); + MODIFY_REG(tim->CCER, TIM_CCER_CC4EN | TIM_CCER_CC4P, (polarity << 12) | TIM_CCER_CC4EN); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the specified TIM PWM shift /DMA reqeat. +/// @param tim: select the tim peripheral. +/// @param it: Specifies the TIM PWM shift channel to enable or disable. +/// This parameter can be any combination of the following values: +/// @arg TIM_PDER_CCDREPE: TIM DMA reqeat enable bit +/// @arg TIM_PDER_CCR1SHIFTEN: TIM Channel 1 output PWM phase shift enable bit +/// @arg TIM_PDER_CCR2SHIFTEN: TIM Channel 2 output PWM phase shift enable bit +/// @arg TIM_PDER_CCR3SHIFTEN: TIM Channel 3 output PWM phase shift enable bit +/// @arg TIM_PDER_CCR4SHIFTEN: TIM Channel 4 output PWM phase shift enable bit +/// @arg TIM_PDER_CCR5SHIFTEN: TIM Channel 5 output PWM phase shift enable bit +/// @param state: new state of the TIM interrupts. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_PWMShiftConfig(TIM_TypeDef* tim, u32 it, FunctionalState state)//TIMIT_TypeDef +{ + (state) ? SET_BIT(tim->PDER, it) : CLEAR_BIT(tim->PDER, it); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Sets the tim CCR1 shift Register value +/// @param tim: select the TIM peripheral. +/// @param compare: specifies the Capture Compare1 register new value. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_SetCCR1FALL(TIM_TypeDef* tim, u32 shift) +{ + if (tim == TIM1) + WRITE_REG(tim->CCR1FALL, (u32)shift); + +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Sets the tim CCR2 shift Register value +/// @param tim: select the TIM peripheral. +/// @param compare: specifies the Capture Compare1 register new value. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_SetCCR2FALL(TIM_TypeDef* tim, u32 shift) +{ + if (tim == TIM1) + WRITE_REG(tim->CCR2FALL, (u32)shift); + +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Sets the tim CCR3 shift Register value +/// @param tim: select the TIM peripheral. +/// @param compare: specifies the Capture Compare1 register new value. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_SetCCR3FALL(TIM_TypeDef* tim, u32 shift) +{ + if (tim == TIM1) + WRITE_REG(tim->CCR3FALL, (u32)shift); + +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Sets the tim CCR4 shift Register value +/// @param tim: select the TIM peripheral. +/// @param compare: specifies the Capture Compare1 register new value. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_SetCCR4FALL(TIM_TypeDef* tim, u32 shift) +{ + if (tim == TIM1) + WRITE_REG(tim->CCR4FALL, (u32)shift); + +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Sets the tim CCR5 shift Register value +/// @param tim: select the TIM peripheral. +/// @param compare: specifies the Capture Compare1 register new value. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void TIM_SetCCR5FALL(TIM_TypeDef* tim, u32 shift) +{ + if (tim == TIM1) + WRITE_REG(tim->CCR5FALL, (u32)shift); + +} +/// @} + +/// @} + +/// @} diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uart.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uart.c new file mode 100644 index 000000000..2a0578f91 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uart.c @@ -0,0 +1,502 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_uart.c +/// @file hal_uart.c +/// @author AE TEAM +/// @brief THIS FILE PROVIDES ALL THE UART FIRMWARE FUNCTIONS. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#define _HAL_UART_C_ + +// Files includes +#include "hal_rcc.h" +#include "hal_uart.h" +#include "hal_gpio.h" +#include "hal_dma.h" +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +///@addtogroup UART_HAL +///@{ + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup UART_Exported_Functions +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Deinitializes the uart peripheral registers to their +/// default reset values. +/// @param uart: Select the UART or the UART peripheral. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void UART_DeInit(UART_TypeDef* uart) +{ + + + if(UART2 == uart) { + exRCC_APB1PeriphReset(RCC_APB1ENR_UART2); + } + if(UART1 == uart) { + exRCC_APB2PeriphReset(RCC_APB2ENR_UART1); + } + if(UART3 == uart) { + exRCC_APB1PeriphReset(RCC_APB1ENR_UART3); + } + if(UART4 == uart) { + exRCC_APB1PeriphReset(RCC_APB1ENR_UART4); + } + if(UART5 == uart) { + exRCC_APB1PeriphReset(RCC_APB1ENR_UART5); + } + if(UART6 == uart) { + exRCC_APB2PeriphReset(RCC_APB2ENR_UART6); + } + if(UART7 == uart) { + exRCC_APB1PeriphReset(RCC_APB1ENR_UART7); + } + if(UART8 == uart) { + exRCC_APB1PeriphReset(RCC_APB1ENR_UART8); + } +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Initializes the uart peripheral according to the specified +/// parameters in the UART_InitStruct . +/// @param uart: Select the UART or the UART peripheral. +/// @param init_struct: pointer to a UART_InitTypeDef structure +/// that contains the configuration information for the +/// specified UART peripheral. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void UART_Init(UART_TypeDef* uart, UART_InitTypeDef* init_struct) +{ + u32 apbclock = 0x00; + // UART CCR Configuration + MODIFY_REG(uart->CCR, UART_CCR_CHAR, init_struct->WordLength); + + + MODIFY_REG(uart->CCR, (UART_CCR_SPB0 | UART_CCR_SPB1), init_struct->StopBits); + + MODIFY_REG(uart->CCR, (UART_CCR_PEN | UART_CCR_PSEL), init_struct->Parity); + + // UART GCR Configuration + MODIFY_REG(uart->GCR, (UART_GCR_TX | UART_GCR_RX), init_struct->Mode); + MODIFY_REG(uart->GCR, UART_GCR_AUTOFLOW, init_struct->HWFlowControl); + + //UART BRR Configuration + //Configure the UART Baud Rate + if (uart == UART1) { + + apbclock = RCC_GetPCLK2Freq(); + } + else { + apbclock = RCC_GetPCLK1Freq(); + } + // Determine the UART_baud + uart->BRR = (apbclock / init_struct->BaudRate) / 16; + uart->FRA = (apbclock / init_struct->BaudRate) % 16; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Fills each UART_InitStruct member with its default value. +/// @param init_struct: pointer to a UART_InitTypeDef structure +/// which will be initialized. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void UART_StructInit(UART_InitTypeDef* init_struct) +{ + // UART_InitStruct members default value + init_struct->BaudRate = 9600; + init_struct->WordLength = UART_WordLength_8b; + init_struct->StopBits = UART_StopBits_1; + init_struct->Parity = UART_Parity_No; + init_struct->Mode = UART_GCR_RX | UART_GCR_TX; + init_struct->HWFlowControl = UART_HWFlowControl_None; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the specified UART peripheral. +/// @param uart: Select the UART or the UART peripheral. +/// @param state: new state of the uart peripheral. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void UART_Cmd(UART_TypeDef* uart, FunctionalState state) +{ + MODIFY_REG(uart->GCR, UART_GCR_UART, state << UART_GCR_UART_Pos); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the specified UART interrupts. +/// @param uart: Select the UART or the UART peripheral. +/// @param it: specifies the UART interrupt sources to be +/// enabled or disabled. +/// This parameter can be one of the following values: +/// @arg UART_IT_ERR: Error interrupt(Frame error,) +/// @arg UART_IT_PE: Parity Error interrupt +/// @arg UART_OVER_ERR: overrun Error interrupt +/// @arg UART_IT_RXIEN: Receive Data register interrupt +/// @arg UART_IT_TXIEN: Tansmit Data Register empty interrupt +/// +/// @param state: new state of the specified uart interrupts. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void UART_ITConfig(UART_TypeDef* uart, u16 it, FunctionalState state) +{ + (state) ? (uart->IER |= it) : (uart->IER &= ~it); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the UART DMA interface. +/// @param uart: Select the UART or the UART peripheral. +/// @param dma_request: specifies the DMA request. +/// This parameter can be any combination of the following values: +/// @arg UART_DMAReq_EN: UART DMA transmit request +/// +/// @param state: new state of the DMA Request sources. +/// This parameter can be: ENABLE or DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void UART_DMACmd(UART_TypeDef* uart, u16 dma_request, FunctionalState state) +{ + MODIFY_REG(uart->GCR, UART_GCR_DMA, state << UART_GCR_DMA_Pos); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Transmits single data through the uart peripheral. +/// @param uart: Select the UART or the UART peripheral. +/// @param Data: the data to transmit. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void UART_SendData(UART_TypeDef* uart, u16 value) +{ + // Transmit Data + WRITE_REG(uart->TDR, (value & 0xFFU)); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Returns the most recent received data by the uart peripheral. +/// @param uart: Select the UART or the UART peripheral. +/// @retval The received data. +//////////////////////////////////////////////////////////////////////////////// +u16 UART_ReceiveData(UART_TypeDef* uart) +{ + // Receive Data + return (u16)(uart->RDR & 0xFFU); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Checks whether the specified UART flag is set or not. +/// @param uart: Select the UART or the UART peripheral. +/// @param flag: specifies the flag to check. +/// This parameter can be one of the following values: +/// @arg UART_FLAG_TXEMPTY: Transmit data register empty flag +/// @arg UART_FLAG_TXFULL: Transmit data buffer full +/// @arg UART_FLAG_RXAVL: RX Buffer has a byte flag +/// @arg UART_FLAG_TXEPT: tx and shifter are emptys flag +/// @retval The new state of UART_FLAG (SET or RESET). +//////////////////////////////////////////////////////////////////////////////// +FlagStatus UART_GetFlagStatus(UART_TypeDef* uart, u16 flag) +{ + return (uart->CSR & flag) ? SET : RESET; +} + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Checks whether the specified UART interrupt has occurred or not. +/// @param uart: Select the UART or the UART peripheral. +/// @param it: specifies the UART interrupt source to check. +/// This parameter can be one of the following values: +/// @arg UART_IT_ERR: Error interrupt(Frame error,) +/// @arg UART_IT_PE: Parity Error interrupt +/// @arg UART_OVER_ERR: overrun Error interrupt +/// @arg UART_IT_RXIEN: Receive Data register interrupt +/// @arg UART_IT_TXIEN: Tansmit Data Register empty interrupt +/// @retval The new state of UART_IT (SET or RESET). +//////////////////////////////////////////////////////////////////////////////// +ITStatus UART_GetITStatus(UART_TypeDef* uart, u16 it) +{ + return (uart->ISR & it) ? SET : RESET; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Clears the uart interrupt pending bits. +/// @param uart: Select the UART or the UART peripheral. +/// @param it: specifies the interrupt pending bit to clear. +/// This parameter can be one of the following values: +/// @arg UART_IT_ERR: Error interrupt(Frame error,) +/// @arg UART_IT_PE: Parity Error interrupt +/// @arg UART_OVER_ERR: overrun Error interrupt +/// @arg UART_IT_RXIEN: Receive Data register interrupt +/// @arg UART_IT_TXIEN: Tansmit Data Register empty interrupt +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void UART_ClearITPendingBit(UART_TypeDef* uart, u16 it) +{ + //clear UART_IT pendings bit + uart->ICR = it; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Selects the UART WakeUp method. +/// @param uart: Select the UART or the UART peripheral. +/// @param mode: specifies the UART wakeup method. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void UART_WakeUpConfig(UART_TypeDef* uart, UART_WakeUp_TypeDef mode) +{ + MODIFY_REG(uart->CCR, UART_CCR_WAKE, mode); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Determines if the UART is in mute mode or not. +/// @param uart: Select the UART or the UART peripheral. +/// @param state: new state of the UART mute mode. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void UART_ReceiverWakeUpCmd(UART_TypeDef* uart, FunctionalState state) +{ + MODIFY_REG(uart->CCR, UART_CCR_RWU, state << UART_CCR_RWU_Pos); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Sets the address of the UART Rx Address. +/// @param uart: Select the UART or the UART peripheral. +/// @param address: Indicates the address of the UART Rx Address. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void UART_SetRXAddress(UART_TypeDef* uart, u8 address) +{ + MODIFY_REG(uart->RXAR, UART_RXAR_ADDR, address); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Sets the address of the UART Rx MASK. +/// @param uart: Select the UART or the UART peripheral. +/// @param address: Indicates the address of the UART Rx MASK. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void UART_SetRXMASK(UART_TypeDef* uart, u8 address) +{ + MODIFY_REG(uart->RXMR, UART_RXMR_MASK, address); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ENBALE or DISABLE the UART's 9bit. +/// @param uart: Select the UART or the UART peripheral. +/// @param state: new state of the UART 9 bit. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void UART_Enable9bit(UART_TypeDef* uart, FunctionalState state) +{ + MODIFY_REG(uart->CCR, UART_CCR_B8EN, state << UART_CCR_B8EN_Pos); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Set the UART's 9bit Level. +/// @param uart: Select the UART or the UART peripheral. +/// @param state: new state of the UART 9 bit. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void UART_Set9bitLevel(UART_TypeDef* uart, FunctionalState state) +{ + MODIFY_REG(uart->CCR, UART_CCR_B8TXD, state << UART_CCR_B8TXD_Pos); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Set the UART's 9bit Polarity. +/// @param uart: Select the UART or the UART peripheral. +/// @param polarity: new state of the UART 9 bit Polarity. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void UART_Set9bitPolarity(UART_TypeDef* uart, UART_9bit_Polarity_TypeDef polarity) +{ + MODIFY_REG(uart->CCR, UART_CCR_B8POL, polarity); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Set the UART's 9bit Automatic Toggle. +/// @param uart: Select the UART or the UART peripheral. +/// @param state: new state of the UART 9 bit Automatic Toggle. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void UART_Set9bitAutomaticToggle(UART_TypeDef* uart, FunctionalState state) +{ + MODIFY_REG(uart->CCR, UART_CCR_B8TOG, state << UART_CCR_B8TOG_Pos); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the UART Half Duplex communication. +/// @param uart: Select the UART or the UART peripheral. +/// @param state: new state of the UART Communication. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void UART_HalfDuplexCmd(UART_TypeDef* uart, FunctionalState state) +{ + MODIFY_REG(uart->SCR, UART_SCR_HDSEL, state << UART_SCR_HDSEL_Pos); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Sets the specified UART guard time. +/// @param uart: Select the UART or the UART peripheral. +/// @param guard_time: specifies the guard time. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void UART_SetGuardTime(UART_TypeDef* uart, u8 guard_time) +{ + MODIFY_REG(uart->SCR, UART_SCR_SCFCNT, guard_time << UART_SCR_SCFCNT_Pos); + // Clear the UART Guard time + // uart->SCR &= SCR_SCFCNT_Mask; + // Set the UART guard time + // uart->SCR |= (u16)((u16)guard_time << 0x04); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables the UART's Smart Card mode. +/// @param uart: Select the UART or the UART peripheral. +/// @param state: new state of the Smart Card mode. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void UART_SmartCardCmd(UART_TypeDef* uart, FunctionalState state) +{ + MODIFY_REG(uart->SCR, UART_SCR_SCEN, state << UART_SCR_SCEN_Pos); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables or disables NACK transmission. +/// @param uart: Select the UART or the UART peripheral. +/// @param state: new state of the NACK transmission. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void UART_SmartCardNACKCmd(UART_TypeDef* uart, FunctionalState state) +{ + MODIFY_REG(uart->SCR, UART_SCR_SCARB, state << UART_SCR_SCARB_Pos); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Transmits break characters. +/// @param uart: Select the UART or the UART peripheral. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void UART_SendBreak(UART_TypeDef* uart) +{ + SET_BIT(uart->CCR, UART_CCR_BRK); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enable or Disable Auto Baud-Rate Detection +/// @param uart: Select the UART or the UART peripheral. +/// @param state: new state of the UART AutoBaudRate Detection. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void UART_AutoBaudRateCmd(UART_TypeDef* uart, FunctionalState state) +{ + state ? SET_BIT(uart->ABRCR, UART_ABRCR_ABREN) : CLEAR_BIT(uart->ABRCR, UART_ABRCR_ABREN) ; +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief AutoBaudRate. +/// @param uart: Select the UART or the UART peripheral. +/// value: special character. +/// state: ENABLE/DISABLE. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void UART_AutoBaudRateSet(UART_TypeDef* uart, UART_AutoBaud_TypeDef value, FunctionalState state) +{ + CLEAR_BIT(uart->ABRCR, UART_ABRCR_ABREN); + //This bit field can only be written when ABREN = 0 or the UART is disabled (UARTEN=0). + + if ((value == ABRMODE_FALLING_TO_RISINGEDGE1BIT) || (value == ABRMODE_STARTBIT) || (value == ABRMODE_VALUE0XFF)) { + //UART measures the duration of the start bit (falling edge) to first rising edge + //FORMER edge = 0 LATTER edge= 1, from fist falling edge to rising edge = one bit + //___ _ _______ + // |_|1 x x x x x x x| = Bxxxx xxx1 F to U = 1 start bit + // + MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \ + UART_ABRCR_LATTER | UART_ABRCR_BITCNT_MODE0 ); + } + else if((value == ABRMODE_FALLING_TO_RISINGEDGE2BIT) || (value == Data_FE)) { + //UART measures the duration of the start bit (falling edge) to first rising edge + //FORMER edge = 0 LATTER edge= 1, from fist falling edge to rising edge = two bit + //___ _ _______ + // |_ _|1 x x x x x x| = Bxxxx xx10 F to U = 2 + // + MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \ + UART_ABRCR_LATTER | UART_ABRCR_BITCNT_MODE1); + } + else if((value == ABRMODE_FALLING_TO_RISINGEDGE4BIT) || (value == Data_F8)) { + //UART measures the duration of the start bit (falling edge) to first rising edge + //FORMER edge = 0 LATTER edge= 1, from fist falling edge to rising edge = four bit + //___ _ _______ + // |_ _ _ _|1 x x x x| = Bxxxx 1000 F to U = 4 + // + MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \ + UART_ABRCR_LATTER | UART_ABRCR_BITCNT_MODE2); + } + else if((value == ABRMODE_FALLING_TO_RISINGEDGE8BIT) || (value == ABRMODE_VALUE0X80)) { + //UART measures the duration of the start bit (falling edge) to first rising edge + //FORMER edge = 0 LATTER edge= 1, from fist falling edge to rising edge = eight bit + //___ _ ______ + // |_ _ _ _ _ _ _ _|1 = B1000 0000 F to U = 8 + // + MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \ + UART_ABRCR_LATTER | UART_ABRCR_BITCNT_MODE3); + } + else if((value == ABRMODE_FALLING_TO_FALLINGEDGE2BIT) || (value == ABRMODE_VALUE0X55)) { + //UART measures the duration of the start bit (falling edge) to next falling edge + //FORMER edge = 0 LATTER edge= 0, from fist falling edge to next falling edge = two bit + //___ _ ______ + // |_|1|_|x x x x x x| = Bxxxx xx01 F to F = 2 0x55 and Falling to Falling + // + MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \ + UART_ABRCR_BITCNT_MODE1); + } + else if((value == ABRMODE_FALLING_TO_FALLINGEDGE4BIT) || (value == ABRMODE_VALUE0XF7)) { + //UART measures the duration of the start bit (falling edge) to next falling edge + //FORMER edge = 0 LATTER edge= 0, from fist falling edge to next falling edge = four bit + //___ _ _ _ ______ + // |_|1 1 1|_|x x x x| = Bxxxx 0111 F to F = 4 + // + MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \ + UART_ABRCR_BITCNT_MODE2); + } + else if((value == ABRMODE_FALLING_TO_FALLINGEDGE8BIT) || (value == ABRMODE_VALUE0x7F)) { + //UART measures the duration of the start bit (falling edge) to next falling edge + //FORMER edge = 0 LATTER edge= 0, from fist falling edge to next falling edge = eight bit + //___ _ _ _ _ _ _ _ ______ + // |_|1 1 1 1 1 1 1|_| = B0111 1111 F to F = 8 0x7F + // + MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \ + UART_ABRCR_BITCNT_MODE3); + } + + else { + //UART measures the duration of the start bit (falling edge) to next falling edge + //FORMER edge = 0 LATTER edge= 0, from fist falling edge to next falling edge = eight bit + //___ _ _ _ _ _ _ _ ______ + // |_|1 1 1 1 1 1 1|_| = B0111 1111 F to F = 8 0x7F + // + MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \ + UART_ABRCR_BITCNT_MODE3); + } + if(state == ENABLE) { + SET_BIT(uart->ABRCR, UART_ABRCR_ABREN); + } +} +/// @} + +/// @} + +/// @} diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uid.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uid.c new file mode 100644 index 000000000..e51bfcade --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uid.c @@ -0,0 +1,55 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_uid.c +/// @author AE TEAM +/// @brief THIS FILE PROVIDES ALL THE UID FIRMWARE FUNCTIONS. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

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+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#define _HAL_UID_C_ + +// Files includes +#include "hal_uid.h" +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +///@addtogroup UID_HAL +///@{ + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup UID_Exported_Functions +/// @{ + +u8 device_id_data[12] = {0}; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Get device ID. +/// @param None. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void GetChipUID(void) +{ + u8 i; + + for (i = 0; i < 12; i++) { + device_id_data[i] = *((vu8*)(UID_BASE + i)); + } +} + +/// @} + +/// @} + +/// @} diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_ver.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_ver.c new file mode 100644 index 000000000..9d771396c --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_ver.c @@ -0,0 +1,131 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_ver.c +/// @author AE TEAM +/// @brief THIS FILE PROVIDES ALL THE LIB AND THE CHIPSET INFORMATION. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

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+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#define _HAL_VER_C_ + +// Files includes +#include "hal_ver.h" + + +// MM32 Library version is 0.90 + +#define __MM32_LIB_VERSION_MAIN (0x0U) //!< [31:24] main version +#define __MM32_LIB_VERSION_SUB1 (0x9U) //!< [23:16] sub1 version +#define __MM32_LIB_VERSION_SUB2 (0x0U) //!< [15:8] sub2 version +#define __MM32_LIB_VERSION_RC (0x00U) //!< [7:0] release candidate +#define __MM32_LIB_VERSION ((__MM32_LIB_VERSION_MAIN << 24U)\ + |(__MM32_LIB_VERSION_SUB1 << 16U)\ + |(__MM32_LIB_VERSION_SUB2 << 8U )\ + |(__MM32_LIB_VERSION_RC)) + +// MM32 Library release date is 2021-05-10 (YYYY-MM-DD) +#define __MM32_LIB_RELESE_YEARH (0x20U) //!< [31:24] release year high +#define __MM32_LIB_RELESE_YEARL (0x21U) //!< [23:16] release year low +#define __MM32_LIB_RELESE_MONTH (0x05U) //!< [15:8] release month +#define __MM32_LIB_RELESE_DAY (0x10U) //!< [7:0] release day +#define __MM32_LIB_RELESE_DATE ((__MM32_LIB_RELESE_YEARH << 24U)\ + |(__MM32_LIB_RELESE_YEARL << 16U)\ + |(__MM32_LIB_RELESE_MONTH << 8U )\ + |(__MM32_LIB_RELESE_DAY)) +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +///@addtogroup VER_HAL +///@{ + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup Lib and chipset_Exported_Functions +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @brief This method returns the Lib revision. +/// @param None. +/// @retval return the Lib version. +//////////////////////////////////////////////////////////////////////////////// +u32 Get_MM32LibVersion(void) +{ + return __MM32_LIB_VERSION; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief This method returns the Lib release date. +/// @param None. +/// @retval return the Lib release date. +//////////////////////////////////////////////////////////////////////////////// +u32 Get_MM32LibReleaseDate(void) +{ + return __MM32_LIB_RELESE_DATE; +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Returns the device revision identifier. +/// @param None. +/// @retval return the device revision identifier. +//////////////////////////////////////////////////////////////////////////////// +u32 Get_ChipsetREVID(void) +{ + return((DBGMCU->IDCODE) & 0xF ); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Returns the device identifier.. +/// @param None. +/// @retval return the device Device identifier. +//////////////////////////////////////////////////////////////////////////////// +u32 Get_ChipsetDEVID(void) +{ + return((DBGMCU->IDCODE) ); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Returns first word of the unique device identifier (UID based on 96 bits) +/// @param None. +/// @retval Device identifier +//////////////////////////////////////////////////////////////////////////////// +u32 Get_ChipsetUIDw0(void) +{ + return(READ_REG(*((vu32*)UID_BASE))); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Returns second word of the unique device identifier (UID based on 96 bits) +/// @param None. +/// @retval Device identifier +//////////////////////////////////////////////////////////////////////////////// +u32 Get_ChipsetUIDw1(void) +{ + return(READ_REG(*((vu32*)(UID_BASE + 4U)))); +} +//////////////////////////////////////////////////////////////////////////////// +/// @brief Returns third word of the unique device identifier (UID based on 96 bits) +/// @param None. +/// @retval Device identifier +//////////////////////////////////////////////////////////////////////////////// +u32 Get_ChipsetUIDw2(void) +{ + return(READ_REG(*((vu32*)(UID_BASE + 8U)))); +} + + + + + +/// @} + +/// @} + +/// @} diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_wwdg.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_wwdg.c new file mode 100644 index 000000000..05d74b596 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_wwdg.c @@ -0,0 +1,147 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file hal_wwdg.c +/// @author AE TEAM +/// @brief THIS FILE PROVIDES ALL THE WWDG FIRMWARE FUNCTIONS. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

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+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#define _HAL_WWDG_C_ + +// Files includes +#include "hal_wwdg.h" +#include "hal_rcc.h" + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup MM32_Hardware_Abstract_Layer +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup WWDG_HAL +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @addtogroup WWDG_Exported_Functions +/// @{ + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Deinitializes the WWDG peripheral registers to their default reset +/// values. +/// @param None. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void WWDG_DeInit() +{ + exRCC_APB1PeriphReset(RCC_APB1RSTR_WWDG); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Sets the WWDG Prescaler. +/// @param WWDG_Prescaler: specifies the WWDG Prescaler. +/// This parameter can be one of the following values: +/// @arg WWDG_Prescaler_1: WWDG counter clock = APB1CLK / 4096 / 1 +/// @arg WWDG_Prescaler_2: WWDG counter clock = APB1CLK / 4096 / 2 +/// @arg WWDG_Prescaler_4: WWDG counter clock = APB1CLK / 4096 / 4 +/// @arg WWDG_Prescaler_8: WWDG counter clock = APB1CLK / 4096 / 8 +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void WWDG_SetPrescaler(u32 prescaler) +{ + WWDG->CFGR = (WWDG->CFGR & ~WWDG_CFGR_WDGTB) | prescaler; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Sets the WWDG window value. +/// @param WindowValue: specifies the window value to be compared to the +/// downcounter. +/// This parameter value must be lower than 0x80. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void WWDG_SetWindowValue(u8 window_value) +{ + WWDG->CFGR = (WWDG->CFGR & ~WWDG_CFGR_WINDOW) | (window_value & WWDG_CFGR_WINDOW); +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables the WWDG Early Wakeup interrupt(EWI). +/// @note Once enabled this interrupt cannot be disabled except by a system +/// reset. +/// @param None. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void WWDG_EnableIT() +{ + WWDG->CFGR |= WWDG_CFGR_EWI; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Sets the WWDG counter value. +/// @param Counter: specifies the watchdog counter value. +/// This parameter must be a number between 0x40 and 0x7F (to prevent +/// generating an immediate reset). +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void WWDG_SetCounter(u8 count) +{ + WWDG->CR = count & WWDG_CFGR_WINDOW; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables WWDG and load the counter value. +/// @param Counter: specifies the watchdog counter value. +/// This parameter must be a number between 0x40 and 0x7F (to prevent +/// generating an immediate reset). +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +u32 WWDG_GetCounter() +{ + return WWDG->CR & WWDG_CR_CNT; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Enables WWDG and load the counter value. +/// @param Counter: specifies the watchdog counter value. +/// This parameter must be a number between 0x40 and 0x7F (to prevent +/// generating an immediate reset). +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void WWDG_Enable(u8 count) +{ + WWDG->CR = WWDG_CR_WDGA | count; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Checks whether the Early Wakeup interrupt flag is set or not. +/// @param None. +/// @retval The new state of the Early Wakeup interrupt flag (SET or RESET). +//////////////////////////////////////////////////////////////////////////////// +FlagStatus WWDG_GetFlagStatus() +{ + return WWDG->SR ? SET : RESET; +} + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Clears Early Wakeup interrupt flag. +/// @param None. +/// @retval None. +//////////////////////////////////////////////////////////////////////////////// +void WWDG_ClearFlag() +{ + WWDG->SR &= ~WWDG_SR_EWIF; +} + +/// @} + +/// @} + +/// @} diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_device.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_device.h new file mode 100644 index 000000000..1a85c131a --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_device.h @@ -0,0 +1,23 @@ +///----------------------------------------------------------------------------- +/// @file mm32_device.h +/// @brief CMSIS Cortex-M Peripheral Access Layer for MindMotion +/// microcontroller devices +/// +/// This is a convenience header file for defining the part number on the +/// build command line, instead of specifying the part specific header file. +/// +/// Example: Add MM32 series to your build options, to define part +/// Add "#include "mm32_device.h" to your source files +/// +/// +/// +/// +///----------------------------------------------------------------------------- + +#ifndef __MM32_DEVICE_H +#define __MM32_DEVICE_H + +#include "mm32_reg.h" + +#endif // __MM32_DEVICE_H + diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_reg.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_reg.h new file mode 100644 index 000000000..dfba84215 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_reg.h @@ -0,0 +1,71 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file mm32_reg.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF +/// MM32 FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +//////////////////////////////////////////////////////////////////////////////// +#ifndef __MM32_REG_H +#define __MM32_REG_H + +#include +#include +#include "types.h" + + + + +#include "reg_common.h" +#include "reg_adc.h" +#include "reg_bkp.h" +#include "reg_can.h" +#include "reg_comp.h" +#include "reg_crc.h" +#include "reg_crs.h" +#include "reg_dac.h" +#include "reg_dbg.h" +#include "reg_dma.h" +#include "reg_exti.h" +#include "reg_eth.h" +#include "reg_flash.h" +#include "reg_gpio.h" +#include "reg_i2c.h" +#include "reg_iwdg.h" +#include "reg_pwm.h" +#include "reg_pwr.h" +#include "reg_rcc.h" +#include "reg_rtc.h" +#include "reg_sdio.h" +#include "reg_spi.h" +#include "reg_syscfg.h" +#include "reg_tim.h" +#include "reg_uart.h" +#include "reg_usb_otg_fs.h" +#include "reg_wwdg.h" + +//////////////////////////////////////////////////////////////////////////////// +#include "mm32_reg_redefine_v1.h" +//////////////////////////////////////////////////////////////////////////////// + +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +#endif // __MM32_REG_H +//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_reg_redefine_v1.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_reg_redefine_v1.h new file mode 100644 index 000000000..6cdd79ead --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_reg_redefine_v1.h @@ -0,0 +1,1175 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file mm32_reg_define_v1.H +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE define for version compatibility define +/// FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#ifndef __MM32_REG_DEFINE_V1_H +#define __MM32_REG_DEFINE_V1_H + +// Files includes + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Version compatibility definition +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief redefine for register +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +/// @brief redefine for ADC of MCU register +//////////////////////////////////////////////////////////////////////////////// + +#define ADC_COMP_IRQHandler ADC1_COMP_IRQHandler + +#define ADDATA_DATA ADC_DR_DATA + +#define ADDATA_CHANNELSEL ADC_DR_CH +#define ADDATA_CHANNELSEL_0 ADC_DR_CH0 +#define ADDATA_CHANNELSEL_1 ADC_DR_CH1 +#define ADDATA_CHANNELSEL_2 ADC_DR_CH2 +#define ADDATA_CHANNELSEL_3 ADC_DR_CH3 +#define ADDATA_CHANNELSEL_4 ADC_DR_CH4 +#define ADDATA_CHANNELSEL_5 ADC_DR_CH5 +#define ADDATA_CHANNELSEL_6 ADC_DR_CH6 +#define ADDATA_CHANNELSEL_7 ADC_DR_CH7 + + + + +#define ADDATA_CHANNELSEL_CH8 ADC_DR_CH8 +#define ADDATA_CHANNELSEL_CH9 ADC_DR_CH9 +#define ADDATA_CHANNELSEL_CH10 ADC_DR_CH10 +#define ADDATA_CHANNELSEL_CH11 ADC_DR_CH11 +#define ADDATA_CHANNELSEL_CH12 ADC_DR_CH12 +#define ADDATA_CHANNELSEL_CH13 ADC_DR_CH13 +#define ADDATA_CHANNELSEL_CH14 ADC_DR_CH14 +#define ADDATA_CHANNELSEL_CH15 ADC_DR_CH15 +#define ADDATA_CHANNELSEL_TempSensor ADC_DR_TempSensor +#define ADDATA_CHANNELSEL_VolSensor ADC_DR_VoltRef + + +#define ADDATA_OVERRUN ADC_DR_OVERRUN +#define ADDATA_VALID ADC_DR_VALID + +#define ADCFG_ADEN ADC_CFGR_ADEN +#define ADCFG_ADWEN ADC_CFGR_ADWEN + +#define ADCFG_RSLTCTL ADC_CFGR_RSLTCTL +#define ADCFG_RSLTCTL_12 ADC_CFGR_RSLTCTL_12 +#define ADCFG_RSLTCTL_11 ADC_CFGR_RSLTCTL_11 +#define ADCFG_RSLTCTL_10 ADC_CFGR_RSLTCTL_10 +#define ADCFG_RSLTCTL_9 ADC_CFGR_RSLTCTL_9 +#define ADCFG_RSLTCTL_8 ADC_CFGR_RSLTCTL_8 + + +#define ADCFG_TSEN ADC_CFGR_TEN +#define ADCFG_VSEN ADC_CFGR_VEN + +#define ADCFG_ADCPRE ADC_CFGR_PRE +#define ADCFG_ADCPRE_2 ADC_CFGR_PRE_2 +#define ADCFG_ADCPRE_4 ADC_CFGR_PRE_4 +#define ADCFG_ADCPRE_6 ADC_CFGR_PRE_6 +#define ADCFG_ADCPRE_8 ADC_CFGR_PRE_8 +#define ADCFG_ADCPRE_10 ADC_CFGR_PRE_10 +#define ADCFG_ADCPRE_12 ADC_CFGR_PRE_12 +#define ADCFG_ADCPRE_14 ADC_CFGR_PRE_14 +#define ADCFG_ADCPRE_16 ADC_CFGR_PRE_16 +#define ADCFG_SAMCTL ADC_CFGR_SAMCTL +#define ADCFG_SAMCTL_1_5 ADC_CFGR_SAMCTL_1_5 +#define ADCFG_SAMCTL_7_5 ADC_CFGR_SAMCTL_7_5 +#define ADCFG_SAMCTL_13_5 ADC_CFGR_SAMCTL_13_5 +#define ADCFG_SAMCTL_28_5 ADC_CFGR_SAMCTL_28_5 +#define ADCFG_SAMCTL_41_5 ADC_CFGR_SAMCTL_41_5 +#define ADCFG_SAMCTL_55_5 ADC_CFGR_SAMCTL_55_5 +#define ADCFG_SAMCTL_71_5 ADC_CFGR_SAMCTL_71_5 +#define ADCFG_SAMCTL_239_5 ADC_CFGR_SAMCTL_239_5 + + +#define ADCFG_ADCPRE_3 ADC_CFGR_PRE_3 +#define ADCFG_ADCPRE_5 ADC_CFGR_PRE_5 +#define ADCFG_ADCPRE_7 ADC_CFGR_PRE_7 +#define ADCFG_ADCPRE_9 ADC_CFGR_PRE_9 +#define ADCFG_ADCPRE_11 ADC_CFGR_PRE_11 +#define ADCFG_ADCPRE_13 ADC_CFGR_PRE_13 +#define ADCFG_ADCPRE_15 ADC_CFGR_PRE_15 +#define ADCFG_ADCPRE_17 ADC_CFGR_PRE_17 +#define ADCFG_SAMCTL_2_5 ADC_CFGR_SAMCTL_2_5 +#define ADCFG_SAMCTL_3_5 ADC_CFGR_SAMCTL_3_5 +#define ADCFG_SAMCTL_4_5 ADC_CFGR_SAMCTL_4_5 +#define ADCFG_SAMCTL_5_5 ADC_CFGR_SAMCTL_5_5 +#define ADCFG_SAMCTL_6_5 ADC_CFGR_SAMCTL_6_5 + +#define ADCR_ADIE ADC_CR_ADIE +#define ADCR_ADWIE ADC_CR_ADWIE +#define ADCR_TRGEN ADC_CR_TRGEN +#define ADCR_DMAEN ADC_CR_DMAEN +#define ADCR_ADST ADC_CR_ADST +#define ADCR_ADMD ADC_CR_MODE +#define ADCR_ADMD_SINGLE ADC_CR_IMM +#define ADCR_ADMD_PERIOD ADC_CR_SCAN +#define ADCR_ADMD_CONTINUE ADC_CR_CONTINUE +#define ADC_Mode_Single ADC_CR_IMM +#define ADC_Mode_Single_Period ADC_CR_SCAN +#define ADC_Mode_Continuous_Scan ADC_CR_CONTINUE + + +#define ADCR_ALIGN ADC_CR_ALIGN +#define ADCR_ALIGN_LEFT ADC_CR_LEFT +#define ADCR_ALIGN_RIGHT ADC_CR_RIGHT +#define ADCR_CMPCH_Pos ADC_CR_CMPCH_Pos +#define ADCR_CMPCH ADC_CR_CMPCH +#define ADCR_CMPCH_0 ADC_CR_CMPCH_0 +#define ADCR_CMPCH_1 ADC_CR_CMPCH_1 +#define ADCR_CMPCH_2 ADC_CR_CMPCH_2 +#define ADCR_CMPCH_4 ADC_CR_CMPCH_4 +#define ADCR_CMPCH_5 ADC_CR_CMPCH_5 +#define ADCR_CMPCH_6 ADC_CR_CMPCH_6 +#define ADCR_CMPCH_7 ADC_CR_CMPCH_7 +#define ADCR_CMPCH_8 ADC_CR_CMPCH_8 +#define ADCR_CMPCH_9 ADC_CR_CMPCH_9 +#define ADCR_CMPCH_10 ADC_CR_CMPCH_10 +#define ADCR_CMPCH_11 ADC_CR_CMPCH_11 +#define ADCR_CMPCH_13 ADC_CR_CMPCH_13 +#define ADCR_CMPCH_14 ADC_CR_CMPCH_14 +#define ADCR_CMPCH_ALL ADC_CR_CMPCH_ALL + + +#define ADCR_TRGSEL ADC_CR_TRGSEL +#define ADCR_TRGSEL_T1_CC1 ADC_CR_T1_CC1 +#define ADCR_TRGSEL_T1_CC2 ADC_CR_T1_CC2 +#define ADCR_TRGSEL_T1_CC3 ADC_CR_T1_CC3 +#define ADCR_TRGSEL_T2_CC2 ADC_CR_T2_CC2 +#define ADCR_TRGSEL_T3_TRGO ADC_CR_T3_TRIG +#define ADCR_TRGSEL_EXTI_11 ADC_CR_EXTI_11 + + + +#define ADCR_TRGSEL_T1_CC4_CC5 ADC_CR_T1_CC4_CC5 +#define ADCR_TRGSEL_T3_CC1 ADC_CR_T3_CC1 +#define ADCR_TRGSEL_T1_TRGO ADC_CR_T1_TRIG +#define ADCR_TRGSEL_T8_CC4 ADC_CR_T8_CC4 +#define ADCR_TRGSEL_T8_CC4_CC5 ADC_CR_T8_CC4_CC5 +#define ADCR_TRGSEL_T2_CC1 ADC_CR_T2_CC1 +#define ADCR_TRGSEL_T3_CC4 ADC_CR_T3_CC4 +#define ADCR_TRGSEL_T2_TRGO ADC_CR_T2_TRIG +#define ADCR_TRGSEL_T8_CC5 ADC_CR_T8_CC5 +#define ADCR_TRGSEL_EXTI_15 ADC_CR_EXTI_15 +#define ADCR_TRGSEL_TIM1_CC4 ADC_CR_TIM1_CC4 +#define ADCR_TRGSEL_TIM1_CC5 ADC_CR_TIM1_CC5 +#define ADCR_SCANDIR ADC_CR_SCANDIR +#define ADCR_TRGSHIFT ADC_CR_TRGSHIFT +#define ADCR_TRGSHIFT_0 ADC_CR_TRGSHIFT_0 +#define ADCR_TRGSHIFT_4 ADC_CR_TRGSHIFT_4 +#define ADCR_TRGSHIFT_16 ADC_CR_TRGSHIFT_16 +#define ADCR_TRGSHIFT_32 ADC_CR_TRGSHIFT_32 +#define ADCR_TRGSHIFT_64 ADC_CR_TRGSHIFT_64 +#define ADCR_TRGSHIFT_128 ADC_CR_TRGSHIFT_128 +#define ADCR_TRGSHIFT_256 ADC_CR_TRGSHIFT_256 +#define ADCR_TRGSHIFT_512 ADC_CR_TRGSHIFT_512 +#define ADCR_CALIBEN ADC_CR_CALIBEN +#define ADCR_CALIBSEL ADC_CR_CALIBSEL + +#define ADCHS_CHEN0 ADC_CHSR_CH0 +#define ADCHS_CHEN1 ADC_CHSR_CH1 +#define ADCHS_CHEN2 ADC_CHSR_CH2 +#define ADCHS_CHEN3 ADC_CHSR_CH3 +#define ADCHS_CHEN4 ADC_CHSR_CH4 +#define ADCHS_CHEN5 ADC_CHSR_CH5 +#define ADCHS_CHEN6 ADC_CHSR_CH6 +#define ADCHS_CHEN7 ADC_CHSR_CH7 +#define ADCHS_ALL ADC_CHSR_CHALL + + +#define ADCHS_CHEN8 ADC_CHSR_CH8 +#define ADCHS_CHEN9 ADC_CHSR_CH9 +#define ADCHS_CHENTS ADC_CHSR_CHT +#define ADCHS_CHENVS ADC_CHSR_CHV +#define ADCHS_CHEN8 ADC_CHSR_CH8 +#define ADCHS_CHEN9 ADC_CHSR_CH9 +#define ADCHS_CHEN10 ADC_CHSR_CH10 +#define ADCHS_CHEN11 ADC_CHSR_CH11 +#define ADCHS_CHEN12 ADC_CHSR_CH12 +#define ADCHS_CHEN13 ADC_CHSR_CH13 +#define ADCHS_CHEN14 ADC_CHSR_CH14 +#define ADCHS_CHEN15 ADC_CHSR_CH15 +#define ADCHS_CHENTS ADC_CHSR_CHT +#define ADCHS_CHENVS ADC_CHSR_CHV + + +#define ADCMPR_CMPLDATA ADC_CMPR_CMPLDATA +#define ADCMPR_CMPHDATA ADC_CMPR_CMPHDATA + +#define ADSTA_ADIF ADC_SR_ADIF +#define ADSTA_ADWIF ADC_SR_ADWIF +#define ADSTA_BUSY ADC_SR_BUSY +#define ADSTA_CHANNEL ADC_SR_CH +#define ADSTA_CHANNEL_CH0 ADC_SR_CH0 +#define ADSTA_CHANNEL_CH1 ADC_SR_CH1 +#define ADSTA_CHANNEL_CH2 ADC_SR_CH2 +#define ADSTA_CHANNEL_CH3 ADC_SR_CH3 +#define ADSTA_CHANNEL_CH4 ADC_SR_CH4 +#define ADSTA_CHANNEL_CH5 ADC_SR_CH5 +#define ADSTA_CHANNEL_CH6 ADC_SR_CH6 +#define ADSTA_CHANNEL_CH7 ADC_SR_CH7 +#define ADSTA_CHANNEL_CH8 ADC_SR_CH8 +#define ADSTA_CHANNEL_CH9 ADC_SR_CH9 +#define ADSTA_CHANNEL_CH10 ADC_SR_CH10 +#define ADSTA_CHANNEL_CH11 ADC_SR_CH11 +#define ADSTA_CHANNEL_CH13 ADC_SR_CH13 +#define ADSTA_CHANNEL_CH14 ADC_SR_CH14 +#define ADSTA_CHANNEL_CH15 ADC_SR_CH15 +#define ADSTA_VALID ADC_SR_VALID +#define ADSTA_OVERRUN ADC_SR_OVERRUN + +#define ADDR_OVERRUN ADC_CHDR_OVERRUN +#define ADDR_VALID ADC_CHDR_VALID +#define ADDR_DATA ADC_CHDR_DATA + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief redefine for HAL library +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +/// @brief redefine for ADC of HAL library +//////////////////////////////////////////////////////////////////////////////// + + +#define ADC_ExternalTrigConv_T1_CC1 ADC1_ExternalTrigConv_T1_CC1 +#define ADC_ExternalTrigConv_T1_CC2 ADC1_ExternalTrigConv_T1_CC2 +#define ADC_ExternalTrigConv_T1_CC3 ADC1_ExternalTrigConv_T1_CC3 +#define ADC_ExternalTrigConv_T2_CC2 ADC1_ExternalTrigConv_T2_CC2 +#define ADC_ExternalTrigConv_T3_TRIG ADC1_ExternalTrigConv_T3_TRIG +#define ADC_ExternalTrigConv_T3_CC1 ADC1_ExternalTrigConv_T3_CC1 +#define ADC_ExternalTrigConv_EXTI_11 ADC1_ExternalTrigConv_EXTI_11 +#define ADC_ExternalTrigConv_T1_CC4_CC5 ADC1_ExternalTrigConv_T1_CC4_CC5 +#define ADC_ExternalTrigConv_T1_TRIG ADC1_ExternalTrigConv_T1_TRIG +#define ADC_ExternalTrigConv_T8_CC4 ADC1_ExternalTrigConv_T8_CC4 +#define ADC_ExternalTrigConv_T8_CC4_CC5 ADC1_ExternalTrigConv_T8_CC4_CC5 +#define ADC_ExternalTrigConv_T2_CC1 ADC1_ExternalTrigConv_T2_CC1 +#define ADC_ExternalTrigConv_T3_CC4 ADC1_ExternalTrigConv_T3_CC4 +#define ADC_ExternalTrigConv_T2_TRIG ADC1_ExternalTrigConv_T2_TRIG +#define ADC_ExternalTrigConv_T8_CC5 ADC1_ExternalTrigConv_T8_CC5 +#define ADC_ExternalTrigConv_EXTI_15 ADC1_ExternalTrigConv_EXTI_15 +#define ADC_ExternalTrigConv_T1_CC4 ADC1_ExternalTrigConv_T1_CC4 +#define ADC_ExternalTrigConv_T1_CC5 ADC1_ExternalTrigConv_T1_CC5 + + + +#define ADC_SampleTime_1_5Cycles ADC_Samctl_1_5 +#define ADC_SampleTime_7_5Cycles ADC_Samctl_7_5 +#define ADC_SampleTime_13_5Cycles ADC_Samctl_13_5 +#define ADC_SampleTime_28_5Cycles ADC_Samctl_28_5 +#define ADC_SampleTime_41_5Cycles ADC_Samctl_41_5 +#define ADC_SampleTime_55_5Cycles ADC_Samctl_55_5 +#define ADC_SampleTime_71_5Cycles ADC_Samctl_71_5 +#define ADC_SampleTime_239_5Cycles ADC_Samctl_239_5 + + + + + + + + + + + + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Version compatibility definition +//////////////////////////////////////////////////////////////////////////////// +#define AES_KEYR0 AES_KEYRn ///< AES Key Register 0 +#define AES_KEYR1 AES_KEYRn ///< AES Key Register 1 +#define AES_KEYR2 AES_KEYRn ///< AES Key Register 2 +#define AES_KEYR3 AES_KEYRn ///< AES Key Register 3 +#define AES_KEYR4 AES_KEYRn ///< AES Key Register 4 +#define AES_KEYR5 AES_KEYRn ///< AES Key Register 5 +#define AES_KEYR6 AES_KEYRn ///< AES Key Register 6 +#define AES_KEYR7 AES_KEYRn ///< AES Key Register 7 + +#define AES_IVR0 AES_IVRn ///< AES Initialization Vector Register 0 +#define AES_IVR1 AES_IVRn ///< AES Initialization Vector Register 1 +#define AES_IVR2 AES_IVRn ///< AES Initialization Vector Register 2 +#define AES_IVR3 AES_IVRn ///< AES Initialization Vector Register 3 + + +#define CRC_DR_DR CRC_DR_DATA +#define CRC_IDR_IDR CRC_IDR_DATA +//////////////////////////////////////////////////////////////////////////////// +/// @brief Version compatibility definition +//////////////////////////////////////////////////////////////////////////////// +#define CRS_CR_SYNCOKIE CRS_CR_OKIE +#define CRS_CR_SYNCWARNIE CRS_CR_WARNIE +#define CRS_CR_ESYNCIE CRS_CR_EXPTIE +#define CRS_CR_CEN CRS_CR_CNTEN +#define CRS_CFGR_SYNCDIV CRS_CFGR_DIV +#define CRS_CFGR_SYNCSRC CRS_CFGR_SRC +#define CRS_CFGR_SYNCPOL CRS_CFGR_POL +#define CRS_ISR_SYNCOKF CRS_ISR_OKIF +#define CRS_ISR_SYNCWARNF CRS_ISR_WARNIF +#define CRS_ISR_ERRF CRS_ISR_ERRIF +#define CRS_ISR_ESYNCF CRS_ISR_EXPTIF +#define CRS_ISR_SYNCERR CRS_ISR_ERR +#define CRS_ISR_SYNCMISS CRS_ISR_MISS +#define CRS_ISR_TRIMOVF CRS_ISR_OVERFLOW +#define CRS_ICR_SYNCOKC CRS_ICR_OK +#define CRS_ICR_SYNCWARNC CRS_ICR_WARN +#define CRS_ICR_ERRC CRS_ICR_ERR +#define CRS_ICR_ESYNCC CRS_ICR_EXPT + +#define CRS_IT_SYNCOK CRS_ISR_SYNCOKF ///< SYNC event OK +#define CRS_IT_SYNCWARN CRS_ISR_SYNCWARNF ///< SYNC warning +#define CRS_IT_ERR CRS_CR_ERRIE ///< error +#define CRS_IT_ESYNC CRS_ISR_ESYNCF ///< Expected SYNC +#define CRS_IT_TRIMOVF CRS_ISR_TRIMOVF ///< Trimming overflow or underflow +#define CRS_IT_SYNCERR CRS_ISR_SYNCERR ///< SYNC error +#define CRS_IT_SYNCMISS CRS_ISR_SYNCMISS ///< SYNC missed + +#define CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF ///< SYNC event OK +#define CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF ///< SYNC warning +#define CRS_FLAG_ERR CRS_ISR_ERRF ///< error +#define CRS_FLAG_ESYNC CRS_ISR_ESYNCF ///< Expected SYNC +#define CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF ///< Trimming overflow or underflow +#define CRS_FLAG_SYNCERR CRS_ISR_SYNCERR ///< SYNC error +#define CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS ///< SYNC missed +//////////////////////////////////////////////////////////////////////////////// +/// @brief Version compatibility definition +//////////////////////////////////////////////////////////////////////////////// +#define DIV_UNSIGN DIV_CR_USIGN ///< Unsigned enable +//////////////////////////////////////////////////////////////////////////////// +/// @brief DMA type pointer Definition +//////////////////////////////////////////////////////////////////////////////// + + +#define DMA_CCR_MEM2MEM DMA_CCR_M2M + +#define DMA_CCR1_EN DMA_CCR_EN +#define DMA_CCR1_DIR DMA_CCR_DIR +#define DMA_CCR1_CIRC DMA_CCR_CIRC +#define DMA_CCR1_PINC DMA_CCR_PINC +#define DMA_CCR1_MINC DMA_CCR_MINC +#define DMA_CCR1_PSIZE_0 DMA_CCR_PSIZE_0 +#define DMA_CCR1_MSIZE_0 DMA_CCR_MSIZE_0 +#define DMA_CCR1_PL_0 DMA_CCR_PL_0 +#define DMA_CCR1_PSIZE_1 DMA_CCR_PSIZE_1 +#define DMA_CCR1_MSIZE_1 DMA_CCR_MSIZE_1 +#define DMA_CCR1_PL_1 DMA_CCR_PL_1 +#define DMA_CCR1_MEM2MEM DMA_CCR_M2M +#define DMA_CCR1_TCIE DMA_CCR_TCIE + + + + +//////////////////////////////////////////////////////////////////////////////// +#define EXTI_IMR_MR0 EXTI_IMR_0 +#define EXTI_IMR_MR1 EXTI_IMR_1 +#define EXTI_IMR_MR2 EXTI_IMR_2 +#define EXTI_IMR_MR3 EXTI_IMR_3 +#define EXTI_IMR_MR4 EXTI_IMR_4 +#define EXTI_IMR_MR5 EXTI_IMR_5 +#define EXTI_IMR_MR6 EXTI_IMR_6 +#define EXTI_IMR_MR7 EXTI_IMR_7 +#define EXTI_IMR_MR8 EXTI_IMR_8 +#define EXTI_IMR_MR9 EXTI_IMR_9 +#define EXTI_IMR_MR10 EXTI_IMR_10 +#define EXTI_IMR_MR11 EXTI_IMR_11 +#define EXTI_IMR_MR12 EXTI_IMR_12 +#define EXTI_IMR_MR13 EXTI_IMR_13 +#define EXTI_IMR_MR14 EXTI_IMR_14 +#define EXTI_IMR_MR15 EXTI_IMR_15 +#define EXTI_IMR_MR16 EXTI_IMR_16 + +#define EXTI_EMR_MR0 EXTI_EMR_0 +#define EXTI_EMR_MR1 EXTI_EMR_1 +#define EXTI_EMR_MR2 EXTI_EMR_2 +#define EXTI_EMR_MR3 EXTI_EMR_3 +#define EXTI_EMR_MR4 EXTI_EMR_4 +#define EXTI_EMR_MR5 EXTI_EMR_5 +#define EXTI_EMR_MR6 EXTI_EMR_6 +#define EXTI_EMR_MR7 EXTI_EMR_7 +#define EXTI_EMR_MR8 EXTI_EMR_8 +#define EXTI_EMR_MR9 EXTI_EMR_9 +#define EXTI_EMR_MR10 EXTI_EMR_10 +#define EXTI_EMR_MR11 EXTI_EMR_11 +#define EXTI_EMR_MR12 EXTI_EMR_12 +#define EXTI_EMR_MR13 EXTI_EMR_13 +#define EXTI_EMR_MR14 EXTI_EMR_14 +#define EXTI_EMR_MR15 EXTI_EMR_15 +#define EXTI_EMR_MR16 EXTI_EMR_16 + +#define EXTI_RTSR_TR0 EXTI_RTSR_0 +#define EXTI_RTSR_TR1 EXTI_RTSR_1 +#define EXTI_RTSR_TR2 EXTI_RTSR_2 +#define EXTI_RTSR_TR3 EXTI_RTSR_3 +#define EXTI_RTSR_TR4 EXTI_RTSR_4 +#define EXTI_RTSR_TR5 EXTI_RTSR_5 +#define EXTI_RTSR_TR6 EXTI_RTSR_6 +#define EXTI_RTSR_TR7 EXTI_RTSR_7 +#define EXTI_RTSR_TR8 EXTI_RTSR_8 +#define EXTI_RTSR_TR9 EXTI_RTSR_9 +#define EXTI_RTSR_TR10 EXTI_RTSR_10 +#define EXTI_RTSR_TR11 EXTI_RTSR_11 +#define EXTI_RTSR_TR12 EXTI_RTSR_12 +#define EXTI_RTSR_TR13 EXTI_RTSR_13 +#define EXTI_RTSR_TR14 EXTI_RTSR_14 +#define EXTI_RTSR_TR15 EXTI_RTSR_15 +#define EXTI_RTSR_TR16 EXTI_RTSR_16 + +#define EXTI_FTSR_TR0 EXTI_FTSR_0 +#define EXTI_FTSR_TR1 EXTI_FTSR_1 +#define EXTI_FTSR_TR2 EXTI_FTSR_2 +#define EXTI_FTSR_TR3 EXTI_FTSR_3 +#define EXTI_FTSR_TR4 EXTI_FTSR_4 +#define EXTI_FTSR_TR5 EXTI_FTSR_5 +#define EXTI_FTSR_TR6 EXTI_FTSR_6 +#define EXTI_FTSR_TR7 EXTI_FTSR_7 +#define EXTI_FTSR_TR8 EXTI_FTSR_8 +#define EXTI_FTSR_TR9 EXTI_FTSR_9 +#define EXTI_FTSR_TR10 EXTI_FTSR_10 +#define EXTI_FTSR_TR11 EXTI_FTSR_11 +#define EXTI_FTSR_TR12 EXTI_FTSR_12 +#define EXTI_FTSR_TR13 EXTI_FTSR_13 +#define EXTI_FTSR_TR14 EXTI_FTSR_14 +#define EXTI_FTSR_TR15 EXTI_FTSR_15 +#define EXTI_FTSR_TR16 EXTI_FTSR_16 + +#define EXTI_SWIER_SWIER0 EXTI_SWIER_0 +#define EXTI_SWIER_SWIER1 EXTI_SWIER_1 +#define EXTI_SWIER_SWIER2 EXTI_SWIER_2 +#define EXTI_SWIER_SWIER3 EXTI_SWIER_3 +#define EXTI_SWIER_SWIER4 EXTI_SWIER_4 +#define EXTI_SWIER_SWIER5 EXTI_SWIER_5 +#define EXTI_SWIER_SWIER6 EXTI_SWIER_6 +#define EXTI_SWIER_SWIER7 EXTI_SWIER_7 +#define EXTI_SWIER_SWIER8 EXTI_SWIER_8 +#define EXTI_SWIER_SWIER9 EXTI_SWIER_9 +#define EXTI_SWIER_SWIER10 EXTI_SWIER_10 +#define EXTI_SWIER_SWIER11 EXTI_SWIER_11 +#define EXTI_SWIER_SWIER12 EXTI_SWIER_12 +#define EXTI_SWIER_SWIER13 EXTI_SWIER_13 +#define EXTI_SWIER_SWIER14 EXTI_SWIER_14 +#define EXTI_SWIER_SWIER15 EXTI_SWIER_15 +#define EXTI_SWIER_SWIER16 EXTI_SWIER_16 + +#define EXTI_PR_PR0 EXTI_PR_0 +#define EXTI_PR_PR1 EXTI_PR_1 +#define EXTI_PR_PR2 EXTI_PR_2 +#define EXTI_PR_PR3 EXTI_PR_3 +#define EXTI_PR_PR4 EXTI_PR_4 +#define EXTI_PR_PR5 EXTI_PR_5 +#define EXTI_PR_PR6 EXTI_PR_6 +#define EXTI_PR_PR7 EXTI_PR_7 +#define EXTI_PR_PR8 EXTI_PR_8 +#define EXTI_PR_PR9 EXTI_PR_9 +#define EXTI_PR_PR10 EXTI_PR_10 +#define EXTI_PR_PR11 EXTI_PR_11 +#define EXTI_PR_PR12 EXTI_PR_12 +#define EXTI_PR_PR13 EXTI_PR_13 +#define EXTI_PR_PR14 EXTI_PR_14 +#define EXTI_PR_PR15 EXTI_PR_15 +#define EXTI_PR_PR16 EXTI_PR_16 + +#define EXTI_IMR_MR17 EXTI_IMR_17 + +#define EXTI_IMR_MR18 EXTI_IMR_18 + +#define EXTI_IMR_MR19 EXTI_IMR_19 + +#define EXTI_IMR_MR20 EXTI_IMR_20 + +#define EXTI_IMR_MR21 EXTI_IMR_21 + + +#define EXTI_IMR_MR24 EXTI_IMR_24 + +#define EXTI_EMR_MR17 EXTI_EMR_17 + +#define EXTI_EMR_MR18 EXTI_EMR_18 + +#define EXTI_EMR_MR19 EXTI_EMR_19 + +#define EXTI_EMR_MR20 EXTI_EMR_20 + +#define EXTI_EMR_MR21 EXTI_EMR_21 + + +#define EXTI_EMR_MR24 EXTI_EMR_24 + +#define EXTI_RTSR_MR17 EXTI_RTSR_17 + +#define EXTI_RTSR_MR18 EXTI_RTSR_18 + +#define EXTI_RTSR_MR19 EXTI_RTSR_19 + +#define EXTI_RTSR_MR20 EXTI_RTSR_20 + +#define EXTI_RTSR_MR21 EXTI_RTSR_21 + + +#define EXTI_RTSR_MR24 EXTI_RTSR_24 + +#define EXTI_FTSR_MR17 EXTI_FTSR_18 + +#define EXTI_FTSR_MR18 EXTI_FTSR_18 + +#define EXTI_FTSR_MR19 EXTI_FTSR_19 + +#define EXTI_FTSR_MR20 EXTI_FTSR_20 + +#define EXTI_FTSR_MR21 EXTI_FTSR_21 + + +#define EXTI_FTSR_MR24 EXTI_FTSR_24 + +#define EXTI_SWIER_MR17 EXTI_SWIER_17 + +#define EXTI_SWIER_MR18 EXTI_SWIER_18 + +#define EXTI_SWIER_MR19 EXTI_SWIER_19 + +#define EXTI_SWIER_MR20 EXTI_SWIER_20 + +#define EXTI_SWIER_MR21 EXTI_SWIER_21 + + +#define EXTI_SWIER_MR24 EXTI_SWIER_24 + +#define EXTI_PR_MR17 EXTI_PR_17 + +#define EXTI_PR_MR18 EXTI_PR_18 + +#define EXTI_PR_MR19 EXTI_PR_19 + +#define EXTI_PR_MR20 EXTI_PR_20 + +#define EXTI_PR_MR21 EXTI_PR_21 + + +#define EXTI_PR_MR24 EXTI_PR_24 + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Version compatibility definition +//////////////////////////////////////////////////////////////////////////////// + +#define GPIO_Mode_IN_FLOATING GPIO_Mode_FLOATING + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Version compatibility definition +//////////////////////////////////////////////////////////////////////////////// +//Bit +#define I2C_CON_MASTER_MODE I2C_CR_MASTER +#define I2C_CON_SPEED I2C_CR_SPEED +#define I2C_CON_SPEED_STANDARD I2C_CR_STD +#define I2C_CON_SPEED_FAST I2C_CR_FAST +#define I2C_CON_10BITADDR_SLAVE I2C_CR_SLAVE10 +#define I2C_CON_10BITADDR_MASTER I2C_CR_MASTER10 +#define I2C_CON_RESTART_EN I2C_CR_REPEN +#define I2C_CON_SLAVE_DISABLE I2C_CR_SLAVEDIS +#define I2C_CON_STOP_DET_IFADDRESSED I2C_CR_STOPINT +#define I2C_CON_EMPTY_CTRL I2C_CR_EMPINT +#define I2C_CON_STOP I2C_CR_STOP +#define I2C_CON_RESTART I2C_CR_RESTART + +#define I2C_TAR_TAR I2C_TAR_ADDR +#define I2C_TAR_GC_OR_START I2C_TAR_GC +#define I2C_SAR_SAR I2C_SAR_ADDR +#define I2C_DATA_CMD_DAT I2C_DR_DAT +#define I2C_DATA_CMD_CMD I2C_DR_CMD +#define I2C_DATA_CMD_STOP I2C_DR_STOP +#define I2C_DATA_CMD_RESTART I2C_DR_RESTART + +#define I2C_SS_SCL_HCNT I2C_SSHR_CNT +#define I2C_SS_SCL_LCNT I2C_SSLR_CNT +#define I2C_FS_SCL_HCNT I2C_FSHR_CNT +#define I2C_FS_SCL_LCNT I2C_FSLR_CNT + +#define I2C_INTR_STAT_RX_UNDER I2C_ISR_RX_UNDER +#define I2C_INTR_STAT_RX_OVER I2C_ISR_RX_OVER +#define I2C_INTR_STAT_RX_FULL I2C_ISR_RX_FULL +#define I2C_INTR_STAT_TX_OVER I2C_ISR_TX_OVER +#define I2C_INTR_STAT_TX_EMPTY I2C_ISR_TX_EMPTY +#define I2C_INTR_STAT_RX_REQ I2C_ISR_RX_REQ +#define I2C_INTR_STAT_TX_ABRT I2C_ISR_TX_ABRT +#define I2C_INTR_STAT_RX_DONE I2C_ISR_RX_DONE +#define I2C_INTR_STAT_ACTIVITY I2C_ISR_ACTIV +#define I2C_INTR_STAT_STOP_DET I2C_ISR_STOP +#define I2C_INTR_STAT_START_DET I2C_ISR_START +#define I2C_INTR_STAT_GEN_CALL I2C_ISR_GC +#define I2C_INTR_STAT_RESTART_DET I2C_ISR_RESTART +#define I2C_INTR_STAT_MST_ON_HOLD I2C_ISR_HOLD + +#define I2C_INTR_MASK_RX_UNDER I2C_IMR_RX_UNDER +#define I2C_INTR_MASK_RX_OVER I2C_IMR_RX_OVER +#define I2C_INTR_MASK_RX_FULL I2C_IMR_RX_FULL +#define I2C_INTR_MASK_TX_OVER I2C_IMR_TX_OVER +#define I2C_INTR_MASK_TX_EMPTY I2C_IMR_TX_EMPTY +#define I2C_INTR_MASK_RX_REQ I2C_IMR_RX_REQ +#define I2C_INTR_MASK_TX_ABRT I2C_IMR_TX_ABRT +#define I2C_INTR_MASK_RX_DONE I2C_IMR_RX_DONE +#define I2C_INTR_MASK_ACTIVITY I2C_IMR_ACTIV +#define I2C_INTR_MASK_STOP_DET I2C_IMR_STOP +#define I2C_INTR_MASK_START_DET I2C_IMR_START +#define I2C_INTR_MASK_GEN_CALL I2C_IMR_GC +#define I2C_INTR_MASK_RESTART_DET I2C_IMR_RESTART +#define I2C_INTR_MASK_MST_ON_HOLD I2C_IMR_HOLD + +#define I2C_RAW_INTR_MASK_RX_UNDER I2C_RAWISR_RX_UNDER +#define I2C_RAW_INTR_MASK_RX_OVER I2C_RAWISR_RX_OVER +#define I2C_RAW_INTR_MASK_RX_FULL I2C_RAWISR_RX_FULL +#define I2C_RAW_INTR_MASK_TX_OVER I2C_RAWISR_TX_OVER +#define I2C_RAW_INTR_MASK_TX_EMPTY I2C_RAWISR_TX_EMPTY +#define I2C_RAW_INTR_MASK_RX_REQ I2C_RAWISR_RX_REQ +#define I2C_RAW_INTR_MASK_TX_ABRT I2C_RAWISR_TX_ABRT +#define I2C_RAW_INTR_MASK_RX_DONE I2C_RAWISR_RX_DONE +#define I2C_RAW_INTR_MASK_ACTIVITY I2C_RAWISR_ACTIV +#define I2C_RAW_INTR_MASK_STOP_DET I2C_RAWISR_STOP +#define I2C_RAW_INTR_MASK_START_DET I2C_RAWISR_START +#define I2C_RAW_INTR_MASK_GEN_CALL I2C_RAWISR_GC +#define I2C_RAW_INTR_MASK_RESTART_DET I2C_RAWISR_RESTART +#define I2C_RAW_INTR_MASK_MST_ON_HOLD I2C_RAWISR_HOLD + +#define I2C_RX_TL I2C_RXTLR_TL +#define I2C_TX_TL I2C_TXTLR_TL + +#define I2C_CLR_INTR I2C_ICR +#define I2C_CLR_RX_UNDER I2C_RX_UNDER +#define I2C_CLR_RX_OVER I2C_RX_OVER +#define I2C_CLR_TX_OVER I2C_TX_OVER +#define I2C_RX_REQ I2C_RD_REQ +#define I2C_CLR_RX_REQ I2C_RD_REQ +#define I2C_CLR_TX_ABRT I2C_TX_ABRT +#define I2C_CLR_RX_DONE I2C_RX_DONE +#define I2C_CLR_ACTIVITY I2C_ACTIV +#define I2C_CLR_STOP_DET I2C_STOP +#define I2C_CLR_START_DET I2C_START +#define I2C_CLR_GEN_CALL I2C_GC + +#define I2C_ENABLE_ENABLE I2C_ENR_ENABLE +#define I2C_ENABLE_ABORT I2C_ENR_ABORT + +#define I2C_STATUS_ACTIVITY I2C_SR_ACTIV +#define I2C_STATUS_TFNF I2C_SR_TFNF +#define I2C_STATUS_TFE I2C_SR_TFE +#define I2C_STATUS_RFNE I2C_SR_RFNE +#define I2C_STATUS_RFF I2C_SR_RFF +#define I2C_STATUS_MST_ACTIVITY I2C_SR_MST_ACTIV +#define I2C_STATUS_SLV_ACTIVITY I2C_SR_SLV_ACTIV + +#define I2C_TXFLR I2C_TXFLR_CNT +#define I2C_RXFLR I2C_RXFLR_CNT + +#define I2C_SDA_TX_HOLD I2C_HOLD_TXCNT +#define I2C_SDA_RX_HOLD I2C_HOLD_RXCNT +#define I2C_DMA_CR_RDMAE I2C_DMA_RXEN +#define I2C_DMA_CR_TDMAE I2C_DMA_TXEN +#define I2C_SDA_SET_UP I2C_SETUP_CNT +#define I2C_ACK_GENERAL_CALL I2C_GCR_GC + + +#define IWDG_PR_PR IWDG_PR_PRE +#define IWDG_PR_PR_DIV4 IWDG_PR_PRE_DIV4 +#define IWDG_PR_PR_DIV8 IWDG_PR_PRE_DIV8 +#define IWDG_PR_PR_DIV16 IWDG_PR_PRE_DIV16 +#define IWDG_PR_PR_DIV32 IWDG_PR_PRE_DIV32 +#define IWDG_PR_PR_DIV64 IWDG_PR_PRE_DIV64 +#define IWDG_PR_PR_DIV128 IWDG_PR_PRE_DIV128 +#define IWDG_PR_PR_DIV256 IWDG_PR_PRE_DIV256 +//////////////////////////////////////////////////////////////////////////////// +/// @brief Version compatibility definition +//////////////////////////////////////////////////////////////////////////////// +#define RCC_AHBENR_DMAEN RCC_AHBENR_DMA1 +#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1 + + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup AHB_peripheral +/// @{ +#define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1 +#define RCC_AHBPeriph_SRAM RCC_AHBENR_SRAM +#define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITF +#define RCC_AHBPeriph_CRC RCC_AHBENR_CRC +#define RCC_AHBPeriph_AES RCC_AHBENR_AES +#define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOA +#define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOB +#define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOC +#define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIOD + + +#define RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOE +#define RCC_AHBPeriph_HIV RCC_AHBENR_HWDIV +#define RCC_AHBPeriph_HWDIV RCC_AHBENR_HWDIV + + + + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup APB2_peripheral +/// @{ +#define RCC_APB2Periph_ADC1 RCC_APB2ENR_ADC1 +#define RCC_APB2Periph_TIM1 RCC_APB2ENR_TIM1 +#define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1 +#define RCC_APB2Periph_UART1 RCC_APB2ENR_UART1 +#define RCC_APB2Periph_COMP RCC_APB2ENR_COMP +#define RCC_APB2Periph_DBGMCU RCC_APB2ENR_DBGMCU + +#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1 +#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1 +#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1 + +#define RCC_APB2Periph_ADC2 RCC_APB2ENR_ADC2 +#define RCC_APB2Periph_ADC3 RCC_APB2ENR_ADC3 +#define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFG +#define RCC_APB2Periph_EXTI RCC_APB2ENR_EXTI + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +/// @defgroup APB1_peripheral +/// @{ +#define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2 +#define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3 +#define RCC_APB1Periph_TIM4 RCC_APB1ENR_TIM4 +#define RCC_APB1Periph_UART3 RCC_APB1ENR_UART3 +#define RCC_APB1Periph_BKP RCC_APB1ENR_BKP +#define RCC_APB1Periph_DAC RCC_APB1ENR_DAC +#define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2 +#define RCC_APB1Periph_ALL 0x3AE64807 +#define RCC_APB1Periph_CAN1 RCC_APB1ENR_CAN +#define RCC_APB1Periph_CRS RCC_APB1ENR_CRS +#define RCC_APB1Periph_UART2 RCC_APB1ENR_UART2 +#define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1 +#define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2 +#define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDG +#define RCC_APB1Periph_PWR RCC_APB1ENR_PWR + +#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWR +#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2 +#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3 +#define RCC_APB1ENR_SYSCFG RCC_APB1ENR_EXTI + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief RTC_CR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define RTC_CRH_SECIE_Pos RTC_CR_SECIE_Pos +#define RTC_CRH_SECIE RTC_CR_SECIE ///< Second Interrupt Enable +#define RTC_CRH_ALRIE_Pos RTC_CR_ALRIE_Pos +#define RTC_CRH_ALRIE RTC_CR_ALRIE ///< Alarm Interrupt Enable +#define RTC_CRH_OWIE_Pos RTC_CR_OWIE_Pos +#define RTC_CRH_OWIE RTC_CR_OWIE ///< OverfloW Interrupt Enable + +//////////////////////////////////////////////////////////////////////////////// +/// @brief RTC_CSR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define RTC_CRL_SECF_Pos RTC_CSR_SECF_Pos +#define RTC_CRL_SECF RTC_CSR_SECF ///< Second Flag +#define RTC_CRL_ALRF_Pos RTC_CSR_ALRF_Pos +#define RTC_CRL_ALRF RTC_CSR_ALRF ///< Alarm Flag +#define RTC_CRL_OWF_Pos RTC_CSR_OWF_Pos +#define RTC_CRL_OWF RTC_CSR_OWF ///< OverfloW Flag +#define RTC_CRL_RSF_Pos RTC_CSR_RSF_Pos +#define RTC_CRL_RSF RTC_CSR_RSF ///< Registers Synchronized Flag +#define RTC_CRL_CNF_Pos RTC_CSR_CNF_Pos +#define RTC_CRL_CNF RTC_CSR_CNF ///< Configuration Flag +#define RTC_CRL_RTOFF_Pos RTC_CSR_RTOFF_Pos +#define RTC_CRL_RTOFF RTC_CSR_RTOFF ///< RTC operation OFF +#define RTC_CRL_ALPEN_Pos RTC_CSR_ALPEN_Pos +#define RTC_CRL_ALPEN RTC_CSR_ALPEN ///< RTC Alarm Loop Enable + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Version compatibility definition +//////////////////////////////////////////////////////////////////////////////// +#define SPI_TXREG_TXREG SPI_TDR_TXREG +#define SPI_RXREG_RXREG SPI_RDR_RXREG + +#define SPI_CSTAT_TXEPT SPI_SR_TXEPT +#define SPI_CSTAT_RXAVL SPI_SR_RXAVL +#define SPI_CSTAT_TXFULL SPI_SR_TXFULL +#define SPI_CSTAT_RXAVL_4BYTE SPI_SR_RXAVL_4BYTE +#define SPI_CSTAT_TXFADDR SPI_SR_TXFADDR +#define SPI_CSTAT_RXFADDR SPI_SR_RXFADDR + +#define SPI_INTSTAT_TX_INTF SPI_ISR_TX_INTF +#define SPI_INTSTAT_RX_INTF SPI_ISR_RX_INTF +#define SPI_INTSTAT_UNDERRUN_INTF SPI_ISR_UNDERRUN_INTF +#define SPI_INTSTAT_RXOERR_INTF SPI_ISR_RXOERR_INTF +#define SPI_INTSTAT_RXMATCH_INTF SPI_ISR_RXMATCH_INTF +#define SPI_INTSTAT_RXFULL_INTF SPI_ISR_RXFULL_INTF +#define SPI_INTSTAT_TXEPT_INTF SPI_ISR_TXEPT_INTF + +#define SPI_INTEN_TX_IEN SPI_IER_TX_IEN +#define SPI_INTEN_RX_IEN SPI_IER_RX_IEN +#define SPI_INTEN_UNDERRUN_IEN SPI_IER_UNDERRUN_IEN +#define SPI_INTEN_RXOERR_IEN SPI_IER_RXOERR_IEN +#define SPI_INTEN_RXMATCH_IEN SPI_IER_RXMATCH_IEN +#define SPI_INTEN_RXFULL_IEN SPI_IER_RXFULL_IEN +#define SPI_INTEN_TXEPT_IEN SPI_IER_TXEPT_IEN + +#define SPI_INTCLR_TX_ICLR SPI_ICR_TX_ICLR +#define SPI_INTCLR_RX_ICLR SPI_ICR_RX_ICLR +#define SPI_INTCLR_UNDERRUN_ICLR SPI_ICR_UNDERRUN_ICLR +#define SPI_INTCLR_RXOERR_ICLR SPI_ICR_RXOERR_ICLR +#define SPI_INTCLR_RXMATCH_ICLR SPI_ICR_RXMATCH_ICLR +#define SPI_INTCLR_RXFULL_ICLR SPI_ICR_RXFULL_ICLR +#define SPI_INTCLR_TXEPT_ICLR SPI_ICR_TXEPT_ICLR + +#define SPI_GCTL_SPIEN SPI_GCR_SPIEN +#define SPI_GCTL_INT_EN SPI_GCR_IEN +#define SPI_GCTL_MM SPI_GCR_MODE +#define SPI_GCTL_TXEN SPI_GCR_TXEN +#define SPI_GCTL_RXEN SPI_GCR_RXEN + +#define SPI_GCTL_RXTLF SPI_GCR_RXTLF +#define SPI_GCTL_RXTLF_One SPI_GCR_RXTLF_One +#define SPI_GCTL_RXTLF_Half SPI_GCR_RXTLF_Half + +#define SPI_GCTL_TXTLF_Pos SPI_GCR_TXTLF_Pos +#define SPI_GCTL_TXTLF SPI_GCR_TXTLF +#define SPI_GCTL_TXTLF_One SPI_GCR_TXTLF_One +#define SPI_GCTL_TXTLF_Half SPI_GCR_TXTLF_Half +#define SPI_GCTL_DMAEN SPI_GCR_DMAEN +#define SPI_GCTL_NSS_SEL SPI_GCR_NSS +#define SPI_GCTL_DATA_SEL SPI_GCR_DWSEL + +#define SPI_GCTL_NSSTOG SPI_GCR_NSSTOG + +#define SPI_CCTL_CPHA SPI_CCR_CPHA +#define SPI_CCTL_CPOL SPI_CCR_CPOL +#define SPI_CCTL_LSBFE SPI_CCR_LSBFE +#define SPI_CCTL_SPILEN SPI_CCR_SPILEN +#define SPI_CCTL_RXEDGE SPI_CCR_RXEDGE +#define SPI_CCTL_TXEDGE SPI_CCR_TXEDGE + +#define SPI_CCTL_CPHASEL SPI_CCR_CPHASEL + +#define SPI_CCTL_HISPD SPI_CCR_HISPD + +#define SPI_SPBRG_SPBRG SPI_BRR_DIVF + +#define SPI_RXDNR_RXDNR SPI_RDNR_RDN + +#define SPI_EXTCTL_EXTLEN SPI_ECR_EXTLEN +#define TIM_CR1_ARPE TIM_CR1_ARPEN + +#define TIM_SMCR_ECE TIM_SMCR_ECEN + +#define TIM_DIER_UIE TIM_DIER_UI +#define TIM_DIER_CC1IE TIM_DIER_CC1I +#define TIM_DIER_CC2IE TIM_DIER_CC2I +#define TIM_DIER_CC3IE TIM_DIER_CC3I +#define TIM_DIER_CC4IE TIM_DIER_CC4I +#define TIM_DIER_COMIE TIM_DIER_COMI +#define TIM_DIER_TIE TIM_DIER_TI +#define TIM_DIER_BIE TIM_DIER_BI +#define TIM_DIER_UDE TIM_DIER_UD +#define TIM_DIER_CC1DE TIM_DIER_CC1D +#define TIM_DIER_CC2DE TIM_DIER_CC2D +#define TIM_DIER_CC3DE TIM_DIER_CC3D +#define TIM_DIER_CC4DE TIM_DIER_CC4D +#define TIM_DIER_COMDE TIM_DIER_COMD +#define TIM_DIER_TDE TIM_DIER_TD + +#define TIM_DIER_UIEN TIM_DIER_UI +#define TIM_DIER_CC1IEN TIM_DIER_CC1I +#define TIM_DIER_CC2IEN TIM_DIER_CC2I +#define TIM_DIER_CC3IEN TIM_DIER_CC3I +#define TIM_DIER_CC4IEN TIM_DIER_CC4I +#define TIM_DIER_COMIEN TIM_DIER_COMI +#define TIM_DIER_TIEN TIM_DIER_TI +#define TIM_DIER_BIEN TIM_DIER_BI +#define TIM_DIER_UDEN TIM_DIER_UD +#define TIM_DIER_CC1DEN TIM_DIER_CC1D +#define TIM_DIER_CC2DEN TIM_DIER_CC2D +#define TIM_DIER_CC3DEN TIM_DIER_CC3D +#define TIM_DIER_CC4DEN TIM_DIER_CC4D +#define TIM_DIER_COMDEN TIM_DIER_COMD +#define TIM_DIER_TDEN TIM_DIER_TD + +#define TIM_DIER_CC5IE TIM_DIER_CC5I +#define TIM_DIER_CC5DE TIM_DIER_CC5D + +#define TIM_SR_UIF TIM_SR_UI +#define TIM_SR_CC1IF TIM_SR_CC1I +#define TIM_SR_CC2IF TIM_SR_CC2I +#define TIM_SR_CC3IF TIM_SR_CC3I +#define TIM_SR_CC4IF TIM_SR_CC4I +#define TIM_SR_COMIF TIM_SR_COMI +#define TIM_SR_TIF TIM_SR_TI +#define TIM_SR_BIF TIM_SR_BI +#define TIM_SR_CC1OF TIM_SR_CC1O +#define TIM_SR_CC2OF TIM_SR_CC2O +#define TIM_SR_CC3OF TIM_SR_CC3O +#define TIM_SR_CC4OF TIM_SR_CC4O + +#define TIM_SR_CC5IF TIM_SR_CC5I + +#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FEN +#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PEN +#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CEN +#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FEN +#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PEN +#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CEN + +#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FEN +#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PEN +#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CEN +#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FEN +#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PEN +#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CEN + +#define TIM_CCER_CC1E TIM_CCER_CC1EN +#define TIM_CCER_CC1NE TIM_CCER_CC1NEN +#define TIM_CCER_CC2E TIM_CCER_CC2EN +#define TIM_CCER_CC2NE TIM_CCER_CC2NEN +#define TIM_CCER_CC3E TIM_CCER_CC3EN +#define TIM_CCER_CC3NE TIM_CCER_CC3NEN +#define TIM_CCER_CC4E TIM_CCER_CC4EN + +#define TIM_CCER_CC5E TIM_CCER_CC5EN + +#define TIM_BDTR_BKE TIM_BDTR_BKEN +#define TIM_BDTR_AOE TIM_BDTR_AOEN +#define TIM_BDTR_MOE TIM_BDTR_MOEN + +#define TIM_BDTR_DOE TIM_BDTR_DOEN + +#define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FEN +#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PEN +#define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CEN +#define UART_TDR_TXREG UART_TDR_DATA +#define UART_RDR_RXREG UART_RDR_DATA + +#define UART_ISR_TX_INTF UART_ISR_TX +#define UART_ISR_RX_INTF UART_ISR_RX +#define UART_ISR_RXOERR_INTF UART_ISR_RXOERR +#define UART_ISR_RXPERR_INTF UART_ISR_RXPERR +#define UART_ISR_RXFERR_INTF UART_ISR_RXFERR +#define UART_ISR_RXBRK_INTF UART_ISR_RXBRK + +#define UART_IER_TXIEN UART_IER_TX +#define UART_IER_RXIEN UART_IER_RXI +#define UART_IER_RXOERREN UART_IER_RXOERR +#define UART_IER_RXPERREN UART_IER_RXPERR +#define UART_IER_RXFERREN UART_IER_RXFERR +#define UART_IER_RXBRKEN UART_IER_RXBRK + +#define UART_ICR_TXICLR UART_ICR_TX +#define UART_ICR_RXICLR UART_ICR_RX +#define UART_ICR_RXOERRCLR UART_ICR_RXOERR +#define UART_ICR_RXPERRCLR UART_ICR_RXPERR +#define UART_ICR_RXFERRCLR UART_ICR_RXFERR +#define UART_ICR_RXBRKCLR UART_ICR_RXBRK + +#define UART_Mode_Rx UART_GCR_RX +#define UART_Mode_Tx UART_GCR_TX +#define UART_EN UART_GCR_UART +#define UART_IT_RXBRK UART_IER_RXBRK +#define UART_IT_ERR UART_IER_RXFERR +#define UART_IT_PE UART_IER_RXPERR +#define UART_OVER_ERR UART_IER_RXOERR +#define UART_IT_RXIEN UART_IER_RX +#define UART_IT_TXIEN UART_IER_TX + +#define UART_HardwareFlowControl_None UART_HWFlowControl_None + +#define UART_BRR_DIV_MANTISSA UART_BRR_MANTISSA +#define UART_BRR_DIV_FRACTION UART_BRR_FRACTION + +#define UART_ISR_TXC_INTF UART_ISR_TXC +#define UART_ISR_TXBRK_INTF UART_ISR_TXBRK +#define UART_ISR_RXB8_INTF UART_ISR_RXB8 + +#define UART_IT_RXB8 UART_IER_RXB8 +#define UART_IT_TXBRK UART_IER_TXBRK +#define UART_IT_TXCIEN UART_IER_TXC +#define UART_ICR_TXCCLR UART_ICR_TXC +#define UART_ICR_TXBRKCLR UART_ICR_TXBRK +#define UART_ICR_RXB8CLR UART_ICR_RXB8 +#define UART_SCR_SCAEN UART_SCR_SCARB +#define UART_DMAReq_EN UART_GCR_DMA +#define UART_FLAG_TXEMPTY UART_CSR_TXEPT +#define UART_FLAG_TXFULL UART_CSR_TXFULL +#define UART_FLAG_RXAVL UART_CSR_RXAVL +#define UART_FLAG_TXEPT UART_CSR_TXC +#define WWDG_CR_T WWDG_CR_CNT + + +#if defined(ENABLEIP_USB_OTG) +//USB + +///------------------- Bit definition for SETUP0 register -------------------- + +//#define SETUP0 ((u16)0x00FF) + +///------------------- Bit definition for SETUP1 register -------------------- +//#define SETUP1 ((u16)0x00FF) + +///------------------- Bit definition for SETUP2 register -------------------- +//#define SETUP2 ((u16)0x00FF) + +///------------------- Bit definition for SETUP3 register -------------------- +//#define SETUP3 ((u16)0x00FF) + +///------------------- Bit definition for SETUP4 register -------------------- +//#define SETUP4 ((u16)0x00FF) + +///------------------- Bit definition for SETUP5 register -------------------- +//#define SETUP5 ((u16)0x00FF) + +///------------------- Bit definition for SETUP6 register -------------------- +//#define SETUP6 ((u16)0x00FF) + +///------------------- Bit definition for SETUP7 register -------------------- +//#define SETUP7 ((u16)0x00FF) + + + +#define USB_TOP_STATE_0 ((u16)0x0020) +#define USB_TOP_STATE_1 ((u16)0x0040) + +///------------------- Bit definition for EP1_INT_STATE register -------------------- +#define EP1_INT_STATE_END ((u16)0x0002) +#define EP1_INT_STATE_INNACK ((u16)0x0004) +#define EP1_INT_STATE_INACK ((u16)0x0008) +#define EP1_INT_STATE_INSTALL ((u16)0x0010) +#define EP1_INT_STATE_OUTNACK ((u16)0x0020) +#define EP1_INT_STATE_OUTACK ((u16)0x0040) +#define EP1_INT_STATE_OUTSTALL ((u16)0x0080) + +///------------------- Bit definition for EP2_INT_STATE register -------------------- +#define EP2_INT_STATE_END ((u16)0x0002) +#define EP2_INT_STATE_INNACK ((u16)0x0004) +#define EP2_INT_STATE_INACK ((u16)0x0008) +#define EP2_INT_STATE_INSTALL ((u16)0x0010) +#define EP2_INT_STATE_OUTNACK ((u16)0x0020) +#define EP2_INT_STATE_OUTACK ((u16)0x0040) +#define EP2_INT_STATE_OUTSTALL ((u16)0x0080) + +///------------------- Bit definition for EP3_INT_STATE register -------------------- +#define EP3_INT_STATE_END ((u16)0x0002) +#define EP3_INT_STATE_INNACK ((u16)0x0004) +#define EP3_INT_STATE_INACK ((u16)0x0008) +#define EP3_INT_STATE_INSTALL ((u16)0x0010) +#define EP3_INT_STATE_OUTNACK ((u16)0x0020) +#define EP3_INT_STATE_OUTACK ((u16)0x0040) +#define EP3_INT_STATE_OUTSTALL ((u16)0x0080) + +///------------------- Bit definition for EP4_INT_STATE register -------------------- +#define EP4_INT_STATE_END ((u16)0x0002) +#define EP4_INT_STATE_INNACK ((u16)0x0004) +#define EP4_INT_STATE_INACK ((u16)0x0008) +#define EP4_INT_STATE_INSTALL ((u16)0x0010) +#define EP4_INT_STATE_OUTNACK ((u16)0x0020) +#define EP4_INT_STATE_OUTACK ((u16)0x0040) +#define EP4_INT_STATE_OUTSTALL ((u16)0x0080) + + +///------------------- Bit definition for EP0_AVIL register -------------------- +#define EP0_AVIL_EPXAVIL ((u16)0x00FF) + +///------------------- Bit definition for EP1_AVIL register -------------------- +#define EP1_AVIL_EPXAVIL ((u16)0x00FF) + +///------------------- Bit definition for EP2_AVIL register -------------------- +#define EP2_AVIL_EPXAVIL ((u16)0x00FF) + +///------------------- Bit definition for EP3_AVIL register -------------------- +#define EP3_AVIL_EPXAVIL ((u16)0x00FF) + +///------------------- Bit definition for EP4_AVIL register -------------------- +#define EP4_AVIL_EPXAVIL ((u16)0x00FF) + +///------------------- Bit definition for EP0_CTRL register -------------------- +#define EP0_CTRL_TRANEN ((u16)0x0080) + +#define EP0_CTRL_TRANCOUNT ((u16)0x007F) +#define EP0_CTRL_TRANCOUNT_0 ((u16)0x0001) +#define EP0_CTRL_TRANCOUNT_1 ((u16)0x0002) +#define EP0_CTRL_TRANCOUNT_2 ((u16)0x0004) +#define EP0_CTRL_TRANCOUNT_3 ((u16)0x0008) +#define EP0_CTRL_TRANCOUNT_4 ((u16)0x0010) +#define EP0_CTRL_TRANCOUNT_5 ((u16)0x0020) +#define EP0_CTRL_TRANCOUNT_6 ((u16)0x0040) + +///------------------- Bit definition for EP1_CTRL register -------------------- +#define EP1_CTRL_TRANEN ((u16)0x0080) + +#define EP1_CTRL_TRANCOUNT ((u16)0x007F) +#define EP1_CTRL_TRANCOUNT_0 ((u16)0x0001) +#define EP1_CTRL_TRANCOUNT_1 ((u16)0x0002) +#define EP1_CTRL_TRANCOUNT_2 ((u16)0x0004) +#define EP1_CTRL_TRANCOUNT_3 ((u16)0x0008) +#define EP1_CTRL_TRANCOUNT_4 ((u16)0x0010) +#define EP1_CTRL_TRANCOUNT_5 ((u16)0x0020) +#define EP1_CTRL_TRANCOUNT_6 ((u16)0x0040) + +///------------------- Bit definition for EP2_CTRL register -------------------- +#define EP2_CTRL_TRANEN ((u16)0x0080) + +#define EP2_CTRL_TRANCOUNT ((u16)0x007F) +#define EP2_CTRL_TRANCOUNT_0 ((u16)0x0001) +#define EP2_CTRL_TRANCOUNT_1 ((u16)0x0002) +#define EP2_CTRL_TRANCOUNT_2 ((u16)0x0004) +#define EP2_CTRL_TRANCOUNT_3 ((u16)0x0008) +#define EP2_CTRL_TRANCOUNT_4 ((u16)0x0010) +#define EP2_CTRL_TRANCOUNT_5 ((u16)0x0020) +#define EP2_CTRL_TRANCOUNT_6 ((u16)0x0040) + +///------------------- Bit definition for EP3_CTRL register -------------------- +#define EP3_CTRL_TRANEN ((u16)0x0080) + +#define EP3_CTRL_TRANCOUNT ((u16)0x007F) +#define EP3_CTRL_TRANCOUNT_0 ((u16)0x0001) +#define EP3_CTRL_TRANCOUNT_1 ((u16)0x0002) +#define EP3_CTRL_TRANCOUNT_2 ((u16)0x0004) +#define EP3_CTRL_TRANCOUNT_3 ((u16)0x0008) +#define EP3_CTRL_TRANCOUNT_4 ((u16)0x0010) +#define EP3_CTRL_TRANCOUNT_5 ((u16)0x0020) +#define EP3_CTRL_TRANCOUNT_6 ((u16)0x0040) + +///------------------- Bit definition for EP4_CTRL register -------------------- +#define EP4_CTRL_TRANEN ((u16)0x0080) + +#define EP4_CTRL_TRANCOUNT ((u16)0x007F) +#define EP4_CTRL_TRANCOUNT_0 ((u16)0x0001) +#define EP4_CTRL_TRANCOUNT_1 ((u16)0x0002) +#define EP4_CTRL_TRANCOUNT_2 ((u16)0x0004) +#define EP4_CTRL_TRANCOUNT_3 ((u16)0x0008) +#define EP4_CTRL_TRANCOUNT_4 ((u16)0x0010) +#define EP4_CTRL_TRANCOUNT_5 ((u16)0x0020) +#define EP4_CTRL_TRANCOUNT_6 ((u16)0x0040) + + +#endif +#endif //__MM32_REG_DEFINE_V1_H + diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_adc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_adc.h new file mode 100644 index 000000000..1aab3ef16 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_adc.h @@ -0,0 +1,953 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file reg_adc.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF +/// MM32 FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion + +#ifndef __REG_ADC_H +#define __REG_ADC_H + +// Files includes + +#include +#include +#include "types.h" + + + + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + + + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ADC Base Address Definition +//////////////////////////////////////////////////////////////////////////////// +#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) ///< Base Address: 0x40012400 +#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) ///< Base Address: 0x40012800 +#define ADC3_BASE (APB2PERIPH_BASE + 0x4C00) ///< Base Address: 0x40014C00 + + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Analog-to-Digital Converter register +//////////////////////////////////////////////////////////////////////////////// +#define USENCOMBINEREGISTER +#ifdef USENCOMBINEREGISTER + +typedef struct { + union { + __IO u32 DR; ///< ADC data register, offset: 0x00 + __IO u32 ADDATA; + }; + union { + __IO u32 CFGR; ///< ADC configuration register, offset: 0x04 + __IO u32 ADCFG; + }; + union { + __IO u32 CR; ///< ADC control register, offset: 0x08 + __IO u32 ADCR; + }; + union { + __IO u32 CHSR; ///< ADC channel selection register, offset: 0x0C + __IO u32 ADCHS; + }; + union { + __IO u32 CMPR; ///< ADC window compare register, offset: 0x10 + __IO u32 ADCMPR; + }; + union { + __IO u32 SR; ///< ADC status register, offset: 0x14 + __IO u32 ADSTA; + }; + union { + __IO u32 CH0DR; ///< ADC channel0 data register, offset: 0x18 + __IO u32 ADDR0; + }; + union { + __IO u32 CH1DR; ///< ADC channel1 data register, offset: 0x1C + __IO u32 ADDR1; + }; + union { + __IO u32 CH2DR; ///< ADC channel2 data register, offset: 0x20 + __IO u32 ADDR2; + }; + union { + __IO u32 CH3DR; ///< ADC channel3 data register, offset: 0x24 + __IO u32 ADDR3; + }; + union { + __IO u32 CH4DR; ///< ADC channel4 data register, offset: 0x28 + __IO u32 ADDR4; + }; + union { + __IO u32 CH5DR; ///< ADC channel5 data register, offset: 0x2C + __IO u32 ADDR5; + }; + union { + __IO u32 CH6DR; ///< ADC channel6 data register, offset: 0x30 + __IO u32 ADDR6; + }; + union { + __IO u32 CH7DR; ///< ADC channel7 data register, offset: 0x34 + __IO u32 ADDR7; + }; + union { + __IO u32 CH8DR; ///< ADC channel8 data register, offset: 0x38 + __IO u32 ADDR8; + }; + union { + __IO u32 CH9DR; ///< ADC channel9 data register, offset: 0x3C + __IO u32 ADDR9; + }; + __IO u32 ADDR10; ///< offset: 0x40 + __IO u32 ADDR11; ///< offset: 0x44 + __IO u32 ADDR12; ///< offset: 0x48 + __IO u32 ADDR13; ///< offset: 0x4C + union { + __IO u32 CH14DR; ///< ADC channel14 data register, offset: 0x50 + __IO u32 ADDR14; + }; + union { + __IO u32 CH15DR; ///< ADC channel15 data register, offset: 0x54 + __IO u32 ADDR15; + }; + __IO u32 SREXT; ///< ADC Extended Status Register, offset: 0x58 + __IO u32 CHANY0; ///< ADC any Chan Select Register 0, offset: 0x5C + __IO u32 CHANY1; ///< ADC any Chan Select Register 1, offset: 0x60 + __IO u32 ANYCFG; ///< ADC any Chan config Register, offset: 0x64 + __IO u32 ANYCR; ///< ADC any Chan control Register, offset: 0x68 + __IO u32 RESERVED0; ///< offset 0x6C + __IO u32 SMPR1; ///< Sampling configuration register 1 offset 0x70 + __IO u32 SMPR2; ///< Sampling configuration register 2 offset 0x74 + __IO u32 RESERVED1; ///< offset 0x78 + __IO u32 JOFR0; ///< Injection channel data compensation register 0 offset 0x7C + __IO u32 JOFR1; ///< Injection channel data compensation register 1 offset 0x80 + __IO u32 JOFR2; ///< Injection channel data compensation register 2 offset 0x84 + __IO u32 JOFR3; ///< Injection channel data compensation register 3 offset 0x88 + __IO u32 JSQR; ///< Injection sequence register offset 0x8C + __IO u32 JDATA; ///< Inject data register offset 0x90 + __IO u32 RESERVED2; ///< offset 0x94 + __IO u32 RESERVED3; ///< offset 0x98 + __IO u32 RESERVED4; ///< offset 0x9C + __IO u32 RESERVED5; ///< offset 0xA0 + __IO u32 RESERVED6; ///< offset 0xA4 + __IO u32 RESERVED7; ///< offset 0xA8 + __IO u32 RESERVED8; ///< offset 0xAC + __IO u32 JDR0; ///< Injection channel data register 0 offset 0xB0 + __IO u32 JDR1; ///< Injection channel data register 1 offset 0xB4 + __IO u32 JDR2; ///< Injection channel data register 2 offset 0xB8 + __IO u32 JDR3; ///< Injection channel data register 3 offset 0xBC +} ADC_TypeDef; + +#endif +#ifdef USENNEWREGISTER +//////////////////////////////////////////////////////////////////////////////// +/// @brief Analog-to-Digital Converter register +//////////////////////////////////////////////////////////////////////////////// +typedef struct { + __IO u32 DR; ///< ADC data register, offset: 0x00 + __IO u32 CFGR; ///< ADC configuration register, offset: 0x04 + __IO u32 CR; ///< ADC control register, offset: 0x08 + __IO u32 CHSR; ///< ADC channel selection register, offset: 0x0C + __IO u32 CMPR; ///< ADC window compare register, offset: 0x10 + __IO u32 SR; ///< ADC status register, offset: 0x14 + __IO u32 CH0DR; ///< ADC channel0 data register, offset: 0x18 + __IO u32 CH1DR; ///< ADC channel1 data register, offset: 0x1C + __IO u32 CH2DR; ///< ADC channel2 data register, offset: 0x20 + __IO u32 CH3DR; ///< ADC channel3 data register, offset: 0x24 + __IO u32 CH4DR; ///< ADC channel4 data register, offset: 0x28 + __IO u32 CH5DR; ///< ADC channel5 data register, offset: 0x2C + __IO u32 CH6DR; ///< ADC channel6 data register, offset: 0x30 + __IO u32 CH7DR; ///< ADC channel7 data register, offset: 0x34 + __IO u32 CH8DR; ///< ADC channel8 data register, offset: 0x38 +} ADC_TypeDef; +#endif +#ifdef USENOLDREGISTER +typedef struct { + __IO u32 ADDATA; ///< ADC data register, offset: 0x00 + __IO u32 ADCFG; ///< ADC configuration register, offset: 0x04 + __IO u32 ADCR; ///< ADC control register, offset: 0x08 + __IO u32 ADCHS; ///< ADC channel selection register, offset: 0x0C + __IO u32 ADCMPR; ///< ADC window compare register, offset: 0x10 + __IO u32 ADSTA; ///< ADC status register, offset: 0x14 + __IO u32 ADDR0; ///< ADC channel0 data register, offset: 0x18 + __IO u32 ADDR1; ///< ADC channel1 data register, offset: 0x1C + __IO u32 ADDR2; ///< ADC channel2 data register, offset: 0x20 + __IO u32 ADDR3; ///< ADC channel3 data register, offset: 0x24 + __IO u32 ADDR4; ///< ADC channel4 data register, offset: 0x28 + __IO u32 ADDR5; ///< ADC channel5 data register, offset: 0x2C + __IO u32 ADDR6; ///< ADC channel6 data register, offset: 0x30 + __IO u32 ADDR7; ///< ADC channel7 data register, offset: 0x34 + __IO u32 ADDR8; ///< ADC channel8 data register, offset: 0x38 +} ADC_TypeDef; +#endif + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ADC type pointer Definition +//////////////////////////////////////////////////////////////////////////////// +#define ADC1 ((ADC_TypeDef*) ADC1_BASE) +#define ADC2 ((ADC_TypeDef*) ADC2_BASE) +#define ADC3 ((ADC_TypeDef*) ADC3_BASE) + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ADC_DR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define ADC_DR_DATA_Pos (0) +#define ADC_DR_DATA (0xFFFFU << ADC_DR_DATA_Pos) ///< ADC 12bit convert data + +#define ADC_DR_CH_Pos (16) +#define ADC_DR_CH (0x0FU << ADC_DR_CH_Pos) ///< CHANNELSEL[19:16] (ADC current channel convert data) + +#define ADC_DR_CH0 (0x00U << ADC_DR_CH_Pos) ///< ADC Channel select 0 +#define ADC_DR_CH1 (0x01U << ADC_DR_CH_Pos) ///< ADC Channel select 1 +#define ADC_DR_CH2 (0x02U << ADC_DR_CH_Pos) ///< ADC Channel select 2 +#define ADC_DR_CH3 (0x03U << ADC_DR_CH_Pos) ///< ADC Channel select 3 +#define ADC_DR_CH4 (0x04U << ADC_DR_CH_Pos) ///< ADC Channel select 4 +#define ADC_DR_CH5 (0x05U << ADC_DR_CH_Pos) ///< ADC Channel select 5 +#define ADC_DR_CH6 (0x06U << ADC_DR_CH_Pos) ///< ADC Channel select 6 +#define ADC_DR_CH7 (0x07U << ADC_DR_CH_Pos) ///< ADC Channel select 7 + +#define ADC_DR_CH8 (0x08U << ADC_DR_CH_Pos) ///< ADC Channel select 8 + +#define ADC_DR_CH10 (0x0AU << ADC_DR_CH_Pos) ///< ADC Channel select 10 +#define ADC_DR_CH11 (0x0BU << ADC_DR_CH_Pos) ///< ADC Channel select 11 +#define ADC_DR_CH13 (0x0CU << ADC_DR_CH_Pos) ///< ADC Channel select 13 + +#define ADC_DR_CH9 (0x09U << ADC_DR_CH_Pos) ///< ADC Channel select 9 +#define ADC_DR_CH14 (0x0EU << ADC_DR_CH_Pos) ///< ADC Channel select 14 +#define ADC_DR_CH15 (0x0FU << ADC_DR_CH_Pos) ///< ADC Channel select 15 +#define ADC_DR_OVERRUN_Pos (20) +#define ADC_DR_OVERRUN (0x01U << ADC_DR_OVERRUN_Pos) ///< ADC data will be cover +#define ADC_DR_VALID_Pos (21) +#define ADC_DR_VALID (0x01U << ADC_DR_VALID_Pos) ///< ADC data[11:0] is valid + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ADC_CFGR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define ADC_CFGR_ADEN_Pos (0) +#define ADC_CFGR_ADEN (0x01U << ADC_CFGR_ADEN_Pos) ///< Enable ADC convert +#define ADC_CFGR_ADWEN_Pos (1) +#define ADC_CFGR_ADWEN (0x01U << ADC_CFGR_ADWEN_Pos) ///< Enable ADC window compare + + +#define ADC_CFGR_RSLTCTL_Pos (7) +#define ADC_CFGR_RSLTCTL (0x07U << ADC_CFGR_RSLTCTL_Pos) ///< ADC resolution select +#define ADC_CFGR_RSLTCTL_12 (0x00U << ADC_CFGR_RSLTCTL_Pos) ///< ADC resolution select 12bit +#define ADC_CFGR_RSLTCTL_11 (0x01U << ADC_CFGR_RSLTCTL_Pos) ///< ADC resolution select 11bit +#define ADC_CFGR_RSLTCTL_10 (0x02U << ADC_CFGR_RSLTCTL_Pos) ///< ADC resolution select 10bit +#define ADC_CFGR_RSLTCTL_9 (0x03U << ADC_CFGR_RSLTCTL_Pos) ///< ADC resolution select 9bit +#define ADC_CFGR_RSLTCTL_8 (0x04U << ADC_CFGR_RSLTCTL_Pos) ///< ADC resolution select 8bit + +#define ADC_CFGR_TEN_Pos (2) +#define ADC_CFGR_TEN (0x01U << ADC_CFGR_TEN_Pos) ///< Enable ADC temperature sensor +#define ADC_CFGR_VEN_Pos (3) +#define ADC_CFGR_VEN (0x01U << ADC_CFGR_VEN_Pos) ///< Enable ADC voltage reference + + + + + +#define ADC_CFGR_PRE_Pos (4) +#define ADC_CFGR_PREL_Pos (14) +#define ADC_CFGR_PRE ((0x07U << ADC_CFGR_PRE_Pos) + (0x01U << ADC_CFGR_PREL_Pos)) +#define ADC_CFGR_PRE_2 (0x00U << ADC_CFGR_PRE_Pos) ///< ADC preclk 2 +#define ADC_CFGR_PRE_4 (0x01U << ADC_CFGR_PRE_Pos) ///< ADC preclk 4 +#define ADC_CFGR_PRE_6 (0x02U << ADC_CFGR_PRE_Pos) ///< ADC preclk 6 +#define ADC_CFGR_PRE_8 (0x03U << ADC_CFGR_PRE_Pos) ///< ADC preclk 8 +#define ADC_CFGR_PRE_10 (0x04U << ADC_CFGR_PRE_Pos) ///< ADC preclk 10 +#define ADC_CFGR_PRE_12 (0x05U << ADC_CFGR_PRE_Pos) ///< ADC preclk 12 +#define ADC_CFGR_PRE_14 (0x06U << ADC_CFGR_PRE_Pos) ///< ADC preclk 14 +#define ADC_CFGR_PRE_16 (0x07U << ADC_CFGR_PRE_Pos) ///< ADC preclk 16 +#define ADC_CFGR_PRE_3 ((0x01U << ADC_CFGR_PREL_Pos) + (0x00U << ADC_CFGR_PRE_Pos)) ///< ADC preclk 3 +#define ADC_CFGR_PRE_5 ((0x01U << ADC_CFGR_PREL_Pos) + (0x01U << ADC_CFGR_PRE_Pos)) ///< ADC preclk 5 +#define ADC_CFGR_PRE_7 ((0x01U << ADC_CFGR_PREL_Pos) + (0x02U << ADC_CFGR_PRE_Pos)) ///< ADC preclk 7 +#define ADC_CFGR_PRE_9 ((0x01U << ADC_CFGR_PREL_Pos) + (0x03U << ADC_CFGR_PRE_Pos)) ///< ADC preclk 9 +#define ADC_CFGR_PRE_11 ((0x01U << ADC_CFGR_PREL_Pos) + (0x04U << ADC_CFGR_PRE_Pos)) ///< ADC preclk 11 +#define ADC_CFGR_PRE_13 ((0x01U << ADC_CFGR_PREL_Pos) + (0x05U << ADC_CFGR_PRE_Pos)) ///< ADC preclk 13 +#define ADC_CFGR_PRE_15 ((0x01U << ADC_CFGR_PREL_Pos) + (0x06U << ADC_CFGR_PRE_Pos)) ///< ADC preclk 15 +#define ADC_CFGR_PRE_17 ((0x01U << ADC_CFGR_PREL_Pos) + (0x07U << ADC_CFGR_PRE_Pos)) ///< ADC preclk 17 + +#define ADC_CFGR_JADWEN_Pos (16) +#define ADC_CFGR_JADWEN (0x01U << ADC_CFGR_JADWEN_Pos) ///< Inject ADC conversion window comparison enable + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ADC_CR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define ADC_CR_ADIE_Pos (0) +#define ADC_CR_ADIE (0x01U << ADC_CR_ADIE_Pos) ///< ADC interrupt enable +#define ADC_CR_ADWIE_Pos (1) +#define ADC_CR_ADWIE (0x01U << ADC_CR_ADWIE_Pos) ///< ADC window compare interrupt enable +#define ADC_CR_TRGEN_Pos (2) +#define ADC_CR_TRGEN (0x01U << ADC_CR_TRGEN_Pos) ///< extranal trigger single start AD convert +#define ADC_CR_DMAEN_Pos (3) +#define ADC_CR_DMAEN (0x01U << ADC_CR_DMAEN_Pos) ///< ADC DMA enable + +#define ADC_CR_ADST_Pos (8) +#define ADC_CR_ADST (0x01U << ADC_CR_ADST_Pos) ///< ADC start convert data +#define ADC_CR_MODE_Pos (9) +#define ADC_CR_MODE (0x03U << ADC_CR_MODE_Pos) ///< ADC convert mode +#define ADC_CR_IMM (0x00U << ADC_CR_MODE_Pos) ///< ADC imm convert mode +#define ADC_CR_SCAN (0x01U << ADC_CR_MODE_Pos) ///< ADC scan convert mode +#define ADC_CR_CONTINUE (0x02U << ADC_CR_MODE_Pos) ///< ADC continue scan convert mode +#define ADC_CR_ALIGN_Pos (11) +#define ADC_CR_ALIGN (0x01U << ADC_CR_ALIGN_Pos) ///< ADC data align +#define ADC_CR_LEFT (0x01U << ADC_CR_ALIGN_Pos) ///< ADC data left align +#define ADC_CR_RIGHT (0x00U << ADC_CR_ALIGN_Pos) ///< ADC data right align +#define ADC_CR_CMPCH_Pos (12) +#define ADC_CR_CMPCH (0x0FU << ADC_CR_CMPCH_Pos) ///< CMPCH[15:12] ADC window compare channel0 convert data +#define ADC_CR_CMPCH_0 (0x00U << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 0 Conversion Results +#define ADC_CR_CMPCH_1 (0x01U << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 1 Conversion Results +#define ADC_CR_CMPCH_2 (0x02U << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 2 Conversion Results +#define ADC_CR_CMPCH_4 (0x04U << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 4 Conversion Results +#define ADC_CR_CMPCH_5 (0x05U << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 5 Conversion Results +#define ADC_CR_CMPCH_6 (0x06U << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 6 Conversion Results +#define ADC_CR_CMPCH_7 (0x07U << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 7 Conversion Results +#define ADC_CR_CMPCH_8 (0x08U << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 8 Conversion Results +#define ADC_CR_CMPCH_9 (0x09U << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 9 Conversion Results +#define ADC_CR_CMPCH_10 (0x0AU << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 10 Conversion Results +#define ADC_CR_CMPCH_11 (0x0BU << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 11 Conversion Results +#define ADC_CR_CMPCH_13 (0x0DU << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 13 Conversion Results +#define ADC_CR_CMPCH_14 (0x0EU << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 14 Conversion Results +#define ADC_CR_CMPCH_ALL (0x0FU << ADC_CR_CMPCH_Pos) ///< Select Compare ALL Channel Conversion Results + + + +#define ADC_CR_SCANDIR_Pos (16) +#define ADC_CR_SCANDIR (0x01U << ADC_CR_SCANDIR_Pos) ///< ADC scan direction +#define ADC_CR_TRGSEL_H_Pos (17) +#define ADC_CR_TRGSEL_L_Pos (4) +#define ADC_CR_TRGSEL ((0x03U << ADC_CR_TRGSEL_H_Pos) + (0x07U << ADC_CR_TRGSEL_L_Pos)) ///< TRGSEL[6:4][18:17] ADC external trigger source select +#define ADC_CR_T1_CC1 (0x00U << ADC_CR_TRGSEL_L_Pos) ///< The external trigger source of the ADC is T1_CC1 +#define ADC_CR_T1_CC2 (0x01U << ADC_CR_TRGSEL_L_Pos) ///< The external trigger source of the ADC is T1_CC2 +#define ADC_CR_T1_CC3 (0x02U << ADC_CR_TRGSEL_L_Pos) ///< The external trigger source of the ADC is T1_CC3 +#define ADC_CR_T2_CC2 (0x03U << ADC_CR_TRGSEL_L_Pos) ///< The external trigger source of the ADC is T2_CC2 +#define ADC_CR_T3_TRIG (0x04U << ADC_CR_TRGSEL_L_Pos) ///< The external trigger source of the ADC is T3_TRIG +#define ADC_CR_T1_CC4_CC5 (0x05U << ADC_CR_TRGSEL_L_Pos) ///< The external trigger source of the ADC is T1_CC4_CC5 +#define ADC_CR_T3_CC1 (0x06U << ADC_CR_TRGSEL_L_Pos) ///< The external trigger source of the ADC is T3_CC1 +#define ADC_CR_EXTI_11 (0x07U << ADC_CR_TRGSEL_L_Pos) ///< The external trigger source of the ADC is EXTI_11 +#define ADC_CR_T1_TRIG ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x00U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is T1_TRIG +#define ADC_CR_T8_CC4 ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x01U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is T8_CC4 +#define ADC_CR_T8_CC4_CC5 ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x02U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is T8_CC4_CC5 +#define ADC_CR_T2_CC1 ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x03U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is T2_CC1 +#define ADC_CR_T3_CC4 ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x04U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is T3_CC4 +#define ADC_CR_T2_TRIG ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x05U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is T2_TRIG +#define ADC_CR_T8_CC5 ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x06U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is T8_CC5 +#define ADC_CR_EXTI_15 ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x07U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is EXTI_15 +#define ADC_CR_TIM1_CC4 ((0x02U << ADC_CR_TRGSEL_H_Pos) + (0x00U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is TIM1_CC4 +#define ADC_CR_TIM1_CC5 ((0x02U << ADC_CR_TRGSEL_H_Pos) + (0x01U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is TIM1_CC5 + +#define ADC_CR_TRGSHIFT_Pos (19) +#define ADC_CR_TRGSHIFT (0x07U << ADC_CR_TRGSHIFT_Pos) ///< External trigger shift sample +#define ADC_CR_TRGSHIFT_0 (0x00U << ADC_CR_TRGSHIFT_Pos) ///< No shift +#define ADC_CR_TRGSHIFT_4 (0x01U << ADC_CR_TRGSHIFT_Pos) ///< Shift 4 period +#define ADC_CR_TRGSHIFT_16 (0x02U << ADC_CR_TRGSHIFT_Pos) ///< Shift 16 period +#define ADC_CR_TRGSHIFT_32 (0x03U << ADC_CR_TRGSHIFT_Pos) ///< Shift 32 period +#define ADC_CR_TRGSHIFT_64 (0x04U << ADC_CR_TRGSHIFT_Pos) ///< Shift 64 period +#define ADC_CR_TRGSHIFT_128 (0x05U << ADC_CR_TRGSHIFT_Pos) ///< Shift 128 period +#define ADC_CR_TRGSHIFT_256 (0x06U << ADC_CR_TRGSHIFT_Pos) ///< Shift 256 period +#define ADC_CR_TRGSHIFT_512 (0x07U << ADC_CR_TRGSHIFT_Pos) ///< Shift 512 period +#define ADC_CR_CALIBEN_Pos (22) +#define ADC_CR_CALIBEN (0x01U << ADC_CR_CALIBEN_Pos) ///< Self-calibration enable +#define ADC_CR_CALIBSEL_Pos (23) +#define ADC_CR_CALIBSEL (0x01U << ADC_CR_CALIBSEL_Pos) ///< Self-calibration voltage selection +#define ADC_CR_TRG_EDGE_Pos (24) +#define ADC_CR_TRG_EDGE (0x03U << ADC_CR_TRG_EDGE_Pos) ///< ADC trig edge config +#define ADC_CR_TRG_EDGE_DUAL (0x00U << ADC_CR_TRG_EDGE_Pos) ///< ADC dual edge trig mode +#define ADC_CR_TRG_EDGE_DOWN (0x01U << ADC_CR_TRG_EDGE_Pos) ///< ADC down edge trig mode +#define ADC_CR_TRG_EDGE_UP (0x02U << ADC_CR_TRG_EDGE_Pos) ///< ADC up edge trig mode +#define ADC_CR_TRG_EDGE_MASK (0x03U << ADC_CR_TRG_EDGE_Pos) ///< ADC mask edge trig mode + +#define ADC_CR_EOSMPIE_Pos (26) +#define ADC_CR_EOSMPIE (0X01U << ADC_CR_EOSMPIE_Pos) ///< ADC end sampling flag interrupt enable +#define ADC_CR_EOCIE_Pos (27) +#define ADC_CR_EOCIE (0X01U << ADC_CR_EOCIE_Pos) ///< ADC end of conversion interrupt enable +//////////////////////////////////////////////////////////////////////////////// +/// @brief ADC_CHSR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define ADC_CHSR_CH0_Pos (0) +#define ADC_CHSR_CH0 (0x01U << ADC_CHSR_CH0_Pos) ///< Enable ADC channel 0 +#define ADC_CHSR_CH1_Pos (1) +#define ADC_CHSR_CH1 (0x01U << ADC_CHSR_CH1_Pos) ///< Enable ADC channel 1 +#define ADC_CHSR_CH2_Pos (2) +#define ADC_CHSR_CH2 (0x01U << ADC_CHSR_CH2_Pos) ///< Enable ADC channel 2 +#define ADC_CHSR_CH3_Pos (3) +#define ADC_CHSR_CH3 (0x01U << ADC_CHSR_CH3_Pos) ///< Enable ADC channel 3 +#define ADC_CHSR_CH4_Pos (4) +#define ADC_CHSR_CH4 (0x01U << ADC_CHSR_CH4_Pos) ///< Enable ADC channel 4 +#define ADC_CHSR_CH5_Pos (5) +#define ADC_CHSR_CH5 (0x01U << ADC_CHSR_CH5_Pos) ///< Enable ADC channel 5 +#define ADC_CHSR_CH6_Pos (6) +#define ADC_CHSR_CH6 (0x01U << ADC_CHSR_CH6_Pos) ///< Enable ADC channel 6 +#define ADC_CHSR_CH7_Pos (7) +#define ADC_CHSR_CH7 (0x01U << ADC_CHSR_CH7_Pos) ///< Enable ADC channel 7 + +#define ADC_CHSR_CH8_Pos (8) +#define ADC_CHSR_CH8 (0x01U << ADC_CHSR_CH8_Pos) ///< Enable ADC channel 8 +#define ADC_CHSR_CH9_Pos (9) +#define ADC_CHSR_CH9 (0x01U << ADC_CHSR_CH9_Pos) ///< Enable ADC channel 9 +#define ADC_CHSR_CHT_Pos (14) +#define ADC_CHSR_CHT (0x01U << ADC_CHSR_CHT_Pos) ///< Enable Temperature Sensor +#define ADC_CHSR_CHV_Pos (15) +#define ADC_CHSR_CHV (0x01U << ADC_CHSR_CHV_Pos) ///< Enable Voltage Sensor + + +#define ADC_CHSR_CH10_Pos (10) +#define ADC_CHSR_CH10 (0x01U << ADC_CHSR_CH10_Pos) ///< Enable ADC channel 10 +#define ADC_CHSR_CH11_Pos (11) +#define ADC_CHSR_CH11 (0x01U << ADC_CHSR_CH11_Pos) ///< Enable ADC channel 11 +#define ADC_CHSR_CH12_Pos (12) +#define ADC_CHSR_CH12 (0x01U << ADC_CHSR_CH12_Pos) ///< Enable ADC channel 12 +#define ADC_CHSR_CH13_Pos (13) +#define ADC_CHSR_CH13 (0x01U << ADC_CHSR_CH13_Pos) ///< Enable ADC channel 13 +//////////////////////////////////////////////////////////////////////////////// +/// @brief ADC_CMPR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define ADC_CMPR_CMPLDATA_Pos (0) +#define ADC_CMPR_CMPLDATA (0x0FFFU << ADC_CMPR_CMPLDATA_Pos) ///< ADC 12bit window compare DOWN LEVEL DATA +#define ADC_CMPR_CMPHDATA_Pos (16) +#define ADC_CMPR_CMPHDATA (0x0FFFU << ADC_CMPR_CMPHDATA_Pos) ///< ADC 12bit window compare UP LEVEL DATA + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ADC_SR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define ADC_SR_ADIF_Pos (0) +#define ADC_SR_ADIF (0x01U << ADC_SR_ADIF_Pos) ///< ADC convert complete flag +#define ADC_SR_ADWIF_Pos (1) +#define ADC_SR_ADWIF (0x01U << ADC_SR_ADWIF_Pos) ///< ADC compare flag +#define ADC_SR_BUSY_Pos (2) +#define ADC_SR_BUSY (0x01U << ADC_SR_BUSY_Pos) ///< ADC busy flag +#define ADC_SR_CH_Pos (4) +#define ADC_SR_CH (0x0FU << ADC_SR_CH_Pos) ///< CHANNEL[7:4] ADC current channel +#define ADC_SR_CH0 (0x00U << ADC_SR_CH_Pos) ///< Channel 0 is the current conversion channel +#define ADC_SR_CH1 (0x01U << ADC_SR_CH_Pos) ///< Channel 1 is the current conversion channel +#define ADC_SR_CH2 (0x02U << ADC_SR_CH_Pos) ///< Channel 2 is the current conversion channel +#define ADC_SR_CH3 (0x03U << ADC_SR_CH_Pos) ///< Channel 3 is the current conversion channel +#define ADC_SR_CH4 (0x04U << ADC_SR_CH_Pos) ///< Channel 4 is the current conversion channel +#define ADC_SR_CH5 (0x05U << ADC_SR_CH_Pos) ///< Channel 5 is the current conversion channel +#define ADC_SR_CH6 (0x06U << ADC_SR_CH_Pos) ///< Channel 6 is the current conversion channel +#define ADC_SR_CH7 (0x07U << ADC_SR_CH_Pos) ///< Channel 7 is the current conversion channel +#define ADC_SR_CH8 (0x08U << ADC_SR_CH_Pos) ///< Channel 8 is the current conversion channel +#define ADC_SR_CH9 (0x09U << ADC_SR_CH_Pos) ///< Channel 9 is the current conversion channel +#define ADC_SR_CH10 (0x0AU << ADC_SR_CH_Pos) ///< Channel 10 is the current conversion channel +#define ADC_SR_CH11 (0x0BU << ADC_SR_CH_Pos) ///< Channel 11 is the current conversion channel +#define ADC_SR_CH13 (0x0DU << ADC_SR_CH_Pos) ///< Channel 13 is the current conversion channel +#define ADC_SR_CH14 (0x0EU << ADC_SR_CH_Pos) ///< Channel 14 is the current conversion channel +#define ADC_SR_CH15 (0x0FU << ADC_SR_CH_Pos) ///< Channel 15 is the current conversion channel + + +#define ADC_SR_VALID_Pos (8) +#define ADC_SR_VALID (0x0FFFU << ADC_SR_VALID_Pos) ///< VALID[19:8] ADC channel 0..11 valid flag +#define ADC_SR_OVERRUN_Pos (20) +#define ADC_SR_OVERRUN (0x0FFFU << ADC_SR_OVERRUN_Pos) ///< OVERRUN[31:20] ADC channel 0..11 data covered flag + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ADC_CHnDR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define ADC_CHDR_DATA_Pos (0) +#define ADC_CHDR_DATA (0xFFFFU << ADC_CHDR_DATA_Pos) ///< ADC channel convert data +#define ADC_CHDR_OVERRUN_Pos (20) +#define ADC_CHDR_OVERRUN (0x01U << ADC_CHDR_OVERRUN_Pos) ///< ADC data covered flag +#define ADC_CHDR_VALID_Pos (21) +#define ADC_CHDR_VALID (0x01U << ADC_CHDR_VALID_Pos) ///< ADC data valid flag + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ADC_SREXT Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define ADC_SREXT_VALID_Pos (0) +#define ADC_SREXT_VALID (0x0FU << ADC_SREXT_VALID_Pos) ///< VALID[3:0] ADC channel 12,14..15 valid flag +#define ADC_SREXT_OVERRUN_Pos (4) +#define ADC_SREXT_OVERRUN (0x0FU << ADC_SREXT_OVERRUN_Pos) ///< OVERRUN[7:4] ADC channel 12,14..15 data covered flag + + +#define ADC_SREXT_EOSMPIF_Pos (16) +#define ADC_SREXT_EOSMPIF (0x01U << ADC_SREXT_EOSMPIF_Pos) ///< End of sampling interrupt flag +#define ADC_SREXT_EOCIF_Pos (17) +#define ADC_SREXT_EOCIF (0x01U << ADC_SREXT_EOCIF_Pos) ///< End of conversion interrupt flag +#define ADC_SREXT_JEOSMPIF_Pos (18) +#define ADC_SREXT_JEOSMPIF (0x01U << ADC_SREXT_JEOSMPIF_Pos) /// Injected channel end of sampling interrupt flag +#define ADC_SREXT_JEOCIF_Pos (19) +#define ADC_SREXT_JEOCIF (0x03U << ADC_SREXT_JEOCIF_Pos) ///< Injected channel end of conversion interrupt flag +#define ADC_SREXT_JEOSIF_Pos (20) +#define ADC_SREXT_JEOSIF (0x03U << ADC_SREXT_JEOSIF_Pos) ///< Injected channel end of sequential conversion interrupt flag +#define ADC_SREXT_JBUSY_Pos (21) +#define ADC_SREXT_JBUSY (0x01U << ADC_SREXT_JBUSY_Pos) ///< Injection mode busy/idle + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ADC_CHANY0 select Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define ADC1_CHANY0_SEL0_Pos (0) ///< CHANY_SEL0 (Bit 0) +#define ADC1_CHANY0_SEL0 (0x0FU << ADC1_CHANY0_SEL0_Pos) ///< CHANY_SEL0 (Bitfield-Mask: 0x0f) +#define ADC1_CHANY0_SEL1_Pos (4) ///< CHANY_SEL1 (Bit 4) +#define ADC1_CHANY0_SEL1 (0x0FU << ADC1_CHANY0_SEL1_Pos) ///< CHANY_SEL1 (Bitfield-Mask: 0x0f) +#define ADC1_CHANY0_SEL2_Pos (8) ///< CHANY_SEL2 (Bit 8) +#define ADC1_CHANY0_SEL2 (0x0FU << ADC1_CHANY0_SEL2_Pos) ///< CHANY_SEL2 (Bitfield-Mask: 0x0f) +#define ADC1_CHANY0_SEL3_Pos (12) ///< CHANY_SEL3 (Bit 12) +#define ADC1_CHANY0_SEL3 (0x0FU << ADC1_CHANY0_SEL3_Pos) ///< CHANY_SEL3 (Bitfield-Mask: 0x0f) +#define ADC1_CHANY0_SEL4_Pos (16) ///< CHANY_SEL4 (Bit 16) +#define ADC1_CHANY0_SEL4 (0x0FU << ADC1_CHANY0_SEL4_Pos) ///< CHANY_SEL4 (Bitfield-Mask: 0x0f) +#define ADC1_CHANY0_SEL5_Pos (20) ///< CHANY_SEL5 (Bit 20) +#define ADC1_CHANY0_SEL5 (0x0FU << ADC1_CHANY0_SEL5_Pos) ///< CHANY_SEL5 (Bitfield-Mask: 0x0f) +#define ADC1_CHANY0_SEL6_Pos (24) ///< CHANY_SEL6 (Bit 24) +#define ADC1_CHANY0_SEL6 (0x0FU << ADC1_CHANY0_SEL6_Pos) ///< CHANY_SEL6 (Bitfield-Mask: 0x0f) +#define ADC1_CHANY0_SEL7_Pos (28) ///< CHANY_SEL7 (Bit 28) +#define ADC1_CHANY0_SEL7 (0x0FU << ADC1_CHANY0_SEL7_Pos) ///< CHANY_SEL7 (Bitfield-Mask: 0x0f) + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ADC_CHANY1 select Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define ADC1_CHANY1_SEL8_Pos (0) ///< CHANY_SEL8 (Bit 0) +#define ADC1_CHANY1_SEL8 (0x0FU << ADC1_CHANY1_SEL8_Pos) ///< CHANY_SEL8 (Bitfield-Mask: 0x0f) +#define ADC1_CHANY1_SEL9_Pos (4) ///< CHANY_SEL9 (Bit 4) +#define ADC1_CHANY1_SEL9 (0x0FU << ADC1_CHANY1_SEL9_Pos) ///< CHANY_SEL9 (Bitfield-Mask: 0x0f) + +#define ADC1_CHANY1_SEL14_Pos (24) ///< CHANY_SEL14 (Bit 24) +#define ADC1_CHANY1_SEL14 (0x0FU << ADC1_CHANY1_SEL14_Pos) ///< CHANY_SEL14 (Bitfield-Mask: 0x0f) +#define ADC1_CHANY1_SEL15_Pos (28) ///< CHANY_SEL15 (Bit 28) +#define ADC1_CHANY1_SEL15 (0x0FU << ADC1_CHANY1_SEL15_Pos) ///< CHANY_SEL15 (Bitfield-Mask: 0x0f) +#define ADC1_CHANY1_SEL10_Pos (8) ///< CHANY_SEL10 (Bit 8) +#define ADC1_CHANY1_SEL10 (0x0FU << ADC1_CHANY1_SEL10_Pos) ///< CHANY_SEL10 (Bitfield-Mask: 0x0f) +#define ADC1_CHANY1_SEL11_Pos (12) ///< CHANY_SEL11 (Bit 12) +#define ADC1_CHANY1_SEL11 (0x0FU << ADC1_CHANY1_SEL11_Pos) ///< CHANY_SEL11 (Bitfield-Mask: 0x0f) +#define ADC1_CHANY1_SEL12_Pos (16) ///< CHANY_SEL12 (Bit 16) +#define ADC1_CHANY1_SEL12 (0x0FU << ADC1_CHANY1_SEL12_Pos) ///< CHANY_SEL12 (Bitfield-Mask: 0x0f) +#define ADC1_CHANY1_SEL13_Pos (20) ///< CHANY_SEL13 (Bit 20) +#define ADC1_CHANY1_SEL13 (0x0FU << ADC1_CHANY1_SEL13_Pos) ///< CHANY_SEL13 (Bitfield-Mask: 0x0f) +//////////////////////////////////////////////////////////////////////////////// +/// @brief ADC_CHANY config number Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define ADC1_CHANY_CFG_NUM_Max (16) ///< CHANY_CFG_NUM Max Value is 16 + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ADC_CHANY mode enable Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define ADC1_CHANY_CR_MDEN_Pos (0) ///< CHANY_MDEN (Bit 0) +#define ADC1_CHANY_CR_MDEN (0x01U << ADC1_CHANY_CR_MDEN_Pos) ///< CHANY_MDEN (Bitfield-Mask: 0x01) + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ADC_ANY_CR mode enable Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define ADC_ANY_CR_JTRGEDGE_Pos (16) ///< Injection mode triggers edge selection +#define ADC_ANY_CR_JTRGEDGE_R_F (0x00U << ADC_ANY_CR_JTRGEDGE_Pos) ///< Triggered along both rising and falling edges +#define ADC_ANY_CR_JTRGEDGE_F (0x01U << ADC_ANY_CR_JTRGEDGE_Pos) ///< Drop edge trigger +#define ADC_ANY_CR_JTRGEDGE_R (0x02U << ADC_ANY_CR_JTRGEDGE_Pos) ///< Rising edge trigger +#define ADC_ANY_CR_JTRGEDGE_S (0x03U << ADC_ANY_CR_JTRGEDGE_Pos) ///< Shield trigger + +#define ADC_ANY_CR_JTRGSHIFT_Pos (13) ///< Injection mode external trigger delay sampling +#define ADC_ANY_CR_JTRGSHIFT_0 (0x00U << ADC_ANY_CR_JTRGSHIFT_Pos) ///< 0 cycle +#define ADC_ANY_CR_JTRGSHIFT_4 (0x01U << ADC_ANY_CR_JTRGSHIFT_Pos) ///< 4 cycle +#define ADC_ANY_CR_JTRGSHIFT_16 (0x02U << ADC_ANY_CR_JTRGSHIFT_Pos) ///< 16 cycle +#define ADC_ANY_CR_JTRGSHIFT_32 (0x03U << ADC_ANY_CR_JTRGSHIFT_Pos) ///< 32 cycle +#define ADC_ANY_CR_JTRGSHIFT_64 (0x04U << ADC_ANY_CR_JTRGSHIFT_Pos) ///< 64 cycle +#define ADC_ANY_CR_JTRGSHIFT_128 (0x05U << ADC_ANY_CR_JTRGSHIFT_Pos) ///< 128 cycle +#define ADC_ANY_CR_JTRGSHIFT_256 (0x06U << ADC_ANY_CR_JTRGSHIFT_Pos) ///< 256 cycle +#define ADC_ANY_CR_JTRGSHIFT_512 (0x07U << ADC_ANY_CR_JTRGSHIFT_Pos) ///< 512 cycle + +#define ADC_ANY_CR_JTRGSEL_Pos (8) ///< External event select for injected group +#define ADC_ANY_CR_JTRGSEL (0x07U << ADC_ANY_CR_JTRGSEL_Pos) +#define ADC_ANY_CR_JTRGSEL_TIM1_TRGO (0x00U << ADC_ANY_CR_JTRGSEL_Pos) ///< TIM1 TRGO +#define ADC_ANY_CR_JTRGSEL_TIM1_CC4 (0x01U << ADC_ANY_CR_JTRGSEL_Pos) ///< TIM1 CC4 +#define ADC_ANY_CR_JTRGSEL_TIM1_CC4_CC5 (0x02U << ADC_ANY_CR_JTRGSEL_Pos) ///< TIM1 CC4 and CC5 +#define ADC_ANY_CR_JTRGSEL_TIM2_TIM4CC1 (0x03U << ADC_ANY_CR_JTRGSEL_Pos) ///< TIM2 CC1 and TIM4 CC1 +#define ADC_ANY_CR_JTRGSEL_TIM3_TIM5CC4 (0x04U << ADC_ANY_CR_JTRGSEL_Pos) ///< TIM3 CC4 and TIM5 CC4 +#define ADC_ANY_CR_JTRGSEL_TIM8_CC4 (0x05U << ADC_ANY_CR_JTRGSEL_Pos) ///< TIM8 CC4 +#define ADC_ANY_CR_JTRGSEL_TIM8_CC4_CC5 (0x06U << ADC_ANY_CR_JTRGSEL_Pos) ///< TIM8 CC4 and CC5 +#define ADC_ANY_CR_JTRGSEL_EXTI12 (0x07U << ADC_ANY_CR_JTRGSEL_Pos) ///< EXTI12 + +#define ADC_ANY_CR_JTRGEN_Pos (7) +#define ADC_ANY_CR_JTRGEN (0x01U << ADC_ANY_CR_JTRGEN_Pos) ///< External trigger conversion mode for injected channels +#define ADC_ANY_CR_JADST_Pos (6) +#define ADC_ANY_CR_JADST (0x01U << ADC_ANY_CR_JADST_Pos) ///< Start conversion of injected channels +#define ADC_ANY_CR_JAUTO_Pos (5) +#define ADC_ANY_CR_JAUTO (0x01U << ADC_ANY_CR_JAUTO_Pos) ///
© COPYRIGHT MINDMOTION
+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion + +#ifndef __REG_BKP_H +#define __REG_BKP_H + +// Files includes + +#include +#include +#include "types.h" + + + + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + + + + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief BKP Base Address Definition +//////////////////////////////////////////////////////////////////////////////// + + +#define BKP_BASE (APB1PERIPH_BASE + 0x2840) ///< Base Address: 0x40002840 + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief BKP Register Structure Definition +//////////////////////////////////////////////////////////////////////////////// + + + +#define BKP_NUMBER 20 + +typedef struct { + __IO u32 RTCCR; ///< RTC clock calibration register, offset: 0x00 + __IO u32 CR; ///< BKP control register, offset: 0x04 + __IO u32 CSR; ///< BKP control/status register, offset: 0x08 + __IO u32 RESERVED0; ///< Reserved, offset: 0x0C + __IO u32 DR1; ///< BKP data register 1, offset: 0x10 + __IO u32 DR2; ///< BKP data register 2, offset: 0x14 + __IO u32 DR3; ///< BKP data register 3, offset: 0x18 + __IO u32 DR4; ///< BKP data register 4, offset: 0x1C + __IO u32 DR5; ///< BKP data register 5, offset: 0x20 + __IO u32 DR6; ///< BKP data register 6, offset: 0x24 + __IO u32 DR7; ///< BKP data register 7, offset: 0x28 + __IO u32 DR8; ///< BKP data register 8, offset: 0x2C + __IO u32 DR9; ///< BKP data register 9, offset: 0x30 + __IO u32 DR10; ///< BKP data register 10 offset: 0x34 + __IO u32 DR11; ///< BKP data register 11, offset: 0x38 + __IO u32 DR12; ///< BKP data register 12, offset: 0x3C + __IO u32 DR13; ///< BKP data register 13, offset: 0x40 + __IO u32 DR14; ///< BKP data register 14, offset: 0x44 + __IO u32 DR15; ///< BKP data register 15, offset: 0x48 + __IO u32 DR16; ///< BKP data register 16, offset: 0x4C + __IO u32 DR17; ///< BKP data register 17, offset: 0x50 + __IO u32 DR18; ///< BKP data register 18, offset: 0x54 + __IO u32 DR19; ///< BKP data register 19, offset: 0x58 + __IO u32 DR20; ///< BKP data register 20, offset: 0x5C +} BKP_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief BKP type pointer Definition +//////////////////////////////////////////////////////////////////////////////// +#define BKP ((BKP_TypeDef*) BKP_BASE) + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief BKP_DRn Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define BKP_DR_DATA_Pos (0) +#define BKP_DR_DATA (0xFFFFU << BKP_DR_DATA) ///< Backup data + +//////////////////////////////////////////////////////////////////////////////// +/// @brief BKP_RTCCR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define BKP_RTCCR_CAL_Pos (0) +#define BKP_RTCCR_CAL (0x7FU << BKP_RTCCR_CAL_Pos) ///< Calibration value +#define BKP_RTCCR_CCO_Pos (7) +#define BKP_RTCCR_CCO (0x01U << BKP_RTCCR_CCO_Pos) ///< Calibration Clock Output +#define BKP_RTCCR_ASOE_Pos (8) +#define BKP_RTCCR_ASOE (0x01U << BKP_RTCCR_ASOE_Pos) ///< Alarm or Second Output Enable +#define BKP_RTCCR_ASOS_Pos (9) +#define BKP_RTCCR_ASOS (0x01U << BKP_RTCCR_ASOS_Pos) ///< Alarm or Second Output Selection + +//////////////////////////////////////////////////////////////////////////////// +/// @brief BKP_CR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define BKP_CR_TPE_Pos (0) +#define BKP_CR_TPE (0x01U << BKP_CR_TPE_Pos) ///< TAMPER pin enable +#define BKP_CR_TPAL_Pos (1) +#define BKP_CR_TPAL (0x01U << BKP_CR_TPAL_Pos) ///< TAMPER pin active level + +//////////////////////////////////////////////////////////////////////////////// +/// @brief BKP_CSR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define BKP_CSR_CTE_Pos (0) +#define BKP_CSR_CTE (0x01U << BKP_CSR_CTE_Pos) ///< Clear Tamper event +#define BKP_CSR_CTI_Pos (1) +#define BKP_CSR_CTI (0x01U << BKP_CSR_CTI_Pos) ///< Clear Tamper Interrupt +#define BKP_CSR_TPIE_Pos (2) +#define BKP_CSR_TPIE (0x01U << BKP_CSR_TPIE_Pos) ///< TAMPER Pin interrupt enable +#define BKP_CSR_TEF_Pos (8) +#define BKP_CSR_TEF (0x01U << BKP_CSR_TEF_Pos) ///< Tamper Event Flag +#define BKP_CSR_TIF_Pos (9) +#define BKP_CSR_TIF (0x01U << BKP_CSR_TIF_Pos) ///< Tamper Interrupt Flag + + + + + +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +#endif +//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_can.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_can.h new file mode 100644 index 000000000..5f66bb681 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_can.h @@ -0,0 +1,532 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file reg_can.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF +/// MM32 FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion + +#ifndef __REG_CAN_H +#define __REG_CAN_H + +// Files includes + +#include +#include +#include "types.h" + + + + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + + + + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief CAN Base Address Definition +//////////////////////////////////////////////////////////////////////////////// +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) ///< Base Address: 0x40006400 + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief CAN Register Structure Definition +//////////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////// +/// @brief CAN basic +//////////////////////////////////////////////////////////////////////////////// +typedef struct { + __IO u32 CR; ///< Control register, offset: 0x00 + __IO u32 CMR; ///< Command register, offset: 0x04 + __IO u32 SR; ///<
© COPYRIGHT MINDMOTION
+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion + +#ifndef __REG_COMMON_H +#define __REG_COMMON_H + +// Files includes +#include +#include +#include "types.h" + + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +#ifndef HSE_STARTUP_TIMEOUT +#define HSE_STARTUP_TIMEOUT (0x0500U) ///< Time out for HSE start up. +#endif +#ifdef CUSTOM_HSE_VAL +#ifndef HSE_VALUE +#define HSE_VALUE (12000000U) ///< Value of the External oscillator in Hz. +#endif +#else +#ifndef HSE_VALUE +#define HSE_VALUE (8000000U) ///< Value of the External oscillator in Hz. +#endif +#endif + + + +#define HSI_VALUE_PLL_ON (8000000U) ///< Value of the Internal oscillator in Hz. +#define HSI_DIV6 (8000000U) ///< Value of the Internal oscillator in Hz. +// Value of the Internal oscillator in Hz. + + +#define LSI_VALUE (40000U) ///< Value of the Internal oscillator in Hz. + + + + + +#ifndef HSI_VALUE + +#define HSI_VALUE (8000000U) ///< Value of the Internal oscillator in Hz. + +#endif + + + + + + + + +#define __MPU_PRESENT (0) ///< Cortex-M3 does not provide a MPU present or not +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS (4) ///< Cortex-M3 uses 4 Bits for the Priority Levels +//#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#define __Vendor_SysTickConfig (0) ///< Set to 1 if different SysTick Config is used + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief MM32 MCU Interrupt Handle +//////////////////////////////////////////////////////////////////////////////// +typedef enum IRQn { + NonMaskableInt_IRQn = -14, ///< 2 Non Maskable Interrupt + MemoryManagement_IRQn = -12, ///< 4 Cortex-M3 Memory Management Interrupt + BusFault_IRQn = -11, ///< 5 Cortex-M3 Bus Fault Interrupt + UsageFault_IRQn = -10, ///< 6 Cortex-M3 Usage Fault Interrupt + SVCall_IRQn = -5, ///< 11 Cortex-M3 SV Call Interrupt + DebugMonitor_IRQn = -4, ///< 12 Cortex-M3 Debug Monitor Interrupt + PendSV_IRQn = -2, ///< 14 Cortex-M3 Pend SV Interrupt + SysTick_IRQn = -1, ///< 15 Cortex-M3 System Tick Interrupt + + WWDG_IWDG_IRQn = 0, ///< Watchdog interrupt + WWDG_IRQn = 0, ///< Watchdog interrupt + PVD_IRQn = 1, ///< (PVD) Interrupt + TAMPER_IRQn = 2, ///< Intrusion detection interrupted + RTC_IRQn = 3, ///< Real-time clock (RTC) global interrupt + FLASH_IRQn = 4, ///< Flash global interrupt + RCC_CRS_IRQn = 5, ///< RCC and CRS global interrupt + EXTI0_IRQn = 6, ///< EXTI line 0 interrupt + EXTI1_IRQn = 7, ///< EXTI line 1 interrupt + EXTI2_IRQn = 8, ///< EXTI line 2 interrupt + EXTI3_IRQn = 9, ///< EXTI line 3 interrupted + EXTI4_IRQn = 10, ///< EXTI line 4 interrupt + DMA1_Channel1_IRQn = 11, ///< DMA1 channel 1 global interrupt + DMA1_Channel2_IRQn = 12, ///< DMA1 channel 2 global interrupt + DMA1_Channel3_IRQn = 13, ///< DMA1 channel 3 global interrupt + DMA1_Channel4_IRQn = 14, ///< DMA1 channel 4 global interrupt + DMA1_Channel5_IRQn = 15, ///< DMA1 channel 5 global interrupt + DMA1_Channel6_IRQn = 16, ///< DMA1 channel 6 global interrupt + DMA1_Channel7_IRQn = 17, ///< DMA1 channel 7 global interrupt + ADC1_IRQn = 18, ///< ADC1 global interrupt + ADC1_2_IRQn = 18, ///< ADC1&ADC2 global interrupt + ADC2_IRQn = 18, ///< ADC2 global interrupt + FlashCache_IRQn = 19, ///< FlashCache outage + CAN1_RX_IRQn = 21, ///< CAN1 receive interrupt + CAN_IRQn = 21, ///< CAN interrupt + EXTI9_5_IRQn = 23, ///< EXTI line [9: 5] interrupted + TIM1_BRK_IRQn = 24, ///< TIM1 disconnect interrupt + TIM1_UP_IRQn = 25, ///< TIM1 update interrupt + IM1_TRG_COM_IRQn = 26, ///< TIM1 trigger and communication interrupt + TIM1_CC_IRQn = 27, ///< TIM1 capture compare interrupt + TIM2_IRQn = 28, ///< TIM2 global interrupt + TIM3_IRQn = 29, ///< TIM3 global interrupt + TIM4_IRQn = 30, ///< TIM4 global interrupt + I2C1_IRQn = 31, ///< I2C1 global interrupt + I2C2_IRQn = 33, ///< I2C2 global interrupt + SPI1_IRQn = 35, ///< SPI1 global interrupt + SPI2_IRQn = 36, ///< SPI2 global interrupt + UART1_IRQn = 37, ///< UART1 global interrupt + UART2_IRQn = 38, ///< UART2 global interrupt + UART3_IRQn = 39, ///< UART3 global interrupt + EXTI15_10_IRQn = 40, ///< EXTI line [15: 10] interrupted + RTCAlarm_IRQn = 41, ///< RTC alarm connected to EXTI interrupted + USB_WKUP_IRQn = 42, ///< Wake-up interrupt from USB connected to EXTI + TIM8_BRK_IRQn = 43, ///< TIM8 brake interruption + TIM8_UP_IRQn = 44, ///< TIM8 update interrupt + TIM8_TRG_COM_IRQn = 45, ///< TIM8 trigger, communication interrupt + TIM8_CC_IRQn = 46, ///< TIM8 capture compare interrupt + ADC3_IRQn = 47, ///< ADC3 global interrupt + SDIO_IRQn = 49, ///< SDIO global interrupt + TIM5_IRQn = 50, ///< TIM5 global interrupt + SPI3_IRQn = 51, ///< SPI3 global interrupt + UART4_IRQn = 52, ///< UART4 global interrupt + UART5_IRQn = 53, ///< UART5 global interrupt + TIM6_IRQn = 54, ///< TIM6 global interrupt + TIM7_IRQn = 55, ///< TIM7 global interrupt + DMA2_Channel1_IRQn = 56, ///< DMA2 channel 1 global interrupt + DMA2_Channel2_IRQn = 57, ///< DMA2 channel 2 global interrupt + DMA2_Channel3_IRQn = 58, ///< DMA2 channel 3 global interrupt + DMA2_Channel4_IRQn = 59, ///< DMA2 channel 4 global interrupt + DMA2_Channel5_IRQn = 60, ///< DMA2 channel 5 global interrupt + ETHERNET_MAC_IRQn = 61, ///< ETHERNET global interrupt + COMP1_2_IRQn = 64, ///< Comparator 1/2 interrupt connected to EXTI + USB_FS_IRQn = 67, ///< USB FS global interrupt + UART6_IRQn = 71, ///< UART6 global interrupt + UART7_IRQn = 82, ///< UART7 global interrupt + UART8_IRQn = 83, ///< UART8 global interrupt +} IRQn_Type; + + + + +#include + + + +#define PERIPH_BASE (0x40000000U) ///< Peripheral base address in the alias region + +#define EEPROM_BASE (0x08100000U) ///< EEPROM base address in the alias region + + +#define SRAM_BITBAND_BASE (0x22000000U) ///< Peripheral base address in the bit-band region +#define PERIPH_BITBAND_BASE (0x42000000U) ///< SRAM base address in the bit-band region + +#define APB1PERIPH_BASE (PERIPH_BASE + 0x00000000) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000) +#define AHB3PERIPH_BASE (PERIPH_BASE + 0x20000000) + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief UID type pointer Definition +//////////////////////////////////////////////////////////////////////////////// +#define UID_BASE (0x1FFFF7E0U) ///< Unique device ID register base address + + + + + + + + +/////////////////////////////////////////////////////////////////////////////// +/// @brief Nested Vectored Interrupt Controller +/////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +/// @brief NVIC_ISER Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define NVIC_ISER_SETENA (0xFFFFFFFFU) ///< Interrupt set enable bits +#define NVIC_ISER_SETENA_0 (0x00000001U) ///< bit 0 +#define NVIC_ISER_SETENA_1 (0x00000002U) ///< bit 1 +#define NVIC_ISER_SETENA_2 (0x00000004U) ///< bit 2 +#define NVIC_ISER_SETENA_3 (0x00000008U) ///< bit 3 +#define NVIC_ISER_SETENA_4 (0x00000010U) ///< bit 4 +#define NVIC_ISER_SETENA_5 (0x00000020U) ///< bit 5 +#define NVIC_ISER_SETENA_6 (0x00000040U) ///< bit 6 +#define NVIC_ISER_SETENA_7 (0x00000080U) ///< bit 7 +#define NVIC_ISER_SETENA_8 (0x00000100U) ///< bit 8 +#define NVIC_ISER_SETENA_9 (0x00000200U) ///< bit 9 +#define NVIC_ISER_SETENA_10 (0x00000400U) ///< bit 10 +#define NVIC_ISER_SETENA_11 (0x00000800U) ///< bit 11 +#define NVIC_ISER_SETENA_12 (0x00001000U) ///< bit 12 +#define NVIC_ISER_SETENA_13 (0x00002000U) ///< bit 13 +#define NVIC_ISER_SETENA_14 (0x00004000U) ///< bit 14 +#define NVIC_ISER_SETENA_15 (0x00008000U) ///< bit 15 +#define NVIC_ISER_SETENA_16 (0x00010000U) ///< bit 16 +#define NVIC_ISER_SETENA_17 (0x00020000U) ///< bit 17 +#define NVIC_ISER_SETENA_18 (0x00040000U) ///< bit 18 +#define NVIC_ISER_SETENA_19 (0x00080000U) ///< bit 19 +#define NVIC_ISER_SETENA_20 (0x00100000U) ///< bit 20 +#define NVIC_ISER_SETENA_21 (0x00200000U) ///< bit 21 +#define NVIC_ISER_SETENA_22 (0x00400000U) ///< bit 22 +#define NVIC_ISER_SETENA_23 (0x00800000U) ///< bit 23 +#define NVIC_ISER_SETENA_24 (0x01000000U) ///< bit 24 +#define NVIC_ISER_SETENA_25 (0x02000000U) ///< bit 25 +#define NVIC_ISER_SETENA_26 (0x04000000U) ///< bit 26 +#define NVIC_ISER_SETENA_27 (0x08000000U) ///< bit 27 +#define NVIC_ISER_SETENA_28 (0x10000000U) ///< bit 28 +#define NVIC_ISER_SETENA_29 (0x20000000U) ///< bit 29 +#define NVIC_ISER_SETENA_30 (0x40000000U) ///< bit 30 +#define NVIC_ISER_SETENA_31 (0x80000000U) ///< bit 31 + +//////////////////////////////////////////////////////////////////////////////// +/// @brief NVIC_ICER Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define NVIC_ICER_CLRENA (0xFFFFFFFFU) ///< Interrupt clear-enable bits +#define NVIC_ICER_CLRENA_0 (0x00000001U) ///< bit 0 +#define NVIC_ICER_CLRENA_1 (0x00000002U) ///< bit 1 +#define NVIC_ICER_CLRENA_2 (0x00000004U) ///< bit 2 +#define NVIC_ICER_CLRENA_3 (0x00000008U) ///< bit 3 +#define NVIC_ICER_CLRENA_4 (0x00000010U) ///< bit 4 +#define NVIC_ICER_CLRENA_5 (0x00000020U) ///< bit 5 +#define NVIC_ICER_CLRENA_6 (0x00000040U) ///< bit 6 +#define NVIC_ICER_CLRENA_7 (0x00000080U) ///< bit 7 +#define NVIC_ICER_CLRENA_8 (0x00000100U) ///< bit 8 +#define NVIC_ICER_CLRENA_9 (0x00000200U) ///< bit 9 +#define NVIC_ICER_CLRENA_10 (0x00000400U) ///< bit 10 +#define NVIC_ICER_CLRENA_11 (0x00000800U) ///< bit 11 +#define NVIC_ICER_CLRENA_12 (0x00001000U) ///< bit 12 +#define NVIC_ICER_CLRENA_13 (0x00002000U) ///< bit 13 +#define NVIC_ICER_CLRENA_14 (0x00004000U) ///< bit 14 +#define NVIC_ICER_CLRENA_15 (0x00008000U) ///< bit 15 +#define NVIC_ICER_CLRENA_16 (0x00010000U) ///< bit 16 +#define NVIC_ICER_CLRENA_17 (0x00020000U) ///< bit 17 +#define NVIC_ICER_CLRENA_18 (0x00040000U) ///< bit 18 +#define NVIC_ICER_CLRENA_19 (0x00080000U) ///< bit 19 +#define NVIC_ICER_CLRENA_20 (0x00100000U) ///< bit 20 +#define NVIC_ICER_CLRENA_21 (0x00200000U) ///< bit 21 +#define NVIC_ICER_CLRENA_22 (0x00400000U) ///< bit 22 +#define NVIC_ICER_CLRENA_23 (0x00800000U) ///< bit 23 +#define NVIC_ICER_CLRENA_24 (0x01000000U) ///< bit 24 +#define NVIC_ICER_CLRENA_25 (0x02000000U) ///< bit 25 +#define NVIC_ICER_CLRENA_26 (0x04000000U) ///< bit 26 +#define NVIC_ICER_CLRENA_27 (0x08000000U) ///< bit 27 +#define NVIC_ICER_CLRENA_28 (0x10000000U) ///< bit 28 +#define NVIC_ICER_CLRENA_29 (0x20000000U) ///< bit 29 +#define NVIC_ICER_CLRENA_30 (0x40000000U) ///< bit 30 +#define NVIC_ICER_CLRENA_31 (0x80000000U) ///< bit 31 + +//////////////////////////////////////////////////////////////////////////////// +/// @brief NVIC_ISPR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define NVIC_ISPR_SETPEND (0xFFFFFFFFU) ///< Interrupt set-pending bits +#define NVIC_ISPR_SETPEND_0 (0x00000001U) ///< bit 0 +#define NVIC_ISPR_SETPEND_1 (0x00000002U) ///< bit 1 +#define NVIC_ISPR_SETPEND_2 (0x00000004U) ///< bit 2 +#define NVIC_ISPR_SETPEND_3 (0x00000008U) ///< bit 3 +#define NVIC_ISPR_SETPEND_4 (0x00000010U) ///< bit 4 +#define NVIC_ISPR_SETPEND_5 (0x00000020U) ///< bit 5 +#define NVIC_ISPR_SETPEND_6 (0x00000040U) ///< bit 6 +#define NVIC_ISPR_SETPEND_7 (0x00000080U) ///< bit 7 +#define NVIC_ISPR_SETPEND_8 (0x00000100U) ///< bit 8 +#define NVIC_ISPR_SETPEND_9 (0x00000200U) ///< bit 9 +#define NVIC_ISPR_SETPEND_10 (0x00000400U) ///< bit 10 +#define NVIC_ISPR_SETPEND_11 (0x00000800U) ///< bit 11 +#define NVIC_ISPR_SETPEND_12 (0x00001000U) ///< bit 12 +#define NVIC_ISPR_SETPEND_13 (0x00002000U) ///< bit 13 +#define NVIC_ISPR_SETPEND_14 (0x00004000U) ///< bit 14 +#define NVIC_ISPR_SETPEND_15 (0x00008000U) ///< bit 15 +#define NVIC_ISPR_SETPEND_16 (0x00010000U) ///< bit 16 +#define NVIC_ISPR_SETPEND_17 (0x00020000U) ///< bit 17 +#define NVIC_ISPR_SETPEND_18 (0x00040000U) ///< bit 18 +#define NVIC_ISPR_SETPEND_19 (0x00080000U) ///< bit 19 +#define NVIC_ISPR_SETPEND_20 (0x00100000U) ///< bit 20 +#define NVIC_ISPR_SETPEND_21 (0x00200000U) ///< bit 21 +#define NVIC_ISPR_SETPEND_22 (0x00400000U) ///< bit 22 +#define NVIC_ISPR_SETPEND_23 (0x00800000U) ///< bit 23 +#define NVIC_ISPR_SETPEND_24 (0x01000000U) ///< bit 24 +#define NVIC_ISPR_SETPEND_25 (0x02000000U) ///< bit 25 +#define NVIC_ISPR_SETPEND_26 (0x04000000U) ///< bit 26 +#define NVIC_ISPR_SETPEND_27 (0x08000000U) ///< bit 27 +#define NVIC_ISPR_SETPEND_28 (0x10000000U) ///< bit 28 +#define NVIC_ISPR_SETPEND_29 (0x20000000U) ///< bit 29 +#define NVIC_ISPR_SETPEND_30 (0x40000000U) ///< bit 30 +#define NVIC_ISPR_SETPEND_31 (0x80000000U) ///< bit 31 + +//////////////////////////////////////////////////////////////////////////////// +/// @brief NVIC_ICPR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define NVIC_ICPR_CLRPEND (0xFFFFFFFFU) ///< Interrupt clear-pending bits +#define NVIC_ICPR_CLRPEND_0 (0x00000001U) ///< bit 0 +#define NVIC_ICPR_CLRPEND_1 (0x00000002U) ///< bit 1 +#define NVIC_ICPR_CLRPEND_2 (0x00000004U) ///< bit 2 +#define NVIC_ICPR_CLRPEND_3 (0x00000008U) ///< bit 3 +#define NVIC_ICPR_CLRPEND_4 (0x00000010U) ///< bit 4 +#define NVIC_ICPR_CLRPEND_5 (0x00000020U) ///< bit 5 +#define NVIC_ICPR_CLRPEND_6 (0x00000040U) ///< bit 6 +#define NVIC_ICPR_CLRPEND_7 (0x00000080U) ///< bit 7 +#define NVIC_ICPR_CLRPEND_8 (0x00000100U) ///< bit 8 +#define NVIC_ICPR_CLRPEND_9 (0x00000200U) ///< bit 9 +#define NVIC_ICPR_CLRPEND_10 (0x00000400U) ///< bit 10 +#define NVIC_ICPR_CLRPEND_11 (0x00000800U) ///< bit 11 +#define NVIC_ICPR_CLRPEND_12 (0x00001000U) ///< bit 12 +#define NVIC_ICPR_CLRPEND_13 (0x00002000U) ///< bit 13 +#define NVIC_ICPR_CLRPEND_14 (0x00004000U) ///< bit 14 +#define NVIC_ICPR_CLRPEND_15 (0x00008000U) ///< bit 15 +#define NVIC_ICPR_CLRPEND_16 (0x00010000U) ///< bit 16 +#define NVIC_ICPR_CLRPEND_17 (0x00020000U) ///< bit 17 +#define NVIC_ICPR_CLRPEND_18 (0x00040000U) ///< bit 18 +#define NVIC_ICPR_CLRPEND_19 (0x00080000U) ///< bit 19 +#define NVIC_ICPR_CLRPEND_20 (0x00100000U) ///< bit 20 +#define NVIC_ICPR_CLRPEND_21 (0x00200000U) ///< bit 21 +#define NVIC_ICPR_CLRPEND_22 (0x00400000U) ///< bit 22 +#define NVIC_ICPR_CLRPEND_23 (0x00800000U) ///< bit 23 +#define NVIC_ICPR_CLRPEND_24 (0x01000000U) ///< bit 24 +#define NVIC_ICPR_CLRPEND_25 (0x02000000U) ///< bit 25 +#define NVIC_ICPR_CLRPEND_26 (0x04000000U) ///< bit 26 +#define NVIC_ICPR_CLRPEND_27 (0x08000000U) ///< bit 27 +#define NVIC_ICPR_CLRPEND_28 (0x10000000U) ///< bit 28 +#define NVIC_ICPR_CLRPEND_29 (0x20000000U) ///< bit 29 +#define NVIC_ICPR_CLRPEND_30 (0x40000000U) ///< bit 30 +#define NVIC_ICPR_CLRPEND_31 (0x80000000U) ///< bit 31 + +//////////////////////////////////////////////////////////////////////////////// +/// @brief NVIC_IABR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define NVIC_IABR_ACTIVE (0xFFFFFFFFU) ///< Interrupt active flags +#define NVIC_IABR_ACTIVE_0 (0x00000001U) ///< bit 0 +#define NVIC_IABR_ACTIVE_1 (0x00000002U) ///< bit 1 +#define NVIC_IABR_ACTIVE_2 (0x00000004U) ///< bit 2 +#define NVIC_IABR_ACTIVE_3 (0x00000008U) ///< bit 3 +#define NVIC_IABR_ACTIVE_4 (0x00000010U) ///< bit 4 +#define NVIC_IABR_ACTIVE_5 (0x00000020U) ///< bit 5 +#define NVIC_IABR_ACTIVE_6 (0x00000040U) ///< bit 6 +#define NVIC_IABR_ACTIVE_7 (0x00000080U) ///< bit 7 +#define NVIC_IABR_ACTIVE_8 (0x00000100U) ///< bit 8 +#define NVIC_IABR_ACTIVE_9 (0x00000200U) ///< bit 9 +#define NVIC_IABR_ACTIVE_10 (0x00000400U) ///< bit 10 +#define NVIC_IABR_ACTIVE_11 (0x00000800U) ///< bit 11 +#define NVIC_IABR_ACTIVE_12 (0x00001000U) ///< bit 12 +#define NVIC_IABR_ACTIVE_13 (0x00002000U) ///< bit 13 +#define NVIC_IABR_ACTIVE_14 (0x00004000U) ///< bit 14 +#define NVIC_IABR_ACTIVE_15 (0x00008000U) ///< bit 15 +#define NVIC_IABR_ACTIVE_16 (0x00010000U) ///< bit 16 +#define NVIC_IABR_ACTIVE_17 (0x00020000U) ///< bit 17 +#define NVIC_IABR_ACTIVE_18 (0x00040000U) ///< bit 18 +#define NVIC_IABR_ACTIVE_19 (0x00080000U) ///< bit 19 +#define NVIC_IABR_ACTIVE_20 (0x00100000U) ///< bit 20 +#define NVIC_IABR_ACTIVE_21 (0x00200000U) ///< bit 21 +#define NVIC_IABR_ACTIVE_22 (0x00400000U) ///< bit 22 +#define NVIC_IABR_ACTIVE_23 (0x00800000U) ///< bit 23 +#define NVIC_IABR_ACTIVE_24 (0x01000000U) ///< bit 24 +#define NVIC_IABR_ACTIVE_25 (0x02000000U) ///< bit 25 +#define NVIC_IABR_ACTIVE_26 (0x04000000U) ///< bit 26 +#define NVIC_IABR_ACTIVE_27 (0x08000000U) ///< bit 27 +#define NVIC_IABR_ACTIVE_28 (0x10000000U) ///< bit 28 +#define NVIC_IABR_ACTIVE_29 (0x20000000U) ///< bit 29 +#define NVIC_IABR_ACTIVE_30 (0x40000000U) ///< bit 30 +#define NVIC_IABR_ACTIVE_31 (0x80000000U) ///< bit 31 + +//////////////////////////////////////////////////////////////////////////////// +/// @brief NVIC_PRI0 Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define NVIC_IPR0_PRI_0 (0x000000FFU) ///< Priority of interrupt 0 +#define NVIC_IPR0_PRI_1 (0x0000FF00U) ///< Priority of interrupt 1 +#define NVIC_IPR0_PRI_2 (0x00FF0000U) ///< Priority of interrupt 2 +#define NVIC_IPR0_PRI_3 (0xFF000000U) ///< Priority of interrupt 3 + +//////////////////////////////////////////////////////////////////////////////// +/// @brief NVIC_PRI1 Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define NVIC_IPR1_PRI_4 (0x000000FFU) ///< Priority of interrupt 4 +#define NVIC_IPR1_PRI_5 (0x0000FF00U) ///< Priority of interrupt 5 +#define NVIC_IPR1_PRI_6 (0x00FF0000U) ///< Priority of interrupt 6 +#define NVIC_IPR1_PRI_7 (0xFF000000U) ///< Priority of interrupt 7 + +//////////////////////////////////////////////////////////////////////////////// +/// @brief NVIC_PRI2 Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define NVIC_IPR2_PRI_8 (0x000000FFU) ///< Priority of interrupt 8 +#define NVIC_IPR2_PRI_9 (0x0000FF00U) ///< Priority of interrupt 9 +#define NVIC_IPR2_PRI_10 (0x00FF0000U) ///< Priority of interrupt 10 +#define NVIC_IPR2_PRI_11 (0xFF000000U) ///< Priority of interrupt 11 + +//////////////////////////////////////////////////////////////////////////////// +/// @brief NVIC_PRI3 Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define NVIC_IPR3_PRI_12 (0x000000FFU) ///< Priority of interrupt 12 +#define NVIC_IPR3_PRI_13 (0x0000FF00U) ///< Priority of interrupt 13 +#define NVIC_IPR3_PRI_14 (0x00FF0000U) ///< Priority of interrupt 14 +#define NVIC_IPR3_PRI_15 (0xFF000000U) ///< Priority of interrupt 15 + +//////////////////////////////////////////////////////////////////////////////// +/// @brief NVIC_PRI4 Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define NVIC_IPR4_PRI_16 (0x000000FFU) ///< Priority of interrupt 16 +#define NVIC_IPR4_PRI_17 (0x0000FF00U) ///< Priority of interrupt 17 +#define NVIC_IPR4_PRI_18 (0x00FF0000U) ///< Priority of interrupt 18 +#define NVIC_IPR4_PRI_19 (0xFF000000U) ///< Priority of interrupt 19 + +//////////////////////////////////////////////////////////////////////////////// +/// @brief NVIC_PRI5 Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define NVIC_IPR5_PRI_20 (0x000000FFU) ///< Priority of interrupt 20 +#define NVIC_IPR5_PRI_21 (0x0000FF00U) ///< Priority of interrupt 21 +#define NVIC_IPR5_PRI_22 (0x00FF0000U) ///< Priority of interrupt 22 +#define NVIC_IPR5_PRI_23 (0xFF000000U) ///< Priority of interrupt 23 + +//////////////////////////////////////////////////////////////////////////////// +/// @brief NVIC_PRI6 Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define NVIC_IPR6_PRI_24 (0x000000FFU) ///< Priority of interrupt 24 +#define NVIC_IPR6_PRI_25 (0x0000FF00U) ///< Priority of interrupt 25 +#define NVIC_IPR6_PRI_26 (0x00FF0000U) ///< Priority of interrupt 26 +#define NVIC_IPR6_PRI_27 (0xFF000000U) ///< Priority of interrupt 27 + +//////////////////////////////////////////////////////////////////////////////// +/// @brief NVIC_PRI7 Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define NVIC_IPR7_PRI_28 (0x000000FFU) ///< Priority of interrupt 28 +#define NVIC_IPR7_PRI_29 (0x0000FF00U) ///< Priority of interrupt 29 +#define NVIC_IPR7_PRI_30 (0x00FF0000U) ///< Priority of interrupt 30 +#define NVIC_IPR7_PRI_31 (0xFF000000U) ///< Priority of interrupt 31 + +//////////////////////////////////////////////////////////////////////////////// +/// @brief NVIC_PRI8 Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define NVIC_IPR7_PRI_32 (0x000000FFU) ///< Priority of interrupt 32 +#define NVIC_IPR7_PRI_33 (0x0000FF00U) ///< Priority of interrupt 33 +#define NVIC_IPR7_PRI_34 (0x00FF0000U) ///< Priority of interrupt 34 +#define NVIC_IPR7_PRI_35 (0xFF000000U) ///< Priority of interrupt 35 + +//////////////////////////////////////////////////////////////////////////////// +/// @brief NVIC_PRI9 Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define NVIC_IPR7_PRI_36 (0x000000FFU) ///< Priority of interrupt 36 +#define NVIC_IPR7_PRI_37 (0x0000FF00U) ///< Priority of interrupt 37 +#define NVIC_IPR7_PRI_38 (0x00FF0000U) ///< Priority of interrupt 38 +#define NVIC_IPR7_PRI_39 (0xFF000000U) ///< Priority of interrupt 39 + +//////////////////////////////////////////////////////////////////////////////// +/// @brief NVIC_PRI10 Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define NVIC_IPR7_PRI_40 (0x000000FFU) ///< Priority of interrupt 40 +#define NVIC_IPR7_PRI_41 (0x0000FF00U) ///< Priority of interrupt 41 +#define NVIC_IPR7_PRI_42 (0x00FF0000U) ///< Priority of interrupt 42 +#define NVIC_IPR7_PRI_43 (0xFF000000U) ///< Priority of interrupt 43 + +//////////////////////////////////////////////////////////////////////////////// +/// @brief NVIC_PRI11 Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define NVIC_IPR7_PRI_44 (0x000000FFU) ///< Priority of interrupt 44 +#define NVIC_IPR7_PRI_45 (0x0000FF00U) ///< Priority of interrupt 45 +#define NVIC_IPR7_PRI_46 (0x00FF0000U) ///< Priority of interrupt 46 +#define NVIC_IPR7_PRI_47 (0xFF000000U) ///< Priority of interrupt 47 + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SCB_CPUID Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define SCB_CPUID_REVISION (0x0000000FU) ///< Implementation defined revision number +#define SCB_CPUID_PARTNO (0x0000FFF0U) ///< Number of processor within family +#define SCB_CPUID_Constant (0x000F0000U) ///< Reads as 0x0F +#define SCB_CPUID_VARIANT (0x00F00000U) ///< Implementation defined variant number +#define SCB_CPUID_IMPLEMENTER (0xFF000000U) ///< Implementer code. ARM is 0x41 + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SCB_ICSR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define SCB_ICSR_VECTACTIVE (0x000001FFU) ///< Active ISR number field +#define SCB_ICSR_RETTOBASE (0x00000800U) ///< All active exceptions minus the IPSR_current_exception yields the empty set +#define SCB_ICSR_VECTPENDING (0x003FF000U) ///< Pending ISR number field +#define SCB_ICSR_ISRPENDING (0x00400000U) ///< Interrupt pending flag +#define SCB_ICSR_ISRPREEMPT (0x00800000U) ///< It indicates that a pending interrupt becomes active in the next running cycle +#define SCB_ICSR_PENDSTCLR (0x02000000U) ///< Clear pending SysTick bit +#define SCB_ICSR_PENDSTSET (0x04000000U) ///< Set pending SysTick bit +#define SCB_ICSR_PENDSVCLR (0x08000000U) ///< Clear pending pendSV bit +#define SCB_ICSR_PENDSVSET (0x10000000U) ///< Set pending pendSV bit +#define SCB_ICSR_NMIPENDSET (0x80000000U) ///< Set pending NMI bit + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SCB_VTOR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define SCB_VTOR_TBLOFF (0x1FFFFF80U) ///< Vector table base offset field +#define SCB_VTOR_TBLBASE (0x20000000U) ///< Table base in code(0) or RAM(1) + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SCB_AIRCR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define SCB_AIRCR_VECTRESET (0x00000001U) ///< System Reset bit +#define SCB_AIRCR_VECTCLRACTIVE (0x00000002U) ///< Clear active vector bit +#define SCB_AIRCR_SYSRESETREQ (0x00000004U) ///< Requests chip control logic to generate a reset +#define SCB_AIRCR_PRIGROUP (0x00000700U) ///< PRIGROUP[2:0] bits (Priority group) +#define SCB_AIRCR_PRIGROUP_0 (0x00000100U) ///< Bit 0 +#define SCB_AIRCR_PRIGROUP_1 (0x00000200U) ///< Bit 1 +#define SCB_AIRCR_PRIGROUP_2 (0x00000400U) ///< Bit 2 + +#define SCB_AIRCR_PRIGROUP0 (0x00000000U) ///< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) +#define SCB_AIRCR_PRIGROUP1 (0x00000100U) ///< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) +#define SCB_AIRCR_PRIGROUP2 (0x00000200U) ///< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) +#define SCB_AIRCR_PRIGROUP3 (0x00000300U) ///< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) +#define SCB_AIRCR_PRIGROUP4 (0x00000400U) ///< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) +#define SCB_AIRCR_PRIGROUP5 (0x00000500U) ///< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) +#define SCB_AIRCR_PRIGROUP6 (0x00000600U) ///< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) +#define SCB_AIRCR_PRIGROUP7 (0x00000700U) ///< Priority group=7 (no pre-emption priority, 8 bits of subpriority) + +#define SCB_AIRCR_ENDIANESS (0x00008000U) ///< Data endianness bit +#define SCB_AIRCR_VECTKEY (0xFFFF0000U) ///< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SCB_SCR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define SCB_SCR_SLEEPONEXIT (0x02U) ///< Sleep on exit bit +#define SCB_SCR_SLEEPDEEP (0x04U) ///< Sleep deep bit +#define SCB_SCR_SEVONPEND (0x10U) ///< Wake up from WFE + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SCB_CCR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define SCB_CCR_NONBASETHRDENA (0x0001U) ///< Thread mode can be entered from any level in Handler mode by controlled return value +#define SCB_CCR_USERSETMPEND (0x0002U) ///< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception +#define SCB_CCR_UNALIGN_TRP (0x0008U) ///< Trap for unaligned access +#define SCB_CCR_DIV_0_TRP (0x0010U) ///< Trap on Divide by 0 +#define SCB_CCR_BFHFNMIGN (0x0100U) ///< Handlers running at priority -1 and -2 +#define SCB_CCR_STKALIGN (0x0200U) ///< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SCB_SHPR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define SCB_SHPR_PRI_N (0x000000FFU) ///< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor +#define SCB_SHPR_PRI_N1 (0x0000FF00U) ///< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved +#define SCB_SHPR_PRI_N2 (0x00FF0000U) ///< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV +#define SCB_SHPR_PRI_N3 (0xFF000000U) ///< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SCB_SHCSR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define SCB_SHCSR_MEMFAULTACT (0x00000001U) ///< MemManage is active +#define SCB_SHCSR_BUSFAULTACT (0x00000002U) ///< BusFault is active +#define SCB_SHCSR_USGFAULTACT (0x00000008U) ///< UsageFault is active +#define SCB_SHCSR_SVCALLACT (0x00000080U) ///< SVCall is active +#define SCB_SHCSR_MONITORACT (0x00000100U) ///< Monitor is active +#define SCB_SHCSR_PENDSVACT (0x00000400U) ///< PendSV is active +#define SCB_SHCSR_SYSTICKACT (0x00000800U) ///< SysTick is active +#define SCB_SHCSR_USGFAULTPENDED (0x00001000U) ///< Usage Fault is pended +#define SCB_SHCSR_MEMFAULTPENDED (0x00002000U) ///< MemManage is pended +#define SCB_SHCSR_BUSFAULTPENDED (0x00004000U) ///< Bus Fault is pended +#define SCB_SHCSR_SVCALLPENDED (0x00008000U) ///< SVCall is pended +#define SCB_SHCSR_MEMFAULTENA (0x00010000U) ///< MemManage enable +#define SCB_SHCSR_BUSFAULTENA (0x00020000U) ///< Bus Fault enable +#define SCB_SHCSR_USGFAULTENA (0x00040000U) ///< UsageFault enable + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SCB_CFSR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +///< MFSR +#define SCB_CFSR_IACCVIOL (0x00000001U) ///< Instruction access violation +#define SCB_CFSR_DACCVIOL (0x00000002U) ///< Data access violation +#define SCB_CFSR_MUNSTKERR (0x00000008U) ///< Unstacking error +#define SCB_CFSR_MSTKERR (0x00000010U) ///< Stacking error +#define SCB_CFSR_MMARVALID (0x00000080U) ///< Memory Manage Address Register address valid flag +///< BFSR +#define SCB_CFSR_IBUSERR (0x00000100U) ///< Instruction bus error flag +#define SCB_CFSR_PRECISERR (0x00000200U) ///< Precise data bus error +#define SCB_CFSR_IMPRECISERR (0x00000400U) ///< Imprecise data bus error +#define SCB_CFSR_UNSTKERR (0x00000800U) ///< Unstacking error +#define SCB_CFSR_STKERR (0x00001000U) ///< Stacking error +#define SCB_CFSR_BFARVALID (0x00008000U) ///< Bus Fault Address Register address valid flag +///< UFSR +#define SCB_CFSR_UNDEFINSTR (0x00010000U) ///< The processor attempt to excecute an undefined instruction +#define SCB_CFSR_INVSTATE (0x00020000U) ///< Invalid combination of EPSR and instruction +#define SCB_CFSR_INVPC (0x00040000U) ///< Attempt to load EXC_RETURN into pc illegally +#define SCB_CFSR_NOCP (0x00080000U) ///< Attempt to use a coprocessor instruction +#define SCB_CFSR_UNALIGNED (0x01000000U) ///< Fault occurs when there is an attempt to make an unaligned memory access +#define SCB_CFSR_DIVBYZERO (0x02000000U) ///< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SCB_HFSR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define SCB_HFSR_VECTTBL (0x00000002U) ///< Fault occures because of vector table read on exception processing +#define SCB_HFSR_FORCED (0x40000000U) ///< Hard Fault activated when a configurable Fault was received and cannot activate +#define SCB_HFSR_DEBUGEVT (0x80000000U) ///< Fault related to debug + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SCB_DFSR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define SCB_DFSR_HALTED (0x01U) ///< Halt request flag +#define SCB_DFSR_BKPT (0x02U) ///< BKPT flag +#define SCB_DFSR_DWTTRAP (0x04U) ///< Data Watchpoint and Trace (DWT) flag +#define SCB_DFSR_VCATCH (0x08U) ///< Vector catch flag +#define SCB_DFSR_EXTERNAL (0x10U) ///< External debug request flag + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SCB_MMFAR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define SCB_MMFAR_ADDRESS (0xFFFFFFFFU) ///< Mem Manage fault address field + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SCB_BFAR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define SCB_BFAR_ADDRESS (0xFFFFFFFFU) ///< Bus fault address field + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SCB_AFSR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define SCB_AFSR_IMPDEF (0xFFFFFFFFU) ///< Implementation defined + + + +#endif +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_comp.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_comp.h new file mode 100644 index 000000000..71297819c --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_comp.h @@ -0,0 +1,228 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file reg_comp.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF +/// MM32 FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

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+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion + +#ifndef __REG_COMP_H +#define __REG_COMP_H + +// Files includes + +#include +#include +#include "types.h" + + + + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + + + + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief COMP Base Address Definition +//////////////////////////////////////////////////////////////////////////////// +#define COMP_BASE (APB2PERIPH_BASE + 0x4000) ///< Base Address: 0x40014000 + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Comparators Register Structure Definition +//////////////////////////////////////////////////////////////////////////////// +typedef struct { + + + + __IO u32 RESERVED1; ///< offset: 0x00 + __IO u32 RESERVED2; ///< offset: 0x04 + __IO u32 RESERVED3; ///< offset: 0x08 + union { + __IO u32 CSR1; ///< COMP1 Control Status Register offset: 0x0C + __IO u32 COMP1_CSR; + }; + union { + __IO u32 CSR2; ///< COMP2 Control Status Register offset: 0x10 + __IO u32 COMP2_CSR; + }; + __IO u32 RESERVED4; ///< offset: 0x14 + union { + __IO u32 CRV; ///< COMP external reference voltage register offset: 0x18 + __IO u32 COMP_CRV; + }; + union { + __IO u32 POLL1; ///< COMP1 polling register offset: 0x1C + __IO u32 COMP1_POLL; + }; + union { + __IO u32 POLL2; ///< COMP2 polling register offset: 0x20 + __IO u32 COMP2_POLL; + }; +} COMP_TypeDef; + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief COMP type pointer Definition +//////////////////////////////////////////////////////////////////////////////// +#define COMP ((COMP_TypeDef*) COMP_BASE) + + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief COMP_CSR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define COMP_CSR_EN_Pos (0) +#define COMP_CSR_EN (0x01U << COMP_CSR_EN_Pos) ///< Comparator enable +#define COMP_CSR_MODE_Pos (2) +#define COMP_CSR_MODE (0x03U << COMP_CSR_MODE_Pos) ///< Comparator mode +#define COMP_CSR_MODE_LOWESTPOWER (0x00U << COMP_CSR_MODE_Pos) ///< Comparator lowest power mode +#define COMP_CSR_MODE_LOWPOWER (0x01U << COMP_CSR_MODE_Pos) ///< Comparator low power mode +#define COMP_CSR_MODE_MEDIUMRATE (0x02U << COMP_CSR_MODE_Pos) ///< Comparator medium rate mode +#define COMP_CSR_MODE_HIGHRATE (0x03U << COMP_CSR_MODE_Pos) ///< Comparator high rate mode + +#define COMP_CSR_INM_Pos (4) +#define COMP_CSR_INM (0x03U << COMP_CSR_INM_Pos) ///< Comparator inverting input selection +#define COMP_CSR_INM_0 (0x00U << COMP_CSR_INM_Pos) ///< INM0 as COMP inverting input +#define COMP_CSR_INM_1 (0x01U << COMP_CSR_INM_Pos) ///< INM1 as COMP inverting input +#define COMP_CSR_INM_2 (0x02U << COMP_CSR_INM_Pos) ///< INM2 as COMP inverting input +#define COMP_CSR_INM_3 (0x03U << COMP_CSR_INM_Pos) ///< INM3 as COMP inverting input + +#define COMP_CSR_INP_Pos (7) +#define COMP_CSR_INP (0x03U << COMP_CSR_INP_Pos) ///< Comparator non-inverting input selection +#define COMP_CSR_INP_INP0 (0x00U << COMP_CSR_INP_Pos) ///< INP0 as COMP non-inverting input +#define COMP_CSR_INP_INP1 (0x01U << COMP_CSR_INP_Pos) ///< INP1 as COMP non-inverting input +#define COMP_CSR_INP_INP2 (0x02U << COMP_CSR_INP_Pos) ///< INP2 as COMP non-inverting input +#define COMP_CSR_INP_INP3 (0x03U << COMP_CSR_INP_Pos) ///< INP3 as COMP non-inverting input + +#define COMP_CSR_OUT_Pos (10) +#define COMP_CSR_OUT (0x0FU << COMP_CSR_OUT_Pos) ///< Comparator output selection +#define COMP_CSR_OUT_TIM1_BRAKE (0x02U << COMP_CSR_OUT_Pos) ///< Timer1 brake input +#define COMP_CSR_OUT_TIM8_BRAKE (0x03U << COMP_CSR_OUT_Pos) ///< Timer8 brake input +#define COMP_CSR_OUT_TIM1_OCREFCLR (0x06U << COMP_CSR_OUT_Pos) ///< Timer1 ocrefclear input +#define COMP_CSR_OUT_TIM1_CAPTURE1 (0x07U << COMP_CSR_OUT_Pos) ///< Timer1 input capture 1 +#define COMP_CSR_OUT_TIM2_CAPTURE4 (0x08U << COMP_CSR_OUT_Pos) ///< Timer2 input capture 4 +#define COMP_CSR_OUT_TIM2_OCREFCLR (0x09U << COMP_CSR_OUT_Pos) ///< Timer2 ocrefclear input +#define COMP_CSR_OUT_TIM3_CAPTURE1 (0x0AU << COMP_CSR_OUT_Pos) ///< Timer3 input capture 1 +#define COMP_CSR_OUT_TIM3_OCREFCLR (0x0BU << COMP_CSR_OUT_Pos) ///< Timer3 ocrefclear input +#define COMP_CSR_OUT_TIM8_OCREFCLR (0x0FU << COMP_CSR_OUT_Pos) ///< Timer8 ocrefclear input + +#define COMP_CSR_POL_Pos (15) +#define COMP_CSR_POL (0x01U << COMP_CSR_POL_Pos) ///< Comparator output polarity +#define COMP_CSR_HYST_Pos (16) +#define COMP_CSR_HYST (0x03U << COMP_CSR_HYST_Pos) ///< Comparator hysteresis +#define COMP_CSR_HYST_0 (0x00U << COMP_CSR_HYST_Pos) ///< Hysteresis Voltage: 0mV +#define COMP_CSR_HYST_15 (0x01U << COMP_CSR_HYST_Pos) ///< Hysteresis Voltage: 15mV +#define COMP_CSR_HYST_30 (0x02U << COMP_CSR_HYST_Pos) ///< Hysteresis Voltage: 30mV +#define COMP_CSR_HYST_90 (0x03U << COMP_CSR_HYST_Pos) ///< Hysteresis Voltage: 90mV + +#define COMP_CSR_OFLT_Pos (18) +#define COMP_CSR_OFLT (0x07U << COMP_CSR_OFLT_Pos) ///< Comparator output filter +#define COMP_CSR_OFLT_0 (0x00U << COMP_CSR_OFLT_Pos) ///< 0 clock cycle +#define COMP_CSR_OFLT_1 (0x01U << COMP_CSR_OFLT_Pos) ///< 2 clock cycle +#define COMP_CSR_OFLT_2 (0x02U << COMP_CSR_OFLT_Pos) ///< 4 clock cycle +#define COMP_CSR_OFLT_3 (0x03U << COMP_CSR_OFLT_Pos) ///< 8 clock cycle +#define COMP_CSR_OFLT_4 (0x04U << COMP_CSR_OFLT_Pos) ///< 16 clock cycle +#define COMP_CSR_OFLT_5 (0x05U << COMP_CSR_OFLT_Pos) ///< 32 clock cycle +#define COMP_CSR_OFLT_6 (0x06U << COMP_CSR_OFLT_Pos) ///< 64 clock cycle +#define COMP_CSR_OFLT_7 (0x07U << COMP_CSR_OFLT_Pos) ///< 128 clock cycle + +#define COMP_CSR_STA_Pos (30) +#define COMP_CSR_STA (0x01U << COMP_CSR_STA_Pos) ///< Comparator output status +#define COMP_CSR_LOCK_Pos (31) +#define COMP_CSR_LOCK (0x01U << COMP_CSR_LOCK_Pos) ///< Comparator lock + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief COMP_CRV Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define COMP_CRV_Pos (0) +#define COMP_CRV_MASK (0x0FU << COMP_CRV_Pos) ///< Comparator external reference voltage select +#define COMP_CRV_1_20 (0x00U << COMP_CRV_Pos) ///< Comparator external reference voltage select +#define COMP_CRV_2_20 (0x01U << COMP_CRV_Pos) ///< Comparator external reference voltage select +#define COMP_CRV_3_20 (0x02U << COMP_CRV_Pos) ///< Comparator external reference voltage select +#define COMP_CRV_4_20 (0x03U << COMP_CRV_Pos) ///< Comparator external reference voltage select +#define COMP_CRV_5_20 (0x04U << COMP_CRV_Pos) ///< Comparator external reference voltage select +#define COMP_CRV_6_20 (0x05U << COMP_CRV_Pos) ///< Comparator external reference voltage select +#define COMP_CRV_7_20 (0x06U << COMP_CRV_Pos) ///< Comparator external reference voltage select +#define COMP_CRV_8_20 (0x07U << COMP_CRV_Pos) ///< Comparator external reference voltage select +#define COMP_CRV_9_20 (0x08U << COMP_CRV_Pos) ///< Comparator external reference voltage select +#define COMP_CRV_10_20 (0x09U << COMP_CRV_Pos) ///< Comparator external reference voltage select +#define COMP_CRV_11_20 (0x0AU << COMP_CRV_Pos) ///< Comparator external reference voltage select +#define COMP_CRV_12_20 (0x0BU << COMP_CRV_Pos) ///< Comparator external reference voltage select +#define COMP_CRV_13_20 (0x0CU << COMP_CRV_Pos) ///< Comparator external reference voltage select +#define COMP_CRV_14_20 (0x0DU << COMP_CRV_Pos) ///< Comparator external reference voltage select +#define COMP_CRV_15_20 (0x0EU << COMP_CRV_Pos) ///< Comparator external reference voltage select +#define COMP_CRV_16_20 (0x0FU << COMP_CRV_Pos) ///< Comparator external reference voltage select + +#define COMP_CRV_EN_Pos (4) +#define COMP_CRV_EN (0x01U << COMP_CRV_EN_Pos) ///< Comparator external reference voltage enable +#define COMP_CRV_EN_DISABLE (0x00U << COMP_CRV_EN_Pos) ///< Disable comparator external reference voltage +#define COMP_CRV_EN_ENABLE (0x01U << COMP_CRV_EN_Pos) ///< Enable comparator external reference voltage +#define COMP_CRV_SRC_Pos (5) +#define COMP_CRV_SRC (0x01U << COMP_CRV_SRC_Pos) ///< Comparator external reference voltage source select +#define COMP_CRV_SRC_VREF (0x00U << COMP_CRV_SRC_Pos) ///< Select VREF +#define COMP_CRV_SRC_AVDD (0x01U << COMP_CRV_SRC_Pos) ///< Select AVDD + +//////////////////////////////////////////////////////////////////////////////// +/// @brief COMP_POL Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define COMP_POLL_EN_Pos (0) +#define COMP_POLL_EN (0x01U << COMP_POLL_EN_Pos) ///< Comparator polling enable +#define COMP_POLL_EN_DISABLE (0x00U << COMP_POLL_EN_Pos) ///< Disable comparator polling mode +#define COMP_POLL_EN_ENABLE (0x01U << COMP_POLL_EN_Pos) ///< Enable comparator polling mode +#define COMP_POLL_CH_Pos (1) +#define COMP_POLL_CH (0x01U << COMP_POLL_CH_Pos) ///< Comparator polling channel +#define COMP_POLL_CH_1_2 (0x00U << COMP_POLL_CH_Pos) ///< Polling channel 1/2 +#define COMP_POLL_CH_1_2_3 (0x01U << COMP_POLL_CH_Pos) ///< Polling channel 1/2/3 +#define COMP_POLL_FIXN_Pos (2) +#define COMP_POLL_FIXN (0x01U << COMP_POLL_FIXN_Pos) ///< Polling inverting input fix +#define COMP_POLL_FIXN_NOTFIXED (0x00U << COMP_POLL_FIXN_Pos) ///< Polling channel inverting input is not fixed +#define COMP_POLL_FIXN_FIXED (0x01U << COMP_POLL_FIXN_Pos) ///< Polling channel inverting input fixed +#define COMP_POLL_PERIOD_Pos (4) +#define COMP_POLL_PERIOD (0x07U << COMP_POLL_PERIOD_Pos) ///< polling wait cycle +#define COMP_POLL_PERIOD_1 (0x00U << COMP_POLL_PERIOD_Pos) ///< 1 clock cycle +#define COMP_POLL_PERIOD_2 (0x01U << COMP_POLL_PERIOD_Pos) ///< 2 clock cycle +#define COMP_POLL_PERIOD_4 (0x02U << COMP_POLL_PERIOD_Pos) ///< 4 clock cycle +#define COMP_POLL_PERIOD_8 (0x03U << COMP_POLL_PERIOD_Pos) ///< 8 clock cycle +#define COMP_POLL_PERIOD_16 (0x04U << COMP_POLL_PERIOD_Pos) ///< 16 clock cycle +#define COMP_POLL_PERIOD_32 (0x05U << COMP_POLL_PERIOD_Pos) ///< 32 clock cycle +#define COMP_POLL_PERIOD_64 (0x06U << COMP_POLL_PERIOD_Pos) ///< 64 clock cycle +#define COMP_POLL_PERIOD_128 (0x07U << COMP_POLL_PERIOD_Pos) ///< 128 clock cycle +#define COMP_POLL_POUT_Pos (8) +#define COMP_POLL_POUT (0x07U << COMP_POLL_POUT_Pos) ///< Polling output +#define COMP_POLL_POUT_Low (0x00U << COMP_POLL_POUT_Pos) ///< Non-inverting input is lower than inverting input +#define COMP_POLL_POUT_High (0x01U << COMP_POLL_POUT_Pos) ///< Non-inverting input is higher than inverting input + + + + + +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +#endif +//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_crc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_crc.h new file mode 100644 index 000000000..9bb28e56f --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_crc.h @@ -0,0 +1,102 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file reg_crc.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF +/// MM32 FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion + +#ifndef __REG_CRC_H +#define __REG_CRC_H + +// Files includes +#include +#include +#include "types.h" + + + + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + + + + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief CRC Base Address Definition +//////////////////////////////////////////////////////////////////////////////// +#define CRC_BASE (AHBPERIPH_BASE + 0x3000) ///< Base Address: 0x40023000 + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief CRC Register Structure Definition +//////////////////////////////////////////////////////////////////////////////// +typedef struct { + __IO u32 DR; ///< CRC data register, offset: 0x00 + __IO u32 IDR; ///< CRC independent data register, offset: 0x04 + __IO u32 CR; ///< CRC control register, offset: 0x08 + __IO u32 MIR; ///< Middle data register, offset: 0x08 +} CRC_TypeDef; + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief CRC type pointer Definition +//////////////////////////////////////////////////////////////////////////////// +#define CRC ((CRC_TypeDef*) CRC_BASE) + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief CRC_DR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define CRC_DR_DATA_Pos (0) +#define CRC_DR_DATA (0xFFFFFFFFU << CRC_DR_DATA_Pos) ///< Data register bits +//////////////////////////////////////////////////////////////////////////////// +/// @brief CRC_IDR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define CRC_IDR_DATA_Pos (0) +#define CRC_IDR_DATA (0xFFU << CRC_IDR_DATA_Pos) ///< General-purpose 8-bit data register bits + +//////////////////////////////////////////////////////////////////////////////// +/// @brief CRC_CTRL Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define CRC_CR_RESET_Pos (0) +#define CRC_CR_RESET (0x01U << CRC_CR_RESET_Pos) ///< RESET bit +//////////////////////////////////////////////////////////////////////////////// +/// @brief CRC_MIR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define CRC_MIR_Pos (0) +#define CRC_MIR (0xFFFFFFFFU << CRC_MIR_Pos) ///< Middle data register + + + + +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +#endif +//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_crs.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_crs.h new file mode 100644 index 000000000..a8beece98 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_crs.h @@ -0,0 +1,152 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file reg_crs.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF +/// MM32 FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion + +#ifndef __REG_CRS_H +#define __REG_CRS_H + +// Files includes + +#include +#include +#include "types.h" + + + + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + + + + + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief CRS Base Address Definition +//////////////////////////////////////////////////////////////////////////////// +#define CRS_BASE (APB1PERIPH_BASE + 0x6C00) ///< Base Address: 0x40006C00 + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief CRS Register Structure Definition +//////////////////////////////////////////////////////////////////////////////// +typedef struct { + __IO u32 CR; ///< Control Register offset: 0x00 + __IO u32 CFGR; ///< Configuration Register offset: 0x04 + __IO u32 ISR; ///< Interrupt and Status Register offset: 0x08 + __IO u32 ICR; ///< Interrupt Flag Clear Register offset: 0x0C +} CRS_TypeDef; + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief CRS type pointer Definition +//////////////////////////////////////////////////////////////////////////////// +#define CRS ((CRS_TypeDef*) CRS_BASE) + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief CRS_CR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define CRS_CR_OKIE_Pos (0) +#define CRS_CR_OKIE (0x01U << CRS_CR_OKIE_Pos) ///< SYNC event OK interrupt enable +#define CRS_CR_WARNIE_Pos (1) +#define CRS_CR_WARNIE (0x01U << CRS_CR_WARNIE_Pos) ///< SYNC warning interrupt enable +#define CRS_CR_ERRIE_Pos (2) +#define CRS_CR_ERRIE (0x01U << CRS_CR_ERRIE_Pos) ///< Synchronization or trimming error interrupt enable +#define CRS_CR_EXPTIE_Pos (3) +#define CRS_CR_EXPTIE (0x01U << CRS_CR_EXPTIE_Pos) ///< Expected SYNC interrupt enable +#define CRS_CR_CNTEN_Pos (5) +#define CRS_CR_CNTEN (0x01U << CRS_CR_CNTEN_Pos) ///< Frequency error counter enable +#define CRS_CR_AUTOTRIMEN_Pos (6) +#define CRS_CR_AUTOTRIMEN (0x01U << CRS_CR_AUTOTRIMEN_Pos) ///< Automatic trimming enable +#define CRS_CR_SWSYNC_Pos (7) +#define CRS_CR_SWSYNC (0x01U << CRS_CR_SWSYNC_Pos) ///< Generate software SYNC event +#define CRS_CR_TRIM_Pos (8) +#define CRS_CR_TRIM (0x3FFU << CRS_CR_TRIM_Pos) ///< HSI 48 oscillator smooth trimming + +//////////////////////////////////////////////////////////////////////////////// +/// @brief CRS_CFGR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define CRS_CFGR_RELOAD_Pos (0) +#define CRS_CFGR_RELOAD (0xFFFFU << CRS_CFGR_RELOAD_Pos) ///< Counter reload value +#define CRS_CFGR_FELIM_Pos (16) +#define CRS_CFGR_FELIM (0xFFU << CRS_CFGR_FELIM_Pos) ///< Frequency error limit +#define CRS_CFGR_DIV_Pos (24) +#define CRS_CFGR_DIV (0x07U << CRS_CFGR_DIV_Pos) ///< SYNC divider +#define CRS_CFGR_SRC_Pos (28) +#define CRS_CFGR_SRC (0x03U << CRS_CFGR_SRC_Pos) ///< SYNC signal source selection +#define CRS_CFGR_SRC_MCO (0x00U << CRS_CFGR_SRC_Pos) +#define CRS_CFGR_SRC_USBSOF (0x02U << CRS_CFGR_SRC_Pos) +#define CRS_CFGR_POL_Pos (31) +#define CRS_CFGR_POL (0x01U << CRS_CFGR_POL_Pos) ///< SYNC polarity selection + +//////////////////////////////////////////////////////////////////////////////// +/// @brief CRS_ISR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define CRS_ISR_OKIF_Pos (0) +#define CRS_ISR_OKIF (0x01U << CRS_ISR_OKIF_Pos) ///< SYNC event OK flag +#define CRS_ISR_WARNIF_Pos (1) +#define CRS_ISR_WARNIF (0x01U << CRS_ISR_WARNIF_Pos) ///< SYNC warning flag +#define CRS_ISR_ERRIF_Pos (2) +#define CRS_ISR_ERRIF (0x01U << CRS_ISR_ERRIF_Pos) ///< Error flag +#define CRS_ISR_EXPTIF_Pos (3) +#define CRS_ISR_EXPTIF (0x01U << CRS_ISR_EXPTIF_Pos) ///< Expected SYNC flag +#define CRS_ISR_ERR_Pos (8) +#define CRS_ISR_ERR (0x01U << CRS_ISR_ERR_Pos) ///< SYNC error +#define CRS_ISR_MISS_Pos (9) +#define CRS_ISR_MISS (0x01U << CRS_ISR_MISS_Pos) ///< SYNC missed +#define CRS_ISR_OVERFLOW_Pos (10) +#define CRS_ISR_OVERFLOW (0x01U << CRS_ISR_OVERFLOW_Pos) ///< Trimming overflow or underflow +#define CRS_ISR_FEDIR_Pos (15) +#define CRS_ISR_FEDIR (0x01U << CRS_ISR_FEDIR_Pos) ///< Frequency error direction +#define CRS_ISR_FECAP_Pos (16) +#define CRS_ISR_FECAP (0xFFFFU << CRS_ISR_FECAP_Pos) ///< Frequency error capture + +//////////////////////////////////////////////////////////////////////////////// +/// @brief CRS_ICR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define CRS_ICR_OK_Pos (0) +#define CRS_ICR_OK (0x01U << CRS_ICR_OK_Pos) ///< SYNC event OK clear flag +#define CRS_ICR_WARN_Pos (1) +#define CRS_ICR_WARN (0x01U << CRS_ICR_WARN_Pos) ///< SYNC warning clear flag +#define CRS_ICR_ERR_Pos (2) +#define CRS_ICR_ERR (0x01U << CRS_ICR_ERR_Pos) ///< Error clear flag +#define CRS_ICR_EXPT_Pos (3) +#define CRS_ICR_EXPT (0x01U << CRS_ICR_EXPT_Pos) ///< Expected SYNC clear flag + + + + + +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +#endif +//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dac.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dac.h new file mode 100644 index 000000000..2e8d1883d --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dac.h @@ -0,0 +1,247 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file reg_dac.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF +/// MM32 FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion + +#ifndef __REG_DAC_H +#define __REG_DAC_H + +// Files includes + +#include +#include +#include "types.h" + + + + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + + + + + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief DAC Base Address Definition +//////////////////////////////////////////////////////////////////////////////// +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) ///< Base Address: 0x40007400 + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Digital to analog converter register +//////////////////////////////////////////////////////////////////////////////// +typedef struct { + __IO u32 CR; ///< DAC control register, offset: 0x00 + __IO u32 SWTRIGR; ///< DAC software trigger register, offset: 0x04 + __IO u32 DHR12R1; ///< Channel 1 12-bit right align data register, offset: 0x08 + __IO u32 DHR12L1; ///< Channel 1 12-bit left align data register, offset: 0x0C + __IO u32 DHR8R1; ///< Channel 1 8-bit right align data register, offset: 0x10 + __IO u32 DHR12R2; ///< Channel 2 12-bit right align data register, offset: 0x14 + __IO u32 DHR12L2; ///< Channel 2 12-bit left align data register, offset: 0x18 + __IO u32 DHR8R2; ///< Channel 2 8-bit right align data register, offset: 0x1C + __IO u32 DHR12RD; ///< Dual channel 12-bit right align data register,offset: 0x20 + __IO u32 DHR12LD; ///< Dual channel 12-bit left align data register, offset: 0x24 + __IO u32 DHR8RD; ///< Dual channel 8-bit right align data register, offset: 0x28 + __IO u32 DOR1; ///< Channel 1 output register, offset: 0x2C + __IO u32 DOR2; ///< Channel 2 output register, offset: 0x30 +} DAC_TypeDef; + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief DAC type pointer Definition +//////////////////////////////////////////////////////////////////////////////// +#define DAC ((DAC_TypeDef*) DAC_BASE) + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief DAC_CR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define DAC_CR_EN1_Pos (0) +#define DAC_CR_EN1 (0x01U << DAC_CR_EN1_Pos) ///< DAC channel1 enable +#define DAC_CR_BOFF1_Pos (1) +#define DAC_CR_BOFF1 (0x01U << DAC_CR_BOFF1_Pos) ///< DAC channel1 output buffer disable +#define DAC_CR_TEN1_Pos (2) +#define DAC_CR_TEN1 (0x01U << DAC_CR_TEN1_Pos) ///< DAC channel1 Trigger enable +#define DAC_CR_TSEL1_Pos (3) +#define DAC_CR_TSEL1 (0x07U << DAC_CR_TSEL1_Pos) ///< TSEL1[2:0] (DAC channel1 Trigger selection) +#define DAC_CR_TSEL1_TIM1_TRIG (0x00U << DAC_CR_TSEL1_Pos) ///< TIM1_TRIG trigger +#define DAC_CR_TSEL1_TIM3_TRIG (0x01U << DAC_CR_TSEL1_Pos) ///< TIM3_TRIG trigger +#define DAC_CR_TSEL1_TIM2_TRIG (0x04U << DAC_CR_TSEL1_Pos) ///< TIM2_TRIG trigger +#define DAC_CR_TSEL1_TIM4_TRIG (0x05U << DAC_CR_TSEL1_Pos) ///< TIM4_TRIG trigger +#define DAC_CR_TSEL1_EXTI9 (0x06U << DAC_CR_TSEL1_Pos) ///< External interrupt line 9 trigger +#define DAC_CR_TSEL1_SOFTWARE (0x07U << DAC_CR_TSEL1_Pos) ///< Software trigger +#define DAC_CR_WAVE1_Pos (6) +#define DAC_CR_WAVE1 (0x03U << DAC_CR_WAVE1_Pos) ///< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) +#define DAC_CR_WAVE1_NONE (0x00U << DAC_CR_WAVE1_Pos) ///< Turn off waveform generation +#define DAC_CR_WAVE1_NOISE (0x01U << DAC_CR_WAVE1_Pos) ///< Noise waveform generation +#define DAC_CR_WAVE1_TRIANGLE (0x02U << DAC_CR_WAVE1_Pos) ///< Triangle wave generation +#define DAC_CR_MAMP1_Pos (8) +#define DAC_CR_MAMP1 (0x0FU << DAC_CR_MAMP1_Pos) ///< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) +#define DAC_CR_MAMP1_1 (0x00U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 1 +#define DAC_CR_MAMP1_3 (0x01U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 3 +#define DAC_CR_MAMP1_7 (0x02U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 7 +#define DAC_CR_MAMP1_15 (0x03U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 15 +#define DAC_CR_MAMP1_31 (0x04U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 31 +#define DAC_CR_MAMP1_63 (0x05U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 63 +#define DAC_CR_MAMP1_127 (0x06U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 127 +#define DAC_CR_MAMP1_255 (0x07U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 255 +#define DAC_CR_MAMP1_511 (0x08U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 511 +#define DAC_CR_MAMP1_1023 (0x09U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 1023 +#define DAC_CR_MAMP1_2047 (0x0AU << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 2047 +#define DAC_CR_MAMP1_4095 (0x0BU << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 4095 +#define DAC_CR_DMAEN1_Pos (12) +#define DAC_CR_DMAEN1 (0x01U << DAC_CR_DMAEN1_Pos) ///< DAC channel1 DMA enable +#define DAC_CR_EN2_Pos (16) +#define DAC_CR_EN2 (0x01U << DAC_CR_EN2_Pos) ///< DAC channel2 enable +#define DAC_CR_BOFF2_Pos (17) +#define DAC_CR_BOFF2 (0x01U << DAC_CR_BOFF2_Pos) ///< DAC channel2 output buffer disable +#define DAC_CR_TEN2_Pos (18) +#define DAC_CR_TEN2 (0x01U << DAC_CR_TEN2_Pos) ///< DAC channel2 Trigger enable +#define DAC_CR_TSEL2_Pos (19) +#define DAC_CR_TSEL2 (0x07U << DAC_CR_TSEL2_Pos) ///< TSEL1[2:0] (DAC channel1 Trigger selection) +#define DAC_CR_TSEL2_TIM1_TRIG (0x00U << DAC_CR_TSEL2_Pos) ///< TIM1_TRIG trigger +#define DAC_CR_TSEL2_TIM3_TRIG (0x01U << DAC_CR_TSEL2_Pos) ///< TIM3_TRIG trigger +#define DAC_CR_TSEL2_TIM2_TRIG (0x04U << DAC_CR_TSEL2_Pos) ///< TIM2_TRIG trigger +#define DAC_CR_TSEL2_TIM4_TRIG (0x05U << DAC_CR_TSEL2_Pos) ///< TIM4_TRIG trigger +#define DAC_CR_TSEL2_EXTI9 (0x06U << DAC_CR_TSEL2_Pos) ///< External interrupt line 9 trigger +#define DAC_CR_TSEL2_SOFTWARE (0x07U << DAC_CR_TSEL2_Pos) ///< Software trigger +#define DAC_CR_WAVE2_Pos (22) +#define DAC_CR_WAVE2 (0x03U << DAC_CR_WAVE2_Pos) ///< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) +#define DAC_CR_WAVE2_NONE (0x00U << DAC_CR_WAVE2_Pos) ///< Turn off waveform generation +#define DAC_CR_WAVE2_NOISE (0x01U << DAC_CR_WAVE2_Pos) ///< Noise waveform generation +#define DAC_CR_WAVE2_TRIANGLE (0x02U << DAC_CR_WAVE2_Pos) ///< Triangle wave generation +#define DAC_CR_MAMP2_Pos (24) +#define DAC_CR_MAMP2 (0x0FU << DAC_CR_MAMP2_Pos) ///< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) +#define DAC_CR_MAMP2_1 (0x00U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 1 +#define DAC_CR_MAMP2_3 (0x01U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 3 +#define DAC_CR_MAMP2_7 (0x02U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 7 +#define DAC_CR_MAMP2_15 (0x03U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 15 +#define DAC_CR_MAMP2_31 (0x04U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 31 +#define DAC_CR_MAMP2_63 (0x05U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 63 +#define DAC_CR_MAMP2_127 (0x06U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 127 +#define DAC_CR_MAMP2_255 (0x07U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 255 +#define DAC_CR_MAMP2_511 (0x08U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 511 +#define DAC_CR_MAMP2_1023 (0x09U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 1023 +#define DAC_CR_MAMP2_2047 (0x0AU << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 2047 +#define DAC_CR_MAMP2_4095 (0x0BU << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 4095 +#define DAC_CR_DMAEN2_Pos (28) +#define DAC_CR_DMAEN2 (0x01U << DAC_CR_DMAEN2_Pos) ///< DAC channel2 DMA enabled + +//////////////////////////////////////////////////////////////////////////////// +/// @brief DAC_SWTRIGR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define DAC_SWTRIGR_SWTRIG1_Pos (0) +#define DAC_SWTRIGR_SWTRIG1 (0x01U << DAC_SWTRIGR_SWTRIG1_Pos) ///< DAC channel1 software trigger +#define DAC_SWTRIGR_SWTRIG2_Pos (1) +#define DAC_SWTRIGR_SWTRIG2 (0x01U << DAC_SWTRIGR_SWTRIG2_Pos) ///< DAC channel2 software trigger +#define DAC_SWTRIGR_DACPRE_Pos (8) +#define DAC_SWTRIGR_DACPRE (0x7FU << DAC_SWTRIGR_DACPRE_Pos) ///< DAC prescale + +//////////////////////////////////////////////////////////////////////////////// +/// @brief DAC_DHR12R1 Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define DAC_DHR12R1_DACC1DHR_Pos (0) +#define DAC_DHR12R1_DACC1DHR (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) ///< DAC channel1 12-bit Right align data + +//////////////////////////////////////////////////////////////////////////////// +/// @brief DAC_DHR12L1 Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define DAC_DHR12L1_DACC1DHR_Pos (4) +#define DAC_DHR12L1_DACC1DHR (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) ///< DAC channel1 12-bit Left align data + +//////////////////////////////////////////////////////////////////////////////// +/// @brief DAC_DHR8R1 Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define DAC_DHR8R1_DACC1DHR_Pos (0) +#define DAC_DHR8R1_DACC1DHR (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) ///< DAC channel1 8-bit Right align data + +//////////////////////////////////////////////////////////////////////////////// +/// @brief DAC_DHR12R2 Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define DAC_DHR12R2_DACC2DHR_Pos (0) +#define DAC_DHR12R2_DACC2DHR (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) ///< DAC channel2 12-bit Right align data + +//////////////////////////////////////////////////////////////////////////////// +/// @brief DAC_DHR12L2 Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define DAC_DHR12L2_DACC2DHR_Pos (4) +#define DAC_DHR12L2_DACC2DHR (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) ///< DAC channel2 12-bit Left align data + +//////////////////////////////////////////////////////////////////////////////// +/// @brief DAC_DHR8R2 Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define DAC_DHR8R2_DACC2DHR_Pos (0) +#define DAC_DHR8R2_DACC2DHR (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) ///< DAC channel2 8-bit Right align data + +//////////////////////////////////////////////////////////////////////////////// +/// @brief DAC_DHR12RD Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define DAC_DHR12RD_DACC1DHR_Pos (0) +#define DAC_DHR12RD_DACC1DHR (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) ///< DAC channel1 12-bit Right align data +#define DAC_DHR12RD_DACC2DHR_Pos (16) +#define DAC_DHR12RD_DACC2DHR (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) ///< DAC channel2 12-bit Right align data + +//////////////////////////////////////////////////////////////////////////////// +/// @brief DAC_DHR12LD Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define DAC_DHR12LD_DACC1DHR_Pos (4) +#define DAC_DHR12LD_DACC1DHR (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) ///< DAC channel1 12-bit Right align data +#define DAC_DHR12LD_DACC2DHR_Pos (20) +#define DAC_DHR12LD_DACC2DHR (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) ///< DAC channel2 12-bit Right align data + +//////////////////////////////////////////////////////////////////////////////// +/// @brief DAC_DHR8RD Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define DAC_DHR8RD_DACC1DHR_Pos (0) +#define DAC_DHR8RD_DACC1DHR (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) ///< DAC channel1 8-bit Right align data +#define DAC_DHR8RD_DACC2DHR_Pos (8) +#define DAC_DHR8RD_DACC2DHR (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) ///< DAC channel2 8-bit Right align data + +//////////////////////////////////////////////////////////////////////////////// +/// @brief DAC_DOR1 Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define DAC_DOR1_DACC1DOR_Pos (0) +#define DAC_DOR1_DACC1DOR (0xFFFU << DAC_DOR1_DACC1DOR_Pos) ///< DAC channel1 data output + +//////////////////////////////////////////////////////////////////////////////// +/// @brief DAC_DOR2 Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define DAC_DOR2_DACC2DOR_Pos (0) +#define DAC_DOR2_DACC2DOR (0xFFFU << DAC_DOR2_DACC2DOR_Pos) ///< DAC channel2 data output #endif + + + + + +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +#endif +//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dbg.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dbg.h new file mode 100644 index 000000000..5e378753e --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dbg.h @@ -0,0 +1,113 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file reg_dbg.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF +/// MM32 FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion + +#ifndef __REG_DBG_H +#define __REG_DBG_H + +// Files includes + +#include +#include +#include "types.h" + + + + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + + + + + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief DBG Base Address Definition +//////////////////////////////////////////////////////////////////////////////// + +#define DBG_BASE (0x40007080UL) ///< Base Address: 0x40007080 +//////////////////////////////////////////////////////////////////////////////// +/// @brief DEBUG Registers Structure Definition +//////////////////////////////////////////////////////////////////////////////// +typedef struct { + __IO u32 IDCODE; ///< Code ID offset: 0x00 + __IO u32 CR; ///< Control Register offset: 0x04 +} DBGMCU_TypeDef; + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief DBGMCU type pointer Definition +//////////////////////////////////////////////////////////////////////////////// +#define DBGMCU ((DBGMCU_TypeDef*) DBG_BASE) + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief DBGMCU_IDCODE Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define DBGMCU_IDCODE_DEV_ID_Pos (0) +#define DBGMCU_IDCODE_DEV_ID (0xFFFFFFFFU << DBGMCU_IDCODE_DEV_ID_Pos) ///< Device identifier + +//////////////////////////////////////////////////////////////////////////////// +/// @brief DBGMCU_CR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define DBGMCU_CR_SLEEP_Pos (0) +#define DBGMCU_CR_SLEEP (0x01U << DBGMCU_CR_SLEEP_Pos) ///< Debug Sleep mode +#define DBGMCU_CR_STOP_Pos (1) +#define DBGMCU_CR_STOP (0x01U << DBGMCU_CR_STOP_Pos) ///< Debug Stop mode +#define DBGMCU_CR_STANDBY_Pos (2) +#define DBGMCU_CR_STANDBY (0x01U << DBGMCU_CR_STANDBY_Pos) ///< Debug Standby mode +#define DBGMCU_CR_TRACE_IOEN_Pos (5) +#define DBGMCU_CR_TRACE_IOEN (0x01U << DBGMCU_CR_TRACE_IOEN_Pos) ///< Trace pin assignment +#define DBGMCU_CR_TRACE_MODE_Pos (6) +#define DBGMCU_CR_TRACE_MODE_Msk (0x03U << DBGMCU_CR_TRACE_MODE_Pos) ///< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) +#define DBGMCU_CR_TRACE_MODE_0 (0x01U << DBGMCU_CR_TRACE_MODE_Pos) ///< Bit 0 +#define DBGMCU_CR_TRACE_MODE_1 (0x02U << DBGMCU_CR_TRACE_MODE_Pos) ///< Bit 1 +#define DBGMCU_CR_TRACE_MODE_ASYNC (0x00U << DBGMCU_CR_TRACE_MODE_Pos) ///< Tracking pin uses asynchronous mode +#define DBGMCU_CR_TRACE_MODE_SYNC1 (0x01U << DBGMCU_CR_TRACE_MODE_Pos) ///< The trace pin uses synchronous mode, and the data length is 1 +#define DBGMCU_CR_TRACE_MODE_SYNC2 (0x02U << DBGMCU_CR_TRACE_MODE_Pos) ///< The trace pin uses synchronous mode, and the data length is 2 + +#define DBGMCU_CR_IWDG_STOP_Pos (8) +#define DBGMCU_CR_IWDG_STOP (0x01U << DBGMCU_CR_IWDG_STOP_Pos) ///< Debug independent watchdog stopped when core is halted +#define DBGMCU_CR_WWDG_STOP_Pos (9) +#define DBGMCU_CR_WWDG_STOP (0x01U << DBGMCU_CR_WWDG_STOP_Pos) ///< Debug window watchdog stopped when core is halted +#define DBGMCU_CR_TIM_STOP_Pos (10) +#define DBGMCU_CR_TIM1_STOP (0x01U << DBGMCU_CR_TIM_STOP_Pos) ///< TIM1 counter stopped when core is halted +#define DBGMCU_CR_TIM2_STOP (0x02U << DBGMCU_CR_TIM_STOP_Pos) ///< TIM2 counter stopped when core is halted +#define DBGMCU_CR_TIM3_STOP (0x04U << DBGMCU_CR_TIM_STOP_Pos) ///< TIM3 counter stopped when core is halted +#define DBGMCU_CR_TIM4_STOP (0x08U << DBGMCU_CR_TIM_STOP_Pos) ///< TIM4 counter stopped when core is halted + + + + + +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +#endif +//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dma.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dma.h new file mode 100644 index 000000000..ffcba5654 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dma.h @@ -0,0 +1,325 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file reg_dma.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF +/// MM32 FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion + +#ifndef __REG_DMA_H +#define __REG_DMA_H + +// Files includes + +#include +#include +#include "types.h" + + + + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + + + + + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief DMA Base Address Definition +//////////////////////////////////////////////////////////////////////////////// +#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) ///< Base Address: 0x40020000 +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) ///< Base Address: 0x40020008 +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) ///< Base Address: 0x4002001C +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) ///< Base Address: 0x40020030 +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) ///< Base Address: 0x40020044 +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) ///< Base Address: 0x40020058 + +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) ///< Base Address: 0x4002006C +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) ///< Base Address: 0x40020080 +#define DMA2_BASE (AHBPERIPH_BASE + 0x0400) ///< Base Address: 0x40020400 +#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) ///< Base Address: 0x40020408 +#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) ///< Base Address: 0x4002041C +#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) ///< Base Address: 0x40020430 +#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) ///< Base Address: 0x40020444 +#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) ///< Base Address: 0x40020458 + +//////////////////////////////////////////////////////////////////////////////// +/// @brief DMA Register Structure Definition +//////////////////////////////////////////////////////////////////////////////// +typedef struct { + __IO u32 CCR; ///< DMA channel x configuration register offset: 0x00 + __IO u32 CNDTR; ///< DMA channel x number of data register offset: 0x04 + __IO u32 CPAR; ///< DMA channel x peripheral address register offset: 0x08 + __IO u32 CMAR; ///< DMA channel x memory address register offset: 0x0C +} DMA_Channel_TypeDef; + +typedef struct { + __IO u32 ISR; ///< Interrupt Status Register offset: 0x00 + __IO u32 IFCR; ///< Interrupt Flag Clear Register offset: 0x04 + __IO u32 CCRx; ///< Channel X configures registers offset: 0x08 + __IO u32 CNDTRx; ///< Channel X transfer quantity register offset: 0x0C + __IO u32 CPARx; ///< Channel X peripheral address register offset: 0x10 + __IO u32 CMARx; ///< Channel X memory address register offset: 0x14 +} DMA_TypeDef; + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief DMA type pointer Definition +//////////////////////////////////////////////////////////////////////////////// +#define DMA1 ((DMA_TypeDef*) DMA1_BASE) +#define DMA1_ch1 ((DMA_Channel_TypeDef*) DMA1_Channel1_BASE) +#define DMA1_ch2 ((DMA_Channel_TypeDef*) DMA1_Channel2_BASE) +#define DMA1_ch3 ((DMA_Channel_TypeDef*) DMA1_Channel3_BASE) +#define DMA1_ch4 ((DMA_Channel_TypeDef*) DMA1_Channel4_BASE) +#define DMA1_ch5 ((DMA_Channel_TypeDef*) DMA1_Channel5_BASE) + +#define DMA1_Channel1 ((DMA_Channel_TypeDef*) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef*) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef*) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef*) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef*) DMA1_Channel5_BASE) + + +#define DMA1_ch6 ((DMA_Channel_TypeDef*) DMA1_Channel6_BASE) +#define DMA1_ch7 ((DMA_Channel_TypeDef*) DMA1_Channel7_BASE) + +#define DMA1_Channel6 ((DMA_Channel_TypeDef*) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef*) DMA1_Channel7_BASE) + +#define DMA2 ((DMA_TypeDef*) DMA2_BASE) +#define DMA2_ch1 ((DMA_Channel_TypeDef*) DMA2_Channel1_BASE) +#define DMA2_ch2 ((DMA_Channel_TypeDef*) DMA2_Channel2_BASE) +#define DMA2_ch3 ((DMA_Channel_TypeDef*) DMA2_Channel3_BASE) +#define DMA2_ch4 ((DMA_Channel_TypeDef*) DMA2_Channel4_BASE) +#define DMA2_ch5 ((DMA_Channel_TypeDef*) DMA2_Channel5_BASE) +#define DMA2_Channel1 ((DMA_Channel_TypeDef*) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef*) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef*) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef*) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef*) DMA2_Channel5_BASE) + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief DMA_ISR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define DMA_ISR_GIF1_Pos (0) +#define DMA_ISR_GIF1 (0x01U << DMA_ISR_GIF1_Pos) ///< Channel 1 Global interrupt flag +#define DMA_ISR_TCIF1_Pos (1) +#define DMA_ISR_TCIF1 (0x01U << DMA_ISR_TCIF1_Pos) ///< Channel 1 Transfer Complete flag +#define DMA_ISR_HTIF1_Pos (2) +#define DMA_ISR_HTIF1 (0x01U << DMA_ISR_HTIF1_Pos) ///< Channel 1 Half Transfer flag +#define DMA_ISR_TEIF1_Pos (3) +#define DMA_ISR_TEIF1 (0x01U << DMA_ISR_TEIF1_Pos) ///< Channel 1 Transfer Error flag +#define DMA_ISR_GIF2_Pos (4) +#define DMA_ISR_GIF2 (0x01U << DMA_ISR_GIF2_Pos) ///< Channel 2 Global interrupt flag +#define DMA_ISR_TCIF2_Pos (5) +#define DMA_ISR_TCIF2 (0x01U << DMA_ISR_TCIF2_Pos) ///< Channel 2 Transfer Complete flag +#define DMA_ISR_HTIF2_Pos (6) +#define DMA_ISR_HTIF2 (0x01U << DMA_ISR_HTIF2_Pos) ///< Channel 2 Half Transfer flag +#define DMA_ISR_TEIF2_Pos (7) +#define DMA_ISR_TEIF2 (0x01U << DMA_ISR_TEIF2_Pos) ///< Channel 2 Transfer Error flag +#define DMA_ISR_GIF3_Pos (8) +#define DMA_ISR_GIF3 (0x01U << DMA_ISR_GIF3_Pos) ///< Channel 3 Global interrupt flag +#define DMA_ISR_TCIF3_Pos (9) +#define DMA_ISR_TCIF3 (0x01U << DMA_ISR_TCIF3_Pos) ///< Channel 3 Transfer Complete flag +#define DMA_ISR_HTIF3_Pos (10) +#define DMA_ISR_HTIF3 (0x01U << DMA_ISR_HTIF3_Pos) ///< Channel 3 Half Transfer flag +#define DMA_ISR_TEIF3_Pos (11) +#define DMA_ISR_TEIF3 (0x01U << DMA_ISR_TEIF3_Pos) ///< Channel 3 Transfer Error flag +#define DMA_ISR_GIF4_Pos (12) +#define DMA_ISR_GIF4 (0x01U << DMA_ISR_GIF4_Pos) ///< Channel 4 Global interrupt flag +#define DMA_ISR_TCIF4_Pos (13) +#define DMA_ISR_TCIF4 (0x01U << DMA_ISR_TCIF4_Pos) ///< Channel 4 Transfer Complete flag +#define DMA_ISR_HTIF4_Pos (14) +#define DMA_ISR_HTIF4 (0x01U << DMA_ISR_HTIF4_Pos) ///< Channel 4 Half Transfer flag +#define DMA_ISR_TEIF4_Pos (15) +#define DMA_ISR_TEIF4 (0x01U << DMA_ISR_TEIF4_Pos) ///< Channel 4 Transfer Error flag +#define DMA_ISR_GIF5_Pos (16) +#define DMA_ISR_GIF5 (0x01U << DMA_ISR_GIF5_Pos) ///< Channel 5 Global interrupt flag +#define DMA_ISR_TCIF5_Pos (17) +#define DMA_ISR_TCIF5 (0x01U << DMA_ISR_TCIF5_Pos) ///< Channel 5 Transfer Complete flag +#define DMA_ISR_HTIF5_Pos (18) +#define DMA_ISR_HTIF5 (0x01U << DMA_ISR_HTIF5_Pos) ///< Channel 5 Half Transfer flag +#define DMA_ISR_TEIF5_Pos (19) +#define DMA_ISR_TEIF5 (0x01U << DMA_ISR_TEIF5_Pos) ///< Channel 5 Transfer Error flag + +#define DMA_ISR_GIF6_Pos (20) +#define DMA_ISR_GIF6 (0x01U << DMA_ISR_GIF6_Pos) ///< Channel 6 Global interrupt flag +#define DMA_ISR_TCIF6_Pos (21) +#define DMA_ISR_TCIF6 (0x01U << DMA_ISR_TCIF6_Pos) ///< Channel 6 Transfer Complete flag +#define DMA_ISR_HTIF6_Pos (22) +#define DMA_ISR_HTIF6 (0x01U << DMA_ISR_HTIF6_Pos) ///< Channel 6 Half Transfer flag +#define DMA_ISR_TEIF6_Pos (23) +#define DMA_ISR_TEIF6 (0x01U << DMA_ISR_TEIF6_Pos) ///< Channel 6 Transfer Error flag +#define DMA_ISR_GIF7_Pos (24) +#define DMA_ISR_GIF7 (0x01U << DMA_ISR_GIF7_Pos) ///< Channel 7 Global interrupt flag +#define DMA_ISR_TCIF7_Pos (25) +#define DMA_ISR_TCIF7 (0x01U << DMA_ISR_TCIF7_Pos) ///< Channel 7 Transfer Complete flag +#define DMA_ISR_HTIF7_Pos (26) +#define DMA_ISR_HTIF7 (0x01U << DMA_ISR_HTIF7_Pos) ///< Channel 7 Half Transfer flag +#define DMA_ISR_TEIF7_Pos (27) +#define DMA_ISR_TEIF7 (0x01U << DMA_ISR_TEIF7_Pos) ///< Channel 7 Transfer Error flag + +//////////////////////////////////////////////////////////////////////////////// +/// @brief DMA_IFCR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define DMA_IFCR_CGIF1_Pos (0) +#define DMA_IFCR_CGIF1 (0x01U << DMA_IFCR_CGIF1_Pos) ///< Channel 1 Global interrupt clearr +#define DMA_IFCR_CTCIF1_Pos (1) +#define DMA_IFCR_CTCIF1 (0x01U << DMA_IFCR_CTCIF1_Pos) ///< Channel 1 Transfer Complete clear +#define DMA_IFCR_CHTIF1_Pos (2) +#define DMA_IFCR_CHTIF1 (0x01U << DMA_IFCR_CHTIF1_Pos) ///< Channel 1 Half Transfer clear +#define DMA_IFCR_CTEIF1_Pos (3) +#define DMA_IFCR_CTEIF1 (0x01U << DMA_IFCR_CTEIF1_Pos) ///< Channel 1 Transfer Error clear +#define DMA_IFCR_CGIF2_Pos (4) +#define DMA_IFCR_CGIF2 (0x01U << DMA_IFCR_CGIF2_Pos) ///< Channel 2 Global interrupt clear +#define DMA_IFCR_CTCIF2_Pos (5) +#define DMA_IFCR_CTCIF2 (0x01U << DMA_IFCR_CTCIF2_Pos) ///< Channel 2 Transfer Complete clear +#define DMA_IFCR_CHTIF2_Pos (6) +#define DMA_IFCR_CHTIF2 (0x01U << DMA_IFCR_CHTIF2_Pos) ///< Channel 2 Half Transfer clear +#define DMA_IFCR_CTEIF2_Pos (7) +#define DMA_IFCR_CTEIF2 (0x01U << DMA_IFCR_CTEIF2_Pos) ///< Channel 2 Transfer Error clear +#define DMA_IFCR_CGIF3_Pos (8) +#define DMA_IFCR_CGIF3 (0x01U << DMA_IFCR_CGIF3_Pos) ///< Channel 3 Global interrupt clear +#define DMA_IFCR_CTCIF3_Pos (9) +#define DMA_IFCR_CTCIF3 (0x01U << DMA_IFCR_CTCIF3_Pos) ///< Channel 3 Transfer Complete clear +#define DMA_IFCR_CHTIF3_Pos (10) +#define DMA_IFCR_CHTIF3 (0x01U << DMA_IFCR_CHTIF3_Pos) ///< Channel 3 Half Transfer clear +#define DMA_IFCR_CTEIF3_Pos (11) +#define DMA_IFCR_CTEIF3 (0x01U << DMA_IFCR_CTEIF3_Pos) ///< Channel 3 Transfer Error clear +#define DMA_IFCR_CGIF4_Pos (12) +#define DMA_IFCR_CGIF4 (0x01U << DMA_IFCR_CGIF4_Pos) ///< Channel 4 Global interrupt clear +#define DMA_IFCR_CTCIF4_Pos (13) +#define DMA_IFCR_CTCIF4 (0x01U << DMA_IFCR_CTCIF4_Pos) ///< Channel 4 Transfer Complete clear +#define DMA_IFCR_CHTIF4_Pos (14) +#define DMA_IFCR_CHTIF4 (0x01U << DMA_IFCR_CHTIF4_Pos) ///< Channel 4 Half Transfer clear +#define DMA_IFCR_CTEIF4_Pos (15) +#define DMA_IFCR_CTEIF4 (0x01U << DMA_IFCR_CTEIF4_Pos) ///< Channel 4 Transfer Error clear +#define DMA_IFCR_CGIF5_Pos (16) +#define DMA_IFCR_CGIF5 (0x01U << DMA_IFCR_CGIF5_Pos) ///< Channel 5 Global interrupt clear +#define DMA_IFCR_CTCIF5_Pos (17) +#define DMA_IFCR_CTCIF5 (0x01U << DMA_IFCR_CTCIF5_Pos) ///< Channel 5 Transfer Complete clear +#define DMA_IFCR_CHTIF5_Pos (18) +#define DMA_IFCR_CHTIF5 (0x01U << DMA_IFCR_CHTIF5_Pos) ///< Channel 5 Half Transfer clear +#define DMA_IFCR_CTEIF5_Pos (19) +#define DMA_IFCR_CTEIF5 (0x01U << DMA_IFCR_CTEIF5_Pos) ///< Channel 5 Transfer Error clear + +#define DMA_IFCR_CGIF6_Pos (20) +#define DMA_IFCR_CGIF6 (0x01U << DMA_IFCR_CGIF6_Pos) ///< Channel 6 Global interrupt clear +#define DMA_IFCR_CTCIF6_Pos (21) +#define DMA_IFCR_CTCIF6 (0x01U << DMA_IFCR_CTCIF6_Pos) ///< Channel 6 Transfer Complete clear +#define DMA_IFCR_CHTIF6_Pos (22) +#define DMA_IFCR_CHTIF6 (0x01U << DMA_IFCR_CHTIF6_Pos) ///< Channel 6 Half Transfer clear +#define DMA_IFCR_CTEIF6_Pos (23) +#define DMA_IFCR_CTEIF6 (0x01U << DMA_IFCR_CTEIF6_Pos) ///< Channel 6 Transfer Error clear +#define DMA_IFCR_CGIF7_Pos (24) +#define DMA_IFCR_CGIF7 (0x01U << DMA_IFCR_CGIF7_Pos) ///< Channel 7 Global interrupt clear +#define DMA_IFCR_CTCIF7_Pos (25) +#define DMA_IFCR_CTCIF7 (0x01U << DMA_IFCR_CTCIF7_Pos) ///< Channel 7 Transfer Complete clear +#define DMA_IFCR_CHTIF7_Pos (26) +#define DMA_IFCR_CHTIF7 (0x01U << DMA_IFCR_CHTIF7_Pos) ///< Channel 7 Half Transfer clear +#define DMA_IFCR_CTEIF7_Pos (27) +#define DMA_IFCR_CTEIF7 (0x01U << DMA_IFCR_CTEIF7_Pos) ///< Channel 7 Transfer Error clear + +//////////////////////////////////////////////////////////////////////////////// +/// @brief DMA_CCR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define DMA_CCR_EN_Pos (0) +#define DMA_CCR_EN (0x01U << DMA_CCR_EN_Pos) ///< Channel enabl +#define DMA_CCR_TCIE_Pos (1) +#define DMA_CCR_TCIE (0x01U << DMA_CCR_TCIE_Pos) ///< Transfer complete interrupt enable +#define DMA_CCR_HTIE_Pos (2) +#define DMA_CCR_HTIE (0x01U << DMA_CCR_HTIE_Pos) ///< Half Transfer interrupt enable +#define DMA_CCR_TEIE_Pos (3) +#define DMA_CCR_TEIE (0x01U << DMA_CCR_TEIE_Pos) ///< Transfer error interrupt enable +#define DMA_CCR_DIR_Pos (4) +#define DMA_CCR_DIR (0x01U << DMA_CCR_DIR_Pos) ///< Data transfer direction +#define DMA_CCR_CIRC_Pos (5) +#define DMA_CCR_CIRC (0x01U << DMA_CCR_CIRC_Pos) ///< Circular mode +#define DMA_CCR_PINC_Pos (6) +#define DMA_CCR_PINC (0x01U << DMA_CCR_PINC_Pos) ///< Peripheral increment mode +#define DMA_CCR_MINC_Pos (7) +#define DMA_CCR_MINC (0x01U << DMA_CCR_MINC_Pos) ///< Memory increment mode + +#define DMA_CCR_PSIZE_Pos (8) +#define DMA_CCR_PSIZE (0x03U << DMA_CCR_PSIZE_Pos) ///< PSIZE[1:0] bits (Peripheral size) +#define DMA_CCR_PSIZE_0 (0x01U << DMA_CCR_PSIZE_Pos) ///< Bit0 +#define DMA_CCR_PSIZE_1 (0x02U << DMA_CCR_PSIZE_Pos) ///< Bit1 + +#define DMA_CCR_PSIZE_BYTE (0x00U << DMA_CCR_PSIZE_Pos) ///< DMA Peripheral Data Size Byte +#define DMA_CCR_PSIZE_HALFWORD (0x01U << DMA_CCR_PSIZE_Pos) ///< DMA Peripheral Data Size HalfWord +#define DMA_CCR_PSIZE_WORD (0x02U << DMA_CCR_PSIZE_Pos) ///< DMA Peripheral Data Size Word + +#define DMA_CCR_MSIZE_Pos (10) +#define DMA_CCR_MSIZE (0x03U << DMA_CCR_MSIZE_Pos) ///< MSIZE[1:0] bits (Memory size) +#define DMA_CCR_MSIZE_0 (0x01U << DMA_CCR_MSIZE_Pos) ///< Bit0 +#define DMA_CCR_MSIZE_1 (0x02U << DMA_CCR_MSIZE_Pos) ///< Bit1 + +#define DMA_CCR_MSIZE_BYTE (0x00U << DMA_CCR_MSIZE_Pos) ///< DMA Memory Data Size Byte +#define DMA_CCR_MSIZE_HALFWORD (0x01U << DMA_CCR_MSIZE_Pos) ///< DMA Memory Data Size HalfWord +#define DMA_CCR_MSIZE_WORD (0x02U << DMA_CCR_MSIZE_Pos) ///< DMA Memory Data Size Word + +#define DMA_CCR_PL_Pos (12) +#define DMA_CCR_PL (0x03U << DMA_CCR_PL_Pos) ///< PL[1:0] bits(Channel Priority level) +#define DMA_CCR_PL_0 (0x01U << DMA_CCR_PL_Pos) ///< Bit0 +#define DMA_CCR_PL_1 (0x02U << DMA_CCR_PL_Pos) ///< Bit1 + +#define DMA_CCR_PL_Low (0x00U << DMA_CCR_PL_Pos) ///< DMA Priority Low +#define DMA_CCR_PL_Medium (0x01U << DMA_CCR_PL_Pos) ///< DMA Priority Medium +#define DMA_CCR_PL_High (0x02U << DMA_CCR_PL_Pos) ///< DMA Priority High +#define DMA_CCR_PL_VeryHigh (0x03U << DMA_CCR_PL_Pos) ///< DMA Priority VeryHigh +#define DMA_CCR_M2M_Pos (14) +#define DMA_CCR_M2M (0x01U << DMA_CCR_M2M_Pos) ///< Memory to memory mode + +#define DMA_CCR_ARE_Pos (15) +#define DMA_CCR_ARE (0x01U << DMA_CCR_ARE_Pos) ///< Auto-Reload Enable bit + +//////////////////////////////////////////////////////////////////////////////// +/// @brief DMA_CNDTR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define DMA_CNDTR_NDT_Pos (0) +#define DMA_CNDTR_NDT (0xFFFFU << DMA_CNDTR_NDT_Pos) ///< Number of data to Transfer + +//////////////////////////////////////////////////////////////////////////////// +/// @brief DMA_CPAR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define DMA_CPAR_PA_Pos (0) +#define DMA_CPAR_PA (0xFFFFFFFFU << DMA_CPAR_PA_Pos) ///< Peripheral Address + +//////////////////////////////////////////////////////////////////////////////// +/// @brief DMA_CMAR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define DMA_CMAR_MA_Pos (0) +#define DMA_CMAR_MA (0xFFFFFFFFU << DMA_CMAR_MA_Pos) ///< Peripheral Address + + + + + +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +#endif +//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_eth.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_eth.h new file mode 100644 index 000000000..61a0d25c2 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_eth.h @@ -0,0 +1,730 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file reg_iwdg.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF +/// MM32 FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion + +#ifndef __REG_ETH_H +#define __REG_ETH_H + +// Files includes + +#include +#include +#include "types.h" + +#include "reg_common.h" + + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +//////////////////////////////////////////////////////////////////////////////// +/// @brief IWDG Base Address Definition +//////////////////////////////////////////////////////////////////////////////// +#define ETH_BASE (AHBPERIPH_BASE + 0x8000) ///< Base Address: 0x40028000 + + +#define ETH ((ETH_TypeDef*) ETH_BASE) +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH Register Structure Definition +//////////////////////////////////////////////////////////////////////////////// +typedef struct { + __IO u32 MACCR; ///< configuration register offset 0x0000 + __IO u32 MACFFR; ///< frame filter register offset 0x0004 + __IO u32 MACHTHR; ///< Hash list high register offset 0x0008 + __IO u32 MACHTLR; ///< Hash list low register offset 0x000C + __IO u32 MACMIIAR; ///< MII address register offset 0x0010 + __IO u32 MACMIIDR; ///< MII data register offset 0x0014 + __IO u32 MACFCR; ///< flow control register offset 0x0018 + __IO u32 MACVLANTR; ///< VLAN label register offset 0x001C + __IO u32 RESERVEDX0020[2]; /// 0x0020 ~ 0x0024 + __IO u32 MACRWUFFR; /// 0x0028 + __IO u32 MACPMTCSR; /// 0x002C + __IO u32 RESERVEDX0030[4]; /// 0x0030 ~ 0x003C + __IO u32 MACA0HR; ///< address 0 high register offset 0x0040 + __IO u32 MACA0LR; ///< address 0 low register offset 0x0044 + __IO u32 MACA1HR; ///< address 1 high register offset 0x0048 + __IO u32 MACA1LR; ///< address 1 low register offset 0x004C + __IO u32 MACA2HR; ///< address 2 high register offset 0x0050 + __IO u32 MACA2LR; ///< address 2 low register offset 0x0054 + __IO u32 MACA3HR; ///< address 3 high register offset 0x0058 + __IO u32 MACA3LR; ///< address 3 low register offset 0x005C + __IO u32 MACA4HR; ///< address 4 high register offset 0x0060 + __IO u32 MACA4LR; ///< address 4 low register offset 0x0064 + __IO u32 MACA5HR; ///< address 5 high register offset 0x0068 + __IO u32 MACA5LR; ///< address 5 low register offset 0x006C + __IO u32 MACA6HR; ///< address 6 high register offset 0x0070 + __IO u32 MACA6LR; ///< address 6 low register offset 0x0074 + __IO u32 MACA7HR; ///< address 7 high register offset 0x0078 + __IO u32 MACA7LR; ///< address 7 low register offset 0x007C + __IO u32 MACA8HR; ///< address 8 high register offset 0x0080 + __IO u32 MACA8LR; ///< address 8 low register offset 0x0084 + __IO u32 MACA9HR; ///< address 9 high register offset 0x0088 + __IO u32 MACA9LR; ///< address 9 low register offset 0x008C + __IO u32 MACA10HR; ///< address 10 high register offset 0x0090 + __IO u32 MACA10LR; ///< address 10 low register offset 0x0094 + __IO u32 MACA11HR; ///< address 11 high register offset 0x0098 + __IO u32 MACA11LR; ///< address 11 low register offset 0x009C + __IO u32 MACA12HR; ///< address 12 high register offset 0x00A0 + __IO u32 MACA12LR; ///< address 12 low register offset 0x00A4 + __IO u32 MACA13HR; ///< address 13 high register offset 0x00A8 + __IO u32 MACA13LR; ///< address 13 low register offset 0x00AC + __IO u32 MACA14HR; ///< address 14 high register offset 0x00B0 + __IO u32 MACA14LR; ///< address 14 low register offset 0x00B4 + __IO u32 MACA15HR; ///< address 15 high register offset 0x00B8 + __IO u32 MACA15LR; ///< address 15 low register offset 0x00BC + __IO u32 MACANCR; ///< Automatic negotiation control register offset 0x00C0 + __IO u32 MACANSR; ///< Automatic negotiation of the status register offset 0x00C4 + __IO u32 MACANAR; ///< Automatic negotiation of broadcast registers offset 0x00C8 + __IO u32 MACANLPAR; ///< Automatic negotiation of link partner capability register offset 0x00CC + __IO u32 MACANER; ///< Automatic negotiation of extension registers offset 0x00D0 + __IO u32 MACTBIER; ///< Ten - place interface extension register offset 0x00D4 + __IO u32 MACMIISR; ///< MII status register offset 0x00D8 + __IO u32 RESERVEDX00DC[9]; ///< offset 0x00DC ~ 0x00FC + __IO u32 MMCCR; ///< MMC controls registers offset 0x0100 + __IO u32 MMCRIR; ///< The MMC receives the interrupt register offset 0x0104 + __IO u32 MMCTIR; ///< The MMC sends the interrupt register offset 0x0108 + __IO u32 MMCRIMR; ///< The MMC receives the interrupt mask register offset 0x010C + __IO u32 MMCTIMR; ///< MMC sends interrupt masking registers offset 0x0110 + __IO u32 RESERVEDX0114[14]; ///< offset 0x0114 ~ 0x0148 + __IO u32 MMCTGFSCCR; ///< A good frame counter register that MMC sends after a single conflict offset 0x014C + __IO u32 MMCTGFMSCCR; ///< A good frame counter register that MMC sends after multiple collisions offset 0x0150 + __IO u32 RESERVEDX0154[5]; ///< offset 0x0154 ~ 0x0164 + __IO u32 MMCTGFCR; ///< Good frame counter register sent by MMC offset 0x0168 + __IO u32 RESERVEDX016C[10]; ///< offset 0x016C ~ 0x0190 + __IO u32 MMCRFCECR; ///< Ethernet MMC with CRC error counter register receives frame register offset 0x0194 + __IO u32 MMCRFAECR; ///< Ethernet MMC receives frames with alignment error counter registers offset 0x0198 + __IO u32 RESERVEDX019C[10]; ///< offset 0x019C ~ 0x01C0 + __IO u32 MMCRGUFCR; ///< Good unicast frame counter register received by MMC offset 0x01C4 + __IO u32 RESERVEDx01C8[910]; ///< offset 0x01C8 ~ 0x0FFC + __IO u32 DMABMR; ///< Bus mode register offset 0x1000 + __IO u32 DMATPDR; ///< DMA sends the polling request register offset 0x1004 + __IO u32 DMARPDR; ///< DMA receives the polling request register offset 0x1008 + __IO u32 DMARDLAR; ///< DMA receives a list of descriptor addresses offset 0x100C + __IO u32 DMATDLAR; ///< DMA sends the descriptor list address offset 0x1010 + __IO u32 DMASR; ///< DMA status register offset 0x1014 + __IO u32 DMAOMR; ///< DMA working mode register offset 0x1018 + __IO u32 DMAIER; ///< DMA interrupt enablement register offset 0x101C + __IO u32 DMAMFBOCR; ///< DMA lost frames and cache overflow counter registers offset 0x1020 + __IO u32 DMARSWTR; /// 0x1024 + __IO u32 RESERVEDX1028[8]; /// 0x1028 ~ 0x1044 + __IO u32 DMACHTDR; /// 0x1048 + __IO u32 DMACHRDR; /// 0x104C + __IO u32 DMACHTBAR; ///< DMA is currently sending the cache address register offset 0x1050 + __IO u32 DMACHRBAR; ///< DMA currently receives the cache address register offset 0x1054 +} ETH_TypeDef; + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH_MACCR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define ETH_MACCR_WD_Pos (23) +#define ETH_MACCR_WD (0x01U << ETH_MACCR_WD_Pos) ///< Watchdog disable +#define ETH_MACCR_JD_Pos (22) +#define ETH_MACCR_JD (0x01U << ETH_MACCR_JD_Pos) ///< Jabber disable +#define ETH_MACCR_FBE_Pos (21) +#define ETH_MACCR_FBE (0x01U << ETH_MACCR_FBE_Pos) ///< Frame Burst Enable +#define ETH_MACCR_JE_Pos (20) +#define ETH_MACCR_JE (0x01U << ETH_MACCR_JE_Pos) ///< Jumbo Frame Enable +#define ETH_MACCR_IFG_Pos (17) ///< Inter-frame gap +#define ETH_MACCR_IFG_96Bit (0x00U << ETH_MACCR_IFG_Pos) ///< Minimum IFG between frames during transmission is 96Bit +#define ETH_MACCR_IFG_88Bit (0x01U << ETH_MACCR_IFG_Pos) ///< Minimum IFG between frames during transmission is 88Bit +#define ETH_MACCR_IFG_80Bit (0x02U << ETH_MACCR_IFG_Pos) ///< Minimum IFG between frames during transmission is 80Bit +#define ETH_MACCR_IFG_72Bit (0x03U << ETH_MACCR_IFG_Pos) ///< Minimum IFG between frames during transmission is 72Bit +#define ETH_MACCR_IFG_64Bit (0x04U << ETH_MACCR_IFG_Pos) ///< Minimum IFG between frames during transmission is 64Bit +#define ETH_MACCR_IFG_56Bit (0x05U << ETH_MACCR_IFG_Pos) ///< Minimum IFG between frames during transmission is 56Bit +#define ETH_MACCR_IFG_48Bit (0x06U << ETH_MACCR_IFG_Pos) ///< Minimum IFG between frames during transmission is 48Bit +#define ETH_MACCR_IFG_40Bit (0x07U << ETH_MACCR_IFG_Pos) ///< Minimum IFG between frames during transmission is 40Bit +#define ETH_MACCR_FES_Pos (14) +#define ETH_MACCR_FES (0x01U << ETH_MACCR_FES_Pos) ///< Fast ethernet speed +#define ETH_MACCR_ROD_Pos (13) +#define ETH_MACCR_ROD (0x01U << ETH_MACCR_ROD_Pos) ///< Receive own disable +#define ETH_MACCR_LM_Pos (12) +#define ETH_MACCR_LM (0x01U << ETH_MACCR_LM_Pos) ///< loopback mode +#define ETH_MACCR_DM_Pos (11) +#define ETH_MACCR_DM (0x01U << ETH_MACCR_DM_Pos) ///< Duplex mode +#define ETH_MACCR_IPCO_Pos (10) +#define ETH_MACCR_IPCO (0x01U << ETH_MACCR_IPCO_Pos) ///< IP Checksum offload +#define ETH_MACCR_RD_Pos (9) +#define ETH_MACCR_RD (0x01U << ETH_MACCR_RD_Pos) ///< Retry disable +#define ETH_MACCR_APCS_Pos (8) +#define ETH_MACCR_APCS (0x01U << ETH_MACCR_APCS_Pos) ///< Automatic Pad/CRC stripping +#define ETH_MACCR_BL_Pos (5) ///< Back-off limit: random integer number (r) of slot time delays before rescheduling a transmission attempt during retries after a collision: 0 =< r <2^k +#define ETH_MACCR_BL_10 (0x00U << ETH_MACCR_BL_Pos) ///< k = min (n, 10) +#define ETH_MACCR_BL_8 (0x01U << ETH_MACCR_BL_Pos) ///< k = min (n, 8) +#define ETH_MACCR_BL_4 (0x02U << ETH_MACCR_BL_Pos) ///< k = min (n, 4) +#define ETH_MACCR_BL_1 (0x03U << ETH_MACCR_BL_Pos) ///< k = min (n, 1) +#define ETH_MACCR_DC_Pos (4) +#define ETH_MACCR_DC (0x01U << ETH_MACCR_DC_Pos) ///< Defferal check +#define ETH_MACCR_TE_Pos (3) +#define ETH_MACCR_TE (0x01U << ETH_MACCR_TE_Pos) ///< Transmitter enable +#define ETH_MACCR_RE_Pos (2) +#define ETH_MACCR_RE (0x01U << ETH_MACCR_RE_Pos) ///< Receiver enable +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH_MACFFR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define ETH_MACFFR_RA_Pos (31) +#define ETH_MACFFR_RA (0x01U << ETH_MACFFR_RA_Pos) ///< Receive all + +#define ETH_MACFFR_SAF_Pos (9) +#define ETH_MACFFR_SAF (0x01U << ETH_MACFFR_SAF_Pos) ///< Source address filter enable +#define ETH_MACFFR_SAIF_Pos (8) +#define ETH_MACFFR_SAIF (0x01U << ETH_MACFFR_SAIF_Pos) ///< SA inverse filtering +#define ETH_MACFFR_PCF_Pos (6) +#define ETH_MACFFR_PCF (0x03U << ETH_MACFFR_PCF_Pos) ///< Pass control frames: 3 cases +#define ETH_MACFFR_PCF_BlockAll (0x01U << ETH_MACFFR_PCF_Pos) ///< MAC filters all control frames from reaching the application +#define ETH_MACFFR_PCF_ForwardAll (0x02U << ETH_MACFFR_PCF_Pos) ///< MAC forwards all control frames to application even if they fail the Address Filter +#define ETH_MACFFR_PCF_ForwardPassedAddrFilter (0x03U << ETH_MACFFR_PCF_Pos) ///< MAC forwards control frames that pass the Address Filter. +#define ETH_MACFFR_BFD_Pos (5) +#define ETH_MACFFR_BFD (0x01U << ETH_MACFFR_BFD_Pos) ///< Broadcast frame disable +#define ETH_MACFFR_PAM_Pos (4) +#define ETH_MACFFR_PAM (0x01U << ETH_MACFFR_PAM_Pos) ///< Pass all mutlicast +#define ETH_MACFFR_DAIF_Pos (3) +#define ETH_MACFFR_DAIF (0x01U << ETH_MACFFR_DAIF_Pos) ///< DA Inverse filtering +#define ETH_MACFFR_HM_Pos (2) +#define ETH_MACFFR_HM (0x01U << ETH_MACFFR_HM_Pos) ///< Hash multicast +#define ETH_MACFFR_HU_Pos (1) +#define ETH_MACFFR_HU (0x01U << ETH_MACFFR_HU_Pos) ///< Hash unicast +#define ETH_MACFFR_PM_Pos (0) +#define ETH_MACFFR_PM (0x01U << ETH_MACFFR_PM_Pos) ///< Promiscuous mode + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH_MACHTHR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define ETH_MACHTHR_HTH (0xFFFFFFFFU) ///< Hash table high + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH_MACHTLR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define ETH_MACHTLR_HTL (0xFFFFFFFFU) ///< Hash table low + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH_MACMIIAR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define ETH_MACMIIAR_PA_Pos (11) +#define ETH_MACMIIAR_PA (0x1FU << ETH_MACMIIAR_PA_Pos) ///< Physical layer address +#define ETH_MACMIIAR_MR_Pos (6) +#define ETH_MACMIIAR_MR (0x1FU << ETH_MACMIIAR_MR_Pos) ///< MII register in the selected PHY +#define ETH_MACMIIAR_CR_Pos (2) +#define ETH_MACMIIAR_CR (0x07U << ETH_MACMIIAR_CR_Pos) ///< CR clock range: 6 cases +#define ETH_MACMIIAR_CR_Div42 (0x00U << ETH_MACMIIAR_CR_Pos) ///< HCLK:60-100 MHz; MDC clock= HCLK/42 +#define ETH_MACMIIAR_CR_Div62 (0x01U << ETH_MACMIIAR_CR_Pos) ///< HCLK:100-150 MHz; MDC clock= HCLK/62 +#define ETH_MACMIIAR_CR_Div16 (0x02U << ETH_MACMIIAR_CR_Pos) ///< HCLK:20-35 MHz; MDC clock= HCLK/16 +#define ETH_MACMIIAR_CR_Div26 (0x03U << ETH_MACMIIAR_CR_Pos) ///< HCLK:35-60 MHz; MDC clock= HCLK/26 +#define ETH_MACMIIAR_CR_Div102 (0x04U << ETH_MACMIIAR_CR_Pos) ///< HCLK:150-168 MHz; MDC clock= HCLK/102 +#define ETH_MACMIIAR_MW_Pos (1) +#define ETH_MACMIIAR_MW (0x01U << ETH_MACMIIAR_MW_Pos) ///< MII write +#define ETH_MACMIIAR_MB_Pos (0) +#define ETH_MACMIIAR_MB (0x01U << ETH_MACMIIAR_MB_Pos) ///< MII busy + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH_MACMIIDR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define ETH_MACMIIDR_MD (0x0000FFFFU) ///< MII data: read/write data from/to PHY + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH_MACFCR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define ETH_MACFCR_PT_Pos (16) +#define ETH_MACFCR_PT ((u32)0xFFFF << ETH_MACFCR_PT_Pos) ///< Pause time +#define ETH_MACFCR_PLT_Pos (4) +#define ETH_MACFCR_PLT (0x03U << ETH_MACFCR_PLT_Pos) ///< Pause low threshold: 4 cases +#define ETH_MACFCR_PLT_Minus4 (0x00U << ETH_MACFCR_PLT_Pos) ///< Pause time minus 4 slot times +#define ETH_MACFCR_PLT_Minus28 (0x01U << ETH_MACFCR_PLT_Pos) ///< Pause time minus 28 slot times +#define ETH_MACFCR_PLT_Minus144 (0x02U << ETH_MACFCR_PLT_Pos) ///< Pause time minus 144 slot times +#define ETH_MACFCR_PLT_Minus256 (0x03U << ETH_MACFCR_PLT_Pos) ///< Pause time minus 256 slot times +#define ETH_MACFCR_UPFD_Pos (3) +#define ETH_MACFCR_UPFD (0x01U << ETH_MACFCR_UPFD_Pos) ///< Unicast pause frame detect +#define ETH_MACFCR_RFCE_Pos (2) +#define ETH_MACFCR_RFCE (0x01U << ETH_MACFCR_RFCE_Pos) ///< Receive flow control enable +#define ETH_MACFCR_TFCE_Pos (1) +#define ETH_MACFCR_TFCE (0x01U << ETH_MACFCR_TFCE_Pos) ///< Transmit flow control enable +#define ETH_MACFCR_FCBBPA_Pos (0) +#define ETH_MACFCR_FCBBPA (0x01U << ETH_MACFCR_FCBBPA_Pos) ///< Flow control busy/backpressure activate + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH_MACVLANTR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define ETH_MACVLANTR_VLANTI (0x0000FFFFU) ///< VLAN tag identifier (for receive frames) + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH_MACRWUFFR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define ETH_MACRWUFFR_D (0xFFFFFFFFU) ///< Wake-up frame filter register data +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH_MACPMTCSR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define ETH_MACPMTCSR_WFFRPR_Pos (31) ///< Wake-Up Frame Filter Register Pointer Reset +#define ETH_MACPMTCSR_WFFRPR (0x01U << ETH_MACPMTCSR_WFFRPR_Pos) ///< Wake-Up Frame Filter Register Pointer Reset +#define ETH_MACPMTCSR_GU_Pos (9) +#define ETH_MACPMTCSR_GU (0x01U << ETH_MACPMTCSR_GU_Pos) ///< Global Unicast +#define ETH_MACPMTCSR_WFR_Pos (6) +#define ETH_MACPMTCSR_WFR (0x01U << ETH_MACPMTCSR_WFR_Pos) ///< Wake-Up Frame Received +#define ETH_MACPMTCSR_MPR_Pos (5) +#define ETH_MACPMTCSR_MPR (0x01U << ETH_MACPMTCSR_MPR_Pos) ///< Magic Packet Received +#define ETH_MACPMTCSR_WFE_Pos (2) +#define ETH_MACPMTCSR_WFE (0x01U << ETH_MACPMTCSR_WFE_Pos) ///< Wake-Up Frame Enable +#define ETH_MACPMTCSR_MPE_Pos (1) +#define ETH_MACPMTCSR_MPE (0x01U << ETH_MACPMTCSR_MPE_Pos) ///< Magic Packet Enable +#define ETH_MACPMTCSR_PD_Pos (0) +#define ETH_MACPMTCSR_PD (0x01U << ETH_MACPMTCSR_PD_Pos) ///< Power Down +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH_MACA0HR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define ETH_MACA0HR_MACA0H ((u32)0x0000FFFF) ///< MAC address0 high + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH_MACA0LR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define ETH_MACA0LR_MACA0L ((u32)0xFFFFFFFF) ///< MAC address0 low + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH_MACA1HR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define ETH_MACA1HR_AE_Pos (31) +#define ETH_MACA1HR_AE (0x01U << ETH_MACA1HR_AE_Pos) ///< Address enable +#define ETH_MACA1HR_SA_Pos (30) +#define ETH_MACA1HR_SA (0x01U << ETH_MACA1HR_SA_Pos) ///< Source address +#define ETH_MACA1HR_MBC_Pos (24) +#define ETH_MACA1HR_MBC (0x3FU << ETH_MACA1HR_MBC_Pos) ///< Mask byte control: bits to mask for comparison of the MAC Address bytes +#define ETH_MACA1HR_MBC_HBits15_8 (0x20U << ETH_MACA1HR_MBC_Pos) ///< Mask MAC Address high reg bits [15:8] +#define ETH_MACA1HR_MBC_HBits7_0 (0x10U << ETH_MACA1HR_MBC_Pos) ///< Mask MAC Address high reg bits [7:0] +#define ETH_MACA1HR_MBC_LBits31_24 (0x08U << ETH_MACA1HR_MBC_Pos) ///< Mask MAC Address low reg bits [31:24] +#define ETH_MACA1HR_MBC_LBits23_16 (0x04U << ETH_MACA1HR_MBC_Pos) ///< Mask MAC Address low reg bits [23:16] +#define ETH_MACA1HR_MBC_LBits15_8 (0x02U << ETH_MACA1HR_MBC_Pos) ///< Mask MAC Address low reg bits [15:8] +#define ETH_MACA1HR_MBC_LBits7_0 (0x00U << ETH_MACA1HR_MBC_Pos) ///< Mask MAC Address low reg bits [7:0] +#define ETH_MACA1HR_MACA1H_Pos (0) +#define ETH_MACA1HR_MACA1H (0x0000FFFFU << ETH_MACA1HR_MACA1H_Pos) ///< MAC address1 high + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH_MACA1LR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define ETH_MACA1LR_MACA1L (0xFFFFFFFFU) ///< MAC address1 low + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH_MACA2HR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define ETH_MACA2HR_AE_Pos (31) +#define ETH_MACA2HR_AE (0x01U << ETH_MACA2HR_AE_Pos) ///< Address enable +#define ETH_MACA2HR_SA_Pos (30) +#define ETH_MACA2HR_SA (0x01U << ETH_MACA2HR_SA_Pos) ///< Source address +#define ETH_MACA2HR_MBC_Pos (24) +#define ETH_MACA2HR_MBC (0x3FU << ETH_MACA2HR_MBC_Pos) ///< Mask byte control: bits to mask for comparison of the MAC Address bytes +#define ETH_MACA2HR_MBC_HBits15_8 (0x20U << ETH_MACA2HR_MBC_Pos) ///< Mask MAC Address high reg bits [15:8] +#define ETH_MACA2HR_MBC_HBits7_0 (0x10U << ETH_MACA2HR_MBC_Pos) ///< Mask MAC Address high reg bits [7:0] +#define ETH_MACA2HR_MBC_LBits31_24 (0x08U << ETH_MACA2HR_MBC_Pos) ///< Mask MAC Address low reg bits [31:24] +#define ETH_MACA2HR_MBC_LBits23_16 (0x04U << ETH_MACA2HR_MBC_Pos) ///< Mask MAC Address low reg bits [23:16] +#define ETH_MACA2HR_MBC_LBits15_8 (0x02U << ETH_MACA2HR_MBC_Pos) ///< Mask MAC Address low reg bits [15:8] +#define ETH_MACA2HR_MBC_LBits7_0 (0x00U << ETH_MACA2HR_MBC_Pos) ///< Mask MAC Address low reg bits [7:0] +#define ETH_MACA2HR_MACA2H_Pos (0) +#define ETH_MACA2HR_MACA2H (0x0000FFFFU << ETH_MACA2HR_MACA2H_Pos) ///< MAC address2 high + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH_MACA2LR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define ETH_MACA2LR_MACA2L (0xFFFFFFFFU) ///< MAC address2 low +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH_MACANCR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define ETH_MACANCR_LR_Pos (17) +#define ETH_MACANCR_LR (0x01U << ETH_MACANCR_LR_Pos) ///< Lock to Reference +#define ETH_MACANCR_ECD_Pos (16) +#define ETH_MACANCR_ECD (0x01U << ETH_MACANCR_ECD_Pos) ///< Enable Comma Detect +#define ETH_MACANCR_ELE_Pos (14) +#define ETH_MACANCR_ELE (0x01U << ETH_MACANCR_ELE_Pos) ///< External Loopback Enable +#define ETH_MACANCR_ANE_Pos (12) +#define ETH_MACANCR_ANE (0x01U << ETH_MACANCR_ANE_Pos) ///< Auto-Negotiation Enable +#define ETH_MACANCR_RAN_Pos (9) +#define ETH_MACANCR_RAN (0x01U << ETH_MACANCR_RAN_Pos) ///< Restart Auto-Negotiation +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH_MACANSR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define ETH_MACANSR_ES_Pos (8) +#define ETH_MACANSR_ES (0x01U << ETH_MACANSR_ES_Pos) ///< Extended Status +#define ETH_MACANSR_ANC_Pos (5) +#define ETH_MACANSR_ANC (0x01U << ETH_MACANSR_ANC_Pos) ///< Auto-Negotiation Complete +#define ETH_MACANSR_ANA_Pos (3) +#define ETH_MACANSR_ANA (0x01U << ETH_MACANSR_ANA_Pos) ///< Auto-Negotiation Ability +#define ETH_MACANSR_LS_Pos (2) +#define ETH_MACANSR_LS (0x01U << ETH_MACANSR_LS_Pos) ///< Link Status +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH_MACANAR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define ETH_MACANAR_NP_Pos (15) +#define ETH_MACANAR_NP (0x01U << ETH_MACANAR_NP_Pos) ///< Next Page Support +#define ETH_MACANAR_RFE_Pos (12) +#define ETH_MACANAR_RFE (0x01U << ETH_MACANAR_RFE_Pos) ///< Remote Fault Encoding +#define ETH_MACANAR_PSE_Pos (7) +#define ETH_MACANAR_PSE (0x01U << ETH_MACANAR_PSE_Pos) ///< Pause Encoding +#define ETH_MACANAR_HD_Pos (6) +#define ETH_MACANAR_HD (0x01U << ETH_MACANAR_HD_Pos) ///< support Half-Duplex +#define ETH_MACANAR_FD_Pos (5) +#define ETH_MACANAR_FD (0x01U << ETH_MACANAR_FD_Pos) ///< support Full-Durplex +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH_MACANLPAR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define ETH_MACANLPAR_NP_Pos (15) +#define ETH_MACANLPAR_NP (0x01U << ETH_MACANLPAR_NP_Pos) ///< Next Page Support +#define ETH_MACANLPAR_ACK_Pos (14) +#define ETH_MACANLPAR_ACK (0x01U << ETH_MACANLPAR_ACK_Pos) ///< Acknowledge +#define ETH_MACANLPAR_RFE_Pos (12) +#define ETH_MACANLPAR_RFE (0x01U << ETH_MACANLPAR_RFE_Pos) ///< Remote Fault Encoding +#define ETH_MACANLPAR_PSE_Pos (7) +#define ETH_MACANLPAR_PSE (0x01U << ETH_MACANLPAR_PSE_Pos) ///< Pause Encoding +#define ETH_MACANLPAR_HD_Pos (6) +#define ETH_MACANLPAR_HD (0x01U << ETH_MACANLPAR_HD_Pos) ///< support Half-Duplex +#define ETH_MACANLPAR_FD_Pos (5) +#define ETH_MACANLPAR_FD (0x01U << ETH_MACANLPAR_FD_Pos) ///< support Full-Durplex +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH_MACANER Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define ETH_MACANER_NPA_Pos (2) +#define ETH_MACANER_NPA (0x01U << ETH_MACANER_NPA_Pos) ///< Next Page Ability +#define ETH_MACANER_NPR_Pos (1) +#define ETH_MACANER_NPR (0x01U << ETH_MACANER_NPR_Pos) ///< New Page Received +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH_MACTBIER Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define ETH_MACTBIER_GFD_Pos (15) +#define ETH_MACTBIER_GFD (0x01U << ETH_MACTBIER_GFD_Pos) ///< 1000BASE-X Full-Duplex Capable +#define ETH_MACTBIER_GHD_Pos (14) +#define ETH_MACTBIER_GHD (0x01U << ETH_MACTBIER_GHD_Pos) ///< 1000BASE-X Half-Duplex Capable +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH_MACMIISR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define ETH_MACMIISR_LS_Pos (3) +#define ETH_MACMIISR_LS (0x01U << ETH_MACMIISR_LS_Pos) ///< Link Status +#define ETH_MACMIISR_LSP_Pos (1) +#define ETH_MACMIISR_LSP_2_5 (0x00U << ETH_MACMIISR_LSP_Pos) ///< Link Speed 2.5 MHz +#define ETH_MACMIISR_LSP_25 (0x01U << ETH_MACMIISR_LSP_Pos) ///< Link Speed 25 MHz +#define ETH_MACMIISR_LSP_125 (0x02U << ETH_MACMIISR_LSP_Pos) ///< Link Speed 125 MHz +#define ETH_MACMIISR_LM_Pos (0) +#define ETH_MACMIISR_LM (0x01U << ETH_MACMIISR_LM_Pos) ///< Link Mode : Full-Duplex Capable + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH_MMCCR Registers bits definition +//////////////////////////////////////////////////////////////////////////////// +#define ETH_MMCCR_MCFHP ((u32)0x00000020) ///< MMC counter Full-Half preset +#define ETH_MMCCR_MCP ((u32)0x00000010) ///< MMC counter preset +#define ETH_MMCCR_MCF ((u32)0x00000008) ///< MMC Counter Freeze +#define ETH_MMCCR_ROR_Pos (2) +#define ETH_MMCCR_ROR (0x01U << ETH_MMCCR_ROR_Pos) ///< Reset on Read +#define ETH_MMCCR_CSR_Pos (1) +#define ETH_MMCCR_CSR (0x01U << ETH_MMCCR_CSR_Pos) ///< Counter Stop Rollover +#define ETH_MMCCR_CR_Pos (0) +#define ETH_MMCCR_CR (0x01U << ETH_MMCCR_CR_Pos) ///< Counters Reset + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH_MMCRIR Registers bits definition +//////////////////////////////////////////////////////////////////////////////// +#define ETH_MMCRIR_RGUF_Pos (17) +#define ETH_MMCRIR_RGUFS (0x01U << ETH_MMCRIR_RGUF_Pos) ///< Set when Rx good unicast frames counter reaches half the maximum value +#define ETH_MMCRIR_RFAES_Pos (6) +#define ETH_MMCRIR_RFAES (0x01U << ETH_MMCRIR_RFAES_Pos) ///< Set when Rx alignment error counter reaches half the maximum value +#define ETH_MMCRIR_RFCES_Pos (5) +#define ETH_MMCRIR_RFCES (0x01U << ETH_MMCRIR_RFCES_Pos) ///< Set when Rx crc error counter reaches half the maximum value + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH_MMCTIR Registers bits definition +//////////////////////////////////////////////////////////////////////////////// +#define ETH_MMCTIR_TGFS_Pos (21) +#define ETH_MMCTIR_TGFS (0x01U << ETH_MMCTIR_TGFS_Pos) ///< Set when Tx good frame count counter reaches half the maximum value +#define ETH_MMCTIR_TGFMSCS_Pos (15) +#define ETH_MMCTIR_TGFMSCS (0x01U << ETH_MMCTIR_TGFMSCS_Pos) ///< Set when Tx good multi col counter reaches half the maximum value +#define ETH_MMCTIR_TGFSCS_Pos (14) +#define ETH_MMCTIR_TGFSCS (0x01U << ETH_MMCTIR_TGFSCS_Pos) ///< Set when Tx good single col counter reaches half the maximum value + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH_MMCRIMR Registers bits definition +//////////////////////////////////////////////////////////////////////////////// +#define ETH_MMCRIMR_RGUFM_Pos (17) +#define ETH_MMCRIMR_RGUFM (0x01U << ETH_MMCRIMR_RGUFM_Pos) ///< Mask the interrupt when Rx good unicast frames counter reaches half the maximum value +#define ETH_MMCRIMR_RFAEM_Pos (6) +#define ETH_MMCRIMR_RFAEM (0x01U << ETH_MMCRIMR_RFAEM_Pos) ///< Mask the interrupt when when Rx alignment error counter reaches half the maximum value +#define ETH_MMCRIMR_RFCEM_Pos (5) +#define ETH_MMCRIMR_RFCEM (0x01U << ETH_MMCRIMR_RFCEM_Pos) ///< Mask the interrupt when Rx crc error counter reaches half the maximum value + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH_MMCTIMR Registers bits definition +//////////////////////////////////////////////////////////////////////////////// +#define ETH_MMCTIMR_TGFM_Pos (21) +#define ETH_MMCTIMR_TGFM (0x01U << ETH_MMCTIMR_TGFM_Pos) ///< Mask the interrupt when Tx good frame count counter reaches half the maximum value +#define ETH_MMCTIMR_TGFMSCM_Pos (15) +#define ETH_MMCTIMR_TGFMSCM (0x01U << ETH_MMCTIMR_TGFMSCM_Pos) ///< Mask the interrupt when Tx good multi col counter reaches half the maximum value +#define ETH_MMCTIMR_TGFSCM_Pos (14) +#define ETH_MMCTIMR_TGFSCM (0x01U << ETH_MMCTIMR_TGFSCM_Pos) ///< Mask the interrupt when Tx good single col counter reaches half the maximum value + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH_MMCTGFSCCR Registers bits definition +//////////////////////////////////////////////////////////////////////////////// +#define ETH_MMCTGFSCCR_TGFSCC (0xFFFFFFFFU) ///< Number of successfully transmitted frames after a single collision in Half-duplex mode. +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH_MMCTGFMSCCR Registers bits definition +//////////////////////////////////////////////////////////////////////////////// +#define ETH_MMCTGFMSCCR_TGFMSCC (0xFFFFFFFFU) ///< Number of successfully transmitted frames after more than a single collision in Half-duplex mode. +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH_MMCTGFCR Registers bits definition +//////////////////////////////////////////////////////////////////////////////// +#define ETH_MMCTGFCR_TGFC (0xFFFFFFFFU) ///< Number of good frames transmitted. +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH_MMCRFCECR Registers bits definition +//////////////////////////////////////////////////////////////////////////////// +#define ETH_MMCRFCECR_RFCEC (0xFFFFFFFFU) ///< Number of frames received with CRC error. +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH_MMCRFAECR Registers bits definition +//////////////////////////////////////////////////////////////////////////////// +#define ETH_MMCRFAECR_RFAEC (0xFFFFFFFFU) ///< Number of frames received with alignment (dribble) error +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH_MMCRGUFCR Registers bits definition +//////////////////////////////////////////////////////////////////////////////// +#define ETH_MMCRGUFCR_RGUFC (0xFFFFFFFFU) ///< Number of good unicast frames received. +/// @brief ETH_DMABMR Registers bits definition +//////////////////////////////////////////////////////////////////////////////// +#define ETH_DMABMR_FB_Pos (16) +#define ETH_DMABMR_FB (0x01U << ETH_DMABMR_FB_Pos) ///< Fixed Burst +#define ETH_DMABMR_RTPR_Pos (14) +#define ETH_DMABMR_RTPR (0x03U << ETH_DMABMR_RTPR_Pos) ///< Rx Tx priority ratio +#define ETH_DMABMR_RTPR_1_1 (0x00U << ETH_DMABMR_RTPR_Pos) ///< Rx Tx priority ratio +#define ETH_DMABMR_RTPR_2_1 (0x01U << ETH_DMABMR_RTPR_Pos) ///< Rx Tx priority ratio +#define ETH_DMABMR_RTPR_3_1 (0x02U << ETH_DMABMR_RTPR_Pos) ///< Rx Tx priority ratio +#define ETH_DMABMR_RTPR_4_1 (0x03U << ETH_DMABMR_RTPR_Pos) ///< Rx Tx priority ratio +#define ETH_DMABMR_PBL_Pos (8) +#define ETH_DMABMR_PBL (0x3FU<< ETH_DMABMR_PBL_Pos) //< Programmable burst length +#define ETH_DMABMR_PBL_1Beat (0x01U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 +#define ETH_DMABMR_PBL_2Beat (0x02U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 +#define ETH_DMABMR_PBL_4Beat (0x04U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 +#define ETH_DMABMR_PBL_8Beat (0x08U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 +#define ETH_DMABMR_PBL_16Beat (0x10U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 +#define ETH_DMABMR_PBL_32Beat (0x20U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 +#define ETH_DMABMR_PBL_4xPBL_4Beat (0x10001U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 +#define ETH_DMABMR_PBL_4xPBL_8Beat (0x10002U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 +#define ETH_DMABMR_PBL_4xPBL_16Beat (0x10004U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 +#define ETH_DMABMR_PBL_4xPBL_32Beat (0x10008U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 +#define ETH_DMABMR_PBL_4xPBL_64Beat (0x10010U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 +#define ETH_DMABMR_PBL_4xPBL_128Beat (0x10020U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 + +#define ETH_DMABMR_DSL_Pos (2) +#define ETH_DMABMR_DSL (0x01U << ETH_DMABMR_DSL_Pos) ///< Descriptor Skip Length +#define ETH_DMABMR_DA_Pos (1) +#define ETH_DMABMR_DA (0x1FU << ETH_DMABMR_DA_Pos) ///< DMA arbitration scheme +#define ETH_DMABMR_SR_Pos (0) +#define ETH_DMABMR_SR (0x01U << ETH_DMABMR_SR_Pos) ///< Software reset + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH_DMATPDR Registers bits definition +//////////////////////////////////////////////////////////////////////////////// +#define ETH_DMATPDR_TPD (0xFFFFFFFFU) ///< Transmit poll demand +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH_DMARPDR Registers bits definition +//////////////////////////////////////////////////////////////////////////////// +#define ETH_DMARPDR_RPD (0xFFFFFFFFU) ///< Receive poll demand +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH_DMARDLAR Registers bits definition +//////////////////////////////////////////////////////////////////////////////// +#define ETH_DMARDLAR_SRL (0xFFFFFFFFU) ///< Start of receive list +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH_DMATDLAR Registers bits definition +//////////////////////////////////////////////////////////////////////////////// +#define ETH_DMATDLAR_STL (0xFFFFFFFFU) ///< Start of transmit list + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH_DMASR Registers bits definition +//////////////////////////////////////////////////////////////////////////////// +#define ETH_DMASR_PMTS_Pos (28) +#define ETH_DMASR_PMTS (0x01U << ETH_DMASR_PMTS_Pos) ///< PMT status +#define ETH_DMASR_MMCS_Pos (27) +#define ETH_DMASR_MMCS (0x01U << ETH_DMASR_MMCS_Pos) ///< MMC status +#define ETH_DMASR_LIS_Pos (26) +#define ETH_DMASR_LIS (0x01U << ETH_DMASR_LIS_Pos) ///< GMAC Line interface Status + +#define ETH_DMASR_EBS_Pos (23) +#define ETH_DMASR_EBS (0x07U << ETH_DMASR_EBS_Pos) ///< Error bits status +#define ETH_DMASR_EBS_DescAccess (0x04U << ETH_DMASR_EBS_Pos) ///< Error bits 0-data buffer, 1-desc. access +#define ETH_DMASR_EBS_ReadTransf (0x02U << ETH_DMASR_EBS_Pos) ///< Error bits 0-write trnsf, 1-read transfr +#define ETH_DMASR_EBS_DataTransfTx (0x01U << ETH_DMASR_EBS_Pos) ///< Error bits 0-Rx DMA, 1-Tx DMA +#define ETH_DMASR_TPS_Pos (20) +#define ETH_DMASR_TPS (0x007U << ETH_DMASR_TPS_Pos) ///< Transmit process state +#define ETH_DMASR_TPS_Stopped (0x000U << ETH_DMASR_TPS_Pos) ///< Stopped - Reset or Stop Tx Command issued +#define ETH_DMASR_TPS_Fetching (0x001U << ETH_DMASR_TPS_Pos) ///< Running - fetching the Tx descriptor +#define ETH_DMASR_TPS_Waiting (0x002U << ETH_DMASR_TPS_Pos) ///< Running - waiting for status +#define ETH_DMASR_TPS_Reading (0x003U << ETH_DMASR_TPS_Pos) ///< Running - reading the data from host memory +#define ETH_DMASR_TPS_Suspended (0x006U << ETH_DMASR_TPS_Pos) ///< Suspended - Tx Descriptor unavailabe +#define ETH_DMASR_TPS_Closing (0x007U << ETH_DMASR_TPS_Pos) ///< Running - closing Rx descriptor +#define ETH_DMASR_RPS_Pos (17) +#define ETH_DMASR_RPS (0x07U << ETH_DMASR_RPS_Pos) ///< Receive process state +#define ETH_DMASR_RPS_Stopped (0x00U << ETH_DMASR_RPS_Pos) ///< Stopped - Reset or Stop Rx Command issued +#define ETH_DMASR_RPS_Fetching (0x01U << ETH_DMASR_RPS_Pos) ///< Running - fetching the Rx descriptor +#define ETH_DMASR_RPS_Waiting (0x03U << ETH_DMASR_RPS_Pos) ///< Running - waiting for packet +#define ETH_DMASR_RPS_Suspended (0x04U << ETH_DMASR_RPS_Pos) ///< Suspended - Rx Descriptor unavailable +#define ETH_DMASR_RPS_Closing (0x05U << ETH_DMASR_RPS_Pos) ///< Running - closing descriptor +#define ETH_DMASR_RPS_Queuing (0x07U << ETH_DMASR_RPS_Pos) ///< Running - queuing the recieve frame into host memory +#define ETH_DMASR_NIS_Pos (16) +#define ETH_DMASR_NIS (0x01U << ETH_DMASR_NIS_Pos ) ///< Normal interrupt summary +#define ETH_DMASR_AIS_Pos (15) +#define ETH_DMASR_AIS (0x01U << ETH_DMASR_AIS_Pos ) ///< Abnormal interrupt summary +#define ETH_DMASR_ERS_Pos (14) +#define ETH_DMASR_ERS (0x01U << ETH_DMASR_ERS_Pos ) ///< Early receive status +#define ETH_DMASR_FBES_Pos (13) +#define ETH_DMASR_FBES (0x01U << ETH_DMASR_FBES_Pos) ///< Fatal bus error status +#define ETH_DMASR_ETS_Pos (10) +#define ETH_DMASR_ETS (0x01U << ETH_DMASR_ETS_Pos ) ///< Early transmit status +#define ETH_DMASR_RWTS_Pos (9) +#define ETH_DMASR_RWTS (0x01U << ETH_DMASR_RWTS_Pos) ///< Receive watchdog timeout status +#define ETH_DMASR_RPSS_Pos (8) +#define ETH_DMASR_RPSS (0x01U << ETH_DMASR_RPSS_Pos) ///< Receive process stopped status +#define ETH_DMASR_RBUS_Pos (7) +#define ETH_DMASR_RBUS (0x01U << ETH_DMASR_RBUS_Pos) ///< Receive buffer unavailable status +#define ETH_DMASR_RS_Pos (6) +#define ETH_DMASR_RS (0x01U << ETH_DMASR_RS_Pos ) ///< Receive status +#define ETH_DMASR_TUS_Pos (5) +#define ETH_DMASR_TUS (0x01U << ETH_DMASR_TUS_Pos ) ///< Transmit underflow status +#define ETH_DMASR_ROS_Pos (4) +#define ETH_DMASR_ROS (0x01U << ETH_DMASR_ROS_Pos ) ///< Receive overflow status +#define ETH_DMASR_TJTS_Pos (3) +#define ETH_DMASR_TJTS (0x01U << ETH_DMASR_TJTS_Pos) ///< Transmit jabber timeout status +#define ETH_DMASR_TBUS_Pos (2) +#define ETH_DMASR_TBUS (0x01U << ETH_DMASR_TBUS_Pos) ///< Transmit buffer unavailable status +#define ETH_DMASR_TPSS_Pos (1) +#define ETH_DMASR_TPSS (0x01U << ETH_DMASR_TPSS_Pos) ///< Transmit process stopped status +#define ETH_DMASR_TS_Pos (0) +#define ETH_DMASR_TS (0x01U << ETH_DMASR_TS_Pos ) ///< Transmit status + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH_DMAOMR Registers bits definition +//////////////////////////////////////////////////////////////////////////////// + +#define ETH_DMAOMR_TSF_Pos (21) +#define ETH_DMAOMR_TSF (0x01U << ETH_DMAOMR_TSF_Pos) ///< Transmit store and forward +#define ETH_DMAOMR_FTF_Pos (20) +#define ETH_DMAOMR_FTF (0x01U << ETH_DMAOMR_FTF_Pos) ///< Flush transmit FIFO +#define ETH_DMAOMR_TTC_Pos (14) +#define ETH_DMAOMR_TTC (0x07U << ETH_DMAOMR_TTC_Pos) ///< Transmit threshold control +#define ETH_DMAOMR_TTC_64Bytes (0x00U << ETH_DMAOMR_TTC_Pos) ///< threshold level of the MTL Transmit FIFO is 64 Bytes +#define ETH_DMAOMR_TTC_128Bytes (0x01U << ETH_DMAOMR_TTC_Pos) ///< threshold level of the MTL Transmit FIFO is 128 Bytes +#define ETH_DMAOMR_TTC_192Bytes (0x02U << ETH_DMAOMR_TTC_Pos) ///< threshold level of the MTL Transmit FIFO is 192 Bytes +#define ETH_DMAOMR_TTC_256Bytes (0x03U << ETH_DMAOMR_TTC_Pos) ///< threshold level of the MTL Transmit FIFO is 256 Bytes +#define ETH_DMAOMR_TTC_40Bytes (0x04U << ETH_DMAOMR_TTC_Pos) ///< threshold level of the MTL Transmit FIFO is 40 Bytes +#define ETH_DMAOMR_TTC_32Bytes (0x05U << ETH_DMAOMR_TTC_Pos) ///< threshold level of the MTL Transmit FIFO is 32 Bytes +#define ETH_DMAOMR_TTC_24Bytes (0x06U << ETH_DMAOMR_TTC_Pos) ///< threshold level of the MTL Transmit FIFO is 24 Bytes +#define ETH_DMAOMR_TTC_16Bytes (0x07U << ETH_DMAOMR_TTC_Pos) ///< threshold level of the MTL Transmit FIFO is 16 Bytes +#define ETH_DMAOMR_ST_Pos (13) +#define ETH_DMAOMR_ST (0x01U << ETH_DMAOMR_ST_Pos ) ///< Start/stop transmission command +#define ETH_DMAOMR_RFD_Pos (11) +#define ETH_DMAOMR_RFD1 (0x00U << ETH_DMAOMR_RFD_Pos ) ///< Threshold for failure flow control 1 byte +#define ETH_DMAOMR_RFD2 (0x01U << ETH_DMAOMR_RFD_Pos ) ///< Threshold for failure flow control 2 byte +#define ETH_DMAOMR_RFD3 (0x02U << ETH_DMAOMR_RFD_Pos ) ///< Threshold for failure flow control 3 byte +#define ETH_DMAOMR_RFD4 (0x03U << ETH_DMAOMR_RFD_Pos ) ///< Threshold for failure flow control 4 byte +#define ETH_DMAOMR_RFA_Pos (9) +#define ETH_DMAOMR_RFA1 (0x00U << ETH_DMAOMR_RFA_Pos ) ///< Activate the threshold for flow control 1 byte +#define ETH_DMAOMR_RFA2 (0x01U << ETH_DMAOMR_RFA_Pos ) ///< Activate the threshold for flow control 2 byte +#define ETH_DMAOMR_RFA3 (0x02U << ETH_DMAOMR_RFA_Pos ) ///< Activate the threshold for flow control 3 byte +#define ETH_DMAOMR_RFA4 (0x03U << ETH_DMAOMR_RFA_Pos ) ///< Activate the threshold for flow control 4 byte + +#define ETH_DMAOMR_EFC_Pos (8) +#define ETH_DMAOMR_EFC (0x01U << ETH_DMAOMR_EFC_Pos ) ///< Enable HW Flow Control +#define ETH_DMAOMR_FEF_Pos (7) +#define ETH_DMAOMR_FEF (0x01U << ETH_DMAOMR_FEF_Pos ) ///< Forward error frames +#define ETH_DMAOMR_FUGF_Pos (6) +#define ETH_DMAOMR_FUGF (0x01U << ETH_DMAOMR_FUGF_Pos) ///< Forward undersized good frames +#define ETH_DMAOMR_RTC_Pos (3) +#define ETH_DMAOMR_RTC (0x03U << ETH_DMAOMR_RTC_Pos) ///< receive threshold control +#define ETH_DMAOMR_RTC_64Bytes (0x00U << ETH_DMAOMR_RTC_Pos) ///< threshold level of the MTL Receive FIFO is 64 Bytes +#define ETH_DMAOMR_RTC_32Bytes (0x01U << ETH_DMAOMR_RTC_Pos) ///< threshold level of the MTL Receive FIFO is 32 Bytes +#define ETH_DMAOMR_RTC_96Bytes (0x02U << ETH_DMAOMR_RTC_Pos) ///< threshold level of the MTL Receive FIFO is 96 Bytes +#define ETH_DMAOMR_RTC_128Bytes (0x03U << ETH_DMAOMR_RTC_Pos) ///< threshold level of the MTL Receive FIFO is 128 Bytes +#define ETH_DMAOMR_OSF_Pos (2) +#define ETH_DMAOMR_OSF (0x01U << ETH_DMAOMR_OSF_Pos) ///< operate on second frame +#define ETH_DMAOMR_SR_Pos (1) +#define ETH_DMAOMR_SR (0x01U << ETH_DMAOMR_SR_Pos ) ///< Start/stop receive + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH_DMAIER Registers bits definition +//////////////////////////////////////////////////////////////////////////////// +#define ETH_DMAIER_NISE_Pos (16) +#define ETH_DMAIER_NISE (0x01U << ETH_DMAIER_NISE_Pos ) ///< Normal interrupt summary enable +#define ETH_DMAIER_AISE_Pos (15) +#define ETH_DMAIER_AISE (0x01U << ETH_DMAIER_AISE_Pos ) ///< Abnormal interrupt summary enable +#define ETH_DMAIER_ERIE_Pos (14) +#define ETH_DMAIER_ERIE (0x01U << ETH_DMAIER_ERIE_Pos ) ///< Early receive interrupt enable +#define ETH_DMAIER_FBEIE_Pos (13) +#define ETH_DMAIER_FBEIE (0x01U << ETH_DMAIER_FBEIE_Pos) ///< Fatal bus error interrupt enable +#define ETH_DMAIER_ETIE_Pos (10) +#define ETH_DMAIER_ETIE (0x01U << ETH_DMAIER_ETIE_Pos ) ///< Early transmit interrupt enable +#define ETH_DMAIER_RWTIE_Pos (9) +#define ETH_DMAIER_RWTIE (0x01U << ETH_DMAIER_RWTIE_Pos) ///< Receive watchdog timeout interrupt enable +#define ETH_DMAIER_RPSIE_Pos (8) +#define ETH_DMAIER_RPSIE (0x01U << ETH_DMAIER_RPSIE_Pos) ///< Receive process stopped interrupt enable +#define ETH_DMAIER_RBUIE_Pos (7) +#define ETH_DMAIER_RBUIE (0x01U << ETH_DMAIER_RBUIE_Pos) ///< Receive buffer unavailable interrupt enable +#define ETH_DMAIER_RIE_Pos (6) +#define ETH_DMAIER_RIE (0x01U << ETH_DMAIER_RIE_Pos ) ///< Receive interrupt enable +#define ETH_DMAIER_TUIE_Pos (5) +#define ETH_DMAIER_TUIE (0x01U << ETH_DMAIER_TUIE_Pos ) ///< Transmit Underflow interrupt enable +#define ETH_DMAIER_ROIE_Pos (4) +#define ETH_DMAIER_ROIE (0x01U << ETH_DMAIER_ROIE_Pos ) ///< Receive Overflow interrupt enable +#define ETH_DMAIER_TJTIE_Pos (3) +#define ETH_DMAIER_TJTIE (0x01U << ETH_DMAIER_TJTIE_Pos) ///< Transmit jabber timeout interrupt enable +#define ETH_DMAIER_TBUIE_Pos (2) +#define ETH_DMAIER_TBUIE (0x01U << ETH_DMAIER_TBUIE_Pos) ///< Transmit buffer unavailable interrupt enable +#define ETH_DMAIER_TPSIE_Pos (1) +#define ETH_DMAIER_TPSIE (0x01U << ETH_DMAIER_TPSIE_Pos) ///< Transmit process stopped interrupt enable +#define ETH_DMAIER_TIE_Pos (0) +#define ETH_DMAIER_TIE (0x01U << ETH_DMAIER_TIE_Pos ) ///< Transmit interrupt enable +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH_DMAMFBOCR Registers bits definition +//////////////////////////////////////////////////////////////////////////////// +#define ETH_DMAMFBOCR_OFOC_Pos (28) +#define ETH_DMAMFBOCR_OFOC (0x01U << ETH_DMAMFBOCR_OFOC_Pos) ///< Overflow bit for FIFO overflow counter + +#define ETH_DMAMFBOCR_MFA_Pos (17) +#define ETH_DMAMFBOCR_MFA (0x7FFU << ETH_DMAMFBOCR_MFA_Pos ) ///< Number of frames missed by the application + +#define ETH_DMAMFBOCR_OMFC_Pos (16) +#define ETH_DMAMFBOCR_OMFC (0x01U << ETH_DMAMFBOCR_OMFC_Pos) ///< Overflow bit for missed frame counter + +#define ETH_DMAMFBOCR_MFC_Pos (0) +#define ETH_DMAMFBOCR_MFC (0xFFFFU << ETH_DMAMFBOCR_MFC_Pos ) ///< Number of frames missed by the controller + +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH_DMACHTDR Registers bits definition +//////////////////////////////////////////////////////////////////////////////// +#define ETH_DMACHTDR_HTDAP (0xFFFFFFFFU) ///< Host transmit descriptor address pointer +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH_DMACHRDR Registers bits definition +//////////////////////////////////////////////////////////////////////////////// +#define ETH_DMACHRDR_HRDAP (0xFFFFFFFFU) ///< Host receive descriptor address pointer +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH_DMACHTBAR Registers bits definition +//////////////////////////////////////////////////////////////////////////////// +#define ETH_DMACHTBAR_HTBAP (0xFFFFFFFFU) ///< Host transmit buffer address pointer +//////////////////////////////////////////////////////////////////////////////// +/// @brief ETH_DMACHRBAR Registers bits definition +//////////////////////////////////////////////////////////////////////////////// +#define ETH_DMACHRBAR_HRBAP (0xFFFFFFFFU) ///< Host receive buffer address pointer + + +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +#endif +//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_exti.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_exti.h new file mode 100644 index 000000000..608c12bc2 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_exti.h @@ -0,0 +1,544 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file reg_exti.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF +/// MM32 FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion + +#ifndef __REG_EXTI_H +#define __REG_EXTI_H + +// Files includes + +#include +#include +#include "types.h" + + + + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + + + + + + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief EXTI Base Address Definition +//////////////////////////////////////////////////////////////////////////////// +#define EXTI_BASE (APB2PERIPH_BASE + 0x0000) ///< Base Address: 0x40010000 + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief EXTI Registers Structure Definition +//////////////////////////////////////////////////////////////////////////////// +typedef struct { + __IO u32 CFGR; ///< configuration register, offset: 0x00 + u32 Reserved; ///< Reserved offset: 0x04 + __IO u32 CR[4]; ///< External interrupt configuration register, offset: 0x08 - 0x14 + __IO u32 CFGR2; ///< configuration register offset: 0x18 + __IO u32 PDETCSR; ///< Power detection configuration status register offset: 0x1C + __IO u32 VOSDLY; ///< VOS delay time offset: 0x20 + u32 Reserved1[0x100 - 0x09]; ///< Reserved space + __IO u32 IMR; ///< Interrupt Mask Register offset: 0x00 + 0x400 + __IO u32 EMR; ///< Event Mask Register offset: 0x04 + 0x400 + __IO u32 RTSR; ///< Rising Trigger Status Register offset: 0x08 + 0x400 + __IO u32 FTSR; ///< Falling Trigger Status Register offset: 0x0C + 0x400 + __IO u32 SWIER; ///< Software Interrupt Enable Register offset: 0x10 + 0x400 + __IO u32 PR; ///< Pending Register offset: 0x14 + 0x400 +} EXTI_TypeDef; + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief EXTI type pointer Definition +//////////////////////////////////////////////////////////////////////////////// +#define EXTI ((EXTI_TypeDef*) EXTI_BASE) + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief EXTI_CFGR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define EXTI_CFGR_MEMMODE_Pos (0) +#define EXTI_CFGR_MEMMODE (0x03U << EXTI_CFGR_MEMMODE_Pos) ///< EXTI_Memory Remap Config +#define EXTI_CFGR_MEMMODE_0 (0x01U << EXTI_CFGR_MEMMODE_Pos) ///< EXTI_Memory Remap Config Bit 0 +#define EXTI_CFGR_MEMMODE_1 (0x02U << EXTI_CFGR_MEMMODE_Pos) ///< EXTI_Memory Remap Config Bit 1 +#define EXTI_CFGR_FLASH_MEMORY (0x00U << EXTI_CFGR_MEMMODE_Pos) ///< EXTI_Memory Remap Config Mode 0 +#define EXTI_CFGR_SYSTEM_MEMORY (0x01U << EXTI_CFGR_MEMMODE_Pos) ///< EXTI_Memory Remap Config Mode 1 +#define EXTI_CFGR_SRAM_MEMORY (0x03U << EXTI_CFGR_MEMMODE_Pos) ///< EXTI_Memory Remap Config Mode 3 + + +#define EXTI_CFGR_FC_SYNCEN_Pos (27) +#define EXTI_CFGR_FC_SYNCEN (0x01U << EXTI_CFGR_FC_SYNCEN_Pos) ///< FSMC synchronization enable +#define EXTI_CFGR_FC_ODATAEN_Pos (28) +#define EXTI_CFGR_FC_ODATAEN (0x01U << EXTI_CFGR_FC_ODATAEN_Pos) ///< FSMC Only used as data pin +#define EXTI_CFGR_MODESEL_Pos (29) ///< FSMC mode selection +#define EXTI_CFGR_MODESEL0 (0x00U << EXTI_CFGR_MODESEL0_Pos) ///< Compatible with 8080 protocol interface +#define EXTI_CFGR_MODESEL1 (0x01U << EXTI_CFGR_MODESEL1_Pos) ///< Compatible with NOR FLASH protocol interface + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief EXTI_CR1 Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define EXTI_CR1_EXTI0_Pos (0) +#define EXTI_CR1_EXTI0 (0x0FU << EXTI_CR1_EXTI0_Pos) ///< EXTI 0 configuration +#define EXTI_CR1_EXTI0_PA (0x00U << EXTI_CR1_EXTI0_Pos) ///< PA[0] pin +#define EXTI_CR1_EXTI0_PB (0x01U << EXTI_CR1_EXTI0_Pos) ///< PB[0] pin +#define EXTI_CR1_EXTI0_PC (0x02U << EXTI_CR1_EXTI0_Pos) ///< PC[0] pin +#define EXTI_CR1_EXTI0_PD (0x03U << EXTI_CR1_EXTI0_Pos) ///< PD[0] pin + +#define EXTI_CR1_EXTI1_Pos (4) +#define EXTI_CR1_EXTI1 (0x0FU << EXTI_CR1_EXTI1_Pos) ///< EXTI 1 configuration +#define EXTI_CR1_EXTI1_PA (0x00U << EXTI_CR1_EXTI1_Pos) ///< PA[1] pin +#define EXTI_CR1_EXTI1_PB (0x01U << EXTI_CR1_EXTI1_Pos) ///< PB[1] pin +#define EXTI_CR1_EXTI1_PC (0x02U << EXTI_CR1_EXTI1_Pos) ///< PC[1] pin +#define EXTI_CR1_EXTI1_PD (0x03U << EXTI_CR1_EXTI1_Pos) ///< PD[1] pin + +#define EXTI_CR1_EXTI2_Pos (8) +#define EXTI_CR1_EXTI2 (0x0FU << EXTI_CR1_EXTI2_Pos) ///< EXTI 2 configuration +#define EXTI_CR1_EXTI2_PA (0x00U << EXTI_CR1_EXTI2_Pos) ///< PA[2] pin +#define EXTI_CR1_EXTI2_PB (0x01U << EXTI_CR1_EXTI2_Pos) ///< PB[2] pin +#define EXTI_CR1_EXTI2_PC (0x02U << EXTI_CR1_EXTI2_Pos) ///< PC[2] pin +#define EXTI_CR1_EXTI2_PD (0x03U << EXTI_CR1_EXTI2_Pos) ///< PD[2] pin + +#define EXTI_CR1_EXTI3_Pos (12) +#define EXTI_CR1_EXTI3 (0x0FU << EXTI_CR1_EXTI3_Pos) ///< EXTI 3 configuration +#define EXTI_CR1_EXTI3_PA (0x00U << EXTI_CR1_EXTI3_Pos) ///< PA[3] pin +#define EXTI_CR1_EXTI3_PB (0x01U << EXTI_CR1_EXTI3_Pos) ///< PB[3] pin +#define EXTI_CR1_EXTI3_PC (0x02U << EXTI_CR1_EXTI3_Pos) ///< PC[3] pin +#define EXTI_CR1_EXTI3_PD (0x03U << EXTI_CR1_EXTI3_Pos) ///< PD[3] pin + +//////////////////////////////////////////////////////////////////////////////// +/// @brief EXTI_CR2 Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define EXTI_CR2_EXTI4_Pos (0) +#define EXTI_CR2_EXTI4 (0x0FU << EXTI_CR2_EXTI4_Pos) ///< EXTI 4 configuration +#define EXTI_CR2_EXTI4_PA (0x00U << EXTI_CR2_EXTI4_Pos) ///< PA[4] pin +#define EXTI_CR2_EXTI4_PB (0x01U << EXTI_CR2_EXTI4_Pos) ///< PB[4] pin +#define EXTI_CR2_EXTI4_PC (0x02U << EXTI_CR2_EXTI4_Pos) ///< PC[4] pin +#define EXTI_CR2_EXTI4_PD (0x03U << EXTI_CR2_EXTI4_Pos) ///< PD[4] pin + +#define EXTI_CR2_EXTI5_Pos (4) +#define EXTI_CR2_EXTI5 (0x0FU << EXTI_CR2_EXTI5_Pos) ///< EXTI 5 configuration +#define EXTI_CR2_EXTI5_PA (0x00U << EXTI_CR2_EXTI5_Pos) ///< PA[5] pin +#define EXTI_CR2_EXTI5_PB (0x01U << EXTI_CR2_EXTI5_Pos) ///< PB[5] pin +#define EXTI_CR2_EXTI5_PC (0x02U << EXTI_CR2_EXTI5_Pos) ///< PC[5] pin +#define EXTI_CR2_EXTI5_PD (0x03U << EXTI_CR2_EXTI5_Pos) ///< PD[5] pin + +#define EXTI_CR2_EXTI6_Pos (8) +#define EXTI_CR2_EXTI6 (0x0FU << EXTI_CR2_EXTI6_Pos) ///< EXTI 6 configuration +#define EXTI_CR2_EXTI6_PA (0x00U << EXTI_CR2_EXTI6_Pos) ///< PA[6] pin +#define EXTI_CR2_EXTI6_PB (0x01U << EXTI_CR2_EXTI6_Pos) ///< PB[6] pin +#define EXTI_CR2_EXTI6_PC (0x02U << EXTI_CR2_EXTI6_Pos) ///< PC[6] pin +#define EXTI_CR2_EXTI6_PD (0x03U << EXTI_CR2_EXTI6_Pos) ///< PD[6] pin + +#define EXTI_CR2_EXTI7_Pos (12) +#define EXTI_CR2_EXTI7 (0x0FU << EXTI_CR2_EXTI7_Pos) ///< EXTI 7 configuration +#define EXTI_CR2_EXTI7_PA (0x00U << EXTI_CR2_EXTI7_Pos) ///< PA[7] pin +#define EXTI_CR2_EXTI7_PB (0x01U << EXTI_CR2_EXTI7_Pos) ///< PB[7] pin +#define EXTI_CR2_EXTI7_PC (0x02U << EXTI_CR2_EXTI7_Pos) ///< PC[7] pin +#define EXTI_CR2_EXTI7_PD (0x03U << EXTI_CR2_EXTI7_Pos) ///< PD[7] pin + +//////////////////////////////////////////////////////////////////////////////// +/// @brief EXTI_CR3 Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define EXTI_CR3_EXTI8_Pos (0) +#define EXTI_CR3_EXTI8 (0x0FU << EXTI_CR3_EXTI8_Pos) ///< EXTI 8 configuration +#define EXTI_CR3_EXTI8_PA (0x00U << EXTI_CR3_EXTI8_Pos) ///< PA[8] pin +#define EXTI_CR3_EXTI8_PB (0x01U << EXTI_CR3_EXTI8_Pos) ///< PB[8] pin +#define EXTI_CR3_EXTI8_PC (0x02U << EXTI_CR3_EXTI8_Pos) ///< PC[8] pin +#define EXTI_CR3_EXTI8_PD (0x03U << EXTI_CR3_EXTI8_Pos) ///< PD[8] pin + +#define EXTI_CR3_EXTI9_Pos (4) +#define EXTI_CR3_EXTI9 (0x0FU << EXTI_CR3_EXTI9_Pos) ///< EXTI 9 configuration +#define EXTI_CR3_EXTI9_PA (0x00U << EXTI_CR3_EXTI9_Pos) ///< PA[9] pin +#define EXTI_CR3_EXTI9_PB (0x01U << EXTI_CR3_EXTI9_Pos) ///< PB[9] pin +#define EXTI_CR3_EXTI9_PC (0x02U << EXTI_CR3_EXTI9_Pos) ///< PC[9] pin +#define EXTI_CR3_EXTI9_PD (0x03U << EXTI_CR3_EXTI9_Pos) ///< PD[9] pin + +#define EXTI_CR3_EXTI10_Pos (8) +#define EXTI_CR3_EXTI10 (0x0FU << EXTI_CR3_EXTI10_Pos) ///< EXTI 10 configuration +#define EXTI_CR3_EXTI10_PA (0x00U << EXTI_CR3_EXTI10_Pos) ///< PA[10] pin +#define EXTI_CR3_EXTI10_PB (0x01U << EXTI_CR3_EXTI10_Pos) ///< PB[10] pin +#define EXTI_CR3_EXTI10_PC (0x02U << EXTI_CR3_EXTI10_Pos) ///< PC[10] pin +#define EXTI_CR3_EXTI10_PD (0x03U << EXTI_CR3_EXTI10_Pos) ///< PD[10] pin + +#define EXTI_CR3_EXTI11_Pos (12) +#define EXTI_CR3_EXTI11 (0x0FU << EXTI_CR3_EXTI11_Pos) ///< EXTI 11 configuration +#define EXTI_CR3_EXTI11_PA (0x00U << EXTI_CR3_EXTI11_Pos) ///< PA[11] pin +#define EXTI_CR3_EXTI11_PB (0x01U << EXTI_CR3_EXTI11_Pos) ///< PB[11] pin +#define EXTI_CR3_EXTI11_PC (0x02U << EXTI_CR3_EXTI11_Pos) ///< PC[11] pin +#define EXTI_CR3_EXTI11_PD (0x03U << EXTI_CR3_EXTI11_Pos) ///< PD[11] pin + +//////////////////////////////////////////////////////////////////////////////// +/// @brief EXTI_CR4 Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define EXTI_CR4_EXTI12_Pos (0) +#define EXTI_CR4_EXTI12 (0x0FU << EXTI_CR4_EXTI12_Pos) ///< EXTI 12 configuration +#define EXTI_CR4_EXTI12_PA (0x00U << EXTI_CR4_EXTI12_Pos) ///< PA[12] pin +#define EXTI_CR4_EXTI12_PB (0x01U << EXTI_CR4_EXTI12_Pos) ///< PB[12] pin +#define EXTI_CR4_EXTI12_PC (0x02U << EXTI_CR4_EXTI12_Pos) ///< PC[12] pin +#define EXTI_CR4_EXTI12_PD (0x03U << EXTI_CR4_EXTI12_Pos) ///< PD[12] pin + +#define EXTI_CR4_EXTI13_Pos (4) +#define EXTI_CR4_EXTI13 (0x0FU << EXTI_CR4_EXTI13_Pos) ///< EXTI 13 configuration +#define EXTI_CR4_EXTI13_PA (0x00U << EXTI_CR4_EXTI13_Pos) ///< PA[13] pin +#define EXTI_CR4_EXTI13_PB (0x01U << EXTI_CR4_EXTI13_Pos) ///< PB[13] pin +#define EXTI_CR4_EXTI13_PC (0x02U << EXTI_CR4_EXTI13_Pos) ///< PC[13] pin +#define EXTI_CR4_EXTI13_PD (0x03U << EXTI_CR4_EXTI13_Pos) ///< PD[13] pin + +#define EXTI_CR4_EXTI14_Pos (8) +#define EXTI_CR4_EXTI14 (0x0FU << EXTI_CR4_EXTI14_Pos) ///< EXTI 14 configuration +#define EXTI_CR4_EXTI14_PA (0x00U << EXTI_CR4_EXTI14_Pos) ///< PA[14] pin +#define EXTI_CR4_EXTI14_PB (0x01U << EXTI_CR4_EXTI14_Pos) ///< PB[14] pin +#define EXTI_CR4_EXTI14_PC (0x02U << EXTI_CR4_EXTI14_Pos) ///< PC[14] pin +#define EXTI_CR4_EXTI14_PD (0x03U << EXTI_CR4_EXTI14_Pos) ///< PD[14] pin + +#define EXTI_CR4_EXTI15_Pos (12) +#define EXTI_CR4_EXTI15 (0x0FU << EXTI_CR4_EXTI15_Pos) ///< EXTI 15 configuration +#define EXTI_CR4_EXTI15_PA (0x00U << EXTI_CR4_EXTI15_Pos) ///< PA[15] pin +#define EXTI_CR4_EXTI15_PB (0x01U << EXTI_CR4_EXTI15_Pos) ///< PB[15] pin +#define EXTI_CR4_EXTI15_PC (0x02U << EXTI_CR4_EXTI15_Pos) ///< PC[15] pin +#define EXTI_CR4_EXTI15_PD (0x03U << EXTI_CR4_EXTI15_Pos) ///< PD[15] pin +//////////////////////////////////////////////////////////////////////////////// +/// @brief EXTI_CFGR2 Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define EXTI_CFGR2_I2C1_Pos (16) +#define EXTI_CFGR2_I2C1_OD (0x00U << EXTI_CFGR2_I2C1_Pos) ///< Select open drain mode +#define EXTI_CFGR2_I2C1_PP (0x01U << EXTI_CFGR2_I2C1_Pos) ///< Select Push-pull mode +#define EXTI_CFGR2_I2C2_Pos (17) +#define EXTI_CFGR2_I2C2_OD (0x00U << EXTI_CFGR2_I2C2_Pos) ///< Select open drain mode +#define EXTI_CFGR2_I2C2_PP (0x01U << EXTI_CFGR2_I2C2_Pos) ///< Select Push-pull mode +#define EXTI_CFGR2_ETPHY_Pos (20) +#define EXTI_CFGR2_ETPHY_MII (0x00U << EXTI_CFGR2_ETPHY_Pos) ///< Select MII port +#define EXTI_CFGR2_ETPHY_RMII (0x01U << EXTI_CFGR2_ETPHY_Pos) ///< Select RMII port +#define EXTI_CFGR2_MAC_SPD_Pos (20) +#define EXTI_CFGR2_MAC_SPD_10 (0x00U << EXTI_CFGR2_ETPHY_Pos) ///< Select MAC_SPD 10 Mbps +#define EXTI_CFGR2_MAC_SPD_100 (0x01U << EXTI_CFGR2_ETPHY_Pos) ///< Select MAC_SPD 100 Mbps +//////////////////////////////////////////////////////////////////////////////// +/// @brief EXTI_PDETCSR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define EXTI_PDETCSR_PVDE_Pos (0) +#define EXTI_PDETCSR_PVDE (0x01U << EXTI_PDETCSR_PVDE_Pos) ///< PVD Enable +#define EXTI_PDETCSR_PLS_Pos (1) +#define EXTI_PDETCSR_PLS_1_7 (0x00U << EXTI_PDETCSR_PLS_Pos) ///< PVD 1.7mV +#define EXTI_PDETCSR_PLS_2_0 (0x01U << EXTI_PDETCSR_PLS_Pos) ///< PVD 2.0mV +#define EXTI_PDETCSR_PLS_2_3 (0x02U << EXTI_PDETCSR_PLS_Pos) ///< PVD 2.3mV +#define EXTI_PDETCSR_PLS_2_6 (0x03U << EXTI_PDETCSR_PLS_Pos) ///< PVD 2.6mV +#define EXTI_PDETCSR_PLS_2_9 (0x04U << EXTI_PDETCSR_PLS_Pos) ///< PVD 2.9mV +#define EXTI_PDETCSR_PLS_3_2 (0x05U << EXTI_PDETCSR_PLS_Pos) ///< PVD 3.2mV +#define EXTI_PDETCSR_PLS_3_5 (0x06U << EXTI_PDETCSR_PLS_Pos) ///< PVD 3.5mV +#define EXTI_PDETCSR_PLS_3_8 (0x07U << EXTI_PDETCSR_PLS_Pos) ///< PVD 3.8mV +#define EXTI_PDETCSR_PLS_4_1 (0x08U << EXTI_PDETCSR_PLS_Pos) ///< PVD 4.1mV +#define EXTI_PDETCSR_PLS_4_4 (0x09U << EXTI_PDETCSR_PLS_Pos) ///< PVD 4.4mV +#define EXTI_PDETCSR_PLS_4_7 (0x0AU << EXTI_PDETCSR_PLS_Pos) ///< PVD 4.7mV +#define EXTI_PDETCSR_PVDO_Pos (5) +#define EXTI_PDETCSR_PVDO (0x01U << EXTI_PDETCSR_PVDO_Pos) ///< PVD Output state +#define EXTI_PDETCSR_VDTO_Pos (6) +#define EXTI_PDETCSR_VDTO (0x01U << EXTI_PDETCSR_VDTO_Pos) ///< VDTO Output state +#define EXTI_PDETCSR_VDTE_Pos (8) +#define EXTI_PDETCSR_VDTE (0x01U << EXTI_PDETCSR_VDTE_Pos) ///< VDT Enable +#define EXTI_PDETCSR_VDTLS_Pos (9) +#define EXTI_PDETCSR_VDTLS0 (0x00U << EXTI_PDETCSR_VDTLS_Pos) ///< select VDT 0.9V +#define EXTI_PDETCSR_VDTLS1 (0x01U << EXTI_PDETCSR_VDTLS_Pos) ///< select VDT 1.0V +#define EXTI_PDETCSR_VDTLS2 (0x02U << EXTI_PDETCSR_VDTLS_Pos) ///< select VDT 1.1V +#define EXTI_PDETCSR_VDTLS3 (0x03U << EXTI_PDETCSR_VDTLS_Pos) ///< select VDT 1.2V +#define EXTI_PDETCSR_VBATDIV3_Pos (11) +#define EXTI_PDETCSR_VBATDIV3 (0x01U << EXTI_PDETCSR_VBATDIV3_Pos) ///< PVD Enable +//////////////////////////////////////////////////////////////////////////////// +/// @brief EXTI_VOSDLY Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define EXTI_EXTI_VOSDLY (0x3FFU) ///< VOS delay time + +//////////////////////////////////////////////////////////////////////////////// +/// @brief EXTI_IMR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define EXTI_IMR_0_Pos (0) +#define EXTI_IMR_0 (0x01U << EXTI_IMR_0_Pos) ///< Interrupt Mask on line 0 +#define EXTI_IMR_1_Pos (1) +#define EXTI_IMR_1 (0x01U << EXTI_IMR_1_Pos) ///< Interrupt Mask on line 1 +#define EXTI_IMR_2_Pos (2) +#define EXTI_IMR_2 (0x01U << EXTI_IMR_2_Pos) ///< Interrupt Mask on line 2 +#define EXTI_IMR_3_Pos (3) +#define EXTI_IMR_3 (0x01U << EXTI_IMR_3_Pos) ///< Interrupt Mask on line 3 +#define EXTI_IMR_4_Pos (4) +#define EXTI_IMR_4 (0x01U << EXTI_IMR_4_Pos) ///< Interrupt Mask on line 4 +#define EXTI_IMR_5_Pos (5) +#define EXTI_IMR_5 (0x01U << EXTI_IMR_5_Pos) ///< Interrupt Mask on line 5 +#define EXTI_IMR_6_Pos (6) +#define EXTI_IMR_6 (0x01U << EXTI_IMR_6_Pos) ///< Interrupt Mask on line 6 +#define EXTI_IMR_7_Pos (7) +#define EXTI_IMR_7 (0x01U << EXTI_IMR_7_Pos) ///< Interrupt Mask on line 7 +#define EXTI_IMR_8_Pos (8) +#define EXTI_IMR_8 (0x01U << EXTI_IMR_8_Pos) ///< Interrupt Mask on line 8 +#define EXTI_IMR_9_Pos (9) +#define EXTI_IMR_9 (0x01U << EXTI_IMR_9_Pos) ///< Interrupt Mask on line 9 +#define EXTI_IMR_10_Pos (10) +#define EXTI_IMR_10 (0x01U << EXTI_IMR_10_Pos) ///< Interrupt Mask on line 10 +#define EXTI_IMR_11_Pos (11) +#define EXTI_IMR_11 (0x01U << EXTI_IMR_11_Pos) ///< Interrupt Mask on line 11 +#define EXTI_IMR_12_Pos (12) +#define EXTI_IMR_12 (0x01U << EXTI_IMR_12_Pos) ///< Interrupt Mask on line 12 +#define EXTI_IMR_13_Pos (13) +#define EXTI_IMR_13 (0x01U << EXTI_IMR_13_Pos) ///< Interrupt Mask on line 13 +#define EXTI_IMR_14_Pos (14) +#define EXTI_IMR_14 (0x01U << EXTI_IMR_14_Pos) ///< Interrupt Mask on line 14 +#define EXTI_IMR_15_Pos (15) +#define EXTI_IMR_15 (0x01U << EXTI_IMR_15_Pos) ///< Interrupt Mask on line 15 +#define EXTI_IMR_16_Pos (16) +#define EXTI_IMR_16 (0x01U << EXTI_IMR_16_Pos) ///< Interrupt Mask on line 16 + + + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief EXTI_EMR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define EXTI_EMR_0_Pos (0) +#define EXTI_EMR_0 (0x01U << EXTI_EMR_0_Pos) ///< Event Mask on line 0 +#define EXTI_EMR_1_Pos (1) +#define EXTI_EMR_1 (0x01U << EXTI_EMR_1_Pos) ///< Event Mask on line 1 +#define EXTI_EMR_2_Pos (2) +#define EXTI_EMR_2 (0x01U << EXTI_EMR_2_Pos) ///< Event Mask on line 2 +#define EXTI_EMR_3_Pos (3) +#define EXTI_EMR_3 (0x01U << EXTI_EMR_3_Pos) ///< Event Mask on line 3 +#define EXTI_EMR_4_Pos (4) +#define EXTI_EMR_4 (0x01U << EXTI_EMR_4_Pos) ///< Event Mask on line 4 +#define EXTI_EMR_5_Pos (5) +#define EXTI_EMR_5 (0x01U << EXTI_EMR_5_Pos) ///< Event Mask on line 5 +#define EXTI_EMR_6_Pos (6) +#define EXTI_EMR_6 (0x01U << EXTI_EMR_6_Pos) ///< Event Mask on line 6 +#define EXTI_EMR_7_Pos (7) +#define EXTI_EMR_7 (0x01U << EXTI_EMR_7_Pos) ///< Event Mask on line 7 +#define EXTI_EMR_8_Pos (8) +#define EXTI_EMR_8 (0x01U << EXTI_EMR_8_Pos) ///< Event Mask on line 8 +#define EXTI_EMR_9_Pos (9) +#define EXTI_EMR_9 (0x01U << EXTI_EMR_9_Pos) ///< Event Mask on line 9 +#define EXTI_EMR_10_Pos (10) +#define EXTI_EMR_10 (0x01U << EXTI_EMR_10_Pos) ///< Event Mask on line 10 +#define EXTI_EMR_11_Pos (11) +#define EXTI_EMR_11 (0x01U << EXTI_EMR_11_Pos) ///< Event Mask on line 11 +#define EXTI_EMR_12_Pos (12) +#define EXTI_EMR_12 (0x01U << EXTI_EMR_12_Pos) ///< Event Mask on line 12 +#define EXTI_EMR_13_Pos (13) +#define EXTI_EMR_13 (0x01U << EXTI_EMR_13_Pos) ///< Event Mask on line 13 +#define EXTI_EMR_14_Pos (14) +#define EXTI_EMR_14 (0x01U << EXTI_EMR_14_Pos) ///< Event Mask on line 14 +#define EXTI_EMR_15_Pos (15) +#define EXTI_EMR_15 (0x01U << EXTI_EMR_15_Pos) ///< Event Mask on line 15 +#define EXTI_EMR_16_Pos (16) +#define EXTI_EMR_16 (0x01U << EXTI_EMR_16_Pos) ///< Event Mask on line 16 + + + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief EXTI_RTSR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define EXTI_RTSR_0_Pos (0) +#define EXTI_RTSR_0 (0x01U << EXTI_RTSR_0_Pos) ///< Rising trigger event configuration bit of line 0 +#define EXTI_RTSR_1_Pos (1) +#define EXTI_RTSR_1 (0x01U << EXTI_RTSR_1_Pos) ///< Rising trigger event configuration bit of line 1 +#define EXTI_RTSR_2_Pos (2) +#define EXTI_RTSR_2 (0x01U << EXTI_RTSR_2_Pos) ///< Rising trigger event configuration bit of line 2 +#define EXTI_RTSR_3_Pos (3) +#define EXTI_RTSR_3 (0x01U << EXTI_RTSR_3_Pos) ///< Rising trigger event configuration bit of line 3 +#define EXTI_RTSR_4_Pos (4) +#define EXTI_RTSR_4 (0x01U << EXTI_RTSR_4_Pos) ///< Rising trigger event configuration bit of line 4 +#define EXTI_RTSR_5_Pos (5) +#define EXTI_RTSR_5 (0x01U << EXTI_RTSR_5_Pos) ///< Rising trigger event configuration bit of line 5 +#define EXTI_RTSR_6_Pos (6) +#define EXTI_RTSR_6 (0x01U << EXTI_RTSR_6_Pos) ///< Rising trigger event configuration bit of line 6 +#define EXTI_RTSR_7_Pos (7) +#define EXTI_RTSR_7 (0x01U << EXTI_RTSR_7_Pos) ///< Rising trigger event configuration bit of line 7 +#define EXTI_RTSR_8_Pos (8) +#define EXTI_RTSR_8 (0x01U << EXTI_RTSR_8_Pos) ///< Rising trigger event configuration bit of line 8 +#define EXTI_RTSR_9_Pos (9) +#define EXTI_RTSR_9 (0x01U << EXTI_RTSR_9_Pos) ///< Rising trigger event configuration bit of line 9 +#define EXTI_RTSR_10_Pos (10) +#define EXTI_RTSR_10 (0x01U << EXTI_RTSR_10_Pos) ///< Rising trigger event configuration bit of line 10 +#define EXTI_RTSR_11_Pos (11) +#define EXTI_RTSR_11 (0x01U << EXTI_RTSR_11_Pos) ///< Rising trigger event configuration bit of line 11 +#define EXTI_RTSR_12_Pos (12) +#define EXTI_RTSR_12 (0x01U << EXTI_RTSR_12_Pos) ///< Rising trigger event configuration bit of line 12 +#define EXTI_RTSR_13_Pos (13) +#define EXTI_RTSR_13 (0x01U << EXTI_RTSR_13_Pos) ///< Rising trigger event configuration bit of line 13 +#define EXTI_RTSR_14_Pos (14) +#define EXTI_RTSR_14 (0x01U << EXTI_RTSR_14_Pos) ///< Rising trigger event configuration bit of line 14 +#define EXTI_RTSR_15_Pos (15) +#define EXTI_RTSR_15 (0x01U << EXTI_RTSR_15_Pos) ///< Rising trigger event configuration bit of line 15 +#define EXTI_RTSR_16_Pos (16) +#define EXTI_RTSR_16 (0x01U << EXTI_RTSR_16_Pos) ///< Rising trigger event configuration bit of line 16 + + + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief EXTI_FTSR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define EXTI_FTSR_0_Pos (0) +#define EXTI_FTSR_0 (0x01U << EXTI_FTSR_0_Pos) ///< Falling trigger event configuration bit of line 0 +#define EXTI_FTSR_1_Pos (1) +#define EXTI_FTSR_1 (0x01U << EXTI_FTSR_1_Pos) ///< Falling trigger event configuration bit of line 1 +#define EXTI_FTSR_2_Pos (2) +#define EXTI_FTSR_2 (0x01U << EXTI_FTSR_2_Pos) ///< Falling trigger event configuration bit of line 2 +#define EXTI_FTSR_3_Pos (3) +#define EXTI_FTSR_3 (0x01U << EXTI_FTSR_3_Pos) ///< Falling trigger event configuration bit of line 3 +#define EXTI_FTSR_4_Pos (4) +#define EXTI_FTSR_4 (0x01U << EXTI_FTSR_4_Pos) ///< Falling trigger event configuration bit of line 4 +#define EXTI_FTSR_5_Pos (5) +#define EXTI_FTSR_5 (0x01U << EXTI_FTSR_5_Pos) ///< Falling trigger event configuration bit of line 5 +#define EXTI_FTSR_6_Pos (6) +#define EXTI_FTSR_6 (0x01U << EXTI_FTSR_6_Pos) ///< Falling trigger event configuration bit of line 6 +#define EXTI_FTSR_7_Pos (7) +#define EXTI_FTSR_7 (0x01U << EXTI_FTSR_7_Pos) ///< Falling trigger event configuration bit of line 7 +#define EXTI_FTSR_8_Pos (8) +#define EXTI_FTSR_8 (0x01U << EXTI_FTSR_8_Pos) ///< Falling trigger event configuration bit of line 8 +#define EXTI_FTSR_9_Pos (9) +#define EXTI_FTSR_9 (0x01U << EXTI_FTSR_9_Pos) ///< Falling trigger event configuration bit of line 9 +#define EXTI_FTSR_10_Pos (10) +#define EXTI_FTSR_10 (0x01U << EXTI_FTSR_10_Pos) ///< Falling trigger event configuration bit of line 10 +#define EXTI_FTSR_11_Pos (11) +#define EXTI_FTSR_11 (0x01U << EXTI_FTSR_11_Pos) ///< Falling trigger event configuration bit of line 11 +#define EXTI_FTSR_12_Pos (12) +#define EXTI_FTSR_12 (0x01U << EXTI_FTSR_12_Pos) ///< Falling trigger event configuration bit of line 12 +#define EXTI_FTSR_13_Pos (13) +#define EXTI_FTSR_13 (0x01U << EXTI_FTSR_13_Pos) ///< Falling trigger event configuration bit of line 13 +#define EXTI_FTSR_14_Pos (14) +#define EXTI_FTSR_14 (0x01U << EXTI_FTSR_14_Pos) ///< Falling trigger event configuration bit of line 14 +#define EXTI_FTSR_15_Pos (15) +#define EXTI_FTSR_15 (0x01U << EXTI_FTSR_15_Pos) ///< Falling trigger event configuration bit of line 15 +#define EXTI_FTSR_16_Pos (16) +#define EXTI_FTSR_16 (0x01U << EXTI_FTSR_16_Pos) ///< Falling trigger event configuration bit of line 16 + + + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief EXTI_SWIER Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define EXTI_SWIER_0_Pos (0) +#define EXTI_SWIER_0 (0x01U << EXTI_SWIER_0_Pos) ///< Software Interrupt on line 0 +#define EXTI_SWIER_1_Pos (1) +#define EXTI_SWIER_1 (0x01U << EXTI_SWIER_1_Pos) ///< Software Interrupt on line 1 +#define EXTI_SWIER_2_Pos (2) +#define EXTI_SWIER_2 (0x01U << EXTI_SWIER_2_Pos) ///< Software Interrupt on line 2 +#define EXTI_SWIER_3_Pos (3) +#define EXTI_SWIER_3 (0x01U << EXTI_SWIER_3_Pos) ///< Software Interrupt on line 3 +#define EXTI_SWIER_4_Pos (4) +#define EXTI_SWIER_4 (0x01U << EXTI_SWIER_4_Pos) ///< Software Interrupt on line 4 +#define EXTI_SWIER_5_Pos (5) +#define EXTI_SWIER_5 (0x01U << EXTI_SWIER_5_Pos) ///< Software Interrupt on line 5 +#define EXTI_SWIER_6_Pos (6) +#define EXTI_SWIER_6 (0x01U << EXTI_SWIER_6_Pos) ///< Software Interrupt on line 6 +#define EXTI_SWIER_7_Pos (7) +#define EXTI_SWIER_7 (0x01U << EXTI_SWIER_7_Pos) ///< Software Interrupt on line 7 +#define EXTI_SWIER_8_Pos (8) +#define EXTI_SWIER_8 (0x01U << EXTI_SWIER_8_Pos) ///< Software Interrupt on line 8 +#define EXTI_SWIER_9_Pos (9) +#define EXTI_SWIER_9 (0x01U << EXTI_SWIER_9_Pos) ///< Software Interrupt on line 9 +#define EXTI_SWIER_10_Pos (10) +#define EXTI_SWIER_10 (0x01U << EXTI_SWIER_10_Pos) ///< Software Interrupt on line 10 +#define EXTI_SWIER_11_Pos (11) +#define EXTI_SWIER_11 (0x01U << EXTI_SWIER_11_Pos) ///< Software Interrupt on line 11 +#define EXTI_SWIER_12_Pos (12) +#define EXTI_SWIER_12 (0x01U << EXTI_SWIER_12_Pos) ///< Software Interrupt on line 12 +#define EXTI_SWIER_13_Pos (13) +#define EXTI_SWIER_13 (0x01U << EXTI_SWIER_13_Pos) ///< Software Interrupt on line 13 +#define EXTI_SWIER_14_Pos (14) +#define EXTI_SWIER_14 (0x01U << EXTI_SWIER_14_Pos) ///< Software Interrupt on line 14 +#define EXTI_SWIER_15_Pos (15) +#define EXTI_SWIER_15 (0x01U << EXTI_SWIER_15_Pos) ///< Software Interrupt on line 15 +#define EXTI_SWIER_16_Pos (16) +#define EXTI_SWIER_16 (0x01U << EXTI_SWIER_16_Pos) ///< Software Interrupt on line 16 + + + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief EXTI_PR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define EXTI_PR_0_Pos (0) +#define EXTI_PR_0 (0x01U << EXTI_PR_0_Pos) ///< Pending bit 0 +#define EXTI_PR_1_Pos (1) +#define EXTI_PR_1 (0x01U << EXTI_PR_1_Pos) ///< Pending bit 1 +#define EXTI_PR_2_Pos (2) +#define EXTI_PR_2 (0x01U << EXTI_PR_2_Pos) ///< Pending bit 2 +#define EXTI_PR_3_Pos (3) +#define EXTI_PR_3 (0x01U << EXTI_PR_3_Pos) ///< Pending bit 3 +#define EXTI_PR_4_Pos (4) +#define EXTI_PR_4 (0x01U << EXTI_PR_4_Pos) ///< Pending bit 4 +#define EXTI_PR_5_Pos (5) +#define EXTI_PR_5 (0x01U << EXTI_PR_5_Pos) ///< Pending bit 5 +#define EXTI_PR_6_Pos (6) +#define EXTI_PR_6 (0x01U << EXTI_PR_6_Pos) ///< Pending bit 6 +#define EXTI_PR_7_Pos (7) +#define EXTI_PR_7 (0x01U << EXTI_PR_7_Pos) ///< Pending bit 7 +#define EXTI_PR_8_Pos (8) +#define EXTI_PR_8 (0x01U << EXTI_PR_8_Pos) ///< Pending bit 8 +#define EXTI_PR_9_Pos (9) +#define EXTI_PR_9 (0x01U << EXTI_PR_9_Pos) ///< Pending bit 9 +#define EXTI_PR_10_Pos (10) +#define EXTI_PR_10 (0x01U << EXTI_PR_10_Pos) ///< Pending bit 10 +#define EXTI_PR_11_Pos (11) +#define EXTI_PR_11 (0x01U << EXTI_PR_11_Pos) ///< Pending bit 11 +#define EXTI_PR_12_Pos (12) +#define EXTI_PR_12 (0x01U << EXTI_PR_12_Pos) ///< Pending bit 12 +#define EXTI_PR_13_Pos (13) +#define EXTI_PR_13 (0x01U << EXTI_PR_13_Pos) ///< Pending bit 13 +#define EXTI_PR_14_Pos (14) +#define EXTI_PR_14 (0x01U << EXTI_PR_14_Pos) ///< Pending bit 14 +#define EXTI_PR_15_Pos (15) +#define EXTI_PR_15 (0x01U << EXTI_PR_15_Pos) ///< Pending bit 15 +#define EXTI_PR_16_Pos (16) +#define EXTI_PR_16 (0x01U << EXTI_PR_16_Pos) ///< Pending bit 16 + + + + + + + + + + +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +#endif +//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_flash.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_flash.h new file mode 100644 index 000000000..b95acef60 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_flash.h @@ -0,0 +1,290 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file reg_flash.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF +/// MM32 FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion + +#ifndef __REG_FLASH_H +#define __REG_FLASH_H + +// Files includes + +#include +#include +#include "types.h" + + + + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief MM32 MCU Memory/Peripherals mapping +//////////////////////////////////////////////////////////////////////////////// +#define FLASH_BASE (0x08000000U) ///< FLASH base address in the alias region +#define SRAM_BASE (0x20000000U) ///< SRAM base address in the alias region + +#define CACHE_BASE (APB2PERIPH_BASE + 0x6000) ///< Base Address: 0x40016000 + +//////////////////////////////////////////////////////////////////////////////// +/// @brief FLASH Base Address Definition +//////////////////////////////////////////////////////////////////////////////// +#define FLASH_REG_BASE (AHBPERIPH_BASE + 0x2000) ///< Base Address: 0x40022000 +//////////////////////////////////////////////////////////////////////////////// +/// @brief OPTB Base Address Definition +//////////////////////////////////////////////////////////////////////////////// +#define OB_BASE (0x1FFFF800U) ///< Flash Option Bytes base address +#define PROTECT_BASE (0x1FFE0000U) ///< Flash Protect Bytes base address + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief FLASH Registers Structure Definition +//////////////////////////////////////////////////////////////////////////////// +typedef struct { + __IO u32 ACR; ///< Access control Register offset: 0x00 + __IO u32 KEYR; ///< Key Register offset: 0x04 + __IO u32 OPTKEYR; ///< Option byte key Register offset: 0x08 + __IO u32 SR; ///< State Register offset: 0x0C + __IO u32 CR; ///< Control Register offset: 0x10 + __IO u32 AR; ///< Address Register offset: 0x14 + __IO u32 RESERVED; + __IO u32 OBR; ///< Option bytes Register offset: 0x1C + __IO u32 WRPR; ///< Write protect Register offset: 0x20 +} FLASH_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief OPT Structure Definition +//////////////////////////////////////////////////////////////////////////////// +typedef struct { + __IO u16 RDP; ///< Read Protect, offset: 0x00 + __IO u16 USER; ///< User option byte, offset: 0x02 + __IO u16 Data0; ///< User data 0, offset: 0x04 + __IO u16 Data1; ///< User data 1, offset: 0x06 + __IO u16 WRP0; ///< Flash write protection option byte 0, offset: 0x08 + __IO u16 WRP1; ///< Flash write protection option byte 1, offset: 0x0A + __IO u16 WRP2; ///< Flash write protection option byte 2, offset: 0x0C + __IO u16 WRP3; ///< Flash write protection option byte 3, offset: 0x0E +} OB_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief PROTECT BYTES Structure Definition +//////////////////////////////////////////////////////////////////////////////// +typedef struct { + __IO u16 PROTECT_LEN0; ///< The length of Protect byte 0, offset: 0x00 + __IO u16 PROTECT_ADDR0; ///< Data of Protect byte 0, offset: 0x02 + __IO u16 PROTECT_LEN1; ///< The length of Protect byte 1, offset: 0x04 + __IO u16 PROTECT_ADDR1; ///< Data of Protect byte 1, offset: 0x06 + __IO u16 PROTECT_LEN2; ///< The length of Protect byte 2, offset: 0x08 + __IO u16 PROTECT_ADDR2; ///< Data of Protect byte 2, offset: 0x0A + __IO u16 PROTECT_LEN3; ///< The length of Protect byte 3, offset: 0x0C + __IO u16 PROTECT_ADDR3; ///< Data of Protect byte 3, offset: 0x0E +} PROTECT_TypeDef; +//////////////////////////////////////////////////////////////////////////////// +/// @brief CACHE BYTES Structure Definition +//////////////////////////////////////////////////////////////////////////////// + +typedef struct { + __IO u32 CCR; ///< Configuration and control register offset: 0x00 + __IO u32 SR; ///< Status register offset: 0x04 + __IO u32 IMR; ///< Interrupt mask register offset: 0x08 + __IO u32 ISR; ///< Interrupt status register offset: 0x0C + __IO u32 RESERVED0; ///< offset: 0x10 + __IO u32 CSHR; ///< Hit Statistics Register offset: 0x14 + __IO u32 CSMR; ///< Lost Statistics Register offset: 0x18 +} CACHE_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief FLASH type pointer Definition +//////////////////////////////////////////////////////////////////////////////// +#define FLASH ((FLASH_TypeDef*) FLASH_REG_BASE) +//////////////////////////////////////////////////////////////////////////////// +/// @brief OPTB type pointer Definition +//////////////////////////////////////////////////////////////////////////////// +#define OB ((OB_TypeDef*) OB_BASE) +#define PROTECT ((PROTECT_TypeDef*) PROTECT_BASE) +//////////////////////////////////////////////////////////////////////////////// +/// @brief CACHE pointer Definition +//////////////////////////////////////////////////////////////////////////////// +#define CACHE ((CACHE_TypeDef*) CACHE_BASE) +//////////////////////////////////////////////////////////////////////////////// +/// @brief FLASH_ACR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define FLASH_ACR_LATENCY_Pos (0) +#define FLASH_ACR_LATENCY (0x07U << FLASH_ACR_LATENCY_Pos) ///< LATENCY[2:0] bits (Latency) +#define FLASH_ACR_LATENCY_0 (0x00U << FLASH_ACR_LATENCY_Pos) ///< 0 waiting state +#define FLASH_ACR_LATENCY_1 (0x01U << FLASH_ACR_LATENCY_Pos) ///< 1 waiting state +#define FLASH_ACR_LATENCY_2 (0x02U << FLASH_ACR_LATENCY_Pos) ///< 2 waiting state +#define FLASH_ACR_LATENCY_3 (0x03U << FLASH_ACR_LATENCY_Pos) ///< 3 waiting state +#define FLASH_ACR_HLFCYA_Pos (3) +#define FLASH_ACR_HLFCYA (0x01U << FLASH_ACR_HLFCYA_Pos) ///< Flash Half Cycle Access Enable +#define FLASH_ACR_PRFTBE_Pos (4) +#define FLASH_ACR_PRFTBE (0x01U << FLASH_ACR_PRFTBE_Pos) ///< Prefetch Buffer Enable +#define FLASH_ACR_PRFTBS_Pos (5) +#define FLASH_ACR_PRFTBS (0x01U << FLASH_ACR_PRFTBS_Pos) ///< Prefetch Buffer Status +//////////////////////////////////////////////////////////////////////////////// +/// @brief FLASH_KEYR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define FLASH_KEYR_FKEY_Pos (0) +#define FLASH_KEYR_FKEY (0xFFFFFFFFU << FLASH_KEYR_FKEY_Pos) ///< FLASH Key + +//////////////////////////////////////////////////////////////////////////////// +/// @brief FLASH_OPTKEYR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define FLASH_OPTKEYR_OPTKEY_Pos (0) +#define FLASH_OPTKEYR_OPTKEY (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEY_Pos) ///< Option Byte Key + +//////////////////////////////////////////////////////////////////////////////// +/// @brief FLASH_SR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define FLASH_SR_BUSY_Pos (0) +#define FLASH_SR_BUSY (0x01U << FLASH_SR_BUSY_Pos) ///< Busy +#define FLASH_SR_PGERR_Pos (2) +#define FLASH_SR_PGERR (0x01U << FLASH_SR_PGERR_Pos) ///< Programming Error +#define FLASH_SR_WRPRTERR_Pos (4) +#define FLASH_SR_WRPRTERR (0x01U << FLASH_SR_WRPRTERR_Pos) ///< Write Protection Error +#define FLASH_SR_EOP_Pos (5) +#define FLASH_SR_EOP (0x01U << FLASH_SR_EOP_Pos) ///< End of operation + +//////////////////////////////////////////////////////////////////////////////// +/// @brief FLASH_CR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define FLASH_CR_PG_Pos (0) +#define FLASH_CR_PG (0x01U << FLASH_CR_PG_Pos) ///< Programming +#define FLASH_CR_PER_Pos (1) +#define FLASH_CR_PER (0x01U << FLASH_CR_PER_Pos) ///< Page Erase +#define FLASH_CR_MER_Pos (2) +#define FLASH_CR_MER (0x01U << FLASH_CR_MER_Pos) ///< Mass Erase +#define FLASH_CR_OPTPG_Pos (4) +#define FLASH_CR_OPTPG (0x01U << FLASH_CR_OPTPG_Pos) ///< Option Byte Programming +#define FLASH_CR_OPTER_Pos (5) +#define FLASH_CR_OPTER (0x01U << FLASH_CR_OPTER_Pos) ///< Option Byte Erase +#define FLASH_CR_STRT_Pos (6) +#define FLASH_CR_STRT (0x01U << FLASH_CR_STRT_Pos) ///< Start +#define FLASH_CR_LOCK_Pos (7) +#define FLASH_CR_LOCK (0x01U << FLASH_CR_LOCK_Pos) ///< Lock +#define FLASH_CR_OPTWRE_Pos (9) +#define FLASH_CR_OPTWRE (0x01U << FLASH_CR_OPTWRE_Pos) ///< Option Bytes Write Enable +#define FLASH_CR_ERRIE_Pos (10) +#define FLASH_CR_ERRIE (0x01U << FLASH_CR_ERRIE_Pos) ///< Error Interrupt Enable +#define FLASH_CR_EOPIE_Pos (12) +#define FLASH_CR_EOPIE (0x01U << FLASH_CR_EOPIE_Pos) ///< End of operation interrupt enable + +//////////////////////////////////////////////////////////////////////////////// +/// @brief FLASH_AR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define FLASH_AR_FAR_Pos (0) +#define FLASH_AR_FAR (0xFFFFFFFFU << FLASH_AR_FAR_Pos) ///< Flash Address + +//////////////////////////////////////////////////////////////////////////////// +/// @brief FLASH_OBR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define FLASH_OBR_OPTERR_Pos (0) +#define FLASH_OBR_OPTERR (0x01U << FLASH_OBR_OPTERR_Pos) ///< Option Byte Error +#define FLASH_OBR_RDPRT_Pos (1) +#define FLASH_OBR_RDPRT (0x01U << FLASH_OBR_RDPRT_Pos) ///< Read protection level status +#define FLASH_OBR_USER_Pos (2) +#define FLASH_OBR_USER (0xFFU << FLASH_OBR_USER_Pos) ///< User Option Bytes + +#define FLASH_OBR_WDG_SW (0x01U << FLASH_OBR_USER_Pos) ///< WDG_SW +#define FLASH_OBR_RST_STOP (0x02U << FLASH_OBR_USER_Pos) ///< nRST_STOP +#define FLASH_OBR_RST_STDBY (0x04U << FLASH_OBR_USER_Pos) ///< nRST_STDBY + + +#define FLASH_OBR_Data0_Pos (10) +#define FLASH_OBR_Data0 (0xFFU << FLASH_OBR_Data0_Pos) ///< User data storage option byte +#define FLASH_OBR_Data1_Pos (18) +#define FLASH_OBR_Data1 (0xFFU << FLASH_OBR_Data1_Pos) ///< User data storage option byte + +//////////////////////////////////////////////////////////////////////////////// +/// @brief FLASH_WRPR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define FLASH_WRPR_WRP_Pos (0) +#define FLASH_WRPR_WRP (0xFFFFFFFFU << FLASH_WRPR_WRP_Pos) ///< Write Protect + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief CACHE_CCR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define CACHE_CCR_EN_Pos (0) +#define CACHE_CCR_EN (0x01U << CACHE_CCR_EN_Pos) ///< Cache Enable +#define CACHE_CCR_INV_Pos (1) +#define CACHE_CCR_INV (0x01U << CACHE_CCR_INV_REQ_Pos) ///< Manually invalidate the request +#define CACHE_CCR_POW_Pos (2) +#define CACHE_CCR_POW (0x01U << CACHE_CCR_POW_REQ_Pos) ///< Manual SRAM power request +#define CACHE_CCR_MAN_POW_Pos (3) +#define CACHE_CCR_MAN_POW (0x01U << CACHE_CCR_MAN_POW_Pos) ///< Set manual or automatic SRAM power request +#define CACHE_CCR_MAN_INV_Pos (4) +#define CACHE_CCR_MAN_INV (0x01U << CACHE_CCR_MAN_INV_Pos) ///< Manually or automatically disable it +#define CACHE_CCR_PREFETCH_Pos (5) +#define CACHE_CCR_PREFETCH (0x01U << CACHE_CCR_PREFETCH_Pos) ///< Prefetch function +#define CACHE_CCR_STATISTIC_Pos (6) +#define CACHE_CCR_STATISTIC (0x01U << CACHE_CCR_STATISTIC_Pos) ///< Statistics enable +//////////////////////////////////////////////////////////////////////////////// +/// @brief CACHE_SR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define CACHE_SR_CS_Pos (0) +#define CACHE_SR_CS0 (0x00U << CACHE_CCR_CS_Pos) ///< Cache is disabled +#define CACHE_SR_CS1 (0x01U << CACHE_CCR_CS_Pos) ///< Cache is being enabled +#define CACHE_SR_CS2 (0x02U << CACHE_CCR_CS_Pos) ///< Cache is enabled +#define CACHE_SR_CS3 (0x03U << CACHE_CCR_CS_Pos) ///< Cache is being disabled +#define CACHE_SR_INV_Pos (2) +#define CACHE_SR_INV (0x01U << CACHE_CCR_INV_REQ_Pos) ///< Invalidation status +#define CACHE_SR_POW_Pos (4) +#define CACHE_SR_POW (0x01U << CACHE_CCR_POW_REQ_Pos) ///< SRAM power response +//////////////////////////////////////////////////////////////////////////////// +/// @brief CACHE_IMR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define CACHE_IMR_MAN_INV_Pos (0) +#define CACHE_IMR_MAN_INV (0x01U << CACHE_IMR_MAN_INV_Pos) ///< Mask the interrupt request of manual invalidation error +#define CACHE_IMR_POW_Pos (1) +#define CACHE_IMR_POW (0x01U << CACHE_IMR_POW_Pos) ///< Mask the interrupt request of power supply error +//////////////////////////////////////////////////////////////////////////////// +/// @brief CACHE_ISR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define CACHE_ISR_MAN_INV_Pos (0) +#define CACHE_ISR_MAN_INV (0x01U << CACHE_ISR_MAN_INV_Pos) ///< Manual invalidation of error flags +#define CACHE_ISR_POW_Pos (1) +#define CACHE_ISR_POW (0x01U << CACHE_ISR_POW_Pos) ///< SRAM power error flags +//////////////////////////////////////////////////////////////////////////////// +/// @brief CACHE_CSHR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define CACHE_CSHR (0xFFFFU ) ///< Cache Hits +//////////////////////////////////////////////////////////////////////////////// +/// @brief CACHE_CSHR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define CACHE_CSMR (0xFFFFU ) ///< Cache Lost times + + + + + + + +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +#endif +//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_fsmc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_fsmc.h new file mode 100644 index 000000000..77870dd1e --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_fsmc.h @@ -0,0 +1,194 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file reg_fsmc.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF +/// MM32 FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion + +#ifndef __REG_FSMC_H +#define __REG_FSMC_H + +// Files includes + +#include +#include +#include "types.h" + + + + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief FLASH Base Address Definition +//////////////////////////////////////////////////////////////////////////////// + +#define FSMC_BANK1_ADDR (0x60000000UL ) +#define FSMC_BANK2_ADDR (0x60000000UL + 0x4000000 ) +#define FSMC_BANK3_ADDR (0x60000000UL + 0x8000000 ) +#define FSMC_BANK4_ADDR (0x60000000UL + 0xc000000 ) +#define FSMC_BASE (0x60000000UL + 0x40000000) ///< Base Address: 0xA0000000 + +//////////////////////////////////////////////////////////////////////////////// +/// @brief FSMC Registers Structure Definition +//////////////////////////////////////////////////////////////////////////////// + +typedef struct { + __IO u32 Reservedoffset0x00; ///< Reserved Register offset: 0x00 + __IO u32 Reservedoffset0x04; ///< Reserved Register offset: 0x04 + __IO u32 Reservedoffset0x08; ///< Reserved Register offset: 0x08 + __IO u32 Reservedoffset0x0c; ///< Reserved Register offset: 0x0c + __IO u32 Reservedoffset0x10; ///< Reserved Register offset: 0x10 + __IO u32 Reservedoffset0x14; ///< Reserved Register offset: 0x14 + __IO u32 Reservedoffset0x18; ///< Reserved Register offset: 0x18 + __IO u32 Reservedoffset0x1c; ///< Reserved Register offset: 0x1c + __IO u32 Reservedoffset0x20; ///< Reserved Register offset: 0x20 + __IO u32 Reservedoffset0x24; ///< Reserved Register offset: 0x24 + __IO u32 Reservedoffset0x28; ///< Reserved Register offset: 0x28 + __IO u32 Reservedoffset0x2c; ///< Reserved Register offset: 0x2c + __IO u32 Reservedoffset0x30; ///< Reserved Register offset: 0x30 + __IO u32 Reservedoffset0x34; ///< Reserved Register offset: 0x34 + __IO u32 Reservedoffset0x38; ///< Reserved Register offset: 0x38 + __IO u32 Reservedoffset0x3c; ///< Reserved Register offset: 0x3c + __IO u32 Reservedoffset0x40; ///< Reserved Register offset: 0x40 + __IO u32 Reservedoffset0x44; ///< Reserved Register offset: 0x44 + __IO u32 Reservedoffset0x48; ///< Reserved Register offset: 0x48 + __IO u32 Reservedoffset0x4c; ///< Reserved Register offset: 0x4c + __IO u32 Reservedoffset0x50; ///< Reserved Register offset: 0x50 + __IO u32 SMSKR; ///< SMSKR control Register offset: 0x54 + __IO u32 Reservedoffset0x58; ///< Reserved Register offset: 0x58 + __IO u32 Reservedoffset0x5c; ///< Reserved Register offset: 0x5c + __IO u32 Reservedoffset0x60; ///< Reserved Register offset: 0x60 + __IO u32 Reservedoffset0x64; ///< Reserved Register offset: 0x64 + __IO u32 Reservedoffset0x68; ///< Reserved Register offset: 0x68 + __IO u32 Reservedoffset0x6c; ///< Reserved Register offset: 0x6c + __IO u32 Reservedoffset0x70; ///< Reserved Register offset: 0x70 + __IO u32 Reservedoffset0x74; ///< Reserved Register offset: 0x74 + __IO u32 Reservedoffset0x78; ///< Reserved Register offset: 0x78 + __IO u32 Reservedoffset0x7c; ///< Reserved Register offset: 0x7c + __IO u32 Reservedoffset0x80; ///< Reserved Register offset: 0x80 + __IO u32 Reservedoffset0x84; ///< Reserved Register offset: 0x84 + __IO u32 Reservedoffset0x88; ///< Reserved Register offset: 0x88 + __IO u32 Reservedoffset0x8c; ///< Reserved Register offset: 0x8c + __IO u32 Reservedoffset0x90; ///< Reserved Register offset: 0x90 + __IO u32 SMTMGR_SET0; ///< SMTMGR_SET Register 0 offset: 0x94 + __IO u32 SMTMGR_SET1; ///< SMTMGR_SET Register 1 offset: 0x98 + __IO u32 SMTMGR_SET2; ///< SMTMGR_SET Register 2 offset: 0x9c + __IO u32 Reservedoffset0xA0; ///< Reserved Register offset: 0xa0 + __IO u32 SMCTLR; ///< Reserved Register offset: 0xa4 + __IO u32 Reservedoffset0xA8; ///< Reserved Register offset: 0xa8 + __IO u32 Reservedoffset0xAC; ///< Reserved Register offset: 0xac +} FSMC_TypeDef; + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief FSMC type pointer Definition +//////////////////////////////////////////////////////////////////////////////// +#define FSMC ((FSMC_TypeDef*) FSMC_BASE) + +//////////////////////////////////////////////////////////////////////////////// +/// @brief FSMC_SMSKR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define FSMC_SMSKR_REG_SELECT_Pos (8) +#define FSMC_SMSKR_REG_SELECT0 (0x00U << FSMC_SMSKR_REG_SELECT_Pos) ///< timing parameter configures the register group 0 +#define FSMC_SMSKR_REG_SELECT1 (0x01U << FSMC_SMSKR_REG_SELECT_Pos) ///< timing parameter configures the register group 1 +#define FSMC_SMSKR_REG_SELECT2 (0x02U << FSMC_SMSKR_REG_SELECT_Pos) ///< timing parameter configures the register group 2 +#define FSMC_SMSKR_MEM_TYPE_Pos (5) +#define FSMC_SMSKR_MEM_TYPE0 (0x00U << FSMC_SMSKR_MEM_TYPE_Pos) ///< SDRAM +#define FSMC_SMSKR_MEM_TYPE1 (0x01U << FSMC_SMSKR_MEM_TYPE_Pos) ///< SRAM +#define FSMC_SMSKR_MEM_TYPE2 (0x02U << FSMC_SMSKR_MEM_TYPE_Pos) ///< FLASH +#define FSMC_SMSKR_MEM_SIZE_Pos (0) +#define FSMC_SMSKR_MEM_SIZE_64K (0x01U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 64KB +#define FSMC_SMSKR_MEM_SIZE_128K (0x02U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 128KB +#define FSMC_SMSKR_MEM_SIZE_256K (0x03U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 256KB +#define FSMC_SMSKR_MEM_SIZE_512K (0x04U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 512KB +#define FSMC_SMSKR_MEM_SIZE_1M (0x05U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 1MB +#define FSMC_SMSKR_MEM_SIZE_2M (0x06U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 2MB +#define FSMC_SMSKR_MEM_SIZE_4M (0x07U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 4MB +#define FSMC_SMSKR_MEM_SIZE_8M (0x08U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 8MB +#define FSMC_SMSKR_MEM_SIZE_16M (0x09U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 16MB +#define FSMC_SMSKR_MEM_SIZE_32M (0x10U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 32MB +#define FSMC_SMSKR_MEM_SIZE_64M (0x11U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 64MB +#define FSMC_SMSKR_MEM_SIZE_128M (0x12U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 128MB +#define FSMC_SMSKR_MEM_SIZE_256M (0x13U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 256MB +#define FSMC_SMSKR_MEM_SIZE_512M (0x14U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 512MB +#define FSMC_SMSKR_MEM_SIZE_1G (0x15U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 1GB +#define FSMC_SMSKR_MEM_SIZE_2G (0x16U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 2GB +#define FSMC_SMSKR_MEM_SIZE_4G (0x17U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 4GB + +//////////////////////////////////////////////////////////////////////////////// +/// @brief FSMC_SMTMGR_SET0/1/2 Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define FSMC_SMTMGR_SET_SM_READ_PIPE_Pos (28) +#define FSMC_SMTMGR_SET_SM_READ_PIPE (0x03U << FSMC_SMTMGR_SET_SM_READ_PIPE_Pos) ///< The period of the latched read data +#define FSMC_SMTMGR_SET_LOW_FREG_SYNC_DEVICE_Pos (27) +#define FSMC_SMTMGR_SET_LOW_FREG_SYNC_DEVICE (0x01U << FSMC_SMTMGR_SET_LOW_FREG_SYNC_DEVICE_Pos) ///< Access low frequency synchronization devices +#define FSMC_SMTMGR_SET_READ_MODE_Pos (26) +#define FSMC_SMTMGR_SET_READ_MODE (0x01U << FSMC_SMTMGR_SET_READ_MODE_Pos) ///< The Hready_RESP signal is from an external DEVICE +#define FSMC_SMTMGR_SET_T_WP_Pos (10) +#define FSMC_SMTMGR_SET_T_WP (0x3FU << FSMC_SMTMGR_SET_T_WP_Pos) ///< Write pulse width 64 clock cycles +#define FSMC_SMTMGR_SET_T_WR_Pos (8) +#define FSMC_SMTMGR_SET_T_WR (0x03U << FSMC_SMTMGR_SET_T_WR_Pos) ///< Address/data retention time for write operations is 3 clock cycles +#define FSMC_SMTMGR_SET_T_AS_Pos (6) +#define FSMC_SMTMGR_SET_T_AS (0x03U << FSMC_SMTMGR_SET_T_AS_Pos) ///< The address establishment time of write operation is 3 clock cycles +#define FSMC_SMTMGR_SET_T_RC_Pos (0) +#define FSMC_SMTMGR_SET_T_RC (0x3FU << FSMC_SMTMGR_SET_T_RC_Pos) ///< Read operation cycle 64 clock cycles + +//////////////////////////////////////////////////////////////////////////////// +/// @brief FSMC_SMCTLR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos (13) +#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2 (0x07U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos) +#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_16 (0x00U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos) ///< Memory data bus bit width 16 bits +#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_32 (0x01U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos) ///< Memory data bus bit width 32 bits +#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_64 (0x02U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos) ///< Memory data bus bit width 64 bits +#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_128 (0x03U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos) ///< Memory data bus bit width 128 bits +#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_8 (0x04U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos) ///< Memory data bus bit width 8 bits +#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos (10) +#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1 (0x07U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos) +#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_16 (0x00U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos) ///< Memory data bus bit width 16 bits +#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_32 (0x01U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos) ///< Memory data bus bit width 32 bits +#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_64 (0x02U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos) ///< Memory data bus bit width 64 bits +#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_128 (0x03U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos) ///< Memory data bus bit width 128 bits +#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_8 (0x04U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos) ///< Memory data bus bit width 8 bits +#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos (7) +#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0 (0x07U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos) +#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_16 (0x00U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos) ///< Memory data bus bit width 16 bits +#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_32 (0x01U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos) ///< Memory data bus bit width 32 bits +#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_64 (0x02U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos) ///< Memory data bus bit width 64 bits +#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_128 (0x03U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos) ///< Memory data bus bit width 128 bits +#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_8 (0x04U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos) ///< Memory data bus bit width 8 bits + + + + + + +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +#endif //__REG_FSMC_H +//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_gpio.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_gpio.h new file mode 100644 index 000000000..44e043bac --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_gpio.h @@ -0,0 +1,706 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file reg_gpio.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF +/// MM32 FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion + +#ifndef __REG_GPIO_H +#define __REG_GPIO_H + +// Files includes + +#include +#include +#include "types.h" + + + + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + + + + + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief GPIO Base Address Definition +//////////////////////////////////////////////////////////////////////////////// + +#define GPIOA_BASE (AHBPERIPH_BASE + 0x0020000) ///< Base Address: 0x40040000 +#define GPIOB_BASE (AHBPERIPH_BASE + 0x0020400) ///< Base Address: 0x40040400 +#define GPIOC_BASE (AHBPERIPH_BASE + 0x0020800) ///< Base Address: 0x40040800 +#define GPIOD_BASE (AHBPERIPH_BASE + 0x0020C00) ///< Base Address: 0x40040C00 +#define GPIOE_BASE (AHBPERIPH_BASE + 0x0021000) ///< Base Address: 0x40041000 +#define GPIOF_BASE (AHBPERIPH_BASE + 0x0021400) ///< Base Address: 0x40041400 +#define GPIOG_BASE (AHBPERIPH_BASE + 0x0021800) ///< Base Address: 0x40041800 +#define GPIOH_BASE (AHBPERIPH_BASE + 0x0021C00) ///< Base Address: 0x40041C00 + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief GPIO Registers Structure Definition +//////////////////////////////////////////////////////////////////////////////// +typedef struct { + __IO u32 CRL; ///< Control Register Low, offset: 0x00 + __IO u32 CRH; ///< Control Register High, offset: 0x04 + __IO u32 IDR; ///< Input Data Register, offset: 0x08 + __IO u32 ODR; ///< Output Data Register, offset: 0x0C + __IO u32 BSRR; ///< Bit Set or Reset Register, offset: 0x10 + __IO u32 BRR; ///< Bit Reset Register, offset: 0x14 + __IO u32 LCKR; ///< Lock Register, offset: 0x18 + __IO u32 DCR; ///< Pin Output Open Drain Config Register, offset: 0x1C + __IO u32 AFRL; ///< Port Multiplexing Function Low Register, offset: 0x20 + __IO u32 AFRH; ///< Port Multiplexing Function High Register, offset: 0x24 +} GPIO_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief GPIO type pointer Definition +//////////////////////////////////////////////////////////////////////////////// +#define GPIOA ((GPIO_TypeDef*) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef*) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef*) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef*) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef*) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef*) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef*) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef*) GPIOH_BASE) + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief GPIO Common Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// + + + + +#define GPIO_CNF_MODE_AIN 0x00UL //0b0000, ///< Analog input +#define GPIO_CNF_MODE_FLOATING 0x04UL //0b0100, ///< Floating input +#define GPIO_CNF_MODE_INPUPD 0x08UL //0b1000, ///< Pull up and down input +#define GPIO_CNF_MODE_INRESEVED 0x0CUL //0b1100, ///< Reseved input mode +#define GPIO_CNF_MODE_OUT_PP 0x01UL //0b0001, ///< Universal push-pull output default +#define GPIO_CNF_MODE_OUT_OD 0x05UL //0b0101, ///< Universal open drain output default +#define GPIO_CNF_MODE_AF_PP 0x09UL //0b1001, ///< Multiplex push-pull output default +#define GPIO_CNF_MODE_AF_OD 0x0DUL //0b1101 ///< Multiplex open drain output default +#define GPIO_CNF_MODE_50MHZ_OUT_PP 0x01UL //0b0001, ///< Universal push-pull output 50MHZ +#define GPIO_CNF_MODE_50MHZ_OUT_OD 0x05UL //0b0101, ///< Universal open drain output 50MHZ +#define GPIO_CNF_MODE_50MHZ_AF_PP 0x09UL //0b1001, ///< Multiplex push-pull output 50MHZ +#define GPIO_CNF_MODE_50MHZ_AF_OD 0x0DUL //0b1101 ///< Multiplex open drain output 50MHZ +#define GPIO_CNF_MODE_20MHZ_OUT_PP 0x02UL //0b0010, ///< Universal push-pull output 20MHZ +#define GPIO_CNF_MODE_20MHZ_OUT_OD 0x06UL //0b0110, ///< Universal open drain output 20MHZ +#define GPIO_CNF_MODE_20MHZ_AF_PP 0x0AUL //0b1010, ///< Multiplex push-pull output 20MHZ +#define GPIO_CNF_MODE_20MHZ_AF_OD 0x0EUL //0b1110 ///< Multiplex open drain output 20MHZ +#define GPIO_CNF_MODE_10MHZ_OUT_PP 0x03UL //0b0011, ///< Universal push-pull output 10MHZ +#define GPIO_CNF_MODE_10MHZ_OUT_OD 0x07UL //0b0111, ///< Universal open drain output 10MHZ +#define GPIO_CNF_MODE_10MHZ_AF_PP 0x0BUL //0b1011, ///< Multiplex push-pull output 10MHZ +#define GPIO_CNF_MODE_10MHZ_AF_OD 0x0FUL //0b1111 ///< Multiplex open drain output 10MHZ +#define GPIO_CNF_MODE_MASK 0x0FUL //0b1111 + +#define GPIO_CRL_CNF_MODE_0_Pos (0) // ///< Analog input +#define GPIO_CRL_CNF_MODE_1_Pos (4) // ///< Floating input +#define GPIO_CRL_CNF_MODE_2_Pos (8) // ///< Pull up and down input +#define GPIO_CRL_CNF_MODE_3_Pos (12) // ///< Reseved input mode +#define GPIO_CRL_CNF_MODE_4_Pos (16) // ///< Universal push-pull output default +#define GPIO_CRL_CNF_MODE_5_Pos (20) // ///< Universal open drain output default +#define GPIO_CRL_CNF_MODE_6_Pos (24) // ///< Multiplex push-pull output default +#define GPIO_CRL_CNF_MODE_7_Pos (28) // ///< Multiplex open drain output default +#define GPIO_CRH_CNF_MODE_8_Pos (0) // ///< Universal push-pull output 50MHZ +#define GPIO_CRH_CNF_MODE_9_Pos (4) // ///< Universal open drain output 50MHZ +#define GPIO_CRH_CNF_MODE_10_Pos (8) // ///< Multiplex push-pull output 50MHZ +#define GPIO_CRH_CNF_MODE_11_Pos (12) // ///< Multiplex open drain output 50MHZ +#define GPIO_CRH_CNF_MODE_12_Pos (16) // ///< Universal push-pull output 20MHZ +#define GPIO_CRH_CNF_MODE_13_Pos (20) // ///< Universal open drain output 20MHZ +#define GPIO_CRH_CNF_MODE_14_Pos (24) // ///< Multiplex push-pull output 20MHZ +#define GPIO_CRH_CNF_MODE_15_Pos (28) // ///< Multiplex open drain output 20MHZ + +//////////////////////////////////////////////////////////////////////////////// +/// @brief GPIO_CRL Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define GPIO_CRL_MODE ((u32)0x33333333) ///< Port x mode bits + +#define GPIO_CRL_MODE0_Pos (0) +#define GPIO_CRL_MODE0 (0x03U << GPIO_CRL_MODE0_Pos) ///< MODE0[1:0] bits (portx mode bits, pin 0) +#define GPIO_CRL_MODE0_0 (0x01U << GPIO_CRL_MODE0_Pos) ///< Bit 0 +#define GPIO_CRL_MODE0_1 (0x02U << GPIO_CRL_MODE0_Pos) ///< Bit 1 + +#define GPIO_CRL_CNF0_Pos (2) +#define GPIO_CRL_CNF0 (0x03U << GPIO_CRL_CNF0_Pos) ///< CNF0[1:0] bits (portx configuration bits, pin 0) +#define GPIO_CRL_CNF0_0 (0x01U << GPIO_CRL_CNF0_Pos) ///< Bit 0 +#define GPIO_CRL_CNF0_1 (0x02U << GPIO_CRL_CNF0_Pos) ///< Bit 1 + +#define GPIO_CRL_MODE1_Pos (4) +#define GPIO_CRL_MODE1 (0x03U << GPIO_CRL_MODE1_Pos) ///< MODE1[1:0] bits (portx mode bits, pin 1) +#define GPIO_CRL_MODE1_0 (0x01U << GPIO_CRL_MODE1_Pos) ///< Bit 0 +#define GPIO_CRL_MODE1_1 (0x02U << GPIO_CRL_MODE1_Pos) ///< Bit 1 + +#define GPIO_CRL_CNF1_Pos (6) +#define GPIO_CRL_CNF1 (0x03U << GPIO_CRL_CNF1_Pos) ///< CNF1[1:0] bits (portx configuration bits, pin 1) +#define GPIO_CRL_CNF1_0 (0x01U << GPIO_CRL_CNF1_Pos) ///< Bit 0 +#define GPIO_CRL_CNF1_1 (0x02U << GPIO_CRL_CNF1_Pos) ///< Bit 1 + +#define GPIO_CRL_MODE2_Pos (8) +#define GPIO_CRL_MODE2 (0x03U << GPIO_CRL_MODE2_Pos) ///< MODE2[1:0] bits (portx mode bits, pin 2) +#define GPIO_CRL_MODE2_0 (0x01U << GPIO_CRL_MODE2_Pos) ///< Bit 0 +#define GPIO_CRL_MODE2_1 (0x02U << GPIO_CRL_MODE2_Pos) ///< Bit 1 + +#define GPIO_CRL_CNF2_Pos (10) +#define GPIO_CRL_CNF2 (0x03U << GPIO_CRL_CNF2_Pos) ///< CNF2[1:0] bits (portx configuration bits, pin 2) +#define GPIO_CRL_CNF2_0 (0x01U << GPIO_CRL_CNF2_Pos) ///< Bit 0 +#define GPIO_CRL_CNF2_1 (0x02U << GPIO_CRL_CNF2_Pos) ///< Bit 1 + +#define GPIO_CRL_MODE3_Pos (12) +#define GPIO_CRL_MODE3 (0x03U << GPIO_CRL_MODE3_Pos) ///< MODE3[1:0] bits (portx mode bits, pin 3) +#define GPIO_CRL_MODE3_0 (0x01U << GPIO_CRL_MODE3_Pos) ///< Bit 0 +#define GPIO_CRL_MODE3_1 (0x02U << GPIO_CRL_MODE3_Pos) ///< Bit 1 + +#define GPIO_CRL_CNF3_Pos (14) +#define GPIO_CRL_CNF3 (0x03U << GPIO_CRL_CNF3_Pos) ///< CNF3[1:0] bits (portx configuration bits, pin 3) +#define GPIO_CRL_CNF3_0 (0x01U << GPIO_CRL_CNF3_Pos) ///< Bit 0 +#define GPIO_CRL_CNF3_1 (0x02U << GPIO_CRL_CNF3_Pos) ///< Bit 1 + + +#define GPIO_CRL_MODE4_Pos (16) +#define GPIO_CRL_MODE4 (0x03U << GPIO_CRL_MODE4_Pos) ///< MODE4[1:0] bits (portx mode bits, pin 4) +#define GPIO_CRL_MODE4_0 (0x01U << GPIO_CRL_MODE4_Pos) ///< Bit 0 +#define GPIO_CRL_MODE4_1 (0x02U << GPIO_CRL_MODE4_Pos) ///< Bit 1 + +#define GPIO_CRL_CNF4_Pos (18) +#define GPIO_CRL_CNF4 (0x03U << GPIO_CRL_CNF4_Pos) ///< CNF4[1:0] bits (portx configuration bits, pin 4) +#define GPIO_CRL_CNF4_0 (0x01U << GPIO_CRL_CNF4_Pos) ///< Bit 0 +#define GPIO_CRL_CNF4_1 (0x02U << GPIO_CRL_CNF4_Pos) ///< Bit 1 + +#define GPIO_CRL_MODE5_Pos (20) +#define GPIO_CRL_MODE5 (0x03U << GPIO_CRL_MODE5_Pos) ///< MODE5[1:0] bits (portx mode bits, pin 5) +#define GPIO_CRL_MODE5_0 (0x01U << GPIO_CRL_MODE5_Pos) ///< Bit 0 +#define GPIO_CRL_MODE5_1 (0x02U << GPIO_CRL_MODE5_Pos) ///< Bit 1 + +#define GPIO_CRL_CNF5_Pos (22) +#define GPIO_CRL_CNF5 (0x03U << GPIO_CRL_CNF5_Pos) ///< CNF5[1:0] bits (portx configuration bits, pin 5) +#define GPIO_CRL_CNF5_0 (0x01U << GPIO_CRL_CNF5_Pos) ///< Bit 0 +#define GPIO_CRL_CNF5_1 (0x02U << GPIO_CRL_CNF5_Pos) ///< Bit 1 + +#define GPIO_CRL_MODE6_Pos (24) +#define GPIO_CRL_MODE6 (0x03U << GPIO_CRL_MODE6_Pos) ///< MODE6[1:0] bits (portx mode bits, pin 6) +#define GPIO_CRL_MODE6_0 (0x01U << GPIO_CRL_MODE6_Pos) ///< Bit 0 +#define GPIO_CRL_MODE6_1 (0x02U << GPIO_CRL_MODE6_Pos) ///< Bit 1 + +#define GPIO_CRL_CNF6_Pos (26) +#define GPIO_CRL_CNF6 (0x03U << GPIO_CRL_CNF6_Pos) ///< CNF6[1:0] bits (portx configuration bits, pin 6) +#define GPIO_CRL_CNF6_0 (0x01U << GPIO_CRL_CNF6_Pos) ///< Bit 0 +#define GPIO_CRL_CNF6_1 (0x02U << GPIO_CRL_CNF6_Pos) ///< Bit 1 + +#define GPIO_CRL_MODE7_Pos (28) +#define GPIO_CRL_MODE7 (0x03U << GPIO_CRL_MODE7_Pos) ///< MODE7[1:0] bits (portx mode bits, pin 7) +#define GPIO_CRL_MODE7_0 (0x01U << GPIO_CRL_MODE7_Pos) ///< Bit 0 +#define GPIO_CRL_MODE7_1 (0x02U << GPIO_CRL_MODE7_Pos) ///< Bit 1 + +#define GPIO_CRL_CNF7_Pos (30) +#define GPIO_CRL_CNF7 (0x03U << GPIO_CRL_CNF7_Pos) ///< CNF7[1:0] bits (portx configuration bits, pin 7) +#define GPIO_CRL_CNF7_0 (0x01U << GPIO_CRL_CNF7_Pos) ///< Bit 0 +#define GPIO_CRL_CNF7_1 (0x02U << GPIO_CRL_CNF7_Pos) ///< Bit 1 + +//////////////////////////////////////////////////////////////////////////////// +/// @brief GPIO_CRH Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define GPIO_CRH_MODE ((u32)0x33333333) ///< Port x mode bits + +#define GPIO_CRH_MODE8_Pos (0) +#define GPIO_CRH_MODE8 (0x03U << GPIO_CRH_MODE8_Pos) ///< MODE8[1:0] bits (portx mode bits, pin 0) +#define GPIO_CRH_MODE8_0 (0x01U << GPIO_CRH_MODE8_Pos) ///< Bit 0 +#define GPIO_CRH_MODE8_1 (0x02U << GPIO_CRH_MODE8_Pos) ///< Bit 1 +#define GPIO_CRH_CNF8_Pos (2) +#define GPIO_CRH_CNF8 (0x03U << GPIO_CRH_CNF8_Pos) ///< CNF8[1:0] bits (portx configuration bits, pin 0) +#define GPIO_CRH_CNF8_0 (0x01U << GPIO_CRH_CNF8_Pos) ///< Bit 0 +#define GPIO_CRH_CNF8_1 (0x02U << GPIO_CRH_CNF8_Pos) ///< Bit 1 +#define GPIO_CRH_MODE9_Pos (4) +#define GPIO_CRH_MODE9 (0x03U << GPIO_CRH_MODE9_Pos) ///< MODE9[1:0] bits (portx mode bits, pin 1) +#define GPIO_CRH_MODE9_0 (0x01U << GPIO_CRH_MODE9_Pos) ///< Bit 0 +#define GPIO_CRH_MODE9_1 (0x02U << GPIO_CRH_MODE9_Pos) ///< Bit 1 +#define GPIO_CRH_CNF9_Pos (6) +#define GPIO_CRH_CNF9 (0x03U << GPIO_CRH_CNF9_Pos) ///< CNF9[1:0] bits (portx configuration bits, pin 1) +#define GPIO_CRH_CNF9_0 (0x01U << GPIO_CRH_CNF9_Pos) ///< Bit 0 +#define GPIO_CRH_CNF9_1 (0x02U << GPIO_CRH_CNF9_Pos) ///< Bit 1 +#define GPIO_CRH_MODE10_Pos (8) +#define GPIO_CRH_MODE10 (0x03U << GPIO_CRH_MODE10_Pos) ///< MODE10[1:0] bits (portx mode bits, pin 2) +#define GPIO_CRH_MODE10_0 (0x01U << GPIO_CRH_MODE10_Pos) ///< Bit 0 +#define GPIO_CRH_MODE10_1 (0x02U << GPIO_CRH_MODE10_Pos) ///< Bit 1 +#define GPIO_CRH_CNF10_Pos (10) +#define GPIO_CRH_CNF10 (0x03U << GPIO_CRH_CNF10_Pos) ///< CNF10[1:0] bits (portx configuration bits, pin 2) +#define GPIO_CRH_CNF10_0 (0x01U << GPIO_CRH_CNF10_Pos) ///< Bit 0 +#define GPIO_CRH_CNF10_1 (0x02U << GPIO_CRH_CNF10_Pos) ///< Bit 1 +#define GPIO_CRH_MODE11_Pos (12) +#define GPIO_CRH_MODE11 (0x03U << GPIO_CRH_MODE11_Pos) ///< MODE11[1:0] bits (portx mode bits, pin 3) +#define GPIO_CRH_MODE11_0 (0x01U << GPIO_CRH_MODE11_Pos) ///< Bit 0 +#define GPIO_CRH_MODE11_1 (0x02U << GPIO_CRH_MODE11_Pos) ///< Bit 1 +#define GPIO_CRH_CNF11_Pos (14) +#define GPIO_CRH_CNF11 (0x03U << GPIO_CRH_CNF11_Pos) ///< CNF11[1:0] bits (portx configuration bits, pin 3) +#define GPIO_CRH_CNF11_0 (0x01U << GPIO_CRH_CNF11_Pos) ///< Bit 0 +#define GPIO_CRH_CNF11_1 (0x02U << GPIO_CRH_CNF11_Pos) ///< Bit 1 +#define GPIO_CRH_MODE12_Pos (16) +#define GPIO_CRH_MODE12 (0x03U << GPIO_CRH_MODE12_Pos) ///< MODE12[1:0] bits (portx mode bits, pin 4) +#define GPIO_CRH_MODE12_0 (0x01U << GPIO_CRH_MODE12_Pos) ///< Bit 0 +#define GPIO_CRH_MODE12_1 (0x02U << GPIO_CRH_MODE12_Pos) ///< Bit 1 +#define GPIO_CRH_CNF12_Pos (18) +#define GPIO_CRH_CNF12 (0x03U << GPIO_CRH_CNF12_Pos) ///< CNF12[1:0] bits (portx configuration bits, pin 4) +#define GPIO_CRH_CNF12_0 (0x01U << GPIO_CRH_CNF12_Pos) ///< Bit 0 +#define GPIO_CRH_CNF12_1 (0x02U << GPIO_CRH_CNF12_Pos) ///< Bit 1 +#define GPIO_CRH_MODE13_Pos (20) +#define GPIO_CRH_MODE13 (0x03U << GPIO_CRH_MODE13_Pos) ///< MODE13[1:0] bits (portx mode bits, pin 5) +#define GPIO_CRH_MODE13_0 (0x01U << GPIO_CRH_MODE13_Pos) ///< Bit 0 +#define GPIO_CRH_MODE13_1 (0x02U << GPIO_CRH_MODE13_Pos) ///< Bit 1 +#define GPIO_CRH_CNF13_Pos (22) +#define GPIO_CRH_CNF13 (0x03U << GPIO_CRH_CNF13_Pos) ///< CNF13[1:0] bits (portx configuration bits, pin 5) +#define GPIO_CRH_CNF13_0 (0x01U << GPIO_CRH_CNF13_Pos) ///< Bit 0 +#define GPIO_CRH_CNF13_1 (0x02U << GPIO_CRH_CNF13_Pos) ///< Bit 1 +#define GPIO_CRH_MODE14_Pos (24) +#define GPIO_CRH_MODE14 (0x03U << GPIO_CRH_MODE14_Pos) ///< MODE14[1:0] bits (portx mode bits, pin 6) +#define GPIO_CRH_MODE14_0 (0x01U << GPIO_CRH_MODE14_Pos) ///< Bit 0 +#define GPIO_CRH_MODE14_1 (0x02U << GPIO_CRH_MODE14_Pos) ///< Bit 1 +#define GPIO_CRH_CNF14_Pos (26) +#define GPIO_CRH_CNF14 (0x03U << GPIO_CRH_CNF14_Pos) ///< CNF14[1:0] bits (portx configuration bits, pin 6) +#define GPIO_CRH_CNF14_0 (0x01U << GPIO_CRH_CNF14_Pos) ///< Bit 0 +#define GPIO_CRH_CNF14_1 (0x02U << GPIO_CRH_CNF14_Pos) ///< Bit 1 +#define GPIO_CRH_MODE15_Pos (28) +#define GPIO_CRH_MODE15 (0x03U << GPIO_CRH_MODE15_Pos) ///< MODE15[1:0] bits (portx mode bits, pin 7) +#define GPIO_CRH_MODE15_0 (0x01U << GPIO_CRH_MODE15_Pos) ///< Bit 0 +#define GPIO_CRH_MODE15_1 (0x02U << GPIO_CRH_MODE15_Pos) ///< Bit 1 +#define GPIO_CRH_CNF15_Pos (30) +#define GPIO_CRH_CNF15 (0x03U << GPIO_CRH_CNF15_Pos) ///< CNF15[1:0] bits (portx configuration bits, pin 7) +#define GPIO_CRH_CNF15_0 (0x01U << GPIO_CRH_CNF15_Pos) ///< Bit 0 +#define GPIO_CRH_CNF15_1 (0x02U << GPIO_CRH_CNF15_Pos) ///< Bit 1 + +//////////////////////////////////////////////////////////////////////////////// +/// @brief GPIO_IDR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define GPIO_IDR_DATA_Pos (0) +#define GPIO_IDR_DATA (0xFFFFU << GPIO_IDR_DATA_Pos) ///< Port input data +//////////////////////////////////////////////////////////////////////////////// +/// @brief GPIO_IDR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define GPIO_IDR_IDR0_Pos (0) +#define GPIO_IDR_IDR0 (0x01U << GPIO_IDR_IDR0_Pos) ///< Portx Set bit 0 +#define GPIO_IDR_IDR1_Pos (1) +#define GPIO_IDR_IDR1 (0x01U << GPIO_IDR_IDR1_Pos) ///< Portx Set bit 1 +#define GPIO_IDR_IDR2_Pos (2) +#define GPIO_IDR_IDR2 (0x01U << GPIO_IDR_IDR2_Pos) ///< Portx Set bit 2 +#define GPIO_IDR_IDR3_Pos (3) +#define GPIO_IDR_IDR3 (0x01U << GPIO_IDR_IDR3_Pos) ///< Portx Set bit 3 +#define GPIO_IDR_IDR4_Pos (4) +#define GPIO_IDR_IDR4 (0x01U << GPIO_IDR_IDR4_Pos) ///< Portx Set bit 4 +#define GPIO_IDR_IDR5_Pos (5) +#define GPIO_IDR_IDR5 (0x01U << GPIO_IDR_IDR5_Pos) ///< Portx Set bit 5 +#define GPIO_IDR_IDR6_Pos (6) +#define GPIO_IDR_IDR6 (0x01U << GPIO_IDR_IDR6_Pos) ///< Portx Set bit 6 +#define GPIO_IDR_IDR7_Pos (7) +#define GPIO_IDR_IDR7 (0x01U << GPIO_IDR_IDR7_Pos) ///< Portx Set bit 7 +#define GPIO_IDR_IDR8_Pos (8) +#define GPIO_IDR_IDR8 (0x01U << GPIO_IDR_IDR8_Pos) ///< Portx Set bit 8 +#define GPIO_IDR_IDR9_Pos (9) +#define GPIO_IDR_IDR9 (0x01U << GPIO_IDR_IDR9_Pos) ///< Portx Set bit 9 +#define GPIO_IDR_IDR10_Pos (10) +#define GPIO_IDR_IDR10 (0x01U << GPIO_IDR_IDR10_Pos) ///< Portx Set bit 10 +#define GPIO_IDR_IDR11_Pos (11) +#define GPIO_IDR_IDR11 (0x01U << GPIO_IDR_IDR11_Pos) ///< Portx Set bit 11 +#define GPIO_IDR_IDR12_Pos (12) +#define GPIO_IDR_IDR12 (0x01U << GPIO_IDR_IDR12_Pos) ///< Portx Set bit 12 +#define GPIO_IDR_IDR13_Pos (13) +#define GPIO_IDR_IDR13 (0x01U << GPIO_IDR_IDR13_Pos) ///< Portx Set bit 13 +#define GPIO_IDR_IDR14_Pos (14) +#define GPIO_IDR_IDR14 (0x01U << GPIO_IDR_IDR14_Pos) ///< Portx Set bit 14 +#define GPIO_IDR_IDR15_Pos (15) +#define GPIO_IDR_IDR15 (0x01U << GPIO_IDR_IDR15_Pos) ///< Portx Set bit 15 +//////////////////////////////////////////////////////////////////////////////// +/// @brief GPIO_ODR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define GPIO_ODR_DATA_Pos (0) +#define GPIO_ODR_DATA (0xFFFF << GPIO_ODR_DATA_Pos) ///< Port output data +//////////////////////////////////////////////////////////////////////////////// +/// @brief GPIO_ODR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define GPIO_ODR_ODR0_Pos (0) +#define GPIO_ODR_ODR0 (0x01U << GPIO_ODR_ODR0_Pos) ///< Portx Set bit 0 +#define GPIO_ODR_ODR1_Pos (1) +#define GPIO_ODR_ODR1 (0x01U << GPIO_ODR_ODR1_Pos) ///< Portx Set bit 1 +#define GPIO_ODR_ODR2_Pos (2) +#define GPIO_ODR_ODR2 (0x01U << GPIO_ODR_ODR2_Pos) ///< Portx Set bit 2 +#define GPIO_ODR_ODR3_Pos (3) +#define GPIO_ODR_ODR3 (0x01U << GPIO_ODR_ODR3_Pos) ///< Portx Set bit 3 +#define GPIO_ODR_ODR4_Pos (4) +#define GPIO_ODR_ODR4 (0x01U << GPIO_ODR_ODR4_Pos) ///< Portx Set bit 4 +#define GPIO_ODR_ODR5_Pos (5) +#define GPIO_ODR_ODR5 (0x01U << GPIO_ODR_ODR5_Pos) ///< Portx Set bit 5 +#define GPIO_ODR_ODR6_Pos (6) +#define GPIO_ODR_ODR6 (0x01U << GPIO_ODR_ODR6_Pos) ///< Portx Set bit 6 +#define GPIO_ODR_ODR7_Pos (7) +#define GPIO_ODR_ODR7 (0x01U << GPIO_ODR_ODR7_Pos) ///< Portx Set bit 7 +#define GPIO_ODR_ODR8_Pos (8) +#define GPIO_ODR_ODR8 (0x01U << GPIO_ODR_ODR8_Pos) ///< Portx Set bit 8 +#define GPIO_ODR_ODR9_Pos (9) +#define GPIO_ODR_ODR9 (0x01U << GPIO_ODR_ODR9_Pos) ///< Portx Set bit 9 +#define GPIO_ODR_ODR10_Pos (10) +#define GPIO_ODR_ODR10 (0x01U << GPIO_ODR_ODR10_Pos) ///< Portx Set bit 10 +#define GPIO_ODR_ODR11_Pos (11) +#define GPIO_ODR_ODR11 (0x01U << GPIO_ODR_ODR11_Pos) ///< Portx Set bit 11 +#define GPIO_ODR_ODR12_Pos (12) +#define GPIO_ODR_ODR12 (0x01U << GPIO_ODR_ODR12_Pos) ///< Portx Set bit 12 +#define GPIO_ODR_ODR13_Pos (13) +#define GPIO_ODR_ODR13 (0x01U << GPIO_ODR_ODR13_Pos) ///< Portx Set bit 13 +#define GPIO_ODR_ODR14_Pos (14) +#define GPIO_ODR_ODR14 (0x01U << GPIO_ODR_ODR14_Pos) ///< Portx Set bit 14 +#define GPIO_ODR_ODR15_Pos (15) +#define GPIO_ODR_ODR15 (0x01U << GPIO_ODR_ODR15_Pos) ///< Portx Set bit 15 + +//////////////////////////////////////////////////////////////////////////////// +/// @brief GPIO_BRR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define GPIO_BSRR_BS_Pos (0) +#define GPIO_BSRR_BS (0xFFFFU << GPIO_BSRR_BS_Pos) ///< Portx Reset +//////////////////////////////////////////////////////////////////////////////// +/// @brief GPIO_BSRR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define GPIO_BSRR_BS0_Pos (0) +#define GPIO_BSRR_BS0 (0x01U << GPIO_BSRR_BS0_Pos) ///< Portx Set bit 0 +#define GPIO_BSRR_BS1_Pos (1) +#define GPIO_BSRR_BS1 (0x01U << GPIO_BSRR_BS1_Pos) ///< Portx Set bit 1 +#define GPIO_BSRR_BS2_Pos (2) +#define GPIO_BSRR_BS2 (0x01U << GPIO_BSRR_BS2_Pos) ///< Portx Set bit 2 +#define GPIO_BSRR_BS3_Pos (3) +#define GPIO_BSRR_BS3 (0x01U << GPIO_BSRR_BS3_Pos) ///< Portx Set bit 3 +#define GPIO_BSRR_BS4_Pos (4) +#define GPIO_BSRR_BS4 (0x01U << GPIO_BSRR_BS4_Pos) ///< Portx Set bit 4 +#define GPIO_BSRR_BS5_Pos (5) +#define GPIO_BSRR_BS5 (0x01U << GPIO_BSRR_BS5_Pos) ///< Portx Set bit 5 +#define GPIO_BSRR_BS6_Pos (6) +#define GPIO_BSRR_BS6 (0x01U << GPIO_BSRR_BS6_Pos) ///< Portx Set bit 6 +#define GPIO_BSRR_BS7_Pos (7) +#define GPIO_BSRR_BS7 (0x01U << GPIO_BSRR_BS7_Pos) ///< Portx Set bit 7 +#define GPIO_BSRR_BS8_Pos (8) +#define GPIO_BSRR_BS8 (0x01U << GPIO_BSRR_BS8_Pos) ///< Portx Set bit 8 +#define GPIO_BSRR_BS9_Pos (9) +#define GPIO_BSRR_BS9 (0x01U << GPIO_BSRR_BS9_Pos) ///< Portx Set bit 9 +#define GPIO_BSRR_BS10_Pos (10) +#define GPIO_BSRR_BS10 (0x01U << GPIO_BSRR_BS10_Pos) ///< Portx Set bit 10 +#define GPIO_BSRR_BS11_Pos (11) +#define GPIO_BSRR_BS11 (0x01U << GPIO_BSRR_BS11_Pos) ///< Portx Set bit 11 +#define GPIO_BSRR_BS12_Pos (12) +#define GPIO_BSRR_BS12 (0x01U << GPIO_BSRR_BS12_Pos) ///< Portx Set bit 12 +#define GPIO_BSRR_BS13_Pos (13) +#define GPIO_BSRR_BS13 (0x01U << GPIO_BSRR_BS13_Pos) ///< Portx Set bit 13 +#define GPIO_BSRR_BS14_Pos (14) +#define GPIO_BSRR_BS14 (0x01U << GPIO_BSRR_BS14_Pos) ///< Portx Set bit 14 +#define GPIO_BSRR_BS15_Pos (15) +#define GPIO_BSRR_BS15 (0x01U << GPIO_BSRR_BS15_Pos) ///< Portx Set bit 15 + +#define GPIO_BSRR_BR0_Pos (16) +#define GPIO_BSRR_BR0 (0x01U << GPIO_BSRR_BR0_Pos) ///< Portx Reset bit 0 +#define GPIO_BSRR_BR1_Pos (17) +#define GPIO_BSRR_BR1 (0x01U << GPIO_BSRR_BR1_Pos) ///< Portx Reset bit 1 +#define GPIO_BSRR_BR2_Pos (18) +#define GPIO_BSRR_BR2 (0x01U << GPIO_BSRR_BR2_Pos) ///< Portx Reset bit 2 +#define GPIO_BSRR_BR3_Pos (19) +#define GPIO_BSRR_BR3 (0x01U << GPIO_BSRR_BR3_Pos) ///< Portx Reset bit 3 +#define GPIO_BSRR_BR4_Pos (20) +#define GPIO_BSRR_BR4 (0x01U << GPIO_BSRR_BR4_Pos) ///< Portx Reset bit 4 +#define GPIO_BSRR_BR5_Pos (21) +#define GPIO_BSRR_BR5 (0x01U << GPIO_BSRR_BR5_Pos) ///< Portx Reset bit 5 +#define GPIO_BSRR_BR6_Pos (22) +#define GPIO_BSRR_BR6 (0x01U << GPIO_BSRR_BR6_Pos) ///< Portx Reset bit 6 +#define GPIO_BSRR_BR7_Pos (23) +#define GPIO_BSRR_BR7 (0x01U << GPIO_BSRR_BR7_Pos) ///< Portx Reset bit 7 +#define GPIO_BSRR_BR8_Pos (24) +#define GPIO_BSRR_BR8 (0x01U << GPIO_BSRR_BR8_Pos) ///< Portx Reset bit 8 +#define GPIO_BSRR_BR9_Pos (25) +#define GPIO_BSRR_BR9 (0x01U << GPIO_BSRR_BR9_Pos) ///< Portx Reset bit 9 +#define GPIO_BSRR_BR10_Pos (26) +#define GPIO_BSRR_BR10 (0x01U << GPIO_BSRR_BR10_Pos) ///< Portx Reset bit 10 +#define GPIO_BSRR_BR11_Pos (27) +#define GPIO_BSRR_BR11 (0x01U << GPIO_BSRR_BR11_Pos) ///< Portx Reset bit 11 +#define GPIO_BSRR_BR12_Pos (28) +#define GPIO_BSRR_BR12 (0x01U << GPIO_BSRR_BR12_Pos) ///< Portx Reset bit 12 +#define GPIO_BSRR_BR13_Pos (29) +#define GPIO_BSRR_BR13 (0x01U << GPIO_BSRR_BR13_Pos) ///< Portx Reset bit 13 +#define GPIO_BSRR_BR14_Pos (30) +#define GPIO_BSRR_BR14 (0x01U << GPIO_BSRR_BR14_Pos) ///< Portx Reset bit 14 +#define GPIO_BSRR_BR15_Pos (31) +#define GPIO_BSRR_BR15 (0x01U << GPIO_BSRR_BR15_Pos) ///< Portx Reset bit 15 + +//////////////////////////////////////////////////////////////////////////////// +/// @brief GPIO_BRR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define GPIO_BRR_BR_Pos (0) +#define GPIO_BRR_BR (0xFFFFU << GPIO_BRR_BR_Pos) ///< Portx Reset + +//////////////////////////////////////////////////////////////////////////////// +/// @brief GPIO_BRR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define GPIO_BRR_BR0_Pos (0) +#define GPIO_BRR_BR0 (0x01U << GPIO_BRR_BR0_Pos) ///< Portx Set bit 0 +#define GPIO_BRR_BR1_Pos (1) +#define GPIO_BRR_BR1 (0x01U << GPIO_BRR_BR1_Pos) ///< Portx Set bit 1 +#define GPIO_BRR_BR2_Pos (2) +#define GPIO_BRR_BR2 (0x01U << GPIO_BRR_BR2_Pos) ///< Portx Set bit 2 +#define GPIO_BRR_BR3_Pos (3) +#define GPIO_BRR_BR3 (0x01U << GPIO_BRR_BR3_Pos) ///< Portx Set bit 3 +#define GPIO_BRR_BR4_Pos (4) +#define GPIO_BRR_BR4 (0x01U << GPIO_BRR_BR4_Pos) ///< Portx Set bit 4 +#define GPIO_BRR_BR5_Pos (5) +#define GPIO_BRR_BR5 (0x01U << GPIO_BRR_BR5_Pos) ///< Portx Set bit 5 +#define GPIO_BRR_BR6_Pos (6) +#define GPIO_BRR_BR6 (0x01U << GPIO_BRR_BR6_Pos) ///< Portx Set bit 6 +#define GPIO_BRR_BR7_Pos (7) +#define GPIO_BRR_BR7 (0x01U << GPIO_BRR_BR7_Pos) ///< Portx Set bit 7 +#define GPIO_BRR_BR8_Pos (8) +#define GPIO_BRR_BR8 (0x01U << GPIO_BRR_BR8_Pos) ///< Portx Set bit 8 +#define GPIO_BRR_BR9_Pos (9) +#define GPIO_BRR_BR9 (0x01U << GPIO_BRR_BR9_Pos) ///< Portx Set bit 9 +#define GPIO_BRR_BR10_Pos (10) +#define GPIO_BRR_BR10 (0x01U << GPIO_BRR_BR10_Pos) ///< Portx Set bit 10 +#define GPIO_BRR_BR11_Pos (11) +#define GPIO_BRR_BR11 (0x01U << GPIO_BRR_BR11_Pos) ///< Portx Set bit 11 +#define GPIO_BRR_BR12_Pos (12) +#define GPIO_BRR_BR12 (0x01U << GPIO_BRR_BR12_Pos) ///< Portx Set bit 12 +#define GPIO_BRR_BR13_Pos (13) +#define GPIO_BRR_BR13 (0x01U << GPIO_BRR_BR13_Pos) ///< Portx Set bit 13 +#define GPIO_BRR_BR14_Pos (14) +#define GPIO_BRR_BR14 (0x01U << GPIO_BRR_BR14_Pos) ///< Portx Set bit 14 +#define GPIO_BRR_BR15_Pos (15) +#define GPIO_BRR_BR15 (0x01U << GPIO_BRR_BR15_Pos) ///< Portx Set bit 15 + +//////////////////////////////////////////////////////////////////////////////// +/// @brief GPIO_LCKR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define GPIO_LCKR_LCK_Pos (0) +#define GPIO_LCKR_LCK (0xFFFFU << GPIO_LCKR_LCK_Pos) ///< Portx Lock +#define GPIO_LCKR_LCKK_Pos (16) +#define GPIO_LCKR_LCKK (0x01U << GPIO_LCKR_LCKK_Pos) ///< Lock key + +//////////////////////////////////////////////////////////////////////////////// +/// @brief GPIO_LCKR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define GPIO_LCKR_LCK0_Pos (0) +#define GPIO_LCKR_LCK0 (0x01U << GPIO_LCKR_LCK0_Pos) ///< Portx Set bit 0 +#define GPIO_LCKR_LCK1_Pos (1) +#define GPIO_LCKR_LCK1 (0x01U << GPIO_LCKR_LCK1_Pos) ///< Portx Set bit 1 +#define GPIO_LCKR_LCK2_Pos (2) +#define GPIO_LCKR_LCK2 (0x01U << GPIO_LCKR_LCK2_Pos) ///< Portx Set bit 2 +#define GPIO_LCKR_LCK3_Pos (3) +#define GPIO_LCKR_LCK3 (0x01U << GPIO_LCKR_LCK3_Pos) ///< Portx Set bit 3 +#define GPIO_LCKR_LCK4_Pos (4) +#define GPIO_LCKR_LCK4 (0x01U << GPIO_LCKR_LCK4_Pos) ///< Portx Set bit 4 +#define GPIO_LCKR_LCK5_Pos (5) +#define GPIO_LCKR_LCK5 (0x01U << GPIO_LCKR_LCK5_Pos) ///< Portx Set bit 5 +#define GPIO_LCKR_LCK6_Pos (6) +#define GPIO_LCKR_LCK6 (0x01U << GPIO_LCKR_LCK6_Pos) ///< Portx Set bit 6 +#define GPIO_LCKR_LCK7_Pos (7) +#define GPIO_LCKR_LCK7 (0x01U << GPIO_LCKR_LCK7_Pos) ///< Portx Set bit 7 +#define GPIO_LCKR_LCK8_Pos (8) +#define GPIO_LCKR_LCK8 (0x01U << GPIO_LCKR_LCK8_Pos) ///< Portx Set bit 8 +#define GPIO_LCKR_LCK9_Pos (9) +#define GPIO_LCKR_LCK9 (0x01U << GPIO_LCKR_LCK9_Pos) ///< Portx Set bit 9 +#define GPIO_LCKR_LCK10_Pos (10) +#define GPIO_LCKR_LCK10 (0x01U << GPIO_LCKR_LCK10_Pos) ///< Portx Set bit 10 +#define GPIO_LCKR_LCK11_Pos (11) +#define GPIO_LCKR_LCK11 (0x01U << GPIO_LCKR_LCK11_Pos) ///< Portx Set bit 11 +#define GPIO_LCKR_LCK12_Pos (12) +#define GPIO_LCKR_LCK12 (0x01U << GPIO_LCKR_LCK12_Pos) ///< Portx Set bit 12 +#define GPIO_LCKR_LCK13_Pos (13) +#define GPIO_LCKR_LCK13 (0x01U << GPIO_LCKR_LCK13_Pos) ///< Portx Set bit 13 +#define GPIO_LCKR_LCK14_Pos (14) +#define GPIO_LCKR_LCK14 (0x01U << GPIO_LCKR_LCK14_Pos) ///< Portx Set bit 14 +#define GPIO_LCKR_LCK15_Pos (15) +#define GPIO_LCKR_LCK15 (0x01U << GPIO_LCKR_LCK15_Pos) ///< Portx Set bit 15 + +//////////////////////////////////////////////////////////////////////////////// +/// @brief GPIO_DCR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define GPIO_DCR_PX0_Pos (0) +#define GPIO_DCR_PX0 (0x03U << GPIO_DCR_PX0_Pos) ///< PX0[1:0] bits (pinx configuration bits, pin 0) +#define GPIO_DCR_PX0_MODE0 (0x00U << GPIO_DCR_PX0_Pos) ///< Mode = 0 +#define GPIO_DCR_PX0_MODE1 (0x01U << GPIO_DCR_PX0_Pos) ///< Mode = 1 +#define GPIO_DCR_PX0_MODE2 (0x02U << GPIO_DCR_PX0_Pos) ///< Mode = 2 +#define GPIO_DCR_PX0_MODE3 (0x03U << GPIO_DCR_PX0_Pos) ///< Mode = 3 +#define GPIO_DCR_PX1_Pos (2) +#define GPIO_DCR_PX1 (0x03U << GPIO_DCR_PX1_Pos) ///< PX1[1:0] bits (pinx configuration bits, pin 1) +#define GPIO_DCR_PX1_MODE0 (0x00U << GPIO_DCR_PX1_Pos) ///< Mode = 0 +#define GPIO_DCR_PX1_MODE1 (0x01U << GPIO_DCR_PX1_Pos) ///< Mode = 1 +#define GPIO_DCR_PX1_MODE2 (0x02U << GPIO_DCR_PX1_Pos) ///< Mode = 2 +#define GPIO_DCR_PX1_MODE3 (0x03U << GPIO_DCR_PX1_Pos) ///< Mode = 3 +#define GPIO_DCR_PX2_Pos (4) +#define GPIO_DCR_PX2 (0x03U << GPIO_DCR_PX2_Pos) ///< PX2[1:0] bits (pinx configuration bits, pin 2) +#define GPIO_DCR_PX2_MODE0 (0x00U << GPIO_DCR_PX2_Pos) ///< Mode = 0 +#define GPIO_DCR_PX2_MODE1 (0x01U << GPIO_DCR_PX2_Pos) ///< Mode = 1 +#define GPIO_DCR_PX2_MODE2 (0x02U << GPIO_DCR_PX2_Pos) ///< Mode = 2 +#define GPIO_DCR_PX2_MODE3 (0x03U << GPIO_DCR_PX2_Pos) ///< Mode = 3 +#define GPIO_DCR_PX3_Pos (6) +#define GPIO_DCR_PX3 (0x03U << GPIO_DCR_PX3_Pos) ///< PX3[1:0] bits (pinx configuration bits, pin 3) +#define GPIO_DCR_PX3_MODE0 (0x00U << GPIO_DCR_PX3_Pos) ///< Mode = 0 +#define GPIO_DCR_PX3_MODE1 (0x01U << GPIO_DCR_PX3_Pos) ///< Mode = 1 +#define GPIO_DCR_PX3_MODE2 (0x02U << GPIO_DCR_PX3_Pos) ///< Mode = 2 +#define GPIO_DCR_PX3_MODE3 (0x03U << GPIO_DCR_PX3_Pos) ///< Mode = 3 + +#define GPIO_DCR_PX4_Pos (8) +#define GPIO_DCR_PX4 (0x03U << GPIO_DCR_PX4_Pos) ///< PX4[1:0] bits (pinx configuration bits, pin 4) +#define GPIO_DCR_PX4_MODE0 (0x00U << GPIO_DCR_PX4_Pos) ///< Mode = 0 +#define GPIO_DCR_PX4_MODE1 (0x01U << GPIO_DCR_PX4_Pos) ///< Mode = 1 +#define GPIO_DCR_PX4_MODE2 (0x02U << GPIO_DCR_PX4_Pos) ///< Mode = 2 +#define GPIO_DCR_PX4_MODE3 (0x03U << GPIO_DCR_PX4_Pos) ///< Mode = 3 + +#define GPIO_DCR_PX5_Pos (10) +#define GPIO_DCR_PX5 (0x03U << GPIO_DCR_PX5_Pos) ///< PX5[1:0] bits (pinx configuration bits, pin 5) +#define GPIO_DCR_PX5_MODE0 (0x00U << GPIO_DCR_PX5_Pos) ///< Mode = 0 +#define GPIO_DCR_PX5_MODE1 (0x01U << GPIO_DCR_PX5_Pos) ///< Mode = 1 +#define GPIO_DCR_PX5_MODE2 (0x02U << GPIO_DCR_PX5_Pos) ///< Mode = 2 +#define GPIO_DCR_PX5_MODE3 (0x03U << GPIO_DCR_PX5_Pos) ///< Mode = 3 + +#define GPIO_DCR_PX6_Pos (12) +#define GPIO_DCR_PX6 (0x03U << GPIO_DCR_PX6_Pos) ///< PX6[1:0] bits (pinx configuration bits, pin 6) +#define GPIO_DCR_PX6_MODE0 (0x00U << GPIO_DCR_PX6_Pos) ///< Mode = 0 +#define GPIO_DCR_PX6_MODE1 (0x01U << GPIO_DCR_PX6_Pos) ///< Mode = 1 +#define GPIO_DCR_PX6_MODE2 (0x02U << GPIO_DCR_PX6_Pos) ///< Mode = 2 +#define GPIO_DCR_PX6_MODE3 (0x03U << GPIO_DCR_PX6_Pos) ///< Mode = 3 + +#define GPIO_DCR_PX7_Pos (14) +#define GPIO_DCR_PX7 (0x03U << GPIO_DCR_PX7_Pos) ///< PX7[1:0] bits (pinx configuration bits, pin 7) +#define GPIO_DCR_PX7_MODE0 (0x00U << GPIO_DCR_PX7_Pos) ///< Mode = 0 +#define GPIO_DCR_PX7_MODE1 (0x01U << GPIO_DCR_PX7_Pos) ///< Mode = 1 +#define GPIO_DCR_PX7_MODE2 (0x02U << GPIO_DCR_PX7_Pos) ///< Mode = 2 +#define GPIO_DCR_PX7_MODE3 (0x03U << GPIO_DCR_PX7_Pos) ///< Mode = 3 + +#define GPIO_DCR_PX8_Pos (16) +#define GPIO_DCR_PX8 (0x03U << GPIO_DCR_PX8_Pos) ///< PX8[1:0] bits (pinx configuration bits, pin 8) +#define GPIO_DCR_PX8_MODE0 (0x00U << GPIO_DCR_PX8_Pos) ///< Mode = 0 +#define GPIO_DCR_PX8_MODE1 (0x01U << GPIO_DCR_PX8_Pos) ///< Mode = 1 +#define GPIO_DCR_PX8_MODE2 (0x02U << GPIO_DCR_PX8_Pos) ///< Mode = 2 +#define GPIO_DCR_PX8_MODE3 (0x03U << GPIO_DCR_PX8_Pos) ///< Mode = 3 + +#define GPIO_DCR_PX9_Pos (18) +#define GPIO_DCR_PX9 (0x03U << GPIO_DCR_PX9_Pos) ///< PX9[1:0] bits (pinx configuration bits, pin 9) +#define GPIO_DCR_PX9_MODE0 (0x00U << GPIO_DCR_PX9_Pos) ///< Mode = 0 +#define GPIO_DCR_PX9_MODE1 (0x01U << GPIO_DCR_PX9_Pos) ///< Mode = 1 +#define GPIO_DCR_PX9_MODE2 (0x02U << GPIO_DCR_PX9_Pos) ///< Mode = 2 +#define GPIO_DCR_PX9_MODE3 (0x03U << GPIO_DCR_PX9_Pos) ///< Mode = 3 + +#define GPIO_DCR_PX10_Pos (20) +#define GPIO_DCR_PX10 (0x03U << GPIO_DCR_PX10_Pos) ///< PX10[1:0] bits (pinx configuration bits, pin 10) +#define GPIO_DCR_PX10_MODE0 (0x00U << GPIO_DCR_PX10_Pos) ///< Mode = 0 +#define GPIO_DCR_PX10_MODE1 (0x01U << GPIO_DCR_PX10_Pos) ///< Mode = 1 +#define GPIO_DCR_PX10_MODE2 (0x02U << GPIO_DCR_PX10_Pos) ///< Mode = 2 +#define GPIO_DCR_PX10_MODE3 (0x03U << GPIO_DCR_PX10_Pos) ///< Mode = 3 + +#define GPIO_DCR_PX11_Pos (22) +#define GPIO_DCR_PX11 (0x03U << GPIO_DCR_PX11_Pos) ///< PX11[1:0] bits (pinx configuration bits, pin 11) +#define GPIO_DCR_PX11_MODE0 (0x00U << GPIO_DCR_PX11_Pos) ///< Mode = 0 +#define GPIO_DCR_PX11_MODE1 (0x01U << GPIO_DCR_PX11_Pos) ///< Mode = 1 +#define GPIO_DCR_PX11_MODE2 (0x02U << GPIO_DCR_PX11_Pos) ///< Mode = 2 +#define GPIO_DCR_PX11_MODE3 (0x03U << GPIO_DCR_PX11_Pos) ///< Mode = 3 +#define GPIO_DCR_PX12_Pos (24) +#define GPIO_DCR_PX12 (0x03U << GPIO_DCR_PX12_Pos) ///< PX12[1:0] bits (pinx configuration bits, pin 12) +#define GPIO_DCR_PX12_MODE0 (0x00U << GPIO_DCR_PX12_Pos) ///< Mode = 0 +#define GPIO_DCR_PX12_MODE1 (0x01U << GPIO_DCR_PX12_Pos) ///< Mode = 1 +#define GPIO_DCR_PX12_MODE2 (0x02U << GPIO_DCR_PX12_Pos) ///< Mode = 2 +#define GPIO_DCR_PX12_MODE3 (0x03U << GPIO_DCR_PX12_Pos) ///< Mode = 3 +#define GPIO_DCR_PX13_Pos (26) +#define GPIO_DCR_PX13 (0x03U << GPIO_DCR_PX13_Pos) ///< PX13[1:0] bits (pinx configuration bits, pin 13) +#define GPIO_DCR_PX13_MODE0 (0x00U << GPIO_DCR_PX13_Pos) ///< Mode = 0 +#define GPIO_DCR_PX13_MODE1 (0x01U << GPIO_DCR_PX13_Pos) ///< Mode = 1 +#define GPIO_DCR_PX13_MODE2 (0x02U << GPIO_DCR_PX13_Pos) ///< Mode = 2 +#define GPIO_DCR_PX13_MODE3 (0x03U << GPIO_DCR_PX13_Pos) ///< Mode = 3 + +#define GPIO_DCR_PX14_Pos (28) +#define GPIO_DCR_PX14 (0x03U << GPIO_DCR_PX14_Pos) ///< PX14[1:0] bits (pinx configuration bits, pin 14) +#define GPIO_DCR_PX14_MODE0 (0x00U << GPIO_DCR_PX14_Pos) ///< Mode = 0 +#define GPIO_DCR_PX14_MODE1 (0x01U << GPIO_DCR_PX14_Pos) ///< Mode = 1 +#define GPIO_DCR_PX14_MODE2 (0x02U << GPIO_DCR_PX14_Pos) ///< Mode = 2 +#define GPIO_DCR_PX14_MODE3 (0x03U << GPIO_DCR_PX14_Pos) ///< Mode = 3 +#define GPIO_DCR_PX15_Pos (30) +#define GPIO_DCR_PX15 (0x03U << GPIO_DCR_PX15_Pos) ///< PX15[1:0] bits (pinx configuration bits, pin 15) +#define GPIO_DCR_PX15_MODE0 (0x00U << GPIO_DCR_PX15_Pos) ///< Mode = 0 +#define GPIO_DCR_PX15_MODE1 (0x01U << GPIO_DCR_PX15_Pos) ///< Mode = 1 +#define GPIO_DCR_PX15_MODE2 (0x02U << GPIO_DCR_PX15_Pos) ///< Mode = 2 +#define GPIO_DCR_PX15_MODE3 (0x03U << GPIO_DCR_PX15_Pos) ///< Mode = 3 +//////////////////////////////////////////////////////////////////////////////// +/// @brief GPIO_AFRL Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define GPIO_AFRL_AFR0_Pos (0) +#define GPIO_AFRL_AFR0 (0x0FU << GPIO_AFRL_AFR0_Pos) ///< Multiplexing function selection for bit 0 of portx +#define GPIO_AFRL_AFR1_Pos (4) +#define GPIO_AFRL_AFR1 (0x0FU << GPIO_AFRL_AFR1_Pos) ///< Multiplexing function selection for bit 1 of portx +#define GPIO_AFRL_AFR2_Pos (8) +#define GPIO_AFRL_AFR2 (0x0FU << GPIO_AFRL_AFR2_Pos) ///< Multiplexing function selection for bit 2 of portx +#define GPIO_AFRL_AFR3_Pos (12) +#define GPIO_AFRL_AFR3 (0x0FU << GPIO_AFRL_AFR3_Pos) ///< Multiplexing function selection for bit 3 of portx +#define GPIO_AFRL_AFR4_Pos (16) +#define GPIO_AFRL_AFR4 (0x0FU << GPIO_AFRL_AFR4_Pos) ///< Multiplexing function selection for bit 4 of portx +#define GPIO_AFRL_AFR5_Pos (20) +#define GPIO_AFRL_AFR5 (0x0FU << GPIO_AFRL_AFR5_Pos) ///< Multiplexing function selection for bit 5 of portx +#define GPIO_AFRL_AFR6_Pos (24) +#define GPIO_AFRL_AFR6 (0x0FU << GPIO_AFRL_AFR6_Pos) ///< Multiplexing function selection for bit 6 of portx +#define GPIO_AFRL_AFR7_Pos (28) +#define GPIO_AFRL_AFR7 (0x0FU << GPIO_AFRL_AFR7_Pos) ///< Multiplexing function selection for bit 7 of portx + +//////////////////////////////////////////////////////////////////////////////// +/// @brief GPIO_AFRH Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define GPIO_AFRH_AFR8_Pos (0) +#define GPIO_AFRH_AFR8 (0x0FU << GPIO_AFRH_AFR8_Pos) ///< Multiplexing function selection for bit 8 of portx +#define GPIO_AFRH_AFR9_Pos (4) +#define GPIO_AFRH_AFR9 (0x0FU << GPIO_AFRH_AFR9_Pos) ///< Multiplexing function selection for bit 9 of portx +#define GPIO_AFRH_AFR10_Pos (8) +#define GPIO_AFRH_AFR10 (0x0FU << GPIO_AFRH_AFR10_Pos) ///< Multiplexing function selection for bit 10 of portx +#define GPIO_AFRH_AFR11_Pos (12) +#define GPIO_AFRH_AFR11 (0x0FU << GPIO_AFRH_AFR11_Pos) ///< Multiplexing function selection for bit 11 of portx +#define GPIO_AFRH_AFR12_Pos (16) +#define GPIO_AFRH_AFR12 (0x0FU << GPIO_AFRH_AFR12_Pos) ///< Multiplexing function selection for bit 12 of portx +#define GPIO_AFRH_AFR13_Pos (20) +#define GPIO_AFRH_AFR13 (0x0FU << GPIO_AFRH_AFR13_Pos) ///< Multiplexing function selection for bit 13 of portx +#define GPIO_AFRH_AFR14_Pos (24) +#define GPIO_AFRH_AFR14 (0x0FU << GPIO_AFRH_AFR14_Pos) ///< Multiplexing function selection for bit 14 of portx +#define GPIO_AFRH_AFR15_Pos (28) +#define GPIO_AFRH_AFR15 (0x0FU << GPIO_AFRH_AFR15_Pos) ///< Multiplexing function selection for bit 15 of portx +#define GPIO_AF_MODEMASK (0x0FU) ///< Mode = 0 +#define GPIO_AF_MODE0 (0x00U) ///< Mode = 0 +#define GPIO_AF_MODE1 (0x01U) ///< Mode = 1 +#define GPIO_AF_MODE2 (0x02U) ///< Mode = 2 +#define GPIO_AF_MODE3 (0x03U) ///< Mode = 3 +#define GPIO_AF_MODE4 (0x04U) ///< Mode = 4 +#define GPIO_AF_MODE5 (0x05U) ///< Mode = 5 +#define GPIO_AF_MODE6 (0x06U) ///< Mode = 6 +#define GPIO_AF_MODE7 (0x07U) ///< Mode = 7 +#define GPIO_AF_MODE8 (0x08U) ///< Mode = 8 +#define GPIO_AF_MODE9 (0x09U) ///< Mode = 9 +#define GPIO_AF_MODE10 (0x0AU) ///< Mode = 10 +#define GPIO_AF_MODE11 (0x0BU) ///< Mode = 11 +#define GPIO_AF_MODE12 (0x0CU) ///< Mode = 12 +#define GPIO_AF_MODE13 (0x0DU) ///< Mode = 13 +#define GPIO_AF_MODE14 (0x0EU) ///< Mode = 14 +#define GPIO_AF_MODE15 (0x0FU) ///< Mode = 15 + + + + +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +#endif +//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_i2c.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_i2c.h new file mode 100644 index 000000000..e12f107e3 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_i2c.h @@ -0,0 +1,635 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file reg_i2c.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF +/// MM32 FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion + +#ifndef __REG_I2C_H +#define __REG_I2C_H + +// Files includes + +#include +#include +#include "types.h" + + + + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + + + + + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief I2C Base Address Definition +//////////////////////////////////////////////////////////////////////////////// +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) ///< Base Address: 0x40005400 +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) ///< Base Address: 0x40005800 + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief I2C Register Structure Definition +//////////////////////////////////////////////////////////////////////////////// +#undef USENCOMBINEREGISTER +#undef USENNEWREGISTER +#undef USENOLDREGISTER +#define USENCOMBINEREGISTER +#ifdef USENCOMBINEREGISTER +typedef struct { + union { + __IO u32 CR; ///< Control Register offset: 0x00 + __IO u32 IC_CON; + }; + union { + __IO u32 TAR; ///< Target Address Register offset: 0x04 + __IO u32 IC_TAR; + }; + union { + __IO u32 SAR; ///< Slave Address Register offset: 0x08 + __IO u32 IC_SAR; + }; + __IO u32 IC_HS_MADDR_RESERVED; ///< Reserved Register offset: 0x0C + union { + __IO u32 DR; ///< Data Command Register offset: 0x10 + __IO u32 IC_DATA_CMD; + }; + union { + __IO u32 SSHR; ///< SCL High Period Count for Std. Speed Register offset: 0x14 + __IO u32 IC_SS_SCL_HCNT; + }; + union { + __IO u32 SSLR; ///< SCL Low Period Count for Std. Speed Register offset: 0x18 + __IO u32 IC_SS_SCL_LCNT; + }; + union { + __IO u32 FSHR; ///< SCL High Period Count for Fast Speed Register offset: 0x1C + __IO u32 IC_FS_SCL_HCNT; + }; + union { + __IO u32 FSLR; ///< SCL Low Period Count for Fast Speed Register offset: 0x20 + __IO u32 IC_FS_SCL_LCNT; + }; + __IO u32 IC_HS_SCL_HCNT_RESERVED; ///< Reserved Register offset: 0x24 + __IO u32 IC_HS_SCL_LCNT_RESERVED; ///< Reserved Register offset: 0x28 + union { + __IO u32 ISR; ///< Interrupt Status Register offset: 0x2C + __IO u32 IC_INTR_STAT; + }; + union { + __IO u32 IMR; ///< Interrupt Mask Register offset: 0x30 + __IO u32 IC_INTR_MASK; + }; + union { + __IO u32 RAWISR; ///< RAW Interrupt Status Register offset: 0x34 + __IO u32 IC_RAW_INTR_STAT; + }; + union { + __IO u32 RXTLR; ///< Receive FIFO Threshold Level Register offset: 0x38 + __IO u32 IC_RX_TL; + }; + union { + __IO u32 TXTLR; ///< Transmit FIFO Threshold Level Register offset: 0x3C + __IO u32 IC_TX_TL; + }; + union { + __IO u32 ICR; ///< Clear All Interrupt Register offset: 0x40 + __IO u32 IC_CLR_INTR; + }; + union { + __IO u32 RX_UNDER; ///< Clear RX_UNDER Interrupt Register offset: 0x44 + __IO u32 IC_CLR_RX_UNDER; + }; + union { + __IO u32 RX_OVER; ///< Clear RX_OVER Interrupt Register offset: 0x48 + __IO u32 IC_CLR_RX_OVER; + }; + union { + __IO u32 TX_OVER; ///< Clear TX_OVER Interrupt Register offset: 0x4C + __IO u32 IC_CLR_TX_OVER; + }; + union { + __IO u32 RD_REQ; ///< Clear RD_REQ Interrupt Register offset: 0x50 + __IO u32 IC_CLR_RD_REQ; + }; + union { + __IO u32 TX_ABRT; ///< Clear TX_ABRT Interrupt Register offset: 0x54 + __IO u32 IC_CLR_TX_ABRT; + }; + union { + __IO u32 RX_DONE; ///< Clear RX_DONE Interrupt Register offset: 0x58 + __IO u32 IC_CLR_RX_DONE; + }; + union { + __IO u32 ACTIV; ///< Clear ACTIVITY Interrupt Register offset: 0x5C + __IO u32 IC_CLR_ACTIVITY; + }; + union { + __IO u32 STOP; ///< Clear STOP_DET Interrupt Register offset: 0x60 + __IO u32 IC_CLR_STOP_DET; + }; + union { + __IO u32 START; ///< Clear START_DET Interrupt Register offset: 0x64 + __IO u32 IC_CLR_START_DET; + }; + union { + __IO u32 GC; ///< Clear GEN_CALL Interrupt Register offset: 0x68 + __IO u32 IC_CLR_GEN_CALL; + }; + union { + __IO u32 ENR; ///< Enable Register offset: 0x6C + __IO u32 IC_ENABLE; + }; + union { + __IO u32 SR; ///< Status Register offset: 0x70 + __IO u32 IC_STATUS; + }; + union { + __IO u32 TXFLR; ///< Transmit FIFO Level Register offset: 0x74 + __IO u32 IC_TXFLR; + }; + union { + __IO u32 RXFLR; ///< Receive FIFO Level Register offset: 0x78 + __IO u32 IC_RXFLR; + }; + union { + __IO u32 HOLD; ///< SDA Hold Time Register offset: 0x7C + __IO u32 IC_SDA_HOLD; + }; + __IO u32 RESERVED28; ///IC_TX_ABRT_SOURCE_RESERVED; + __IO u32 RESERVED29; ///IC_SLV_DATA_NACK_ONLY_RESERVED; + + union { + __IO u32 DMA; ///< DMA Control Register offset: 0x88 + __IO u32 IC_DMA_CR; + }; + __IO u32 RESERVED30; ///IC_DMA_TDLR_RESERVED; + __IO u32 RESERVED31; ///IC_DMA_RDLR_RESERVED; + union { + __IO u32 SETUP; ///< SDA Setup Time Register offset: 0x94 + __IO u32 IC_SDA_SETUP; + }; + union { + __IO u32 GCR; ///< ACK General Call Register offset: 0x98 + __IO u32 IC_ACK_GENERAL_CALL; + }; + __IO u32 RESERVED32a; ///_RESERVED; offset: 0x9C + __IO u32 RESERVED33; ///_RESERVED; offset: 0xA0 + __IO u32 RESERVED34; ///_RESERVED; offset: 0xA4 + __IO u32 RESERVED35; ///_RESERVED; offset: 0xA8 + __IO u32 RESERVED36; ///_RESERVED; offset: 0xAC     + __IO u32 SLVMASK; ///
© COPYRIGHT MINDMOTION
+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion + +#ifndef __REG_IWDG_H +#define __REG_IWDG_H + +// Files includes + +#include +#include +#include "types.h" + + + + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief IWDG Base Address Definition +//////////////////////////////////////////////////////////////////////////////// +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) ///< Base Address: 0x40003000 + +//////////////////////////////////////////////////////////////////////////////// +/// @brief IWDG Register Structure Definition +//////////////////////////////////////////////////////////////////////////////// +typedef struct { + __IO u32 KR; ///< Key Register offset: 0x00 + __IO u32 PR; ///< Prescaler Register offset: 0x04 + __IO u32 RLR; ///< Reload Register offset: 0x08 + __IO u32 SR; ///< Status Register offset: 0x0C + __IO u32 CR; ///< Control Register offset: 0x10 + __IO u32 IGEN; ///< Interrupt Generator Register offset: 0x14 + __IO u32 CNT; ///< Interrupt Generator count Register offset: 0x18 + __IO u32 PS; ///< Prescaler count Register offset: 0x1C +} IWDG_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief IWDG type pointer Definition +//////////////////////////////////////////////////////////////////////////////// +#define IWDG ((IWDG_TypeDef*) IWDG_BASE) + +//////////////////////////////////////////////////////////////////////////////// +/// @brief IWDG_KR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define IWDG_KEYR_KEY_Pos (0) +#define IWDG_KEYR_KEY (0xFFFFU << IWDG_KEYR_KEY_Pos) ///< Key Value + +//////////////////////////////////////////////////////////////////////////////// +/// @brief IWDG_PR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define IWDG_PR_PRE_Pos (0) +#define IWDG_PR_PRE (0x07U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 4 +#define IWDG_PR_PRE_DIV4 (0x00U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 4 +#define IWDG_PR_PRE_DIV8 (0x01U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 8 +#define IWDG_PR_PRE_DIV16 (0x02U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 16 +#define IWDG_PR_PRE_DIV32 (0x03U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 32 +#define IWDG_PR_PRE_DIV64 (0x04U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 64 +#define IWDG_PR_PRE_DIV128 (0x05U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 128 +#define IWDG_PR_PRE_DIV256 (0x06U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 256 + +//////////////////////////////////////////////////////////////////////////////// +/// @brief IWDG_RLR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define IWDG_RLR_RL_Pos (0) +#define IWDG_RLR_RL (0x0FFFU << IWDG_RLR_RL_Pos) ///< Watchdog counter reload value + +//////////////////////////////////////////////////////////////////////////////// +/// @brief IWDG_SR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define IWDG_SR_PVU_Pos (0) +#define IWDG_SR_PVU (0x01U << IWDG_SR_PVU_Pos) ///< Watchdog prescaler value update +#define IWDG_SR_RVU_Pos (1) +#define IWDG_SR_RVU (0x01U << IWDG_SR_RVU_Pos) ///< Watchdog counter reload value update + +#define IWDG_SR_IVU_Pos (2) +#define IWDG_SR_IVU (0x01U << IWDG_SR_IVU_Pos) + +#define IWDG_SR_UPDATE_Pos (3) +#define IWDG_SR_UPDATE (0x01U << IWDG_SR_UPDATE_Pos) + +//////////////////////////////////////////////////////////////////////////////// +/// @brief IWDG_CR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define IWDG_CR_IRQSEL_Pos (0) +#define IWDG_CR_IRQSEL (0x01U << IWDG_CR_IRQSEL_Pos) ///< IWDG overflow operation selection +#define IWDG_CR_IRQCLR_Pos (1) +#define IWDG_CR_IRQCLR (0x01U << IWDG_CR_IRQCLR_Pos) ///< IWDG interrupt clear + +//////////////////////////////////////////////////////////////////////////////// +/// @brief IWDG_IGRN Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define IWDG_IGEN_IGEN_Pos (0) +#define IWDG_IGEN_IGEN (0xFFFU << IWDG_CR_IRQSEL_Pos) ///< IWDG Interrupt Generate value + + +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +#endif +//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_pwm.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_pwm.h new file mode 100644 index 000000000..aa3605524 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_pwm.h @@ -0,0 +1,72 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file reg_pwm.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF +/// MM32 FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion + +#ifndef __REG_PWM_H +#define __REG_PWM_H + +// Files includes + +#include +#include +#include "types.h" + + + + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + + + + + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief PWM Base Address Definition +//////////////////////////////////////////////////////////////////////////////// + + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief PWM Register Structure Definition +//////////////////////////////////////////////////////////////////////////////// + + + + + + + + + +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +#endif +//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_pwr.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_pwr.h new file mode 100644 index 000000000..99f523225 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_pwr.h @@ -0,0 +1,219 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file reg_pwr.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF +/// MM32 FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion + +#ifndef __REG_PWR_H +#define __REG_PWR_H + +// Files includes + +#include +#include +#include "types.h" + + + + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + + + + + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief PWR Base Address Definition +//////////////////////////////////////////////////////////////////////////////// +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) ///< Base Address: 0x40007000 + + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief PWR Register Structure Definition +//////////////////////////////////////////////////////////////////////////////// +typedef struct { + union { + __IO u32 CR; ///< Control register, offset: 0x00 + __IO u32 CR1; + }; + union { + __IO u32 CSR; ///< Control Status register offset: 0x04 + __IO u32 CSR1; + }; + __IO u32 CR2; ///< Control register 2 offset: 0x08 + __IO u32 CR3; ///< Control register 3 offset: 0x0C + __IO u32 CR4; ///< Control register 4 offset: 0x10 + __IO u32 CR5; ///< Control register 5 offset: 0x14 + __IO u32 CR6; ///< Control register 6 offset: 0x18 + __IO u32 SR; ///< Status register offset: 0x1C + __IO u32 SCR; ///< clear status register offset: 0x20 + __IO u32 CFGR; ///< Configuration register offset: 0x24 +} PWR_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief PWR type pointer Definition +//////////////////////////////////////////////////////////////////////////////// +#define PWR ((PWR_TypeDef*) PWR_BASE) + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief PWR_CR register Bit definition +//////////////////////////////////////////////////////////////////////////////// +#define PWR_CR_LDPS_Pos (0) +#define PWR_CR_LDPS (0x01U << PWR_CR_LDPS_Pos) ///< Domain Write Protction + +#define PWR_CR_PDDS_Pos (1) +#define PWR_CR_PDDS (0x01U << PWR_CR_PDDS_Pos) ///< Power Down Deepsleep +#define PWR_CR_CSBF_Pos (3) +#define PWR_CR_CSBF (0x01U << PWR_CR_CSBF_Pos) ///< Clear Standby Flag +#define PWR_CR_LPR_Pos (13) +#define PWR_CR_LPR (0x01U << PWR_CR_LPR_Pos) ///< Low power run +#define PWR_CR_VOS_Pos (14) +#define PWR_CR_VOS0 (0x00U << PWR_CR_VOS_Pos) ///< Modulator Voltage Output Select 1.80V +#define PWR_CR_VOS1 (0x01U << PWR_CR_VOS_Pos) ///< Modulator Voltage Output Select 1.70V +#define PWR_CR_VOS2 (0x02U << PWR_CR_VOS_Pos) ///< Modulator Voltage Output Select 1.60V +#define PWR_CR_VOS3 (0x03U << PWR_CR_VOS_Pos) ///< Modulator Voltage Output Select 1.55V + +//////////////////////////////////////////////////////////////////////////////// +/// @brief PWR_CSR register Bit definition +//////////////////////////////////////////////////////////////////////////////// +#define PWR_CSR_SBF_Pos (1) +#define PWR_CSR_SBF (0x01U << PWR_CSR_SBF_Pos) ///< Standby Flag +#define PWR_CSR_VOSRDY_Pos (14) +#define PWR_CSR_VOSRDY (0x01U << PWR_CR_VOSRDY_Pos) ///< Voltage Modulator Output Selection Ready +//////////////////////////////////////////////////////////////////////////////// +/// @brief PWR_CR2 register Bit definition +//////////////////////////////////////////////////////////////////////////////// +#define PWR_CR2_EWUP1_Pos (0) +#define PWR_CR2_EWUP1 (0x01U << PWR_CR2_EWUP1_Pos) ///< Enable WKUP1 wake-up pin +#define PWR_CR2_EWUP2_Pos (1) +#define PWR_CR2_EWUP2 (0x01U << PWR_CR2_EWUP2_Pos) ///< Enable WKUP2 wake-up pin +#define PWR_CR2_EWUP3_Pos (2) +#define PWR_CR2_EWUP3 (0x01U << PWR_CR2_EWUP3_Pos) ///< Enable WKUP3 wake-up pin +#define PWR_CR2_EWUP4_Pos (3) +#define PWR_CR2_EWUP4 (0x01U << PWR_CR2_EWUP4_Pos) ///< Enable WKUP4 wake-up pin +#define PWR_CR2_EWUP5_Pos (4) +#define PWR_CR2_EWUP5 (0x01U << PWR_CR2_EWUP5_Pos) ///< Enable WKUP5 wake-up pin +#define PWR_CR2_EWUP6_Pos (5) +#define PWR_CR2_EWUP6 (0x01U << PWR_CR2_EWUP6_Pos) ///< Enable WKUP6 wake-up pin +#define PWR_CR2_ENWU_Pos (15) +#define PWR_CR2_ENWU (0x01U << PWR_CR2_ENWU_Pos) ///< Enable wakeup module +//////////////////////////////////////////////////////////////////////////////// +/// @brief PWR_CR3 register Bit definition +//////////////////////////////////////////////////////////////////////////////// +#define PWR_CR3_WP1_Pos (0) +#define PWR_CR3_WP1 (0x01U << PWR_CR3_WP1_Pos) ///< WKUP1 used for event polarity detection +#define PWR_CR3_WP2_Pos (1) +#define PWR_CR3_WP2 (0x01U << PWR_CR3_WP2_Pos) ///< WKUP2 used for event polarity detection +#define PWR_CR3_WP3_Pos (2) +#define PWR_CR3_WP3 (0x01U << PWR_CR3_WP3_Pos) ///< WKUP3 used for event polarity detection +#define PWR_CR3_WP4_Pos (3) +#define PWR_CR3_WP4 (0x01U << PWR_CR3_WP4_Pos) ///< WKUP4 used for event polarity detection +#define PWR_CR3_WP5_Pos (4) +#define PWR_CR3_WP5 (0x01U << PWR_CR3_WP5_Pos) ///< WKUP5 used for event polarity detection +#define PWR_CR3_WP6_Pos (5) +#define PWR_CR3_WP6 (0x01U << PWR_CR3_WP6_Pos) ///< WKUP6 used for event polarity detection +//////////////////////////////////////////////////////////////////////////////// +/// @brief PWR_CR4 register Bit definition +//////////////////////////////////////////////////////////////////////////////// +#define PWR_CR4_FILTSEL0_Pos (0) +#define PWR_CR4_FILTSEL0 (0x01U << PWR_CR4_FILTSEL0_Pos) ///< selection wake-up source +#define PWR_CR4_FILTE0_Pos (2) +#define PWR_CR4_FILTE0 (0x01U << PWR_CR4_FILTE0_Pos) ///< enable Filter 0 +#define PWR_CR4_FILTF0_Pos (4) +#define PWR_CR4_FILTF0 (0x01U << PWR_CR4_FILTF0_Pos) ///< Whether the wake source passes through filter 0 +#define PWR_CR4_FILTCNT0_Pos (8) +#define PWR_CR4_FILTCNT0 (0xFFU << PWR_CR4_FILTCNT0_Pos) ///< Filter 0 counter +//////////////////////////////////////////////////////////////////////////////// +/// @brief PWR_CR5 register Bit definition +//////////////////////////////////////////////////////////////////////////////// +#define PWR_CR5_FILTSEL1_Pos (0) +#define PWR_CR5_FILTSEL1 (0x01U << PWR_CR5_FILTSEL1_Pos) ///< selection wake-up source +#define PWR_CR5_FILTE1_Pos (2) +#define PWR_CR5_FILTE1 (0x01U << PWR_CR5_FILTE1_Pos) ///< enable Filter 1 +#define PWR_CR5_FILTF1_Pos (4) +#define PWR_CR5_FILTF1 (0x01U << PWR_CR5_FILTF1_Pos) ///< Whether the wake source passes through filter 1 +#define PWR_CR5_FILTCNT1_Pos (8) +#define PWR_CR5_FILTCNT1 (0xFFU << PWR_CR5_FILTCNT1_Pos) ///< Filter 1 counter +//////////////////////////////////////////////////////////////////////////////// +/// @brief PWR_CR6 register Bit definition +//////////////////////////////////////////////////////////////////////////////// +#define PWR_CR6_STDBY_FS_W_Pos (0) +#define PWR_CR6_STDBY_FS_W1 (0x00U << PWR_CR6_STDBY_FS_W_Pos) ///< 1 LSI cycle wake +#define PWR_CR6_STDBY_FS_W2 (0x01U << PWR_CR6_STDBY_FS_W_Pos) ///< 2 LSI cycle wake +#define PWR_CR6_STDBY_FS_W3 (0x02U << PWR_CR6_STDBY_FS_W_Pos) ///< 3 LSI cycle wake +#define PWR_CR6_STDBY_FS_W4 (0x03U << PWR_CR6_STDBY_FS_W_Pos) ///< 4 LSI cycle wake +#define PWR_CR6_STDBY_FS_W5 (0x04U << PWR_CR6_STDBY_FS_W_Pos) ///< 5 LSI cycle wake +#define PWR_CR6_STDBY_FS_W6 (0x05U << PWR_CR6_STDBY_FS_W_Pos) ///< 6 LSI cycle wake +#define PWR_CR6_STDBY_FS_W7 (0x06U << PWR_CR6_STDBY_FS_W_Pos) ///< 7 LSI cycle wake +#define PWR_CR6_STDBY_FS_W8 (0x07U << PWR_CR6_STDBY_FS_W_Pos) ///< 8 LSI cycle wake +//////////////////////////////////////////////////////////////////////////////// +/// @brief PWR_SR register Bit definition +//////////////////////////////////////////////////////////////////////////////// +#define PWR_SR_WUF1_Pos (0) +#define PWR_SR_WUF1 (0x01U << PWR_SR_WUF1_Pos) ///< wake-up flag 1 +#define PWR_SR_WUF2_Pos (1) +#define PWR_SR_WUF2 (0x01U << PWR_SR_WUF2_Pos) ///< wake-up flag 2 +#define PWR_SR_WUF3_Pos (2) +#define PWR_SR_WUF3 (0x01U << PWR_SR_WUF3_Pos) ///< wake-up flag 3 +#define PWR_SR_WUF4_Pos (3) +#define PWR_SR_WUF4 (0x01U << PWR_SR_WUF4_Pos) ///< wake-up flag 4 +#define PWR_SR_WUF5_Pos (4) +#define PWR_SR_WUF5 (0x01U << PWR_SR_WUF5_Pos) ///< wake-up flag 5 +#define PWR_SR_WUF6_Pos (5) +#define PWR_SR_WUF6 (0x01U << PWR_SR_WUF6_Pos) ///< wake-up flag 6 +//////////////////////////////////////////////////////////////////////////////// +/// @brief PWR_SCR register Bit definition +//////////////////////////////////////////////////////////////////////////////// +#define PWR_SCR_CWUF1_Pos (0) +#define PWR_SCR_CWUF1 (0x01U << PWR_SCR_CWUF1_Pos) ///< clear wake-up flag 1 +#define PWR_SCR_CWUF2_Pos (1) +#define PWR_SCR_CWUF2 (0x01U << PWR_SCR_CWUF2_Pos) ///< clear wake-up flag 2 +#define PWR_SCR_CWUF3_Pos (2) +#define PWR_SCR_CWUF3 (0x01U << PWR_SCR_CWUF3_Pos) ///< clear wake-up flag 3 +#define PWR_SCR_CWUF4_Pos (3) +#define PWR_SCR_CWUF4 (0x01U << PWR_SCR_CWUF4_Pos) ///< clear wake-up flag 4 +#define PWR_SCR_CWUF5_Pos (4) +#define PWR_SCR_CWUF5 (0x01U << PWR_SCR_CWUF5_Pos) ///< clear wake-up flag 5 +#define PWR_SCR_CWUF6_Pos (5) +#define PWR_SCR_CWUF6 (0x01U << PWR_SCR_CWUF6_Pos) ///< clear wake-up flag 6 +//////////////////////////////////////////////////////////////////////////////// +/// @brief PWR_CFGR register Bit definition +//////////////////////////////////////////////////////////////////////////////// +#define PWR_CFGR_LSICALSEL_Pos (0) +#define PWR_CFGR_LSICALSEL (0x1FU << PWR_CFGR_LSICALSEL_Pos) ///< Enable internal clock calibration +#define PWR_CFGR_LSICAL_Pos (5) +#define PWR_CFGR_LSICAL (0x1FU << PWR_CFGR_LSICAL_Pos) ///< Internal high-speed clock calibration + +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +#endif +//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_rcc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_rcc.h new file mode 100644 index 000000000..d378371fc --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_rcc.h @@ -0,0 +1,654 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file reg_rcc.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF +/// MM32 FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion + +#ifndef __REG_RCC_H +#define __REG_RCC_H + +// Files includes + +#include +#include +#include "types.h" + + + + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + + + + + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief RCC Base Address Definition +//////////////////////////////////////////////////////////////////////////////// +#define RCC_BASE (AHBPERIPH_BASE + 0x1000) ///< Base Address: 0x40021000 + + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief RCC Register Structure Definition +//////////////////////////////////////////////////////////////////////////////// +typedef struct { + __IO u32 CR; ///< Control Register offset: 0x00 + __IO u32 CFGR; ///< Configuration Register offset: 0x04 + __IO u32 CIR; ///< Clock Interrupt Register offset: 0x08 + __IO u32 AHB3RSTR; ///< Advanced High Performance Bus 3 Reset Register offset: 0x0C + __IO u32 AHB2RSTR; ///< Advanced High Performance Bus 2 Reset Register offset: 0x10 + __IO u32 AHBRSTR; ///< Advanced High Performance Bus 1 Reset Register offset: 0x14 + __IO u32 APB2RSTR; ///< Advanced Peripheral Bus 2 Reset Register offset: 0x18 + __IO u32 APB1RSTR; ///< Advanced Peripheral Bus 1 Reset Register offset: 0x1C + __IO u32 AHB3ENR; ///< Advanced High Performance Bus 3 Enable Register offset: 0x20 + __IO u32 AHB2ENR; ///< Advanced High Performance Bus 2 Enable Register offset: 0x24 + union { + __IO u32 AHBENR; ///< Advanced High Performance Bus 1 Enable Register offset: 0x28 + __IO u32 AHB1ENR; + }; + + __IO u32 APB2ENR; ///< Advanced Peripheral Bus 2 Enable Register offset: 0x2C + __IO u32 APB1ENR; ///< Advanced Peripheral Bus 1 Enable Register offset: 0x30 + + + __IO u32 BDCR; ///< Backup Domain Control Register offset: 0x34 + __IO u32 CSR; ///< Control Status Register offset: 0x38 + __IO u32 SYSCFGR; ///< System Configuration Register offset: 0x3C + __IO u32 CFGR2; ///< System Configuration Register offset: 0x40 + __IO u32 ICSCR; ///< Internal clock source calibration register offset: 0x44 + __IO u32 PLLCFGR; ///< PLL configures registers offset: 0x48 + u32 Reserved1[13]; ///< Reserved space + __IO u32 HSIDLY; ///< HSI delay register offset: 0x80 + __IO u32 HSEDLY; ///< HSE delay register offset: 0x84 + __IO u32 PLLDLY; ///< PLL delay register offset: 0x88 +} RCC_TypeDef; + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief RCC type pointer Definition +//////////////////////////////////////////////////////////////////////////////// +#define RCC ((RCC_TypeDef*) RCC_BASE) + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief RCC_CR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define RCC_CR_HSION_Pos (0) +#define RCC_CR_HSION (0x01U << RCC_CR_HSION_Pos) ///< Internal High Speed clock enable + +#define RCC_CR_HSIRDY_Pos (1) +#define RCC_CR_HSIRDY (0x01U << RCC_CR_HSIRDY_Pos) ///< Internal High Speed clock ready flag + + + +#define RCC_CR_HSIDIV_Pos (11) +#define RCC_CR_HSIDIV_0 (0x00U << RCC_CR_HSIDIV_Pos) ///< HSI regardless of frequency +#define RCC_CR_HSIDIV_2 (0x01U << RCC_CR_HSIDIV_Pos) ///< HSI 2 frequency division +#define RCC_CR_HSIDIV_4 (0x02U << RCC_CR_HSIDIV_Pos) ///< HSI 4 frequency division +#define RCC_CR_HSIDIV_8 (0x03U << RCC_CR_HSIDIV_Pos) ///< HSI eight points and frequency +#define RCC_CR_HSIDIV_16 (0x04U << RCC_CR_HSIDIV_Pos) ///< HSI 16 points and frequency +#define RCC_CR_HSIDIV_32 (0x05U << RCC_CR_HSIDIV_Pos) ///< HSI 32 points and frequency +#define RCC_CR_HSIDIV_64 (0x06U << RCC_CR_HSIDIV_Pos) ///< HSI 64 frequency division +#define RCC_CR_HSIDIV_128 (0x07U << RCC_CR_HSIDIV_Pos) ///< HSI 128 frequency division +#define RCC_CR_HSEON_Pos (16) +#define RCC_CR_HSEON (0x01U << RCC_CR_HSEON_Pos) ///< External High Speed clock enable +#define RCC_CR_HSERDY_Pos (17) +#define RCC_CR_HSERDY (0x01U << RCC_CR_HSERDY_Pos) ///< External High Speed clock ready flag +#define RCC_CR_HSEBYP_Pos (18) +#define RCC_CR_HSEBYP (0x01U << RCC_CR_HSEBYP_Pos) ///< External High Speed clock Bypass +#define RCC_CR_CSSON_Pos (19) +#define RCC_CR_CSSON (0x01U << RCC_CR_CSSON_Pos) ///< Clock Security System enable + + +#define RCC_CR_PLLON_Pos (24) +#define RCC_CR_PLLON (0x01U << RCC_CR_PLLON_Pos) ///< PLL enable +#define RCC_CR_PLLRDY_Pos (25) +#define RCC_CR_PLLRDY (0x01U << RCC_CR_PLLRDY_Pos) ///< PLL clock ready flag +//////////////////////////////////////////////////////////////////////////////// +/// @brief RCC_CFGR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define RCC_CFGR_SW_Pos (0) +#define RCC_CFGR_SW (0x03U << RCC_CFGR_SW_Pos) ///< SW[1:0] bits (System clock Switch) +#define RCC_CFGR_SW_HSI_DIV6 (0x00U << RCC_CFGR_SW_Pos) ///< HSI/6 selected as system clock +#define RCC_CFGR_SW_HSE (0x01U << RCC_CFGR_SW_Pos) ///< HSE selected as system clock +#define RCC_CFGR_SW_PLL (0x02U << RCC_CFGR_SW_Pos) ///< PLL selected as system clock +#define RCC_CFGR_SW_LSI (0x03U << RCC_CFGR_SW_Pos) ///< LSI selected as system clock + +#define RCC_CFGR_SWS_Pos (2) +#define RCC_CFGR_SWS (0x03U << RCC_CFGR_SWS_Pos) ///< SWS[1:0] bits (System Clock Switch Status) +#define RCC_CFGR_SWS_HSI_DIV6 (0x00U << RCC_CFGR_SWS_Pos) ///< HSI/6 oscillator used as system clock +#define RCC_CFGR_SWS_HSE (0x01U << RCC_CFGR_SWS_Pos) ///< HSE oscillator used as system clock +#define RCC_CFGR_SWS_PLL (0x02U << RCC_CFGR_SWS_Pos) ///< PLL used as system clock +#define RCC_CFGR_SWS_LSI (0x03U << RCC_CFGR_SWS_Pos) ///< LSI used as system clock + +#define RCC_CFGR_HPRE_Pos (4) +#define RCC_CFGR_HPRE (0x0FU << RCC_CFGR_HPRE_Pos) ///< HPRE[3:0] bits (AHB prescaler) +#define RCC_CFGR_PPRE_0 (0x01U << RCC_CFGR_HPRE_Pos) ///< Bit 0 +#define RCC_CFGR_PPRE_1 (0x02U << RCC_CFGR_HPRE_Pos) ///< Bit 1 +#define RCC_CFGR_PPRE_2 (0x04U << RCC_CFGR_HPRE_Pos) ///< Bit 2 +#define RCC_CFGR_PPRE_3 (0x08U << RCC_CFGR_HPRE_Pos) ///< Bit 3 + +#define RCC_CFGR_HPRE_DIV1 (0x00U << RCC_CFGR_HPRE_Pos) ///< AHB = FCLK = SYSCLK not divided +#define RCC_CFGR_HPRE_DIV2 (0x08U << RCC_CFGR_HPRE_Pos) ///< AHB = FCLK = SYSCLK divided by 2 +#define RCC_CFGR_HPRE_DIV4 (0x09U << RCC_CFGR_HPRE_Pos) ///< AHB = FCLK = SYSCLK divided by 4 +#define RCC_CFGR_HPRE_DIV8 (0x0AU << RCC_CFGR_HPRE_Pos) ///< AHB = FCLK = SYSCLK divided by 8 +#define RCC_CFGR_HPRE_DIV16 (0x0BU << RCC_CFGR_HPRE_Pos) ///< AHB = FCLK = SYSCLK divided by 16 +#define RCC_CFGR_HPRE_DIV64 (0x0CU << RCC_CFGR_HPRE_Pos) ///< AHB = FCLK = SYSCLK divided by 64 +#define RCC_CFGR_HPRE_DIV128 (0x0DU << RCC_CFGR_HPRE_Pos) ///< AHB = FCLK = SYSCLK divided by 128 +#define RCC_CFGR_HPRE_DIV256 (0x0EU << RCC_CFGR_HPRE_Pos) ///< AHB = FCLK = SYSCLK divided by 256 +#define RCC_CFGR_HPRE_DIV512 (0x0FU << RCC_CFGR_HPRE_Pos) ///< AHB = FCLK = SYSCLK divided by 512 + +#define RCC_CFGR_PPRE1_Pos (8) +#define RCC_CFGR_PPRE1 (0x07U << RCC_CFGR_PPRE1_Pos) ///< PRE1[2:0] bits (APB1 prescaler) +#define RCC_CFGR_PPRE1_0 (0x01U << RCC_CFGR_PPRE1_Pos) ///< Bit 0 +#define RCC_CFGR_PPRE1_1 (0x02U << RCC_CFGR_PPRE1_Pos) ///< Bit 1 +#define RCC_CFGR_PPRE1_2 (0x04U << RCC_CFGR_PPRE1_Pos) ///< Bit 2 + +#define RCC_CFGR_PPRE1_DIV1 (0x00U << RCC_CFGR_PPRE1_Pos) ///< APB1 = HCLK not divided +#define RCC_CFGR_PPRE1_DIV2 (0x04U << RCC_CFGR_PPRE1_Pos) ///< APB1 = HCLK divided by 2 +#define RCC_CFGR_PPRE1_DIV4 (0x05U << RCC_CFGR_PPRE1_Pos) ///< APB1 = HCLK divided by 4 +#define RCC_CFGR_PPRE1_DIV8 (0x06U << RCC_CFGR_PPRE1_Pos) ///< APB1 = HCLK divided by 8 +#define RCC_CFGR_PPRE1_DIV16 (0x07U << RCC_CFGR_PPRE1_Pos) ///< APB1 = HCLK divided by 16 + +#define RCC_CFGR_PPRE2_Pos (11) +#define RCC_CFGR_PPRE2 (0x07U << RCC_CFGR_PPRE2_Pos) ///< PRE2[2:0] bits (APB2 prescaler) +#define RCC_CFGR_PPRE2_0 (0x01U << RCC_CFGR_PPRE2_Pos) ///< Bit 0 +#define RCC_CFGR_PPRE2_1 (0x02U << RCC_CFGR_PPRE2_Pos) ///< Bit 1 +#define RCC_CFGR_PPRE2_2 (0x04U << RCC_CFGR_PPRE2_Pos) ///< Bit 2 + +#define RCC_CFGR_PPRE2_DIV1 (0x00U << RCC_CFGR_PPRE2_Pos) ///< APB2 = HCLK not divided +#define RCC_CFGR_PPRE2_DIV2 (0x04U << RCC_CFGR_PPRE2_Pos) ///< APB2 = HCLK divided by 2 +#define RCC_CFGR_PPRE2_DIV4 (0x05U << RCC_CFGR_PPRE2_Pos) ///< APB2 = HCLK divided by 4 +#define RCC_CFGR_PPRE2_DIV8 (0x06U << RCC_CFGR_PPRE2_Pos) ///< APB2 = HCLK divided by 8 +#define RCC_CFGR_PPRE2_DIV16 (0x07U << RCC_CFGR_PPRE2_Pos) ///< APB2 = HCLK divided by 16 + + +#define RCC_CFGR_USBPRE_Pos (22) +#define RCC_CFGR_USBPRE (0x03U << RCC_CFGR_USBPRE_Pos) ///< USB prescaler BIT[1:0] + +#define RCC_CFGR_MCO_Pos (24) +#define RCC_CFGR_MCO (0x07U << RCC_CFGR_MCO_Pos) ///< MCO[2:0] bits (Microcontroller Clock Output) +#define RCC_CFGR_MCO_NOCLOCK (0x00U << RCC_CFGR_MCO_Pos) ///< No clock +#define RCC_CFGR_MCO_LSI (0x02U << RCC_CFGR_MCO_Pos) ///< LSI clock +#define RCC_CFGR_MCO_LSE (0x03U << RCC_CFGR_MCO_Pos) ///< LSE clock +#define RCC_CFGR_MCO_SYSCLK (0x04U << RCC_CFGR_MCO_Pos) ///< System clock selected +#define RCC_CFGR_MCO_HSI (0x05U << RCC_CFGR_MCO_Pos) ///< Internal 48 MHz RC oscillator clock selected +#define RCC_CFGR_MCO_HSE (0x06U << RCC_CFGR_MCO_Pos) ///< External 1-25 MHz oscillator clock selected +#define RCC_CFGR_MCO_PLL (0x07U << RCC_CFGR_MCO_Pos) ///< PLL clock divided by 2 selected + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief RCC_CIR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define RCC_CIR_LSIRDYF_Pos (0) +#define RCC_CIR_LSIRDYF (0x01U << RCC_CIR_LSIRDYF_Pos) ///< LSI Ready Interrupt flag + +#define RCC_CIR_LSERDYF_Pos (1) +#define RCC_CIR_LSERDYF (0x01U << RCC_CIR_LSERDYF_Pos) ///< LSE Ready Interrupt flag + +#define RCC_CIR_HSIRDYF_Pos (2) +#define RCC_CIR_HSIRDYF (0x01U << RCC_CIR_HSIRDYF_Pos) ///< HSI Ready Interrupt flag +#define RCC_CIR_HSERDYF_Pos (3) +#define RCC_CIR_HSERDYF (0x01U << RCC_CIR_HSERDYF_Pos) ///< HSE Ready Interrupt flag + +#define RCC_CIR_PLLRDYF_Pos (4) +#define RCC_CIR_PLLRDYF (0x01U << RCC_CIR_PLLRDYF_Pos) ///< PLL Ready Interrupt flag + +#define RCC_CIR_CSSF_Pos (7) +#define RCC_CIR_CSSF (0x01U << RCC_CIR_CSSF_Pos) ///< Clock Security System Interrupt flag +#define RCC_CIR_LSIRDYIE_Pos (8) +#define RCC_CIR_LSIRDYIE (0x01U << RCC_CIR_LSIRDYIE_Pos) ///< LSI Ready Interrupt Enable + +#define RCC_CIR_LSERDYIE_Pos (9) +#define RCC_CIR_LSERDYIE (0x01U << RCC_CIR_LSERDYIE_Pos) ///< LSE Ready Interrupt Enable + +#define RCC_CIR_HSIRDYIE_Pos (10) +#define RCC_CIR_HSIRDYIE (0x01U << RCC_CIR_HSIRDYIE_Pos) ///< HSI Ready Interrupt Enable +#define RCC_CIR_HSERDYIE_Pos (11) +#define RCC_CIR_HSERDYIE (0x01U << RCC_CIR_HSIRDYIE_Pos) ///< HSE Ready Interrupt Enable + +#define RCC_CIR_PLLRDYIE_Pos (12) +#define RCC_CIR_PLLRDYIE (0x01U << RCC_CIR_PLLRDYIE_Pos) ///< PLL Ready Interrupt Enable + +#define RCC_CIR_LSIRDYC_Pos (16) +#define RCC_CIR_LSIRDYC (0x01U << RCC_CIR_LSIRDYC_Pos) ///< LSI Ready Interrupt Clear + +#define RCC_CIR_LSERDYC_Pos (17) +#define RCC_CIR_LSERDYC (0x01U << RCC_CIR_LSERDYC_Pos) ///< LSE Ready Interrupt Clear + +#define RCC_CIR_HSIRDYC_Pos (18) +#define RCC_CIR_HSIRDYC (0x01U << RCC_CIR_HSIRDYC_Pos) ///< HSI Ready Interrupt Clear +#define RCC_CIR_HSERDYC_Pos (19) +#define RCC_CIR_HSERDYC (0x01U << RCC_CIR_HSERDYC_Pos) ///< HSE Ready Interrupt Clear + +#define RCC_CIR_PLLRDYC_Pos (20) +#define RCC_CIR_PLLRDYC (0x01U << RCC_CIR_PLLRDYC_Pos) ///< PLL Ready Interrupt Clear + +#define RCC_CIR_CSSC_Pos (23) +#define RCC_CIR_CSSC (0x01U << RCC_CIR_CSSC_Pos) ///< Clock Security System Interrupt Clear + +//////////////////////////////////////////////////////////////////////////////// +/// @brief RCC_APB2RSTR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define RCC_APB2RSTR_TIM1_Pos (0) +#define RCC_APB2RSTR_TIM1 (0x01U << RCC_APB2RSTR_TIM1_Pos) ///< TIM1 reset +#define RCC_APB2RSTR_TIM8_Pos (1) +#define RCC_APB2RSTR_TIM8 (0x01U << RCC_APB2RSTR_TIM8_Pos) ///< TIM8 reset +#define RCC_APB2RSTR_UART1_Pos (4) +#define RCC_APB2RSTR_UART1 (0x01U << RCC_APB2RSTR_UART1_Pos) ///< UART1 reset +#define RCC_APB2RSTR_UART6_Pos (5) +#define RCC_APB2RSTR_UART6 (0x01U << RCC_APB2RSTR_UART6_Pos) ///< UART6 reset +#define RCC_APB2RSTR_ADC1_Pos (8) +#define RCC_APB2RSTR_ADC1 (0x01U << RCC_APB2RSTR_ADC1_Pos) ///< ADC1 reset +#define RCC_APB2RSTR_ADC2_Pos (9) +#define RCC_APB2RSTR_ADC2 (0x01U << RCC_APB2RSTR_ADC2_Pos) ///< ADC2 reset +#define RCC_APB2RSTR_ADC3_Pos (10) +#define RCC_APB2RSTR_ADC3 (0x01U << RCC_APB2RSTR_ADC3_Pos) ///< ADC3 reset +#define RCC_APB2RSTR_SPI1_Pos (12) +#define RCC_APB2RSTR_SPI1 (0x01U << RCC_APB2RSTR_SPI1_Pos) ///< SPI1 reset +#define RCC_APB2RSTR_SYSCFG_Pos (14) +#define RCC_APB2RSTR_SYSCFG (0x01U << RCC_APB2RSTR_SYSCFG_Pos) ///< SYSCFG reset +#define RCC_APB2RSTR_COMP_Pos (15) +#define RCC_APB2RSTR_COMP (0x01U << RCC_APB2RSTR_COMP_Pos) ///< COMP reset + + + + + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief RCC_AHB3RSTR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define RCC_AHB3RSTR_FSMC_Pos (0) +#define RCC_AHB3RSTR_FSMC (0x01U << RCC_AHB3RSTR_FSMC_Pos) ///< FSMC reset + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief RCC_APB1RSTR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define RCC_APB1RSTR_TIM2_Pos (0) +#define RCC_APB1RSTR_TIM2 (0x01U << RCC_APB1RSTR_TIM2_Pos) ///< Timer 2 reset +#define RCC_APB1RSTR_TIM3_Pos (1) +#define RCC_APB1RSTR_TIM3 (0x01U << RCC_APB1RSTR_TIM3_Pos) ///< Timer 3 reset + +#define RCC_APB1RSTR_TIM4_Pos (2) +#define RCC_APB1RSTR_TIM4 (0x01U << RCC_APB1RSTR_TIM4_Pos) ///< Timer 4 reset +#define RCC_APB1RSTR_TIM5_Pos (3) +#define RCC_APB1RSTR_TIM5 (0x01U << RCC_APB1RSTR_TIM5_Pos) ///< Timer 5 reset +#define RCC_APB1RSTR_TIM6_Pos (4) +#define RCC_APB1RSTR_TIM6 (0x01U << RCC_APB1RSTR_TIM6_Pos) ///< Timer 6 reset +#define RCC_APB1RSTR_TIM7_Pos (5) +#define RCC_APB1RSTR_TIM7 (0x01U << RCC_APB1RSTR_TIM7_Pos) ///< Timer 7 reset + +#define RCC_APB1RSTR_WWDG_Pos (11) +#define RCC_APB1RSTR_WWDG (0x01U << RCC_APB1RSTR_WWDG_Pos) ///< Window Watchdog reset +#define RCC_APB1RSTR_SPI2_Pos (14) +#define RCC_APB1RSTR_SPI2 (0x01U << RCC_APB1RSTR_SPI2_Pos) ///< SPI 2 reset +#define RCC_APB1RSTR_SPI3_Pos (15) +#define RCC_APB1RSTR_SPI3 (0x01U << RCC_APB1RSTR_SPI3_Pos) ///< SPI 3 reset + +#define RCC_APB1RSTR_UART2_Pos (17) +#define RCC_APB1RSTR_UART2 (0x01U << RCC_APB1RSTR_UART2_Pos) ///< UART 2 reset +#define RCC_APB1RSTR_UART3_Pos (18) +#define RCC_APB1RSTR_UART3 (0x01U << RCC_APB1RSTR_UART3_Pos) ///< UART 3 reset +#define RCC_APB1RSTR_UART4_Pos (19) +#define RCC_APB1RSTR_UART4 (0x01U << RCC_APB1RSTR_UART4_Pos) ///< UART 4 reset +#define RCC_APB1RSTR_UART5_Pos (20) +#define RCC_APB1RSTR_UART5 (0x01U << RCC_APB1RSTR_UART5_Pos) ///< UART 5 reset +#define RCC_APB1RSTR_I2C1_Pos (21) +#define RCC_APB1RSTR_I2C1 (0x01U << RCC_APB1RSTR_I2C1_Pos) ///< I2C 1 reset +#define RCC_APB1RSTR_I2C2_Pos (22) +#define RCC_APB1RSTR_I2C2 (0x01U << RCC_APB1RSTR_I2C2_Pos) ///< I2C 2 reset + +#define RCC_APB1RSTR_CRS_Pos (24) +#define RCC_APB1RSTR_CRS (0x01U << RCC_APB1RSTR_CRS_Pos) ///< CRS reset +#define RCC_APB1RSTR_CAN_Pos (25) +#define RCC_APB1RSTR_CAN (0x01U << RCC_APB1RSTR_CAN_Pos) ///< CAN reset + +#define RCC_APB1RSTR_BKP_Pos (27) +#define RCC_APB1RSTR_BKP (0x01U << RCC_APB1RSTR_BKP_Pos) ///< Backup interface reset + +#define RCC_APB1RSTR_PWR_Pos (28) +#define RCC_APB1RSTR_PWR (0x01U << RCC_APB1RSTR_PWR_Pos) ///< Power interface reset +#define RCC_APB1RSTR_DAC_Pos (29) +#define RCC_APB1RSTR_DAC (0x01U << RCC_APB1RSTR_DAC_Pos) ///< DAC interface reset + + +#define RCC_APB1RSTR_UART7_Pos (30) +#define RCC_APB1RSTR_UART7 (0x01U << RCC_APB1RSTR_UART7_Pos) ///< UART7 reset +#define RCC_APB1RSTR_UART8_Pos (31) +#define RCC_APB1RSTR_UART8 (0x01U << RCC_APB1RSTR_UART8_Pos) ///< UART8 reset + +//////////////////////////////////////////////////////////////////////////////// +/// @brief RCC_AHB2RSTR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define RCC_AHB2RSTR_USBFS_Pos (7) +#define RCC_AHB2RSTR_USBFS (0x01U << RCC_AHB2RSTR_USBFS_Pos) ///< USBFS reset +//////////////////////////////////////////////////////////////////////////////// +/// @brief RCC_AHB3ENR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define RCC_AHB3ENR_FSMC_Pos (0) +#define RCC_AHB3ENR_FSMC (0x01U << RCC_AHB3ENR_FSMC_Pos) ///< FSMC reset + +//////////////////////////////////////////////////////////////////////////////// +/// @brief RCC_AHB2ENR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define RCC_AHB2ENR_USBFS_Pos (7) +#define RCC_AHB2ENR_USBFS (0x01U << RCC_AHB2ENR_USBFS_Pos) ///< USBFS reset + +//////////////////////////////////////////////////////////////////////////////// +/// @brief RCC_AHBENR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// + + + +#define RCC_AHBENR_GPIOA_Pos (0) +#define RCC_AHBENR_GPIOA (0x01U << RCC_AHBENR_GPIOA_Pos) ///< GPIOA clock enable +#define RCC_AHBENR_GPIOB_Pos (1) +#define RCC_AHBENR_GPIOB (0x01U << RCC_AHBENR_GPIOB_Pos) ///< GPIOB clock enable +#define RCC_AHBENR_GPIOC_Pos (2) +#define RCC_AHBENR_GPIOC (0x01U << RCC_AHBENR_GPIOC_Pos) ///< GPIOC clock enable +#define RCC_AHBENR_GPIOD_Pos (3) +#define RCC_AHBENR_GPIOD (0x01U << RCC_AHBENR_GPIOD_Pos) ///< GPIOD clock enable +#define RCC_AHBENR_GPIOE_Pos (4) +#define RCC_AHBENR_GPIOE (0x01U << RCC_AHBENR_GPIOE_Pos) ///< GPIOE clock enable +#define RCC_AHBENR_GPIOF_Pos (5) +#define RCC_AHBENR_GPIOF (0x01U << RCC_AHBENR_GPIOF_Pos) ///< GPIOF clock enable +#define RCC_AHBENR_GPIOG_Pos (6) +#define RCC_AHBENR_GPIOG (0x01U << RCC_AHBENR_GPIOG_Pos) ///< GPIOG clock enable +#define RCC_AHBENR_GPIOH_Pos (7) +#define RCC_AHBENR_GPIOH (0x01U << RCC_AHBENR_GPIOH_Pos) ///< GPIOH clock enable +#define RCC_AHBENR_SDIO_Pos (10) +#define RCC_AHBENR_SDIO (0x01U << RCC_AHBENR_SDIO_Pos) ///< SDIO clock enable +#define RCC_AHBENR_CRC_Pos (12) +#define RCC_AHBENR_CRC (0x01U << RCC_AHBENR_CRC_Pos) ///< CRC clock enable +#define RCC_AHBENR_FLASH_Pos (13) +#define RCC_AHBENR_FLASH (0x01U << RCC_AHBENR_FLASH_Pos) ///< FLASH clock enable +#define RCC_AHBENR_SRAM_Pos (14) +#define RCC_AHBENR_SRAM (0x01U << RCC_AHBENR_SRAM_Pos) ///< SRAM clock enable +#define RCC_AHBENR_DMA1_Pos (21) +#define RCC_AHBENR_DMA1 (0x01U << RCC_AHBENR_DMA1_Pos) ///< DMA1 clock enable +#define RCC_AHBENR_DMA2_Pos (22) +#define RCC_AHBENR_DMA2 (0x01U << RCC_AHBENR_DMA2_Pos) ///< DMA2 clock enable +#define RCC_AHBENR_ETHMAC_Pos (25) +#define RCC_AHBENR_ETHMAC (0x01U << RCC_AHBENR_ETHMAC_Pos) ///< ETHMAC clock enable +//////////////////////////////////////////////////////////////////////////////// +/// @brief RCC_APB2ENR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define RCC_APB2ENR_TIM1_Pos (0) +#define RCC_APB2ENR_TIM1 (0x01U << RCC_APB2ENR_TIM1_Pos) ///< TIM1 enable +#define RCC_APB2ENR_TIM8_Pos (1) +#define RCC_APB2ENR_TIM8 (0x01U << RCC_APB2ENR_TIM8_Pos) ///< TIM8 enable +#define RCC_APB2ENR_UART1_Pos (4) +#define RCC_APB2ENR_UART1 (0x01U << RCC_APB2ENR_UART1_Pos) ///< UART1 enable +#define RCC_APB2ENR_UART6_Pos (5) +#define RCC_APB2ENR_UART6 (0x01U << RCC_APB2ENR_UART6_Pos) ///< UART6 enable +#define RCC_APB2ENR_ADC1_Pos (8) +#define RCC_APB2ENR_ADC1 (0x01U << RCC_APB2ENR_ADC1_Pos) ///< ADC1 enable +#define RCC_APB2ENR_ADC2_Pos (9) +#define RCC_APB2ENR_ADC2 (0x01U << RCC_APB2ENR_ADC2_Pos) ///< ADC2 enable +#define RCC_APB2ENR_ADC3_Pos (10) +#define RCC_APB2ENR_ADC3 (0x01U << RCC_APB2ENR_ADC3_Pos) ///< ADC3 enable +#define RCC_APB2ENR_SPI1_Pos (12) +#define RCC_APB2ENR_SPI1 (0x01U << RCC_APB2ENR_SPI1_Pos) ///< SPI1 enable +#define RCC_APB2ENR_EXTI_Pos (14) +#define RCC_APB2ENR_EXTI (0x01U << RCC_APB2ENR_EXTI_Pos) ///< EXTI Block enable +#define RCC_APB2ENR_SYSCFG_Pos (14) +#define RCC_APB2ENR_SYSCFG (0x01U << RCC_APB2ENR_SYSCFG_Pos) ///< SYSCFG enable +#define RCC_APB2ENR_COMP_Pos (15) +#define RCC_APB2ENR_COMP (0x01U << RCC_APB2ENR_COMP_Pos) ///< COMP enable +//////////////////////////////////////////////////////////////////////////////// +/// @brief RCC_APB1ENR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define RCC_APB1ENR_TIM2_Pos (0) +#define RCC_APB1ENR_TIM2 (0x01U << RCC_APB1ENR_TIM2_Pos) ///< Timer 2 clock enable + +#define RCC_APB1ENR_TIM3_Pos (1) +#define RCC_APB1ENR_TIM3 (0x01U << RCC_APB1ENR_TIM3_Pos) ///< Timer 3 clock enabled + +#define RCC_APB1ENR_TIM4_Pos (2) +#define RCC_APB1ENR_TIM4 (0x01U << RCC_APB1ENR_TIM4_Pos) ///< Timer 4 clock enable + + +#define RCC_APB1ENR_TIM5_Pos (3) +#define RCC_APB1ENR_TIM5 (0x01U << RCC_APB1ENR_TIM5_Pos) ///< TIM5 Timer clock enable +#define RCC_APB1ENR_TIM6_Pos (4) +#define RCC_APB1ENR_TIM6 (0x01U << RCC_APB1ENR_TIM6_Pos) ///< TIM6 Timer clock enable +#define RCC_APB1ENR_TIM7_Pos (5) +#define RCC_APB1ENR_TIM7 (0x01U << RCC_APB1ENR_TIM7_Pos) ///< TIM7 Timer clock enable + +#define RCC_APB1ENR_WWDG_Pos (11) +#define RCC_APB1ENR_WWDG (0x01U << RCC_APB1ENR_WWDG_Pos) ///< Window Watchdog clock enable + + +#define RCC_APB1ENR_SPI2_Pos (14) +#define RCC_APB1ENR_SPI2 (0x01U << RCC_APB1ENR_SPI2_Pos) ///< SPI 2 clock enable +#define RCC_APB1ENR_SPI3_Pos (15) +#define RCC_APB1ENR_SPI3 (0x01U << RCC_APB1ENR_SPI3_Pos) ///< SPI 3 clock enable + +#define RCC_APB1ENR_UART2_Pos (17) +#define RCC_APB1ENR_UART2 (0x01U << RCC_APB1ENR_UART2_Pos) ///< UART 2 clock enable +#define RCC_APB1ENR_UART3_Pos (18) +#define RCC_APB1ENR_UART3 (0x01U << RCC_APB1ENR_UART3_Pos) ///< UART 3 clock enable +#define RCC_APB1ENR_UART4_Pos (19) +#define RCC_APB1ENR_UART4 (0x01U << RCC_APB1ENR_UART4_Pos) ///< UART 4 clock enable +#define RCC_APB1ENR_UART5_Pos (20) +#define RCC_APB1ENR_UART5 (0x01U << RCC_APB1ENR_UART5_Pos) ///< UART 5 clock enable +#define RCC_APB1ENR_I2C1_Pos (21) +#define RCC_APB1ENR_I2C1 (0x01U << RCC_APB1ENR_I2C1_Pos) ///< I2C 1 clock enable +#define RCC_APB1ENR_I2C2_Pos (22) +#define RCC_APB1ENR_I2C2 (0x01U << RCC_APB1ENR_I2C2_Pos) ///< I2C 2 clock enable +#define RCC_APB1ENR_CRS_Pos (24) +#define RCC_APB1ENR_CRS (0x01U << RCC_APB1ENR_CRS_Pos) ///< CRS 4 clock enable +#define RCC_APB1ENR_CAN_Pos (25) +#define RCC_APB1ENR_CAN (0x01U << RCC_APB1ENR_CAN_Pos) ///< CAN 5 clock enable + + + +#define RCC_APB1ENR_BKP_Pos (27) +#define RCC_APB1ENR_BKP (0x01U << RCC_APB1ENR_BKP_Pos) ///< Backup interface clock enable + +#define RCC_APB1ENR_PWR_Pos (28) +#define RCC_APB1ENR_PWR (0x01U << RCC_APB1ENR_PWR_Pos) ///< Power interface clock enable + +#define RCC_APB1ENR_DBGMCU_Pos (28) +#define RCC_APB1ENR_DBGMCU (0x01U << RCC_APB1ENR_DBGMCU_Pos) ///< DBGMCU clock enable + + +#define RCC_APB1ENR_DAC_Pos (29) +#define RCC_APB1ENR_DAC (0x01U << RCC_APB1ENR_DAC_Pos) ///< DAC interface clock enable +#define RCC_APB1ENR_UART7_Pos (30) +#define RCC_APB1ENR_UART7 (0x01U << RCC_APB1ENR_UART7_Pos) ///< UART7 interface clock enable +#define RCC_APB1ENR_UART8_Pos (31) +#define RCC_APB1ENR_UART8 (0x01U << RCC_APB1ENR_UART8_Pos) ///< UART8 interface clock enable +//////////////////////////////////////////////////////////////////////////////// +/// @brief RCC_BDCR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define RCC_BDCR_LSEON_Pos (0) +#define RCC_BDCR_LSEON (0x01U << RCC_BDCR_LSEON_Pos) ///< External Low Speed oscillator enable +#define RCC_BDCR_LSERDY_Pos (1) +#define RCC_BDCR_LSERDY (0x01U << RCC_BDCR_LSERDY_Pos) ///< External Low Speed oscillator Ready +#define RCC_BDCR_LSEBYP_Pos (2) +#define RCC_BDCR_LSEBYP (0x01U << RCC_BDCR_LSEBYP_Pos) ///< External Low Speed oscillator Bypass + +#define RCC_BDCR_RTCSEL_Pos (8) +#define RCC_BDCR_RTCSEL (0x03U << RCC_BDCR_RTCSEL_Pos) ///< RTCSEL[1:0] bits (RTC clock source selection) +#define RCC_BDCR_RTCSEL_LSE (0x01U << RCC_BDCR_RTCSEL_Pos) ///< LSE oscillator clock used as RTC clock +#define RCC_BDCR_RTCSEL_LSI (0x02U << RCC_BDCR_RTCSEL_Pos) ///< LSI oscillator clock used as RTC clock +#define RCC_BDCR_RTCSEL_HSE (0x03U << RCC_BDCR_RTCSEL_Pos) ///< HSE oscillator clock divided by 128 used as RTC clock + +#define RCC_BDCR_RTCEN_Pos (15) +#define RCC_BDCR_RTCEN (0x01U << RCC_BDCR_RTCEN_Pos) ///< RTC clock enable +#define RCC_BDCR_BDRST_Pos (16) +#define RCC_BDCR_BDRST (0x01U << RCC_BDCR_BDRST_Pos) ///< Backup domain software reset +#define RCC_BDCR_DBP_Pos (24) +#define RCC_BDCR_DBP (0x01U << RCC_BDCR_DBP_Pos) ///< DBP clock enable + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief RCC_CSR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define RCC_CSR_LSION_Pos (0) +#define RCC_CSR_LSION (0x01U << RCC_CSR_LSION_Pos) ///< Internal Low Speed oscillator enable +#define RCC_CSR_LSIRDY_Pos (1) +#define RCC_CSR_LSIRDY (0x01U << RCC_CSR_LSIRDY_Pos) ///< Internal Low Speed oscillator Ready +#define RCC_CSR_LSIOENLV_Pos (5) +#define RCC_CSR_LSIOENLV (0x01U << RCC_CSR_LSIOENLV_Pos) ///< LSI output enable lower voltage +#define RCC_CSR_PVDRSTEN_Pos (6) +#define RCC_CSR_PVDRSTEN (0x01U << RCC_CSR_PVDRSTEN_Pos) ///< PVD reset enable +#define RCC_CSR_LOCKUPEN_Pos (7) +#define RCC_CSR_LOCKUPEN (0x01U << RCC_CSR_LOCKUPEN_Pos) ///< CPU lockup reset enable +#define RCC_CSR_VDTRSTNEN_Pos (8) +#define RCC_CSR_VDTRSTNEN (0x01U << RCC_CSR_VDTRSTNEN_Pos) ///< Voltage detect reset enable +#define RCC_CSR_VDTRSTF_Pos (21) +#define RCC_CSR_VDTRSTF (0x01U << RCC_CSR_VDTRSTF_Pos) ///< Voltage detect reset flag +#define RCC_CSR_PVDRSTF_Pos (22) +#define RCC_CSR_PVDRSTF (0x01U << RCC_CSR_PVDRSTF_Pos) ///< PVD reset flag +#define RCC_CSR_LOCKUPF_Pos (23) +#define RCC_CSR_LOCKUPF (0x01U << RCC_CSR_LOCKUPF_Pos) ///< CPU lockup reset flag + +#define RCC_CSR_RMVF_Pos (24) +#define RCC_CSR_RMVF (0x01U << RCC_CSR_RMVF_Pos) ///< Remove reset flag +#define RCC_CSR_PINRSTF_Pos (26) +#define RCC_CSR_PINRSTF (0x01U << RCC_CSR_PINRSTF_Pos) ///< PIN reset flag + +#define RCC_CSR_PORRSTF_Pos (27) +#define RCC_CSR_PORRSTF (0x01U << RCC_CSR_PORRSTF_Pos) ///< POR/PDR reset flag + +#define RCC_CSR_SFTRSTF_Pos (28) +#define RCC_CSR_SFTRSTF (0x01U << RCC_CSR_SFTRSTF_Pos) ///< Software Reset flag + +#define RCC_CSR_IWDGRSTF_Pos (29) +#define RCC_CSR_IWDGRSTF (0x01U << RCC_CSR_IWDGRSTF_Pos) ///< Independent Watchdog reset flag + +#define RCC_CSR_WWDGRSTF_Pos (30) +#define RCC_CSR_WWDGRSTF (0x01U << RCC_CSR_WWDGRSTF_Pos) ///< Window watchdog reset flag + +//////////////////////////////////////////////////////////////////////////////// +/// @brief RCC_AHBRSTR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define RCC_AHBRSTR_GPIOA_Pos (0) +#define RCC_AHBRSTR_GPIOA (0x01U << RCC_AHBRSTR_GPIOA_Pos) ///< GPIOA clock reset +#define RCC_AHBRSTR_GPIOB_Pos (1) +#define RCC_AHBRSTR_GPIOB (0x01U << RCC_AHBRSTR_GPIOB_Pos) ///< GPIOB clock reset +#define RCC_AHBRSTR_GPIOC_Pos (2) +#define RCC_AHBRSTR_GPIOC (0x01U << RCC_AHBRSTR_GPIOC_Pos) ///< GPIOC clock reset +#define RCC_AHBRSTR_GPIOD_Pos (3) +#define RCC_AHBRSTR_GPIOD (0x01U << RCC_AHBRSTR_GPIOD_Pos) ///< GPIOD clock reset +#define RCC_AHBRSTR_GPIOE_Pos (4) +#define RCC_AHBRSTR_GPIOE (0x01U << RCC_AHBRSTR_GPIOE_Pos) ///< GPIOE clock reset +#define RCC_AHBRSTR_GPIOF_Pos (5) +#define RCC_AHBRSTR_GPIOF (0x01U << RCC_AHBRSTR_GPIOF_Pos) ///< GPIOF clock reset +#define RCC_AHBRSTR_GPIOG_Pos (6) +#define RCC_AHBRSTR_GPIOG (0x01U << RCC_AHBRSTR_GPIOG_Pos) ///< GPIOG clock reset +#define RCC_AHBRSTR_GPIOH_Pos (7) +#define RCC_AHBRSTR_GPIOH (0x01U << RCC_AHBRSTR_GPIOH_Pos) ///< GPIOH clock reset +#define RCC_AHBRSTR_SDIO_Pos (10) +#define RCC_AHBRSTR_SDIO (0x01U << RCC_AHBRSTR_SDIO_Pos) ///< SDIO clock reset +#define RCC_AHBRSTR_CRC_Pos (12) +#define RCC_AHBRSTR_CRC (0x01U << RCC_AHBRSTR_CRC_Pos) ///< CRC clock reset +#define RCC_AHBRSTR_DMA1_Pos (21) +#define RCC_AHBRSTR_DMA1 (0x01U << RCC_AHBRSTR_DMA1_Pos) ///< DMA1 clock reset +#define RCC_AHBRSTR_DMA2_Pos (22) +#define RCC_AHBRSTR_DMA2 (0x01U << RCC_AHBRSTR_DMA2_Pos) ///< DMA2 clock reset +#define RCC_AHBRSTR_ETHMAC_Pos (25) +#define RCC_AHBRSTR_ETHMAC (0x01U << RCC_AHBRSTR_ETHMAC_Pos) ///< ETHMAC clock reset +//////////////////////////////////////////////////////////////////////////////// +/// @brief RCC_SYSCFG Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// + +#define RCC_SYSCFG_PROGCHECKEN_Pos (0) +#define RCC_SYSCFG_PROGCHECKEN (0x01U << RCC_SYSCFG_PROGCHECKEN_Pos) ///< Whether to check the number in Flash when writing to Flash +#define RCC_SYSCFG_SECTOR1KCFG_Pos (1) +#define RCC_SYSCFG_SECTOR1KCFG (0x01U << RCC_SYSCFG_SECTOR1KCFG_Pos) ///< The size of the Flash page when erased. +#define RCC_SYSCFG_DATAPREFETCH_Pos (2) +#define RCC_SYSCFG_DATAPREFETCH (0x01U << RCC_SYSCFG_DATAPREFETCH_Pos) ///< DATA prefetch module enable bit +#define RCC_SYSCFG_PAD_OSC_TRIM_Pos (8) +#define RCC_SYSCFG_PAD_OSC_TRIM (0x1FU << RCC_SYSCFG_PAD_OSC_TRIM_Pos) ///< Calibration value of external crystal vibration +#define RCC_SYSCFG_OSC_LPFEN_Pos (14) +#define RCC_SYSCFG_OSC_LPFEN (0x01U << RCC_SYSCFG_OSC_LPFEN_Pos) ///< External crystal oscillator low pass filtering enables +//////////////////////////////////////////////////////////////////////////////// +/// @brief RCC_CFGR2 Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define RCC_CFGR2_TIMADVCKSEL_Pos (1) +#define RCC_CFGR2_TIMADVCKSEL (0x01U << RCC_CFGR2_TIMADVCKSEL_Pos) ///< TIMADV_CKSEL +#define RCC_CFGR2_TIMADV_PRE_Pos (1) ///< +#define RCC_CFGR2_TIMADV_PRE (0x07U << RCC_CFGR2_TIMADV_PRE_Pos) ///< SYSCLK's advance points are controlled by the software Frequency coefficient +#define RCC_CFGR2_FSMC_PRE_Pos (8) +#define RCC_CFGR2_FSMC_PRE (0x1FU << RCC_CFGR2_FSMC_PRE_Pos) ///< FSMC Output clock frequency division factor +#define RCC_CFGR2_APB1_CLK_HV_PRE_Pos (16) +#define RCC_CFGR2_APB1_CLK_HV_PRE (0x0FU << RCC_CFGR2_APB1_CLK_HV_PRE_Pos) ///< APB1 Output clock frequency division factor +//////////////////////////////////////////////////////////////////////////////// +/// @brief RCC_ICSCR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define RCC_ICSCR_TIME_CRS_SEL_Pos (0) +#define RCC_ICSCR_TIME_CRS_SEL (0x01U << RCC_ICSCR_TIME_CRS_SEL_Pos) ///< Whether to use the CRS module as source +#define RCC_ICSCR_HSI_CAL_SEL_Pos (11) ///< +#define RCC_ICSCR_HSI_CAL_SEL (0x1FU << RCC_ICSCR_HSI_CAL_SEL_Pos) ///< Select the internal high speed clock calibration value +#define RCC_ICSCR_HSI_CAL_SFT_Pos (16) +#define RCC_ICSCR_HSI_CAL_SFT (0x3FU << RCC_ICSCR_HSI_CAL_SFT_Pos) ///< Internal high-speed clock calibration +//////////////////////////////////////////////////////////////////////////////// +/// @brief RCC_PLLCFGR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define RCC_PLLCFGR_PLLSRC_Pos (0) +#define RCC_PLLCFGR_PLLSRC (0x01U << RCC_PLLCFGR_PLLSRC_Pos) ///< PLL entry clock source +#define RCC_PLLCFGR_PLLXTPRE_Pos (1) ///< +#define RCC_PLLCFGR_PLLXTPRE (0x01U << RCC_PLLCFGR_PLLXTPRE_Pos) ///< HSE divider for PLL entry +#define RCC_PLLCFGR_PLL_ICTRL_Pos (2) +#define RCC_PLLCFGR_PLL_ICTRL (0x03U << RCC_PLLCFGR_PLL_ICTRL_Pos) ///< PLL CP current control signals +#define RCC_PLLCFGR_PLL_LDS_Pos (4) +#define RCC_PLLCFGR_PLL_LDS (0x03U << RCC_PLLCFGR_PLL_LDS_Pos) ///< PLL lock detector accuracy select +#define RCC_PLLCFGR_PLL_DP_Pos (8) ///< +#define RCC_PLLCFGR_PLL_DP (0x07U << RCC_PLLCFGR_PLL_DP_Pos) ///< PLL divider factor DP +#define RCC_PLLCFGR_PLL_DN_Pos (16) +#define RCC_PLLCFGR_PLL_DN (0x7FU << RCC_PLLCFGR_PLL_DN_Pos) ///< PLL divider factor DN +//////////////////////////////////////////////////////////////////////////////// +/// @brief RCC_HSIDLY Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define RCC_HSIDLY_HSI_EQU_CNT (0xFFU) ///< HSI delay time +//////////////////////////////////////////////////////////////////////////////// +/// @brief RCC_HSEDLY Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define RCC_HSEDLY_HSI_EQU_CNT (0xFFFFU) ///< HSE delay time +//////////////////////////////////////////////////////////////////////////////// +/// @brief RCC_PLLDLY Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define RCC_PLLDLY_HSI_EQU_CNT (0xFFU) ///< PLL delay time + + + +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +#endif +//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_rtc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_rtc.h new file mode 100644 index 000000000..7f8acab01 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_rtc.h @@ -0,0 +1,203 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file reg_rtc.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF +/// MM32 FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion + +#ifndef __REG_RTC_H +#define __REG_RTC_H + +// Files includes + +#include +#include +#include "types.h" + + + + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + + + + + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief RTC Base Address Definition +//////////////////////////////////////////////////////////////////////////////// +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) ///< Base Address: 0x40002800 + + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief RTC Registers Structure Definition +//////////////////////////////////////////////////////////////////////////////// +typedef struct { + union { + __IO u32 CR; ///< Control Register, offset: 0x00 + __IO u32 CRH; + }; + union { + __IO u32 CSR; ///< Control & Status Register, offset: 0x04 + __IO u32 CRL; + }; + __IO u32 PRLH; ///< Prescaler Reload Value High, offset: 0x08 + __IO u32 PRLL; ///< Prescaler Reload Value Low, offset: 0x0C + __IO u32 DIVH; ///< Clock Divider High, offset: 0x10 + __IO u32 DIVL; ///< Clock Divider Low, offset: 0x14 + __IO u32 CNTH; ///< Counter High, offset: 0x18 + __IO u32 CNTL; ///< Counter Low, offset: 0x1C + __IO u32 ALRH; ///< Alarm High, offset: 0x20 + __IO u32 ALRL; ///< Alarm Low, offset: 0x24 + __IO u32 MSRH; ///< Millisecond alarm high register offset: 0x28 + __IO u32 MSRL; ///< Millisecond alarm low register offset: 0x2C + __IO u32 RESERVED0; ///< Reserved offset: 0x30 + __IO u32 RESERVED1; ///< Reserved offset: 0x34 + __IO u32 RESERVED2; ///< Reserved offset: 0x38 + __IO u32 LSE_CFG; ///< LSE configure register offset: 0x3C +} RTC_TypeDef; + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief RTC type pointer Definition +//////////////////////////////////////////////////////////////////////////////// +#define RTC ((RTC_TypeDef*)RTC_BASE) + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief RTC_CR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define RTC_CR_SECIE_Pos (0) +#define RTC_CR_SECIE (0x01U << RTC_CR_SECIE_Pos) ///< Second Interrupt Enable +#define RTC_CR_ALRIE_Pos (1) +#define RTC_CR_ALRIE (0x01U << RTC_CR_ALRIE_Pos) ///< Alarm Interrupt Enable +#define RTC_CR_OWIE_Pos (2) +#define RTC_CR_OWIE (0x01U << RTC_CR_OWIE_Pos) ///< OverfloW Interrupt Enable + +//////////////////////////////////////////////////////////////////////////////// +/// @brief RTC_CSR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define RTC_CSR_SECF_Pos (0) +#define RTC_CSR_SECF (0x01 << RTC_CSR_SECF_Pos) ///< Second Flag +#define RTC_CSR_ALRF_Pos (1) +#define RTC_CSR_ALRF (0x01 << RTC_CSR_ALRF_Pos) ///< Alarm Flag +#define RTC_CSR_OWF_Pos (2) +#define RTC_CSR_OWF (0x01 << RTC_CSR_OWF_Pos) ///< OverfloW Flag +#define RTC_CSR_RSF_Pos (3) +#define RTC_CSR_RSF (0x01 << RTC_CSR_RSF_Pos) ///< Registers Synchronized Flag +#define RTC_CSR_CNF_Pos (4) +#define RTC_CSR_CNF (0x01 << RTC_CSR_CNF_Pos) ///< Configuration Flag +#define RTC_CSR_RTOFF_Pos (5) +#define RTC_CSR_RTOFF (0x01 << RTC_CSR_RTOFF_Pos) ///< RTC operation OFF +#define RTC_CSR_ALPEN_Pos (6) +#define RTC_CSR_ALPEN (0x01 << RTC_CSR_ALPEN_Pos) ///< RTC Alarm Loop Enable +//////////////////////////////////////////////////////////////////////////////// +/// @brief RTC_PRLH Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define RTC_PRLH_PRL_Pos (0) +#define RTC_PRLH_PRL (0x0F << RTC_PRLH_PRL_Pos) ///< RTC Prescaler Reload Value High + +//////////////////////////////////////////////////////////////////////////////// +/// @brief RTC_PRLL Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define RTC_PRLL_PRL_Pos (0) +#define RTC_PRLL_PRL (0xFFFFU << RTC_PRLL_PRL_Pos) ///< RTC Prescaler Reload Value Low + +//////////////////////////////////////////////////////////////////////////////// +/// @brief RTC_DIVH Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define RTC_DIVH_DIV_Pos (0) +#define RTC_DIVH_DIV (0x0F << RTC_DIVH_DIV_Pos) ///< RTC Clock Divider High + +//////////////////////////////////////////////////////////////////////////////// +/// @brief RTC_DIVL Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define RTC_DIVL_DIV_Pos (0) +#define RTC_DIVL_DIV (0xFFFFU << RTC_DIVL_DIV_Pos) ///< RTC Clock Divider Low + +//////////////////////////////////////////////////////////////////////////////// +/// @brief RTC_CNTH Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define RTC_CNTH_CNT_Pos (0) +#define RTC_CNTH_CNT (0xFFFFU << RTC_CNTH_CNT_Pos) ///< RTC Counter High + +//////////////////////////////////////////////////////////////////////////////// +/// @brief RTC_CNTL Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define RTC_CNTL_CNT_Pos (0) +#define RTC_CNTL_CNT (0xFFFFU << RTC_CNTL_CNT_Pos) ///< RTC Counter Low + +//////////////////////////////////////////////////////////////////////////////// +/// @brief RTC_ALRH Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define RTC_ALRH_ALR_Pos (0) +#define RTC_ALRH_ALR (0xFFFFU << RTC_ALRH_ALR_Pos) ///< RTC Alarm High + +//////////////////////////////////////////////////////////////////////////////// +/// @brief RTC_ALRL Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define RTC_ALRL_ALR_Pos (0) +#define RTC_ALRL_ALR (0xFFFFU << RTC_ALRL_ALR_Pos) ///< RTC Alarm Low + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief RTC_MSRH Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define RTC_MSRH_MSR_Pos (0) +#define RTC_MSRH_MSR (0xFFFFU << RTC_MSRH_MSR_Pos) ///< RTC MS Alarm Register High + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief RTC_MSRL Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define RTC_MSRL_MSR_Pos (0) +#define RTC_MSRL_MSR (0xFFFFU << RTC_MSRL_MSR_Pos) ///< RTC MS Alarm Register Low + +//////////////////////////////////////////////////////////////////////////////// +/// @brief RTC_LSE_CFG Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// + +#define RTC_LSE_CFG_TEST_Pos (0) +#define RTC_LSE_CFG_TEST (0x0FU << RTC_LSE_CFG_TEST_Pos) ///< Test control signal +#define RTC_LSE_CFG_DR_Pos (4) +#define RTC_LSE_CFG_DR (0x03U << RTC_LSE_CFG_DR_Pos) ///< Drive capability selection +#define RTC_LSE_CFG_RFB_SEL_Pos (6) +#define RTC_LSE_CFG_RFB_SEL_3 (0x03U << RTC_LSE_CFG_RFB_SEL_Pos) ///< Feedback resistance selection 3M +#define RTC_LSE_CFG_RFB_SEL_6 (0x02U << RTC_LSE_CFG_RFB_SEL_Pos) ///< Feedback resistance selection 6M +#define RTC_LSE_CFG_RFB_SEL_10 (0x01U << RTC_LSE_CFG_RFB_SEL_Pos) ///< Feedback resistance selection 10M +#define RTC_LSE_CFG_RFB_SEL_12 (0x00U << RTC_LSE_CFG_RFB_SEL_Pos) ///< Feedback resistance selection 12M +#define RTC_LSE_CFG_IB_Pos (8) +#define RTC_LSE_CFG_IB (0x01U << RTC_MSRL_MSR_Pos) ///< Bias current regulation + + +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +#endif +//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_sdio.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_sdio.h new file mode 100644 index 000000000..9c5d0cb60 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_sdio.h @@ -0,0 +1,391 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file reg_sdio.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF +/// MM32 FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion + +#ifndef __REG_SDIO_H +#define __REG_SDIO_H + +// Files includes + +#include +#include +//#include "types.h" +#include "mm32_reg.h" + +//#if defined ( __CC_ARM ) +//#pragma anon_unions +//#endif + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SDIO Base Address Definition +//////////////////////////////////////////////////////////////////////////////// +#define SDIO_BASE (0x40018000U) ///< Base Address: 0x40018000 + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SDIO Register Structure Definition +//////////////////////////////////////////////////////////////////////////////// + +typedef struct { + __IO u32 MMC_CTRL; ///< SDIO transmit data register, offset: 0x00 + __IO u32 MMC_IO; ///< SDIO receive data register, offset: 0x04 + __IO u32 MMC_BYTECNTL; ///< SDIO current state register, offset: 0x08 + __IO u32 MMC_TR_BLOCKCNT; ///< SDIO interruput state register, offset: 0x0C + __IO u32 MMC_CRCCTL; ///< SDIO interruput enable register, offset: 0x10 + __IO u32 CMD_CRC; ///< SDIO interruput control register, offset: 0x14 + __IO u32 DAT_CRCL; ///< SDIO global control register, offset: 0x18 + __IO u32 DAT_CRCH; ///< SDIO common control register, offset: 0x1C + __IO u32 MMC_PORT; ///< SDIO baud rate control register, offset: 0x20 + __IO u32 MMC_INT_MASK; ///< SDIO receive data number register, offset: 0x24 + __IO u32 CLR_MMC_INT; ///< SDIO chip select register, offset: 0x28 + __IO u32 MMC_CARDSEL; ///< SDIO extand control register, offset: 0x2C + __IO u32 MMC_SIG; ///< 0ffset: 0x30 + __IO u32 MMC_IO_MBCTL; ///< 0ffset: 0x34 + __IO u32 MMC_BLOCKCNT; ///< 0ffset: 0x38 + __IO u32 MMC_TIMEOUTCNT; ///< 0ffset: 0x3C + __IO u32 CMD_BUF0; ///< 0ffset: 0x40 + __IO u32 CMD_BUF1; ///< 0ffset: 0x44 + __IO u32 CMD_BUF2; ///< 0ffset: 0x48 + __IO u32 CMD_BUF3; ///< 0ffset: 0x4C + __IO u32 CMD_BUF4; ///< 0ffset: 0x50 + __IO u32 CMD_BUF5; ///< 0ffset: 0x54 + __IO u32 CMD_BUF6; ///< 0ffset: 0x58 + __IO u32 CMD_BUF7; ///< 0ffset: 0x5C + __IO u32 CMD_BUF8; ///< 0ffset: 0x60 + __IO u32 CMD_BUF9; ///< 0ffset: 0x64 + __IO u32 CMD_BUF10; ///< 0ffset: 0x68 + __IO u32 CMD_BUF11; ///< 0ffset: 0x6C + __IO u32 CMD_BUF12; ///< 0ffset: 0x70 + __IO u32 CMD_BUF13; ///< 0ffset: 0x74 + __IO u32 CMD_BUF14; ///< 0ffset: 0x78 + __IO u32 CMD_BUF15; ///< 0ffset: 0x7C + __IO u32 BUF_CTL; ///< 0ffset: 0x80 + + __IO u32 RESERVED[31]; ///< 0ffset: 0x84 + union { + __IO u32 DATA_BUF0; ///< 0ffset: 0x100 + __IO u32 FIFO; + }; + __IO u32 DATA_BUF1; ///< 0ffset: 0x104 + __IO u32 DATA_BUF2; ///< 0ffset: 0x108 + __IO u32 DATA_BUF3; ///< 0ffset: 0x10C + __IO u32 DATA_BUF4; ///< 0ffset: 0x110 +} SDIO_TypeDef; + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SDIO type pointer Definition +//////////////////////////////////////////////////////////////////////////////// +#define SDIO ((SDIO_TypeDef*) SDIO_BASE) + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SDIO_MMC_CTRL Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define SDIO_MMC_CTRL_OPMSel_Pos (0) +#define SDIO_MMC_CTRL_OPMSel (0x01U << SDIO_MMC_CTRL_OPMSel_Pos) ///< SD/MMC/SDIO port operation mode select +#define SDIO_MMC_CTRL_SelSM_Pos (1) +#define SDIO_MMC_CTRL_SelSM (0x01U << SDIO_MMC_CTRL_SelSM_Pos) ///< Select automatic mode +#define SDIO_MMC_CTRL_OUTM_Pos (2) +#define SDIO_MMC_CTRL_OUTM (0x01U << SDIO_MMC_CTRL_OUTM_Pos) ///< SD/MMC/SDIO port CMD line output driver mode selection Open drain +#define SDIO_MMC_CTRL_CLKSP_Pos (3) +#define SDIO_MMC_CTRL_CLKSP2 (0x00U << SDIO_MMC_CTRL_CLKSP_Pos) ///< SD/MMC/SDIO port CLK linespeedselection 1/2 baseclock +#define SDIO_MMC_CTRL_CLKSP4 (0x01U << SDIO_MMC_CTRL_CLKSP_Pos) ///< SD/MMC/SDIO port CLK linespeedselection 1/4 baseclock +#define SDIO_MMC_CTRL_CLKSP6 (0x02U << SDIO_MMC_CTRL_CLKSP_Pos) ///< SD/MMC/SDIO port CLK linespeedselection 1/6 baseclock +#define SDIO_MMC_CTRL_CLKSP8 (0x03U << SDIO_MMC_CTRL_CLKSP_Pos) ///< SD/MMC/SDIO port CLK linespeedselection 1/8 baseclock +#define SDIO_MMC_CTRL_CLKSP10 (0x04U << SDIO_MMC_CTRL_CLKSP_Pos) ///< SD/MMC/SDIO port CLK linespeedselection 1/10 baseclock +#define SDIO_MMC_CTRL_CLKSP12 (0x05U << SDIO_MMC_CTRL_CLKSP_Pos) ///< SD/MMC/SDIO port CLK linespeedselection 1/12 baseclock +#define SDIO_MMC_CTRL_CLKSP14 (0x06U << SDIO_MMC_CTRL_CLKSP_Pos) ///< SD/MMC/SDIO port CLK linespeedselection 1/14 baseclock +#define SDIO_MMC_CTRL_CLKSP16 (0x07U << SDIO_MMC_CTRL_CLKSP_Pos) ///< SD/MMC/SDIO port CLK linespeedselection 1/16 baseclock +#define SDIO_MMC_CTRL_SelPTSM_Pos (6) +#define SDIO_MMC_CTRL_SelPTSM (0x01U << SDIO_MMC_CTRL_SelPTSM_Pos) ///< SelectSD/MMC/SDIO port transfer high speed mode +#define SDIO_MMC_CTRL_DATWT_Pos (7) +#define SDIO_MMC_CTRL_DATWT (0x01U << SDIO_MMC_CTRL_DATWT_Pos) ///< Definethe bus width of SD/MMC/SDIO port DAT line +#define SDIO_MMC_CTRL_MDEN_Pos (8) +#define SDIO_MMC_CTRL_MDEN (0x01U << SDIO_MMC_CTRL_MDEN_Pos) ///< SDIO mode enable +#define SDIO_MMC_CTRL_INTEN_Pos (9) +#define SDIO_MMC_CTRL_INTEN (0x01U << SDIO_MMC_CTRL_INTEN_Pos) ///< SDIO interrupt enale signal +#define SDIO_MMC_CTRL_RDWTEN_Pos (10) +#define SDIO_MMC_CTRL_RDWTEN (0x01U << SDIO_MMC_CTRL_RDWTEN_Pos) ///< SDIO read wait enable signal +//////////////////////////////////////////////////////////////////////////////// +/// @brief SDIO_MMC_IO Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define SDIO_MMC_IO_AUTODATTR_Pos (0) +#define SDIO_MMC_IO_AUTODATTR (0x01U << SDIO_MMC_IO_AUTODATTR_Pos) ///< Set up automatic data transfer +#define SDIO_MMC_IO_TRANSFDIR_Pos (1) +#define SDIO_MMC_IO_TRANSFDIR (0x01U << SDIO_MMC_IO_TRANSFDIR_Pos) ///< Set the direction of data transfer +#define SDIO_MMC_IO_AUTOTR_Pos (2) +#define SDIO_MMC_IO_AUTOTR (0x01U << SDIO_MMC_IO_AUTOTR_Pos) ///< Set up automatic 8-bit/command/response transmission. +#define SDIO_MMC_IO_RESPCMDSEL_Pos (3) +#define SDIO_MMC_IO_RESPCMDSEL (0x01U << SDIO_MMC_IO_RESPCMDSEL_Pos) ///< Receive response +#define SDIO_MMC_IO_CID_CSDRD_Pos (4) +#define SDIO_MMC_IO_CID_CSDRD (0x01U << SDIO_MMC_IO_CID_CSDRD_Pos) ///< CID and CSD reads +#define SDIO_MMC_IO_PCLKG_Pos (5) +#define SDIO_MMC_IO_PCLKG (0x01U << SDIO_MMC_IO_PCLKG_Pos) ///< SD/MMC/SDIO port CLK line 8 empty clock generated +#define SDIO_MMC_IO_ENRRESP_Pos (6) +#define SDIO_MMC_IO_ENRRESP (0x01U << SDIO_MMC_IO_ENRRESP_Pos) ///< Enable automatic receiving of responses after a command +#define SDIO_MMC_IO_AUTOCLKG_Pos (7) +#define SDIO_MMC_IO_AUTOCLKG (0x01U << SDIO_MMC_IO_AUTOCLKG_Pos) ///< Enable automatic conversion of the 8 empty clock after a response/command or a single block of data +#define SDIO_MMC_IO_CMDCH_Pos (8) +#define SDIO_MMC_IO_CMDCH (0x01U << SDIO_MMC_IO_CMDCH_Pos) ///< SDIO mode enable +#define SDIO_MMC_IO_CMDAF_Pos (9) +#define SDIO_MMC_IO_CMDAF (0x01U << SDIO_MMC_IO_CMDAF_Pos) ///< SDIO CMD12 / IO abort flag +//////////////////////////////////////////////////////////////////////////////// +/// @brief SDIO_MMC_BYTECNTL Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define SDIO_MMC_BYTECNTL_CNT (0xFFFFU) ///< Data transfer byte count register +//////////////////////////////////////////////////////////////////////////////// +/// @brief SDIO_MMC_TR_BLOCKCNT Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define SDIO_MMC_TR_BLOCKCNT_CNT (0xFFFFU) ///< The value of the counter that completes the transfer when multiple blocks are transferred. +//////////////////////////////////////////////////////////////////////////////// +/// @brief SDIO_MMC_CRCCTL Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define SDIO_MMC_CRCCTL_DAT_CRCE_Pos (0) +#define SDIO_MMC_CRCCTL_DAT_CRCE (0x01U << SDIO_MMC_CRCCTL_DAT_CRCE_Pos) ///< DAT CRC error +#define SDIO_MMC_CRCCTL_CMD_CRCE_Pos (1) +#define SDIO_MMC_CRCCTL_CMD_CRCE (0x01U << SDIO_MMC_CRCCTL_CMD_CRCE_Pos) ///< CMD CRC error +#define SDIO_MMC_CRCCTL_DAT_CRCS_Pos (2) +#define SDIO_MMC_CRCCTL_DAT_CRCS (0x03U << SDIO_MMC_CRCCTL_DAT_CRCS_Pos) ///< DAT CRC selection +#define SDIO_MMC_CRCCTL_ENRDMB_Pos (4) +#define SDIO_MMC_CRCCTL_ENRDMB (0x01U << SDIO_MMC_CRCCTL_ENRDMB_Pos) ///< Enable reading multiple blocks of data before responding +#define SDIO_MMC_CRCCTL_ENCHK_Pos (5) +#define SDIO_MMC_CRCCTL_ENCHK (0x01U << SDIO_MMC_CRCCTL_ENCHK_Pos) ///< Enable automatic checking +#define SDIO_MMC_CRCCTL_DAT_CRCEN_Pos (6) +#define SDIO_MMC_CRCCTL_DAT_CRCEN (0x01U << SDIO_MMC_CRCCTL_DAT_CRCEN_Pos) ///< SD/MMC/SDIO PORT DAT line CRC circuit enablement +#define SDIO_MMC_CRCCTL_CMD_CRCEN_Pos (7) +#define SDIO_MMC_CRCCTL_CMD_CRCEN (0x01U << SDIO_MMC_CRCCTL_CMD_CRCEN_Pos) ///< SD/MMC/SDIO port CMD line CRC circuit enablement +//////////////////////////////////////////////////////////////////////////////// +/// @brief SDIO_CMD_CRC Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define SDIO_CMD_CRC_CMD_CRCV (0x7FU) ///< CMD_CRCV register value +//////////////////////////////////////////////////////////////////////////////// +/// @brief SDIO_DAT_CRCL Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define SDIO_DAT_CRCL_DAT_CRCLV (0xFFU) ///< CMD_CRCV low register value +//////////////////////////////////////////////////////////////////////////////// +/// @brief SDIO_DAT_CRCH Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define SDIO_DAT_CRCL_DAT_CRCHV (0xFFU) ///< CMD_CRCV high register value +//////////////////////////////////////////////////////////////////////////////// +/// @brief SDIO_MMC_PORT Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define SDIO_MMC_PORT_NTCR_Pos (0) +#define SDIO_MMC_PORT_NTCR (0x0FU << SDIO_MMC_PORT_NTCR_Pos) ///< Ncr timeout count register +#define SDIO_MMC_PORT_AUTONTEN_Pos (4) +#define SDIO_MMC_PORT_AUTONTEN (0x01U << SDIO_MMC_PORT_AUTONTEN_Pos) ///< Automatic Ncr timer output enablement +#define SDIO_MMC_PORT_PDATS_Pos (5) +#define SDIO_MMC_PORT_PDATS (0x01U << SDIO_MMC_PORT_PDATS_Pos) ///< SD/MMC/SDIO port DAT line signal +#define SDIO_MMC_PORT_PCMDS_Pos (6) +#define SDIO_MMC_PORT_PCMDS (0x01U << SDIO_MMC_PORT_PCMDS_Pos) ///< SD/MMC/SDIO port CMD line signal +#define SDIO_MMC_PORT_PCLKS_Pos (7) +#define SDIO_MMC_PORT_PCLKS (0x01U << SDIO_MMC_PORT_PCLKS_Pos) ///< SD/MMC/SDIO port CLK line signal +//////////////////////////////////////////////////////////////////////////////// +/// @brief SDIO_MMC_INT_MASK Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define SDIO_MMC_INT_MASK_CMDDINT_Pos (0) +#define SDIO_MMC_INT_MASK_CMDDINT (0x01U << SDIO_MMC_INT_MASK_CMDDINT_Pos) ///
© COPYRIGHT MINDMOTION
+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion + +#ifndef __REG_SPI_H +#define __REG_SPI_H + +// Files includes + +#include +#include +#include "types.h" + + + + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + + + + + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SPI Base Address Definition +//////////////////////////////////////////////////////////////////////////////// +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) ///< Base Address: 0x40003800 +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) ///< Base Address: 0x400013000 +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) ///< Base Address: 0x40003C000 + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SPI Register Structure Definition +//////////////////////////////////////////////////////////////////////////////// +#undef USENCOMBINEREGISTER +#undef USENNEWREGISTER +#undef USENOLDREGISTER +#define USENCOMBINEREGISTER +#ifdef USENCOMBINEREGISTER +typedef struct { + union { + __IO u32 TDR; ///< SPI transmit data register, offset: 0x00 + __IO u32 TXREG; + }; + union { + __IO u32 RDR; ///< SPI receive data register, offset: 0x04 + __IO u32 RXREG; + }; + union { + __IO u32 SR; ///< SPI current state register, offset: 0x08 + __IO u32 CSTAT; + }; + union { + __IO u32 ISR; ///< SPI interruput state register, offset: 0x0C + __IO u32 INTSTAT; + }; + union { + __IO u32 IER; ///< SPI interruput enable register, offset: 0x10 + __IO u32 INTEN; + }; + union { + __IO u32 ICR; ///< SPI interruput control register, offset: 0x14 + __IO u32 INTCLR; + }; + union { + __IO u32 GCR; ///< SPI global control register, offset: 0x18 + __IO u32 GCTL; + }; + union { + __IO u32 CCR; ///< SPI common control register, offset: 0x1C + __IO u32 CCTL; + }; + union { + __IO u32 BRR; ///< SPI baud rate control register, offset: 0x20 + __IO u32 SPBRG; + }; + union { + __IO u32 RDNR; ///< SPI receive data number register, offset: 0x24 + __IO u32 RXDNR; + }; + union { + __IO u32 NSSR; ///< SPI chip select register, offset: 0x28 + __IO u32 SCSR; + }; + union { + __IO u32 ECR; ///< SPI extand control register, offset: 0x2C + __IO u32 EXTCTL; + }; + __IO u32 CFGR; ///< I2S configuration register, offset: 0x30 +} SPI_TypeDef; +#endif +#ifdef USENNEWREGISTER +typedef struct { + __IO u32 TDR; ///< SPI transmit data register, offset: 0x00 + __IO u32 RDR; ///< SPI receive data register, offset: 0x04 + __IO u32 SR; ///< SPI current state register, offset: 0x08 + __IO u32 ISR; ///< SPI interruput state register, offset: 0x0C + __IO u32 IER; ///< SPI interruput enable register, offset: 0x10 + __IO u32 ICR; ///< SPI interruput control register, offset: 0x14 + __IO u32 GCR; ///< SPI global control register, offset: 0x18 + __IO u32 CCR; ///< SPI common control register, offset: 0x1C + __IO u32 BRR; ///< SPI baud rate control register, offset: 0x20 + __IO u32 RDNR; ///< SPI receive data number register, offset: 0x24 + __IO u32 NSSR; ///< SPI chip select register, offset: 0x28 + __IO u32 ECR; ///< SPI extand control register, offset: 0x2C +} SPI_TypeDef; +#endif +#ifdef USENOLDREGISTER +typedef struct { + __IO u32 TXREG; ///< SPI transmit data register, offset: 0x00 + __IO u32 RXREG; ///< SPI receive data register, offset: 0x04 + __IO u32 CSTAT; ///< SPI current state register, offset: 0x08 + __IO u32 INTSTAT; ///< SPI interruput state register, offset: 0x0C + __IO u32 INTEN; ///< SPI interruput enable register, offset: 0x10 + __IO u32 INTCLR; ///< SPI interruput control register, offset: 0x14 + __IO u32 GCTL; ///< SPI global control register, offset: 0x18 + __IO u32 CCTL; ///< SPI common control register, offset: 0x1C + __IO u32 SPBRG; ///< SPI baud rate control register, offset: 0x20 + __IO u32 RXDNR; ///< SPI receive data number register, offset: 0x24 + __IO u32 NSSR; ///< SPI chip select register, offset: 0x28 + __IO u32 EXTCTL; ///< SPI extand control register, offset: 0x2C +} SPI_TypeDef; +#endif + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SPI type pointer Definition +//////////////////////////////////////////////////////////////////////////////// +#define SPI2 ((SPI_TypeDef*) SPI2_BASE) +#define SPI1 ((SPI_TypeDef*) SPI1_BASE) +#define SPI3 ((SPI_TypeDef*) SPI3_BASE) +//////////////////////////////////////////////////////////////////////////////// +/// @brief SPI_TDR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define SPI_TDR_TXREG_Pos (0) +#define SPI_TDR_TXREG (0xFFFFFFFFU << SPI_TDR_TXREG_Pos) ///< Transmit data register + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SPI_RDR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define SPI_RDR_RXREG_Pos (0) +#define SPI_RDR_RXREG (0xFFFFFFFFU << SPI_RDR_RXREG_Pos) ///< Receive data register + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SPI_SR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define SPI_SR_TXEPT_Pos (0) +#define SPI_SR_TXEPT (0x01U << SPI_SR_TXEPT_Pos) ///< Transmitter empty bit +#define SPI_SR_RXAVL_Pos (1) +#define SPI_SR_RXAVL (0x01U << SPI_SR_RXAVL_Pos) ///< Receive available byte data message +#define SPI_SR_TXFULL_Pos (2) +#define SPI_SR_TXFULL (0x01U << SPI_SR_TXFULL_Pos) ///< Transmitter FIFO full status bit +#define SPI_SR_RXAVL_4BYTE_Pos (3) +#define SPI_SR_RXAVL_4BYTE (0x01U << SPI_SR_RXAVL_4BYTE_Pos) ///< Receive available 4 byte data message +#define SPI_SR_TXFADDR_Pos (4) +#define SPI_SR_TXFADDR (0x0FU << SPI_SR_TXFADDR_Pos) ///< Transmit FIFO address +#define SPI_SR_RXFADDR_Pos (8) +#define SPI_SR_RXFADDR (0x0FU << SPI_SR_RXFADDR_Pos) ///< Receive FIFO address +#define SPI_SR_BUSY_Pos (12) +#define SPI_SR_BUSY (0x01U << SPI_SR_BUSY_Pos) ///< Data transfer flag +#define SPI_SR_CHSIDE_Pos (13) +#define SPI_SR_CHSIDE (0x01U << SPI_SR_CHSIDE_Pos) ///< transmission channel +//////////////////////////////////////////////////////////////////////////////// +/// @brief SPI_ISR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define SPI_ISR_TX_INTF_Pos (0) +#define SPI_ISR_TX_INTF (0x01U << SPI_ISR_TX_INTF_Pos) ///< Transmit FIFO available interrupt flag bit +#define SPI_ISR_RX_INTF_Pos (1) +#define SPI_ISR_RX_INTF (0x01U << SPI_ISR_RX_INTF_Pos) ///< Receive data available interrupt flag bit +#define SPI_ISR_UNDERRUN_INTF_Pos (2) +#define SPI_ISR_UNDERRUN_INTF (0x01U << SPI_ISR_UNDERRUN_INTF_Pos) ///< SPI underrun interrupt flag bit +#define SPI_ISR_RXOERR_INTF_Pos (3) +#define SPI_ISR_RXOERR_INTF (0x01U << SPI_ISR_RXOERR_INTF_Pos) ///< Receive overrun error interrupt flag bit +#define SPI_ISR_RXMATCH_INTF_Pos (4) +#define SPI_ISR_RXMATCH_INTF (0x01U << SPI_ISR_RXMATCH_INTF_Pos) ///< Receive data match the RXDNR number, the receive process will be completed and generate the interrupt +#define SPI_ISR_RXFULL_INTF_Pos (5) +#define SPI_ISR_RXFULL_INTF (0x01U << SPI_ISR_RXFULL_INTF_Pos) ///< RX FIFO full interrupt flag bit +#define SPI_ISR_TXEPT_INTF_Pos (6) +#define SPI_ISR_TXEPT_INTF (0x01U << SPI_ISR_TXEPT_INTF_Pos) ///< Transmitter empty interrupt flag bit +#define SPI_ISR_FRE_INTF_Pos (7) +#define SPI_ISR_FRE_INTF (0x01U << SPI_ISR_FRE_INTF_Pos) ///< I2S frame transmission error flag bit +//////////////////////////////////////////////////////////////////////////////// +/// @brief SPI_IER Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define SPI_IER_TX_IEN_Pos (0) +#define SPI_IER_TX_IEN (0x01U << SPI_IER_TX_IEN_Pos) ///< Transmit FIFO empty interrupt enable bit +#define SPI_IER_RX_IEN_Pos (1) +#define SPI_IER_RX_IEN (0x01U << SPI_IER_RX_IEN_Pos) ///< Receive FIFO interrupt enable bit +#define SPI_IER_UNDERRUN_IEN_Pos (2) +#define SPI_IER_UNDERRUN_IEN (0x01U << SPI_IER_UNDERRUN_IEN_Pos) ///< Transmitter underrun interrupt enable bit +#define SPI_IER_RXOERR_IEN_Pos (3) +#define SPI_IER_RXOERR_IEN (0x01U << SPI_IER_RXOERR_IEN_Pos) ///< Overrun error interrupt enable bit +#define SPI_IER_RXMATCH_IEN_Pos (4) +#define SPI_IER_RXMATCH_IEN (0x01U << SPI_IER_RXMATCH_IEN_Pos) ///< Receive data complete interrupt enable bit +#define SPI_IER_RXFULL_IEN_Pos (5) +#define SPI_IER_RXFULL_IEN (0x01U << SPI_IER_RXFULL_IEN_Pos) ///< Receive FIFO full interrupt enable bit +#define SPI_IER_TXEPT_IEN_Pos (6) +#define SPI_IER_TXEPT_IEN (0x01U << SPI_IER_TXEPT_IEN_Pos) ///< Transmit empty interrupt enable bit +#define SPI_IER_FRE_IEN_Pos (7) +#define SPI_IER_FRE_IEN (0x01U << SPI_IER_FRE_IEN_Pos) ///< I2S frame transmission interrupt enable bit +//////////////////////////////////////////////////////////////////////////////// +/// @brief SPI_ICR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define SPI_ICR_TX_ICLR_Pos (0) +#define SPI_ICR_TX_ICLR (0x01U << SPI_ICR_TX_ICLR_Pos) ///< Transmitter FIFO empty interrupt clear bit +#define SPI_ICR_RX_ICLR_Pos (1) +#define SPI_ICR_RX_ICLR (0x01U << SPI_ICR_RX_ICLR_Pos) ///< Receive interrupt clear bit +#define SPI_ICR_UNDERRUN_ICLR_Pos (2) +#define SPI_ICR_UNDERRUN_ICLR (0x01U << SPI_ICR_UNDERRUN_ICLR_Pos) ///< Transmitter underrun interrupt clear bit +#define SPI_ICR_RXOERR_ICLR_Pos (3) +#define SPI_ICR_RXOERR_ICLR (0x01U << SPI_ICR_RXOERR_ICLR_Pos) ///< Overrun error interrupt clear bit +#define SPI_ICR_RXMATCH_ICLR_Pos (4) +#define SPI_ICR_RXMATCH_ICLR (0x01U << SPI_ICR_RXMATCH_ICLR_Pos) ///< Receive completed interrupt clear bit +#define SPI_ICR_RXFULL_ICLR_Pos (5) +#define SPI_ICR_RXFULL_ICLR (0x01U << SPI_ICR_RXFULL_ICLR_Pos) ///< Receiver buffer full interrupt clear bit +#define SPI_ICR_TXEPT_ICLR_Pos (6) +#define SPI_ICR_TXEPT_ICLR (0x01U << SPI_ICR_TXEPT_ICLR_Pos) ///< Transmitter empty interrupt clear bit +#define SPI_ICR_FRE_ICLR_Pos (7) +#define SPI_ICR_FRE_ICLR (0x01U << SPI_ICR_FRE_ICLR_Pos) ///< I2S frame transmission interrupt clear bit +//////////////////////////////////////////////////////////////////////////////// +/// @brief SPI_GCR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define SPI_GCR_SPIEN_Pos (0) +#define SPI_GCR_SPIEN (0x01U << SPI_GCR_SPIEN_Pos) ///< SPI select bit +#define SPI_GCR_IEN_Pos (1) +#define SPI_GCR_IEN (0x01U << SPI_GCR_IEN_Pos) ///< SPI interrupt enable bit +#define SPI_GCR_MODE_Pos (2) +#define SPI_GCR_MODE (0x01U << SPI_GCR_MODE_Pos) ///< Master mode bit +#define SPI_GCR_TXEN_Pos (3) +#define SPI_GCR_TXEN (0x01U << SPI_GCR_TXEN_Pos) ///< Transmit enable bit +#define SPI_GCR_RXEN_Pos (4) +#define SPI_GCR_RXEN (0x01U << SPI_GCR_RXEN_Pos) ///< Receive enable bit + +#define SPI_GCR_RXTLF_Pos (5) +#define SPI_GCR_RXTLF (0x03U << SPI_GCR_RXTLF_Pos) ///< RX FIFO trigger level bit +#define SPI_GCR_RXTLF_One (0x00U << SPI_GCR_RXTLF_Pos) ///< +#define SPI_GCR_RXTLF_Half (0x01U << SPI_GCR_RXTLF_Pos) ///< + +#define SPI_GCR_TXTLF_Pos (7) +#define SPI_GCR_TXTLF (0x03U << SPI_GCR_TXTLF_Pos) ///< TX FIFO trigger level bit +#define SPI_GCR_TXTLF_One (0x00U << SPI_GCR_TXTLF_Pos) ///< +#define SPI_GCR_TXTLF_Half (0x01U << SPI_GCR_TXTLF_Pos) ///< +#define SPI_GCR_DMAEN_Pos (9) +#define SPI_GCR_DMAEN (0x01U << SPI_GCR_DMAEN_Pos) ///< DMA access mode enable +#define SPI_GCR_NSS_Pos (10) +#define SPI_GCR_NSS (0x01U << SPI_GCR_NSS_Pos) ///< NSS select signal that from software or hardware +#define SPI_GCR_DWSEL_Pos (11) +#define SPI_GCR_DWSEL (0x01U << SPI_GCR_DWSEL_Pos) ///< Valid byte or double-word data select signal + +#define SPI_GCR_NSSTOG_Pos (12) +#define SPI_GCR_NSSTOG (0x01U << SPI_GCR_NSSTOG_Pos) ///< Slave select toggle +#define SPI_GCR_PAD_SEL_Pos (13) +#define SPI_GCR_PAD_SEL (0x1FU << SPI_GCR_PAD_SEL_Pos) ///< Bus mapping transformation +//////////////////////////////////////////////////////////////////////////////// +/// @brief SPI_CCR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define SPI_CCR_CPHA_Pos (0) +#define SPI_CCR_CPHA (0x01U << SPI_CCR_CPHA_Pos) ///< Clock phase select bit +#define SPI_CCR_CPOL_Pos (1) +#define SPI_CCR_CPOL (0x01U << SPI_CCR_CPOL_Pos) ///< Clock polarity select bit +#define SPI_CCR_LSBFE_Pos (2) +#define SPI_CCR_LSBFE (0x01U << SPI_CCR_LSBFE_Pos) ///< LSI first enable bit +#define SPI_CCR_SPILEN_Pos (3) +#define SPI_CCR_SPILEN (0x01U << SPI_CCR_SPILEN_Pos) ///< SPI character length bit +#define SPI_CCR_RXEDGE_Pos (4) +#define SPI_CCR_RXEDGE (0x01U << SPI_CCR_RXEDGE_Pos) ///< Receive data edge select +#define SPI_CCR_TXEDGE_Pos (5) +#define SPI_CCR_TXEDGE (0x01U << SPI_CCR_TXEDGE_Pos) ///< Transmit data edge select + +#define SPI_CCR_CPHASEL_Pos (6) +#define SPI_CCR_CPHASEL (0x01U << SPI_CCR_CPHASEL) ///< CPHA polarity select + +#define SPI_CCR_HISPD_Pos (7) +#define SPI_CCR_HISPD (0x01U << SPI_CCR_HISPD) ///< High speed slave mode + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SPI_BRR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define SPI_BRR_DIVF_Pos (0) +#define SPI_BRR_DIVF (0xFFFFU << SPI_BRR_DIVF_Pos) ///< SPI baud rate control register for baud rate + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SPI_RDNR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define SPI_RDNR_RDN_Pos (0) +#define SPI_RDNR_RDN (0xFFFFU << SPI_RDNR_RDN_Pos) ///< The register is used to hold a count of to be received bytes in next receive process + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SPI_NSSR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define SPI_NSSR_NSS_Pos (0) +#define SPI_NSSR_NSS (0xFFU << SPI_NSSR_NSS_Pos) ///< Chip select output signal in Master mode + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SPI_ECR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define SPI_ECR_EXTLEN_Pos (0) +#define SPI_ECR_EXTLEN (0x1FU << SPI_ECR_EXTLEN_Pos) ///< control SPI data length + +//////////////////////////////////////////////////////////////////////////////// +/// @brief I2S_CFGR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// + +#define I2SCFGR_CLEAR_Mask ((u32)0xFE00F388) +#define I2S_CFGR_CHLEN_Pos (0) +#define I2S_CFGR_CHLEN (0x01U << I2S_CFGR_CHLEN_Pos) ///< Vocal tract length +#define I2S_CFGR_DATLEN_Pos (1) +#define I2S_CFGR_DATLEN_16 (0x00U << I2S_CFGR_DATLEN_Pos) ///< Audio data width 16 +#define I2S_CFGR_DATLEN_24 (0x01U << I2S_CFGR_DATLEN_Pos) ///< Audio data width 24 +#define I2S_CFGR_DATLEN_32 (0x02U << I2S_CFGR_DATLEN_Pos) ///< Audio data width 32 + +#define I2S_CFGR_I2SSTD_Pos (4) +#define I2S_CFGR_I2SSTD_PCM (0x00U << I2S_CFGR_I2SSTD_Pos) ///< I2S selection PCM standard +#define I2S_CFGR_I2SSTD_MSB_R (0x01U << I2S_CFGR_I2SSTD_Pos) ///< I2S selection Right alignment (MSB) standard +#define I2S_CFGR_I2SSTD_MSB_L (0x02U << I2S_CFGR_I2SSTD_Pos) ///< I2S selection Left aligned (MSB) standard +#define I2S_CFGR_I2SSTD_Philips (0x03U << I2S_CFGR_I2SSTD_Pos) ///< I2S selection Philips standard + +#define I2S_CFGR_PCMSYNC_Pos (6) +#define I2S_CFGR_PCMSYNC (0x01U << I2S_CFGR_PCMSYNC_Pos) ///< PCM frame synchronization mode +#define I2S_CFGR_SPI_I2S_Pos (10) +#define I2S_CFGR_SPI_I2S (0x01U << I2S_CFGR_SPI_I2S_Pos) ///< SPI/I2S module function selection +#define I2S_CFGR_MCKOE_Pos (11) +#define I2S_CFGR_MCKOE (0x01U << I2S_CFGR_MCKOE_Pos) ///< I2S master clock output enable +#define I2S_CFGR_I2SDIV_Pos (16) +#define I2S_CFGR_I2SDIV (0x1FFU << I2S_CFGR_I2SDIV_Pos) ///< The frequency division + + + +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +#endif +//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_syscfg.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_syscfg.h new file mode 100644 index 000000000..677250dc8 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_syscfg.h @@ -0,0 +1,299 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file reg_syscfg.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF +/// MM32 FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion + +#ifndef __REG_SYSCFG_H +#define __REG_SYSCFG_H + +// Files includes + +#include +#include +#include "types.h" + + + + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + + + + + + + + + +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000) ///< Base Address: 0x40010000 + + + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief SysTem Configuration Register Structure Definition +//////////////////////////////////////////////////////////////////////////////// +typedef struct { + union { + __IO u32 CFGR; ///< SYSCFG configuration register offset: 0x00 + __IO u32 CFGR1; + }; + __IO u32 RESERVED0x04; ///< RESERVED register offset: 0x04 + __IO u32 EXTICR[4]; ///< SYSCFG configuration register offset: 0x08-0x14 + __IO u32 CFGR2; ///< SYSCFG configuration2 register offset: 0x18 + __IO u32 PDETCSR; ///< SYSCFG Power Detect configuration stautus reg offset: 0x1C + __IO u32 VOSDLY; ///< SYSCFG VOSDLY Counter register offset: 0x20 +} SYSCFG_TypeDef; + + +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) + + + +//////////////////////////////////////////////////////////////////////////////// +///@brief System Configuration (SYSCFG) +//////////////////////////////////////////////////////////////////////////////// + +/// @brief SYSCFG_CFGR Register Bit definition +#define SYSCFG_CFGR_MEM_MODE_Pos (0) +#define SYSCFG_CFGR_MEM_MODE ((u32)0x00000003) ///< SYSCFG_Memory Remap Config +#define SYSCFG_CFGR_MEM_MODE_0 ((u32)0x00000001) ///< SYSCFG_Memory Remap Config Bit 0 +#define SYSCFG_CFGR_MEM_MODE_1 ((u32)0x00000002) ///< SYSCFG_Memory Remap Config Bit 1 +/// + +#define SYSCFG_CFGR_FSMC_SYNC_EN_Pos (27) +#define SYSCFG_CFGR_FSMC_SYNC_EN (0x01U << SYSCFG_CFGR_FSMC_SYNC_EN_Pos)///< FSMC SYNC Enable +#define SYSCFG_CFGR_FSMC_AF_ADDR_Pos (28) +#define SYSCFG_CFGR_FSMC_AF_ADDR (0x01U << SYSCFG_CFGR_FSMC_AF_ADDR_Pos)///< FSMC Databus AF Address +#define SYSCFG_CFGR_FSMC_MODE_Pos (29) +#define SYSCFG_CFGR_FSMC_MODE ((u32)0x03<
© COPYRIGHT MINDMOTION
+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion + +#ifndef __REG_TIM_H +#define __REG_TIM_H + +// Files includes + +#include +#include +#include "types.h" + + + + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + + + + + + + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM Base Address Definition +//////////////////////////////////////////////////////////////////////////////// +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) ///< Base Address: 0x40012C00 +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) ///< Base Address: 0x40000000 +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) ///< Base Address: 0x40000400 +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) ///< Base Address: 0x40000800 + +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) ///< Base Address: 0x40000C00 +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) ///< Base Address: 0x40001000 +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) ///< Base Address: 0x40001400 +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) ///< Base Address: 0x40013400 + + + + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief Timer Register Structure Definition +//////////////////////////////////////////////////////////////////////////////// +typedef struct { + __IO u32 CR1; ///< TIM control register 1, offset: 0x00 + __IO u32 CR2; ///< TIM control register 2, offset: 0x04 + __IO u32 SMCR; ///< TIM slave Mode Control register, offset: 0x08 + __IO u32 DIER; ///< TIM DMA/interrupt enable register, offset: 0x0C + __IO u32 SR; ///< TIM status register, offset: 0x10 + __IO u32 EGR; ///< TIM event generation register, offset: 0x14 + __IO u32 CCMR1; ///< TIM capture/compare mode register 1, offset: 0x18 + __IO u32 CCMR2; ///< TIM capture/compare mode register 2, offset: 0x1C + __IO u32 CCER; ///< TIM capture/compare enable register, offset: 0x20 + __IO u32 CNT; ///< TIM counter register, offset: 0x24 + __IO u32 PSC; ///< TIM prescaler register, offset: 0x28 + __IO u32 ARR; ///< TIM auto-reload register, offset: 0x2C + __IO u32 RCR; ///< TIM repetition counter register, offset: 0x30 + __IO u32 CCR1; ///< TIM capture/compare register 1, offset: 0x34 + __IO u32 CCR2; ///< TIM capture/compare register 2, offset: 0x38 + __IO u32 CCR3; ///< TIM capture/compare register 3, offset: 0x3C + __IO u32 CCR4; ///< TIM capture/compare register 4, offset: 0x40 + __IO u32 BDTR; ///< TIM break and dead-time register, offset: 0x44 + __IO u32 DCR; ///< TIM DMA control register, offset: 0x48 + __IO u32 DMAR; ///< TIM DMA address for full transfer register, offset: 0x4C + __IO u32 OR; ///< Option register, offset: 0x50 + __IO u32 CCMR3; ///< TIM capture/compare mode register 3, offset: 0x54 + __IO u32 CCR5; ///< TIM capture/compare register 5, offset: 0x58 + __IO u32 PDER; ///< PWM Shift repeat enable register, offset: 0x5C + __IO u32 CCR1FALL; ///< PWM shift count CCR1 register, offset: 0x60 + __IO u32 CCR2FALL; ///< PWM shift count CCR2 register, offset: 0x64 + __IO u32 CCR3FALL; ///< PWM shift count CCR3 register, offset: 0x68 + __IO u32 CCR4FALL; ///< PWM shift count CCR4 register, offset: 0x6c + __IO u32 CCR5FALL; ///< PWM shift count CCR5 register, offset: 0x70 +} TIM_TypeDef; + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM type pointer Definition +//////////////////////////////////////////////////////////////////////////////// +#define TIM1 ((TIM_TypeDef*) TIM1_BASE) +#define TIM2 ((TIM_TypeDef*) TIM2_BASE) +#define TIM3 ((TIM_TypeDef*) TIM3_BASE) +#define TIM4 ((TIM_TypeDef*) TIM4_BASE) + +#define TIM5 ((TIM_TypeDef*) TIM5_BASE) +#define TIM6 ((TIM_TypeDef*) TIM6_BASE) +#define TIM7 ((TIM_TypeDef*) TIM7_BASE) + +#define TIM8 ((TIM_TypeDef*) TIM8_BASE) + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_CR1 Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define TIM_CR1_CEN_Pos (0) +#define TIM_CR1_CEN (0x01U << TIM_CR1_CEN_Pos) ///< Counter enable +#define TIM_CR1_UDIS_Pos (1) +#define TIM_CR1_UDIS (0x01U << TIM_CR1_UDIS_Pos) ///< Update disable +#define TIM_CR1_URS_Pos (2) +#define TIM_CR1_URS (0x01U << TIM_CR1_URS_Pos) ///< Update request source +#define TIM_CR1_OPM_Pos (3) +#define TIM_CR1_OPM (0x01U << TIM_CR1_OPM_Pos) ///< One pulse mode +#define TIM_CR1_DIR_Pos (4) +#define TIM_CR1_DIR (0x01U << TIM_CR1_DIR_Pos) ///< Direction +#define TIM_CR1_CMS_Pos (5) +#define TIM_CR1_CMS (0x03U << TIM_CR1_CMS_Pos) ///< CMS[1:0] bits (Center-aligned mode selection) +#define TIM_CR1_CMS_EDGEALIGNED (0x00U << TIM_CR1_CMS_Pos) ///< Edge-aligned mode +#define TIM_CR1_CMS_CENTERALIGNED1 (0x01U << TIM_CR1_CMS_Pos) ///< Center-aligned mode 1 +#define TIM_CR1_CMS_CENTERALIGNED2 (0x02U << TIM_CR1_CMS_Pos) ///< Center-aligned mode 2 +#define TIM_CR1_CMS_CENTERALIGNED3 (0x03U << TIM_CR1_CMS_Pos) ///< Center-aligned mode 3 +#define TIM_CR1_ARPEN_Pos (7) +#define TIM_CR1_ARPEN (0x01U << TIM_CR1_ARPEN_Pos) ///< Auto-reload preload enable +#define TIM_CR1_CKD_Pos (8) +#define TIM_CR1_CKD (0x03U << TIM_CR1_CKD_Pos) ///< CKD[1:0] bits (clock division) +#define TIM_CR1_CKD_DIV1 (0x00U << TIM_CR1_CKD_Pos) ///< Divided by 1 +#define TIM_CR1_CKD_DIV2 (0x01U << TIM_CR1_CKD_Pos) ///< Divided by 2 +#define TIM_CR1_CKD_DIV4 (0x02U << TIM_CR1_CKD_Pos) ///< Divided by 4 + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_CR2 Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define TIM_CR2_CCPC_Pos (0) +#define TIM_CR2_CCPC (0x01U << TIM_CR2_CCPC_Pos) ///< Capture/Compare Preloaded Control +#define TIM_CR2_CCUS_Pos (2) +#define TIM_CR2_CCUS (0x01U << TIM_CR2_CCUS_Pos) ///< Capture/Compare Control Update Selection +#define TIM_CR2_CCDS_Pos (3) +#define TIM_CR2_CCDS (0x01U << TIM_CR2_CCDS_Pos) ///< Capture/Compare DMA Selection +#define TIM_CR2_MMS_Pos (4) +#define TIM_CR2_MMS (0x07U << TIM_CR2_MMS_Pos) ///< MMS[2:0] bits (Master Mode Selection) +#define TIM_CR2_MMS_RESET (0x00U << TIM_CR2_MMS_Pos) ///< Master Mode Select: Reset +#define TIM_CR2_MMS_ENABLE (0x01U << TIM_CR2_MMS_Pos) ///< Master Mode Select: Enable +#define TIM_CR2_MMS_UPDATE (0x02U << TIM_CR2_MMS_Pos) ///< Master Mode Select: Update +#define TIM_CR2_MMS_OC1 (0x03U << TIM_CR2_MMS_Pos) ///< Master Mode Select: OC1 +#define TIM_CR2_MMS_OC1REF (0x04U << TIM_CR2_MMS_Pos) ///< Master Mode Select: OC1Ref +#define TIM_CR2_MMS_OC2REF (0x05U << TIM_CR2_MMS_Pos) ///< Master Mode Select: OC2Ref +#define TIM_CR2_MMS_OC3REF (0x06U << TIM_CR2_MMS_Pos) ///< Master Mode Select: OC3Ref +#define TIM_CR2_MMS_OC4REF (0x07U << TIM_CR2_MMS_Pos) ///< Master Mode Select: OC4Ref +#define TIM_CR2_TI1S_Pos (7) +#define TIM_CR2_TI1S (0x01U << TIM_CR2_TI1S_Pos) ///< TI1 Selection +#define TIM_CR2_OIS1_Pos (8) +#define TIM_CR2_OIS1 (0x01U << TIM_CR2_OIS1_Pos) ///< Output Idle state 1 (OC1 output) +#define TIM_CR2_OIS1N_Pos (9) +#define TIM_CR2_OIS1N (0x01U << TIM_CR2_OIS1N_Pos) ///< Output Idle state 1 (OC1N output) +#define TIM_CR2_OIS2_Pos (10) +#define TIM_CR2_OIS2 (0x01U << TIM_CR2_OIS2_Pos) ///< Output Idle state 2 (OC2 output) +#define TIM_CR2_OIS2N_Pos (11) +#define TIM_CR2_OIS2N (0x01U << TIM_CR2_OIS2N_Pos) ///< Output Idle state 2 (OC2N output) +#define TIM_CR2_OIS3_Pos (12) +#define TIM_CR2_OIS3 (0x01U << TIM_CR2_OIS3_Pos) ///< Output Idle state 3 (OC3 output) +#define TIM_CR2_OIS3N_Pos (13) +#define TIM_CR2_OIS3N (0x01U << TIM_CR2_OIS3N_Pos) ///< Output Idle state 3 (OC3N output) +#define TIM_CR2_OIS4_Pos (14) +#define TIM_CR2_OIS4 (0x01U << TIM_CR2_OIS4_Pos) ///< Output Idle state 4 (OC4 output) + + +#define TIM_CR2_OIS5_Pos (16) +#define TIM_CR2_OIS5 (0x01U << TIM_CR2_OIS5_Pos) ///< Output Idle state 5 (OC5 output) + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_SMCR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define TIM_SMCR_SMS_Pos (0) +#define TIM_SMCR_SMS (0x07U << TIM_SMCR_SMS_Pos) ///< SMS[2:0] bits (Slave mode selection) +#define TIM_SMCR_SMS_OFF (0x00U << TIM_SMCR_SMS_Pos) ///< Slave Mode select: OFF +#define TIM_SMCR_SMS_ENCODER1 (0x01U << TIM_SMCR_SMS_Pos) ///< Slave Mode select: Encoder1 +#define TIM_SMCR_SMS_ENCODER2 (0x02U << TIM_SMCR_SMS_Pos) ///< Slave Mode select: Encoder2 +#define TIM_SMCR_SMS_ENCODER3 (0x03U << TIM_SMCR_SMS_Pos) ///< Slave Mode select: Encoder3 +#define TIM_SMCR_SMS_RESET (0x04U << TIM_SMCR_SMS_Pos) ///< Slave Mode select: Reset +#define TIM_SMCR_SMS_GATED (0x05U << TIM_SMCR_SMS_Pos) ///< Slave Mode select: Gated +#define TIM_SMCR_SMS_TRIGGER (0x06U << TIM_SMCR_SMS_Pos) ///< Slave Mode select: Trigger +#define TIM_SMCR_SMS_EXTERNAL1 (0x07U << TIM_SMCR_SMS_Pos) ///< Slave Mode select: External1 + +#define TIM_SMCR_OCCS_Pos (3) +#define TIM_SMCR_OCCS (0x01U << TIM_SMCR_OCCS_Pos) ///< Output compare clear selection + +#define TIM_SMCR_TS_Pos (4) +#define TIM_SMCR_TS (0x07U << TIM_SMCR_TS_Pos) ///< TS[2:0] bits (Trigger selection) +#define TIM_SMCR_TS_ITR0 (0x00U << TIM_SMCR_TS_Pos) ///< Internal Trigger 0 (ITR0) +#define TIM_SMCR_TS_ITR1 (0x01U << TIM_SMCR_TS_Pos) ///< Internal Trigger 1 (ITR1) +#define TIM_SMCR_TS_ITR2 (0x02U << TIM_SMCR_TS_Pos) ///< Internal Trigger 2 (ITR2) +#define TIM_SMCR_TS_ITR3 (0x03U << TIM_SMCR_TS_Pos) ///< Internal Trigger 3 (ITR3) +#define TIM_SMCR_TS_TI1F_ED (0x04U << TIM_SMCR_TS_Pos) ///< TI1 Edge Detector (TI1F_ED) +#define TIM_SMCR_TS_TI1FP1 (0x05U << TIM_SMCR_TS_Pos) ///< Filtered Timer Input 1 (TI1FP1) +#define TIM_SMCR_TS_TI2FP2 (0x06U << TIM_SMCR_TS_Pos) ///< Filtered Timer Input 2 (TI2FP2) +#define TIM_SMCR_TS_ETRF (0x07U << TIM_SMCR_TS_Pos) ///< External Trigger input (ETRF) +#define TIM_SMCR_MSM_Pos (7) +#define TIM_SMCR_MSM (0x01U << TIM_SMCR_MSM_Pos) ///< Master/slave mode +#define TIM_SMCR_ETF_Pos (8) +#define TIM_SMCR_ETF (0x0FU << TIM_SMCR_ETF_Pos) ///< ETF[3:0] bits (External trigger filter) +#define TIM_SMCR_ETF_0 (0x01U << TIM_SMCR_ETF_Pos) ///< Bit 0 +#define TIM_SMCR_ETF_1 (0x02U << TIM_SMCR_ETF_Pos) ///< Bit 1 +#define TIM_SMCR_ETF_2 (0x04U << TIM_SMCR_ETF_Pos) ///< Bit 2 +#define TIM_SMCR_ETF_3 (0x08U << TIM_SMCR_ETF_Pos) ///< Bit 3 +#define TIM_SMCR_ETPS_Pos (12) +#define TIM_SMCR_ETPS (0x03U << TIM_SMCR_ETPS_Pos) ///< ETPS[1:0] bits (External trigger prescaler) +#define TIM_SMCR_ETPS_OFF (0x00U << TIM_SMCR_ETPS_Pos) ///< Prescaler OFF +#define TIM_SMCR_ETPS_DIV2 (0x01U << TIM_SMCR_ETPS_Pos) ///< ETRP frequency divided by 2 +#define TIM_SMCR_ETPS_DIV4 (0x02U << TIM_SMCR_ETPS_Pos) ///< ETRP frequency divided by 4 +#define TIM_SMCR_ETPS_DIV8 (0x03U << TIM_SMCR_ETPS_Pos) ///< ETRP frequency divided by 8 +#define TIM_SMCR_ECEN_Pos (14) +#define TIM_SMCR_ECEN (0x01U << TIM_SMCR_ECEN_Pos) ///< External clock enable +#define TIM_SMCR_ETP_Pos (15) +#define TIM_SMCR_ETP (0x01U << TIM_SMCR_ETP_Pos) ///< External trigger polarity +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_DIER Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define TIM_DIER_UI_Pos (0) +#define TIM_DIER_UI (0x01U << TIM_DIER_UI_Pos) ///< Update interrupt enable +#define TIM_DIER_CC1I_Pos (1) +#define TIM_DIER_CC1I (0x01U << TIM_DIER_CC1I_Pos) ///< Capture/Compare 1 interrupt enable +#define TIM_DIER_CC2I_Pos (2) +#define TIM_DIER_CC2I (0x01U << TIM_DIER_CC2I_Pos) ///< Capture/Compare 2 interrupt enable +#define TIM_DIER_CC3I_Pos (3) +#define TIM_DIER_CC3I (0x01U << TIM_DIER_CC3I_Pos) ///< Capture/Compare 3 interrupt enable +#define TIM_DIER_CC4I_Pos (4) +#define TIM_DIER_CC4I (0x01U << TIM_DIER_CC4I_Pos) ///< Capture/Compare 4 interrupt enable +#define TIM_DIER_COMI_Pos (5) +#define TIM_DIER_COMI (0x01U << TIM_DIER_COMI_Pos) ///< COM interrupt enable +#define TIM_DIER_TI_Pos (6) +#define TIM_DIER_TI (0x01U << TIM_DIER_TI_Pos) ///< Trigger interrupt enable +#define TIM_DIER_BI_Pos (7) +#define TIM_DIER_BI (0x01U << TIM_DIER_BI_Pos) ///< Break interrupt enable +#define TIM_DIER_UD_Pos (8) +#define TIM_DIER_UD (0x01U << TIM_DIER_UD_Pos) ///< Update DMA request enable +#define TIM_DIER_CC1D_Pos (9) +#define TIM_DIER_CC1D (0x01U << TIM_DIER_CC1D_Pos) ///< Capture/Compare 1 DMA request enable +#define TIM_DIER_CC2D_Pos (10) +#define TIM_DIER_CC2D (0x01U << TIM_DIER_CC2D_Pos) ///< Capture/Compare 2 DMA request enable +#define TIM_DIER_CC3D_Pos (11) +#define TIM_DIER_CC3D (0x01U << TIM_DIER_CC3D_Pos) ///< Capture/Compare 3 DMA request enable +#define TIM_DIER_CC4D_Pos (12) +#define TIM_DIER_CC4D (0x01U << TIM_DIER_CC4D_Pos) ///< Capture/Compare 4 DMA request enable +#define TIM_DIER_COMD_Pos (13) +#define TIM_DIER_COMD (0x01U << TIM_DIER_COMD_Pos) ///< COM DMA request enable +#define TIM_DIER_TD_Pos (14) +#define TIM_DIER_TD (0x01U << TIM_DIER_TD_Pos) ///< Trigger DMA request enable +#define TIM_DIER_CC5I_Pos (16) +#define TIM_DIER_CC5I (0x01U << TIM_DIER_CC5I_Pos) ///< Capture/Compare 5 interrupt enable + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_SR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define TIM_SR_UI_Pos (0) +#define TIM_SR_UI (0x01U << TIM_SR_UI_Pos) ///< Update interrupt Flag +#define TIM_SR_CC1I_Pos (1) +#define TIM_SR_CC1I (0x01U << TIM_SR_CC1I_Pos) ///< Capture/Compare 1 interrupt Flag +#define TIM_SR_CC2I_Pos (2) +#define TIM_SR_CC2I (0x01U << TIM_SR_CC2I_Pos) ///< Capture/Compare 2 interrupt Flag +#define TIM_SR_CC3I_Pos (3) +#define TIM_SR_CC3I (0x01U << TIM_SR_CC3I_Pos) ///< Capture/Compare 3 interrupt Flag +#define TIM_SR_CC4I_Pos (4) +#define TIM_SR_CC4I (0x01U << TIM_SR_CC4I_Pos) ///< Capture/Compare 4 interrupt Flag +#define TIM_SR_COMI_Pos (5) +#define TIM_SR_COMI (0x01U << TIM_SR_COMI_Pos) ///< COM interrupt Flag +#define TIM_SR_TI_Pos (6) +#define TIM_SR_TI (0x01U << TIM_SR_TI_Pos) ///< Trigger interrupt Flag +#define TIM_SR_BI_Pos (7) +#define TIM_SR_BI (0x01U << TIM_SR_BI_Pos) ///< Break interrupt Flag +#define TIM_SR_CC1O_Pos (9) +#define TIM_SR_CC1O (0x01U << TIM_SR_CC1O_Pos) ///< Capture/Compare 1 Overcapture Flag +#define TIM_SR_CC2O_Pos (10) +#define TIM_SR_CC2O (0x01U << TIM_SR_CC2O_Pos) ///< Capture/Compare 2 Overcapture Flag +#define TIM_SR_CC3O_Pos (11) +#define TIM_SR_CC3O (0x01U << TIM_SR_CC3O_Pos) ///< Capture/Compare 3 Overcapture Flag +#define TIM_SR_CC4O_Pos (12) +#define TIM_SR_CC4O (0x01U << TIM_SR_CC4O_Pos) ///< Capture/Compare 4 Overcapture Flag + +#define TIM_SR_CC5I_Pos (16) +#define TIM_SR_CC5I (0x01U << TIM_SR_CC5I_Pos) ///< Capture/Compare 5 interrupt Flag + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_EGR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define TIM_EGR_UG_Pos (0) +#define TIM_EGR_UG (0x01U << TIM_EGR_UG_Pos) ///< Update Generation +#define TIM_EGR_CC1G_Pos (1) +#define TIM_EGR_CC1G (0x01U << TIM_EGR_CC1G_Pos) ///< Capture/Compare 1 Generation +#define TIM_EGR_CC2G_Pos (2) +#define TIM_EGR_CC2G (0x01U << TIM_EGR_CC2G_Pos) ///< Capture/Compare 2 Generation +#define TIM_EGR_CC3G_Pos (3) +#define TIM_EGR_CC3G (0x01U << TIM_EGR_CC3G_Pos) ///< Capture/Compare 3 Generation +#define TIM_EGR_CC4G_Pos (4) +#define TIM_EGR_CC4G (0x01U << TIM_EGR_CC4G_Pos) ///< Capture/Compare 4 Generation +#define TIM_EGR_COMG_Pos (5) +#define TIM_EGR_COMG (0x01U << TIM_EGR_COMG_Pos) ///< Capture/Compare Control Update Generation +#define TIM_EGR_TG_Pos (6) +#define TIM_EGR_TG (0x01U << TIM_EGR_TG_Pos) ///< Trigger Generation +#define TIM_EGR_BG_Pos (7) +#define TIM_EGR_BG (0x01U << TIM_EGR_BG_Pos) ///< Break Generation + +#define TIM_EGR_CC5G_Pos (16) +#define TIM_EGR_CC5G (0x01U << TIM_EGR_CC5G_Pos) ///< Capture/Compare 5 Generation + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_CCMR1 Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define TIM_CCMR1_CC1S_Pos (0) +#define TIM_CCMR1_CC1S (0x03U << TIM_CCMR1_CC1S_Pos) ///< CC1S[1:0] bits (Capture/Compare 1 Selection) +#define TIM_CCMR1_CC1S_OC (0x00U << TIM_CCMR1_CC1S_Pos) ///< Channel is configured as output +#define TIM_CCMR1_CC1S_DIRECTTI (0x01U << TIM_CCMR1_CC1S_Pos) ///< Channel is configured as input, IC1 is mapped on TI1 +#define TIM_CCMR1_CC1S_INDIRECTTI (0x02U << TIM_CCMR1_CC1S_Pos) ///< Channel is configured as input, IC1 is mapped on TI2 +#define TIM_CCMR1_CC1S_TRC (0x03U << TIM_CCMR1_CC1S_Pos) ///< Channel is configured as input, IC1 is mapped on TRC +#define TIM_CCMR1_OC1FEN_Pos (2) +#define TIM_CCMR1_OC1FEN (0x01U << TIM_CCMR1_OC1FEN_Pos) ///< Output Compare 1 Fast enable + +#define TIM_CCMR1_OC1PEN_Pos (3) +#define TIM_CCMR1_OC1PEN (0x01U << TIM_CCMR1_OC1PEN_Pos) ///< Output Compare 1 Preload enable +#define TIM_CCMR1_OC1M_Pos (4) +#define TIM_CCMR1_OC1M (0x07U << TIM_CCMR1_OC1M_Pos) ///< OC1M[2:0] bits (Output Compare 1 Mode) +#define TIM_CCMR1_OC1M_TIMING (0x00U << TIM_CCMR1_OC1M_Pos) ///< Timing +#define TIM_CCMR1_OC1M_ACTIVE (0x01U << TIM_CCMR1_OC1M_Pos) ///< Active +#define TIM_CCMR1_OC1M_INACTIVE (0x02U << TIM_CCMR1_OC1M_Pos) ///< Inactive +#define TIM_CCMR1_OC1M_TOGGLE (0x03U << TIM_CCMR1_OC1M_Pos) ///< Toggle +#define TIM_CCMR1_OC1M_FORCEINACTIVE (0x04U << TIM_CCMR1_OC1M_Pos) ///< Forceinactive +#define TIM_CCMR1_OC1M_FORCEACTIVE (0x05U << TIM_CCMR1_OC1M_Pos) ///< Forceactive +#define TIM_CCMR1_OC1M_PWM1 (0x06U << TIM_CCMR1_OC1M_Pos) ///< PWM1 +#define TIM_CCMR1_OC1M_PWM2 (0x07U << TIM_CCMR1_OC1M_Pos) ///< PWM2 + +#define TIM_CCMR1_OC1CEN_Pos (7) +#define TIM_CCMR1_OC1CEN (0x01U << TIM_CCMR1_OC1CEN_Pos) ///< Output Compare 1Clear Enable +#define TIM_CCMR1_CC2S_Pos (8) +#define TIM_CCMR1_CC2S (0x03U << TIM_CCMR1_CC2S_Pos) ///< CC2S[1:0] bits (Capture/Compare 2 Selection) +#define TIM_CCMR1_CC2S_OC (0x00U << TIM_CCMR1_CC2S_Pos) ///< Channel is configured as output +#define TIM_CCMR1_CC2S_DIRECTTI (0x01U << TIM_CCMR1_CC2S_Pos) ///< Channel is configured as input, IC2 is mapped on TI2 +#define TIM_CCMR1_CC2S_INDIRECTTI (0x02U << TIM_CCMR1_CC2S_Pos) ///< Channel is configured as input, IC2 is mapped on TI1 +#define TIM_CCMR1_CC2S_TRC (0x03U << TIM_CCMR1_CC2S_Pos) ///< Channel is configured as input, IC2 is mapped on TRC +#define TIM_CCMR1_OC2FEN_Pos (10) +#define TIM_CCMR1_OC2FEN (0x01U << TIM_CCMR1_OC2FEN_Pos) ///< Output Compare 2 Fast enable +#define TIM_CCMR1_OC2PEN_Pos (11) +#define TIM_CCMR1_OC2PEN (0x01U << TIM_CCMR1_OC2PEN_Pos) ///< Output Compare 2 Preload enable +#define TIM_CCMR1_OC2M_Pos (12) +#define TIM_CCMR1_OC2M (0x07U << TIM_CCMR1_OC2M_Pos) ///< OC2M[2:0] bits (Output Compare 2 Mode) +#define TIM_CCMR1_OC2M_TIMING (0x00U << TIM_CCMR1_OC2M_Pos) ///< Timing +#define TIM_CCMR1_OC2M_ACTIVE (0x01U << TIM_CCMR1_OC2M_Pos) ///< Active +#define TIM_CCMR1_OC2M_INACTIVE (0x02U << TIM_CCMR1_OC2M_Pos) ///< Inactive +#define TIM_CCMR1_OC2M_TOGGLE (0x03U << TIM_CCMR1_OC2M_Pos) ///< Toggle +#define TIM_CCMR1_OC2M_FORCEINACTIVE (0x04U << TIM_CCMR1_OC2M_Pos) ///< Forceinactive +#define TIM_CCMR1_OC2M_FORCEACTIVE (0x05U << TIM_CCMR1_OC2M_Pos) ///< Forceactive +#define TIM_CCMR1_OC2M_PWM1 (0x06U << TIM_CCMR1_OC2M_Pos) ///< PWM1 +#define TIM_CCMR1_OC2M_PWM2 (0x07U << TIM_CCMR1_OC2M_Pos) ///< PWM2 +#define TIM_CCMR1_OC2CEN_Pos (15) +#define TIM_CCMR1_OC2CEN (0x01U << TIM_CCMR1_OC2CEN_Pos) ///< Output Compare 2 Clear Enable + +#define TIM_CCMR1_IC1PSC_Pos (2) +#define TIM_CCMR1_IC1PSC (0x03U << TIM_CCMR1_IC1PSC_Pos) ///< IC1PSC[1:0] bits (Input Capture 1 Prescaler) +#define TIM_CCMR1_IC1PSC_DIV1 (0x00U << TIM_CCMR1_IC1PSC_Pos) ///< No Prescaler +#define TIM_CCMR1_IC1PSC_DIV2 (0x01U << TIM_CCMR1_IC1PSC_Pos) ///< Capture is done once every 2 events +#define TIM_CCMR1_IC1PSC_DIV4 (0x02U << TIM_CCMR1_IC1PSC_Pos) ///< Capture is done once every 4 events +#define TIM_CCMR1_IC1PSC_DIV8 (0x03U << TIM_CCMR1_IC1PSC_Pos) ///< Capture is done once every 8 events +#define TIM_CCMR1_IC1F_Pos (4) +#define TIM_CCMR1_IC1F (0x0FU << TIM_CCMR1_IC1F_Pos) ///< IC1F[3:0] bits (Input Capture 1 Filter) +#define TIM_CCMR1_IC1F_0 (0x01U << TIM_CCMR1_IC1F_Pos) ///< Bit 0 +#define TIM_CCMR1_IC1F_1 (0x02U << TIM_CCMR1_IC1F_Pos) ///< Bit 1 +#define TIM_CCMR1_IC1F_2 (0x04U << TIM_CCMR1_IC1F_Pos) ///< Bit 2 +#define TIM_CCMR1_IC1F_3 (0x08U << TIM_CCMR1_IC1F_Pos) ///< Bit 3 + +#define TIM_CCMR1_IC2PSC_Pos (10) +#define TIM_CCMR1_IC2PSC (0x03U << TIM_CCMR1_IC2PSC_Pos) ///< IC2PSC[1:0] bits (Input Capture 2 Prescaler) +#define TIM_CCMR1_IC2PSC_DIV1 (0x00U << TIM_CCMR1_IC2PSC_Pos) ///< No Prescaler +#define TIM_CCMR1_IC2PSC_DIV2 (0x01U << TIM_CCMR1_IC2PSC_Pos) ///< Capture is done once every 2 events +#define TIM_CCMR1_IC2PSC_DIV4 (0x02U << TIM_CCMR1_IC2PSC_Pos) ///< Capture is done once every 4 events +#define TIM_CCMR1_IC2PSC_DIV8 (0x03U << TIM_CCMR1_IC2PSC_Pos) ///< Capture is done once every 8 events +#define TIM_CCMR1_IC2F_Pos (12) +#define TIM_CCMR1_IC2F (0x0FU << TIM_CCMR1_IC2F_Pos) ///< IC2F[3:0] bits (Input Capture 2 Filter) +#define TIM_CCMR1_IC2F_0 (0x01U << TIM_CCMR1_IC2F_Pos) ///< Bit 0 +#define TIM_CCMR1_IC2F_1 (0x02U << TIM_CCMR1_IC2F_Pos) ///< Bit 1 +#define TIM_CCMR1_IC2F_2 (0x04U << TIM_CCMR1_IC2F_Pos) ///< Bit 2 +#define TIM_CCMR1_IC2F_3 (0x08U << TIM_CCMR1_IC2F_Pos) ///< Bit 3 + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_CCMR2 Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define TIM_CCMR2_CC3S_Pos (0) +#define TIM_CCMR2_CC3S (0x03U << TIM_CCMR2_CC3S_Pos) ///< CC3S[1:0] bits (Capture/Compare 3 Selection) +#define TIM_CCMR2_CC3S_OC (0x00U << TIM_CCMR2_CC3S_Pos) ///< Channel is configured as output +#define TIM_CCMR2_CC3S_DIRECTTI (0x01U << TIM_CCMR2_CC3S_Pos) ///< Channel is configured as input, IC3 is mapped on TI3 +#define TIM_CCMR2_CC3S_INDIRECTTI (0x02U << TIM_CCMR2_CC3S_Pos) ///< Channel is configured as input, IC3 is mapped on TI4 +#define TIM_CCMR2_CC3S_TRC (0x03U << TIM_CCMR2_CC3S_Pos) ///< Channel is configured as input, IC3 is mapped on TRC +#define TIM_CCMR2_OC3FEN_Pos (2) +#define TIM_CCMR2_OC3FEN (0x01U << TIM_CCMR2_OC3FEN_Pos) ///< Output Compare 3 Fast enable +#define TIM_CCMR2_IC3PSC_Pos (2) +#define TIM_CCMR2_IC3PSC (0x03U << TIM_CCMR2_IC3PSC_Pos) ///< IC3PSC[1:0] bits (Input Capture 3 Prescaler) +#define TIM_CCMR2_IC3PSC_DIV1 (0x00U << TIM_CCMR2_IC3PSC_Pos) ///< No Prescaler +#define TIM_CCMR2_IC3PSC_DIV2 (0x01U << TIM_CCMR2_IC3PSC_Pos) ///< Capture is done once every 2 events +#define TIM_CCMR2_IC3PSC_DIV4 (0x02U << TIM_CCMR2_IC3PSC_Pos) ///< Capture is done once every 4 events +#define TIM_CCMR2_IC3PSC_DIV8 (0x03U << TIM_CCMR2_IC3PSC_Pos) ///< Capture is done once every 8 events +#define TIM_CCMR2_OC3PEN_Pos (3) +#define TIM_CCMR2_OC3PEN (0x01U << TIM_CCMR2_OC3PEN_Pos) ///< Output Compare 3 Preload enable +#define TIM_CCMR2_OC3M_Pos (4) +#define TIM_CCMR2_OC3M (0x07U << TIM_CCMR2_OC3M_Pos) ///< OC3M[2:0] bits (Output Compare 3 Mode) +#define TIM_CCMR2_OC3M_TIMING (0x00U << TIM_CCMR2_OC3M_Pos) ///< Timing +#define TIM_CCMR2_OC3M_ACTIVE (0x01U << TIM_CCMR2_OC3M_Pos) ///< Active +#define TIM_CCMR2_OC3M_INACTIVE (0x02U << TIM_CCMR2_OC3M_Pos) ///< Inactive +#define TIM_CCMR2_OC3M_TOGGLE (0x03U << TIM_CCMR2_OC3M_Pos) ///< Toggle +#define TIM_CCMR2_OC3M_FORCEINACTIVE (0x04U << TIM_CCMR2_OC3M_Pos) ///< Forceinactive +#define TIM_CCMR2_OC3M_FORCEACTIVE (0x05U << TIM_CCMR2_OC3M_Pos) ///< Forceactive +#define TIM_CCMR2_OC3M_PWM1 (0x06U << TIM_CCMR2_OC3M_Pos) ///< PWM1 +#define TIM_CCMR2_OC3M_PWM2 (0x07U << TIM_CCMR2_OC3M_Pos) ///< PWM2 +#define TIM_CCMR2_IC3F_Pos (4) +#define TIM_CCMR2_IC3F (0x0FU << TIM_CCMR2_IC3F_Pos) ///< IC3F[3:0] bits (Input Capture 3 Filter) +#define TIM_CCMR2_IC3F_0 (0x01U << TIM_CCMR2_IC3F_Pos) ///< Bit 0 +#define TIM_CCMR2_IC3F_1 (0x02U << TIM_CCMR2_IC3F_Pos) ///< Bit 1 +#define TIM_CCMR2_IC3F_2 (0x04U << TIM_CCMR2_IC3F_Pos) ///< Bit 2 +#define TIM_CCMR2_IC3F_3 (0x08U << TIM_CCMR2_IC3F_Pos) ///< Bit 3 +#define TIM_CCMR2_OC3CEN_Pos (7) +#define TIM_CCMR2_OC3CEN (0x01U << TIM_CCMR2_OC3CEN_Pos) ///< Output Compare 3 Clear Enable +#define TIM_CCMR2_CC4S_Pos (8) +#define TIM_CCMR2_CC4S (0x03U << TIM_CCMR2_CC4S_Pos) ///< CC4S[1:0] bits (Capture/Compare 4 Selection) +#define TIM_CCMR2_CC4S_OC (0x00U << TIM_CCMR2_CC4S_Pos) ///< Channel is configured as output +#define TIM_CCMR2_CC4S_DIRECTTI (0x01U << TIM_CCMR2_CC4S_Pos) ///< Channel is configured as input, IC4 is mapped on TI4 +#define TIM_CCMR2_CC4S_INDIRECTTI (0x02U << TIM_CCMR2_CC4S_Pos) ///< Channel is configured as input, IC4 is mapped on TI3 +#define TIM_CCMR2_CC4S_TRC (0x03U << TIM_CCMR2_CC4S_Pos) ///< Channel is configured as input, IC4 is mapped on TRC +#define TIM_CCMR2_OC4FEN_Pos (10) +#define TIM_CCMR2_OC4FEN (0x01U << TIM_CCMR2_OC4FEN_Pos) ///< Output Compare 4 Fast enable +#define TIM_CCMR2_OC4PEN_Pos (11) +#define TIM_CCMR2_OC4PEN (0x01U << TIM_CCMR2_OC4PEN_Pos) ///< Output Compare 4 Preload enable +#define TIM_CCMR2_OC4M_Pos (12) +#define TIM_CCMR2_OC4M (0x07U << TIM_CCMR2_OC4M_Pos) ///< OC4M[2:0] bits (Output Compare 4 Mode) +#define TIM_CCMR2_OC4M_TIMING (0x00U << TIM_CCMR2_OC4M_Pos) ///< Timing +#define TIM_CCMR2_OC4M_ACTIVE (0x01U << TIM_CCMR2_OC4M_Pos) ///< Active +#define TIM_CCMR2_OC4M_INACTIVE (0x02U << TIM_CCMR2_OC4M_Pos) ///< Inactive +#define TIM_CCMR2_OC4M_TOGGLE (0x03U << TIM_CCMR2_OC4M_Pos) ///< Toggle +#define TIM_CCMR2_OC4M_FORCEINACTIVE (0x04U << TIM_CCMR2_OC4M_Pos) ///< Forceinactive +#define TIM_CCMR2_OC4M_FORCEACTIVE (0x05U << TIM_CCMR2_OC4M_Pos) ///< Forceactive +#define TIM_CCMR2_OC4M_PWM1 (0x06U << TIM_CCMR2_OC4M_Pos) ///< PWM1 +#define TIM_CCMR2_OC4M_PWM2 (0x07U << TIM_CCMR2_OC4M_Pos) ///< PWM2 +#define TIM_CCMR2_OC4CEN_Pos (15) +#define TIM_CCMR2_OC4CEN (0x01U << TIM_CCMR2_OC4CEN_Pos) ///< Output Compare 4 Clear Enable +#define TIM_CCMR2_IC4PSC_Pos (10) +#define TIM_CCMR2_IC4PSC (0x03U << TIM_CCMR2_IC4PSC_Pos) ///< IC4PSC[1:0] bits (Input Capture 4 Prescaler) +#define TIM_CCMR2_IC4PSC_DIV1 (0x00U << TIM_CCMR2_IC4PSC_Pos) ///< No Prescaler +#define TIM_CCMR2_IC4PSC_DIV2 (0x01U << TIM_CCMR2_IC4PSC_Pos) ///< Capture is done once every 2 events +#define TIM_CCMR2_IC4PSC_DIV4 (0x02U << TIM_CCMR2_IC4PSC_Pos) ///< Capture is done once every 4 events +#define TIM_CCMR2_IC4PSC_DIV8 (0x03U << TIM_CCMR2_IC4PSC_Pos) ///< Capture is done once every 8 events +#define TIM_CCMR2_IC4F_Pos (12) +#define TIM_CCMR2_IC4F (0x0FU << TIM_CCMR2_IC4F_Pos) ///< IC4F[3:0] bits (Input Capture 4 Filter) +#define TIM_CCMR2_IC4F_0 (0x01U << TIM_CCMR2_IC4F_Pos) ///< Bit 0 +#define TIM_CCMR2_IC4F_1 (0x02U << TIM_CCMR2_IC4F_Pos) ///< Bit 1 +#define TIM_CCMR2_IC4F_2 (0x04U << TIM_CCMR2_IC4F_Pos) ///< Bit 2 +#define TIM_CCMR2_IC4F_3 (0x08U << TIM_CCMR2_IC4F_Pos) ///< Bit 3 + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_CCER Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define TIM_CCER_CC1EN_Pos (0) +#define TIM_CCER_CC1EN (0x01U << TIM_CCER_CC1EN_Pos) ///< Capture/Compare 1 output enable +#define TIM_CCER_CC1P_Pos (1) +#define TIM_CCER_CC1P (0x01U << TIM_CCER_CC1P_Pos) ///< Capture/Compare 1 output Polarity +#define TIM_CCER_CC1NEN_Pos (2) +#define TIM_CCER_CC1NEN (0x01U << TIM_CCER_CC1NEN_Pos) ///< Capture/Compare 1 Complementary output enable +#define TIM_CCER_CC1NP_Pos (3) +#define TIM_CCER_CC1NP (0x01U << TIM_CCER_CC1NP_Pos) ///< Capture/Compare 1 Complementary output Polarity +#define TIM_CCER_CC2EN_Pos (4) +#define TIM_CCER_CC2EN (0x01U << TIM_CCER_CC2EN_Pos) ///< Capture/Compare 2 output enable +#define TIM_CCER_CC2P_Pos (5) +#define TIM_CCER_CC2P (0x01U << TIM_CCER_CC2P_Pos) ///< Capture/Compare 2 output Polarity +#define TIM_CCER_CC2NEN_Pos (6) +#define TIM_CCER_CC2NEN (0x01U << TIM_CCER_CC2NEN_Pos) ///< Capture/Compare 2 Complementary output enable +#define TIM_CCER_CC2NP_Pos (7) +#define TIM_CCER_CC2NP (0x01U << TIM_CCER_CC2NP_Pos) ///< Capture/Compare 2 Complementary output Polarity +#define TIM_CCER_CC3EN_Pos (8) +#define TIM_CCER_CC3EN (0x01U << TIM_CCER_CC3EN_Pos) ///< Capture/Compare 3 output enable +#define TIM_CCER_CC3P_Pos (9) +#define TIM_CCER_CC3P (0x01U << TIM_CCER_CC3P_Pos) ///< Capture/Compare 3 output Polarity +#define TIM_CCER_CC3NEN_Pos (10) +#define TIM_CCER_CC3NEN (0x01U << TIM_CCER_CC3NEN_Pos) ///< Capture/Compare 3 Complementary output enable +#define TIM_CCER_CC3NP_Pos (11) +#define TIM_CCER_CC3NP (0x01U << TIM_CCER_CC3NP_Pos) ///< Capture/Compare 3 Complementary output Polarity +#define TIM_CCER_CC4EN_Pos (12) +#define TIM_CCER_CC4EN (0x01U << TIM_CCER_CC4EN_Pos) ///< Capture/Compare 4 output enable +#define TIM_CCER_CC4P_Pos (13) +#define TIM_CCER_CC4P (0x01U << TIM_CCER_CC4P_Pos) ///< Capture/Compare 4 output Polarity +#define TIM_CCER_CC4NP_Pos (15) +#define TIM_CCER_CC4NP (0x01U << TIM_CCER_CC4NP_Pos) ///< Capture/Compare 4 complementary output polarity + +#define TIM_CCER_CC5EN_Pos (16) +#define TIM_CCER_CC5EN (0x01U << TIM_CCER_CC5EN_Pos) ///< Capture/Compare 5 output enable +#define TIM_CCER_CC5P_Pos (17) +#define TIM_CCER_CC5P (0x01U << TIM_CCER_CC5P_Pos) ///< Capture/Compare 5 output Polarity + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_CNT Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define TIM_CNT_CNT (0xFFFFU) ///< Counter Value + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_PSC Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define TIM_PSC_PSC (0xFFFFU) ///< Prescaler Value + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_ARR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define TIM_ARR_ARR (0xFFFFU) ///< actual auto-reload Value + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_RCR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define TIM_RCR_REP (0xFFU) ///< Repetition Counter Value + +#define TIM_RCR_REP_CNT_Pos (8) +#define TIM_RCR_REP_CNT (0xFFU << TIM_RCR_REP_CNT_Pos) ///< Repetition counter value of real-time writing + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_CCR1 Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define TIM_CCR1_CCR1 (0xFFFFU) ///< Capture/Compare 1 Value + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_CCR2 Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define TIM_CCR2_CCR2 (0xFFFFU) ///< Capture/Compare 2 Value + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_CCR3 Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define TIM_CCR3_CCR3 (0xFFFFU) ///< Capture/Compare 3 Value + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_CCR4 Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define TIM_CCR4_CCR4 (0xFFFFU) ///< Capture/Compare 4 Value + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_BDTR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define TIM_BDTR_DTG_Pos (0) +#define TIM_BDTR_DTG (0xFFU << TIM_BDTR_DTG_Pos) ///< DTG[0:7] bits (Dead-Time Generator set-up) +#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) ///< Bit 0 +#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) ///< Bit 1 +#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) ///< Bit 2 +#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) ///< Bit 3 +#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) ///< Bit 4 +#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) ///< Bit 5 +#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) ///< Bit 6 +#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) ///< Bit 7 +#define TIM_BDTR_LOCK_Pos (8) +#define TIM_BDTR_LOCK (0x03U << TIM_BDTR_LOCK_Pos) ///< LOCK[1:0] bits (Lock Configuration) +#define TIM_BDTR_LOCK_OFF (0x00U << TIM_BDTR_LOCK_Pos) ///< Lock Off +#define TIM_BDTR_LOCK_1 (0x01U << TIM_BDTR_LOCK_Pos) ///< Lock Level 1 +#define TIM_BDTR_LOCK_2 (0x02U << TIM_BDTR_LOCK_Pos) ///< Lock Level 2 +#define TIM_BDTR_LOCK_3 (0x03U << TIM_BDTR_LOCK_Pos) ///< Lock Level 3 +#define TIM_BDTR_OSSI_Pos (10) +#define TIM_BDTR_OSSI (0x01U << TIM_BDTR_OSSI_Pos) ///< Off-State Selection for Idle mode +#define TIM_BDTR_OSSR_Pos (11) +#define TIM_BDTR_OSSR (0x01U << TIM_BDTR_OSSR_Pos) ///< Off-State Selection for Run mode +#define TIM_BDTR_BKEN_Pos (12) +#define TIM_BDTR_BKEN (0x01U << TIM_BDTR_BKEN_Pos) ///< Break enable +#define TIM_BDTR_BKP_Pos (13) +#define TIM_BDTR_BKP (0x01U << TIM_BDTR_BKP_Pos) ///< Break Polarity +#define TIM_BDTR_AOEN_Pos (14) +#define TIM_BDTR_AOEN (0x01U << TIM_BDTR_AOEN_Pos) ///< Automatic Output enable +#define TIM_BDTR_MOEN_Pos (15) +#define TIM_BDTR_MOEN (0x01U << TIM_BDTR_MOEN_Pos) ///< Main Output enable + +#define TIM_BDTR_DOEN_Pos (16) +#define TIM_BDTR_DOEN (0x01U << TIM_BDTR_DOEN_Pos) ///< Direct Output enable +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_DCR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define TIM_DCR_DBA_Pos (0) +#define TIM_DCR_DBA (0x1FU << TIM_DCR_DBA_Pos) ///< DBA[4:0] bits (DMA Base Address) +#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) ///< Bit 0 +#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) ///< Bit 1 +#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) ///< Bit 2 +#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) ///< Bit 3 +#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) ///< Bit 4 +#define TIM_DCR_DBL_Pos (8) +#define TIM_DCR_DBL (0x1FU << TIM_DCR_DBL_Pos) ///< DBL[4:0] bits (DMA Burst Length) +#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) ///< Bit 0 +#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) ///< Bit 1 +#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) ///< Bit 2 +#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) ///< Bit 3 +#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) ///< Bit 4 + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_DMAR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define TIM_DMAR_DMAB (0xFFFFU) ///< DMA register for burst accesses + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_CCMR3 Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define TIM_CCMR3_OC5FEN_Pos (2) +#define TIM_CCMR3_OC5FEN (0x01U << TIM_CCMR3_OC5FEN_Pos) ///< Output Compare 5 Fast enable +#define TIM_CCMR3_OC5PEN_Pos (3) +#define TIM_CCMR3_OC5PEN (0x01U << TIM_CCMR3_OC5PEN_Pos) ///< Output Compare 5 Preload enable +#define TIM_CCMR3_OC5M_Pos (4) +#define TIM_CCMR3_OC5M (0x07U << TIM_CCMR3_OC5M_Pos) ///< OC5M[2:0] bits (Output Compare 5 Mode) + +#define TIM_CCMR3_OC5CEN_Pos (7) +#define TIM_CCMR3_OC5CEN (0x01U << TIM_CCMR3_OC5CEN_Pos) ///< Output Compare 5 Clear Enable +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_CCR5 Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define TIM_CCR5_CCR5 (0xFFFF) ///< Capture/Compare 5 Value + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_PDER Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define TIM_PDER_CCDREPE_Pos (0) +#define TIM_PDER_CCDREPE (0x01U << TIM_PDER_CCDREPE_Pos) ///< DMA request flow enable +#define TIM_PDER_CCR1SHIFTEN_Pos (1) +#define TIM_PDER_CCR1SHIFTEN (0x01U << TIM_PDER_CCR1SHIFTEN_Pos) ///< CCR1 pwm shift enable +#define TIM_PDER_CCR2SHIFTEN_Pos (2) +#define TIM_PDER_CCR2SHIFTEN (0x01U << TIM_PDER_CCR2SHIFTEN_Pos) ///< CCR2 pwm shift enable +#define TIM_PDER_CCR3SHIFTEN_Pos (3) +#define TIM_PDER_CCR3SHIFTEN (0x01U << TIM_PDER_CCR3SHIFTEN_Pos) ///< CCR3 pwm shift enable +#define TIM_PDER_CCR4SHIFTEN_Pos (4) +#define TIM_PDER_CCR4SHIFTEN (0x01U << TIM_PDER_CCR4SHIFTEN_Pos) ///< CCR4 pwm shift enable +#define TIM_PDER_CCR5SHIFTEN_Pos (5) +#define TIM_PDER_CCR5SHIFTEN (0x01U << TIM_PDER_CCR5SHIFTEN_Pos) ///< CCR5 pwm shift enable + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_CCR1FALL Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define TIM_CCR1FALL_CCR1FALL (0xFFFFU) ///< Capture/compare value for ch1 when counting down in PWM center-aligned mode + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_CCR2FALL Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define TIM_CCR2FALL_CCR2FALL (0xFFFFU) ///< Capture/compare value for ch2 when counting down in PWM center-aligned mode + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_CCR3FALL Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define TIM_CCR3FALL_CCR3FALL (0xFFFFU) ///< Capture/compare value for ch3 when counting down in PWM center-aligned mode + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_CCR4FALL Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define TIM_CCR4FALL_CCR4FALL (0xFFFFU) ///< Capture/compare value for ch4 when counting down in PWM center-aligned mode + +//////////////////////////////////////////////////////////////////////////////// +/// @brief TIM_CCR5FALL Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define TIM_CCR5FALL_CCR5FALL (0xFFFFU) ///< Capture/compare value for ch5 when counting down in PWM center-aligned mode + + + +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +#endif +//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_uart.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_uart.h new file mode 100644 index 000000000..069ff2cf9 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_uart.h @@ -0,0 +1,362 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file reg_uart.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF +/// MM32 FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion + +#ifndef __REG_UART_H +#define __REG_UART_H + +// Files includes + +#include +#include +#include "types.h" + + + + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + + + + + + + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief UART Base Address Definition +//////////////////////////////////////////////////////////////////////////////// +#define UART1_BASE (APB2PERIPH_BASE + 0x3800) ///< Base Address: 0x40013800 +#define UART2_BASE (APB1PERIPH_BASE + 0x4400) ///< Base Address: 0x40004400 +#define UART3_BASE (APB1PERIPH_BASE + 0x4800) ///< Base Address: 0x40004800 +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) ///< Base Address: 0x40004C00 +#define UART5_BASE (APB1PERIPH_BASE + 0x5000) ///< Base Address: 0x40005000 +#define UART6_BASE (APB2PERIPH_BASE + 0x3C00) ///< Base Address: 0x40013C00 +#define UART7_BASE (APB1PERIPH_BASE + 0x7800) ///< Base Address: 0x40007800 +#define UART8_BASE (APB1PERIPH_BASE + 0x7C00) ///< Base Address: 0x40007C00 + + + + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief UART Register Structure Definition +//////////////////////////////////////////////////////////////////////////////// +typedef struct { + __IO u32 TDR; ///< Transmit Data Register, offset: 0x00 + __IO u32 RDR; ///< Receive Data Register, offset: 0x04 + __IO u32 CSR; ///< Current Status Register, offset: 0x08 + __IO u32 ISR; ///< Interrupt Status Register, offset: 0x0C + __IO u32 IER; ///< Interrupt Enable Register, offset: 0x10 + __IO u32 ICR; ///< Interrupt Clear Register, offset: 0x14 + __IO u32 GCR; ///< Global Control Register, offset: 0x18 + __IO u32 CCR; ///< Config Control Register, offset: 0x1C + __IO u32 BRR; ///< Baud Rate Register, offset: 0x20 + __IO u32 FRA; ///< Fraction Register, offset: 0x24 + + __IO u32 RXAR; ///< Receive Address Register, offset: 0x28 + __IO u32 RXMR; ///< Receive Address Mask Register, offset: 0x2C + __IO u32 SCR; ///< Smart Card Register, offset: 0x30 + + __IO u32 IDLR; ///< Data length register offset: 0x34 + __IO u32 ABRCR; ///< automatic Baud rate control delivery offset: 0x38 + __IO u32 IRDA; ///< Infrared function control register, offset: 0x3C +} UART_TypeDef; + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief UART type pointer Definition +//////////////////////////////////////////////////////////////////////////////// +#define UART1 ((UART_TypeDef*) UART1_BASE) +#define UART2 ((UART_TypeDef*) UART2_BASE) + +#define UART3 ((UART_TypeDef*) UART3_BASE) +#define UART4 ((UART_TypeDef*) UART4_BASE) +#define UART5 ((UART_TypeDef*) UART5_BASE) +#define UART6 ((UART_TypeDef*) UART6_BASE) +#define UART7 ((UART_TypeDef*) UART7_BASE) +#define UART8 ((UART_TypeDef*) UART8_BASE) + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief UART_TDR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define UART_TDR_DATA_Pos (0) +#define UART_TDR_DATA (0xFFU << UART_TDR_DATA_Pos) ///< Transmit data register + +//////////////////////////////////////////////////////////////////////////////// +/// @brief UART_RDR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define UART_RDR_DATA_Pos (0) +#define UART_RDR_DATA (0xFFU << UART_RDR_DATA_Pos) ///< Receive data register + +//////////////////////////////////////////////////////////////////////////////// +/// @brief UART_CSR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define UART_CSR_TXC_Pos (0) +#define UART_CSR_TXC (0x01U << UART_CSR_TXC_Pos) ///< Transmit complete flag bit +#define UART_CSR_RXAVL_Pos (1) +#define UART_CSR_RXAVL (0x01U << UART_CSR_RXAVL_Pos) ///< Receive valid data flag bit +#define UART_CSR_TXFULL_Pos (2) +#define UART_CSR_TXFULL (0x01U << UART_CSR_TXFULL_Pos) ///< Transmit buffer full flag bit +#define UART_CSR_TXEPT_Pos (3) +#define UART_CSR_TXEPT (0x01U << UART_CSR_TXEPT_Pos) ///< Transmit buffer empty flag bit + +//////////////////////////////////////////////////////////////////////////////// +/// @brief UART_ISR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define UART_ISR_TX_Pos (0) +#define UART_ISR_TX (0x01U << UART_ISR_TX_Pos) ///< Transmit buffer empty interrupt flag bit +#define UART_ISR_RX_Pos (1) +#define UART_ISR_RX (0x01U << UART_ISR_RX_Pos) ///< Receive valid data interrupt flag bit + +#define UART_ISR_TXC_Pos (2) +#define UART_ISR_TXC (0x01U << UART_ISR_TXC_Pos) ///< Transmit complete interrupt flag bit + +#define UART_ISR_RXOERR_Pos (3) +#define UART_ISR_RXOERR (0x01U << UART_ISR_RXOERR_Pos) ///< Receive overflow error interrupt flag bit +#define UART_ISR_RXPERR_Pos (4) +#define UART_ISR_RXPERR (0x01U << UART_ISR_RXPERR_Pos) ///< Parity error interrupt flag bit +#define UART_ISR_RXFERR_Pos (5) +#define UART_ISR_RXFERR (0x01U << UART_ISR_RXFERR_Pos) ///< Frame error interrupt flag bit +#define UART_ISR_RXBRK_Pos (6) +#define UART_ISR_RXBRK (0x01U << UART_ISR_RXBRK_Pos) ///< Receive frame break interrupt flag bit + +#define UART_ISR_TXBRK_Pos (7) +#define UART_ISR_TXBRK (0x01U << UART_ISR_TXBRK_Pos) ///< Transmit Break Frame Interrupt Flag Bit +#define UART_ISR_RXB8_Pos (8) +#define UART_ISR_RXB8 (0x01U << UART_ISR_RXB8_Pos) ///< Receive Bit 8 Interrupt Flag Bit + +#define UART_ISR_RXIDLE_Pos (9) +#define UART_ISR_RXIDLE (0x01U << UART_ISR_RXIDLE_Pos) ///< Receive Bit 8 Interrupt clear Bit +#define UART_ISR_ABREND_INTF_Pos (10) +#define UART_ISR_ABREND_INTF (0x01U << UART_ISR_ABREND_INTF_Pos) ///< Auto baud rate end interrupt flag bit +#define UART_ISR_ABRERR_INTF_Pos (11) +#define UART_ISR_ABRERR_INTF (0x01U << UART_ISR_ABRERR_INTF_Pos) ///< Auto baud rate error interrupt flag bit + +//////////////////////////////////////////////////////////////////////////////// +/// @brief UART_IER Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define UART_IER_TX_Pos (0) +#define UART_IER_TX (0x01U << UART_IER_TX_Pos) ///< Transmit buffer empty interrupt enable bit +#define UART_IER_RX_Pos (1) +#define UART_IER_RX (0x01U << UART_IER_RX_Pos) ///< Receive buffer interrupt enable bit + +#define UART_IER_TXC_Pos (2) +#define UART_IER_TXC (0x01U << UART_IER_TXC_Pos) ///< Transmit complete interrupt enable bit + +#define UART_IER_RXOERR_Pos (3) +#define UART_IER_RXOERR (0x01U << UART_IER_RXOERR_Pos) ///< Receive overflow error interrupt enable bit +#define UART_IER_RXPERR_Pos (4) +#define UART_IER_RXPERR (0x01U << UART_IER_RXPERR_Pos) ///< Parity error interrupt enable bit +#define UART_IER_RXFERR_Pos (5) +#define UART_IER_RXFERR (0x01U << UART_IER_RXFERR_Pos) ///< Frame error interrupt enable bit +#define UART_IER_RXBRK_Pos (6) +#define UART_IER_RXBRK (0x01U << UART_IER_RXBRK_Pos) ///< Receive frame break interrupt enable bit + +#define UART_IER_TXBRK_Pos (7) +#define UART_IER_TXBRK (0x01U << UART_IER_TXBRK_Pos) ///< Transmit Break Frame Interrupt Enable Bit +#define UART_IER_RXB8_Pos (8) +#define UART_IER_RXB8 (0x01U << UART_IER_RXB8_Pos) ///< Receive Bit 8 Interrupt Enable Bit + +#define UART_IER_RXIDLE_Pos (9) +#define UART_IER_RXIDLE (0x01U << UART_IER_RXIDLE_Pos) ///< Receive Bit 8 Interrupt clear Bit +#define UART_IER_ABREND_IEN_Pos (10) +#define UART_IER_ABREND_IEN (0x01U << UART_IER_ABREND_IEN_Pos) ///< Auto baud rate end enable bit +#define UART_IER_ABRERR_IEN_Pos (11) +#define UART_IER_ABRERR_IEN (0x01U << UART_IER_ABRERR_IEN_Pos) ///< Auto baud rate error enable bit + +//////////////////////////////////////////////////////////////////////////////// +/// @brief UART_ICR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// + +#define UART_ICR_TX_Pos (0) +#define UART_ICR_TX (0x01U << UART_ICR_TX_Pos) ///< Transmit buffer empty interrupt clear bit +#define UART_ICR_RX_Pos (1) +#define UART_ICR_RX (0x01U << UART_ICR_RX_Pos) ///< Receive interrupt clear bit + +#define UART_ICR_TXC_Pos (2) +#define UART_ICR_TXC (0x01U << UART_ICR_TXC_Pos) ///< Transmit complete interrupt clear bit + +#define UART_ICR_RXOERR_Pos (3) +#define UART_ICR_RXOERR (0x01U << UART_ICR_RXOERR_Pos) ///< Receive overflow error interrupt clear bit +#define UART_ICR_RXPERR_Pos (4) +#define UART_ICR_RXPERR (0x01U << UART_ICR_RXPERR_Pos) ///< Parity error interrupt clear bit + +#define UART_ICR_RXFERR_Pos (5) +#define UART_ICR_RXFERR (0x01U << UART_ICR_RXFERR_Pos) ///< Frame error interrupt clear bit +#define UART_ICR_RXBRK_Pos (6) +#define UART_ICR_RXBRK (0x01U << UART_ICR_RXBRK_Pos) ///< Receive frame break interrupt clear bit + +#define UART_ICR_TXBRK_Pos (7) +#define UART_ICR_TXBRK (0x01U << UART_ICR_TXBRK_Pos) ///< Transmit Break Frame Interrupt clear Bit +#define UART_ICR_RXB8_Pos (8) +#define UART_ICR_RXB8 (0x01U << UART_ICR_RXB8_Pos) ///< Receive Bit 8 Interrupt clear Bit + +#define UART_ICR_RXIDLE_Pos (9) +#define UART_ICR_RXIDLE (0x01U << UART_ICR_RXIDLE_Pos) ///< Receive Bit 8 Interrupt clear Bit +#define UART_ICR_ABRENDCLR_Pos (10) +#define UART_ICR_ABRENDCLR (0x01U << UART_ICR_ABRENDCLR_Pos) ///< Auto baud rate end clear bit +#define UART_ICR_ABRERRCLR_Pos (11) +#define UART_ICR_ABRERRCLR (0x01U << UART_ICR_ABRERRCLR_Pos) ///< Auto baud rate error clear bit + +//////////////////////////////////////////////////////////////////////////////// +/// @brief UART_GCR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define UART_GCR_UART_Pos (0) +#define UART_GCR_UART (0x01U << UART_GCR_UART_Pos) ///< UART mode selection bit +#define UART_GCR_DMA_Pos (1) +#define UART_GCR_DMA (0x01U << UART_GCR_DMA_Pos) ///< DMA mode selection bit +#define UART_GCR_AUTOFLOW_Pos (2) +#define UART_GCR_AUTOFLOW (0x01U << UART_GCR_AUTOFLOW_Pos) ///< Automatic flow control enable bit +#define UART_GCR_RX_Pos (3) +#define UART_GCR_RX (0x01U << UART_GCR_RX_Pos) ///< Enable receive +#define UART_GCR_TX_Pos (4) +#define UART_GCR_TX (0x01U << UART_GCR_TX_Pos) ///< Enable transmit + +#define UART_GCR_SELB8_Pos (7) +#define UART_GCR_SELB8 (0x01U << UART_GCR_SELB8_Pos) ///< UART mode selection bit +#define UART_GCR_SWAP_Pos (8) +#define UART_GCR_SWAP (0x01U << UART_GCR_SWAP_Pos) ///< DMA mode selection bit +#define UART_GCR_RXTOG_Pos (9) +#define UART_GCR_RXTOG (0x01U << UART_GCR_RXTOG_Pos) ///< Automatic flow control enable bit +#define UART_GCR_TXTOG_Pos (10) +#define UART_GCR_TXTOG (0x01U << UART_GCR_TXTOG_Pos) ///< Enable receive + +//////////////////////////////////////////////////////////////////////////////// +/// @brief UART_CCR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define UART_CCR_PEN_Pos (0) +#define UART_CCR_PEN (0x01U << UART_CCR_PEN_Pos) ///< Parity enable bit +#define UART_CCR_PSEL_Pos (1) +#define UART_CCR_PSEL (0x01U << UART_CCR_PSEL_Pos) ///< Parity selection bit + +#define UART_CCR_SPB_Pos (2) +#define UART_CCR_SPB (0x01U << UART_CCR_SPB_Pos) ///< Stop bit selection + + + +#define UART_CCR_SPB0_Pos UART_CCR_SPB_Pos +#define UART_CCR_SPB0 UART_CCR_SPB ///< Stop bit 0 selection + +#define UART_CCR_BRK_Pos (3) +#define UART_CCR_BRK (0x01U << UART_CCR_BRK_Pos) ///< UART transmit frame break +#define UART_CCR_CHAR_Pos (4) +#define UART_CCR_CHAR (0x03U << UART_CCR_CHAR_Pos) ///< UART width bit +#define UART_CCR_CHAR_5b (0x00U << UART_CCR_CHAR_Pos) ///< UART Word Length 5b +#define UART_CCR_CHAR_6b (0x01U << UART_CCR_CHAR_Pos) ///< UART Word Length 6b +#define UART_CCR_CHAR_7b (0x02U << UART_CCR_CHAR_Pos) ///< UART Word Length 7b +#define UART_CCR_CHAR_8b (0x03U << UART_CCR_CHAR_Pos) ///< UART Word Length 8b + +#define UART_CCR_SPB1_Pos (6) +#define UART_CCR_SPB1 (0x01U << UART_CCR_SPB1_Pos) ///< Stop bit 1 selection +#define UART_CCR_B8RXD_Pos (7) +#define UART_CCR_B8RXD (0x01U << UART_CCR_B8RXD_Pos) ///< Synchronous frame receive +#define UART_CCR_B8TXD_Pos (8) +#define UART_CCR_B8TXD (0x01U << UART_CCR_B8TXD_Pos) ///< Synchronous frame transmit +#define UART_CCR_B8POL_Pos (9) +#define UART_CCR_B8POL (0x01U << UART_CCR_B8POL_Pos) ///< Synchronous frame polarity control bit +#define UART_CCR_B8TOG_Pos (10) +#define UART_CCR_B8TOG (0x01U << UART_CCR_B8TOG_Pos) ///< Synchronous frame auto toggle bit +#define UART_CCR_B8EN_Pos (11) +#define UART_CCR_B8EN (0x01U << UART_CCR_B8EN_Pos) ///< Synchronous frame enable bit +#define UART_CCR_RWU_Pos (12) +#define UART_CCR_RWU (0x01U << UART_CCR_RWU_Pos) ///< Receive wake up method +#define UART_CCR_WAKE_Pos (13) +#define UART_CCR_WAKE (0x01U << UART_CCR_WAKE_Pos) ///< Wake up method + +#define UART_CCR_LIN_Pos (14) +#define UART_CCR_LIN (0x01U << UART_CCR_LIN_Pos) ///< Wake up method + +//////////////////////////////////////////////////////////////////////////////// +/// @brief UART_BRR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define UART_BRR_MANTISSA_Pos (0) +#define UART_BRR_MANTISSA (0xFFFFU << UART_BRR_MANTISSA_Pos) ///< UART DIV MANTISSA + +//////////////////////////////////////////////////////////////////////////////// +/// @brief UART_FRA Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define UART_BRR_FRACTION_Pos (0) +#define UART_BRR_FRACTION (0x0FU << UART_BRR_FRACTION_Pos) ///< UART DIV FRACTION + +//////////////////////////////////////////////////////////////////////////////// +/// @brief UART_RXAR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define UART_RXAR_ADDR_Pos (0) +#define UART_RXAR_ADDR (0xFFU << UART_RXAR_ADDR_Pos) ///< Synchronous frame match address + +//////////////////////////////////////////////////////////////////////////////// +/// @brief UART_RXMR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define UART_RXMR_MASK_Pos (0) +#define UART_RXMR_MASK (0xFFU << UART_RXMR_MASK_Pos) ///< Synchronous frame match address mask + +//////////////////////////////////////////////////////////////////////////////// +/// @brief UART_SCR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define UART_SCR_SCEN_Pos (0) +#define UART_SCR_SCEN (0x01U << UART_SCR_SCEN_Pos) ///< ISO7816 enable bit +#define UART_SCR_SCARB_Pos (1) +#define UART_SCR_SCARB (0x01U << UART_SCR_SCARB_Pos) ///< ISO7816 check auto answer bit +#define UART_SCR_NACK_Pos (2) +#define UART_SCR_NACK (0x01U << UART_SCR_NACK_Pos) ///< Master receive frame answer bit +#define UART_SCR_SCFCNT_Pos (4) +#define UART_SCR_SCFCNT (0xFFU << UART_SCR_SCFCNT_Pos) ///< ISO7816 protection counter bit +#define UART_SCR_HDSEL_Pos (12) +#define UART_SCR_HDSEL (0x01U << UART_SCR_HDSEL_Pos) ///< Single-line half-duplex mode selection bit +//////////////////////////////////////////////////////////////////////////////// +/// @brief UART_ABRCR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define UART_ABRCR_ABREN_Pos (0) +#define UART_ABRCR_ABREN (0x01U<
© COPYRIGHT MINDMOTION
+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion + +#ifndef __REG_USB_OTG_FS_H +#define __REG_USB_OTG_FS_H + +// Files includes + +#include +#include +#include "types.h" + + + + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + + + + + + + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief USB Base Address Definition +//////////////////////////////////////////////////////////////////////////////// + +#define USB_OTG_FS_BASE (AHB2PERIPH_BASE + 0x0000) ///< Base Address: 0x50000000 + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief USB Register Structure Definition +//////////////////////////////////////////////////////////////////////////////// + +typedef struct { + __IO u32 PER_ID; ///< Peripheral ID register offset: 0x00 + __IO u32 ID_COMP; ///< Peripheral ID complement register offset: 0x04 + __IO u32 REV; ///< Peripheral revision register offset: 0x08 + __IO u32 ADD_INFO; ///< Peripheral additional info register offset: 0x0C + __IO u32 OTG_ISTAT; ///< OTG Interrupt Status Register offset: 0x10 + __IO u32 OTG_ICTRL; ///< OTG Interrupt Control Register offset: 0x14 + __IO u32 OTG_STAT; ///< OTG Status Register offset: 0x18 + __IO u32 OTG_CTRL; ///< OTG Control register offset: 0x1C + __IO u32 RESERVED0[24]; ///< Reserved offset: 0x20 + __IO u32 INT_STAT; ///< Interrupt status register offset: 0x80 + __IO u32 INT_ENB; ///< Interrupt enable register offset: 0x84 + __IO u32 ERR_STAT; ///< Error interrupt status register offset: 0x88 + __IO u32 ERR_ENB; ///< Error interrupt enable register offset: 0x8C + __IO u32 STAT; ///< Status register offset: 0x90 + __IO u32 CTL; ///< Control register offset: 0x94 + __IO u32 ADDR; ///< Address register offset: 0x98 + __IO u32 BDT_PAGE_01; ///< BDT page register 1 offset: 0x9C + __IO u32 FRM_NUML; ///< Frame number register offset: 0xA0 + __IO u32 FRM_NUMH; ///< Frame number register offset: 0xA4 + __IO u32 TOKEN; ///< Token register offset: 0xA8 + __IO u32 SOF_THLD; ///< SOF threshold register offset: 0xAC + __IO u32 BDT_PAGE_02; ///< BDT page register 2 offset: 0xB0 + __IO u32 BDT_PAGE_03; ///< BDT page register 3 offset: 0xB4 + __IO u32 RESERVED1; ///< Reserved offset: 0xB8 + __IO u32 RESERVED2; ///< Reserved offset: 0xBC + __IO u32 EP_CTL[16]; ///< Endpoint control register offset: 0xC0 +} USB_OTG_FS_TypeDef; +//////////////////////////////////////////////////////////////////////////////// +/// @brief USBD type pointer Definition +//////////////////////////////////////////////////////////////////////////////// +#define USB_OTG_FS ((USB_OTG_FS_TypeDef*) USB_OTG_FS_BASE ) + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief OTG_FS_PER_ID Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define OTG_FS_PER_ID_ID_Pos (0) +#define OTG_FS_PER_ID_ID (0x3FU << OTG_FS_PER_ID_ID_Pos) + +//////////////////////////////////////////////////////////////////////////////// +/// @brief OTG_FS_ID_COMP Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define OTG_FS_ID_COMP_NID_Pos (0) +#define OTG_FS_ID_COMP_NID (0x3FU << OTG_FS_ID_COMP_NID_Pos) + +//////////////////////////////////////////////////////////////////////////////// +/// @brief OTG_FS_REV Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define OTG_FS_REV_REV_Pos (0) +#define OTG_FS_REV_REV (0xFFU << OTG_FS_REV_REV_Pos) + +//////////////////////////////////////////////////////////////////////////////// +/// @brief OTG_FS_ADD_INFO Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define OTG_FS_ADD_INFO_HOST_Pos (0) +#define OTG_FS_ADD_INFO_HOST (0x01U << OTG_FS_ADD_INFO_HOST_Pos) +#define OTG_FS_ADD_INFO_IRQ_NUM_Pos (3) +#define OTG_FS_ADD_INFO_IRQ_NUM (0x1FU << OTG_FS_ADD_INFO_IRQ_NUM_Pos) + +//////////////////////////////////////////////////////////////////////////////// +/// @brief OTG_FS_OTG_ISTAT Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define OTG_FS_OTG_ISTAT_A_VBUS_VLD_CHG_Pos (0) +#define OTG_FS_OTG_ISTAT_A_VBUS_VLD_CHG (0x01U << OTG_FS_OTG_ISTAT_A_VBUS_VLD_CHG_Pos) +#define OTG_FS_OTG_ISTAT_B_SESS_END_CHG_Pos (2) +#define OTG_FS_OTG_ISTAT_B_SESS_END_CHG (0x01U << OTG_FS_OTG_ISTAT_B_SESS_END_CHG_Pos) +#define OTG_FS_OTG_ISTAT_SESS_VLD_CHG_Pos (3) +#define OTG_FS_OTG_ISTAT_SESS_VLD_CHG (0x01U << OTG_FS_OTG_ISTAT_SESS_VLD_CHG_Pos) +#define OTG_FS_OTG_ISTAT_LINE_STATE_CHG_Pos (5) +#define OTG_FS_OTG_ISTAT_LINE_STATE_CHG (0x01U << OTG_FS_OTG_ISTAT_LINE_STATE_CHG_Pos) +#define OTG_FS_OTG_ISTAT_1_MSEC_Pos (6) +#define OTG_FS_OTG_ISTAT_1_MSEC (0x01U << OTG_FS_OTG_ISTAT_1_MSEC_Pos) +#define OTG_FS_OTG_ISTAT_ID_CHG_Pos (7) +#define OTG_FS_OTG_ISTAT_ID_CHG (0x01U << OTG_FS_OTG_ISTAT_ID_CHG_Pos) + +//////////////////////////////////////////////////////////////////////////////// +/// @brief OTG_FS_OTG_ICTRL Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define OTG_FS_OTG_ICTRL_A_VBUS_VLD_EN_Pos (0) +#define OTG_FS_OTG_ICTRL_A_VBUS_VLD_EN (0x01U << OTG_FS_OTG_ICTRL_A_VBUS_VLD_EN_Pos) +#define OTG_FS_OTG_ICTRL_B_SESS_END_EN_Pos (2) +#define OTG_FS_OTG_ICTRL_B_SESS_END_EN (0x01U << OTG_FS_OTG_ICTRL_B_SESS_END_EN_Pos) +#define OTG_FS_OTG_ICTRL_SESS_VLD_EN_Pos (3) +#define OTG_FS_OTG_ICTRL_SESS_VLD_EN (0x01U << OTG_FS_OTG_ICTRL_SESS_VLD_EN_Pos) +#define OTG_FS_OTG_ICTRL_LINE_STATE_EN_Pos (5) +#define OTG_FS_OTG_ICTRL_LINE_STATE_EN (0x01U << OTG_FS_OTG_ICTRL_LINE_STATE_EN_Pos) +#define OTG_FS_OTG_ICTRL_1_MSEC_EN_Pos (6) +#define OTG_FS_OTG_ICTRL_1_MSEC_EN (0x01U << OTG_FS_OTG_ICTRL_1_MSEC_EN_Pos) +#define OTG_FS_OTG_ICTRL_ID_EN_Pos (7) +#define OTG_FS_OTG_ICTRL_ID_EN (0x01U << OTG_FS_OTG_ICTRL_ID_EN_Pos) + +//////////////////////////////////////////////////////////////////////////////// +/// @brief OTG_FS_OTG_STAT Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define OTG_FS_OTG_STAT_A_VBUS_VLD_Pos (0) +#define OTG_FS_OTG_STAT_A_VBUS_VLD (0x01U << OTG_FS_OTG_STAT_A_VBUS_VLD_Pos) +#define OTG_FS_OTG_STAT_B_SESS_END_Pos (2) +#define OTG_FS_OTG_STAT_B_SESS_END (0x01U << OTG_FS_OTG_STAT_B_SESS_END_Pos) +#define OTG_FS_OTG_STAT_SESS_VLD_Pos (3) +#define OTG_FS_OTG_STAT_SESS_VLD (0x01U << OTG_FS_OTG_STAT_SESS_VLD_Pos) +#define OTG_FS_OTG_STAT_LINE_STATE_STABLE_Pos (5) +#define OTG_FS_OTG_STAT_LINE_STATE_STABLE (0x01U << OTG_FS_OTG_STAT_LINE_STATE_STABLE_Pos) +#define OTG_FS_OTG_STAT_1_MSEC_Pos (6) +#define OTG_FS_OTG_STAT_1_MSEC (0x01U << OTG_FS_OTG_STAT_1_MSEC_Pos) +#define OTG_FS_OTG_STAT_ID_Pos (7) +#define OTG_FS_OTG_STAT_ID (0x01U << OTG_FS_OTG_STAT_ID_Pos) + +//////////////////////////////////////////////////////////////////////////////// +/// @brief OTG_FS_OTG_CTRL Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define OTG_FS_OTG_CTRL_VBUS_DSCHG_Pos (0) +#define OTG_FS_OTG_CTRL_VBUS_DSCHG (0x01U << OTG_FS_OTG_CTRL_VBUS_DSCHG_Pos) +#define OTG_FS_OTG_CTRL_VBUS_CHG_Pos (1) +#define OTG_FS_OTG_CTRL_VBUS_CHG (0x01U << OTG_FS_OTG_CTRL_VBUS_CHG_Pos) +#define OTG_FS_OTG_CTRL_OTG_EN_Pos (2) +#define OTG_FS_OTG_CTRL_OTG_EN (0x01U << OTG_FS_OTG_CTRL_OTG_EN_Pos) +#define OTG_FS_OTG_CTRL_VBUS_ON_Pos (3) +#define OTG_FS_OTG_CTRL_VBUS_ON (0x01U << OTG_FS_OTG_CTRL_VBUS_ON_Pos) +#define OTG_FS_OTG_CTRL_DM_LOW_Pos (4) +#define OTG_FS_OTG_CTRL_DM_LOW (0x01U << OTG_FS_OTG_CTRL_DM_LOW_Pos) +#define OTG_FS_OTG_CTRL_DP_LOW_Pos (5) +#define OTG_FS_OTG_CTRL_DP_LOW (0x01U << OTG_FS_OTG_CTRL_DP_LOW_Pos) +#define OTG_FS_OTG_CTRL_DM_HIGH_Pos (6) +#define OTG_FS_OTG_CTRL_DM_HIGH (0x01U << OTG_FS_OTG_CTRL_DM_HIGH_Pos) +#define OTG_FS_OTG_CTRL_DP_HIGH_Pos (7) +#define OTG_FS_OTG_CTRL_DP_HIGH (0x01U << OTG_FS_OTG_CTRL_DP_HIGH_Pos) + +//////////////////////////////////////////////////////////////////////////////// +/// @brief OTG_FS_INT_STAT Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define OTG_FS_INT_STAT_USB_RST_Pos (0) +#define OTG_FS_INT_STAT_USB_RST (0x01U << OTG_FS_INT_STAT_USB_RST_Pos) +#define OTG_FS_INT_STAT_ERROR_Pos (1) +#define OTG_FS_INT_STAT_ERROR (0x01U << OTG_FS_INT_STAT_ERROR_Pos) +#define OTG_FS_INT_STAT_SOF_TOK_Pos (2) +#define OTG_FS_INT_STAT_SOF_TOK (0x01U << OTG_FS_INT_STAT_SOF_TOK_Pos) +#define OTG_FS_INT_STAT_TOK_DNE_Pos (3) +#define OTG_FS_INT_STAT_TOK_DNE (0x01U << OTG_FS_INT_STAT_TOK_DNE_Pos) +#define OTG_FS_INT_STAT_SLEEP_Pos (4) +#define OTG_FS_INT_STAT_SLEEP (0x01U << OTG_FS_INT_STAT_SLEEP_Pos) +#define OTG_FS_INT_STAT_RESUME_Pos (5) +#define OTG_FS_INT_STAT_RESUME (0x01U << OTG_FS_INT_STAT_RESUME_Pos) +#define OTG_FS_INT_STAT_ATTACH_Pos (6) +#define OTG_FS_INT_STAT_ATTACH (0x01U << OTG_FS_INT_STAT_ATTACH_Pos) +#define OTG_FS_INT_STAT_STALL_Pos (7) +#define OTG_FS_INT_STAT_STALL (0x01U << OTG_FS_INT_STAT_STALL_Pos) + +//////////////////////////////////////////////////////////////////////////////// +/// @brief OTG_FS_INT_ENB Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define OTG_FS_INT_ENB_USB_RST_EN_Pos (0) +#define OTG_FS_INT_ENB_USB_RST_EN (0x01U << OTG_FS_INT_ENB_USB_RST_EN_Pos) +#define OTG_FS_INT_ENB_ERROR_EN_Pos (1) +#define OTG_FS_INT_ENB_ERROR_EN (0x01U << OTG_FS_INT_ENB_ERROR_EN_Pos) +#define OTG_FS_INT_ENB_SOF_TOK_EN_Pos (2) +#define OTG_FS_INT_ENB_SOF_TOK_EN (0x01U << OTG_FS_INT_ENB_SOF_TOK_EN_Pos) +#define OTG_FS_INT_ENB_TOK_DNE_EN_Pos (3) +#define OTG_FS_INT_ENB_TOK_DNE_EN (0x01U << OTG_FS_INT_ENB_TOK_DNE_EN_Pos) +#define OTG_FS_INT_ENB_SLEEP_EN_Pos (4) +#define OTG_FS_INT_ENB_SLEEP_EN (0x01U << OTG_FS_INT_ENB_SLEEP_EN_Pos) +#define OTG_FS_INT_ENB_RESUME_EN_Pos (5) +#define OTG_FS_INT_ENB_RESUME_EN (0x01U << OTG_FS_INT_ENB_RESUME_EN_Pos) +#define OTG_FS_INT_ENB_ATTACH_EN_Pos (6) +#define OTG_FS_INT_ENB_ATTACH_EN (0x01U << OTG_FS_INT_ENB_ATTACH_EN_Pos) +#define OTG_FS_INT_ENB_STALL_EN_Pos (7) +#define OTG_FS_INT_ENB_STALL_EN (0x01U << OTG_FS_INT_ENB_STALL_EN_Pos) + +//////////////////////////////////////////////////////////////////////////////// +/// @brief OTG_FS_ERR_STAT Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define OTG_FS_ERR_STAT_PID_ERR_Pos (0) +#define OTG_FS_ERR_STAT_PID_ERR (0x01U << OTG_FS_ERR_STAT_PID_ERR_Pos) +#define OTG_FS_ERR_STAT_CRC5_EOF_Pos (1) +#define OTG_FS_ERR_STAT_CRC5_EOF (0x01U << OTG_FS_ERR_STAT_CRC5_EOF_Pos) +#define OTG_FS_ERR_STAT_CRC16_Pos (2) +#define OTG_FS_ERR_STAT_CRC16 (0x01U << OTG_FS_ERR_STAT_CRC16_Pos) +#define OTG_FS_ERR_STAT_DFN8_Pos (3) +#define OTG_FS_ERR_STAT_DFN8 (0x01U << OTG_FS_ERR_STAT_DFN8_Pos) +#define OTG_FS_ERR_STAT_BTO_ERR_Pos (4) +#define OTG_FS_ERR_STAT_BTO_ERR (0x01U << OTG_FS_ERR_STAT_BTO_ERR_Pos) +#define OTG_FS_ERR_STAT_DMA_ERR_Pos (5) +#define OTG_FS_ERR_STAT_DMA_ERR (0x01U << OTG_FS_ERR_STAT_DMA_ERR_Pos) +#define OTG_FS_ERR_STAT_BTS_ERR_Pos (7) +#define OTG_FS_ERR_STAT_BTS_ERR (0x01U << OTG_FS_ERR_STAT_BTS_ERR_Pos) + +//////////////////////////////////////////////////////////////////////////////// +/// @brief OTG_FS_ERR_ENB Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define OTG_FS_ERR_ENB_PID_ERR_EN_Pos (0) +#define OTG_FS_ERR_ENB_PID_ERR_EN (0x01U << OTG_FS_ERR_ENB_PID_ERR_EN_Pos) +#define OTG_FS_ERR_ENB_CRC5_EOF_EN_Pos (1) +#define OTG_FS_ERR_ENB_CRC5_EOF_EN (0x01U << OTG_FS_ERR_ENB_CRC5_EOF_EN_Pos) +#define OTG_FS_ERR_ENB_CRC16_EN_Pos (2) +#define OTG_FS_ERR_ENB_CRC16_EN (0x01U << OTG_FS_ERR_ENB_CRC16_EN_Pos) +#define OTG_FS_ERR_ENB_DFN8_EN_Pos (3) +#define OTG_FS_ERR_ENB_DFN8_EN (0x01U << OTG_FS_ERR_ENB_DFN8_EN_Pos) +#define OTG_FS_ERR_ENB_BTO_ERR_EN_Pos (4) +#define OTG_FS_ERR_ENB_BTO_ERR_EN (0x01U << OTG_FS_ERR_ENB_BTO_ERR_EN_Pos) +#define OTG_FS_ERR_ENB_DMA_ERR_EN_Pos (5) +#define OTG_FS_ERR_ENB_DMA_ERR_EN (0x01U << OTG_FS_ERR_ENB_DMA_ERR_EN_Pos) +#define OTG_FS_ERR_ENB_BTS_ERR_EN_Pos (7) +#define OTG_FS_ERR_ENB_BTS_ERR_EN (0x01U << OTG_FS_ERR_ENB_BTS_ERR_EN_Pos) + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief OTG_FS_STAT Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define OTG_FS_STAT_ODD_Pos (2) +#define OTG_FS_STAT_ODD (0x01U << OTG_FS_STAT_ODD_Pos) +#define OTG_FS_STAT_TX_Pos (3) +#define OTG_FS_STAT_TX (0x01U << OTG_FS_STAT_TX_Pos) +#define OTG_FS_STAT_ENDP_Pos (4) +#define OTG_FS_STAT_ENDP (0x0FU << OTG_FS_STAT_ENDP_Pos) + +//////////////////////////////////////////////////////////////////////////////// +/// @brief OTG_FS_CTL Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define OTG_FS_CTL_USB_EN_SOF_EN_Pos (0) +#define OTG_FS_CTL_USB_EN_SOF_EN (0x01U << OTG_FS_CTL_USB_EN_SOF_EN_Pos) +#define OTG_FS_CTL_ODD_RST_Pos (1) +#define OTG_FS_CTL_ODD_RST (0x01U << OTG_FS_CTL_ODD_RST_Pos) +#define OTG_FS_CTL_RESUME_Pos (2) +#define OTG_FS_CTL_RESUME (0x01U << OTG_FS_CTL_RESUME_Pos) +#define OTG_FS_CTL_HOST_MODE_EN_Pos (3) +#define OTG_FS_CTL_HOST_MODE_EN (0x01U << OTG_FS_CTL_HOST_MODE_EN_Pos) +#define OTG_FS_CTL_RESET_Pos (4) +#define OTG_FS_CTL_RESET (0x01U << OTG_FS_CTL_RESET_Pos) +#define OTG_FS_CTL_TXDSUSPEND_TOKENBUSY_Pos (5) +#define OTG_FS_CTL_TXDSUSPEND_TOKENBUSY (0x01U << OTG_FS_CTL_TXDSUSPEND_TOKENBUSY_Pos) +#define OTG_FS_CTL_SE0_Pos (6) +#define OTG_FS_CTL_SE0 (0x01U << OTG_FS_CTL_SE0_Pos) +#define OTG_FS_CTL_JSTATE_Pos (7) +#define OTG_FS_CTL_JSTATE (0x01U << OTG_FS_CTL_JSTATE_Pos) + +//////////////////////////////////////////////////////////////////////////////// +/// @brief OTG_FS_ADDR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define OTG_FS_ADDR_ADDR_Pos (0) +#define OTG_FS_ADDR_ADDR (0x7FU << OTG_FS_ADDR_ADDR_Pos) +#define OTG_FS_ADDR_LS_EN_Pos (7) +#define OTG_FS_ADDR_LS_EN (0x01U << OTG_FS_ADDR_LS_EN_Pos) + +//////////////////////////////////////////////////////////////////////////////// +/// @brief OTG_FS_BDT_PAGE_01 Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define OTG_FS_BDT_PAGE_01_BDT_BA_15_9_Pos (1) +#define OTG_FS_BDT_PAGE_01_BDT_BA_15_9 (0x7FU << OTG_FS_BDT_PAGE_01_BDT_BA_15_9_Pos) + +//////////////////////////////////////////////////////////////////////////////// +/// @brief OTG_FS_FRM_NUML Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define OTG_FS_FRM_NUML_FRM_Pos (0) +#define OTG_FS_FRM_NUML_FRM (0xFFU << OTG_FS_FRM_NUML_FRM_Pos) + +//////////////////////////////////////////////////////////////////////////////// +/// @brief OTG_FS_FRM_NUMH Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define OTG_FS_FRM_NUMH_FRM_Pos (0) +#define OTG_FS_FRM_NUMH_FRM (0x07U << OTG_FS_FRM_NUMH_FRM_Pos) + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief OTG_FS_TOKEN Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define OTG_FS_TOKEN_TOKEN_ENDPT_Pos (0) +#define OTG_FS_TOKEN_TOKEN_ENDPT (0x0FU << OTG_FS_TOKEN_TOKEN_ENDPT_Pos) +#define OTG_FS_TOKEN_TOKEN_PID_Pos (4) +#define OTG_FS_TOKEN_TOKEN_PID (0x0FU << OTG_FS_TOKEN_TOKEN_PID_Pos) + +//////////////////////////////////////////////////////////////////////////////// +/// @brief OTG_FS_SOF_THLD Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define OTG_FS_SOF_THLD_CNT_Pos (0) +#define OTG_FS_SOF_THLD_CNT (0xFFU << OTG_FS_SOF_THLD_CNT_Pos) + +//////////////////////////////////////////////////////////////////////////////// +/// @brief OTG_FS_BDT_PAGE_02 Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define OTG_FS_BDT_PAGE_02_BDT_BA_23_16_Pos (0) +#define OTG_FS_BDT_PAGE_02_BDT_BA_23_16 (0xFFU << OTG_FS_BDT_PAGE_02_BDT_BA_23_16_Pos) + +//////////////////////////////////////////////////////////////////////////////// +/// @brief OTG_FS_BDT_PAGE_03 Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define OTG_FS_BDT_PAGE_03_BDT_BA_31_24_Pos (0) +#define OTG_FS_BDT_PAGE_03_BDT_BA_31_24 (0xFFU << OTG_FS_BDT_PAGE_03_BDT_BA_31_24_Pos) + +//////////////////////////////////////////////////////////////////////////////// +/// @brief OTG_FS_EP_CTL Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define OTG_FS_EP_CTL_EP_HSHK_Pos (0) +#define OTG_FS_EP_CTL_EP_HSHK (0x01U << OTG_FS_EP_CTL_EP_HSHK_Pos) +#define OTG_FS_EP_CTL_EP_STALL_Pos (1) +#define OTG_FS_EP_CTL_EP_STALL (0x01U << OTG_FS_EP_CTL_EP_STALL_Pos) +#define OTG_FS_EP_CTL_EP_TX_EN_Pos (2) +#define OTG_FS_EP_CTL_EP_TX_EN (0x01U << OTG_FS_EP_CTL_EP_TX_EN_Pos) +#define OTG_FS_EP_CTL_EP_RX_EN_Pos (3) +#define OTG_FS_EP_CTL_EP_RX_EN (0x01U << OTG_FS_EP_CTL_EP_RX_EN_Pos) +#define OTG_FS_EP_CTL_EP_CTL_DIS_Pos (4) +#define OTG_FS_EP_CTL_EP_CTL_DIS (0x01U << OTG_FS_EP_CTL_EP_CTL_DIS_Pos) +#define OTG_FS_EP_CTL_RETRY_DIS_Pos (6) +#define OTG_FS_EP_CTL_RETRY_DIS (0x01U << OTG_FS_EP_CTL_RETRY_DIS_Pos) +#define OTG_FS_EP_CTL_HOST_WO_HUB_Pos (7) +#define OTG_FS_EP_CTL_HOST_WO_HUB (0x01U << OTG_FS_EP_CTL_HOST_WO_HUB_Pos) + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief OTG_FS Buffer Descriptor Bit Definition +//////////////////////////////////////////////////////////////////////////////// + +#define OTG_FS_BD_TOK_PID_Pos (2) +#define OTG_FS_BD_TOK_PID (0x0FU << OTG_FS_BD_TOK_PID_Pos) +#define OTG_FS_BD_DATA01_Pos (6) +#define OTG_FS_BD_DATA01 (0x01U << OTG_FS_BD_DATA01_Pos) +#define OTG_FS_BD_OWN_Pos (7) +#define OTG_FS_BD_OWN (0x01U << OTG_FS_BD_OWN_Pos) +#define OTG_FS_BD_BC_Pos (16) +#define OTG_FS_BD_BC (0x3FFU << OTG_FS_BD_BC_Pos) +#define OTG_FS_BD_ADDRESS_Pos (0) +#define OTG_FS_BD_ADDRESS (0xFFFFFFFFU << OTG_FS_BD_ADDRESS_Pos) + + + +/** +* @} +*/ +//#define OTG_FS_INT_STAT_RST ((uint32_t)0x01) +//#define OTG_FS_INT_STAT_ERROR ((uint32_t)0x02) +//#define OTG_FS_INT_STAT_SOF ((uint32_t)0x04) +//#define OTG_FS_INT_STAT_DNE ((uint32_t)0x08) +//#define OTG_FS_INT_STAT_SLEEP ((uint32_t)0x10) +//#define OTG_FS_INT_STAT_RESUME ((uint32_t)0x20) +//#define OTG_FS_INT_STAT_ATTACH ((uint32_t)0x40) +//#define OTG_FS_INT_STAT_STALL ((uint32_t)0x80) + +//TEMP +#define USB_INT_STAT_RST 0x01 +#define USB_INT_STAT_ERROR 0x02 +#define USB_INT_STAT_SOF_TOK 0x04 +#define USB_INT_STAT_TOK_DNE 0x08 +#define USB_INT_STAT_SLEEP 0x10 +#define USB_INT_STAT_RESUME 0x20 +#define USB_INT_STAT_ATTACH 0x40 +#define USB_INT_STAT_STALL 0x80 + + + + + + + + + + + + + + + + + + + +/*! @name PERID - Peripheral ID register */ +#define USB_PERID_ID_MASK (0x3FU) +#define USB_PERID_ID_SHIFT (0U) +#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK) + +/*! @name IDCOMP - Peripheral ID Complement register */ +#define USB_IDCOMP_NID_MASK (0x3FU) +#define USB_IDCOMP_NID_SHIFT (0U) +#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK) + +/*! @name REV - Peripheral Revision register */ +#define USB_REV_REV_MASK (0xFFU) +#define USB_REV_REV_SHIFT (0U) +#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK) + +/*! @name ADDINFO - Peripheral Additional Info register */ +#define USB_ADDINFO_IEHOST_MASK (0x1U) +#define USB_ADDINFO_IEHOST_SHIFT (0U) +#define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK) + +/*! @name OTGISTAT - OTG Interrupt Status register */ +#define USB_OTGISTAT_LINE_STATE_CHG_MASK (0x20U) +#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT (5U) +#define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK) +#define USB_OTGISTAT_ONEMSEC_MASK (0x40U) +#define USB_OTGISTAT_ONEMSEC_SHIFT (6U) +#define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK) + +/*! @name OTGICR - OTG Interrupt Control register */ +#define USB_OTGICR_LINESTATEEN_MASK (0x20U) +#define USB_OTGICR_LINESTATEEN_SHIFT (5U) +#define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK) +#define USB_OTGICR_ONEMSECEN_MASK (0x40U) +#define USB_OTGICR_ONEMSECEN_SHIFT (6U) +#define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK) + +/*! @name OTGSTAT - OTG Status register */ +#define USB_OTGSTAT_LINESTATESTABLE_MASK (0x20U) +#define USB_OTGSTAT_LINESTATESTABLE_SHIFT (5U) +#define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK) +#define USB_OTGSTAT_ONEMSECEN_MASK (0x40U) +#define USB_OTGSTAT_ONEMSECEN_SHIFT (6U) +#define USB_OTGSTAT_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSECEN_SHIFT)) & USB_OTGSTAT_ONEMSECEN_MASK) + +/*! @name OTGCTL - OTG Control register */ +#define USB_OTGCTL_OTGEN_MASK (0x4U) +#define USB_OTGCTL_OTGEN_SHIFT (2U) +#define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK) +#define USB_OTGCTL_DMLOW_MASK (0x10U) +#define USB_OTGCTL_DMLOW_SHIFT (4U) +#define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK) +#define USB_OTGCTL_DPLOW_MASK (0x20U) +#define USB_OTGCTL_DPLOW_SHIFT (5U) +#define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK) +#define USB_OTGCTL_DPHIGH_MASK (0x80U) +#define USB_OTGCTL_DPHIGH_SHIFT (7U) +#define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK) + +/*! @name ISTAT - Interrupt Status register */ +#define USB_ISTAT_USBRST_MASK (0x1U) +#define USB_ISTAT_USBRST_SHIFT (0U) +#define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK) +#define USB_ISTAT_ERROR_MASK (0x2U) +#define USB_ISTAT_ERROR_SHIFT (1U) +#define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK) +#define USB_ISTAT_SOFTOK_MASK (0x4U) +#define USB_ISTAT_SOFTOK_SHIFT (2U) +#define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK) +#define USB_ISTAT_TOKDNE_MASK (0x8U) +#define USB_ISTAT_TOKDNE_SHIFT (3U) +#define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK) +#define USB_ISTAT_SLEEP_MASK (0x10U) +#define USB_ISTAT_SLEEP_SHIFT (4U) +#define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK) +#define USB_ISTAT_RESUME_MASK (0x20U) +#define USB_ISTAT_RESUME_SHIFT (5U) +#define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK) +#define USB_ISTAT_ATTACH_MASK (0x40U) +#define USB_ISTAT_ATTACH_SHIFT (6U) +#define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK) +#define USB_ISTAT_STALL_MASK (0x80U) +#define USB_ISTAT_STALL_SHIFT (7U) +#define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK) + +/*! @name INTEN - Interrupt Enable register */ +#define USB_INTEN_USBRSTEN_MASK (0x1U) +#define USB_INTEN_USBRSTEN_SHIFT (0U) +#define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK) +#define USB_INTEN_ERROREN_MASK (0x2U) +#define USB_INTEN_ERROREN_SHIFT (1U) +#define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK) +#define USB_INTEN_SOFTOKEN_MASK (0x4U) +#define USB_INTEN_SOFTOKEN_SHIFT (2U) +#define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK) +#define USB_INTEN_TOKDNEEN_MASK (0x8U) +#define USB_INTEN_TOKDNEEN_SHIFT (3U) +#define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK) +#define USB_INTEN_SLEEPEN_MASK (0x10U) +#define USB_INTEN_SLEEPEN_SHIFT (4U) +#define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK) +#define USB_INTEN_RESUMEEN_MASK (0x20U) +#define USB_INTEN_RESUMEEN_SHIFT (5U) +#define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK) +#define USB_INTEN_ATTACHEN_MASK (0x40U) +#define USB_INTEN_ATTACHEN_SHIFT (6U) +#define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK) +#define USB_INTEN_STALLEN_MASK (0x80U) +#define USB_INTEN_STALLEN_SHIFT (7U) +#define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK) + +/*! @name ERRSTAT - Error Interrupt Status register */ +#define USB_ERRSTAT_PIDERR_MASK (0x1U) +#define USB_ERRSTAT_PIDERR_SHIFT (0U) +#define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK) +#define USB_ERRSTAT_CRC5EOF_MASK (0x2U) +#define USB_ERRSTAT_CRC5EOF_SHIFT (1U) +#define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK) +#define USB_ERRSTAT_CRC16_MASK (0x4U) +#define USB_ERRSTAT_CRC16_SHIFT (2U) +#define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK) +#define USB_ERRSTAT_DFN8_MASK (0x8U) +#define USB_ERRSTAT_DFN8_SHIFT (3U) +#define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK) +#define USB_ERRSTAT_BTOERR_MASK (0x10U) +#define USB_ERRSTAT_BTOERR_SHIFT (4U) +#define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK) +#define USB_ERRSTAT_DMAERR_MASK (0x20U) +#define USB_ERRSTAT_DMAERR_SHIFT (5U) +#define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK) +#define USB_ERRSTAT_OWNERR_MASK (0x40U) +#define USB_ERRSTAT_OWNERR_SHIFT (6U) +#define USB_ERRSTAT_OWNERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_OWNERR_SHIFT)) & USB_ERRSTAT_OWNERR_MASK) +#define USB_ERRSTAT_BTSERR_MASK (0x80U) +#define USB_ERRSTAT_BTSERR_SHIFT (7U) +#define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK) + +/*! @name ERREN - Error Interrupt Enable register */ +#define USB_ERREN_PIDERREN_MASK (0x1U) +#define USB_ERREN_PIDERREN_SHIFT (0U) +#define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK) +#define USB_ERREN_CRC5EOFEN_MASK (0x2U) +#define USB_ERREN_CRC5EOFEN_SHIFT (1U) +#define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK) +#define USB_ERREN_CRC16EN_MASK (0x4U) +#define USB_ERREN_CRC16EN_SHIFT (2U) +#define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK) +#define USB_ERREN_DFN8EN_MASK (0x8U) +#define USB_ERREN_DFN8EN_SHIFT (3U) +#define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK) +#define USB_ERREN_BTOERREN_MASK (0x10U) +#define USB_ERREN_BTOERREN_SHIFT (4U) +#define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK) +#define USB_ERREN_DMAERREN_MASK (0x20U) +#define USB_ERREN_DMAERREN_SHIFT (5U) +#define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK) +#define USB_ERREN_OWNERREN_MASK (0x40U) +#define USB_ERREN_OWNERREN_SHIFT (6U) +#define USB_ERREN_OWNERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_OWNERREN_SHIFT)) & USB_ERREN_OWNERREN_MASK) +#define USB_ERREN_BTSERREN_MASK (0x80U) +#define USB_ERREN_BTSERREN_SHIFT (7U) +#define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK) + +/*! @name STAT - Status register */ +#define USB_STAT_ODD_MASK (0x4U) +#define USB_STAT_ODD_SHIFT (2U) +#define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK) +#define USB_STAT_TX_MASK (0x8U) +#define USB_STAT_TX_SHIFT (3U) +#define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK) +#define USB_STAT_ENDP_MASK (0xF0U) +#define USB_STAT_ENDP_SHIFT (4U) +#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK) + +/*! @name CTL - Control register */ +#define USB_CTL_USBENSOFEN_MASK (0x1U) +#define USB_CTL_USBENSOFEN_SHIFT (0U) +#define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK) +#define USB_CTL_ODDRST_MASK (0x2U) +#define USB_CTL_ODDRST_SHIFT (1U) +#define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK) +#define USB_CTL_RESUME_MASK (0x4U) +#define USB_CTL_RESUME_SHIFT (2U) +#define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK) +#define USB_CTL_HOSTMODEEN_MASK (0x8U) +#define USB_CTL_HOSTMODEEN_SHIFT (3U) +#define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK) +#define USB_CTL_RESET_MASK (0x10U) +#define USB_CTL_RESET_SHIFT (4U) +#define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK) +#define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U) +#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U) +#define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK) +#define USB_CTL_SE0_MASK (0x40U) +#define USB_CTL_SE0_SHIFT (6U) +#define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK) +#define USB_CTL_JSTATE_MASK (0x80U) +#define USB_CTL_JSTATE_SHIFT (7U) +#define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK) + +/*! @name ADDR - Address register */ +#define USB_ADDR_ADDR_MASK (0x7FU) +#define USB_ADDR_ADDR_SHIFT (0U) +#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK) +#define USB_ADDR_LSEN_MASK (0x80U) +#define USB_ADDR_LSEN_SHIFT (7U) +#define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK) + +/*! @name BDTPAGE1 - BDT Page register 1 */ +#define USB_BDTPAGE1_BDTBA_MASK (0xFEU) +#define USB_BDTPAGE1_BDTBA_SHIFT (1U) +#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK) + +/*! @name FRMNUML - Frame Number register Low */ +#define USB_FRMNUML_FRM_MASK (0xFFU) +#define USB_FRMNUML_FRM_SHIFT (0U) +#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK) + +/*! @name FRMNUMH - Frame Number register High */ +#define USB_FRMNUMH_FRM_MASK (0x7U) +#define USB_FRMNUMH_FRM_SHIFT (0U) +#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK) + +/*! @name TOKEN - Token register */ +#define USB_TOKEN_TOKENENDPT_MASK (0xFU) +#define USB_TOKEN_TOKENENDPT_SHIFT (0U) +#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK) +#define USB_TOKEN_TOKENPID_MASK (0xF0U) +#define USB_TOKEN_TOKENPID_SHIFT (4U) +#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK) + +/*! @name SOFTHLD - SOF Threshold register */ +#define USB_SOFTHLD_CNT_MASK (0xFFU) +#define USB_SOFTHLD_CNT_SHIFT (0U) +#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK) + +/*! @name BDTPAGE2 - BDT Page Register 2 */ +#define USB_BDTPAGE2_BDTBA_MASK (0xFFU) +#define USB_BDTPAGE2_BDTBA_SHIFT (0U) +#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK) + +/*! @name BDTPAGE3 - BDT Page Register 3 */ +#define USB_BDTPAGE3_BDTBA_MASK (0xFFU) +#define USB_BDTPAGE3_BDTBA_SHIFT (0U) +#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK) + +/*! @name ENDPT - Endpoint Control register */ +#define USB_ENDPT_EPHSHK_MASK (0x1U) +#define USB_ENDPT_EPHSHK_SHIFT (0U) +#define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK) +#define USB_ENDPT_EPSTALL_MASK (0x2U) +#define USB_ENDPT_EPSTALL_SHIFT (1U) +#define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK) +#define USB_ENDPT_EPTXEN_MASK (0x4U) +#define USB_ENDPT_EPTXEN_SHIFT (2U) +#define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK) +#define USB_ENDPT_EPRXEN_MASK (0x8U) +#define USB_ENDPT_EPRXEN_SHIFT (3U) +#define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK) +#define USB_ENDPT_EPCTLDIS_MASK (0x10U) +#define USB_ENDPT_EPCTLDIS_SHIFT (4U) +#define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK) +#define USB_ENDPT_RETRYDIS_MASK (0x40U) +#define USB_ENDPT_RETRYDIS_SHIFT (6U) +#define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK) +#define USB_ENDPT_HOSTWOHUB_MASK (0x80U) +#define USB_ENDPT_HOSTWOHUB_SHIFT (7U) +#define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK) + +/* The count of USB_ENDPT */ +#define USB_ENDPT_COUNT (16U) + +/*! @name USBCTRL - USB Control register */ +#define USB_USBCTRL_UARTSEL_MASK (0x10U) +#define USB_USBCTRL_UARTSEL_SHIFT (4U) +#define USB_USBCTRL_UARTSEL(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTSEL_SHIFT)) & USB_USBCTRL_UARTSEL_MASK) +#define USB_USBCTRL_UARTCHLS_MASK (0x20U) +#define USB_USBCTRL_UARTCHLS_SHIFT (5U) +#define USB_USBCTRL_UARTCHLS(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTCHLS_SHIFT)) & USB_USBCTRL_UARTCHLS_MASK) +#define USB_USBCTRL_PDE_MASK (0x40U) +#define USB_USBCTRL_PDE_SHIFT (6U) +#define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK) +#define USB_USBCTRL_SUSP_MASK (0x80U) +#define USB_USBCTRL_SUSP_SHIFT (7U) +#define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK) + +/*! @name OBSERVE - USB OTG Observe register */ +#define USB_OBSERVE_DMPD_MASK (0x10U) +#define USB_OBSERVE_DMPD_SHIFT (4U) +#define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK) +#define USB_OBSERVE_DPPD_MASK (0x40U) +#define USB_OBSERVE_DPPD_SHIFT (6U) +#define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK) +#define USB_OBSERVE_DPPU_MASK (0x80U) +#define USB_OBSERVE_DPPU_SHIFT (7U) +#define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK) + +/*! @name CONTROL - USB OTG Control register */ +#define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U) +#define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U) +#define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK) + +/*! @name USBTRC0 - USB Transceiver Control register 0 */ +#define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U) +#define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U) +#define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK) +#define USB_USBTRC0_SYNC_DET_MASK (0x2U) +#define USB_USBTRC0_SYNC_DET_SHIFT (1U) +#define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK) +#define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK (0x4U) +#define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT (2U) +#define USB_USBTRC0_USB_CLK_RECOVERY_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK) +#define USB_USBTRC0_VREDG_DET_MASK (0x8U) +#define USB_USBTRC0_VREDG_DET_SHIFT (3U) +#define USB_USBTRC0_VREDG_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VREDG_DET_SHIFT)) & USB_USBTRC0_VREDG_DET_MASK) +#define USB_USBTRC0_VFEDG_DET_MASK (0x10U) +#define USB_USBTRC0_VFEDG_DET_SHIFT (4U) +#define USB_USBTRC0_VFEDG_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VFEDG_DET_SHIFT)) & USB_USBTRC0_VFEDG_DET_MASK) +#define USB_USBTRC0_USBRESMEN_MASK (0x20U) +#define USB_USBTRC0_USBRESMEN_SHIFT (5U) +#define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK) +#define USB_USBTRC0_USBRESET_MASK (0x80U) +#define USB_USBTRC0_USBRESET_SHIFT (7U) +#define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK) + +/*! @name USBFRMADJUST - Frame Adjust Register */ +#define USB_USBFRMADJUST_ADJ_MASK (0xFFU) +#define USB_USBFRMADJUST_ADJ_SHIFT (0U) +#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK) + +/*! @name MISCCTRL - Miscellaneous Control register */ +#define USB_MISCCTRL_SOFDYNTHLD_MASK (0x1U) +#define USB_MISCCTRL_SOFDYNTHLD_SHIFT (0U) +#define USB_MISCCTRL_SOFDYNTHLD(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_SOFDYNTHLD_SHIFT)) & USB_MISCCTRL_SOFDYNTHLD_MASK) +#define USB_MISCCTRL_SOFBUSSET_MASK (0x2U) +#define USB_MISCCTRL_SOFBUSSET_SHIFT (1U) +#define USB_MISCCTRL_SOFBUSSET(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_SOFBUSSET_SHIFT)) & USB_MISCCTRL_SOFBUSSET_MASK) +#define USB_MISCCTRL_OWNERRISODIS_MASK (0x4U) +#define USB_MISCCTRL_OWNERRISODIS_SHIFT (2U) +#define USB_MISCCTRL_OWNERRISODIS(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_OWNERRISODIS_SHIFT)) & USB_MISCCTRL_OWNERRISODIS_MASK) +#define USB_MISCCTRL_VREDG_EN_MASK (0x8U) +#define USB_MISCCTRL_VREDG_EN_SHIFT (3U) +#define USB_MISCCTRL_VREDG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VREDG_EN_SHIFT)) & USB_MISCCTRL_VREDG_EN_MASK) +#define USB_MISCCTRL_VFEDG_EN_MASK (0x10U) +#define USB_MISCCTRL_VFEDG_EN_SHIFT (4U) +#define USB_MISCCTRL_VFEDG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VFEDG_EN_SHIFT)) & USB_MISCCTRL_VFEDG_EN_MASK) +#define USB_MISCCTRL_STL_ADJ_EN_MASK (0x80U) +#define USB_MISCCTRL_STL_ADJ_EN_SHIFT (7U) +#define USB_MISCCTRL_STL_ADJ_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_STL_ADJ_EN_SHIFT)) & USB_MISCCTRL_STL_ADJ_EN_MASK) + +/*! @name STALL_IL_DIS - Peripheral mode stall disable for endpoints 7 to 0 in IN direction */ +#define USB_STALL_IL_DIS_STALL_I_DIS0_MASK (0x1U) +#define USB_STALL_IL_DIS_STALL_I_DIS0_SHIFT (0U) +#define USB_STALL_IL_DIS_STALL_I_DIS0(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS0_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS0_MASK) +#define USB_STALL_IL_DIS_STALL_I_DIS1_MASK (0x2U) +#define USB_STALL_IL_DIS_STALL_I_DIS1_SHIFT (1U) +#define USB_STALL_IL_DIS_STALL_I_DIS1(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS1_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS1_MASK) +#define USB_STALL_IL_DIS_STALL_I_DIS2_MASK (0x4U) +#define USB_STALL_IL_DIS_STALL_I_DIS2_SHIFT (2U) +#define USB_STALL_IL_DIS_STALL_I_DIS2(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS2_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS2_MASK) +#define USB_STALL_IL_DIS_STALL_I_DIS3_MASK (0x8U) +#define USB_STALL_IL_DIS_STALL_I_DIS3_SHIFT (3U) +#define USB_STALL_IL_DIS_STALL_I_DIS3(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS3_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS3_MASK) +#define USB_STALL_IL_DIS_STALL_I_DIS4_MASK (0x10U) +#define USB_STALL_IL_DIS_STALL_I_DIS4_SHIFT (4U) +#define USB_STALL_IL_DIS_STALL_I_DIS4(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS4_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS4_MASK) +#define USB_STALL_IL_DIS_STALL_I_DIS5_MASK (0x20U) +#define USB_STALL_IL_DIS_STALL_I_DIS5_SHIFT (5U) +#define USB_STALL_IL_DIS_STALL_I_DIS5(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS5_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS5_MASK) +#define USB_STALL_IL_DIS_STALL_I_DIS6_MASK (0x40U) +#define USB_STALL_IL_DIS_STALL_I_DIS6_SHIFT (6U) +#define USB_STALL_IL_DIS_STALL_I_DIS6(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS6_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS6_MASK) +#define USB_STALL_IL_DIS_STALL_I_DIS7_MASK (0x80U) +#define USB_STALL_IL_DIS_STALL_I_DIS7_SHIFT (7U) +#define USB_STALL_IL_DIS_STALL_I_DIS7(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS7_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS7_MASK) + +/*! @name STALL_IH_DIS - Peripheral mode stall disable for endpoints 15 to 8 in IN direction */ +#define USB_STALL_IH_DIS_STALL_I_DIS8_MASK (0x1U) +#define USB_STALL_IH_DIS_STALL_I_DIS8_SHIFT (0U) +#define USB_STALL_IH_DIS_STALL_I_DIS8(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS8_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS8_MASK) +#define USB_STALL_IH_DIS_STALL_I_DIS9_MASK (0x2U) +#define USB_STALL_IH_DIS_STALL_I_DIS9_SHIFT (1U) +#define USB_STALL_IH_DIS_STALL_I_DIS9(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS9_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS9_MASK) +#define USB_STALL_IH_DIS_STALL_I_DIS10_MASK (0x4U) +#define USB_STALL_IH_DIS_STALL_I_DIS10_SHIFT (2U) +#define USB_STALL_IH_DIS_STALL_I_DIS10(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS10_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS10_MASK) +#define USB_STALL_IH_DIS_STALL_I_DIS11_MASK (0x8U) +#define USB_STALL_IH_DIS_STALL_I_DIS11_SHIFT (3U) +#define USB_STALL_IH_DIS_STALL_I_DIS11(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS11_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS11_MASK) +#define USB_STALL_IH_DIS_STALL_I_DIS12_MASK (0x10U) +#define USB_STALL_IH_DIS_STALL_I_DIS12_SHIFT (4U) +#define USB_STALL_IH_DIS_STALL_I_DIS12(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS12_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS12_MASK) +#define USB_STALL_IH_DIS_STALL_I_DIS13_MASK (0x20U) +#define USB_STALL_IH_DIS_STALL_I_DIS13_SHIFT (5U) +#define USB_STALL_IH_DIS_STALL_I_DIS13(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS13_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS13_MASK) +#define USB_STALL_IH_DIS_STALL_I_DIS14_MASK (0x40U) +#define USB_STALL_IH_DIS_STALL_I_DIS14_SHIFT (6U) +#define USB_STALL_IH_DIS_STALL_I_DIS14(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS14_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS14_MASK) +#define USB_STALL_IH_DIS_STALL_I_DIS15_MASK (0x80U) +#define USB_STALL_IH_DIS_STALL_I_DIS15_SHIFT (7U) +#define USB_STALL_IH_DIS_STALL_I_DIS15(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS15_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS15_MASK) + +/*! @name STALL_OL_DIS - Peripheral mode stall disable for endpoints 7 to 0 in OUT direction */ +#define USB_STALL_OL_DIS_STALL_O_DIS0_MASK (0x1U) +#define USB_STALL_OL_DIS_STALL_O_DIS0_SHIFT (0U) +#define USB_STALL_OL_DIS_STALL_O_DIS0(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS0_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS0_MASK) +#define USB_STALL_OL_DIS_STALL_O_DIS1_MASK (0x2U) +#define USB_STALL_OL_DIS_STALL_O_DIS1_SHIFT (1U) +#define USB_STALL_OL_DIS_STALL_O_DIS1(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS1_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS1_MASK) +#define USB_STALL_OL_DIS_STALL_O_DIS2_MASK (0x4U) +#define USB_STALL_OL_DIS_STALL_O_DIS2_SHIFT (2U) +#define USB_STALL_OL_DIS_STALL_O_DIS2(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS2_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS2_MASK) +#define USB_STALL_OL_DIS_STALL_O_DIS3_MASK (0x8U) +#define USB_STALL_OL_DIS_STALL_O_DIS3_SHIFT (3U) +#define USB_STALL_OL_DIS_STALL_O_DIS3(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS3_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS3_MASK) +#define USB_STALL_OL_DIS_STALL_O_DIS4_MASK (0x10U) +#define USB_STALL_OL_DIS_STALL_O_DIS4_SHIFT (4U) +#define USB_STALL_OL_DIS_STALL_O_DIS4(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS4_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS4_MASK) +#define USB_STALL_OL_DIS_STALL_O_DIS5_MASK (0x20U) +#define USB_STALL_OL_DIS_STALL_O_DIS5_SHIFT (5U) +#define USB_STALL_OL_DIS_STALL_O_DIS5(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS5_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS5_MASK) +#define USB_STALL_OL_DIS_STALL_O_DIS6_MASK (0x40U) +#define USB_STALL_OL_DIS_STALL_O_DIS6_SHIFT (6U) +#define USB_STALL_OL_DIS_STALL_O_DIS6(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS6_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS6_MASK) +#define USB_STALL_OL_DIS_STALL_O_DIS7_MASK (0x80U) +#define USB_STALL_OL_DIS_STALL_O_DIS7_SHIFT (7U) +#define USB_STALL_OL_DIS_STALL_O_DIS7(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS7_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS7_MASK) + +/*! @name STALL_OH_DIS - Peripheral mode stall disable for endpoints 15 to 8 in OUT direction */ +#define USB_STALL_OH_DIS_STALL_O_DIS8_MASK (0x1U) +#define USB_STALL_OH_DIS_STALL_O_DIS8_SHIFT (0U) +#define USB_STALL_OH_DIS_STALL_O_DIS8(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS8_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS8_MASK) +#define USB_STALL_OH_DIS_STALL_O_DIS9_MASK (0x2U) +#define USB_STALL_OH_DIS_STALL_O_DIS9_SHIFT (1U) +#define USB_STALL_OH_DIS_STALL_O_DIS9(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS9_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS9_MASK) +#define USB_STALL_OH_DIS_STALL_O_DIS10_MASK (0x4U) +#define USB_STALL_OH_DIS_STALL_O_DIS10_SHIFT (2U) +#define USB_STALL_OH_DIS_STALL_O_DIS10(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS10_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS10_MASK) +#define USB_STALL_OH_DIS_STALL_O_DIS11_MASK (0x8U) +#define USB_STALL_OH_DIS_STALL_O_DIS11_SHIFT (3U) +#define USB_STALL_OH_DIS_STALL_O_DIS11(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS11_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS11_MASK) +#define USB_STALL_OH_DIS_STALL_O_DIS12_MASK (0x10U) +#define USB_STALL_OH_DIS_STALL_O_DIS12_SHIFT (4U) +#define USB_STALL_OH_DIS_STALL_O_DIS12(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS12_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS12_MASK) +#define USB_STALL_OH_DIS_STALL_O_DIS13_MASK (0x20U) +#define USB_STALL_OH_DIS_STALL_O_DIS13_SHIFT (5U) +#define USB_STALL_OH_DIS_STALL_O_DIS13(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS13_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS13_MASK) +#define USB_STALL_OH_DIS_STALL_O_DIS14_MASK (0x40U) +#define USB_STALL_OH_DIS_STALL_O_DIS14_SHIFT (6U) +#define USB_STALL_OH_DIS_STALL_O_DIS14(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS14_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS14_MASK) +#define USB_STALL_OH_DIS_STALL_O_DIS15_MASK (0x80U) +#define USB_STALL_OH_DIS_STALL_O_DIS15_SHIFT (7U) +#define USB_STALL_OH_DIS_STALL_O_DIS15(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS15_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS15_MASK) + +/*! @name CLK_RECOVER_CTRL - USB Clock recovery control */ +#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U) +#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U) +#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK) +#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U) +#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U) +#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK) +#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U) +#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U) +#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK) + +/*! @name CLK_RECOVER_IRC_EN - IRC48M oscillator enable register */ +#define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK (0x1U) +#define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT (0U) +#define USB_CLK_RECOVER_IRC_EN_REG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_REG_EN_MASK) +#define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK (0x2U) +#define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT (1U) +#define USB_CLK_RECOVER_IRC_EN_IRC_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK) + +/*! @name CLK_RECOVER_INT_EN - Clock recovery combined interrupt enable */ +#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK (0x10U) +#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT (4U) +#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT)) & USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK) + +/*! @name CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status */ +#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U) +#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U) +#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK) + +#define USB0_BASE ((0x50000000)) + +#define USB_BASE_ADDRS { USB0_BASE } + + + + + + + +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +#endif //__REG_USB_OTG_FS_H +//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_wwdg.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_wwdg.h new file mode 100644 index 000000000..a802bbab6 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_wwdg.h @@ -0,0 +1,133 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file reg_wwdg.h +/// @author AE TEAM +/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF +/// MM32 FIRMWARE LIBRARY. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

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+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion + +#ifndef __REG_WWDG_H +#define __REG_WWDG_H + +// Files includes + +#include +#include +#include "types.h" + + + + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + + + + + + + + + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief WWDG Base Address Definition +//////////////////////////////////////////////////////////////////////////////// +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) ///< Base Address: 0x40002C00 + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief WWDG Register Structure Definition +//////////////////////////////////////////////////////////////////////////////// +#undef USENCOMBINEREGISTER +#undef USENNEWREGISTER +#undef USENOLDREGISTER +#define USENCOMBINEREGISTER +#ifdef USENCOMBINEREGISTER +typedef struct { + __IO u32 CR; ///< Control register offset: 0x00 + union { + __IO u32 CFGR; ///< Configuration register offset: 0x04 + __IO u32 CFR; + }; + __IO u32 SR; ///< Status register offset: 0x08 +} WWDG_TypeDef; +#endif +#ifdef USENNEWREGISTER +typedef struct { + __IO u32 CR; ///< Control register offset: 0x00 + __IO u32 CFGR; ///< Configuration register offset: 0x04 + __IO u32 SR; ///< Status register offset: 0x08 +} WWDG_TypeDef; +#endif +#ifdef USENOLDREGISTER +typedef struct { + __IO u32 CR; + __IO u32 CFR; + __IO u32 SR; +} WWDG_TypeDef; +#endif + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief WWDG type pointer Definition +//////////////////////////////////////////////////////////////////////////////// +#define WWDG ((WWDG_TypeDef*) WWDG_BASE) + + + +//////////////////////////////////////////////////////////////////////////////// +/// @brief WWDG_CR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define WWDG_CR_CNT_Pos (0) +#define WWDG_CR_CNT (0x7FU << WWDG_CR_CNT_Pos) ///< T[6:0] bits (7-Bit counter (MSB to LSB)) +#define WWDG_CR_WDGA_Pos (7) +#define WWDG_CR_WDGA (0x01U << WWDG_CR_WDGA_Pos) ///< Activation bit + +//////////////////////////////////////////////////////////////////////////////// +/// @brief WWDG_CFR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define WWDG_CFGR_WINDOW_Pos (0) +#define WWDG_CFGR_WINDOW (0x7FU << WWDG_CFGR_WINDOW_Pos) ///< W[6:0] bits (7-bit window value) +#define WWDG_CFGR_WDGTB_Pos (7) +#define WWDG_CFGR_WDGTB (0x03U << WWDG_CFGR_WDGTB_Pos) ///< WDGTB[1:0] bits (Timer Base) +#define WWDG_CFGR_WDGTB_1 (0x00U << WWDG_CFGR_WDGTB_Pos) ///< WDGTB[1:0] bits (Timer Base /1) +#define WWDG_CFGR_WDGTB_2 (0x01U << WWDG_CFGR_WDGTB_Pos) ///< WDGTB[1:0] bits (Timer Base /2) +#define WWDG_CFGR_WDGTB_4 (0x02U << WWDG_CFGR_WDGTB_Pos) ///< WDGTB[1:0] bits (Timer Base /4) +#define WWDG_CFGR_WDGTB_8 (0x03U << WWDG_CFGR_WDGTB_Pos) ///< WDGTB[1:0] bits (Timer Base /8) +#define WWDG_CFGR_EWI_Pos (9) +#define WWDG_CFGR_EWI (0x01U << WWDG_CFGR_EWI_Pos) ///< Early Wakeup Interrupt + +//////////////////////////////////////////////////////////////////////////////// +/// @brief WWDG_SR Register Bit Definition +//////////////////////////////////////////////////////////////////////////////// +#define WWDG_SR_EWIF_Pos (0) +#define WWDG_SR_EWIF (0x01U << WWDG_SR_EWIF_Pos) ///< Early Wakeup Interrupt Flag + + + + +/// @} + +/// @} + +/// @} + +//////////////////////////////////////////////////////////////////////////////// +#endif +//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/types.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/types.h new file mode 100644 index 000000000..baceddd05 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/types.h @@ -0,0 +1,105 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file types.h +/// @author AE TEAM +/// @brief THIS FILE PROVIDES ALL THE TYPE FIRMWARE FUNCTIONS. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#ifndef __TYPES_H +#define __TYPES_H + +// Files includes +#include +#include + + + +#ifdef __cplusplus +#define __I volatile ///< Defines 'read only' permissions +#else +#define __I volatile const ///< Defines 'read only' permissions +#endif +#define __O volatile ///< Defines 'write only' permissions +#define __IO volatile ///< Defines 'read / write' permissions + +typedef long long s64; ///< used for signed 64bit + +typedef signed int s32; +typedef signed short s16; +typedef signed char s8; + +typedef signed int const sc32; ///< Read Only +typedef signed short const sc16; ///< Read Only +typedef signed char const sc8; ///< Read Only + +typedef volatile signed int vs32; +typedef volatile signed short vs16; +typedef volatile signed char vs8; + +typedef volatile signed int const vsc32; ///< Read Only +typedef volatile signed short const vsc16; ///< Read Only +typedef volatile signed char const vsc8; ///< Read Only + +typedef unsigned int u32; +typedef unsigned short u16; +typedef unsigned char u8; + +typedef unsigned int const uc32; ///< Read Only +typedef unsigned short const uc16; ///< Read Only +typedef unsigned char const uc8; ///< Read Only + +typedef volatile unsigned int vu32; +typedef volatile unsigned short vu16; +typedef volatile unsigned char vu8; + +typedef volatile unsigned int const vuc32; ///< Read Only +typedef volatile unsigned short const vuc16; ///< Read Only +typedef volatile unsigned char const vuc8; ///< Read Only +typedef bool BOOL; +#ifndef NULL +#define NULL ((void *)0) +#endif +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + + +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +#define U8_MAX ((u8)255) +#define S8_MAX ((s8)127) +#define S8_MIN ((s8)-128) +#define U16_MAX ((u16)65535u) +#define S16_MAX ((s16)32767) +#define S16_MIN ((s16)-32768) +#define U32_MAX ((u32)4294967295uL) +#define S32_MAX ((s32)2147483647) +#define S32_MIN ((s32)-2147483648uL) + +#define MAX(a,b)((a)>(b)?(a):(b)) +#define MIN(a,b)((a)<(b)?(a):(b)) + +#define SET_BIT(reg, bit) ((reg) |= (bit)) +#define CLEAR_BIT(reg, bit) ((reg) &= ~(bit)) +#define READ_BIT(reg, bit) ((reg) & (bit)) +#define CLEAR_REG(reg) ((reg) = (0x0)) +#define WRITE_REG(reg, value) ((reg) = (value)) +#define READ_REG(reg) ((reg)) +#define MODIFY_REG(reg, CLEARMASK, SETMASK) WRITE_REG((reg), (((READ_REG(reg)) & (~(CLEARMASK))) | (SETMASK))) +#define POSITION_VAL(value) (__CLZ(__RBIT(value))) + +#define LEFT_SHIFT_BIT(x) (1 << x) + + +#endif diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Source/GCC_StartAsm/startup_mm32m3ux_u_gcc.S b/hw/mcu/mm32/mm32f327x/MM32F327x/Source/GCC_StartAsm/startup_mm32m3ux_u_gcc.S new file mode 100644 index 000000000..920aefcba --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Source/GCC_StartAsm/startup_mm32m3ux_u_gcc.S @@ -0,0 +1,440 @@ +/** + ****************************************************************************** + * @file startup_mm32m3ux_u_gcc.s + * @author AE Team + * @brief MM32 devices vector table for GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + + .global g_pfnVectors + .global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ + .word _sidata +/* start address for the .data section. defined in linker script */ + .word _sdata +/* end address for the .data section. defined in linker script */ + .word _edata +/* start address for the .bss section. defined in linker script */ + .word _sbss +/* end address for the .bss section. defined in linker script */ + .word _ebss + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr + .size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack /* Top of Stack */ + .word Reset_Handler /* Reset Handler */ + .word NMI_Handler /*-14 NMI Handler */ + .word HardFault_Handler /*-13 Hard Fault Handler */ + .word MemManage_Handler /*-12 MPU Fault Handler */ + .word BusFault_Handler /*-11 Bus Fault Handler */ + .word UsageFault_Handler /*-10 Usage Fault Handler */ + .word 0 /*-9 Reserved */ + .word 0 /*-8 Reserved */ + .word 0 /*-7 Reserved */ + .word 0 /*-6 Reserved */ + .word SVC_Handler /*-5 SVCall Handler */ + .word DebugMon_Handler /*-4 Debug Monitor Handler */ + .word 0 /*-3 Reserved */ + .word PendSV_Handler /*-2 PendSV Handler */ + .word SysTick_Handler /*-1 SysTick Handler */ + + /* External Interrupts */ + .word WWDG_IRQHandler /*0 Window Watchdog */ + .word PVD_IRQHandler /*1 PVD through EXTI Line detect */ + .word TAMPER_IRQHandler /*2 Tamper */ + .word RTC_IRQHandler /*3 RTC */ + .word FLASH_IRQHandler /*4 Flash */ + .word RCC_CRS_IRQHandler /*5 RCC */ + .word EXTI0_IRQHandler /*6 EXTI Line 0 */ + .word EXTI1_IRQHandler /*7 EXTI Line 1 */ + .word EXTI2_IRQHandler /*8 EXTI Line 2 */ + .word EXTI3_IRQHandler /*9 EXTI Line 3 */ + .word EXTI4_IRQHandler /*10 EXTI Line 4 */ + .word DMA1_Channel1_IRQHandler /*11 DMA1 Channel 1 */ + .word DMA1_Channel2_IRQHandler /*12 DMA1 Channel 2 */ + .word DMA1_Channel3_IRQHandler /*13 DMA1 Channel 3 */ + .word DMA1_Channel4_IRQHandler /*14 DMA1 Channel 4 */ + .word DMA1_Channel5_IRQHandler /*15 DMA1 Channel 5 */ + .word DMA1_Channel6_IRQHandler /*16 DMA1 Channel 6 */ + .word DMA1_Channel7_IRQHandler /*17 DMA1 Channel 7 */ + .word ADC1_2_IRQHandler /*18 ADC1 and ADC2 */ + .word FlashCache_IRQHandler /*19 FlashCache outage */ + .word 0 /*20 Reserved */ + .word CAN1_RX_IRQHandler /*21 CAN1_RX */ + .word 0 /*22 Reserved */ + .word EXTI9_5_IRQHandler /*23 EXTI Line 9..5 */ + .word TIM1_BRK_IRQHandler /*24 TIM1 Break */ + .word TIM1_UP_IRQHandler /*25 TIM1 Update */ + .word TIM1_TRG_COM_IRQHandler /*26 TIM1 Trigger and Commutation */ + .word TIM1_CC_IRQHandler /*27 TIM1 Capture Compare */ + .word TIM2_IRQHandler /*28 TIM2 */ + .word TIM3_IRQHandler /*29 TIM3 */ + .word TIM4_IRQHandler /*30 TIM4 */ + .word I2C1_IRQHandler /*31 I2C1 Event */ + .word 0 /*32 Reserved */ + .word I2C2_IRQHandler /*33 I2C2 Event */ + .word 0 /*34 Reserved */ + .word SPI1_IRQHandler /*35 SPI1 */ + .word SPI2_IRQHandler /*36 SPI2 */ + .word UART1_IRQHandler /*37 UART1 */ + .word UART2_IRQHandler /*38 UART2 */ + .word UART3_IRQHandler /*39 UART3 */ + .word EXTI15_10_IRQHandler /*40 EXTI Line 15..10 */ + .word RTCAlarm_IRQHandler /*41 RTC Alarm through EXTI Line 17 */ + .word OTG_FS_WKUP_IRQHandler /*42 USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_IRQHandler /*43 TIM8 Break */ + .word TIM8_UP_IRQHandler /*44 TIM8 Update */ + .word TIM8_TRG_COM_IRQHandler /*45 TIM8 Trigger and Commutation */ + .word TIM8_CC_IRQHandler /*46 TIM8 Capture Compare */ + .word ADC3_IRQHandler /*47 ADC3 */ + .word 0 /*48 Reserved */ + .word SDIO_IRQHandler /*49 SDIO */ + .word TIM5_IRQHandler /*50 TIM5 */ + .word SPI3_IRQHandler /*51 SPI3 */ + .word UART4_IRQHandler /*52 UART4 */ + .word UART5_IRQHandler /*53 UART5 */ + .word TIM6_IRQHandler /*54 TIM6 */ + .word TIM7_IRQHandler /*55 TIM7 */ + .word DMA2_Channel1_IRQHandler /*56 DMA2 Channel 1 */ + .word DMA2_Channel2_IRQHandler /*57 DMA2 Channel 2 */ + .word DMA2_Channel3_IRQHandler /*58 DMA2 Channel 3 */ + .word DMA2_Channel4_IRQHandler /*59 DMA2 Channel 4 */ + .word DMA2_Channel5_IRQHandler /*60 DMA2 Channel 5 */ + .word ETH_IRQHandler /*61 Ethernet */ + .word 0 /*62 Reserved */ + .word 0 /*63 Reserved */ + .word COMP1_2_IRQHandler /*64 COMP1,COMP2 */ + .word 0 /*65 Reserved */ + .word 0 /*66 Reserved */ + .word OTG_FS_IRQHandler /*67 USB OTG_FullSpeed */ + .word 0 /*68 Reserved */ + .word 0 /*69 Reserved */ + .word 0 /*70 Reserved */ + .word UART6_IRQHandler /*71 UART6 */ + .word 0 /*72 Reserved */ + .word 0 /*73 Reserved */ + .word 0 /*74 Reserved */ + .word 0 /*75 Reserved */ + .word 0 /*76 Reserved */ + .word 0 /*77 Reserved */ + .word 0 /*78 Reserved */ + .word 0 /*79 Reserved */ + .word 0 /*80 Reserved */ + .word 0 /*81 Reserved */ + .word UART7_IRQHandler /*82 UART7 */ + .word UART8_IRQHandler /*83 UART8 */ +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler ,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler ,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler ,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler ,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler ,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler ,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler ,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler ,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler ,Default_Handler + + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler ,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler ,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler ,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler ,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler ,Default_Handler + + .weak RCC_CRS_IRQHandler + .thumb_set RCC_CRS_IRQHandler ,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler ,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler ,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler ,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler ,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler ,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler ,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler ,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler ,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler ,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler ,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler ,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler ,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler ,Default_Handler + + .weak FlashCache_IRQHandler + .thumb_set FlashCache_IRQHandler ,Default_Handler + + .weak CAN1_RX_IRQHandler + .thumb_set CAN1_RX_IRQHandler ,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler ,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler ,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler ,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler ,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler ,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler ,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler ,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler ,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler ,Default_Handler + + .weak I2C2_IRQHandler + .thumb_set I2C2_IRQHandler ,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler ,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler ,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler ,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler ,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler ,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler ,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler ,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler ,Default_Handler + + .weak TIM8_BRK_IRQHandler + .thumb_set TIM8_BRK_IRQHandler ,Default_Handler + + .weak TIM8_UP_IRQHandler + .thumb_set TIM8_UP_IRQHandler ,Default_Handler + + .weak TIM8_TRG_COM_IRQHandler + .thumb_set TIM8_TRG_COM_IRQHandler ,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler ,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler ,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler ,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler ,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler ,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler ,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler ,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler ,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler ,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler ,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler ,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler ,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler ,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler ,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler ,Default_Handler + + .weak COMP1_2_IRQHandler + .thumb_set COMP1_2_IRQHandler ,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler ,Default_Handler + + .weak UART6_IRQHandler + .thumb_set UART6_IRQHandler ,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler ,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler ,Default_Handler + + + + +/****END OF FILE****/ + diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Source/system_mm32f327x.c b/hw/mcu/mm32/mm32f327x/MM32F327x/Source/system_mm32f327x.c new file mode 100644 index 000000000..cdfa8e801 --- /dev/null +++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Source/system_mm32f327x.c @@ -0,0 +1,866 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file SYSTEM_MM32.C +/// @author AE TEAM +/// @brief THIS FILE PROVIDES ALL THE SYSTEM FUNCTIONS. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +// Define to prevent recursive inclusion +#define _SYSTEM_MM32_C_ + +// Files includes + +/// @addtogroup CMSIS +/// @{ + +#include "mm32_device.h" + + +/// @} + + + +/// @} + + +/// Uncomment the line corresponding to the desired System clock (SYSCLK) +/// frequency (after reset the HSI is used as SYSCLK source) +/// +/// IMPORTANT NOTE: +/// ============== +/// 1. After each device reset the HSI is used as System clock source. +/// +/// 2. Please make sure that the selected System clock doesn't exceed your device's +/// maximum frequency. +/// +/// 3. If none of the define below is enabled, the HSI is used as System clock +/// source. +/// +/// 4. The System clock configuration functions provided within this file assume that: +/// - For Low, Medium and High density Value line devices an external 8MHz +/// crystal is used to drive the System clock. +/// - For Low, Medium and High density devices an external 8MHz crystal is +/// used to drive the System clock. +/// - For Connectivity line devices an external 25MHz crystal is used to drive +/// the System clock. +/// If you are using different crystal you have to adapt those functions accordingly. + +//#define SYSCLK_FREQ_HSE HSE_VALUE //HSE_VALUE is define in reg_common.h +//#define SYSCLK_FREQ_24MHz (HSE_VALUE*3) //24000000 based HSE_VALUE = 8000000 +//#define SYSCLK_FREQ_36MHz (HSE_VALUE*9/2) //36000000 based HSE_VALUE = 8000000 +//#define SYSCLK_FREQ_48MHz (HSE_VALUE*6) //48000000 based HSE_VALUE = 8000000 +//#define SYSCLK_FREQ_XXMHz (HSE_VALUE*6) //48000000 based HSE_VALUE = 8000000 +//#define SYSCLK_FREQ_XXMHz (HSE_VALUE*9) //72000000 based HSE_VALUE = 8000000 +//#define SYSCLK_FREQ_XXMHz (HSE_VALUE*12) //96000000 based HSE_VALUE = 8000000 +#define SYSCLK_FREQ_XXMHz (HSE_VALUE*12) //120000000 based HSE_VALUE = 8000000 + +#if defined(SYSCLK_FREQ_HSE) || defined(SYSCLK_FREQ_24MHz) || defined(SYSCLK_FREQ_36MHz) || defined(SYSCLK_FREQ_48MHz) || defined(SYSCLK_FREQ_XXMHz) + +#if defined(HSE_VALUE) && (!(HSE_VALUE == 8000000)) +#warning redefine HSE_VALUE in reg_common.h Line 48 and ignore this warning +#endif + +#endif + + +//#define SYSCLK_HSI_24MHz 24000000 +//#define SYSCLK_HSI_36MHz 36000000 +//#define SYSCLK_HSI_48MHz 48000000 +//#define SYSCLK_HSI_XXMHz 48000000 +//#define SYSCLK_HSI_XXMHz 72000000 +//#define SYSCLK_HSI_XXMHz 96000000 +#define SYSCLK_HSI_XXMHz 120000000 +/// Uncomment the following line if you need to relocate your vector Table in +/// Internal SRAM. +///#define VECT_TAB_SRAM +#define VECT_TAB_OFFSET 0x0 +/// Vector Table base offset field. +/// This value must be a multiple of 0x200. + + +/// @} + + + + +/////////////////////////////////////////////////////////////// +///Clock Definitions +/////////////////////////////////////////////////////////////// +#if defined SYSCLK_FREQ_HSE +u32 SystemCoreClock = SYSCLK_FREQ_HSE; +#elif defined SYSCLK_FREQ_24MHz +u32 SystemCoreClock = SYSCLK_FREQ_24MHz; +#elif defined SYSCLK_FREQ_36MHz +u32 SystemCoreClock = SYSCLK_FREQ_36MHz; +#elif defined SYSCLK_FREQ_48MHz +u32 SystemCoreClock = SYSCLK_FREQ_48MHz; +#elif defined SYSCLK_FREQ_XXMHz +u32 SystemCoreClock = SYSCLK_FREQ_XXMHz; + + +#elif defined SYSCLK_HSI_24MHz +u32 SystemCoreClock = SYSCLK_HSI_24MHz; +#elif defined SYSCLK_HSI_36MHz +u32 SystemCoreClock = SYSCLK_HSI_36MHz; +#elif defined SYSCLK_HSI_48MHz +u32 SystemCoreClock = SYSCLK_HSI_48MHz; +#elif defined SYSCLK_HSI_XXMHz +u32 SystemCoreClock = SYSCLK_HSI_XXMHz; +#else //HSI Selected as System Clock source +u32 SystemCoreClock = HSI_VALUE; +#endif + +__I u8 AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/// @} + + +static void SetSysClock(void); + +#if defined SYSCLK_FREQ_HSE +static void SetSysClockToHSE(void); +#elif defined SYSCLK_FREQ_24MHz +static void SetSysClockTo24(void); +#elif defined SYSCLK_FREQ_36MHz +static void SetSysClockTo36(void); +#elif defined SYSCLK_FREQ_48MHz +static void SetSysClockTo48(void); +#elif defined SYSCLK_FREQ_XXMHz +static void SetSysClockToXX(void); + +#elif defined SYSCLK_HSI_24MHz +static void SetSysClockTo24_HSI(void); +#elif defined SYSCLK_HSI_36MHz +static void SetSysClockTo36_HSI(void); +#elif defined SYSCLK_HSI_48MHz +static void SetSysClockTo48_HSI(void); +#elif defined SYSCLK_HSI_XXMHz +static void SetSysClockToXX_HSI(void); +#endif + +#ifdef DATA_IN_ExtSRAM +static void SystemInit_ExtMemCtl(void); +#endif //DATA_IN_ExtSRAM + + +/// @} + + + +/// @brief Setup the microcontroller system +/// Initialize the Embedded Flash Interface, the PLL and update the +/// SystemCoreClock variable. +/// @note This function should be used only after reset. +/// @param None +/// @retval None + +void SystemInit (void) +{ + //Reset the RCC clock configuration to the default reset state(for debug purpose) + //Set HSION bit + RCC->CR |= (u32)0x00000001; + + //Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits + RCC->CFGR &= (u32)0xF8FFC00C; + + //Reset HSEON, CSSON and PLLON bits + RCC->CR &= (u32)0xFEF6FFFF; + + //Reset HSEBYP bit + RCC->CR &= (u32)0xFFFBFFFF; + + //Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits + RCC->CFGR &= (u32)0xFF3CFFFF; + RCC->CR &= (u32)0x008FFFFF; + + //Disable all interrupts and clear pending bits + RCC->CIR = 0x009F0000; + //Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers + //Configure the Flash Latency cycles and enable prefetch buffer + SetSysClock(); +} + + +/// @brief use to return the pllm&plln. +/// @param pllclkSourceFrq : PLL source clock frquency; +/// pllclkFrq : Target PLL clock frquency; +/// plln : PLL factor PLLN +/// pllm : PLL factor PLLM +/// @retval amount of error +u32 AutoCalPllFactor(u32 pllclkSourceFrq, u32 pllclkFrq, u8* plln, u8* pllm) +{ + u32 n, m; + u32 tempFrq; + u32 minDiff = pllclkFrq; + u8 flag = 0; + for(m = 0; m < 4 ; m++) { + for(n = 0; n < 64 ; n++) { + tempFrq = pllclkSourceFrq * (n + 1) / (m + 1); + tempFrq = (tempFrq > pllclkFrq) ? (tempFrq - pllclkFrq) : (pllclkFrq - tempFrq) ; + + if(minDiff > tempFrq) { + minDiff = tempFrq; + *plln = n; + *pllm = m; + } + if(minDiff == 0) { + flag = 1; + break; + } + } + if(flag != 0) { + break; + } + } + return minDiff; +} +static void DELAY_xUs(u32 count) +{ + u32 temp; + SysTick->CTRL = 0x0; //disable systick function + SysTick->LOAD = count * 8; //time count for 1us with HSI as SYSCLK + SysTick->VAL = 0x00; //clear counter + SysTick->CTRL = 0x5; //start discrease with Polling + do { + temp = SysTick->CTRL; + } while((temp & 0x01) && !(temp & (1 << 16))); //wait time count done + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; //Close Counter + SysTick->VAL = 0X00; //clear counter +} +/// @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. +/// @param None +/// @retval None + +static void SetSysClock(void) +{ + CACHE->CCR &= ~(0x3 << 3); + CACHE->CCR |= 1; + while((CACHE->SR & 0x3) != 2); +#ifdef SYSCLK_FREQ_HSE + SetSysClockToHSE(); +#elif defined SYSCLK_FREQ_24MHz + SetSysClockTo24(); +#elif defined SYSCLK_FREQ_36MHz + SetSysClockTo36(); +#elif defined SYSCLK_FREQ_48MHz + SetSysClockTo48(); +#elif defined SYSCLK_FREQ_XXMHz + SetSysClockToXX(); + +#elif defined SYSCLK_HSI_24MHz + SetSysClockTo24_HSI(); +#elif defined SYSCLK_HSI_36MHz + SetSysClockTo36_HSI(); +#elif defined SYSCLK_HSI_48MHz + SetSysClockTo48_HSI(); +#elif defined SYSCLK_HSI_XXMHz + SetSysClockToXX_HSI(); +#endif + + //If none of the define above is enabled, the HSI is used as System clock + //source (default after reset) +} + +#ifdef SYSCLK_FREQ_HSE + +/// @brief Selects HSE as System clock source and configure HCLK, PCLK2 +/// and PCLK1 prescalers. +/// @note This function should be used only after reset. +/// @param None +/// @retval None + +static void SetSysClockToHSE(void) +{ + __IO u32 StartUpCounter = 0, HSEStatus = 0; + s32 i; + + //SYSCLK, HCLK, PCLK2 and PCLK1 configuration --------------------------- + //Enable HSE + RCC->CR |= ((u32)RCC_CR_HSEON); + + //Wait till HSE is ready and if Time out is reached exit + do { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) { + HSEStatus = (u32)0x01; + i = 2000; + while(i--); + } + else { + HSEStatus = (u32)0x00; + } + + if (HSEStatus == (u32)0x01) { + //Enable Prefetch Buffer + FLASH->ACR |= FLASH_ACR_PRFTBE; + + //Flash 0 wait state ,bit0~2 + FLASH->ACR &= ~0x07; + //HCLK = SYSCLK + RCC->CFGR |= (u32)RCC_CFGR_HPRE_DIV1; + + //PCLK2 = HCLK + RCC->CFGR |= (u32)RCC_CFGR_PPRE2_DIV1; + + //PCLK1 = HCLK + RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV1; + + //Select HSE as system clock source + RCC->CFGR &= (u32)((u32)~(RCC_CFGR_SW)); + RCC->CFGR |= (u32)RCC_CFGR_SW_HSE; + + //Wait till HSE is used as system clock source + while ((RCC->CFGR & (u32)RCC_CFGR_SWS) != (u32)0x04) { + } + } + else { + //If HSE fails to start-up, the application will have wrong clock + //configuration. User can add here some code to deal with this error + } +} +#elif defined SYSCLK_FREQ_24MHz + +/// @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 +/// and PCLK1 prescalers. +/// @note This function should be used only after reset. +/// @param None +/// @retval None + +static void SetSysClockTo24(void) +{ + __IO u32 StartUpCounter = 0, HSEStatus = 0; + s32 i; + + //SYSCLK, HCLK, PCLK2 and PCLK1 configuration --------------------------- + //Enable HSE + RCC->CR |= ((u32)RCC_CR_HSEON); + + //Wait till HSE is ready and if Time out is reached exit + do { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) { + HSEStatus = (u32)0x01; + i = 2000; + while(i--); + } + else { + HSEStatus = (u32)0x00; + } + + if (HSEStatus == (u32)0x01) { + //Enable Prefetch Buffer + FLASH->ACR |= FLASH_ACR_PRFTBE; + //Flash 0 wait state ,bit0~2 + FLASH->ACR &= ~0x07; + FLASH->ACR |= 0x01; + //HCLK = SYSCLK + RCC->CFGR |= (u32)RCC_CFGR_HPRE_DIV1; + + //PCLK2 = HCLK + RCC->CFGR |= (u32)RCC_CFGR_PPRE2_DIV1; + + //PCLK1 = HCLK + RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV1; + + // PLL configuration: = (HSE ) * (2+1) = 24 MHz + RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ; + RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC ; + + RCC->APB1ENR |= RCC_APB1ENR_PWR; + RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP)); + RCC->PLLCFGR |= ((0 << RCC_PLLCFGR_PLL_DN_Pos) | (2 << RCC_PLLCFGR_PLL_DP_Pos)); + //Enable PLL + RCC->CR |= RCC_CR_PLLON; + + //Wait till PLL is ready + while((RCC->CR & RCC_CR_PLLRDY) == 0) { + } + + //Select PLL as system clock source + RCC->CFGR &= (u32)((u32)~(RCC_CFGR_SW)); + RCC->CFGR |= (u32)RCC_CFGR_SW_PLL; + + //Wait till PLL is used as system clock source + while ((RCC->CFGR & (u32)RCC_CFGR_SWS) != (u32)0x08) { + } + } + else { + //If HSE fails to start-up, the application will have wrong clock + //configuration. User can add here some code to deal with this error + } +} +#elif defined SYSCLK_FREQ_36MHz + +/// @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 +/// and PCLK1 prescalers. +/// @note This function should be used only after reset. +/// @param None +/// @retval None + +static void SetSysClockTo36(void) +{ + s32 i; + __IO u32 StartUpCounter = 0, HSEStatus = 0; + + //SYSCLK, HCLK, PCLK2 and PCLK1 configuration --------------------------- + //Enable HSE + RCC->CR |= ((u32)RCC_CR_HSEON); + + //Wait till HSE is ready and if Time out is reached exit + do { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) { + HSEStatus = (u32)0x01; + i = 2000; + while(i--); + } + else { + HSEStatus = (u32)0x00; + } + + if (HSEStatus == (u32)0x01) { + //Enable Prefetch Buffer + FLASH->ACR |= FLASH_ACR_PRFTBE; + + //Flash 0 wait state ,bit0~2 + FLASH->ACR &= ~0x07; + FLASH->ACR |= 0x01; + //HCLK = SYSCLK + RCC->CFGR |= (u32)RCC_CFGR_HPRE_DIV1; + + //PCLK2 = HCLK + RCC->CFGR |= (u32)RCC_CFGR_PPRE2_DIV1; + + //PCLK1 = HCLK + RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV1; + RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ; + RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC ; + + RCC->APB1ENR |= RCC_APB1ENR_PWR; + RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP)); + RCC->PLLCFGR |= ((1 << RCC_PLLCFGR_PLL_DN_Pos) | (8 << RCC_PLLCFGR_PLL_DP_Pos)); + //Enable PLL + RCC->CR |= RCC_CR_PLLON; + + //Wait till PLL is ready + while((RCC->CR & RCC_CR_PLLRDY) == 0) { + } + + //Select PLL as system clock source + RCC->CFGR &= (u32)((u32)~(RCC_CFGR_SW)); + RCC->CFGR |= (u32)RCC_CFGR_SW_PLL; + + //Wait till PLL is used as system clock source + while ((RCC->CFGR & (u32)RCC_CFGR_SWS) != (u32)0x08) { + } + } + else { + //If HSE fails to start-up, the application will have wrong clock + //configuration. User can add here some code to deal with this error + } +} +#elif defined SYSCLK_FREQ_48MHz + +/// @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 +/// and PCLK1 prescalers. +/// @note This function should be used only after reset. +/// @param None +/// @retval None + +static void SetSysClockTo48(void) +{ + __IO u32 StartUpCounter = 0, HSEStatus = 0; + s32 i; + //SYSCLK, HCLK, PCLK2 and PCLK1 configuration --------------------------- + //Enable HSE + RCC->CR |= ((u32)RCC_CR_HSEON); + + //Wait till HSE is ready and if Time out is reached exit + do { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) { + HSEStatus = (u32)0x01; + i = 2000; + while(i--); + } + else { + HSEStatus = (u32)0x00; + } + + if (HSEStatus == (u32)0x01) { + //Enable Prefetch Buffer + FLASH->ACR |= FLASH_ACR_PRFTBE; + //Flash 0 wait state ,bit0~2 + FLASH->ACR &= ~0x07; + FLASH->ACR |= 0x02; + //HCLK = SYSCLK + RCC->CFGR |= (u32)RCC_CFGR_HPRE_DIV1; + + //PCLK2 = HCLK + RCC->CFGR |= (u32)RCC_CFGR_PPRE2_DIV1; + + //PCLK1 = HCLK + RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV2; + + // PLL configuration: = (HSE ) * (5+1) = 48MHz + RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ; + RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC ; + + RCC->APB1ENR |= RCC_APB1ENR_PWR; + RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP)); + RCC->PLLCFGR |= ((0 << RCC_PLLCFGR_PLL_DN_Pos) | (5 << RCC_PLLCFGR_PLL_DP_Pos)); + //Enable PLL + RCC->CR |= RCC_CR_PLLON; + + //Wait till PLL is ready + while((RCC->CR & RCC_CR_PLLRDY) == 0) { + } + + //Select PLL as system clock source + RCC->CFGR &= (u32)((u32)~(RCC_CFGR_SW)); + RCC->CFGR |= (u32)RCC_CFGR_SW_PLL; + + //Wait till PLL is used as system clock source + while ((RCC->CFGR & (u32)RCC_CFGR_SWS) != (u32)0x08) { + } + } + else { + //If HSE fails to start-up, the application will have wrong clock + //configuration. User can add here some code to deal with this error + } +} +#elif defined SYSCLK_FREQ_XXMHz + +/// @brief Sets System clock frequency to XXMHz and configure HCLK, PCLK2 +/// and PCLK1 prescalers. +/// @note This function should be used only after reset. +/// @param None +/// @retval None + +static void SetSysClockToXX(void) +{ + __IO u32 temp, tn, tm;//j, + __IO u32 StartUpCounter = 0, HSEStatus = 0; + + u8 plln, pllm; + + RCC->CR |= RCC_CR_HSION; + while(!(RCC->CR & RCC_CR_HSIRDY)); + //PLL SYSCLK, HCLK, PCLK2 and PCLK1 configuration --------------------------- + //Enable HSE + RCC->CR |= ((u32)RCC_CR_HSEON); + + DELAY_xUs(5); + + if(SystemCoreClock > 96000000) { + RCC->APB1ENR |= RCC_APB1ENR_PWR; + PWR->CR &= ~(3 << 14); + PWR->CR |= 3 << 14; + } + //Wait till HSE is ready and if Time out is reached exit + while(1) { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + if(HSEStatus != 0) + break; + StartUpCounter++; + if(StartUpCounter >= (10 * HSE_STARTUP_TIMEOUT)) + return; + } + + if ((RCC->CR & RCC_CR_HSERDY) == RESET) { + //If HSE fails to start-up, the application will have wrong clock + //configuration. User can add here some code to deal with this error + HSEStatus = (u32)0x00; + return; + } + + HSEStatus = (u32)0x01; + DELAY_xUs(5); + + SystemCoreClock = SYSCLK_FREQ_XXMHz; + //Enable Prefetch Buffer + FLASH->ACR |= FLASH_ACR_PRFTBE; + //Flash 0 wait state ,bit0~2 + FLASH->ACR &= ~FLASH_ACR_LATENCY; + temp = (SystemCoreClock - 1) / 24000000; + FLASH->ACR |= (temp & FLASH_ACR_LATENCY); + RCC->CFGR &= (~RCC_CFGR_HPRE) & ( ~RCC_CFGR_PPRE1) & (~RCC_CFGR_PPRE2); + + //HCLK = AHB = FCLK = SYSCLK divided by 4 + RCC->CFGR |= (u32)RCC_CFGR_HPRE_DIV4; + + //PCLK2 = APB2 = HCLK divided by 1, APB2 is high APB CLK + RCC->CFGR |= (u32)RCC_CFGR_PPRE2_DIV1; + + if(SystemCoreClock > 72000000) { + //PCLK1 = APB1 = HCLK divided by 4, APB1 is low APB CLK + RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV4; + } + else if(SystemCoreClock > 36000000) { + //PCLK1 = APB1 = HCLK divided by 2, APB1 is low APB CLK + RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV2; + } + + AutoCalPllFactor(HSE_VALUE, SystemCoreClock, &plln, &pllm); + + RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ; + RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC ; + + tm = (((u32)pllm) & 0x07); + tn = (((u32)plln) & 0x7F); + + RCC->APB1ENR |= RCC_APB1ENR_PWR; + RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP)); + RCC->PLLCFGR |= ((tn << RCC_PLLCFGR_PLL_DN_Pos) | (tm << RCC_PLLCFGR_PLL_DP_Pos)); + //Enable PLL + RCC->CR |= RCC_CR_PLLON; + //Wait till PLL is ready + while((RCC->CR & RCC_CR_PLLRDY) == 0) { + __ASM ("nop") ;//__NOP(); + } + //Select PLL as system clock source + RCC->CFGR &= (u32)((u32)~(RCC_CFGR_SW)); + RCC->CFGR |= (u32)RCC_CFGR_SW_PLL; + + //Wait till PLL is used as system clock source + while ((RCC->CFGR & (u32)RCC_CFGR_SWS) != (u32)RCC_CFGR_SWS_PLL) { + __ASM ("nop") ;//__NOP(); + } + + DELAY_xUs(1); + // set HCLK = AHB = FCLK = SYSCLK divided by 2 + RCC->CFGR &= (~(RCC_CFGR_PPRE_0)); + DELAY_xUs(1); + + // set HCLK = AHB = FCLK = SYSCLK divided by 1 + RCC->CFGR &= (~(RCC_CFGR_PPRE_3)); + + DELAY_xUs(1); + +} +#elif defined SYSCLK_HSI_24MHz +void SetSysClockTo24_HSI(void) +{ + u8 temp = 0; + + RCC->CR |= RCC_CR_HSION; + + while(!(RCC->CR & RCC_CR_HSIRDY)); + FLASH->ACR = FLASH_ACR_PRFTBE; + + RCC->CFGR = RCC_CFGR_PPRE1_2; + // PLL configuration: = (HSI = 8M ) * (2+1)/(0+1) = 24 MHz + RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ; + RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC ; + + RCC->APB1ENR |= RCC_APB1ENR_PWR; + RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP)); + RCC->PLLCFGR |= ((0 << RCC_PLLCFGR_PLL_DN_Pos) | (2 << RCC_PLLCFGR_PLL_DP_Pos)); + + + RCC->CR |= RCC_CR_PLLON; + + while(!(RCC->CR & RCC_CR_PLLRDY)); + + RCC->CFGR &= ~RCC_CFGR_SW; + + RCC->CFGR |= RCC_CFGR_SW_PLL; + + while(temp != 0x02) { + temp = RCC->CFGR >> 2; + temp &= 0x03; + } +} + +#elif defined SYSCLK_HSI_36MHz +void SetSysClockTo36_HSI(void) +{ + u8 temp = 0; + + RCC->CR |= RCC_CR_HSION; + + while(!(RCC->CR & RCC_CR_HSIRDY)); + FLASH->ACR = FLASH_ACR_LATENCY_1 | FLASH_ACR_PRFTBE; + RCC->CFGR = RCC_CFGR_PPRE1_2; + // PLL configuration: = (HSI = 8M ) * (8+1)/(1+1) = 36 MHz + RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ; + RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC ; + + RCC->APB1ENR |= RCC_APB1ENR_PWR; + RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP)); + RCC->PLLCFGR |= ((1 << RCC_PLLCFGR_PLL_DN_Pos) | (8 << RCC_PLLCFGR_PLL_DP_Pos)); + + RCC->CR |= RCC_CR_PLLON; + + while(!(RCC->CR & RCC_CR_PLLRDY)); + + RCC->CFGR &= ~ RCC_CFGR_SW; + + RCC->CFGR |= RCC_CFGR_SW_PLL; + + while(temp != 0x02) { + temp = RCC->CFGR >> 2; + temp &= 0x03; + } +} + +#elif defined SYSCLK_HSI_48MHz +void SetSysClockTo48_HSI(void) +{ + u8 temp = 0; + + RCC->CR |= RCC_CR_HSION; + + while(!(RCC->CR & RCC_CR_HSIRDY)); + FLASH->ACR = FLASH_ACR_LATENCY_1 | FLASH_ACR_PRFTBE; + RCC->CFGR = RCC_CFGR_PPRE1_2; + + + + + + // PLL configuration: = (HSI = 8M ) * (5+1)/(0+1) = 36 MHz + RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ; + RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC ; + + RCC->APB1ENR |= RCC_APB1ENR_PWR; + RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP)); + RCC->PLLCFGR |= ((0 << RCC_PLLCFGR_PLL_DN_Pos) | (5 << RCC_PLLCFGR_PLL_DP_Pos)); + + RCC->CR |= RCC_CR_PLLON; + + while(!(RCC->CR & RCC_CR_PLLRDY)); + + RCC->CFGR &= ~RCC_CFGR_SW; + + RCC->CFGR |= RCC_CFGR_SW_PLL; + + while(temp != 0x02) { + temp = RCC->CFGR >> 2; + temp &= 0x03; + } +} +#elif defined SYSCLK_HSI_XXMHz + + +static void SetSysClockToXX_HSI(void) +{ + __IO u32 temp, tn, tm; + u8 plln, pllm; + + RCC->CR |= RCC_CR_HSION; + while(!(RCC->CR & RCC_CR_HSIRDY)); + + if(SystemCoreClock > 96000000) { + RCC->APB1ENR |= RCC_APB1ENR_PWR; + PWR->CR &= ~(3 << 14); + PWR->CR |= 3 << 14; + } + + + + SystemCoreClock = SYSCLK_HSI_XXMHz; + //Enable Prefetch Buffer + FLASH->ACR |= FLASH_ACR_PRFTBE; + //Flash 0 wait state ,bit0~2 + FLASH->ACR &= ~FLASH_ACR_LATENCY; + + temp = (SystemCoreClock - 1) / 24000000; + + FLASH->ACR |= (temp & FLASH_ACR_LATENCY); + + + RCC->CFGR &= (~RCC_CFGR_HPRE) & ( ~RCC_CFGR_PPRE1) & (~RCC_CFGR_PPRE2); + //HCLK = AHB = FCLK = SYSCLK divided by 4 + RCC->CFGR |= (u32)RCC_CFGR_HPRE_DIV4; + + //PCLK2 = APB2 = HCLK divided by 1, APB2 is high APB CLK + RCC->CFGR |= (u32)RCC_CFGR_PPRE2_DIV1; + + if(SystemCoreClock > 72000000) { + //PCLK1 = APB1 = HCLK divided by 4, APB1 is low APB CLK + RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV4; + } + else if(SystemCoreClock > 36000000) { + //PCLK1 = APB1 = HCLK divided by 2, APB1 is low APB CLK + RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV2; + } + + + + AutoCalPllFactor(HSI_VALUE_PLL_ON, SystemCoreClock, &plln, &pllm); + + RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ; + RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC); + + tm = (((u32)pllm) & 0x07); + tn = (((u32)plln) & 0x7F); + + RCC->APB1ENR |= RCC_APB1ENR_PWR; + RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP)); + RCC->PLLCFGR |= ((tn << RCC_PLLCFGR_PLL_DN_Pos) | (tm << RCC_PLLCFGR_PLL_DP_Pos)); + //Enable PLL + RCC->CR |= RCC_CR_PLLON; + //Wait till PLL is ready + while((RCC->CR & RCC_CR_PLLRDY) == 0) { + __ASM ("nop") ;//__NOP(); + } + //Select PLL as system clock source + RCC->CFGR &= (u32)((u32)~(RCC_CFGR_SW)); + RCC->CFGR |= (u32)RCC_CFGR_SW_PLL; + + //Wait till PLL is used as system clock source + while ((RCC->CFGR & (u32)RCC_CFGR_SWS) != (u32)RCC_CFGR_SWS_PLL) { + __ASM ("nop") ;//__NOP(); + } + + DELAY_xUs(1); + // set HCLK = AHB = FCLK = SYSCLK divided by 2 + RCC->CFGR &= (~(RCC_CFGR_PPRE_0)); + DELAY_xUs(1); + + // set HCLK = AHB = FCLK = SYSCLK divided by 1 + RCC->CFGR &= (~(RCC_CFGR_PPRE_3)); + + DELAY_xUs(1); + +} + +#endif + + + +/// @} + + + +/// @} + + + +/// @} + + + diff --git a/src/portable/mm32/dcd_mm32f327x_otg.c b/src/portable/mm32/dcd_mm32f327x_otg.c new file mode 100644 index 000000000..914bbb38c --- /dev/null +++ b/src/portable/mm32/dcd_mm32f327x_otg.c @@ -0,0 +1,462 @@ +//////////////////////////////////////////////////////////////////////////////// +/// @file dcd_mm32f327x_otg.c +/// @author SE TEAM +/// @brief tinyusb driver. +//////////////////////////////////////////////////////////////////////////////// +/// @attention +/// +/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE +/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE +/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR +/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH +/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN +/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. +/// +///

© COPYRIGHT MINDMOTION

+//////////////////////////////////////////////////////////////////////////////// + +#include "tusb_option.h" +#include "reg_usb_otg_fs.h" +#include "mm32_device.h" +#include "hal_conf.h" + +#if TUSB_OPT_DEVICE_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_MM32F327X ) + +#include "device/dcd.h" + +//--------------------------------------------------------------------+ +// MACRO TYPEDEF CONSTANT ENUM DECLARATION +//--------------------------------------------------------------------+ + +enum { + TOK_PID_OUT = 0x1u, + TOK_PID_IN = 0x9u, + TOK_PID_SETUP = 0xDu, +}; + +typedef struct TU_ATTR_PACKED +{ + union { + uint32_t head; + struct { + union { + struct { + uint16_t : 2; + uint16_t tok_pid : 4; + uint16_t data : 1; + uint16_t own : 1; + uint16_t : 8; + }; + struct { + uint16_t : 2; + uint16_t bdt_stall: 1; + uint16_t dts : 1; + uint16_t ninc : 1; + uint16_t keep : 1; + uint16_t : 10; + }; + }; + uint16_t bc : 10; + uint16_t : 6; + }; + }; + uint8_t *addr; +}buffer_descriptor_t; + +TU_VERIFY_STATIC( sizeof(buffer_descriptor_t) == 8, "size is not correct" ); + +typedef struct TU_ATTR_PACKED +{ + union { + uint32_t state; + struct { + uint32_t max_packet_size :11; + uint32_t : 5; + uint32_t odd : 1; + uint32_t :15; + }; + }; + uint16_t length; + uint16_t remaining; +}endpoint_state_t; + +TU_VERIFY_STATIC( sizeof(endpoint_state_t) == 8, "size is not correct" ); + +typedef struct +{ + union { + /* [#EP][OUT,IN][EVEN,ODD] */ + buffer_descriptor_t bdt[16][2][2]; + uint16_t bda[512]; + }; + TU_ATTR_ALIGNED(4) union { + endpoint_state_t endpoint[16][2]; + endpoint_state_t endpoint_unified[16 * 2]; + }; + uint8_t setup_packet[8]; + uint8_t addr; +}dcd_data_t; + +//--------------------------------------------------------------------+ +// INTERNAL OBJECT & FUNCTION DECLARATION +//--------------------------------------------------------------------+ +// BDT(Buffer Descriptor Table) must be 256-byte aligned +CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(512) static dcd_data_t _dcd; + +TU_VERIFY_STATIC( sizeof(_dcd.bdt) == 512, "size is not correct" ); + +static void prepare_next_setup_packet(uint8_t rhport) +{ + const unsigned out_odd = _dcd.endpoint[0][0].odd; + const unsigned in_odd = _dcd.endpoint[0][1].odd; + if (_dcd.bdt[0][0][out_odd].own) { + TU_LOG1("DCD fail to prepare the next SETUP %d %d\r\n", out_odd, in_odd); + return; + } + _dcd.bdt[0][0][out_odd].data = 0; + _dcd.bdt[0][0][out_odd ^ 1].data = 1; + _dcd.bdt[0][1][in_odd].data = 1; + _dcd.bdt[0][1][in_odd ^ 1].data = 0; + dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_OUT), + _dcd.setup_packet, sizeof(_dcd.setup_packet)); +} + +static void process_stall(uint8_t rhport) +{ + if (USB_OTG_FS->EP_CTL[0] & USB_ENDPT_EPSTALL_MASK) { + /* clear stall condition of the control pipe */ + prepare_next_setup_packet(rhport); + USB_OTG_FS->EP_CTL[0] &= ~USB_ENDPT_EPSTALL_MASK; + } +} + +static void process_tokdne(uint8_t rhport) +{ + const unsigned s = USB_OTG_FS->STAT; + USB_OTG_FS->INT_STAT = USB_ISTAT_TOKDNE_MASK; /* fetch the next token if received */ + buffer_descriptor_t *bd = (buffer_descriptor_t *)&_dcd.bda[s]; + endpoint_state_t *ep = &_dcd.endpoint_unified[s >> 3]; + unsigned odd = (s & USB_STAT_ODD_MASK) ? 1 : 0; + + /* fetch pid before discarded by the next steps */ + const unsigned pid = bd->tok_pid; + /* reset values for a next transfer */ + bd->bdt_stall = 0; + bd->dts = 1; + bd->ninc = 0; + bd->keep = 0; + /* update the odd variable to prepare for the next transfer */ + ep->odd = odd ^ 1; + if (pid == TOK_PID_SETUP) { + dcd_event_setup_received(rhport, bd->addr, true); + USB_OTG_FS->CTL &= ~USB_CTL_TXSUSPENDTOKENBUSY_MASK; + return; + } + if (s >> 4) { + TU_LOG1("TKDNE %x\r\n", s); + } + + const unsigned bc = bd->bc; + const unsigned remaining = ep->remaining - bc; + if (remaining && bc == ep->max_packet_size) { + /* continue the transferring consecutive data */ + ep->remaining = remaining; + const int next_remaining = remaining - ep->max_packet_size; + if (next_remaining > 0) { + /* prepare to the after next transfer */ + bd->addr += ep->max_packet_size * 2; + bd->bc = next_remaining > ep->max_packet_size ? ep->max_packet_size: next_remaining; + __DSB(); + bd->own = 1; /* the own bit must set after addr */ + } + return; + } + const unsigned length = ep->length; + dcd_event_xfer_complete(rhport, + ((s & USB_STAT_TX_MASK) << 4) | (s >> USB_STAT_ENDP_SHIFT), + length - remaining, XFER_RESULT_SUCCESS, true); + if (0 == (s & USB_STAT_ENDP_MASK) && 0 == length) { + /* After completion a ZLP of control transfer, + * it prepares for the next steup transfer. */ + if (_dcd.addr) { + /* When the transfer was the SetAddress, + * the device address should be updated here. */ + USB_OTG_FS->ADDR = _dcd.addr; + _dcd.addr = 0; + } + prepare_next_setup_packet(rhport); + } +} + +static void process_bus_reset(uint8_t rhport) +{ + USB_OTG_FS->CTL |= USB_CTL_ODDRST_MASK; + USB_OTG_FS->ADDR = 0; + USB_OTG_FS->INT_ENB = (USB_OTG_FS->INT_ENB & ~USB_INTEN_RESUMEEN_MASK) | USB_INTEN_SLEEPEN_MASK; + + USB_OTG_FS->EP_CTL[0] = USB_ENDPT_EPHSHK_MASK | USB_ENDPT_EPRXEN_MASK | USB_ENDPT_EPTXEN_MASK; + for (unsigned i = 1; i < 16; ++i) { + USB_OTG_FS->EP_CTL[i] = 0; + } + buffer_descriptor_t *bd = _dcd.bdt[0][0]; + for (unsigned i = 0; i < sizeof(_dcd.bdt)/sizeof(*bd); ++i, ++bd) { + bd->head = 0; + } + const endpoint_state_t ep0 = { + .max_packet_size = CFG_TUD_ENDPOINT0_SIZE, + .odd = 0, + .length = 0, + .remaining = 0, + }; + _dcd.endpoint[0][0] = ep0; + _dcd.endpoint[0][1] = ep0; + tu_memclr(_dcd.endpoint[1], sizeof(_dcd.endpoint) - sizeof(_dcd.endpoint[0])); + _dcd.addr = 0; + prepare_next_setup_packet(rhport); + USB_OTG_FS->CTL &= ~USB_CTL_ODDRST_MASK; + dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true); +} + +static void process_bus_inactive(uint8_t rhport) +{ + (void) rhport; + const unsigned inten = USB_OTG_FS->INT_ENB; + USB_OTG_FS->INT_ENB = (inten & ~USB_INTEN_SLEEPEN_MASK) | USB_INTEN_RESUMEEN_MASK; + dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); +} + +static void process_bus_active(uint8_t rhport) +{ + (void) rhport; + const unsigned inten = USB_OTG_FS->INT_ENB; + USB_OTG_FS->INT_ENB = (inten & ~USB_INTEN_RESUMEEN_MASK) | USB_INTEN_SLEEPEN_MASK; + dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true); +} + +/*------------------------------------------------------------------*/ +/* Device API + *------------------------------------------------------------------*/ +void dcd_init(uint8_t rhport) +{ + (void) rhport; + + tu_memclr(&_dcd, sizeof(_dcd)); + USB_OTG_FS->BDT_PAGE_01 = (uint8_t)((uintptr_t)_dcd.bdt >> 8); + USB_OTG_FS->BDT_PAGE_02 = (uint8_t)((uintptr_t)_dcd.bdt >> 16); + USB_OTG_FS->BDT_PAGE_03 = (uint8_t)((uintptr_t)_dcd.bdt >> 24); + + dcd_connect(rhport); + NVIC_ClearPendingIRQ(USB_FS_IRQn); +} +#define USB_DEVICE_INTERRUPT_PRIORITY (3U) +void dcd_int_enable(uint8_t rhport) +{ + uint8_t irqNumber; + irqNumber = USB_FS_IRQn; + (void) rhport; + USB_OTG_FS->INT_ENB = USB_INTEN_USBRSTEN_MASK | USB_INTEN_TOKDNEEN_MASK | + USB_INTEN_SLEEPEN_MASK | USB_INTEN_ERROREN_MASK | USB_INTEN_STALLEN_MASK; + NVIC_SetPriority((IRQn_Type)irqNumber, USB_DEVICE_INTERRUPT_PRIORITY); + NVIC_EnableIRQ(USB_FS_IRQn); +} + +void dcd_int_disable(uint8_t rhport) +{ + (void) rhport; + NVIC_DisableIRQ(USB_FS_IRQn); + USB_OTG_FS->INT_ENB = 0; +} + +void dcd_set_address(uint8_t rhport, uint8_t dev_addr) +{ + (void) rhport; + _dcd.addr = dev_addr & 0x7F; + /* Response with status first before changing device address */ + dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0); +} +extern u32 SystemCoreClock ; +void dcd_remote_wakeup(uint8_t rhport) +{ + (void) rhport; + unsigned cnt = SystemCoreClock / 100; + USB_OTG_FS->CTL |= USB_CTL_RESUME_MASK; + while (cnt--) __NOP(); + USB_OTG_FS->CTL &= ~USB_CTL_RESUME_MASK; +} + +void dcd_connect(uint8_t rhport) +{ + (void) rhport; + USB_OTG_FS->CTL |= USB_CTL_USBENSOFEN_MASK; +} + +void dcd_disconnect(uint8_t rhport) +{ + (void) rhport; + USB_OTG_FS->CTL = 0; +} + +//--------------------------------------------------------------------+ +// Endpoint API +//--------------------------------------------------------------------+ +bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) +{ + (void) rhport; + + const unsigned ep_addr = ep_desc->bEndpointAddress; + const unsigned epn = ep_addr & 0xFu; + const unsigned dir = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT; + const unsigned xfer = ep_desc->bmAttributes.xfer; + endpoint_state_t *ep = &_dcd.endpoint[epn][dir]; + const unsigned odd = ep->odd; + buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][0]; + + /* No support for control transfer */ + TU_ASSERT(epn && (xfer != TUSB_XFER_CONTROL)); + + ep->max_packet_size = ep_desc->wMaxPacketSize.size; + unsigned val = USB_ENDPT_EPCTLDIS_MASK; + val |= (xfer != TUSB_XFER_ISOCHRONOUS) ? USB_ENDPT_EPHSHK_MASK: 0; + val |= dir ? USB_ENDPT_EPTXEN_MASK : USB_ENDPT_EPRXEN_MASK; + USB_OTG_FS->EP_CTL[epn] |= val; + + if (xfer != TUSB_XFER_ISOCHRONOUS) { + bd[odd].dts = 1; + bd[odd].data = 0; + bd[odd ^ 1].dts = 1; + bd[odd ^ 1].data = 1; + } + + return true; +} + +void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) +{ + (void) rhport; + + const unsigned epn = ep_addr & 0xFu; + const unsigned dir = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT; + endpoint_state_t *ep = &_dcd.endpoint[epn][dir]; + buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][0]; + const unsigned msk = dir ? USB_ENDPT_EPTXEN_MASK : USB_ENDPT_EPRXEN_MASK; + USB_OTG_FS->EP_CTL[epn] &= ~msk; + ep->max_packet_size = 0; + ep->length = 0; + ep->remaining = 0; + bd->head = 0; +} + +bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) +{ + (void) rhport; + NVIC_DisableIRQ(USB_FS_IRQn); + const unsigned epn = ep_addr & 0xFu; + const unsigned dir = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT; + endpoint_state_t *ep = &_dcd.endpoint[epn][dir]; + buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][ep->odd]; + + if (bd->own) { + TU_LOG1("DCD XFER fail %x %d %lx %lx\r\n", ep_addr, total_bytes, ep->state, bd->head); + return false; /* The last transfer has not completed */ + } + ep->length = total_bytes; + ep->remaining = total_bytes; + + const unsigned mps = ep->max_packet_size; + if (total_bytes > mps) { + buffer_descriptor_t *next = ep->odd ? bd - 1: bd + 1; + /* When total_bytes is greater than the max packet size, + * it prepares to the next transfer to avoid NAK in advance. */ + next->bc = total_bytes >= 2 * mps ? mps: total_bytes - mps; + next->addr = buffer + mps; + next->own = 1; + } + bd->bc = total_bytes >= mps ? mps: total_bytes; + bd->addr = buffer; + __DSB(); + bd->own = 1; /* the own bit must set after addr */ + NVIC_EnableIRQ(USB_FS_IRQn); + return true; +} + +void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) +{ + (void) rhport; + const unsigned epn = ep_addr & 0xFu; + if (0 == epn) { + USB_OTG_FS->EP_CTL[epn] |= USB_ENDPT_EPSTALL_MASK; + } else { + const unsigned dir = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT; + buffer_descriptor_t *bd = _dcd.bdt[epn][dir]; + bd[0].bdt_stall = 1; + bd[1].bdt_stall = 1; + } +} + +void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) +{ + (void) rhport; + const unsigned epn = ep_addr & 0xFu; + const unsigned dir = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT; + const unsigned odd = _dcd.endpoint[epn][dir].odd; + buffer_descriptor_t *bd = _dcd.bdt[epn][dir]; + + bd[odd ^ 1].own = 0; + bd[odd ^ 1].data = 1; + bd[odd ^ 1].bdt_stall = 0; + bd[odd].own = 0; + bd[odd].data = 0; + bd[odd].bdt_stall = 0; +} + +//--------------------------------------------------------------------+ +// ISR +//--------------------------------------------------------------------+ +void dcd_int_handler(uint8_t rhport) +{ + (void) rhport; + + uint32_t is = USB_OTG_FS->INT_STAT; + uint32_t msk = USB_OTG_FS->INT_ENB; + USB_OTG_FS->INT_STAT = is & ~msk; + is &= msk; + if (is & USB_ISTAT_ERROR_MASK) { + /* TODO: */ + uint32_t es = USB_OTG_FS->ERR_STAT; + USB_OTG_FS->ERR_STAT = es; + USB_OTG_FS->INT_STAT = is; /* discard any pending events */ + return; + } + + if (is & USB_ISTAT_USBRST_MASK) { + USB_OTG_FS->INT_STAT = is; /* discard any pending events */ + process_bus_reset(rhport); + return; + } + if (is & USB_ISTAT_SLEEP_MASK) { + USB_OTG_FS->INT_STAT = USB_ISTAT_SLEEP_MASK; + process_bus_inactive(rhport); + return; + } + if (is & USB_ISTAT_RESUME_MASK) { + USB_OTG_FS->INT_STAT = USB_ISTAT_RESUME_MASK; + process_bus_active(rhport); + return; + } + if (is & USB_ISTAT_SOFTOK_MASK) { + USB_OTG_FS->INT_STAT = USB_ISTAT_SOFTOK_MASK; + dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true); + return; + } + if (is & USB_ISTAT_STALL_MASK) { + USB_OTG_FS->INT_STAT = USB_ISTAT_STALL_MASK; + process_stall(rhport); + return; + } + if (is & USB_ISTAT_TOKDNE_MASK) { + process_tokdne(rhport); + return; + } +} + +#endif -- cgit v1.3.1 From 373b977cc3b0bbb0144429d52d4ad6132b8319e2 Mon Sep 17 00:00:00 2001 From: zhangslice <1304224508@qq.com> Date: Wed, 2 Jun 2021 09:54:21 +0800 Subject: add keil projrct Signed-off-by: zhangslice <1304224508@qq.com> --- tinyusb_keil.zip | Bin 0 -> 1001190 bytes 1 file changed, 0 insertions(+), 0 deletions(-) create mode 100644 tinyusb_keil.zip diff --git a/tinyusb_keil.zip b/tinyusb_keil.zip new file mode 100644 index 000000000..6b178fcfc Binary files /dev/null and b/tinyusb_keil.zip differ -- cgit v1.3.1 From b8ac5f12872a97ccb1fa81fdc028ab91947fb217 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 2 Jun 2021 13:32:00 +0700 Subject: add mindmotion mm32sdk as submodule remove the local copy of mm32 --- .../mm32f327x/CMSIS/IAR_Core/arm_common_tables.h | 121 - .../mm32f327x/CMSIS/IAR_Core/arm_const_structs.h | 66 - hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_math.h | 7122 -------------------- hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_armcc.h | 796 --- .../mm32/mm32f327x/CMSIS/IAR_Core/cmsis_armclang.h | 1735 ----- .../mm32/mm32f327x/CMSIS/IAR_Core/cmsis_compiler.h | 231 - hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_gcc.h | 1900 ------ .../mm32/mm32f327x/CMSIS/IAR_Core/core_armv8mbl.h | 1813 ----- .../mm32/mm32f327x/CMSIS/IAR_Core/core_armv8mml.h | 2821 -------- hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm0.h | 850 --- .../mm32/mm32f327x/CMSIS/IAR_Core/core_cm0plus.h | 975 --- hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm23.h | 1813 ----- hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm3.h | 1880 ------ hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm33.h | 2821 -------- hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm4.h | 2061 ------ hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm7.h | 2592 ------- hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_sc000.h | 976 --- hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_sc300.h | 1851 ----- hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/tz_context.h | 69 - .../mm32f327x/CMSIS/KEIL_Core/arm_common_tables.h | 121 - .../mm32f327x/CMSIS/KEIL_Core/arm_const_structs.h | 66 - hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_math.h | 7122 -------------------- .../mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_armcc.h | 796 --- .../mm32f327x/CMSIS/KEIL_Core/cmsis_armclang.h | 1735 ----- .../mm32f327x/CMSIS/KEIL_Core/cmsis_compiler.h | 231 - hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_gcc.h | 1900 ------ .../mm32/mm32f327x/CMSIS/KEIL_Core/core_armv8mbl.h | 1813 ----- .../mm32/mm32f327x/CMSIS/KEIL_Core/core_armv8mml.h | 2821 -------- hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm0.h | 850 --- .../mm32/mm32f327x/CMSIS/KEIL_Core/core_cm0plus.h | 975 --- hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm23.h | 1813 ----- hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm3.h | 1880 ------ hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm33.h | 2821 -------- hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm4.h | 2061 ------ hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm7.h | 2592 ------- hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_sc000.h | 976 --- hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_sc300.h | 1851 ----- hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/tz_context.h | 69 - .../mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/dtype.h | 33 - .../mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_adc.h | 341 - .../mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_bkp.h | 130 - .../mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_can.h | 340 - .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_comp.h | 228 - .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_conf.h | 62 - .../mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crc.h | 84 - .../mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crs.h | 46 - .../mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dac.h | 166 - .../mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dbg.h | 72 - .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_device.h | 41 - .../mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dma.h | 306 - .../mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_eth.h | 729 -- .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_eth_conf.h | 68 - .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_exti.h | 181 - .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_flash.h | 230 - .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_fsmc.h | 147 - .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_gpio.h | 198 - .../mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_i2c.h | 255 - .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_iwdg.h | 130 - .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_misc.h | 128 - .../mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_pwr.h | 156 - .../mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rcc.h | 329 - .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_redefine.h | 102 - .../mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rtc.h | 114 - .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_sdio.h | 503 -- .../mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_spi.h | 351 - .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_syscfg.h | 83 - .../mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_tim.h | 755 --- .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_uart.h | 211 - .../mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_uid.h | 71 - .../mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_ver.h | 89 - .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_wwdg.h | 90 - .../mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_adc.c | 563 -- .../mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_bkp.c | 231 - .../mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_can.c | 696 -- .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_comp.c | 226 - .../mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_crc.c | 108 - .../mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_crs.c | 43 - .../mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dac.c | 184 - .../mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dbg.c | 53 - .../mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dma.c | 319 - .../mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_eth.c | 836 --- .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_exti.c | 222 - .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_flash.c | 548 -- .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_fsmc.c | 124 - .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_gpio.c | 344 - .../mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_i2c.c | 526 -- .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_iwdg.c | 208 - .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_misc.c | 147 - .../mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_pwr.c | 215 - .../mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rcc.c | 995 --- .../mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rtc.c | 234 - .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_sdio.c | 527 -- .../mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_spi.c | 648 -- .../mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_tim.c | 1875 ------ .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_uart.c | 502 -- .../mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uid.c | 55 - .../mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_ver.c | 131 - .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_wwdg.c | 147 - .../mm32/mm32f327x/MM32F327x/Include/mm32_device.h | 23 - hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_reg.h | 71 - .../MM32F327x/Include/mm32_reg_redefine_v1.h | 1175 ---- hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_adc.h | 953 --- hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_bkp.h | 147 - hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_can.h | 532 -- .../mm32/mm32f327x/MM32F327x/Include/reg_common.h | 643 -- hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_comp.h | 228 - hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_crc.h | 102 - hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_crs.h | 152 - hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dac.h | 247 - hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dbg.h | 113 - hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dma.h | 325 - hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_eth.h | 730 -- hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_exti.h | 544 -- .../mm32/mm32f327x/MM32F327x/Include/reg_flash.h | 290 - hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_fsmc.h | 194 - hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_gpio.h | 706 -- hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_i2c.h | 635 -- hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_iwdg.h | 125 - hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_pwm.h | 72 - hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_pwr.h | 219 - hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_rcc.h | 654 -- hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_rtc.h | 203 - hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_sdio.h | 391 -- hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_spi.h | 359 - .../mm32/mm32f327x/MM32F327x/Include/reg_syscfg.h | 299 - hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_tim.h | 681 -- hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_uart.h | 362 - .../mm32f327x/MM32F327x/Include/reg_usb_otg_fs.h | 923 --- hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_wwdg.h | 133 - hw/mcu/mm32/mm32f327x/MM32F327x/Include/types.h | 105 - .../Source/GCC_StartAsm/startup_mm32m3ux_u_gcc.S | 440 -- .../mm32f327x/MM32F327x/Source/system_mm32f327x.c | 866 --- 132 files changed, 96104 deletions(-) delete mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_common_tables.h delete mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_const_structs.h delete mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_math.h delete mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_armcc.h delete mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_armclang.h delete mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_compiler.h delete mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_gcc.h delete mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_armv8mbl.h delete mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_armv8mml.h delete mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm0.h delete mode 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--git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_common_tables.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_common_tables.h deleted file mode 100644 index dfea7460e..000000000 --- a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_common_tables.h +++ /dev/null @@ -1,121 +0,0 @@ -/* ---------------------------------------------------------------------- - * Project: CMSIS DSP Library - * Title: arm_common_tables.h - * Description: Extern declaration for common tables - * - * $Date: 27. January 2017 - * $Revision: V.1.5.1 - * - * Target Processor: Cortex-M cores - * -------------------------------------------------------------------- */ -/* - * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef _ARM_COMMON_TABLES_H -#define _ARM_COMMON_TABLES_H - -#include "arm_math.h" - -extern const uint16_t armBitRevTable[1024]; -extern const q15_t armRecipTableQ15[64]; -extern const q31_t armRecipTableQ31[64]; -extern const float32_t twiddleCoef_16[32]; -extern const float32_t twiddleCoef_32[64]; -extern const float32_t twiddleCoef_64[128]; -extern const float32_t twiddleCoef_128[256]; -extern const float32_t twiddleCoef_256[512]; -extern const float32_t twiddleCoef_512[1024]; -extern const float32_t twiddleCoef_1024[2048]; -extern const float32_t twiddleCoef_2048[4096]; -extern const float32_t twiddleCoef_4096[8192]; -#define twiddleCoef twiddleCoef_4096 -extern const q31_t twiddleCoef_16_q31[24]; -extern const q31_t twiddleCoef_32_q31[48]; -extern const q31_t twiddleCoef_64_q31[96]; -extern const q31_t twiddleCoef_128_q31[192]; -extern const q31_t twiddleCoef_256_q31[384]; -extern const q31_t twiddleCoef_512_q31[768]; -extern const q31_t twiddleCoef_1024_q31[1536]; -extern const q31_t twiddleCoef_2048_q31[3072]; -extern const q31_t twiddleCoef_4096_q31[6144]; -extern const q15_t twiddleCoef_16_q15[24]; -extern const q15_t twiddleCoef_32_q15[48]; -extern const q15_t twiddleCoef_64_q15[96]; -extern const q15_t twiddleCoef_128_q15[192]; -extern const q15_t twiddleCoef_256_q15[384]; -extern const q15_t twiddleCoef_512_q15[768]; -extern const q15_t twiddleCoef_1024_q15[1536]; -extern const q15_t twiddleCoef_2048_q15[3072]; -extern const q15_t twiddleCoef_4096_q15[6144]; -extern const float32_t twiddleCoef_rfft_32[32]; -extern const float32_t twiddleCoef_rfft_64[64]; -extern const float32_t twiddleCoef_rfft_128[128]; -extern const float32_t twiddleCoef_rfft_256[256]; -extern const float32_t twiddleCoef_rfft_512[512]; -extern const float32_t twiddleCoef_rfft_1024[1024]; -extern const float32_t twiddleCoef_rfft_2048[2048]; -extern const float32_t twiddleCoef_rfft_4096[4096]; - -/* floating-point bit reversal tables */ -#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20) -#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48) -#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56) -#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) -#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) -#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) -#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800) -#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808) -#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH]; - -/* fixed-point bit reversal tables */ -#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12) -#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24) -#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56) -#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112) -#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240) -#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480) -#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992) -#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) -#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; - -/* Tables for Fast Math Sine and Cosine */ -extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; -extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; -extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; - -#endif /* ARM_COMMON_TABLES_H */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_const_structs.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_const_structs.h deleted file mode 100644 index 84ffe8b85..000000000 --- a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_const_structs.h +++ /dev/null @@ -1,66 +0,0 @@ -/* ---------------------------------------------------------------------- - * Project: CMSIS DSP Library - * Title: arm_const_structs.h - * Description: Constant structs that are initialized for user convenience. - * For example, some can be given as arguments to the arm_cfft_f32() function. - * - * $Date: 27. January 2017 - * $Revision: V.1.5.1 - * - * Target Processor: Cortex-M cores - * -------------------------------------------------------------------- */ -/* - * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef _ARM_CONST_STRUCTS_H -#define _ARM_CONST_STRUCTS_H - -#include "arm_math.h" -#include "arm_common_tables.h" - -extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; -extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; -extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; -extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; -extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; -extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; -extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; -extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; -extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; - -extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; -extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; -extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; -extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; -extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; -extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; -extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; -extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; -extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; - -extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; -extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; -extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; -extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; -extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; -extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; -extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; -extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; -extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; - -#endif diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_math.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_math.h deleted file mode 100644 index 9d678052b..000000000 --- a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_math.h +++ /dev/null @@ -1,7122 +0,0 @@ -/* ---------------------------------------------------------------------- - * Project: CMSIS DSP Library - * Title: arm_math.h - * Description: Public header file for CMSIS DSP Library - * - * $Date: 27. January 2017 - * $Revision: V.1.5.1 - * - * Target Processor: Cortex-M cores - * -------------------------------------------------------------------- */ -/* - * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/** - \mainpage CMSIS DSP Software Library - * - * Introduction - * ------------ - * - * This user manual describes the CMSIS DSP software library, - * a suite of common signal processing functions for use on Cortex-M processor based devices. - * - * The library is divided into a number of functions each covering a specific category: - * - Basic math functions - * - Fast math functions - * - Complex math functions - * - Filters - * - Matrix functions - * - Transforms - * - Motor control functions - * - Statistical functions - * - Support functions - * - Interpolation functions - * - * The library has separate functions for operating on 8-bit integers, 16-bit integers, - * 32-bit integer and 32-bit floating-point values. - * - * Using the Library - * ------------ - * - * The library installer contains prebuilt versions of the libraries in the Lib folder. - * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit) - * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit) - * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit) - * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on) - * - arm_cortexM7l_math.lib (Cortex-M7, Little endian) - * - arm_cortexM7b_math.lib (Cortex-M7, Big endian) - * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit) - * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit) - * - arm_cortexM4l_math.lib (Cortex-M4, Little endian) - * - arm_cortexM4b_math.lib (Cortex-M4, Big endian) - * - arm_cortexM3l_math.lib (Cortex-M3, Little endian) - * - arm_cortexM3b_math.lib (Cortex-M3, Big endian) - * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian) - * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian) - * - arm_ARMv8MBLl_math.lib (ARMv8M Baseline, Little endian) - * - arm_ARMv8MMLl_math.lib (ARMv8M Mainline, Little endian) - * - arm_ARMv8MMLlfsp_math.lib (ARMv8M Mainline, Little endian, Single Precision Floating Point Unit) - * - arm_ARMv8MMLld_math.lib (ARMv8M Mainline, Little endian, DSP instructions) - * - arm_ARMv8MMLldfsp_math.lib (ARMv8M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit) - * - * The library functions are declared in the public file arm_math.h which is placed in the Include folder. - * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single - * public header file arm_math.h for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. - * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or - * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. - * For ARMv8M cores define pre processor MACRO ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML. - * Set Pre processor MACRO __DSP_PRESENT if ARMv8M Mainline core supports DSP instructions. - * - * - * Examples - * -------- - * - * The library ships with a number of examples which demonstrate how to use the library functions. - * - * Toolchain Support - * ------------ - * - * The library has been developed and tested with MDK-ARM version 5.14.0.0 - * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. - * - * Building the Library - * ------------ - * - * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. - * - arm_cortexM_math.uvprojx - * - * - * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. - * - * Pre-processor Macros - * ------------ - * - * Each library project have differant pre-processor macros. - * - * - UNALIGNED_SUPPORT_DISABLE: - * - * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access - * - * - ARM_MATH_BIG_ENDIAN: - * - * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. - * - * - ARM_MATH_MATRIX_CHECK: - * - * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices - * - * - ARM_MATH_ROUNDING: - * - * Define macro ARM_MATH_ROUNDING for rounding on support functions - * - * - ARM_MATH_CMx: - * - * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target - * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and - * ARM_MATH_CM7 for building the library on cortex-M7. - * - * - ARM_MATH_ARMV8MxL: - * - * Define macro ARM_MATH_ARMV8MBL for building the library on ARMv8M Baseline target, ARM_MATH_ARMV8MBL for building library - * on ARMv8M Mainline target. - * - * - __FPU_PRESENT: - * - * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries. - * - * - __DSP_PRESENT: - * - * Initialize macro __DSP_PRESENT = 1 when ARMv8M Mainline core supports DSP instructions. - * - *
- * CMSIS-DSP in ARM::CMSIS Pack - * ----------------------------- - * - * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: - * |File/Folder |Content | - * |------------------------------|------------------------------------------------------------------------| - * |\b CMSIS\\Documentation\\DSP | This documentation | - * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | - * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | - * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | - * - *
- * Revision History of CMSIS-DSP - * ------------ - * Please refer to \ref ChangeLog_pg. - * - * Copyright Notice - * ------------ - * - * Copyright (C) 2010-2015 ARM Limited. All rights reserved. - */ - - -/** - * @defgroup groupMath Basic Math Functions - */ - -/** - * @defgroup groupFastMath Fast Math Functions - * This set of functions provides a fast approximation to sine, cosine, and square root. - * As compared to most of the other functions in the CMSIS math library, the fast math functions - * operate on individual values and not arrays. - * There are separate functions for Q15, Q31, and floating-point data. - * - */ - -/** - * @defgroup groupCmplxMath Complex Math Functions - * This set of functions operates on complex data vectors. - * The data in the complex arrays is stored in an interleaved fashion - * (real, imag, real, imag, ...). - * In the API functions, the number of samples in a complex array refers - * to the number of complex values; the array contains twice this number of - * real values. - */ - -/** - * @defgroup groupFilters Filtering Functions - */ - -/** - * @defgroup groupMatrix Matrix Functions - * - * This set of functions provides basic matrix math operations. - * The functions operate on matrix data structures. For example, - * the type - * definition for the floating-point matrix structure is shown - * below: - * 
- *     typedef struct
- *     {
- *       uint16_t numRows;     // number of rows of the matrix.
- *       uint16_t numCols;     // number of columns of the matrix.
- *       float32_t *pData;     // points to the data of the matrix.
- *     } arm_matrix_instance_f32;
- *
- * There are similar definitions for Q15 and Q31 data types. - * - * The structure specifies the size of the matrix and then points to - * an array of data. The array is of size numRows X numCols - * and the values are arranged in row order. That is, the - * matrix element (i, j) is stored at: - * 
- *     pData[i*numCols + j]
- *
- * - * \par Init Functions - * There is an associated initialization function for each type of matrix - * data structure. - * The initialization function sets the values of the internal structure fields. - * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() - * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. - * - * \par - * Use of the initialization function is optional. However, if initialization function is used - * then the instance structure cannot be placed into a const data section. - * To place the instance structure in a const data - * section, manually initialize the data structure. For example: - * 
- * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
- *
- * where nRows specifies the number of rows, nColumns - * specifies the number of columns, and pData points to the - * data array. - * - * \par Size Checking - * By default all of the matrix functions perform size checking on the input and - * output matrices. For example, the matrix addition function verifies that the - * two input matrices and the output matrix all have the same number of rows and - * columns. If the size check fails the functions return: - * 
- *     ARM_MATH_SIZE_MISMATCH
- *
- * Otherwise the functions return - * 
- *     ARM_MATH_SUCCESS
- *
- * There is some overhead associated with this matrix size checking. - * The matrix size checking is enabled via the \#define - * 
- *     ARM_MATH_MATRIX_CHECK
- *
- * within the library project settings. By default this macro is defined - * and size checking is enabled. By changing the project settings and - * undefining this macro size checking is eliminated and the functions - * run a bit faster. With size checking disabled the functions always - * return ARM_MATH_SUCCESS. - */ - -/** - * @defgroup groupTransforms Transform Functions - */ - -/** - * @defgroup groupController Controller Functions - */ - -/** - * @defgroup groupStats Statistics Functions - */ -/** - * @defgroup groupSupport Support Functions - */ - -/** - * @defgroup groupInterpolation Interpolation Functions - * These functions perform 1- and 2-dimensional interpolation of data. - * Linear interpolation is used for 1-dimensional data and - * bilinear interpolation is used for 2-dimensional data. - */ - -/** - * @defgroup groupExamples Examples - */ -#ifndef _ARM_MATH_H -#define _ARM_MATH_H - -/* ignore some GCC warnings */ -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" -#endif - -#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ - -#if defined(ARM_MATH_CM7) -#include "core_cm7.h" -#define ARM_MATH_DSP -#elif defined (ARM_MATH_CM4) -#include "core_cm4.h" -#define ARM_MATH_DSP -#elif defined (ARM_MATH_CM3) -#include "core_cm3.h" -#elif defined (ARM_MATH_CM0) -#include "core_cm0.h" -#define ARM_MATH_CM0_FAMILY -#elif defined (ARM_MATH_CM0PLUS) -#include "core_cm0plus.h" -#define ARM_MATH_CM0_FAMILY -#elif defined (ARM_MATH_ARMV8MBL) -#include "core_armv8mbl.h" -#define ARM_MATH_CM0_FAMILY -#elif defined (ARM_MATH_ARMV8MML) -#include "core_armv8mml.h" -#if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1)) -#define ARM_MATH_DSP -#endif -#else -#error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML" -#endif - -#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ -#include "string.h" -#include "math.h" -#ifdef __cplusplus -extern "C" -{ -#endif - - -/** - * @brief Macros required for reciprocal calculation in Normalized LMS - */ - -#define DELTA_Q31 (0x100) -#define DELTA_Q15 0x5 -#define INDEX_MASK 0x0000003F -#ifndef PI -#define PI 3.14159265358979f -#endif - -/** - * @brief Macros required for SINE and COSINE Fast math approximations - */ - -#define FAST_MATH_TABLE_SIZE 512 -#define FAST_MATH_Q31_SHIFT (32 - 10) -#define FAST_MATH_Q15_SHIFT (16 - 10) -#define CONTROLLER_Q31_SHIFT (32 - 9) -#define TABLE_SPACING_Q31 0x400000 -#define TABLE_SPACING_Q15 0x80 - -/** - * @brief Macros required for SINE and COSINE Controller functions - */ -/* 1.31(q31) Fixed value of 2/360 */ -/* -1 to +1 is divided into 360 values so total spacing is (2/360) */ -#define INPUT_SPACING 0xB60B61 - -/** - * @brief Macro for Unaligned Support - */ -#ifndef UNALIGNED_SUPPORT_DISABLE -#define ALIGN4 -#else -#if defined (__GNUC__) -#define ALIGN4 __attribute__((aligned(4))) -#else -#define ALIGN4 __align(4) -#endif -#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ - -/** - * @brief Error status returned by some functions in the library. - */ - -typedef enum { - ARM_MATH_SUCCESS = 0, /**< No error */ - ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ - ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ - ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ - ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ - ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ - ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ -} arm_status; - -/** - * @brief 8-bit fractional data type in 1.7 format. - */ -typedef int8_t q7_t; - -/** - * @brief 16-bit fractional data type in 1.15 format. - */ -typedef int16_t q15_t; - -/** - * @brief 32-bit fractional data type in 1.31 format. - */ -typedef int32_t q31_t; - -/** - * @brief 64-bit fractional data type in 1.63 format. - */ -typedef int64_t q63_t; - -/** - * @brief 32-bit floating-point type definition. - */ -typedef float float32_t; - -/** - * @brief 64-bit floating-point type definition. - */ -typedef double float64_t; - -/** - * @brief definition to read/write two 16 bit values. - */ -#if defined ( __CC_ARM ) -#define __SIMD32_TYPE int32_t __packed -#define CMSIS_UNUSED __attribute__((unused)) -#define CMSIS_INLINE __attribute__((always_inline)) - -#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) -#define __SIMD32_TYPE int32_t -#define CMSIS_UNUSED __attribute__((unused)) -#define CMSIS_INLINE __attribute__((always_inline)) - -#elif defined ( __GNUC__ ) -#define __SIMD32_TYPE int32_t -#define CMSIS_UNUSED __attribute__((unused)) -#define CMSIS_INLINE __attribute__((always_inline)) - -#elif defined ( __ICCARM__ ) -#define __SIMD32_TYPE int32_t __packed -#define CMSIS_UNUSED -#define CMSIS_INLINE - -#elif defined ( __TI_ARM__ ) -#define __SIMD32_TYPE int32_t -#define CMSIS_UNUSED __attribute__((unused)) -#define CMSIS_INLINE - -#elif defined ( __CSMC__ ) -#define __SIMD32_TYPE int32_t -#define CMSIS_UNUSED -#define CMSIS_INLINE - -#elif defined ( __TASKING__ ) -#define __SIMD32_TYPE __unaligned int32_t -#define CMSIS_UNUSED -#define CMSIS_INLINE - -#else -#error Unknown compiler -#endif - -#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) -#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) -#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) -#define __SIMD64(addr) (*(int64_t **) & (addr)) - -/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ -#if !defined (ARM_MATH_DSP) -/** - * @brief definition to pack two 16 bit values. - */ -#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ - (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) -#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ - (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) - -/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ -#endif /* !defined (ARM_MATH_DSP) */ - -/** -* @brief definition to pack four 8 bit values. -*/ -#ifndef ARM_MATH_BIG_ENDIAN - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) -#else - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) - -#endif - - -/** - * @brief Clips Q63 to Q31 values. - */ -CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31( - q63_t x) -{ - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; -} - -/** - * @brief Clips Q63 to Q15 values. - */ -CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15( - q63_t x) -{ - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); -} - -/** - * @brief Clips Q31 to Q7 values. - */ -CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7( - q31_t x) -{ - return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? - ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; -} - -/** - * @brief Clips Q31 to Q15 values. - */ -CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15( - q31_t x) -{ - return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? - ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; -} - -/** - * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. - */ - -CMSIS_INLINE __STATIC_INLINE q63_t mult32x64( - q63_t x, - q31_t y) -{ - return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + - (((q63_t) (x >> 32) * y))); -} - -/* - #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) - #define __CLZ __clz - #endif - */ -/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */ -#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ) -CMSIS_INLINE __STATIC_INLINE uint32_t __CLZ( - q31_t data); - -CMSIS_INLINE __STATIC_INLINE uint32_t __CLZ( - q31_t data) -{ - uint32_t count = 0; - uint32_t mask = 0x80000000; - - while ((data & mask) == 0) { - count += 1u; - mask = mask >> 1u; - } - - return (count); -} -#endif - -/** - * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. - */ - -CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31( - q31_t in, - q31_t* dst, - q31_t* pRecipTable) -{ - q31_t out; - uint32_t tempVal; - uint32_t index, i; - uint32_t signBits; - - if (in > 0) { - signBits = ((uint32_t) (__CLZ( in) - 1)); - } - else { - signBits = ((uint32_t) (__CLZ(-in) - 1)); - } - - /* Convert input sample to 1.31 format */ - in = (in << signBits); - - /* calculation of index for initial approximated Val */ - index = (uint32_t)(in >> 24); - index = (index & INDEX_MASK); - - /* 1.31 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0u; i < 2u; i++) { - tempVal = (uint32_t) (((q63_t) in * out) >> 31); - tempVal = 0x7FFFFFFFu - tempVal; - /* 1.31 with exp 1 */ - /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ - out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1u); -} - - -/** - * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. - */ -CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15( - q15_t in, - q15_t* dst, - q15_t* pRecipTable) -{ - q15_t out = 0; - uint32_t tempVal = 0; - uint32_t index = 0, i = 0; - uint32_t signBits = 0; - - if (in > 0) { - signBits = ((uint32_t)(__CLZ( in) - 17)); - } - else { - signBits = ((uint32_t)(__CLZ(-in) - 17)); - } - - /* Convert input sample to 1.15 format */ - in = (in << signBits); - - /* calculation of index for initial approximated Val */ - index = (uint32_t)(in >> 8); - index = (index & INDEX_MASK); - - /* 1.15 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0u; i < 2u; i++) { - tempVal = (uint32_t) (((q31_t) in * out) >> 15); - tempVal = 0x7FFFu - tempVal; - /* 1.15 with exp 1 */ - out = (q15_t) (((q31_t) out * tempVal) >> 14); - /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1); -} - - -/* - * @brief C custom defined intrinisic function for only M0 processors - */ -#if defined(ARM_MATH_CM0_FAMILY) -CMSIS_INLINE __STATIC_INLINE q31_t __SSAT( - q31_t x, - uint32_t y) -{ - int32_t posMax, negMin; - uint32_t i; - - posMax = 1; - for (i = 0; i < (y - 1); i++) { - posMax = posMax * 2; - } - - if (x > 0) { - posMax = (posMax - 1); - - if (x > posMax) { - x = posMax; - } - } - else { - negMin = -posMax; - - if (x < negMin) { - x = negMin; - } - } - return (x); -} -#endif /* end of ARM_MATH_CM0_FAMILY */ - - -/* - * @brief C custom defined intrinsic function for M3 and M0 processors - */ -/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ -#if !defined (ARM_MATH_DSP) - -/* - * @brief C custom defined QADD8 for M3 and M0 processors - */ -CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8( - uint32_t x, - uint32_t y) -{ - q31_t r, s, t, u; - - r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; - s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; - t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; - u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; - - return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); -} - - -/* - * @brief C custom defined QSUB8 for M3 and M0 processors - */ -CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8( - uint32_t x, - uint32_t y) -{ - q31_t r, s, t, u; - - r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; - s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; - t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; - u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; - - return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); -} - - -/* - * @brief C custom defined QADD16 for M3 and M0 processors - */ -CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16( - uint32_t x, - uint32_t y) -{ - /* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ - q31_t r = 0, s = 0; - - r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); -} - - -/* - * @brief C custom defined SHADD16 for M3 and M0 processors - */ -CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16( - uint32_t x, - uint32_t y) -{ - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); -} - - -/* - * @brief C custom defined QSUB16 for M3 and M0 processors - */ -CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16( - uint32_t x, - uint32_t y) -{ - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); -} - - -/* - * @brief C custom defined SHSUB16 for M3 and M0 processors - */ -CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16( - uint32_t x, - uint32_t y) -{ - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); -} - - -/* - * @brief C custom defined QASX for M3 and M0 processors - */ -CMSIS_INLINE __STATIC_INLINE uint32_t __QASX( - uint32_t x, - uint32_t y) -{ - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); -} - - -/* - * @brief C custom defined SHASX for M3 and M0 processors - */ -CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX( - uint32_t x, - uint32_t y) -{ - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); -} - - -/* - * @brief C custom defined QSAX for M3 and M0 processors - */ -CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX( - uint32_t x, - uint32_t y) -{ - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); -} - - -/* - * @brief C custom defined SHSAX for M3 and M0 processors - */ -CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX( - uint32_t x, - uint32_t y) -{ - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); -} - - -/* - * @brief C custom defined SMUSDX for M3 and M0 processors - */ -CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX( - uint32_t x, - uint32_t y) -{ - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); -} - -/* - * @brief C custom defined SMUADX for M3 and M0 processors - */ -CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX( - uint32_t x, - uint32_t y) -{ - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); -} - - -/* - * @brief C custom defined QADD for M3 and M0 processors - */ -CMSIS_INLINE __STATIC_INLINE int32_t __QADD( - int32_t x, - int32_t y) -{ - return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); -} - - -/* - * @brief C custom defined QSUB for M3 and M0 processors - */ -CMSIS_INLINE __STATIC_INLINE int32_t __QSUB( - int32_t x, - int32_t y) -{ - return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); -} - - -/* - * @brief C custom defined SMLAD for M3 and M0 processors - */ -CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD( - uint32_t x, - uint32_t y, - uint32_t sum) -{ - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + - ( ((q31_t)sum ) ) )); -} - - -/* - * @brief C custom defined SMLADX for M3 and M0 processors - */ -CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX( - uint32_t x, - uint32_t y, - uint32_t sum) -{ - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q31_t)sum ) ) )); -} - - -/* - * @brief C custom defined SMLSDX for M3 and M0 processors - */ -CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX( - uint32_t x, - uint32_t y, - uint32_t sum) -{ - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q31_t)sum ) ) )); -} - - -/* - * @brief C custom defined SMLALD for M3 and M0 processors - */ -CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD( - uint32_t x, - uint32_t y, - uint64_t sum) -{ - /* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ - return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + - ( ((q63_t)sum ) ) )); -} - - -/* - * @brief C custom defined SMLALDX for M3 and M0 processors - */ -CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX( - uint32_t x, - uint32_t y, - uint64_t sum) -{ - /* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ - return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q63_t)sum ) ) )); -} - - -/* - * @brief C custom defined SMUAD for M3 and M0 processors - */ -CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD( - uint32_t x, - uint32_t y) -{ - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); -} - - -/* - * @brief C custom defined SMUSD for M3 and M0 processors - */ -CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD( - uint32_t x, - uint32_t y) -{ - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); -} - - -/* - * @brief C custom defined SXTB16 for M3 and M0 processors - */ -CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16( - uint32_t x) -{ - return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | - ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); -} - -/* - * @brief C custom defined SMMLA for M3 and M0 processors - */ -CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA( - int32_t x, - int32_t y, - int32_t sum) -{ - return (sum + (int32_t) (((int64_t) x * y) >> 32)); -} - -#if 0 -/* - * @brief C custom defined PKHBT for unavailable DSP extension - */ -CMSIS_INLINE __STATIC_INLINE uint32_t __PKHBT( - uint32_t x, - uint32_t y, - uint32_t leftshift) -{ - return ( ((x ) & 0x0000FFFFUL) | - ((y << leftshift) & 0xFFFF0000UL) ); -} - -/* - * @brief C custom defined PKHTB for unavailable DSP extension - */ -CMSIS_INLINE __STATIC_INLINE uint32_t __PKHTB( - uint32_t x, - uint32_t y, - uint32_t rightshift) -{ - return ( ((x ) & 0xFFFF0000UL) | - ((y >> rightshift) & 0x0000FFFFUL) ); -} -#endif - -/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ -#endif /* !defined (ARM_MATH_DSP) */ - - -/** - * @brief Instance structure for the Q7 FIR filter. - */ -typedef struct { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q7_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q7_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ -} arm_fir_instance_q7; - -/** - * @brief Instance structure for the Q15 FIR filter. - */ -typedef struct { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q15_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ -} arm_fir_instance_q15; - -/** - * @brief Instance structure for the Q31 FIR filter. - */ -typedef struct { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q31_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ -} arm_fir_instance_q31; - -/** - * @brief Instance structure for the floating-point FIR filter. - */ -typedef struct { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - float32_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ -} arm_fir_instance_f32; - - -/** - * @brief Processing function for the Q7 FIR filter. - * @param[in] S points to an instance of the Q7 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ -void arm_fir_q7( - const arm_fir_instance_q7* S, - q7_t* pSrc, - q7_t* pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q7 FIR filter. - * @param[in,out] S points to an instance of the Q7 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed. - */ -void arm_fir_init_q7( - arm_fir_instance_q7* S, - uint16_t numTaps, - q7_t* pCoeffs, - q7_t* pState, - uint32_t blockSize); - - -/** - * @brief Processing function for the Q15 FIR filter. - * @param[in] S points to an instance of the Q15 FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ -void arm_fir_q15( - const arm_fir_instance_q15* S, - q15_t* pSrc, - q15_t* pDst, - uint32_t blockSize); - - -/** - * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ -void arm_fir_fast_q15( - const arm_fir_instance_q15* S, - q15_t* pSrc, - q15_t* pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 FIR filter. - * @param[in,out] S points to an instance of the Q15 FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if - * numTaps is not a supported value. - */ -arm_status arm_fir_init_q15( - arm_fir_instance_q15* S, - uint16_t numTaps, - q15_t* pCoeffs, - q15_t* pState, - uint32_t blockSize); - - -/** - * @brief Processing function for the Q31 FIR filter. - * @param[in] S points to an instance of the Q31 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ -void arm_fir_q31( - const arm_fir_instance_q31* S, - q31_t* pSrc, - q31_t* pDst, - uint32_t blockSize); - - -/** - * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ -void arm_fir_fast_q31( - const arm_fir_instance_q31* S, - q31_t* pSrc, - q31_t* pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q31 FIR filter. - * @param[in,out] S points to an instance of the Q31 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - */ -void arm_fir_init_q31( - arm_fir_instance_q31* S, - uint16_t numTaps, - q31_t* pCoeffs, - q31_t* pState, - uint32_t blockSize); - - -/** - * @brief Processing function for the floating-point FIR filter. - * @param[in] S points to an instance of the floating-point FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ -void arm_fir_f32( - const arm_fir_instance_f32* S, - float32_t* pSrc, - float32_t* pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the floating-point FIR filter. - * @param[in,out] S points to an instance of the floating-point FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - */ -void arm_fir_init_f32( - arm_fir_instance_f32* S, - uint16_t numTaps, - float32_t* pCoeffs, - float32_t* pState, - uint32_t blockSize); - - -/** - * @brief Instance structure for the Q15 Biquad cascade filter. - */ -typedef struct { - int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q15_t* pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q15_t* pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ -} arm_biquad_casd_df1_inst_q15; - -/** - * @brief Instance structure for the Q31 Biquad cascade filter. - */ -typedef struct { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q31_t* pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t* pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ -} arm_biquad_casd_df1_inst_q31; - -/** - * @brief Instance structure for the floating-point Biquad cascade filter. - */ -typedef struct { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t* pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t* pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ -} arm_biquad_casd_df1_inst_f32; - - -/** - * @brief Processing function for the Q15 Biquad cascade filter. - * @param[in] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ -void arm_biquad_cascade_df1_q15( - const arm_biquad_casd_df1_inst_q15* S, - q15_t* pSrc, - q15_t* pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 Biquad cascade filter. - * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - */ -void arm_biquad_cascade_df1_init_q15( - arm_biquad_casd_df1_inst_q15* S, - uint8_t numStages, - q15_t* pCoeffs, - q15_t* pState, - int8_t postShift); - - -/** - * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ -void arm_biquad_cascade_df1_fast_q15( - const arm_biquad_casd_df1_inst_q15* S, - q15_t* pSrc, - q15_t* pDst, - uint32_t blockSize); - - -/** - * @brief Processing function for the Q31 Biquad cascade filter - * @param[in] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ -void arm_biquad_cascade_df1_q31( - const arm_biquad_casd_df1_inst_q31* S, - q31_t* pSrc, - q31_t* pDst, - uint32_t blockSize); - - -/** - * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ -void arm_biquad_cascade_df1_fast_q31( - const arm_biquad_casd_df1_inst_q31* S, - q31_t* pSrc, - q31_t* pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q31 Biquad cascade filter. - * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - */ -void arm_biquad_cascade_df1_init_q31( - arm_biquad_casd_df1_inst_q31* S, - uint8_t numStages, - q31_t* pCoeffs, - q31_t* pState, - int8_t postShift); - - -/** - * @brief Processing function for the floating-point Biquad cascade filter. - * @param[in] S points to an instance of the floating-point Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ -void arm_biquad_cascade_df1_f32( - const arm_biquad_casd_df1_inst_f32* S, - float32_t* pSrc, - float32_t* pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the floating-point Biquad cascade filter. - * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ -void arm_biquad_cascade_df1_init_f32( - arm_biquad_casd_df1_inst_f32* S, - uint8_t numStages, - float32_t* pCoeffs, - float32_t* pState); - - -/** - * @brief Instance structure for the floating-point matrix structure. - */ -typedef struct { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float32_t* pData; /**< points to the data of the matrix. */ -} arm_matrix_instance_f32; - - -/** - * @brief Instance structure for the floating-point matrix structure. - */ -typedef struct { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float64_t* pData; /**< points to the data of the matrix. */ -} arm_matrix_instance_f64; - -/** - * @brief Instance structure for the Q15 matrix structure. - */ -typedef struct { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q15_t* pData; /**< points to the data of the matrix. */ -} arm_matrix_instance_q15; - -/** - * @brief Instance structure for the Q31 matrix structure. - */ -typedef struct { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q31_t* pData; /**< points to the data of the matrix. */ -} arm_matrix_instance_q31; - - -/** - * @brief Floating-point matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ -arm_status arm_mat_add_f32( - const arm_matrix_instance_f32* pSrcA, - const arm_matrix_instance_f32* pSrcB, - arm_matrix_instance_f32* pDst); - - -/** - * @brief Q15 matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ -arm_status arm_mat_add_q15( - const arm_matrix_instance_q15* pSrcA, - const arm_matrix_instance_q15* pSrcB, - arm_matrix_instance_q15* pDst); - - -/** - * @brief Q31 matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ -arm_status arm_mat_add_q31( - const arm_matrix_instance_q31* pSrcA, - const arm_matrix_instance_q31* pSrcB, - arm_matrix_instance_q31* pDst); - - -/** - * @brief Floating-point, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ -arm_status arm_mat_cmplx_mult_f32( - const arm_matrix_instance_f32* pSrcA, - const arm_matrix_instance_f32* pSrcB, - arm_matrix_instance_f32* pDst); - - -/** - * @brief Q15, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ -arm_status arm_mat_cmplx_mult_q15( - const arm_matrix_instance_q15* pSrcA, - const arm_matrix_instance_q15* pSrcB, - arm_matrix_instance_q15* pDst, - q15_t* pScratch); - - -/** - * @brief Q31, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ -arm_status arm_mat_cmplx_mult_q31( - const arm_matrix_instance_q31* pSrcA, - const arm_matrix_instance_q31* pSrcB, - arm_matrix_instance_q31* pDst); - - -/** - * @brief Floating-point matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ -arm_status arm_mat_trans_f32( - const arm_matrix_instance_f32* pSrc, - arm_matrix_instance_f32* pDst); - - -/** - * @brief Q15 matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ -arm_status arm_mat_trans_q15( - const arm_matrix_instance_q15* pSrc, - arm_matrix_instance_q15* pDst); - - -/** - * @brief Q31 matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ -arm_status arm_mat_trans_q31( - const arm_matrix_instance_q31* pSrc, - arm_matrix_instance_q31* pDst); - - -/** - * @brief Floating-point matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ -arm_status arm_mat_mult_f32( - const arm_matrix_instance_f32* pSrcA, - const arm_matrix_instance_f32* pSrcB, - arm_matrix_instance_f32* pDst); - - -/** - * @brief Q15 matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @param[in] pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ -arm_status arm_mat_mult_q15( - const arm_matrix_instance_q15* pSrcA, - const arm_matrix_instance_q15* pSrcB, - arm_matrix_instance_q15* pDst, - q15_t* pState); - - -/** - * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @param[in] pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ -arm_status arm_mat_mult_fast_q15( - const arm_matrix_instance_q15* pSrcA, - const arm_matrix_instance_q15* pSrcB, - arm_matrix_instance_q15* pDst, - q15_t* pState); - - -/** - * @brief Q31 matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ -arm_status arm_mat_mult_q31( - const arm_matrix_instance_q31* pSrcA, - const arm_matrix_instance_q31* pSrcB, - arm_matrix_instance_q31* pDst); - - -/** - * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ -arm_status arm_mat_mult_fast_q31( - const arm_matrix_instance_q31* pSrcA, - const arm_matrix_instance_q31* pSrcB, - arm_matrix_instance_q31* pDst); - - -/** - * @brief Floating-point matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ -arm_status arm_mat_sub_f32( - const arm_matrix_instance_f32* pSrcA, - const arm_matrix_instance_f32* pSrcB, - arm_matrix_instance_f32* pDst); - - -/** - * @brief Q15 matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ -arm_status arm_mat_sub_q15( - const arm_matrix_instance_q15* pSrcA, - const arm_matrix_instance_q15* pSrcB, - arm_matrix_instance_q15* pDst); - - -/** - * @brief Q31 matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ -arm_status arm_mat_sub_q31( - const arm_matrix_instance_q31* pSrcA, - const arm_matrix_instance_q31* pSrcB, - arm_matrix_instance_q31* pDst); - - -/** - * @brief Floating-point matrix scaling. - * @param[in] pSrc points to the input matrix - * @param[in] scale scale factor - * @param[out] pDst points to the output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ -arm_status arm_mat_scale_f32( - const arm_matrix_instance_f32* pSrc, - float32_t scale, - arm_matrix_instance_f32* pDst); - - -/** - * @brief Q15 matrix scaling. - * @param[in] pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ -arm_status arm_mat_scale_q15( - const arm_matrix_instance_q15* pSrc, - q15_t scaleFract, - int32_t shift, - arm_matrix_instance_q15* pDst); - - -/** - * @brief Q31 matrix scaling. - * @param[in] pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ -arm_status arm_mat_scale_q31( - const arm_matrix_instance_q31* pSrc, - q31_t scaleFract, - int32_t shift, - arm_matrix_instance_q31* pDst); - - -/** - * @brief Q31 matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ -void arm_mat_init_q31( - arm_matrix_instance_q31* S, - uint16_t nRows, - uint16_t nColumns, - q31_t* pData); - - -/** - * @brief Q15 matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ -void arm_mat_init_q15( - arm_matrix_instance_q15* S, - uint16_t nRows, - uint16_t nColumns, - q15_t* pData); - - -/** - * @brief Floating-point matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ -void arm_mat_init_f32( - arm_matrix_instance_f32* S, - uint16_t nRows, - uint16_t nColumns, - float32_t* pData); - - - -/** - * @brief Instance structure for the Q15 PID Control. - */ -typedef struct { - q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ -#if !defined (ARM_MATH_DSP) - q15_t A1; - q15_t A2; -#else - q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ -#endif - q15_t state[3]; /**< The state array of length 3. */ - q15_t Kp; /**< The proportional gain. */ - q15_t Ki; /**< The integral gain. */ - q15_t Kd; /**< The derivative gain. */ -} arm_pid_instance_q15; - -/** - * @brief Instance structure for the Q31 PID Control. - */ -typedef struct { - q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - q31_t A2; /**< The derived gain, A2 = Kd . */ - q31_t state[3]; /**< The state array of length 3. */ - q31_t Kp; /**< The proportional gain. */ - q31_t Ki; /**< The integral gain. */ - q31_t Kd; /**< The derivative gain. */ -} arm_pid_instance_q31; - -/** - * @brief Instance structure for the floating-point PID Control. - */ -typedef struct { - float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - float32_t A2; /**< The derived gain, A2 = Kd . */ - float32_t state[3]; /**< The state array of length 3. */ - float32_t Kp; /**< The proportional gain. */ - float32_t Ki; /**< The integral gain. */ - float32_t Kd; /**< The derivative gain. */ -} arm_pid_instance_f32; - - - -/** - * @brief Initialization function for the floating-point PID Control. - * @param[in,out] S points to an instance of the PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ -void arm_pid_init_f32( - arm_pid_instance_f32* S, - int32_t resetStateFlag); - - -/** - * @brief Reset function for the floating-point PID Control. - * @param[in,out] S is an instance of the floating-point PID Control structure - */ -void arm_pid_reset_f32( - arm_pid_instance_f32* S); - - -/** - * @brief Initialization function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ -void arm_pid_init_q31( - arm_pid_instance_q31* S, - int32_t resetStateFlag); - - -/** - * @brief Reset function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q31 PID Control structure - */ - -void arm_pid_reset_q31( - arm_pid_instance_q31* S); - - -/** - * @brief Initialization function for the Q15 PID Control. - * @param[in,out] S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ -void arm_pid_init_q15( - arm_pid_instance_q15* S, - int32_t resetStateFlag); - - -/** - * @brief Reset function for the Q15 PID Control. - * @param[in,out] S points to an instance of the q15 PID Control structure - */ -void arm_pid_reset_q15( - arm_pid_instance_q15* S); - - -/** - * @brief Instance structure for the floating-point Linear Interpolate function. - */ -typedef struct { - uint32_t nValues; /**< nValues */ - float32_t x1; /**< x1 */ - float32_t xSpacing; /**< xSpacing */ - float32_t* pYData; /**< pointer to the table of Y values */ -} arm_linear_interp_instance_f32; - -/** - * @brief Instance structure for the floating-point bilinear interpolation function. - */ -typedef struct { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - float32_t* pData; /**< points to the data table. */ -} arm_bilinear_interp_instance_f32; - -/** -* @brief Instance structure for the Q31 bilinear interpolation function. -*/ -typedef struct { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q31_t* pData; /**< points to the data table. */ -} arm_bilinear_interp_instance_q31; - -/** -* @brief Instance structure for the Q15 bilinear interpolation function. -*/ -typedef struct { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q15_t* pData; /**< points to the data table. */ -} arm_bilinear_interp_instance_q15; - -/** -* @brief Instance structure for the Q15 bilinear interpolation function. -*/ -typedef struct { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q7_t* pData; /**< points to the data table. */ -} arm_bilinear_interp_instance_q7; - - -/** - * @brief Q7 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ -void arm_mult_q7( - q7_t* pSrcA, - q7_t* pSrcB, - q7_t* pDst, - uint32_t blockSize); - - -/** - * @brief Q15 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ -void arm_mult_q15( - q15_t* pSrcA, - q15_t* pSrcB, - q15_t* pDst, - uint32_t blockSize); - - -/** - * @brief Q31 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ -void arm_mult_q31( - q31_t* pSrcA, - q31_t* pSrcB, - q31_t* pDst, - uint32_t blockSize); - - -/** - * @brief Floating-point vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ -void arm_mult_f32( - float32_t* pSrcA, - float32_t* pSrcB, - float32_t* pDst, - uint32_t blockSize); - - -/** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ -typedef struct { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t* pTwiddle; /**< points to the Sin twiddle factor table. */ - uint16_t* pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ -} arm_cfft_radix2_instance_q15; - -/* Deprecated */ -arm_status arm_cfft_radix2_init_q15( - arm_cfft_radix2_instance_q15* S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ -void arm_cfft_radix2_q15( - const arm_cfft_radix2_instance_q15* S, - q15_t* pSrc); - - -/** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ -typedef struct { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t* pTwiddle; /**< points to the twiddle factor table. */ - uint16_t* pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ -} arm_cfft_radix4_instance_q15; - -/* Deprecated */ -arm_status arm_cfft_radix4_init_q15( - arm_cfft_radix4_instance_q15* S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ -void arm_cfft_radix4_q15( - const arm_cfft_radix4_instance_q15* S, - q15_t* pSrc); - -/** - * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. - */ -typedef struct { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t* pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t* pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ -} arm_cfft_radix2_instance_q31; - -/* Deprecated */ -arm_status arm_cfft_radix2_init_q31( - arm_cfft_radix2_instance_q31* S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ -void arm_cfft_radix2_q31( - const arm_cfft_radix2_instance_q31* S, - q31_t* pSrc); - -/** - * @brief Instance structure for the Q31 CFFT/CIFFT function. - */ -typedef struct { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t* pTwiddle; /**< points to the twiddle factor table. */ - uint16_t* pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ -} arm_cfft_radix4_instance_q31; - -/* Deprecated */ -void arm_cfft_radix4_q31( - const arm_cfft_radix4_instance_q31* S, - q31_t* pSrc); - -/* Deprecated */ -arm_status arm_cfft_radix4_init_q31( - arm_cfft_radix4_instance_q31* S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ -typedef struct { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t* pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t* pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ -} arm_cfft_radix2_instance_f32; - -/* Deprecated */ -arm_status arm_cfft_radix2_init_f32( - arm_cfft_radix2_instance_f32* S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ -void arm_cfft_radix2_f32( - const arm_cfft_radix2_instance_f32* S, - float32_t* pSrc); - -/** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ -typedef struct { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t* pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t* pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ -} arm_cfft_radix4_instance_f32; - -/* Deprecated */ -arm_status arm_cfft_radix4_init_f32( - arm_cfft_radix4_instance_f32* S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ -void arm_cfft_radix4_f32( - const arm_cfft_radix4_instance_f32* S, - float32_t* pSrc); - -/** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ -typedef struct { - uint16_t fftLen; /**< length of the FFT. */ - const q15_t* pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t* pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ -} arm_cfft_instance_q15; - -void arm_cfft_q15( - const arm_cfft_instance_q15* S, - q15_t* p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ -typedef struct { - uint16_t fftLen; /**< length of the FFT. */ - const q31_t* pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t* pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ -} arm_cfft_instance_q31; - -void arm_cfft_q31( - const arm_cfft_instance_q31* S, - q31_t* p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ -typedef struct { - uint16_t fftLen; /**< length of the FFT. */ - const float32_t* pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t* pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ -} arm_cfft_instance_f32; - -void arm_cfft_f32( - const arm_cfft_instance_f32* S, - float32_t* p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/** - * @brief Instance structure for the Q15 RFFT/RIFFT function. - */ -typedef struct { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q15_t* pTwiddleAReal; /**< points to the real twiddle factor table. */ - q15_t* pTwiddleBReal; /**< points to the imag twiddle factor table. */ - const arm_cfft_instance_q15* pCfft; /**< points to the complex FFT instance. */ -} arm_rfft_instance_q15; - -arm_status arm_rfft_init_q15( - arm_rfft_instance_q15* S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - -void arm_rfft_q15( - const arm_rfft_instance_q15* S, - q15_t* pSrc, - q15_t* pDst); - -/** - * @brief Instance structure for the Q31 RFFT/RIFFT function. - */ -typedef struct { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q31_t* pTwiddleAReal; /**< points to the real twiddle factor table. */ - q31_t* pTwiddleBReal; /**< points to the imag twiddle factor table. */ - const arm_cfft_instance_q31* pCfft; /**< points to the complex FFT instance. */ -} arm_rfft_instance_q31; - -arm_status arm_rfft_init_q31( - arm_rfft_instance_q31* S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - -void arm_rfft_q31( - const arm_rfft_instance_q31* S, - q31_t* pSrc, - q31_t* pDst); - -/** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ -typedef struct { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint16_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - float32_t* pTwiddleAReal; /**< points to the real twiddle factor table. */ - float32_t* pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_f32* pCfft; /**< points to the complex FFT instance. */ -} arm_rfft_instance_f32; - -arm_status arm_rfft_init_f32( - arm_rfft_instance_f32* S, - arm_cfft_radix4_instance_f32* S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - -void arm_rfft_f32( - const arm_rfft_instance_f32* S, - float32_t* pSrc, - float32_t* pDst); - -/** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ -typedef struct { - arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ - uint16_t fftLenRFFT; /**< length of the real sequence */ - float32_t* pTwiddleRFFT; /**< Twiddle factors real stage */ -} arm_rfft_fast_instance_f32 ; - -arm_status arm_rfft_fast_init_f32 ( - arm_rfft_fast_instance_f32* S, - uint16_t fftLen); - -void arm_rfft_fast_f32( - arm_rfft_fast_instance_f32* S, - float32_t* p, float32_t* pOut, - uint8_t ifftFlag); - -/** - * @brief Instance structure for the floating-point DCT4/IDCT4 function. - */ -typedef struct { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - float32_t normalize; /**< normalizing factor. */ - float32_t* pTwiddle; /**< points to the twiddle factor table. */ - float32_t* pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_f32* pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_f32* pCfft; /**< points to the complex FFT instance. */ -} arm_dct4_instance_f32; - - -/** - * @brief Initialization function for the floating-point DCT4/IDCT4. - * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. - * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. - */ -arm_status arm_dct4_init_f32( - arm_dct4_instance_f32* S, - arm_rfft_instance_f32* S_RFFT, - arm_cfft_radix4_instance_f32* S_CFFT, - uint16_t N, - uint16_t Nby2, - float32_t normalize); - - -/** - * @brief Processing function for the floating-point DCT4/IDCT4. - * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ -void arm_dct4_f32( - const arm_dct4_instance_f32* S, - float32_t* pState, - float32_t* pInlineBuffer); - - -/** - * @brief Instance structure for the Q31 DCT4/IDCT4 function. - */ -typedef struct { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q31_t normalize; /**< normalizing factor. */ - q31_t* pTwiddle; /**< points to the twiddle factor table. */ - q31_t* pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q31* pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q31* pCfft; /**< points to the complex FFT instance. */ -} arm_dct4_instance_q31; - - -/** - * @brief Initialization function for the Q31 DCT4/IDCT4. - * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure - * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ -arm_status arm_dct4_init_q31( - arm_dct4_instance_q31* S, - arm_rfft_instance_q31* S_RFFT, - arm_cfft_radix4_instance_q31* S_CFFT, - uint16_t N, - uint16_t Nby2, - q31_t normalize); - - -/** - * @brief Processing function for the Q31 DCT4/IDCT4. - * @param[in] S points to an instance of the Q31 DCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ -void arm_dct4_q31( - const arm_dct4_instance_q31* S, - q31_t* pState, - q31_t* pInlineBuffer); - - -/** - * @brief Instance structure for the Q15 DCT4/IDCT4 function. - */ -typedef struct { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q15_t normalize; /**< normalizing factor. */ - q15_t* pTwiddle; /**< points to the twiddle factor table. */ - q15_t* pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q15* pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q15* pCfft; /**< points to the complex FFT instance. */ -} arm_dct4_instance_q15; - - -/** - * @brief Initialization function for the Q15 DCT4/IDCT4. - * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. - * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ -arm_status arm_dct4_init_q15( - arm_dct4_instance_q15* S, - arm_rfft_instance_q15* S_RFFT, - arm_cfft_radix4_instance_q15* S_CFFT, - uint16_t N, - uint16_t Nby2, - q15_t normalize); - - -/** - * @brief Processing function for the Q15 DCT4/IDCT4. - * @param[in] S points to an instance of the Q15 DCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ -void arm_dct4_q15( - const arm_dct4_instance_q15* S, - q15_t* pState, - q15_t* pInlineBuffer); - - -/** - * @brief Floating-point vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ -void arm_add_f32( - float32_t* pSrcA, - float32_t* pSrcB, - float32_t* pDst, - uint32_t blockSize); - - -/** - * @brief Q7 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ -void arm_add_q7( - q7_t* pSrcA, - q7_t* pSrcB, - q7_t* pDst, - uint32_t blockSize); - - -/** - * @brief Q15 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ -void arm_add_q15( - q15_t* pSrcA, - q15_t* pSrcB, - q15_t* pDst, - uint32_t blockSize); - - -/** - * @brief Q31 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ -void arm_add_q31( - q31_t* pSrcA, - q31_t* pSrcB, - q31_t* pDst, - uint32_t blockSize); - - -/** - * @brief Floating-point vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ -void arm_sub_f32( - float32_t* pSrcA, - float32_t* pSrcB, - float32_t* pDst, - uint32_t blockSize); - - -/** - * @brief Q7 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ -void arm_sub_q7( - q7_t* pSrcA, - q7_t* pSrcB, - q7_t* pDst, - uint32_t blockSize); - - -/** - * @brief Q15 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ -void arm_sub_q15( - q15_t* pSrcA, - q15_t* pSrcB, - q15_t* pDst, - uint32_t blockSize); - - -/** - * @brief Q31 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ -void arm_sub_q31( - q31_t* pSrcA, - q31_t* pSrcB, - q31_t* pDst, - uint32_t blockSize); - - -/** - * @brief Multiplies a floating-point vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scale scale factor to be applied - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ -void arm_scale_f32( - float32_t* pSrc, - float32_t scale, - float32_t* pDst, - uint32_t blockSize); - - -/** - * @brief Multiplies a Q7 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ -void arm_scale_q7( - q7_t* pSrc, - q7_t scaleFract, - int8_t shift, - q7_t* pDst, - uint32_t blockSize); - - -/** - * @brief Multiplies a Q15 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ -void arm_scale_q15( - q15_t* pSrc, - q15_t scaleFract, - int8_t shift, - q15_t* pDst, - uint32_t blockSize); - - -/** - * @brief Multiplies a Q31 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ -void arm_scale_q31( - q31_t* pSrc, - q31_t scaleFract, - int8_t shift, - q31_t* pDst, - uint32_t blockSize); - - -/** - * @brief Q7 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ -void arm_abs_q7( - q7_t* pSrc, - q7_t* pDst, - uint32_t blockSize); - - -/** - * @brief Floating-point vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ -void arm_abs_f32( - float32_t* pSrc, - float32_t* pDst, - uint32_t blockSize); - - -/** - * @brief Q15 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ -void arm_abs_q15( - q15_t* pSrc, - q15_t* pDst, - uint32_t blockSize); - - -/** - * @brief Q31 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ -void arm_abs_q31( - q31_t* pSrc, - q31_t* pDst, - uint32_t blockSize); - - -/** - * @brief Dot product of floating-point vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ -void arm_dot_prod_f32( - float32_t* pSrcA, - float32_t* pSrcB, - uint32_t blockSize, - float32_t* result); - - -/** - * @brief Dot product of Q7 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ -void arm_dot_prod_q7( - q7_t* pSrcA, - q7_t* pSrcB, - uint32_t blockSize, - q31_t* result); - - -/** - * @brief Dot product of Q15 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ -void arm_dot_prod_q15( - q15_t* pSrcA, - q15_t* pSrcB, - uint32_t blockSize, - q63_t* result); - - -/** - * @brief Dot product of Q31 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ -void arm_dot_prod_q31( - q31_t* pSrcA, - q31_t* pSrcB, - uint32_t blockSize, - q63_t* result); - - -/** - * @brief Shifts the elements of a Q7 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ -void arm_shift_q7( - q7_t* pSrc, - int8_t shiftBits, - q7_t* pDst, - uint32_t blockSize); - - -/** - * @brief Shifts the elements of a Q15 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ -void arm_shift_q15( - q15_t* pSrc, - int8_t shiftBits, - q15_t* pDst, - uint32_t blockSize); - - -/** - * @brief Shifts the elements of a Q31 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ -void arm_shift_q31( - q31_t* pSrc, - int8_t shiftBits, - q31_t* pDst, - uint32_t blockSize); - - -/** - * @brief Adds a constant offset to a floating-point vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ -void arm_offset_f32( - float32_t* pSrc, - float32_t offset, - float32_t* pDst, - uint32_t blockSize); - - -/** - * @brief Adds a constant offset to a Q7 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ -void arm_offset_q7( - q7_t* pSrc, - q7_t offset, - q7_t* pDst, - uint32_t blockSize); - - -/** - * @brief Adds a constant offset to a Q15 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ -void arm_offset_q15( - q15_t* pSrc, - q15_t offset, - q15_t* pDst, - uint32_t blockSize); - - -/** - * @brief Adds a constant offset to a Q31 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ -void arm_offset_q31( - q31_t* pSrc, - q31_t offset, - q31_t* pDst, - uint32_t blockSize); - - -/** - * @brief Negates the elements of a floating-point vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ -void arm_negate_f32( - float32_t* pSrc, - float32_t* pDst, - uint32_t blockSize); - - -/** - * @brief Negates the elements of a Q7 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ -void arm_negate_q7( - q7_t* pSrc, - q7_t* pDst, - uint32_t blockSize); - - -/** - * @brief Negates the elements of a Q15 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ -void arm_negate_q15( - q15_t* pSrc, - q15_t* pDst, - uint32_t blockSize); - - -/** - * @brief Negates the elements of a Q31 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ -void arm_negate_q31( - q31_t* pSrc, - q31_t* pDst, - uint32_t blockSize); - - -/** - * @brief Copies the elements of a floating-point vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ -void arm_copy_f32( - float32_t* pSrc, - float32_t* pDst, - uint32_t blockSize); - - -/** - * @brief Copies the elements of a Q7 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ -void arm_copy_q7( - q7_t* pSrc, - q7_t* pDst, - uint32_t blockSize); - - -/** - * @brief Copies the elements of a Q15 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ -void arm_copy_q15( - q15_t* pSrc, - q15_t* pDst, - uint32_t blockSize); - - -/** - * @brief Copies the elements of a Q31 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ -void arm_copy_q31( - q31_t* pSrc, - q31_t* pDst, - uint32_t blockSize); - - -/** - * @brief Fills a constant value into a floating-point vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ -void arm_fill_f32( - float32_t value, - float32_t* pDst, - uint32_t blockSize); - - -/** - * @brief Fills a constant value into a Q7 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ -void arm_fill_q7( - q7_t value, - q7_t* pDst, - uint32_t blockSize); - - -/** - * @brief Fills a constant value into a Q15 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ -void arm_fill_q15( - q15_t value, - q15_t* pDst, - uint32_t blockSize); - - -/** - * @brief Fills a constant value into a Q31 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ -void arm_fill_q31( - q31_t value, - q31_t* pDst, - uint32_t blockSize); - - -/** - * @brief Convolution of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - */ -void arm_conv_f32( - float32_t* pSrcA, - uint32_t srcALen, - float32_t* pSrcB, - uint32_t srcBLen, - float32_t* pDst); - - -/** - * @brief Convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - */ -void arm_conv_opt_q15( - q15_t* pSrcA, - uint32_t srcALen, - q15_t* pSrcB, - uint32_t srcBLen, - q15_t* pDst, - q15_t* pScratch1, - q15_t* pScratch2); - - -/** - * @brief Convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - */ -void arm_conv_q15( - q15_t* pSrcA, - uint32_t srcALen, - q15_t* pSrcB, - uint32_t srcBLen, - q15_t* pDst); - - -/** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ -void arm_conv_fast_q15( - q15_t* pSrcA, - uint32_t srcALen, - q15_t* pSrcB, - uint32_t srcBLen, - q15_t* pDst); - - -/** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - */ -void arm_conv_fast_opt_q15( - q15_t* pSrcA, - uint32_t srcALen, - q15_t* pSrcB, - uint32_t srcBLen, - q15_t* pDst, - q15_t* pScratch1, - q15_t* pScratch2); - - -/** - * @brief Convolution of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ -void arm_conv_q31( - q31_t* pSrcA, - uint32_t srcALen, - q31_t* pSrcB, - uint32_t srcBLen, - q31_t* pDst); - - -/** - * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ -void arm_conv_fast_q31( - q31_t* pSrcA, - uint32_t srcALen, - q31_t* pSrcB, - uint32_t srcBLen, - q31_t* pDst); - - -/** -* @brief Convolution of Q7 sequences. -* @param[in] pSrcA points to the first input sequence. -* @param[in] srcALen length of the first input sequence. -* @param[in] pSrcB points to the second input sequence. -* @param[in] srcBLen length of the second input sequence. -* @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. -* @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. -* @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). -*/ -void arm_conv_opt_q7( - q7_t* pSrcA, - uint32_t srcALen, - q7_t* pSrcB, - uint32_t srcBLen, - q7_t* pDst, - q15_t* pScratch1, - q15_t* pScratch2); - - -/** - * @brief Convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ -void arm_conv_q7( - q7_t* pSrcA, - uint32_t srcALen, - q7_t* pSrcB, - uint32_t srcBLen, - q7_t* pDst); - - -/** - * @brief Partial convolution of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ -arm_status arm_conv_partial_f32( - float32_t* pSrcA, - uint32_t srcALen, - float32_t* pSrcB, - uint32_t srcBLen, - float32_t* pDst, - uint32_t firstIndex, - uint32_t numPoints); - - -/** - * @brief Partial convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ -arm_status arm_conv_partial_opt_q15( - q15_t* pSrcA, - uint32_t srcALen, - q15_t* pSrcB, - uint32_t srcBLen, - q15_t* pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t* pScratch1, - q15_t* pScratch2); - - -/** - * @brief Partial convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ -arm_status arm_conv_partial_q15( - q15_t* pSrcA, - uint32_t srcALen, - q15_t* pSrcB, - uint32_t srcBLen, - q15_t* pDst, - uint32_t firstIndex, - uint32_t numPoints); - - -/** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ -arm_status arm_conv_partial_fast_q15( - q15_t* pSrcA, - uint32_t srcALen, - q15_t* pSrcB, - uint32_t srcBLen, - q15_t* pDst, - uint32_t firstIndex, - uint32_t numPoints); - - -/** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ -arm_status arm_conv_partial_fast_opt_q15( - q15_t* pSrcA, - uint32_t srcALen, - q15_t* pSrcB, - uint32_t srcBLen, - q15_t* pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t* pScratch1, - q15_t* pScratch2); - - -/** - * @brief Partial convolution of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ -arm_status arm_conv_partial_q31( - q31_t* pSrcA, - uint32_t srcALen, - q31_t* pSrcB, - uint32_t srcBLen, - q31_t* pDst, - uint32_t firstIndex, - uint32_t numPoints); - - -/** - * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ -arm_status arm_conv_partial_fast_q31( - q31_t* pSrcA, - uint32_t srcALen, - q31_t* pSrcB, - uint32_t srcBLen, - q31_t* pDst, - uint32_t firstIndex, - uint32_t numPoints); - - -/** - * @brief Partial convolution of Q7 sequences - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ -arm_status arm_conv_partial_opt_q7( - q7_t* pSrcA, - uint32_t srcALen, - q7_t* pSrcB, - uint32_t srcBLen, - q7_t* pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t* pScratch1, - q15_t* pScratch2); - - -/** - * @brief Partial convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ -arm_status arm_conv_partial_q7( - q7_t* pSrcA, - uint32_t srcALen, - q7_t* pSrcB, - uint32_t srcBLen, - q7_t* pDst, - uint32_t firstIndex, - uint32_t numPoints); - - -/** - * @brief Instance structure for the Q15 FIR decimator. - */ -typedef struct { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q15_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ -} arm_fir_decimate_instance_q15; - -/** - * @brief Instance structure for the Q31 FIR decimator. - */ -typedef struct { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q31_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ -} arm_fir_decimate_instance_q31; - -/** - * @brief Instance structure for the floating-point FIR decimator. - */ -typedef struct { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - float32_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ -} arm_fir_decimate_instance_f32; - - -/** - * @brief Processing function for the floating-point FIR decimator. - * @param[in] S points to an instance of the floating-point FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ -void arm_fir_decimate_f32( - const arm_fir_decimate_instance_f32* S, - float32_t* pSrc, - float32_t* pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the floating-point FIR decimator. - * @param[in,out] S points to an instance of the floating-point FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ -arm_status arm_fir_decimate_init_f32( - arm_fir_decimate_instance_f32* S, - uint16_t numTaps, - uint8_t M, - float32_t* pCoeffs, - float32_t* pState, - uint32_t blockSize); - - -/** - * @brief Processing function for the Q15 FIR decimator. - * @param[in] S points to an instance of the Q15 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ -void arm_fir_decimate_q15( - const arm_fir_decimate_instance_q15* S, - q15_t* pSrc, - q15_t* pDst, - uint32_t blockSize); - - -/** - * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ -void arm_fir_decimate_fast_q15( - const arm_fir_decimate_instance_q15* S, - q15_t* pSrc, - q15_t* pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 FIR decimator. - * @param[in,out] S points to an instance of the Q15 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ -arm_status arm_fir_decimate_init_q15( - arm_fir_decimate_instance_q15* S, - uint16_t numTaps, - uint8_t M, - q15_t* pCoeffs, - q15_t* pState, - uint32_t blockSize); - - -/** - * @brief Processing function for the Q31 FIR decimator. - * @param[in] S points to an instance of the Q31 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ -void arm_fir_decimate_q31( - const arm_fir_decimate_instance_q31* S, - q31_t* pSrc, - q31_t* pDst, - uint32_t blockSize); - -/** - * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ -void arm_fir_decimate_fast_q31( - arm_fir_decimate_instance_q31* S, - q31_t* pSrc, - q31_t* pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q31 FIR decimator. - * @param[in,out] S points to an instance of the Q31 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ -arm_status arm_fir_decimate_init_q31( - arm_fir_decimate_instance_q31* S, - uint16_t numTaps, - uint8_t M, - q31_t* pCoeffs, - q31_t* pState, - uint32_t blockSize); - - -/** - * @brief Instance structure for the Q15 FIR interpolator. - */ -typedef struct { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q15_t* pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q15_t* pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ -} arm_fir_interpolate_instance_q15; - -/** - * @brief Instance structure for the Q31 FIR interpolator. - */ -typedef struct { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q31_t* pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q31_t* pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ -} arm_fir_interpolate_instance_q31; - -/** - * @brief Instance structure for the floating-point FIR interpolator. - */ -typedef struct { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - float32_t* pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - float32_t* pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ -} arm_fir_interpolate_instance_f32; - - -/** - * @brief Processing function for the Q15 FIR interpolator. - * @param[in] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ -void arm_fir_interpolate_q15( - const arm_fir_interpolate_instance_q15* S, - q15_t* pSrc, - q15_t* pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 FIR interpolator. - * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ -arm_status arm_fir_interpolate_init_q15( - arm_fir_interpolate_instance_q15* S, - uint8_t L, - uint16_t numTaps, - q15_t* pCoeffs, - q15_t* pState, - uint32_t blockSize); - - -/** - * @brief Processing function for the Q31 FIR interpolator. - * @param[in] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ -void arm_fir_interpolate_q31( - const arm_fir_interpolate_instance_q31* S, - q31_t* pSrc, - q31_t* pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q31 FIR interpolator. - * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ -arm_status arm_fir_interpolate_init_q31( - arm_fir_interpolate_instance_q31* S, - uint8_t L, - uint16_t numTaps, - q31_t* pCoeffs, - q31_t* pState, - uint32_t blockSize); - - -/** - * @brief Processing function for the floating-point FIR interpolator. - * @param[in] S points to an instance of the floating-point FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ -void arm_fir_interpolate_f32( - const arm_fir_interpolate_instance_f32* S, - float32_t* pSrc, - float32_t* pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the floating-point FIR interpolator. - * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ -arm_status arm_fir_interpolate_init_f32( - arm_fir_interpolate_instance_f32* S, - uint8_t L, - uint16_t numTaps, - float32_t* pCoeffs, - float32_t* pState, - uint32_t blockSize); - - -/** - * @brief Instance structure for the high precision Q31 Biquad cascade filter. - */ -typedef struct { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q63_t* pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t* pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ -} arm_biquad_cas_df1_32x64_ins_q31; - - -/** - * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ -void arm_biquad_cas_df1_32x64_q31( - const arm_biquad_cas_df1_32x64_ins_q31* S, - q31_t* pSrc, - q31_t* pDst, - uint32_t blockSize); - - -/** - * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format - */ -void arm_biquad_cas_df1_32x64_init_q31( - arm_biquad_cas_df1_32x64_ins_q31* S, - uint8_t numStages, - q31_t* pCoeffs, - q63_t* pState, - uint8_t postShift); - - -/** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ -typedef struct { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t* pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float32_t* pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ -} arm_biquad_cascade_df2T_instance_f32; - -/** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ -typedef struct { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t* pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t* pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ -} arm_biquad_cascade_stereo_df2T_instance_f32; - -/** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ -typedef struct { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float64_t* pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float64_t* pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ -} arm_biquad_cascade_df2T_instance_f64; - - -/** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ -void arm_biquad_cascade_df2T_f32( - const arm_biquad_cascade_df2T_instance_f32* S, - float32_t* pSrc, - float32_t* pDst, - uint32_t blockSize); - - -/** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ -void arm_biquad_cascade_stereo_df2T_f32( - const arm_biquad_cascade_stereo_df2T_instance_f32* S, - float32_t* pSrc, - float32_t* pDst, - uint32_t blockSize); - - -/** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ -void arm_biquad_cascade_df2T_f64( - const arm_biquad_cascade_df2T_instance_f64* S, - float64_t* pSrc, - float64_t* pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ -void arm_biquad_cascade_df2T_init_f32( - arm_biquad_cascade_df2T_instance_f32* S, - uint8_t numStages, - float32_t* pCoeffs, - float32_t* pState); - - -/** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ -void arm_biquad_cascade_stereo_df2T_init_f32( - arm_biquad_cascade_stereo_df2T_instance_f32* S, - uint8_t numStages, - float32_t* pCoeffs, - float32_t* pState); - - -/** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ -void arm_biquad_cascade_df2T_init_f64( - arm_biquad_cascade_df2T_instance_f64* S, - uint8_t numStages, - float64_t* pCoeffs, - float64_t* pState); - - -/** - * @brief Instance structure for the Q15 FIR lattice filter. - */ -typedef struct { - uint16_t numStages; /**< number of filter stages. */ - q15_t* pState; /**< points to the state variable array. The array is of length numStages. */ - q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ -} arm_fir_lattice_instance_q15; - -/** - * @brief Instance structure for the Q31 FIR lattice filter. - */ -typedef struct { - uint16_t numStages; /**< number of filter stages. */ - q31_t* pState; /**< points to the state variable array. The array is of length numStages. */ - q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ -} arm_fir_lattice_instance_q31; - -/** - * @brief Instance structure for the floating-point FIR lattice filter. - */ -typedef struct { - uint16_t numStages; /**< number of filter stages. */ - float32_t* pState; /**< points to the state variable array. The array is of length numStages. */ - float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ -} arm_fir_lattice_instance_f32; - - -/** - * @brief Initialization function for the Q15 FIR lattice filter. - * @param[in] S points to an instance of the Q15 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ -void arm_fir_lattice_init_q15( - arm_fir_lattice_instance_q15* S, - uint16_t numStages, - q15_t* pCoeffs, - q15_t* pState); - - -/** - * @brief Processing function for the Q15 FIR lattice filter. - * @param[in] S points to an instance of the Q15 FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ -void arm_fir_lattice_q15( - const arm_fir_lattice_instance_q15* S, - q15_t* pSrc, - q15_t* pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q31 FIR lattice filter. - * @param[in] S points to an instance of the Q31 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ -void arm_fir_lattice_init_q31( - arm_fir_lattice_instance_q31* S, - uint16_t numStages, - q31_t* pCoeffs, - q31_t* pState); - - -/** - * @brief Processing function for the Q31 FIR lattice filter. - * @param[in] S points to an instance of the Q31 FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ -void arm_fir_lattice_q31( - const arm_fir_lattice_instance_q31* S, - q31_t* pSrc, - q31_t* pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the floating-point FIR lattice filter. - * @param[in] S points to an instance of the floating-point FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ -void arm_fir_lattice_init_f32( - arm_fir_lattice_instance_f32* S, - uint16_t numStages, - float32_t* pCoeffs, - float32_t* pState); - - -/** - * @brief Processing function for the floating-point FIR lattice filter. - * @param[in] S points to an instance of the floating-point FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ -void arm_fir_lattice_f32( - const arm_fir_lattice_instance_f32* S, - float32_t* pSrc, - float32_t* pDst, - uint32_t blockSize); - - -/** - * @brief Instance structure for the Q15 IIR lattice filter. - */ -typedef struct { - uint16_t numStages; /**< number of stages in the filter. */ - q15_t* pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q15_t* pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q15_t* pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ -} arm_iir_lattice_instance_q15; - -/** - * @brief Instance structure for the Q31 IIR lattice filter. - */ -typedef struct { - uint16_t numStages; /**< number of stages in the filter. */ - q31_t* pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q31_t* pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q31_t* pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ -} arm_iir_lattice_instance_q31; - -/** - * @brief Instance structure for the floating-point IIR lattice filter. - */ -typedef struct { - uint16_t numStages; /**< number of stages in the filter. */ - float32_t* pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - float32_t* pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - float32_t* pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ -} arm_iir_lattice_instance_f32; - - -/** - * @brief Processing function for the floating-point IIR lattice filter. - * @param[in] S points to an instance of the floating-point IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ -void arm_iir_lattice_f32( - const arm_iir_lattice_instance_f32* S, - float32_t* pSrc, - float32_t* pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the floating-point IIR lattice filter. - * @param[in] S points to an instance of the floating-point IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. - * @param[in] blockSize number of samples to process. - */ -void arm_iir_lattice_init_f32( - arm_iir_lattice_instance_f32* S, - uint16_t numStages, - float32_t* pkCoeffs, - float32_t* pvCoeffs, - float32_t* pState, - uint32_t blockSize); - - -/** - * @brief Processing function for the Q31 IIR lattice filter. - * @param[in] S points to an instance of the Q31 IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ -void arm_iir_lattice_q31( - const arm_iir_lattice_instance_q31* S, - q31_t* pSrc, - q31_t* pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q31 IIR lattice filter. - * @param[in] S points to an instance of the Q31 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process. - */ -void arm_iir_lattice_init_q31( - arm_iir_lattice_instance_q31* S, - uint16_t numStages, - q31_t* pkCoeffs, - q31_t* pvCoeffs, - q31_t* pState, - uint32_t blockSize); - - -/** - * @brief Processing function for the Q15 IIR lattice filter. - * @param[in] S points to an instance of the Q15 IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ -void arm_iir_lattice_q15( - const arm_iir_lattice_instance_q15* S, - q15_t* pSrc, - q15_t* pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 IIR lattice filter. - * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process per call. - */ -void arm_iir_lattice_init_q15( - arm_iir_lattice_instance_q15* S, - uint16_t numStages, - q15_t* pkCoeffs, - q15_t* pvCoeffs, - q15_t* pState, - uint32_t blockSize); - - -/** - * @brief Instance structure for the floating-point LMS filter. - */ -typedef struct { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that controls filter coefficient updates. */ -} arm_lms_instance_f32; - - -/** - * @brief Processing function for floating-point LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ -void arm_lms_f32( - const arm_lms_instance_f32* S, - float32_t* pSrc, - float32_t* pRef, - float32_t* pOut, - float32_t* pErr, - uint32_t blockSize); - - -/** - * @brief Initialization function for floating-point LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to the coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - */ -void arm_lms_init_f32( - arm_lms_instance_f32* S, - uint16_t numTaps, - float32_t* pCoeffs, - float32_t* pState, - float32_t mu, - uint32_t blockSize); - - -/** - * @brief Instance structure for the Q15 LMS filter. - */ -typedef struct { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ -} arm_lms_instance_q15; - - -/** - * @brief Initialization function for the Q15 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to the coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ -void arm_lms_init_q15( - arm_lms_instance_q15* S, - uint16_t numTaps, - q15_t* pCoeffs, - q15_t* pState, - q15_t mu, - uint32_t blockSize, - uint32_t postShift); - - -/** - * @brief Processing function for Q15 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ -void arm_lms_q15( - const arm_lms_instance_q15* S, - q15_t* pSrc, - q15_t* pRef, - q15_t* pOut, - q15_t* pErr, - uint32_t blockSize); - - -/** - * @brief Instance structure for the Q31 LMS filter. - */ -typedef struct { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ -} arm_lms_instance_q31; - - -/** - * @brief Processing function for Q31 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ -void arm_lms_q31( - const arm_lms_instance_q31* S, - q31_t* pSrc, - q31_t* pRef, - q31_t* pOut, - q31_t* pErr, - uint32_t blockSize); - - -/** - * @brief Initialization function for Q31 LMS filter. - * @param[in] S points to an instance of the Q31 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ -void arm_lms_init_q31( - arm_lms_instance_q31* S, - uint16_t numTaps, - q31_t* pCoeffs, - q31_t* pState, - q31_t mu, - uint32_t blockSize, - uint32_t postShift); - - -/** - * @brief Instance structure for the floating-point normalized LMS filter. - */ -typedef struct { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that control filter coefficient updates. */ - float32_t energy; /**< saves previous frame energy. */ - float32_t x0; /**< saves previous input sample. */ -} arm_lms_norm_instance_f32; - - -/** - * @brief Processing function for floating-point normalized LMS filter. - * @param[in] S points to an instance of the floating-point normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ -void arm_lms_norm_f32( - arm_lms_norm_instance_f32* S, - float32_t* pSrc, - float32_t* pRef, - float32_t* pOut, - float32_t* pErr, - uint32_t blockSize); - - -/** - * @brief Initialization function for floating-point normalized LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - */ -void arm_lms_norm_init_f32( - arm_lms_norm_instance_f32* S, - uint16_t numTaps, - float32_t* pCoeffs, - float32_t* pState, - float32_t mu, - uint32_t blockSize); - - -/** - * @brief Instance structure for the Q31 normalized LMS filter. - */ -typedef struct { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q31_t* recipTable; /**< points to the reciprocal initial value table. */ - q31_t energy; /**< saves previous frame energy. */ - q31_t x0; /**< saves previous input sample. */ -} arm_lms_norm_instance_q31; - - -/** - * @brief Processing function for Q31 normalized LMS filter. - * @param[in] S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ -void arm_lms_norm_q31( - arm_lms_norm_instance_q31* S, - q31_t* pSrc, - q31_t* pRef, - q31_t* pOut, - q31_t* pErr, - uint32_t blockSize); - - -/** - * @brief Initialization function for Q31 normalized LMS filter. - * @param[in] S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ -void arm_lms_norm_init_q31( - arm_lms_norm_instance_q31* S, - uint16_t numTaps, - q31_t* pCoeffs, - q31_t* pState, - q31_t mu, - uint32_t blockSize, - uint8_t postShift); - - -/** - * @brief Instance structure for the Q15 normalized LMS filter. - */ -typedef struct { - uint16_t numTaps; /**< Number of coefficients in the filter. */ - q15_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q15_t* recipTable; /**< Points to the reciprocal initial value table. */ - q15_t energy; /**< saves previous frame energy. */ - q15_t x0; /**< saves previous input sample. */ -} arm_lms_norm_instance_q15; - - -/** - * @brief Processing function for Q15 normalized LMS filter. - * @param[in] S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ -void arm_lms_norm_q15( - arm_lms_norm_instance_q15* S, - q15_t* pSrc, - q15_t* pRef, - q15_t* pOut, - q15_t* pErr, - uint32_t blockSize); - - -/** - * @brief Initialization function for Q15 normalized LMS filter. - * @param[in] S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ -void arm_lms_norm_init_q15( - arm_lms_norm_instance_q15* S, - uint16_t numTaps, - q15_t* pCoeffs, - q15_t* pState, - q15_t mu, - uint32_t blockSize, - uint8_t postShift); - - -/** - * @brief Correlation of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ -void arm_correlate_f32( - float32_t* pSrcA, - uint32_t srcALen, - float32_t* pSrcB, - uint32_t srcBLen, - float32_t* pDst); - - -/** -* @brief Correlation of Q15 sequences -* @param[in] pSrcA points to the first input sequence. -* @param[in] srcALen length of the first input sequence. -* @param[in] pSrcB points to the second input sequence. -* @param[in] srcBLen length of the second input sequence. -* @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. -* @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. -*/ -void arm_correlate_opt_q15( - q15_t* pSrcA, - uint32_t srcALen, - q15_t* pSrcB, - uint32_t srcBLen, - q15_t* pDst, - q15_t* pScratch); - - -/** - * @brief Correlation of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - -void arm_correlate_q15( - q15_t* pSrcA, - uint32_t srcALen, - q15_t* pSrcB, - uint32_t srcBLen, - q15_t* pDst); - - -/** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - -void arm_correlate_fast_q15( - q15_t* pSrcA, - uint32_t srcALen, - q15_t* pSrcB, - uint32_t srcBLen, - q15_t* pDst); - - -/** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - */ -void arm_correlate_fast_opt_q15( - q15_t* pSrcA, - uint32_t srcALen, - q15_t* pSrcB, - uint32_t srcBLen, - q15_t* pDst, - q15_t* pScratch); - - -/** - * @brief Correlation of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ -void arm_correlate_q31( - q31_t* pSrcA, - uint32_t srcALen, - q31_t* pSrcB, - uint32_t srcBLen, - q31_t* pDst); - - -/** - * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ -void arm_correlate_fast_q31( - q31_t* pSrcA, - uint32_t srcALen, - q31_t* pSrcB, - uint32_t srcBLen, - q31_t* pDst); - - -/** - * @brief Correlation of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - */ -void arm_correlate_opt_q7( - q7_t* pSrcA, - uint32_t srcALen, - q7_t* pSrcB, - uint32_t srcBLen, - q7_t* pDst, - q15_t* pScratch1, - q15_t* pScratch2); - - -/** - * @brief Correlation of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ -void arm_correlate_q7( - q7_t* pSrcA, - uint32_t srcALen, - q7_t* pSrcB, - uint32_t srcBLen, - q7_t* pDst); - - -/** - * @brief Instance structure for the floating-point sparse FIR filter. - */ -typedef struct { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - float32_t* pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t* pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ -} arm_fir_sparse_instance_f32; - -/** - * @brief Instance structure for the Q31 sparse FIR filter. - */ -typedef struct { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q31_t* pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t* pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ -} arm_fir_sparse_instance_q31; - -/** - * @brief Instance structure for the Q15 sparse FIR filter. - */ -typedef struct { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q15_t* pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t* pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ -} arm_fir_sparse_instance_q15; - -/** - * @brief Instance structure for the Q7 sparse FIR filter. - */ -typedef struct { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q7_t* pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q7_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t* pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ -} arm_fir_sparse_instance_q7; - - -/** - * @brief Processing function for the floating-point sparse FIR filter. - * @param[in] S points to an instance of the floating-point sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ -void arm_fir_sparse_f32( - arm_fir_sparse_instance_f32* S, - float32_t* pSrc, - float32_t* pDst, - float32_t* pScratchIn, - uint32_t blockSize); - - -/** - * @brief Initialization function for the floating-point sparse FIR filter. - * @param[in,out] S points to an instance of the floating-point sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ -void arm_fir_sparse_init_f32( - arm_fir_sparse_instance_f32* S, - uint16_t numTaps, - float32_t* pCoeffs, - float32_t* pState, - int32_t* pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - -/** - * @brief Processing function for the Q31 sparse FIR filter. - * @param[in] S points to an instance of the Q31 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ -void arm_fir_sparse_q31( - arm_fir_sparse_instance_q31* S, - q31_t* pSrc, - q31_t* pDst, - q31_t* pScratchIn, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q31 sparse FIR filter. - * @param[in,out] S points to an instance of the Q31 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ -void arm_fir_sparse_init_q31( - arm_fir_sparse_instance_q31* S, - uint16_t numTaps, - q31_t* pCoeffs, - q31_t* pState, - int32_t* pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - -/** - * @brief Processing function for the Q15 sparse FIR filter. - * @param[in] S points to an instance of the Q15 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ -void arm_fir_sparse_q15( - arm_fir_sparse_instance_q15* S, - q15_t* pSrc, - q15_t* pDst, - q15_t* pScratchIn, - q31_t* pScratchOut, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 sparse FIR filter. - * @param[in,out] S points to an instance of the Q15 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ -void arm_fir_sparse_init_q15( - arm_fir_sparse_instance_q15* S, - uint16_t numTaps, - q15_t* pCoeffs, - q15_t* pState, - int32_t* pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - -/** - * @brief Processing function for the Q7 sparse FIR filter. - * @param[in] S points to an instance of the Q7 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ -void arm_fir_sparse_q7( - arm_fir_sparse_instance_q7* S, - q7_t* pSrc, - q7_t* pDst, - q7_t* pScratchIn, - q31_t* pScratchOut, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q7 sparse FIR filter. - * @param[in,out] S points to an instance of the Q7 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ -void arm_fir_sparse_init_q7( - arm_fir_sparse_instance_q7* S, - uint16_t numTaps, - q7_t* pCoeffs, - q7_t* pState, - int32_t* pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - -/** - * @brief Floating-point sin_cos function. - * @param[in] theta input value in degrees - * @param[out] pSinVal points to the processed sine output. - * @param[out] pCosVal points to the processed cos output. - */ -void arm_sin_cos_f32( - float32_t theta, - float32_t* pSinVal, - float32_t* pCosVal); - - -/** - * @brief Q31 sin_cos function. - * @param[in] theta scaled input value in degrees - * @param[out] pSinVal points to the processed sine output. - * @param[out] pCosVal points to the processed cosine output. - */ -void arm_sin_cos_q31( - q31_t theta, - q31_t* pSinVal, - q31_t* pCosVal); - - -/** - * @brief Floating-point complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ -void arm_cmplx_conj_f32( - float32_t* pSrc, - float32_t* pDst, - uint32_t numSamples); - -/** - * @brief Q31 complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ -void arm_cmplx_conj_q31( - q31_t* pSrc, - q31_t* pDst, - uint32_t numSamples); - - -/** - * @brief Q15 complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ -void arm_cmplx_conj_q15( - q15_t* pSrc, - q15_t* pDst, - uint32_t numSamples); - - -/** - * @brief Floating-point complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ -void arm_cmplx_mag_squared_f32( - float32_t* pSrc, - float32_t* pDst, - uint32_t numSamples); - - -/** - * @brief Q31 complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ -void arm_cmplx_mag_squared_q31( - q31_t* pSrc, - q31_t* pDst, - uint32_t numSamples); - - -/** - * @brief Q15 complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ -void arm_cmplx_mag_squared_q15( - q15_t* pSrc, - q15_t* pDst, - uint32_t numSamples); - - -/** - * @ingroup groupController - */ - -/** - * @defgroup PID PID Motor Control - * - * A Proportional Integral Derivative (PID) controller is a generic feedback control - * loop mechanism widely used in industrial control systems. - * A PID controller is the most commonly used type of feedback controller. - * - * This set of functions implements (PID) controllers - * for Q15, Q31, and floating-point data types. The functions operate on a single sample - * of data and each call to the function returns a single processed value. - * S points to an instance of the PID control data structure. in - * is the input sample value. The functions return the output value. - * - * \par Algorithm: - * 
- *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
- *    A0 = Kp + Ki + Kd
- *    A1 = (-Kp ) - (2 * Kd )
- *    A2 = Kd
- * - * \par - * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant - * - * \par - * \image html PID.gif "Proportional Integral Derivative Controller" - * - * \par - * The PID controller calculates an "error" value as the difference between - * the measured output and the reference input. - * The controller attempts to minimize the error by adjusting the process control inputs. - * The proportional value determines the reaction to the current error, - * the integral value determines the reaction based on the sum of recent errors, - * and the derivative value determines the reaction based on the rate at which the error has been changing. - * - * \par Instance Structure - * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. - * A separate instance structure must be defined for each PID Controller. - * There are separate instance structure declarations for each of the 3 supported data types. - * - * \par Reset Functions - * There is also an associated reset function for each data type which clears the state array. - * - * \par Initialization Functions - * There is also an associated initialization function for each data type. - * The initialization function performs the following operations: - * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. - * - Zeros out the values in the state buffer. - * - * \par - * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. - * - * \par Fixed-Point Behavior - * Care must be taken when using the fixed-point versions of the PID Controller functions. - * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - -/** - * @addtogroup PID - * @{ - */ - -/** - * @brief Process function for the floating-point PID Control. - * @param[in,out] S is an instance of the floating-point PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - */ -CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32( - arm_pid_instance_f32* S, - float32_t in) -{ - float32_t out; - - /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ - out = (S->A0 * in) + - (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - -} - -/** - * @brief Process function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q31 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 64-bit accumulator. - * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. - * Thus, if the accumulator result overflows it wraps around rather than clip. - * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. - * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. - */ -CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31( - arm_pid_instance_q31* S, - q31_t in) -{ - q63_t acc; - q31_t out; - - /* acc = A0 * x[n] */ - acc = (q63_t) S->A0 * in; - - /* acc += A1 * x[n-1] */ - acc += (q63_t) S->A1 * S->state[0]; - - /* acc += A2 * x[n-2] */ - acc += (q63_t) S->A2 * S->state[1]; - - /* convert output to 1.31 format to add y[n-1] */ - out = (q31_t) (acc >> 31u); - - /* out += y[n-1] */ - out += S->state[2]; - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); -} - - -/** - * @brief Process function for the Q15 PID Control. - * @param[in,out] S points to an instance of the Q15 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using a 64-bit internal accumulator. - * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. - * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. - * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. - * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. - * Lastly, the accumulator is saturated to yield a result in 1.15 format. - */ -CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15( - arm_pid_instance_q15* S, - q15_t in) -{ - q63_t acc; - q15_t out; - -#if defined (ARM_MATH_DSP) - __SIMD32_TYPE* vstate; - - /* Implementation of PID controller */ - - /* acc = A0 * x[n] */ - acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - vstate = __SIMD32_CONST(S->state); - acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t) * vstate, (uint64_t)acc); -#else - /* acc = A0 * x[n] */ - acc = ((q31_t) S->A0) * in; - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - acc += (q31_t) S->A1 * S->state[0]; - acc += (q31_t) S->A2 * S->state[1]; -#endif - - /* acc += y[n-1] */ - acc += (q31_t) S->state[2] << 15; - - /* saturate the output */ - out = (q15_t) (__SSAT((acc >> 15), 16)); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); -} - -/** - * @} end of PID group - */ - - -/** - * @brief Floating-point matrix inverse. - * @param[in] src points to the instance of the input floating-point matrix structure. - * @param[out] dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ -arm_status arm_mat_inverse_f32( - const arm_matrix_instance_f32* src, - arm_matrix_instance_f32* dst); - - -/** - * @brief Floating-point matrix inverse. - * @param[in] src points to the instance of the input floating-point matrix structure. - * @param[out] dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ -arm_status arm_mat_inverse_f64( - const arm_matrix_instance_f64* src, - arm_matrix_instance_f64* dst); - - - -/** - * @ingroup groupController - */ - -/** - * @defgroup clarke Vector Clarke Transform - * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. - * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents - * in the two-phase orthogonal stator axis Ialpha and Ibeta. - * When Ialpha is superposed with Ia as shown in the figure below - * \image html clarke.gif Stator current space vector and its components in (a,b). - * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta - * can be calculated using only Ia and Ib. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeFormula.gif - * where Ia and Ib are the instantaneous stator phases and - * pIalpha and pIbeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - -/** - * @addtogroup clarke - * @{ - */ - -/** - * - * @brief Floating-point Clarke transform - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - */ -CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32( - float32_t Ia, - float32_t Ib, - float32_t* pIalpha, - float32_t* pIbeta) -{ - /* Calculate pIalpha using the equation, pIalpha = Ia */ - *pIalpha = Ia; - - /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ - *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); -} - - -/** - * @brief Clarke transform for Q31 version - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ -CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31( - q31_t Ia, - q31_t Ib, - q31_t* pIalpha, - q31_t* pIbeta) -{ - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIalpha from Ia by equation pIalpha = Ia */ - *pIalpha = Ia; - - /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); - - /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ - product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); - - /* pIbeta is calculated by adding the intermediate products */ - *pIbeta = __QADD(product1, product2); -} - -/** - * @} end of clarke group - */ - -/** - * @brief Converts the elements of the Q7 vector to Q31 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ -void arm_q7_to_q31( - q7_t* pSrc, - q31_t* pDst, - uint32_t blockSize); - - - -/** - * @ingroup groupController - */ - -/** - * @defgroup inv_clarke Vector Inverse Clarke Transform - * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeInvFormula.gif - * where pIa and pIb are the instantaneous stator phases and - * Ialpha and Ibeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - -/** - * @addtogroup inv_clarke - * @{ - */ - -/** -* @brief Floating-point Inverse Clarke transform -* @param[in] Ialpha input two-phase orthogonal vector axis alpha -* @param[in] Ibeta input two-phase orthogonal vector axis beta -* @param[out] pIa points to output three-phase coordinate a -* @param[out] pIb points to output three-phase coordinate b -*/ -CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t* pIa, - float32_t* pIb) -{ - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ - *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; -} - - -/** - * @brief Inverse Clarke transform for Q31 version - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] pIa points to output three-phase coordinate a - * @param[out] pIb points to output three-phase coordinate b - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the subtraction, hence there is no risk of overflow. - */ -CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t* pIa, - q31_t* pIb) -{ - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); - - /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); - - /* pIb is calculated by subtracting the products */ - *pIb = __QSUB(product2, product1); -} - -/** - * @} end of inv_clarke group - */ - -/** - * @brief Converts the elements of the Q7 vector to Q15 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ -void arm_q7_to_q15( - q7_t* pSrc, - q15_t* pDst, - uint32_t blockSize); - - - -/** - * @ingroup groupController - */ - -/** - * @defgroup park Vector Park Transform - * - * Forward Park transform converts the input two-coordinate vector to flux and torque components. - * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents - * from the stationary to the moving reference frame and control the spatial relationship between - * the stator vector current and rotor flux vector. - * If we consider the d axis aligned with the rotor flux, the diagram below shows the - * current vector and the relationship from the two reference frames: - * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkFormula.gif - * where Ialpha and Ibeta are the stator vector components, - * pId and pIq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - -/** - * @addtogroup park - * @{ - */ - -/** - * @brief Floating-point Park transform - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] pId points to output rotor reference frame d - * @param[out] pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * The function implements the forward Park transform. - * - */ -CMSIS_INLINE __STATIC_INLINE void arm_park_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t* pId, - float32_t* pIq, - float32_t sinVal, - float32_t cosVal) -{ - /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ - *pId = Ialpha * cosVal + Ibeta * sinVal; - - /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ - *pIq = -Ialpha * sinVal + Ibeta * cosVal; -} - - -/** - * @brief Park transform for Q31 version - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] pId points to output rotor reference frame d - * @param[out] pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition and subtraction, hence there is no risk of overflow. - */ -CMSIS_INLINE __STATIC_INLINE void arm_park_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t* pId, - q31_t* pIq, - q31_t sinVal, - q31_t cosVal) -{ - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Ialpha * cosVal) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * sinVal) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Ialpha * sinVal) */ - product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * cosVal) */ - product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); - - /* Calculate pId by adding the two intermediate products 1 and 2 */ - *pId = __QADD(product1, product2); - - /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ - *pIq = __QSUB(product4, product3); -} - -/** - * @} end of park group - */ - -/** - * @brief Converts the elements of the Q7 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ -void arm_q7_to_float( - q7_t* pSrc, - float32_t* pDst, - uint32_t blockSize); - - -/** - * @ingroup groupController - */ - -/** - * @defgroup inv_park Vector Inverse Park transform - * Inverse Park transform converts the input flux and torque components to two-coordinate vector. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkInvFormula.gif - * where pIalpha and pIbeta are the stator vector components, - * Id and Iq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - -/** - * @addtogroup inv_park - * @{ - */ - -/** -* @brief Floating-point Inverse Park transform -* @param[in] Id input coordinate of rotor reference frame d -* @param[in] Iq input coordinate of rotor reference frame q -* @param[out] pIalpha points to output two-phase orthogonal vector axis alpha -* @param[out] pIbeta points to output two-phase orthogonal vector axis beta -* @param[in] sinVal sine value of rotation angle theta -* @param[in] cosVal cosine value of rotation angle theta -*/ -CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32( - float32_t Id, - float32_t Iq, - float32_t* pIalpha, - float32_t* pIbeta, - float32_t sinVal, - float32_t cosVal) -{ - /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ - *pIalpha = Id * cosVal - Iq * sinVal; - - /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ - *pIbeta = Id * sinVal + Iq * cosVal; -} - - -/** - * @brief Inverse Park transform for Q31 version - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ -CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31( - q31_t Id, - q31_t Iq, - q31_t* pIalpha, - q31_t* pIbeta, - q31_t sinVal, - q31_t cosVal) -{ - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Id * cosVal) */ - product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Iq * sinVal) */ - product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Id * sinVal) */ - product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Iq * cosVal) */ - product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); - - /* Calculate pIalpha by using the two intermediate products 1 and 2 */ - *pIalpha = __QSUB(product1, product2); - - /* Calculate pIbeta by using the two intermediate products 3 and 4 */ - *pIbeta = __QADD(product4, product3); -} - -/** - * @} end of Inverse park group - */ - - -/** - * @brief Converts the elements of the Q31 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ -void arm_q31_to_float( - q31_t* pSrc, - float32_t* pDst, - uint32_t blockSize); - -/** - * @ingroup groupInterpolation - */ - -/** - * @defgroup LinearInterpolate Linear Interpolation - * - * Linear interpolation is a method of curve fitting using linear polynomials. - * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line - * - * \par - * \image html LinearInterp.gif "Linear interpolation" - * - * \par - * A Linear Interpolate function calculates an output value(y), for the input(x) - * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) - * - * \par Algorithm: - * 
- *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
- *       where x0, x1 are nearest values of input x
- *             y0, y1 are nearest values to output y
- *
- * - * \par - * This set of functions implements Linear interpolation process - * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single - * sample of data and each call to the function returns a single processed value. - * S points to an instance of the Linear Interpolate function data structure. - * x is the input sample value. The functions returns the output value. - * - * \par - * if x is outside of the table boundary, Linear interpolation returns first value of the table - * if x is below input range and returns last value of table if x is above range. - */ - -/** - * @addtogroup LinearInterpolate - * @{ - */ - -/** - * @brief Process function for the floating-point Linear Interpolation Function. - * @param[in,out] S is an instance of the floating-point Linear Interpolation structure - * @param[in] x input sample to process - * @return y processed output sample. - * - */ -CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32( - arm_linear_interp_instance_f32* S, - float32_t x) -{ - float32_t y; - float32_t x0, x1; /* Nearest input values */ - float32_t y0, y1; /* Nearest output values */ - float32_t xSpacing = S->xSpacing; /* spacing between input values */ - int32_t i; /* Index variable */ - float32_t* pYData = S->pYData; /* pointer to output table */ - - /* Calculation of index */ - i = (int32_t) ((x - S->x1) / xSpacing); - - if (i < 0) { - /* Iniatilize output for below specified range as least output value of table */ - y = pYData[0]; - } - else if ((uint32_t)i >= S->nValues) { - /* Iniatilize output for above specified range as last output value of table */ - y = pYData[S->nValues - 1]; - } - else { - /* Calculation of nearest input values */ - x0 = S->x1 + i * xSpacing; - x1 = S->x1 + (i + 1) * xSpacing; - - /* Read of nearest output values */ - y0 = pYData[i]; - y1 = pYData[i + 1]; - - /* Calculation of output */ - y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); - - } - - /* returns output value */ - return (y); -} - - -/** -* -* @brief Process function for the Q31 Linear Interpolation Function. -* @param[in] pYData pointer to Q31 Linear Interpolation table -* @param[in] x input sample to process -* @param[in] nValues number of table values -* @return y processed output sample. -* -* \par -* Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. -* This function can support maximum of table size 2^12. -* -*/ -CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31( - q31_t* pYData, - q31_t x, - uint32_t nValues) -{ - q31_t y; /* output */ - q31_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & (q31_t)0xFFF00000) >> 20); - - if (index >= (int32_t)(nValues - 1)) { - return (pYData[nValues - 1]); - } - else if (index < 0) { - return (pYData[0]); - } - else { - /* 20 bits for the fractional part */ - /* shift left by 11 to keep fract in 1.31 format */ - fract = (x & 0x000FFFFF) << 11; - - /* Read two nearest output values from the index in 1.31(q31) format */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract) and y is in 2.30 format */ - y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); - - /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ - y += ((q31_t) (((q63_t) y1 * fract) >> 32)); - - /* Convert y to 1.31 format */ - return (y << 1u); - } -} - - -/** - * - * @brief Process function for the Q15 Linear Interpolation Function. - * @param[in] pYData pointer to Q15 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ -CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15( - q15_t* pYData, - q31_t x, - uint32_t nValues) -{ - q63_t y; /* output */ - q15_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & (int32_t)0xFFF00000) >> 20); - - if (index >= (int32_t)(nValues - 1)) { - return (pYData[nValues - 1]); - } - else if (index < 0) { - return (pYData[0]); - } - else { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract) and y is in 13.35 format */ - y = ((q63_t) y0 * (0xFFFFF - fract)); - - /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ - y += ((q63_t) y1 * (fract)); - - /* convert y to 1.15 format */ - return (q15_t) (y >> 20); - } -} - - -/** - * - * @brief Process function for the Q7 Linear Interpolation Function. - * @param[in] pYData pointer to Q7 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - */ -CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7( - q7_t* pYData, - q31_t x, - uint32_t nValues) -{ - q31_t y; /* output */ - q7_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - uint32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - if (x < 0) { - return (pYData[0]); - } - index = (x >> 20) & 0xfff; - - if (index >= (nValues - 1)) { - return (pYData[nValues - 1]); - } - else { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index and are in 1.7(q7) format */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ - y = ((y0 * (0xFFFFF - fract))); - - /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ - y += (y1 * fract); - - /* convert y to 1.7(q7) format */ - return (q7_t) (y >> 20); - } -} - -/** - * @} end of LinearInterpolate group - */ - -/** - * @brief Fast approximation to the trigonometric sine function for floating-point data. - * @param[in] x input value in radians. - * @return sin(x). - */ -float32_t arm_sin_f32( - float32_t x); - - -/** - * @brief Fast approximation to the trigonometric sine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ -q31_t arm_sin_q31( - q31_t x); - - -/** - * @brief Fast approximation to the trigonometric sine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ -q15_t arm_sin_q15( - q15_t x); - - -/** - * @brief Fast approximation to the trigonometric cosine function for floating-point data. - * @param[in] x input value in radians. - * @return cos(x). - */ -float32_t arm_cos_f32( - float32_t x); - - -/** - * @brief Fast approximation to the trigonometric cosine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ -q31_t arm_cos_q31( - q31_t x); - - -/** - * @brief Fast approximation to the trigonometric cosine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ -q15_t arm_cos_q15( - q15_t x); - - -/** - * @ingroup groupFastMath - */ - - -/** - * @defgroup SQRT Square Root - * - * Computes the square root of a number. - * There are separate functions for Q15, Q31, and floating-point data types. - * The square root function is computed using the Newton-Raphson algorithm. - * This is an iterative algorithm of the form: - * 
- *      x1 = x0 - f(x0)/f'(x0)
- *
- * where x1 is the current estimate, - * x0 is the previous estimate, and - * f'(x0) is the derivative of f() evaluated at x0. - * For the square root function, the algorithm reduces to: - * 
- *     x0 = in/2                         [initial guess]
- *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
- *
- */ - - -/** - * @addtogroup SQRT - * @{ - */ - -/** - * @brief Floating-point square root function. - * @param[in] in input value. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ -CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32( - float32_t in, - float32_t* pOut) -{ - if (in >= 0.0f) { - -#if (__FPU_USED == 1) && defined ( __CC_ARM ) - *pOut = __sqrtf(in); -#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - *pOut = __builtin_sqrtf(in); -#elif (__FPU_USED == 1) && defined(__GNUC__) - *pOut = __builtin_sqrtf(in); -#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) - __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); -#else - *pOut = sqrtf(in); -#endif - - return (ARM_MATH_SUCCESS); - } - else { - *pOut = 0.0f; - return (ARM_MATH_ARGUMENT_ERROR); - } -} - - -/** - * @brief Q31 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ -arm_status arm_sqrt_q31( - q31_t in, - q31_t* pOut); - - -/** - * @brief Q15 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ -arm_status arm_sqrt_q15( - q15_t in, - q15_t* pOut); - -/** - * @} end of SQRT group - */ - - -/** - * @brief floating-point Circular write function. - */ -CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32( - int32_t* circBuffer, - int32_t L, - uint16_t* writeOffset, - int32_t bufferInc, - const int32_t* src, - int32_t srcInc, - uint32_t blockSize) -{ - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0u) { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if (wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; -} - - - -/** - * @brief floating-point Circular Read function. - */ -CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32( - int32_t* circBuffer, - int32_t L, - int32_t* readOffset, - int32_t bufferInc, - int32_t* dst, - int32_t* dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) -{ - uint32_t i = 0u; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0u) { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if (dst == (int32_t*) dst_end) { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if (rOffset >= L) { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; -} - - -/** - * @brief Q15 Circular write function. - */ -CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15( - q15_t* circBuffer, - int32_t L, - uint16_t* writeOffset, - int32_t bufferInc, - const q15_t* src, - int32_t srcInc, - uint32_t blockSize) -{ - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0u) { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if (wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; -} - - -/** - * @brief Q15 Circular Read function. - */ -CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15( - q15_t* circBuffer, - int32_t L, - int32_t* readOffset, - int32_t bufferInc, - q15_t* dst, - q15_t* dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) -{ - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0u) { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if (dst == (q15_t*) dst_end) { - dst = dst_base; - } - - /* Circularly update wOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if (rOffset >= L) { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; -} - - -/** - * @brief Q7 Circular write function. - */ -CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7( - q7_t* circBuffer, - int32_t L, - uint16_t* writeOffset, - int32_t bufferInc, - const q7_t* src, - int32_t srcInc, - uint32_t blockSize) -{ - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0u) { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if (wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; -} - - -/** - * @brief Q7 Circular Read function. - */ -CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7( - q7_t* circBuffer, - int32_t L, - int32_t* readOffset, - int32_t bufferInc, - q7_t* dst, - q7_t* dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) -{ - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0u) { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if (dst == (q7_t*) dst_end) { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if (rOffset >= L) { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; -} - - -/** - * @brief Sum of the squares of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void arm_power_q31( - q31_t* pSrc, - uint32_t blockSize, - q63_t* pResult); - - -/** - * @brief Sum of the squares of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void arm_power_f32( - float32_t* pSrc, - uint32_t blockSize, - float32_t* pResult); - - -/** - * @brief Sum of the squares of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void arm_power_q15( - q15_t* pSrc, - uint32_t blockSize, - q63_t* pResult); - - -/** - * @brief Sum of the squares of the elements of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void arm_power_q7( - q7_t* pSrc, - uint32_t blockSize, - q31_t* pResult); - - -/** - * @brief Mean value of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void arm_mean_q7( - q7_t* pSrc, - uint32_t blockSize, - q7_t* pResult); - - -/** - * @brief Mean value of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void arm_mean_q15( - q15_t* pSrc, - uint32_t blockSize, - q15_t* pResult); - - -/** - * @brief Mean value of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void arm_mean_q31( - q31_t* pSrc, - uint32_t blockSize, - q31_t* pResult); - - -/** - * @brief Mean value of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void arm_mean_f32( - float32_t* pSrc, - uint32_t blockSize, - float32_t* pResult); - - -/** - * @brief Variance of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void arm_var_f32( - float32_t* pSrc, - uint32_t blockSize, - float32_t* pResult); - - -/** - * @brief Variance of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void arm_var_q31( - q31_t* pSrc, - uint32_t blockSize, - q31_t* pResult); - - -/** - * @brief Variance of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void arm_var_q15( - q15_t* pSrc, - uint32_t blockSize, - q15_t* pResult); - - -/** - * @brief Root Mean Square of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void arm_rms_f32( - float32_t* pSrc, - uint32_t blockSize, - float32_t* pResult); - - -/** - * @brief Root Mean Square of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void arm_rms_q31( - q31_t* pSrc, - uint32_t blockSize, - q31_t* pResult); - - -/** - * @brief Root Mean Square of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void arm_rms_q15( - q15_t* pSrc, - uint32_t blockSize, - q15_t* pResult); - - -/** - * @brief Standard deviation of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void arm_std_f32( - float32_t* pSrc, - uint32_t blockSize, - float32_t* pResult); - - -/** - * @brief Standard deviation of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void arm_std_q31( - q31_t* pSrc, - uint32_t blockSize, - q31_t* pResult); - - -/** - * @brief Standard deviation of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void arm_std_q15( - q15_t* pSrc, - uint32_t blockSize, - q15_t* pResult); - - -/** - * @brief Floating-point complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ -void arm_cmplx_mag_f32( - float32_t* pSrc, - float32_t* pDst, - uint32_t numSamples); - - -/** - * @brief Q31 complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ -void arm_cmplx_mag_q31( - q31_t* pSrc, - q31_t* pDst, - uint32_t numSamples); - - -/** - * @brief Q15 complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ -void arm_cmplx_mag_q15( - q15_t* pSrc, - q15_t* pDst, - uint32_t numSamples); - - -/** - * @brief Q15 complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ -void arm_cmplx_dot_prod_q15( - q15_t* pSrcA, - q15_t* pSrcB, - uint32_t numSamples, - q31_t* realResult, - q31_t* imagResult); - - -/** - * @brief Q31 complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ -void arm_cmplx_dot_prod_q31( - q31_t* pSrcA, - q31_t* pSrcB, - uint32_t numSamples, - q63_t* realResult, - q63_t* imagResult); - - -/** - * @brief Floating-point complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ -void arm_cmplx_dot_prod_f32( - float32_t* pSrcA, - float32_t* pSrcB, - uint32_t numSamples, - float32_t* realResult, - float32_t* imagResult); - - -/** - * @brief Q15 complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ -void arm_cmplx_mult_real_q15( - q15_t* pSrcCmplx, - q15_t* pSrcReal, - q15_t* pCmplxDst, - uint32_t numSamples); - - -/** - * @brief Q31 complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ -void arm_cmplx_mult_real_q31( - q31_t* pSrcCmplx, - q31_t* pSrcReal, - q31_t* pCmplxDst, - uint32_t numSamples); - - -/** - * @brief Floating-point complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ -void arm_cmplx_mult_real_f32( - float32_t* pSrcCmplx, - float32_t* pSrcReal, - float32_t* pCmplxDst, - uint32_t numSamples); - - -/** - * @brief Minimum value of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] result is output pointer - * @param[in] index is the array index of the minimum value in the input buffer. - */ -void arm_min_q7( - q7_t* pSrc, - uint32_t blockSize, - q7_t* result, - uint32_t* index); - - -/** - * @brief Minimum value of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[in] pIndex is the array index of the minimum value in the input buffer. - */ -void arm_min_q15( - q15_t* pSrc, - uint32_t blockSize, - q15_t* pResult, - uint32_t* pIndex); - - -/** - * @brief Minimum value of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[out] pIndex is the array index of the minimum value in the input buffer. - */ -void arm_min_q31( - q31_t* pSrc, - uint32_t blockSize, - q31_t* pResult, - uint32_t* pIndex); - - -/** - * @brief Minimum value of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[out] pIndex is the array index of the minimum value in the input buffer. - */ -void arm_min_f32( - float32_t* pSrc, - uint32_t blockSize, - float32_t* pResult, - uint32_t* pIndex); - - -/** - * @brief Maximum value of a Q7 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ -void arm_max_q7( - q7_t* pSrc, - uint32_t blockSize, - q7_t* pResult, - uint32_t* pIndex); - - -/** - * @brief Maximum value of a Q15 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ -void arm_max_q15( - q15_t* pSrc, - uint32_t blockSize, - q15_t* pResult, - uint32_t* pIndex); - - -/** - * @brief Maximum value of a Q31 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ -void arm_max_q31( - q31_t* pSrc, - uint32_t blockSize, - q31_t* pResult, - uint32_t* pIndex); - - -/** - * @brief Maximum value of a floating-point vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ -void arm_max_f32( - float32_t* pSrc, - uint32_t blockSize, - float32_t* pResult, - uint32_t* pIndex); - - -/** - * @brief Q15 complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ -void arm_cmplx_mult_cmplx_q15( - q15_t* pSrcA, - q15_t* pSrcB, - q15_t* pDst, - uint32_t numSamples); - - -/** - * @brief Q31 complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ -void arm_cmplx_mult_cmplx_q31( - q31_t* pSrcA, - q31_t* pSrcB, - q31_t* pDst, - uint32_t numSamples); - - -/** - * @brief Floating-point complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ -void arm_cmplx_mult_cmplx_f32( - float32_t* pSrcA, - float32_t* pSrcB, - float32_t* pDst, - uint32_t numSamples); - - -/** - * @brief Converts the elements of the floating-point vector to Q31 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q31 output vector - * @param[in] blockSize length of the input vector - */ -void arm_float_to_q31( - float32_t* pSrc, - q31_t* pDst, - uint32_t blockSize); - - -/** - * @brief Converts the elements of the floating-point vector to Q15 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q15 output vector - * @param[in] blockSize length of the input vector - */ -void arm_float_to_q15( - float32_t* pSrc, - q15_t* pDst, - uint32_t blockSize); - - -/** - * @brief Converts the elements of the floating-point vector to Q7 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q7 output vector - * @param[in] blockSize length of the input vector - */ -void arm_float_to_q7( - float32_t* pSrc, - q7_t* pDst, - uint32_t blockSize); - - -/** - * @brief Converts the elements of the Q31 vector to Q15 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ -void arm_q31_to_q15( - q31_t* pSrc, - q15_t* pDst, - uint32_t blockSize); - - -/** - * @brief Converts the elements of the Q31 vector to Q7 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ -void arm_q31_to_q7( - q31_t* pSrc, - q7_t* pDst, - uint32_t blockSize); - - -/** - * @brief Converts the elements of the Q15 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ -void arm_q15_to_float( - q15_t* pSrc, - float32_t* pDst, - uint32_t blockSize); - - -/** - * @brief Converts the elements of the Q15 vector to Q31 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ -void arm_q15_to_q31( - q15_t* pSrc, - q31_t* pDst, - uint32_t blockSize); - - -/** - * @brief Converts the elements of the Q15 vector to Q7 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ -void arm_q15_to_q7( - q15_t* pSrc, - q7_t* pDst, - uint32_t blockSize); - - -/** - * @ingroup groupInterpolation - */ - -/** - * @defgroup BilinearInterpolate Bilinear Interpolation - * - * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. - * The underlying function f(x, y) is sampled on a regular grid and the interpolation process - * determines values between the grid points. - * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. - * Bilinear interpolation is often used in image processing to rescale images. - * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. - * - * Algorithm - * \par - * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. - * For floating-point, the instance structure is defined as: - * 
- *   typedef struct
- *   {
- *     uint16_t numRows;
- *     uint16_t numCols;
- *     float32_t *pData;
- * } arm_bilinear_interp_instance_f32;
- *
- * - * \par - * where numRows specifies the number of rows in the table; - * numCols specifies the number of columns in the table; - * and pData points to an array of size numRows*numCols values. - * The data table pTable is organized in row order and the supplied data values fall on integer indexes. - * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. - * - * \par - * Let (x, y) specify the desired interpolation point. Then define: - * 
- *     XF = floor(x)
- *     YF = floor(y)
- *
- * \par - * The interpolated output point is computed as: - * 
- *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
- *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
- *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
- *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
- *
- * Note that the coordinates (x, y) contain integer and fractional components. - * The integer components specify which portion of the table to use while the - * fractional components control the interpolation processor. - * - * \par - * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. - */ - -/** - * @addtogroup BilinearInterpolate - * @{ - */ - - -/** -* -* @brief Floating-point bilinear interpolation. -* @param[in,out] S points to an instance of the interpolation structure. -* @param[in] X interpolation coordinate. -* @param[in] Y interpolation coordinate. -* @return out interpolated value. -*/ -CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32( - const arm_bilinear_interp_instance_f32* S, - float32_t X, - float32_t Y) -{ - float32_t out; - float32_t f00, f01, f10, f11; - float32_t* pData = S->pData; - int32_t xIndex, yIndex, index; - float32_t xdiff, ydiff; - float32_t b1, b2, b3, b4; - - xIndex = (int32_t) X; - yIndex = (int32_t) Y; - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) { - return (0); - } - - /* Calculation of index for two nearest points in X-direction */ - index = (xIndex - 1) + (yIndex - 1) * S->numCols; - - - /* Read two nearest points in X-direction */ - f00 = pData[index]; - f01 = pData[index + 1]; - - /* Calculation of index for two nearest points in Y-direction */ - index = (xIndex - 1) + (yIndex) * S->numCols; - - - /* Read two nearest points in Y-direction */ - f10 = pData[index]; - f11 = pData[index + 1]; - - /* Calculation of intermediate values */ - b1 = f00; - b2 = f01 - f00; - b3 = f10 - f00; - b4 = f00 - f01 - f10 + f11; - - /* Calculation of fractional part in X */ - xdiff = X - xIndex; - - /* Calculation of fractional part in Y */ - ydiff = Y - yIndex; - - /* Calculation of bi-linear interpolated output */ - out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; - - /* return to application */ - return (out); -} - - -/** -* -* @brief Q31 bilinear interpolation. -* @param[in,out] S points to an instance of the interpolation structure. -* @param[in] X interpolation coordinate in 12.20 format. -* @param[in] Y interpolation coordinate in 12.20 format. -* @return out interpolated value. -*/ -CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31( - arm_bilinear_interp_instance_q31* S, - q31_t X, - q31_t Y) -{ - q31_t out; /* Temporary output */ - q31_t acc = 0; /* output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q31_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q31_t* pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) { - return (0); - } - - /* 20 bits for the fractional part */ - /* shift left xfract by 11 to keep 1.31 format */ - xfract = (X & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; - x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; - - /* 20 bits for the fractional part */ - /* shift left yfract by 11 to keep 1.31 format */ - yfract = (Y & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; - y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ - out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); - acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); - - /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); - - /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* Convert acc to 1.31(q31) format */ - return ((q31_t)(acc << 2)); -} - - -/** -* @brief Q15 bilinear interpolation. -* @param[in,out] S points to an instance of the interpolation structure. -* @param[in] X interpolation coordinate in 12.20 format. -* @param[in] Y interpolation coordinate in 12.20 format. -* @return out interpolated value. -*/ -CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15( - arm_bilinear_interp_instance_q15* S, - q31_t X, - q31_t Y) -{ - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q15_t x1, x2, y1, y2; /* Nearest output values */ - q31_t xfract, yfract; /* X, Y fractional parts */ - int32_t rI, cI; /* Row and column indices */ - q15_t* pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; - x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; - y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ - - /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ - /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ - out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); - acc = ((q63_t) out * (0xFFFFF - yfract)); - - /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); - acc += ((q63_t) out * (xfract)); - - /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* acc is in 13.51 format and down shift acc by 36 times */ - /* Convert out to 1.15 format */ - return ((q15_t)(acc >> 36)); -} - - -/** -* @brief Q7 bilinear interpolation. -* @param[in,out] S points to an instance of the interpolation structure. -* @param[in] X interpolation coordinate in 12.20 format. -* @param[in] Y interpolation coordinate in 12.20 format. -* @return out interpolated value. -*/ -CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7( - arm_bilinear_interp_instance_q7* S, - q31_t X, - q31_t Y) -{ - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q7_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q7_t* pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & (q31_t)0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; - x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & (q31_t)0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; - y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ - out = ((x1 * (0xFFFFF - xfract))); - acc = (((q63_t) out * (0xFFFFF - yfract))); - - /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ - out = ((x2 * (0xFFFFF - yfract))); - acc += (((q63_t) out * (xfract))); - - /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y1 * (0xFFFFF - xfract))); - acc += (((q63_t) out * (yfract))); - - /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y2 * (yfract))); - acc += (((q63_t) out * (xfract))); - - /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ - return ((q7_t)(acc >> 40)); -} - -/** - * @} end of BilinearInterpolate group - */ - - -/* SMMLAR */ -#define multAcc_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) - -/* SMMLSR */ -#define multSub_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) - -/* SMMULR */ -#define mult_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) - -/* SMMLA */ -#define multAcc_32x32_keep32(a, x, y) \ - a += (q31_t) (((q63_t) x * y) >> 32) - -/* SMMLS */ -#define multSub_32x32_keep32(a, x, y) \ - a -= (q31_t) (((q63_t) x * y) >> 32) - -/* SMMUL */ -#define mult_32x32_keep32(a, x, y) \ - a = (q31_t) (((q63_t) x * y ) >> 32) - - -#if defined ( __CC_ARM ) -/* Enter low optimization region - place directly above function definition */ -#if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) -#define LOW_OPTIMIZATION_ENTER \ - _Pragma ("push") \ - _Pragma ("O1") -#else -#define LOW_OPTIMIZATION_ENTER -#endif - -/* Exit low optimization region - place directly after end of function definition */ -#if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) -#define LOW_OPTIMIZATION_EXIT \ - _Pragma ("pop") -#else -#define LOW_OPTIMIZATION_EXIT -#endif - -/* Enter low optimization region - place directly above function definition */ -#define IAR_ONLY_LOW_OPTIMIZATION_ENTER - -/* Exit low optimization region - place directly after end of function definition */ -#define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) -#define LOW_OPTIMIZATION_ENTER -#define LOW_OPTIMIZATION_EXIT -#define IAR_ONLY_LOW_OPTIMIZATION_ENTER -#define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined ( __GNUC__ ) -#define LOW_OPTIMIZATION_ENTER \ - __attribute__(( optimize("-O1") )) -#define LOW_OPTIMIZATION_EXIT -#define IAR_ONLY_LOW_OPTIMIZATION_ENTER -#define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined ( __ICCARM__ ) -/* Enter low optimization region - place directly above function definition */ -#if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) -#define LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") -#else -#define LOW_OPTIMIZATION_ENTER -#endif - -/* Exit low optimization region - place directly after end of function definition */ -#define LOW_OPTIMIZATION_EXIT - -/* Enter low optimization region - place directly above function definition */ -#if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) -#define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") -#else -#define IAR_ONLY_LOW_OPTIMIZATION_ENTER -#endif - -/* Exit low optimization region - place directly after end of function definition */ -#define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined ( __TI_ARM__ ) -#define LOW_OPTIMIZATION_ENTER -#define LOW_OPTIMIZATION_EXIT -#define IAR_ONLY_LOW_OPTIMIZATION_ENTER -#define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined ( __CSMC__ ) -#define LOW_OPTIMIZATION_ENTER -#define LOW_OPTIMIZATION_EXIT -#define IAR_ONLY_LOW_OPTIMIZATION_ENTER -#define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined ( __TASKING__ ) -#define LOW_OPTIMIZATION_ENTER -#define LOW_OPTIMIZATION_EXIT -#define IAR_ONLY_LOW_OPTIMIZATION_ENTER -#define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#endif - - -#ifdef __cplusplus -} -#endif - - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -#endif /* _ARM_MATH_H */ - -/** - * - * End of file. - */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_armcc.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_armcc.h deleted file mode 100644 index 4617b1280..000000000 --- a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_armcc.h +++ /dev/null @@ -1,796 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armcc.h - * @brief CMSIS compiler ARMCC (ARM compiler V5) header file - * @version V5.0.1 - * @date 03. February 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_ARMCC_H -#define __CMSIS_ARMCC_H - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) -#error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* CMSIS compiler control architecture macros */ -#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ - (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) -#define __ARM_ARCH_6M__ 1 -#endif - -#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) -#define __ARM_ARCH_7M__ 1 -#endif - -#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) -#define __ARM_ARCH_7EM__ 1 -#endif - -/* __ARM_ARCH_8M_BASE__ not applicable */ -/* __ARM_ARCH_8M_MAIN__ not applicable */ - - -/* CMSIS compiler specific defines */ -#ifndef __ASM -#define __ASM __asm -#endif -#ifndef __INLINE -#define __INLINE __inline -#endif -#ifndef __STATIC_INLINE -#define __STATIC_INLINE static __inline -#endif -#ifndef __NO_RETURN -#define __NO_RETURN __declspec(noreturn) -#endif -#ifndef __USED -#define __USED __attribute__((used)) -#endif -#ifndef __WEAK -#define __WEAK __attribute__((weak)) -#endif -#ifndef __UNALIGNED_UINT32 -#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) -#endif -#ifndef __ALIGNED -#define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __PACKED -#define __PACKED __attribute__((packed)) -#endif -#ifndef __PACKED_STRUCT -#define __PACKED_STRUCT __packed struct -#endif - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -/* intrinsic void __enable_irq(); */ - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -/* intrinsic void __disable_irq(); */ - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xFFU); -} - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - register uint32_t __regBasePriMax __ASM("basepri_max"); - __regBasePriMax = (basePri & 0xFFU); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1U); -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#else - (void)fpscr; -#endif -} - -#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() do {\ - __schedule_barrier();\ - __isb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() do {\ - __schedule_barrier();\ - __dsb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() do {\ - __schedule_barrier();\ - __dmb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - - -/** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) -#define __RBIT __rbit -#else -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ - return(result); -} -#endif - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) -#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) -#else -#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) -#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) -#else -#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) -#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) -#else -#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) -#define __STREXB(value, ptr) __strex(value, ptr) -#else -#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) -#define __STREXH(value, ptr) __strex(value, ptr) -#else -#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) -#define __STREXW(value, ptr) __strex(value, ptr) -#else -#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __clrex - - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) -{ - rrx r0, r0 - bx lr -} -#endif - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRBT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRHT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRT(value, ptr) __strt(value, ptr) - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ - ((int64_t)(ARG3) << 32U) ) >> 32U)) - -#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCC_H */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_armclang.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_armclang.h deleted file mode 100644 index 6b21a5bea..000000000 --- a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_armclang.h +++ /dev/null @@ -1,1735 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armclang.h - * @brief CMSIS compiler ARMCLANG (ARM compiler V6) header file - * @version V5.0.1 - * @date 02. February 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_ARMCLANG_H -#define __CMSIS_ARMCLANG_H - -#ifndef __ARM_COMPAT_H -#include /* Compatibility header for ARM Compiler 5 intrinsics */ -#endif - -/* CMSIS compiler specific defines */ -#ifndef __ASM -#define __ASM __asm -#endif -#ifndef __INLINE -#define __INLINE __inline -#endif -#ifndef __STATIC_INLINE -#define __STATIC_INLINE static __inline -#endif -#ifndef __NO_RETURN -#define __NO_RETURN __attribute__((noreturn)) -#endif -#ifndef __USED -#define __USED __attribute__((used)) -#endif -#ifndef __WEAK -#define __WEAK __attribute__((weak)) -#endif -#ifndef __UNALIGNED_UINT32 -#pragma clang diagnostic push -#pragma clang diagnostic ignored "-Wpacked" -struct __attribute__((packed)) T_UINT32 { - uint32_t v; -}; -#pragma clang diagnostic pop -#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -#endif -#ifndef __ALIGNED -#define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __PACKED -#define __PACKED __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_STRUCT -#define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -/* intrinsic void __enable_irq(); see arm_compat.h */ - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -/* intrinsic void __disable_irq(); see arm_compat.h */ - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - -/** - \brief Get Process Stack Pointer Limit - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return(result); -} - - -#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ - (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Get Process Stack Pointer Limit (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -} - - -#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ - (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - - return(result); -} - - -#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ - (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Get Main Stack Pointer Limit (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -} - - -#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ - (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Set Main Stack Pointer Limit (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -} -#endif - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -/* #define __get_FPSCR __builtin_arm_get_fpscr */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - uint32_t result; - - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - return(result); -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -/* #define __set_FPSCR __builtin_arm_set_fpscr */ -__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "memory"); -#else - (void)fpscr; -#endif -} - -#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __builtin_arm_nop - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __builtin_arm_wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __builtin_arm_wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __builtin_arm_sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() __builtin_arm_isb(0xF); - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __builtin_arm_dsb(0xF); - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __builtin_arm_dmb(0xF); - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __builtin_bswap32 - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV16 __builtin_bswap16 /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */ -#if 0 -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} -#endif - - -/** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. - \param [in] value Value to reverse - \return Reversed value - */ -/* ToDo ARMCLANG: check if __builtin_bswap16 could be used */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ - int32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -/* ToDo ARMCLANG: check if __builtin_arm_rbit is supported */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ -#endif - return(result); -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __builtin_clz - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB (uint8_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH (uint16_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW (uint32_t)__builtin_arm_ldrex - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW (uint32_t)__builtin_arm_strex - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __builtin_arm_clrex - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __builtin_arm_ssat - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __builtin_arm_usat - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t* ptr) -{ - uint32_t result; - - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t* ptr) -{ - uint32_t result; - - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t* ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t* ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t* ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t* ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t* ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t* ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t* ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t* ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t* ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t* ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDAEXB (uint8_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDAEXH (uint16_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDAEX (uint32_t)__builtin_arm_ldaex - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXB (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXH (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEX (uint32_t)__builtin_arm_stlex - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ - ({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ - ({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u { - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u { - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u { - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u { - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#if 0 -#define __PKHBT(ARG1,ARG2,ARG3) \ - ({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ - ({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) -#endif - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCLANG_H */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_compiler.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_compiler.h deleted file mode 100644 index 89cd69027..000000000 --- a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_compiler.h +++ /dev/null @@ -1,231 +0,0 @@ -/**************************************************************************//** - * @file cmsis_compiler.h - * @brief CMSIS compiler generic header file - * @version V5.0.1 - * @date 30. January 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_COMPILER_H -#define __CMSIS_COMPILER_H - -#include - -/* - * ARM Compiler 4/5 - */ -#if defined ( __CC_ARM ) -#include "cmsis_armcc.h" - - -/* - * ARM Compiler 6 (armclang) - */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#include "cmsis_armclang.h" - - -/* - * GNU Compiler - */ -#elif defined ( __GNUC__ ) -#include "cmsis_gcc.h" - - -/* - * IAR Compiler - */ -#elif defined ( __ICCARM__ ) - -#ifndef __ASM -#define __ASM __asm -#endif -#ifndef __INLINE -#define __INLINE inline -#endif -#ifndef __STATIC_INLINE -#define __STATIC_INLINE static inline -#endif - -#include - -#ifndef __NO_RETURN -#define __NO_RETURN __noreturn -#endif -#ifndef __USED -#define __USED __root -#endif -#ifndef __WEAK -#define __WEAK __weak -#endif -#ifndef __UNALIGNED_UINT32 -__packed struct T_UINT32 { - uint32_t v; -}; -#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -#endif -#ifndef __ALIGNED -#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. -#define __ALIGNED(x) -#endif -#ifndef __PACKED -#define __PACKED __packed -#endif -#ifndef __PACKED_STRUCT -#define __PACKED_STRUCT __packed struct -#endif - - -/* - * TI ARM Compiler - */ -#elif defined ( __TI_ARM__ ) -#include - -#ifndef __ASM -#define __ASM __asm -#endif -#ifndef __INLINE -#define __INLINE inline -#endif -#ifndef __STATIC_INLINE -#define __STATIC_INLINE static inline -#endif -#ifndef __NO_RETURN -#define __NO_RETURN __attribute__((noreturn)) -#endif -#ifndef __USED -#define __USED __attribute__((used)) -#endif -#ifndef __WEAK -#define __WEAK __attribute__((weak)) -#endif -#ifndef __UNALIGNED_UINT32 -struct __attribute__((packed)) T_UINT32 { - uint32_t v; -}; -#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -#endif -#ifndef __ALIGNED -#define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __PACKED -#define __PACKED __attribute__((packed)) -#endif -#ifndef __PACKED_STRUCT -#define __PACKED_STRUCT struct __attribute__((packed)) -#endif - - -/* - * TASKING Compiler - */ -#elif defined ( __TASKING__ ) -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -#ifndef __ASM -#define __ASM __asm -#endif -#ifndef __INLINE -#define __INLINE inline -#endif -#ifndef __STATIC_INLINE -#define __STATIC_INLINE static inline -#endif -#ifndef __NO_RETURN -#define __NO_RETURN __attribute__((noreturn)) -#endif -#ifndef __USED -#define __USED __attribute__((used)) -#endif -#ifndef __WEAK -#define __WEAK __attribute__((weak)) -#endif -#ifndef __UNALIGNED_UINT32 -struct __packed__ T_UINT32 { - uint32_t v; -}; -#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -#endif -#ifndef __ALIGNED -#define __ALIGNED(x) __align(x) -#endif -#ifndef __PACKED -#define __PACKED __packed__ -#endif -#ifndef __PACKED_STRUCT -#define __PACKED_STRUCT struct __packed__ -#endif - - -/* - * COSMIC Compiler - */ -#elif defined ( __CSMC__ ) -#include - -#ifndef __ASM -#define __ASM _asm -#endif -#ifndef __INLINE -#define __INLINE inline -#endif -#ifndef __STATIC_INLINE -#define __STATIC_INLINE static inline -#endif -#ifndef __NO_RETURN -// NO RETURN is automatically detected hence no warning here -#define __NO_RETURN -#endif -#ifndef __USED -#warning No compiler specific solution for __USED. __USED is ignored. -#define __USED -#endif -#ifndef __WEAK -#define __WEAK __weak -#endif -#ifndef __UNALIGNED_UINT32 -@packed struct T_UINT32 { - uint32_t v; -}; -#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -#endif -#ifndef __ALIGNED -#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. -#define __ALIGNED(x) -#endif -#ifndef __PACKED -#define __PACKED @packed -#endif -#ifndef __PACKED_STRUCT -#define __PACKED_STRUCT @packed struct -#endif - - -#else -#error Unknown compiler. -#endif - - -#endif /* __CMSIS_COMPILER_H */ - diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_gcc.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_gcc.h deleted file mode 100644 index 919f26d15..000000000 --- a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_gcc.h +++ /dev/null @@ -1,1900 +0,0 @@ -/**************************************************************************//** - * @file cmsis_gcc.h - * @brief CMSIS compiler GCC header file - * @version V5.0.1 - * @date 02. February 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_GCC_H -#define __CMSIS_GCC_H - -/* ignore some GCC warnings */ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" - -/* CMSIS compiler specific defines */ -#ifndef __ASM -#define __ASM __asm -#endif -#ifndef __INLINE -#define __INLINE inline -#endif -#ifndef __STATIC_INLINE -#define __STATIC_INLINE static inline -#endif -#ifndef __NO_RETURN -#define __NO_RETURN __attribute__((noreturn)) -#endif -#ifndef __USED -#define __USED __attribute__((used)) -#endif -#ifndef __WEAK -#define __WEAK __attribute__((weak)) -#endif -#ifndef __UNALIGNED_UINT32 -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpacked" -#pragma GCC diagnostic ignored "-Wattributes" -struct __attribute__((packed)) T_UINT32 { - uint32_t v; -}; -#pragma GCC diagnostic pop -#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -#endif -#ifndef __ALIGNED -#define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __PACKED -#define __PACKED __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_STRUCT -#define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - -/** - \brief Get Process Stack Pointer Limit - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return(result); -} - - -#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ - (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Get Process Stack Pointer Limit (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -} - - -#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ - (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - - return(result); -} - - -#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ - (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Get Main Stack Pointer Limit (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -} - - -#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ - (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Set Main Stack Pointer Limit (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -} -#endif - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - uint32_t result; - - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - return(result); -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); -#else - (void)fpscr; -#endif -} - -#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_RW_REG(r) "+l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_RW_REG(r) "+r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -//__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) -//{ -// __ASM volatile ("nop"); -//} -#define __NOP() __ASM volatile ("nop") /* This implementation generates debug information */ - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -//__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) -//{ -// __ASM volatile ("wfi"); -//} -#define __WFI() __ASM volatile ("wfi") /* This implementation generates debug information */ - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -//__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) -//{ -// __ASM volatile ("wfe"); -//} -#define __WFE() __ASM volatile ("wfe") /* This implementation generates debug information */ - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -//__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) -//{ -// __ASM volatile ("sev"); -//} -#define __SEV() __ASM volatile ("sev") /* This implementation generates debug information */ - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb 0xF"::: "memory"); -} - - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb 0xF"::: "memory"); -} - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb 0xF"::: "memory"); -} - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (short)__builtin_bswap16(value); -#else - int32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ -#endif - return(result); -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __builtin_clz - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t* addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t* addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t* addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t* addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t* addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t* addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ - ({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ - ({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t* ptr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t* ptr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t* ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t* ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t* ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t* ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t* ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t* ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t* ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t* ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t* ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t* ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAEXB(volatile uint8_t* ptr) -{ - uint32_t result; - - __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAEXH(volatile uint16_t* ptr) -{ - uint32_t result; - - __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDAEX(volatile uint32_t* ptr) -{ - uint32_t result; - - __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t* ptr) -{ - uint32_t result; - - __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t* ptr) -{ - uint32_t result; - - __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEX(uint32_t value, volatile uint32_t* ptr) -{ - uint32_t result; - - __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); - return(result); -} - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (__ARM_FEATURE_DSP == 1) /* ToDo ARMCLANG: This should be ARCH >= ARMv7-M + SIMD */ - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ - ({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ - ({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u { - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u { - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u { - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u { - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#if 0 -#define __PKHBT(ARG1,ARG2,ARG3) \ - ({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ - ({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) -#endif - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#pragma GCC diagnostic pop - -#endif /* __CMSIS_GCC_H */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_armv8mbl.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_armv8mbl.h deleted file mode 100644 index 4e65d1d95..000000000 --- a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_armv8mbl.h +++ /dev/null @@ -1,1813 +0,0 @@ -/**************************************************************************//** - * @file core_armv8mbl.h - * @brief CMSIS ARMv8MBL Core Peripheral Access Layer Header File - * @version V5.0.1 - * @date 25. November 2016 - ******************************************************************************/ -/* - * Copyright (c) 2009-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) -#pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_ARMV8MBL_H_GENERIC -#define __CORE_ARMV8MBL_H_GENERIC - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_ARMv8MBL - @{ - */ - -/* CMSIS cmGrebe definitions */ -#define __ARMv8MBL_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ -#define __ARMv8MBL_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ -#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ - __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) -#if defined __TARGET_FPU_VFP -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#if defined __ARM_PCS_VFP -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __GNUC__ ) -#if defined (__VFP_FP__) && !defined(__SOFTFP__) -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __ICCARM__ ) -#if defined __ARMVFP__ -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __TI_ARM__ ) -#if defined __TI_VFP_SUPPORT__ -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __TASKING__ ) -#if defined __FPU_VFP__ -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __CSMC__ ) -#if ( __CSMC__ & 0x400U) -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV8MBL_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_ARMV8MBL_H_DEPENDANT -#define __CORE_ARMV8MBL_H_DEPENDANT - -#ifdef __cplusplus -extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES -#ifndef __ARMv8MBL_REV -#define __ARMv8MBL_REV 0x0000U -#warning "__ARMv8MBL_REV not defined in device header file; using default!" -#endif - -#ifndef __FPU_PRESENT -#define __FPU_PRESENT 0U -#warning "__FPU_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __MPU_PRESENT -#define __MPU_PRESENT 0U -#warning "__MPU_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __SAUREGION_PRESENT -#define __SAUREGION_PRESENT 0U -#warning "__SAUREGION_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __VTOR_PRESENT -#define __VTOR_PRESENT 0U -#warning "__VTOR_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __NVIC_PRIO_BITS -#define __NVIC_PRIO_BITS 2U -#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" -#endif - -#ifndef __Vendor_SysTickConfig -#define __Vendor_SysTickConfig 0U -#warning "__Vendor_SysTickConfig not defined in device header file; using default!" -#endif - -#ifndef __ETM_PRESENT -#define __ETM_PRESENT 0U -#warning "__ETM_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __MTB_PRESENT -#define __MTB_PRESENT 0U -#warning "__MTB_PRESENT not defined in device header file; using default!" -#endif - -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus -#define __I volatile /*!< Defines 'read only' permissions */ -#else -#define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group ARMv8MBL */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union { - struct { - uint32_t _reserved0: 28; /*!< bit: 0..27 Reserved */ - uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ - uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union { - struct { - uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union { - struct { - uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */ - uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1: 3; /*!< bit: 25..27 Reserved */ - uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ - uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union { - struct { - uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL: 1; /*!< bit: 1 Stack-pointer select */ - uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct { - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct { - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - uint32_t RESERVED0[6U]; - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct { - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct { - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - uint32_t RESERVED0[7U]; - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#endif -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct { - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED4[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ -#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ -#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ -#define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ -#define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ -#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ -#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ -#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - -#define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ -#define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ -#define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ -#define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ -#define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ -#endif - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifndef CMSIS_NVIC_VIRTUAL -/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for ARMv8-M Baseline */ -/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for ARMv8-M Baseline */ -#define NVIC_EnableIRQ __NVIC_EnableIRQ -#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ -#define NVIC_DisableIRQ __NVIC_DisableIRQ -#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ -#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ -#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -#define NVIC_GetActive __NVIC_GetActive -#define NVIC_SetPriority __NVIC_SetPriority -#define NVIC_GetPriority __NVIC_GetPriority -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifndef CMSIS_VECTAB_VIRTUAL -#define NVIC_SetVector __NVIC_SetVector -#define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else { - SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else { - return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - If VTOR is not present address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t* vectors = (uint32_t*)SCB->VTOR; -#else - uint32_t* vectors = (uint32_t*)0x0U; -#endif - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t* vectors = (uint32_t*)SCB->VTOR; -#else - uint32_t* vectors = (uint32_t*)0x0U; -#endif - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) { /* wait until reset */ - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else { - SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else { - return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_armv8mml.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_armv8mml.h deleted file mode 100644 index 273c3849c..000000000 --- a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_armv8mml.h +++ /dev/null @@ -1,2821 +0,0 @@ -/**************************************************************************//** - * @file core_armv8mml.h - * @brief CMSIS ARMv8MML Core Peripheral Access Layer Header File - * @version V5.0.2 - * @date 07. December 2016 - ******************************************************************************/ -/* - * Copyright (c) 2009-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) -#pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_ARMV8MML_H_GENERIC -#define __CORE_ARMV8MML_H_GENERIC - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_ARMv8MML - @{ - */ - -/* CMSIS ARMv8MML definitions */ -#define __ARMv8MML_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ -#define __ARMv8MML_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ -#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ - __ARMv8MML_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (81U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) -#if defined __TARGET_FPU_VFP -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#if defined __ARM_PCS_VFP -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined ( __GNUC__ ) -#if defined (__VFP_FP__) && !defined(__SOFTFP__) -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined ( __ICCARM__ ) -#if defined __ARMVFP__ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined ( __TI_ARM__ ) -#if defined __TI_VFP_SUPPORT__ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined ( __TASKING__ ) -#if defined __FPU_VFP__ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined ( __CSMC__ ) -#if ( __CSMC__ & 0x400U) -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV8MML_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_ARMV8MML_H_DEPENDANT -#define __CORE_ARMV8MML_H_DEPENDANT - -#ifdef __cplusplus -extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES -#ifndef __ARMv8MML_REV -#define __ARMv8MML_REV 0x0000U -#warning "__ARMv8MML_REV not defined in device header file; using default!" -#endif - -#ifndef __FPU_PRESENT -#define __FPU_PRESENT 0U -#warning "__FPU_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __MPU_PRESENT -#define __MPU_PRESENT 0U -#warning "__MPU_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __SAUREGION_PRESENT -#define __SAUREGION_PRESENT 0U -#warning "__SAUREGION_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __DSP_PRESENT -#define __DSP_PRESENT 0U -#warning "__DSP_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __NVIC_PRIO_BITS -#define __NVIC_PRIO_BITS 3U -#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" -#endif - -#ifndef __Vendor_SysTickConfig -#define __Vendor_SysTickConfig 0U -#warning "__Vendor_SysTickConfig not defined in device header file; using default!" -#endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus -#define __I volatile /*!< Defines 'read only' permissions */ -#else -#define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group ARMv8MML */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union { - struct { - uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */ - uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */ - uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ - uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ - uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union { - struct { - uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union { - struct { - uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0: 7; /*!< bit: 9..15 Reserved */ - uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1: 4; /*!< bit: 20..23 Reserved */ - uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT: 2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ - uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ - uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union { - struct { - uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL: 1; /*!< bit: 1 Stack-pointer select */ - uint32_t FPCA: 1; /*!< bit: 2 Floating-point context active */ - uint32_t SFPA: 1; /*!< bit: 3 Secure floating-point active */ - uint32_t _reserved1: 28; /*!< bit: 4..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ -#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ - -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct { - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED6[580U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct { - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ - uint32_t RESERVED3[92U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - uint32_t RESERVED7[6U]; - __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ - __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ - __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ - __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ - uint32_t RESERVED8[1U]; - __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ -#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ -#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ - -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ -#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ -#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Non-Secure Access Control Register Definitions */ -#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ -#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ - -#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ -#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ - -#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ -#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/* Instruction Tightly-Coupled Memory Control Register Definitions */ -#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ -#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ - -#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ -#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ - -#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ -#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ - -#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ - -/* Data Tightly-Coupled Memory Control Register Definitions */ -#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ -#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ - -#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ -#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ - -#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ -#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ - -#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ - -/* AHBP Control Register Definitions */ -#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ -#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ - -#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ -#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ - -/* L1 Cache Control Register Definitions */ -#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ -#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ - -#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ -#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ - -#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ -#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ - -/* AHBS Control Register Definitions */ -#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ -#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ - -#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ -#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ - -#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ -#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ - -/* Auxiliary Bus Fault Status Register Definitions */ -#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ -#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ - -#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ -#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ - -#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ -#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ - -#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ -#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ - -#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ -#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ - -#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ -#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct { - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ - __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct { - __OM union { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ - uint32_t RESERVED6[4U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Stimulus Port Register Definitions */ -#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ -#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ - -#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ -#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ -#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ - -#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ -#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ - uint32_t RESERVED32[934U]; - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ - uint32_t RESERVED33[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ -#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct { - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct { - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ - __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ - __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ - __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ - uint32_t RESERVED0[1]; - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#else - uint32_t RESERVED0[3]; -#endif - __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/* Secure Fault Status Register Definitions */ -#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ -#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ - -#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ -#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ - -#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ -#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ - -#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ -#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ - -#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ -#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ - -#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ -#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ - -#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ -#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ - -#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ -#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct { - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ -#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ - -#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ -#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ - -#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ -#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ - -#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ -#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ - -#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ -#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ - -#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ -#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ -#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ -#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct { - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED4[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ -#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ -#define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ -#endif - -#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ -#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ -#define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ -#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ -#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ -#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - -#define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ -#define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ -#define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ -#define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ -#define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ -#define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ -#endif - -#define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ -#define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifndef CMSIS_NVIC_VIRTUAL -#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping -#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping -#define NVIC_EnableIRQ __NVIC_EnableIRQ -#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ -#define NVIC_DisableIRQ __NVIC_DisableIRQ -#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ -#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ -#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -#define NVIC_GetActive __NVIC_GetActive -#define NVIC_SetPriority __NVIC_SetPriority -#define NVIC_GetPriority __NVIC_GetPriority -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifndef CMSIS_VECTAB_VIRTUAL -#define NVIC_SetVector __NVIC_SetVector -#define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else { - SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) { - return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else { - return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t* vectors = (uint32_t*)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t* vectors = (uint32_t*)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) { /* wait until reset */ - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Priority Grouping (non-secure) - \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB_NS->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB_NS->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping (non-secure) - \details Reads the priority grouping field from the non-secure NVIC when in secure state. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) -{ - return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else { - SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) { - return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else { - return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) { - return 2U; /* Double + Single precision FPU */ - } - else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { - return 1U; /* Single precision FPU */ - } - else { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) { /* ITM Port #0 enabled */ - while (ITM->PORT[0U].u32 == 0UL) { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } - else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV8MML_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm0.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm0.h deleted file mode 100644 index d06d984b7..000000000 --- a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm0.h +++ /dev/null @@ -1,850 +0,0 @@ -/**************************************************************************//** - * @file core_cm0.h - * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File - * @version V5.0.1 - * @date 25. November 2016 - ******************************************************************************/ -/* - * Copyright (c) 2009-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) -#pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM0_H_GENERIC -#define __CORE_CM0_H_GENERIC - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M0 - @{ - */ - -/* CMSIS CM0 definitions */ -#define __CM0_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ -#define __CM0_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ - __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) -#if defined __TARGET_FPU_VFP -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#if defined __ARM_PCS_VFP -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __GNUC__ ) -#if defined (__VFP_FP__) && !defined(__SOFTFP__) -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __ICCARM__ ) -#if defined __ARMVFP__ -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __TI_ARM__ ) -#if defined __TI_VFP_SUPPORT__ -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __TASKING__ ) -#if defined __FPU_VFP__ -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __CSMC__ ) -#if ( __CSMC__ & 0x400U) -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0_H_DEPENDANT -#define __CORE_CM0_H_DEPENDANT - -#ifdef __cplusplus -extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES -#ifndef __CM0_REV -#define __CM0_REV 0x0000U -#warning "__CM0_REV not defined in device header file; using default!" -#endif - -#ifndef __NVIC_PRIO_BITS -#define __NVIC_PRIO_BITS 2U -#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" -#endif - -#ifndef __Vendor_SysTickConfig -#define __Vendor_SysTickConfig 0U -#warning "__Vendor_SysTickConfig not defined in device header file; using default!" -#endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus -#define __I volatile /*!< Defines 'read only' permissions */ -#else -#define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M0 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union { - struct { - uint32_t _reserved0: 28; /*!< bit: 0..27 Reserved */ - uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ - uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union { - struct { - uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union { - struct { - uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */ - uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1: 3; /*!< bit: 25..27 Reserved */ - uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ - uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union { - struct { - uint32_t _reserved0: 1; /*!< bit: 0 Reserved */ - uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct { - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct { - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - uint32_t RESERVED0; - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifndef CMSIS_NVIC_VIRTUAL -/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0 */ -/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0 */ -#define NVIC_EnableIRQ __NVIC_EnableIRQ -#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ -#define NVIC_DisableIRQ __NVIC_DisableIRQ -#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ -#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ -#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ -#define NVIC_SetPriority __NVIC_SetPriority -#define NVIC_GetPriority __NVIC_GetPriority -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifndef CMSIS_VECTAB_VIRTUAL -#define NVIC_SetVector __NVIC_SetVector -#define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - Address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t* vectors = (uint32_t*)0x0U; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t* vectors = (uint32_t*)0x0U; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) { /* wait until reset */ - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm0plus.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm0plus.h deleted file mode 100644 index ebc43f3a1..000000000 --- a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm0plus.h +++ /dev/null @@ -1,975 +0,0 @@ -/**************************************************************************//** - * @file core_cm0plus.h - * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File - * @version V5.0.1 - * @date 25. November 2016 - ******************************************************************************/ -/* - * Copyright (c) 2009-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) -#pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM0PLUS_H_GENERIC -#define __CORE_CM0PLUS_H_GENERIC - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex-M0+ - @{ - */ - -/* CMSIS CM0+ definitions */ -#define __CM0PLUS_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ -#define __CM0PLUS_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ - __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) -#if defined __TARGET_FPU_VFP -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#if defined __ARM_PCS_VFP -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __GNUC__ ) -#if defined (__VFP_FP__) && !defined(__SOFTFP__) -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __ICCARM__ ) -#if defined __ARMVFP__ -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __TI_ARM__ ) -#if defined __TI_VFP_SUPPORT__ -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __TASKING__ ) -#if defined __FPU_VFP__ -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __CSMC__ ) -#if ( __CSMC__ & 0x400U) -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0PLUS_H_DEPENDANT -#define __CORE_CM0PLUS_H_DEPENDANT - -#ifdef __cplusplus -extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES -#ifndef __CM0PLUS_REV -#define __CM0PLUS_REV 0x0000U -#warning "__CM0PLUS_REV not defined in device header file; using default!" -#endif - -#ifndef __MPU_PRESENT -#define __MPU_PRESENT 0U -#warning "__MPU_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __VTOR_PRESENT -#define __VTOR_PRESENT 0U -#warning "__VTOR_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __NVIC_PRIO_BITS -#define __NVIC_PRIO_BITS 2U -#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" -#endif - -#ifndef __Vendor_SysTickConfig -#define __Vendor_SysTickConfig 0U -#warning "__Vendor_SysTickConfig not defined in device header file; using default!" -#endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus -#define __I volatile /*!< Defines 'read only' permissions */ -#else -#define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex-M0+ */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union { - struct { - uint32_t _reserved0: 28; /*!< bit: 0..27 Reserved */ - uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ - uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union { - struct { - uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union { - struct { - uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */ - uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1: 3; /*!< bit: 25..27 Reserved */ - uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ - uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union { - struct { - uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct { - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct { - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct { - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the Cortex-M0+ header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ -#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifndef CMSIS_NVIC_VIRTUAL -/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0+ */ -/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0+ */ -#define NVIC_EnableIRQ __NVIC_EnableIRQ -#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ -#define NVIC_DisableIRQ __NVIC_DisableIRQ -#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ -#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ -#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ -#define NVIC_SetPriority __NVIC_SetPriority -#define NVIC_GetPriority __NVIC_GetPriority -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifndef CMSIS_VECTAB_VIRTUAL -#define NVIC_SetVector __NVIC_SetVector -#define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - If VTOR is not present address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t* vectors = (uint32_t*)SCB->VTOR; -#else - uint32_t* vectors = (uint32_t*)0x0U; -#endif - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t* vectors = (uint32_t*)SCB->VTOR; -#else - uint32_t* vectors = (uint32_t*)0x0U; -#endif - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; - -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) { /* wait until reset */ - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm23.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm23.h deleted file mode 100644 index 513635a58..000000000 --- a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm23.h +++ /dev/null @@ -1,1813 +0,0 @@ -/**************************************************************************//** - * @file core_cm23.h - * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File - * @version V5.0.1 - * @date 25. November 2016 - ******************************************************************************/ -/* - * Copyright (c) 2009-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) -#pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM23_H_GENERIC -#define __CORE_CM23_H_GENERIC - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M23 - @{ - */ - -/* CMSIS cmGrebe definitions */ -#define __CM23_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ -#define __CM23_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ -#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ - __CM23_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (23U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) -#if defined __TARGET_FPU_VFP -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#if defined __ARM_PCS_VFP -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __GNUC__ ) -#if defined (__VFP_FP__) && !defined(__SOFTFP__) -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __ICCARM__ ) -#if defined __ARMVFP__ -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __TI_ARM__ ) -#if defined __TI_VFP_SUPPORT__ -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __TASKING__ ) -#if defined __FPU_VFP__ -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __CSMC__ ) -#if ( __CSMC__ & 0x400U) -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM23_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM23_H_DEPENDANT -#define __CORE_CM23_H_DEPENDANT - -#ifdef __cplusplus -extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES -#ifndef __CM23_REV -#define __CM23_REV 0x0000U -#warning "__CM23_REV not defined in device header file; using default!" -#endif - -#ifndef __FPU_PRESENT -#define __FPU_PRESENT 0U -#warning "__FPU_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __MPU_PRESENT -#define __MPU_PRESENT 0U -#warning "__MPU_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __SAUREGION_PRESENT -#define __SAUREGION_PRESENT 0U -#warning "__SAUREGION_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __VTOR_PRESENT -#define __VTOR_PRESENT 0U -#warning "__VTOR_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __NVIC_PRIO_BITS -#define __NVIC_PRIO_BITS 2U -#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" -#endif - -#ifndef __Vendor_SysTickConfig -#define __Vendor_SysTickConfig 0U -#warning "__Vendor_SysTickConfig not defined in device header file; using default!" -#endif - -#ifndef __ETM_PRESENT -#define __ETM_PRESENT 0U -#warning "__ETM_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __MTB_PRESENT -#define __MTB_PRESENT 0U -#warning "__MTB_PRESENT not defined in device header file; using default!" -#endif - -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus -#define __I volatile /*!< Defines 'read only' permissions */ -#else -#define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M23 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union { - struct { - uint32_t _reserved0: 28; /*!< bit: 0..27 Reserved */ - uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ - uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union { - struct { - uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union { - struct { - uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */ - uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1: 3; /*!< bit: 25..27 Reserved */ - uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ - uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union { - struct { - uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL: 1; /*!< bit: 1 Stack-pointer select */ - uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct { - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct { - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - uint32_t RESERVED0[6U]; - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct { - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct { - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - uint32_t RESERVED0[7U]; - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#endif -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct { - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED4[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ -#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ -#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ -#define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ -#define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ -#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ -#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ -#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - -#define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ -#define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ -#define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ -#define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ -#define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ -#endif - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifndef CMSIS_NVIC_VIRTUAL -/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ -/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ -#define NVIC_EnableIRQ __NVIC_EnableIRQ -#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ -#define NVIC_DisableIRQ __NVIC_DisableIRQ -#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ -#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ -#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -#define NVIC_GetActive __NVIC_GetActive -#define NVIC_SetPriority __NVIC_SetPriority -#define NVIC_GetPriority __NVIC_GetPriority -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifndef CMSIS_VECTAB_VIRTUAL -#define NVIC_SetVector __NVIC_SetVector -#define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else { - SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else { - return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - If VTOR is not present address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t* vectors = (uint32_t*)SCB->VTOR; -#else - uint32_t* vectors = (uint32_t*)0x0U; -#endif - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t* vectors = (uint32_t*)SCB->VTOR; -#else - uint32_t* vectors = (uint32_t*)0x0U; -#endif - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) { /* wait until reset */ - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else { - SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else { - return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM23_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm3.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm3.h deleted file mode 100644 index 8cbf329b8..000000000 --- a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm3.h +++ /dev/null @@ -1,1880 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V5.0.1 - * @date 30. January 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) -#pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM3_H_GENERIC -#define __CORE_CM3_H_GENERIC - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M3 - @{ - */ - -/* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ - __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (3U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) -#if defined __TARGET_FPU_VFP -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#if defined __ARM_PCS_VFP -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __GNUC__ ) -#if defined (__VFP_FP__) && !defined(__SOFTFP__) -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __ICCARM__ ) -#if defined __ARMVFP__ -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __TI_ARM__ ) -#if defined __TI_VFP_SUPPORT__ -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __TASKING__ ) -#if defined __FPU_VFP__ -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __CSMC__ ) -#if ( __CSMC__ & 0x400U) -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM3_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM3_H_DEPENDANT -#define __CORE_CM3_H_DEPENDANT - -#ifdef __cplusplus -extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES -#ifndef __CM3_REV -#define __CM3_REV 0x0200U -#warning "__CM3_REV not defined in device header file; using default!" -#endif - -#ifndef __MPU_PRESENT -#define __MPU_PRESENT 0U -#warning "__MPU_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __NVIC_PRIO_BITS -#define __NVIC_PRIO_BITS 3U -#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" -#endif - -#ifndef __Vendor_SysTickConfig -#define __Vendor_SysTickConfig 0U -#warning "__Vendor_SysTickConfig not defined in device header file; using default!" -#endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus -#define __I volatile /*!< Defines 'read only' permissions */ -#else -#define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M3 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union { - struct { - uint32_t _reserved0: 27; /*!< bit: 0..26 Reserved */ - uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ - uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ - uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union { - struct { - uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union { - struct { - uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0: 1; /*!< bit: 9 Reserved */ - uint32_t ICI_IT_1: 6; /*!< bit: 10..15 ICI/IT part 1 */ - uint32_t _reserved1: 8; /*!< bit: 16..23 Reserved */ - uint32_t T: 1; /*!< bit: 24 Thumb bit */ - uint32_t ICI_IT_2: 2; /*!< bit: 25..26 ICI/IT part 2 */ - uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ - uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ - uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ -#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ -#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union { - struct { - uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct { - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct { - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ -#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#else -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct { - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ -#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -#else - uint32_t RESERVED1[1U]; -#endif -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct { - __OM union { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct { - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct { - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct { - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ -#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL -#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE -#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" -#endif -#include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else -#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping -#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping -#define NVIC_EnableIRQ __NVIC_EnableIRQ -#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ -#define NVIC_DisableIRQ __NVIC_DisableIRQ -#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ -#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ -#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -#define NVIC_GetActive __NVIC_GetActive -#define NVIC_SetPriority __NVIC_SetPriority -#define NVIC_GetPriority __NVIC_GetPriority -#define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL -#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" -#endif -#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else -#define NVIC_SetVector __NVIC_SetVector -#define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t* vectors = (uint32_t*)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t* vectors = (uint32_t*)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) { /* wait until reset */ - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) { /* ITM Port #0 enabled */ - while (ITM->PORT[0U].u32 == 0UL) { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } - else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM3_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm33.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm33.h deleted file mode 100644 index 00de7795e..000000000 --- a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm33.h +++ /dev/null @@ -1,2821 +0,0 @@ -/**************************************************************************//** - * @file core_cm33.h - * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File - * @version V5.0.2 - * @date 07. December 2016 - ******************************************************************************/ -/* - * Copyright (c) 2009-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) -#pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM33_H_GENERIC -#define __CORE_CM33_H_GENERIC - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M33 - @{ - */ - -/* CMSIS CM33 definitions */ -#define __CM33_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ -#define __CM33_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ -#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ - __CM33_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (33U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) -#if defined __TARGET_FPU_VFP -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#if defined __ARM_PCS_VFP -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined ( __GNUC__ ) -#if defined (__VFP_FP__) && !defined(__SOFTFP__) -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined ( __ICCARM__ ) -#if defined __ARMVFP__ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined ( __TI_ARM__ ) -#if defined __TI_VFP_SUPPORT__ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined ( __TASKING__ ) -#if defined __FPU_VFP__ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined ( __CSMC__ ) -#if ( __CSMC__ & 0x400U) -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM33_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM33_H_DEPENDANT -#define __CORE_CM33_H_DEPENDANT - -#ifdef __cplusplus -extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES -#ifndef __CM33_REV -#define __CM33_REV 0x0000U -#warning "__CM33_REV not defined in device header file; using default!" -#endif - -#ifndef __FPU_PRESENT -#define __FPU_PRESENT 0U -#warning "__FPU_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __MPU_PRESENT -#define __MPU_PRESENT 0U -#warning "__MPU_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __SAUREGION_PRESENT -#define __SAUREGION_PRESENT 0U -#warning "__SAUREGION_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __DSP_PRESENT -#define __DSP_PRESENT 0U -#warning "__DSP_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __NVIC_PRIO_BITS -#define __NVIC_PRIO_BITS 3U -#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" -#endif - -#ifndef __Vendor_SysTickConfig -#define __Vendor_SysTickConfig 0U -#warning "__Vendor_SysTickConfig not defined in device header file; using default!" -#endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus -#define __I volatile /*!< Defines 'read only' permissions */ -#else -#define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M33 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union { - struct { - uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */ - uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */ - uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ - uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ - uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union { - struct { - uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union { - struct { - uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0: 7; /*!< bit: 9..15 Reserved */ - uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1: 4; /*!< bit: 20..23 Reserved */ - uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT: 2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ - uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ - uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union { - struct { - uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL: 1; /*!< bit: 1 Stack-pointer select */ - uint32_t FPCA: 1; /*!< bit: 2 Floating-point context active */ - uint32_t SFPA: 1; /*!< bit: 3 Secure floating-point active */ - uint32_t _reserved1: 28; /*!< bit: 4..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ -#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ - -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct { - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED6[580U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct { - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ - uint32_t RESERVED3[92U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - uint32_t RESERVED7[6U]; - __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ - __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ - __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ - __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ - uint32_t RESERVED8[1U]; - __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ -#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ -#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ - -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ -#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ -#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Non-Secure Access Control Register Definitions */ -#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ -#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ - -#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ -#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ - -#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ -#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/* Instruction Tightly-Coupled Memory Control Register Definitions */ -#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ -#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ - -#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ -#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ - -#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ -#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ - -#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ - -/* Data Tightly-Coupled Memory Control Register Definitions */ -#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ -#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ - -#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ -#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ - -#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ -#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ - -#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ - -/* AHBP Control Register Definitions */ -#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ -#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ - -#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ -#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ - -/* L1 Cache Control Register Definitions */ -#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ -#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ - -#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ -#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ - -#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ -#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ - -/* AHBS Control Register Definitions */ -#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ -#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ - -#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ -#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ - -#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ -#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ - -/* Auxiliary Bus Fault Status Register Definitions */ -#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ -#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ - -#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ -#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ - -#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ -#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ - -#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ -#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ - -#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ -#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ - -#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ -#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct { - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ - __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct { - __OM union { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ - uint32_t RESERVED6[4U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Stimulus Port Register Definitions */ -#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ -#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ - -#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ -#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ -#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ - -#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ -#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ - uint32_t RESERVED32[934U]; - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ - uint32_t RESERVED33[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ -#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct { - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct { - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ - __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ - __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ - __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ - uint32_t RESERVED0[1]; - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#else - uint32_t RESERVED0[3]; -#endif - __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/* Secure Fault Status Register Definitions */ -#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ -#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ - -#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ -#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ - -#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ -#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ - -#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ -#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ - -#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ -#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ - -#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ -#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ - -#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ -#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ - -#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ -#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct { - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ -#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ - -#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ -#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ - -#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ -#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ - -#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ -#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ - -#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ -#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ - -#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ -#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ -#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ -#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct { - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED4[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ -#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ -#define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ -#endif - -#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ -#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ -#define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ -#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ -#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ -#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - -#define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ -#define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ -#define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ -#define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ -#define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ -#define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ -#endif - -#define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ -#define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifndef CMSIS_NVIC_VIRTUAL -#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping -#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping -#define NVIC_EnableIRQ __NVIC_EnableIRQ -#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ -#define NVIC_DisableIRQ __NVIC_DisableIRQ -#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ -#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ -#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -#define NVIC_GetActive __NVIC_GetActive -#define NVIC_SetPriority __NVIC_SetPriority -#define NVIC_GetPriority __NVIC_GetPriority -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifndef CMSIS_VECTAB_VIRTUAL -#define NVIC_SetVector __NVIC_SetVector -#define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else { - SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) { - return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else { - return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t* vectors = (uint32_t*)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t* vectors = (uint32_t*)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) { /* wait until reset */ - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Priority Grouping (non-secure) - \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB_NS->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB_NS->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping (non-secure) - \details Reads the priority grouping field from the non-secure NVIC when in secure state. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) -{ - return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else { - SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) { - return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else { - return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) { - return 2U; /* Double + Single precision FPU */ - } - else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { - return 1U; /* Single precision FPU */ - } - else { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) { /* ITM Port #0 enabled */ - while (ITM->PORT[0U].u32 == 0UL) { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } - else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM33_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm4.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm4.h deleted file mode 100644 index f4c8011f8..000000000 --- a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm4.h +++ /dev/null @@ -1,2061 +0,0 @@ -/**************************************************************************//** - * @file core_cm4.h - * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V5.0.1 - * @date 30. January 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) -#pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM4_H_GENERIC -#define __CORE_CM4_H_GENERIC - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M4 - @{ - */ - -/* CMSIS CM4 definitions */ -#define __CM4_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ -#define __CM4_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ -#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ - __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (4U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) -#if defined __TARGET_FPU_VFP -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#if defined __ARM_PCS_VFP -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined ( __GNUC__ ) -#if defined (__VFP_FP__) && !defined(__SOFTFP__) -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined ( __ICCARM__ ) -#if defined __ARMVFP__ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined ( __TI_ARM__ ) -#if defined __TI_VFP_SUPPORT__ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined ( __TASKING__ ) -#if defined __FPU_VFP__ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined ( __CSMC__ ) -#if ( __CSMC__ & 0x400U) -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM4_H_DEPENDANT -#define __CORE_CM4_H_DEPENDANT - -#ifdef __cplusplus -extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES -#ifndef __CM4_REV -#define __CM4_REV 0x0000U -#warning "__CM4_REV not defined in device header file; using default!" -#endif - -#ifndef __FPU_PRESENT -#define __FPU_PRESENT 0U -#warning "__FPU_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __MPU_PRESENT -#define __MPU_PRESENT 0U -#warning "__MPU_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __NVIC_PRIO_BITS -#define __NVIC_PRIO_BITS 3U -#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" -#endif - -#ifndef __Vendor_SysTickConfig -#define __Vendor_SysTickConfig 0U -#warning "__Vendor_SysTickConfig not defined in device header file; using default!" -#endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus -#define __I volatile /*!< Defines 'read only' permissions */ -#else -#define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M4 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union { - struct { - uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */ - uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */ - uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ - uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ - uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union { - struct { - uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union { - struct { - uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0: 1; /*!< bit: 9 Reserved */ - uint32_t ICI_IT_1: 6; /*!< bit: 10..15 ICI/IT part 1 */ - uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1: 4; /*!< bit: 20..23 Reserved */ - uint32_t T: 1; /*!< bit: 24 Thumb bit */ - uint32_t ICI_IT_2: 2; /*!< bit: 25..26 ICI/IT part 2 */ - uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ - uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ - uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ -#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ -#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union { - struct { - uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA: 1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0: 29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct { - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct { - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct { - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ -#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ - -#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ -#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct { - __OM union { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct { - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct { - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct { - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct { - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ -#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ -#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL -#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE -#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" -#endif -#include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else -#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping -#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping -#define NVIC_EnableIRQ __NVIC_EnableIRQ -#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ -#define NVIC_DisableIRQ __NVIC_DisableIRQ -#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ -#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ -#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -#define NVIC_GetActive __NVIC_GetActive -#define NVIC_SetPriority __NVIC_SetPriority -#define NVIC_GetPriority __NVIC_GetPriority -#define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL -#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" -#endif -#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else -#define NVIC_SetVector __NVIC_SetVector -#define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t* vectors = (uint32_t*)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t* vectors = (uint32_t*)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) { /* wait until reset */ - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { - return 1U; /* Single precision FPU */ - } - else { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) { /* ITM Port #0 enabled */ - while (ITM->PORT[0U].u32 == 0UL) { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } - else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm7.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm7.h deleted file mode 100644 index c09acc824..000000000 --- a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm7.h +++ /dev/null @@ -1,2592 +0,0 @@ -/**************************************************************************//** - * @file core_cm7.h - * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File - * @version V5.0.1 - * @date 25. November 2016 - ******************************************************************************/ -/* - * Copyright (c) 2009-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) -#pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM7_H_GENERIC -#define __CORE_CM7_H_GENERIC - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M7 - @{ - */ - -/* CMSIS CM7 definitions */ -#define __CM7_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ -#define __CM7_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ -#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ - __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (7U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) -#if defined __TARGET_FPU_VFP -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#if defined __ARM_PCS_VFP -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined ( __GNUC__ ) -#if defined (__VFP_FP__) && !defined(__SOFTFP__) -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined ( __ICCARM__ ) -#if defined __ARMVFP__ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined ( __TI_ARM__ ) -#if defined __TI_VFP_SUPPORT__ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined ( __TASKING__ ) -#if defined __FPU_VFP__ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined ( __CSMC__ ) -#if ( __CSMC__ & 0x400U) -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM7_H_DEPENDANT -#define __CORE_CM7_H_DEPENDANT - -#ifdef __cplusplus -extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES -#ifndef __CM7_REV -#define __CM7_REV 0x0000U -#warning "__CM7_REV not defined in device header file; using default!" -#endif - -#ifndef __FPU_PRESENT -#define __FPU_PRESENT 0U -#warning "__FPU_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __MPU_PRESENT -#define __MPU_PRESENT 0U -#warning "__MPU_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __ICACHE_PRESENT -#define __ICACHE_PRESENT 0U -#warning "__ICACHE_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __DCACHE_PRESENT -#define __DCACHE_PRESENT 0U -#warning "__DCACHE_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __DTCM_PRESENT -#define __DTCM_PRESENT 0U -#warning "__DTCM_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __NVIC_PRIO_BITS -#define __NVIC_PRIO_BITS 3U -#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" -#endif - -#ifndef __Vendor_SysTickConfig -#define __Vendor_SysTickConfig 0U -#warning "__Vendor_SysTickConfig not defined in device header file; using default!" -#endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus -#define __I volatile /*!< Defines 'read only' permissions */ -#else -#define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M7 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union { - struct { - uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */ - uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */ - uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ - uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ - uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union { - struct { - uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union { - struct { - uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0: 1; /*!< bit: 9 Reserved */ - uint32_t ICI_IT_1: 6; /*!< bit: 10..15 ICI/IT part 1 */ - uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1: 4; /*!< bit: 20..23 Reserved */ - uint32_t T: 1; /*!< bit: 24 Thumb bit */ - uint32_t ICI_IT_2: 2; /*!< bit: 25..26 ICI/IT part 2 */ - uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ - uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ - uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ -#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ -#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union { - struct { - uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA: 1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0: 29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct { - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct { - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[1U]; - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - uint32_t RESERVED3[93U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - uint32_t RESERVED7[6U]; - __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ - __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ - __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ - __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ - uint32_t RESERVED8[1U]; - __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ - -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/* Instruction Tightly-Coupled Memory Control Register Definitions */ -#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ -#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ - -#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ -#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ - -#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ -#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ - -#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ - -/* Data Tightly-Coupled Memory Control Register Definitions */ -#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ -#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ - -#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ -#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ - -#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ -#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ - -#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ - -/* AHBP Control Register Definitions */ -#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ -#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ - -#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ -#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ - -/* L1 Cache Control Register Definitions */ -#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ -#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ - -#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ -#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ - -#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ -#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ - -/* AHBS Control Register Definitions */ -#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ -#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ - -#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ -#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ - -#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ -#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ - -/* Auxiliary Bus Fault Status Register Definitions */ -#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ -#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ - -#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ -#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ - -#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ -#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ - -#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ -#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ - -#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ -#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ - -#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ -#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct { - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ - -#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ -#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ - -#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ -#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct { - __OM union { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED3[981U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct { - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct { - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct { - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/* Media and FP Feature Register 2 Definitions */ - -/*@} end of group CMSIS_FPU */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct { - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ -#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ -#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifndef CMSIS_NVIC_VIRTUAL -#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping -#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping -#define NVIC_EnableIRQ __NVIC_EnableIRQ -#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ -#define NVIC_DisableIRQ __NVIC_DisableIRQ -#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ -#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ -#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -#define NVIC_GetActive __NVIC_GetActive -#define NVIC_SetPriority __NVIC_SetPriority -#define NVIC_GetPriority __NVIC_GetPriority -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifndef CMSIS_VECTAB_VIRTUAL -#define NVIC_SetVector __NVIC_SetVector -#define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else { - SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else { - return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t* vectors = (uint32_t*)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t* vectors = (uint32_t*)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) { /* wait until reset */ - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = SCB->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) { - return 2U; /* Double + Single precision FPU */ - } - else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { - return 1U; /* Single precision FPU */ - } - else { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## Cache functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_CacheFunctions Cache Functions - \brief Functions that configure Instruction and Data cache. - @{ - */ - -/* Cache Size ID Register Macros */ -#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) -#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) - - -/** - \brief Enable I-Cache - \details Turns on I-Cache - */ -__STATIC_INLINE void SCB_EnableICache (void) -{ -#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - __DSB(); - __ISB(); - SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ - __DSB(); - __ISB(); -#endif -} - - -/** - \brief Disable I-Cache - \details Turns off I-Cache - */ -__STATIC_INLINE void SCB_DisableICache (void) -{ -#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - __DSB(); - __ISB(); -#endif -} - - -/** - \brief Invalidate I-Cache - \details Invalidates I-Cache - */ -__STATIC_INLINE void SCB_InvalidateICache (void) -{ -#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; - __DSB(); - __ISB(); -#endif -} - - -/** - \brief Enable D-Cache - \details Turns on D-Cache - */ -__STATIC_INLINE void SCB_EnableDCache (void) -{ -#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); -#if defined ( __CC_ARM ) - __schedule_barrier(); -#endif - } while (ways-- != 0U); - } while(sets-- != 0U); - __DSB(); - - SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ - - __DSB(); - __ISB(); -#endif -} - - -/** - \brief Disable D-Cache - \details Turns off D-Cache - */ -__STATIC_INLINE void SCB_DisableDCache (void) -{ -#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - register uint32_t ccsidr; - register uint32_t sets; - register uint32_t ways; - - SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ - __DSB(); - - SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); -#if defined ( __CC_ARM ) - __schedule_barrier(); -#endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); -#endif -} - - -/** - \brief Invalidate D-Cache - \details Invalidates D-Cache - */ -__STATIC_INLINE void SCB_InvalidateDCache (void) -{ -#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); -#if defined ( __CC_ARM ) - __schedule_barrier(); -#endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); -#endif -} - - -/** - \brief Clean D-Cache - \details Cleans D-Cache - */ -__STATIC_INLINE void SCB_CleanDCache (void) -{ -#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | - ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); -#if defined ( __CC_ARM ) - __schedule_barrier(); -#endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); -#endif -} - - -/** - \brief Clean & Invalidate D-Cache - \details Cleans and Invalidates D-Cache - */ -__STATIC_INLINE void SCB_CleanInvalidateDCache (void) -{ -#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); -#if defined ( __CC_ARM ) - __schedule_barrier(); -#endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); -#endif -} - - -/** - \brief D-Cache Invalidate by address - \details Invalidates D-Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t* addr, int32_t dsize) -{ -#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t)addr; - int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCIMVAC = op_addr; - op_addr += (uint32_t)linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); -#endif -} - - -/** - \brief D-Cache Clean by address - \details Cleans D-Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t* addr, int32_t dsize) -{ -#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t) addr; - int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCCMVAC = op_addr; - op_addr += (uint32_t)linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); -#endif -} - - -/** - \brief D-Cache Clean and Invalidate by address - \details Cleans and invalidates D_Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t* addr, int32_t dsize) -{ -#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t) addr; - int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCCIMVAC = op_addr; - op_addr += (uint32_t)linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); -#endif -} - - -/*@} end of CMSIS_Core_CacheFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) { /* ITM Port #0 enabled */ - while (ITM->PORT[0U].u32 == 0UL) { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } - else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_sc000.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_sc000.h deleted file mode 100644 index ed1063364..000000000 --- a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_sc000.h +++ /dev/null @@ -1,976 +0,0 @@ -/**************************************************************************//** - * @file core_sc000.h - * @brief CMSIS SC000 Core Peripheral Access Layer Header File - * @version V5.0.1 - * @date 25. November 2016 - ******************************************************************************/ -/* - * Copyright (c) 2009-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) -#pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_SC000_H_GENERIC -#define __CORE_SC000_H_GENERIC - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup SC000 - @{ - */ - -/* CMSIS SC000 definitions */ -#define __SC000_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ -#define __SC000_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ -#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ - __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_SC (000U) /*!< Cortex secure core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) -#if defined __TARGET_FPU_VFP -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#if defined __ARM_PCS_VFP -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __GNUC__ ) -#if defined (__VFP_FP__) && !defined(__SOFTFP__) -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __ICCARM__ ) -#if defined __ARMVFP__ -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __TI_ARM__ ) -#if defined __TI_VFP_SUPPORT__ -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __TASKING__ ) -#if defined __FPU_VFP__ -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __CSMC__ ) -#if ( __CSMC__ & 0x400U) -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC000_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC000_H_DEPENDANT -#define __CORE_SC000_H_DEPENDANT - -#ifdef __cplusplus -extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES -#ifndef __SC000_REV -#define __SC000_REV 0x0000U -#warning "__SC000_REV not defined in device header file; using default!" -#endif - -#ifndef __MPU_PRESENT -#define __MPU_PRESENT 0U -#warning "__MPU_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __NVIC_PRIO_BITS -#define __NVIC_PRIO_BITS 2U -#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" -#endif - -#ifndef __Vendor_SysTickConfig -#define __Vendor_SysTickConfig 0U -#warning "__Vendor_SysTickConfig not defined in device header file; using default!" -#endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus -#define __I volatile /*!< Defines 'read only' permissions */ -#else -#define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group SC000 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union { - struct { - uint32_t _reserved0: 28; /*!< bit: 0..27 Reserved */ - uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ - uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union { - struct { - uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union { - struct { - uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */ - uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1: 3; /*!< bit: 25..27 Reserved */ - uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ - uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union { - struct { - uint32_t _reserved0: 1; /*!< bit: 0 Reserved */ - uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct { - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct { - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - uint32_t RESERVED1[154U]; - __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct { - uint32_t RESERVED0[2U]; - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct { - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the SC000 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ -#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifndef CMSIS_NVIC_VIRTUAL -/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ -/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ -#define NVIC_EnableIRQ __NVIC_EnableIRQ -#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ -#define NVIC_DisableIRQ __NVIC_DisableIRQ -#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ -#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ -#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ -#define NVIC_SetPriority __NVIC_SetPriority -#define NVIC_GetPriority __NVIC_GetPriority -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifndef CMSIS_VECTAB_VIRTUAL -#define NVIC_SetVector __NVIC_SetVector -#define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t* vectors = (uint32_t*)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t* vectors = (uint32_t*)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) { /* wait until reset */ - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC000_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_sc300.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_sc300.h deleted file mode 100644 index a1b17e1ce..000000000 --- a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_sc300.h +++ /dev/null @@ -1,1851 +0,0 @@ -/**************************************************************************//** - * @file core_sc300.h - * @brief CMSIS SC300 Core Peripheral Access Layer Header File - * @version V5.0.1 - * @date 25. November 2016 - ******************************************************************************/ -/* - * Copyright (c) 2009-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) -#pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_SC300_H_GENERIC -#define __CORE_SC300_H_GENERIC - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup SC3000 - @{ - */ - -/* CMSIS SC300 definitions */ -#define __SC300_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ -#define __SC300_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ -#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ - __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_SC (300U) /*!< Cortex secure core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) -#if defined __TARGET_FPU_VFP -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#if defined __ARM_PCS_VFP -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __GNUC__ ) -#if defined (__VFP_FP__) && !defined(__SOFTFP__) -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __ICCARM__ ) -#if defined __ARMVFP__ -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __TI_ARM__ ) -#if defined __TI_VFP_SUPPORT__ -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __TASKING__ ) -#if defined __FPU_VFP__ -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __CSMC__ ) -#if ( __CSMC__ & 0x400U) -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC300_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC300_H_DEPENDANT -#define __CORE_SC300_H_DEPENDANT - -#ifdef __cplusplus -extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES -#ifndef __SC300_REV -#define __SC300_REV 0x0000U -#warning "__SC300_REV not defined in device header file; using default!" -#endif - -#ifndef __MPU_PRESENT -#define __MPU_PRESENT 0U -#warning "__MPU_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __NVIC_PRIO_BITS -#define __NVIC_PRIO_BITS 3U -#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" -#endif - -#ifndef __Vendor_SysTickConfig -#define __Vendor_SysTickConfig 0U -#warning "__Vendor_SysTickConfig not defined in device header file; using default!" -#endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus -#define __I volatile /*!< Defines 'read only' permissions */ -#else -#define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group SC300 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union { - struct { - uint32_t _reserved0: 27; /*!< bit: 0..26 Reserved */ - uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ - uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ - uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union { - struct { - uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union { - struct { - uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0: 1; /*!< bit: 9 Reserved */ - uint32_t ICI_IT_1: 6; /*!< bit: 10..15 ICI/IT part 1 */ - uint32_t _reserved1: 8; /*!< bit: 16..23 Reserved */ - uint32_t T: 1; /*!< bit: 24 Thumb bit */ - uint32_t ICI_IT_2: 2; /*!< bit: 25..26 ICI/IT part 2 */ - uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ - uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ - uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ -#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ -#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union { - struct { - uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct { - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct { - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - uint32_t RESERVED1[129U]; - __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct { - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - uint32_t RESERVED1[1U]; -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct { - __OM union { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct { - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct { - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct { - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ -#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifndef CMSIS_NVIC_VIRTUAL -#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping -#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping -#define NVIC_EnableIRQ __NVIC_EnableIRQ -#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ -#define NVIC_DisableIRQ __NVIC_DisableIRQ -#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ -#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ -#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -#define NVIC_GetActive __NVIC_GetActive -#define NVIC_SetPriority __NVIC_SetPriority -#define NVIC_GetPriority __NVIC_GetPriority -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifndef CMSIS_VECTAB_VIRTUAL -#define NVIC_SetVector __NVIC_SetVector -#define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t* vectors = (uint32_t*)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t* vectors = (uint32_t*)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) { /* wait until reset */ - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) { /* ITM Port #0 enabled */ - while (ITM->PORT[0U].u32 == 0UL) { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } - else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC300_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/tz_context.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/tz_context.h deleted file mode 100644 index cd6d8ab07..000000000 --- a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/tz_context.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (c) 2015-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * ---------------------------------------------------------------------------- - * - * $Date: 21. September 2016 - * $Revision: V1.0 - * - * Project: TrustZone for ARMv8-M - * Title: Context Management for ARMv8-M TrustZone - * - * Version 1.0 - * Initial Release - *---------------------------------------------------------------------------*/ - -#ifndef TZ_CONTEXT_H -#define TZ_CONTEXT_H - -#include - -#ifndef TZ_MODULEID_T -#define TZ_MODULEID_T -/// \details Data type that identifies secure software modules called by a process. -typedef uint32_t TZ_ModuleId_t; -#endif - -/// \details TZ Memory ID identifies an allocated memory slot. -typedef uint32_t TZ_MemoryId_t; - -/// Initialize secure context memory system -/// \return execution status (1: success, 0: error) -uint32_t TZ_InitContextSystem_S (void); - -/// Allocate context memory for calling secure software modules in TrustZone -/// \param[in] module identifies software modules called from non-secure mode -/// \return value != 0 id TrustZone memory slot identifier -/// \return value 0 no memory available or internal error -TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); - -/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); - -/// Load secure context (called on RTOS thread context switch) -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); - -/// Store secure context (called on RTOS thread context switch) -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); - -#endif // TZ_CONTEXT_H diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_common_tables.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_common_tables.h deleted file mode 100644 index dfea7460e..000000000 --- a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_common_tables.h +++ /dev/null @@ -1,121 +0,0 @@ -/* ---------------------------------------------------------------------- - * Project: CMSIS DSP Library - * Title: arm_common_tables.h - * Description: Extern declaration for common tables - * - * $Date: 27. January 2017 - * $Revision: V.1.5.1 - * - * Target Processor: Cortex-M cores - * -------------------------------------------------------------------- */ -/* - * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef _ARM_COMMON_TABLES_H -#define _ARM_COMMON_TABLES_H - -#include "arm_math.h" - -extern const uint16_t armBitRevTable[1024]; -extern const q15_t armRecipTableQ15[64]; -extern const q31_t armRecipTableQ31[64]; -extern const float32_t twiddleCoef_16[32]; -extern const float32_t twiddleCoef_32[64]; -extern const float32_t twiddleCoef_64[128]; -extern const float32_t twiddleCoef_128[256]; -extern const float32_t twiddleCoef_256[512]; -extern const float32_t twiddleCoef_512[1024]; -extern const float32_t twiddleCoef_1024[2048]; -extern const float32_t twiddleCoef_2048[4096]; -extern const float32_t twiddleCoef_4096[8192]; -#define twiddleCoef twiddleCoef_4096 -extern const q31_t twiddleCoef_16_q31[24]; -extern const q31_t twiddleCoef_32_q31[48]; -extern const q31_t twiddleCoef_64_q31[96]; -extern const q31_t twiddleCoef_128_q31[192]; -extern const q31_t twiddleCoef_256_q31[384]; -extern const q31_t twiddleCoef_512_q31[768]; -extern const q31_t twiddleCoef_1024_q31[1536]; -extern const q31_t twiddleCoef_2048_q31[3072]; -extern const q31_t twiddleCoef_4096_q31[6144]; -extern const q15_t twiddleCoef_16_q15[24]; -extern const q15_t twiddleCoef_32_q15[48]; -extern const q15_t twiddleCoef_64_q15[96]; -extern const q15_t twiddleCoef_128_q15[192]; -extern const q15_t twiddleCoef_256_q15[384]; -extern const q15_t twiddleCoef_512_q15[768]; -extern const q15_t twiddleCoef_1024_q15[1536]; -extern const q15_t twiddleCoef_2048_q15[3072]; -extern const q15_t twiddleCoef_4096_q15[6144]; -extern const float32_t twiddleCoef_rfft_32[32]; -extern const float32_t twiddleCoef_rfft_64[64]; -extern const float32_t twiddleCoef_rfft_128[128]; -extern const float32_t twiddleCoef_rfft_256[256]; -extern const float32_t twiddleCoef_rfft_512[512]; -extern const float32_t twiddleCoef_rfft_1024[1024]; -extern const float32_t twiddleCoef_rfft_2048[2048]; -extern const float32_t twiddleCoef_rfft_4096[4096]; - -/* floating-point bit reversal tables */ -#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20) -#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48) -#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56) -#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) -#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) -#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) -#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800) -#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808) -#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH]; - -/* fixed-point bit reversal tables */ -#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12) -#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24) -#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56) -#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112) -#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240) -#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480) -#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992) -#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) -#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; - -/* Tables for Fast Math Sine and Cosine */ -extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; -extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; -extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; - -#endif /* ARM_COMMON_TABLES_H */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_const_structs.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_const_structs.h deleted file mode 100644 index 84ffe8b85..000000000 --- a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_const_structs.h +++ /dev/null @@ -1,66 +0,0 @@ -/* ---------------------------------------------------------------------- - * Project: CMSIS DSP Library - * Title: arm_const_structs.h - * Description: Constant structs that are initialized for user convenience. - * For example, some can be given as arguments to the arm_cfft_f32() function. - * - * $Date: 27. January 2017 - * $Revision: V.1.5.1 - * - * Target Processor: Cortex-M cores - * -------------------------------------------------------------------- */ -/* - * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef _ARM_CONST_STRUCTS_H -#define _ARM_CONST_STRUCTS_H - -#include "arm_math.h" -#include "arm_common_tables.h" - -extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; -extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; -extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; -extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; -extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; -extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; -extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; -extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; -extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; - -extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; -extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; -extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; -extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; -extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; -extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; -extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; -extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; -extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; - -extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; -extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; -extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; -extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; -extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; -extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; -extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; -extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; -extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; - -#endif diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_math.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_math.h deleted file mode 100644 index 9d678052b..000000000 --- a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_math.h +++ /dev/null @@ -1,7122 +0,0 @@ -/* ---------------------------------------------------------------------- - * Project: CMSIS DSP Library - * Title: arm_math.h - * Description: Public header file for CMSIS DSP Library - * - * $Date: 27. January 2017 - * $Revision: V.1.5.1 - * - * Target Processor: Cortex-M cores - * -------------------------------------------------------------------- */ -/* - * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/** - \mainpage CMSIS DSP Software Library - * - * Introduction - * ------------ - * - * This user manual describes the CMSIS DSP software library, - * a suite of common signal processing functions for use on Cortex-M processor based devices. - * - * The library is divided into a number of functions each covering a specific category: - * - Basic math functions - * - Fast math functions - * - Complex math functions - * - Filters - * - Matrix functions - * - Transforms - * - Motor control functions - * - Statistical functions - * - Support functions - * - Interpolation functions - * - * The library has separate functions for operating on 8-bit integers, 16-bit integers, - * 32-bit integer and 32-bit floating-point values. - * - * Using the Library - * ------------ - * - * The library installer contains prebuilt versions of the libraries in the Lib folder. - * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit) - * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit) - * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit) - * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on) - * - arm_cortexM7l_math.lib (Cortex-M7, Little endian) - * - arm_cortexM7b_math.lib (Cortex-M7, Big endian) - * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit) - * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit) - * - arm_cortexM4l_math.lib (Cortex-M4, Little endian) - * - arm_cortexM4b_math.lib (Cortex-M4, Big endian) - * - arm_cortexM3l_math.lib (Cortex-M3, Little endian) - * - arm_cortexM3b_math.lib (Cortex-M3, Big endian) - * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian) - * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian) - * - arm_ARMv8MBLl_math.lib (ARMv8M Baseline, Little endian) - * - arm_ARMv8MMLl_math.lib (ARMv8M Mainline, Little endian) - * - arm_ARMv8MMLlfsp_math.lib (ARMv8M Mainline, Little endian, Single Precision Floating Point Unit) - * - arm_ARMv8MMLld_math.lib (ARMv8M Mainline, Little endian, DSP instructions) - * - arm_ARMv8MMLldfsp_math.lib (ARMv8M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit) - * - * The library functions are declared in the public file arm_math.h which is placed in the Include folder. - * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single - * public header file arm_math.h for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. - * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or - * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. - * For ARMv8M cores define pre processor MACRO ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML. - * Set Pre processor MACRO __DSP_PRESENT if ARMv8M Mainline core supports DSP instructions. - * - * - * Examples - * -------- - * - * The library ships with a number of examples which demonstrate how to use the library functions. - * - * Toolchain Support - * ------------ - * - * The library has been developed and tested with MDK-ARM version 5.14.0.0 - * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. - * - * Building the Library - * ------------ - * - * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. - * - arm_cortexM_math.uvprojx - * - * - * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. - * - * Pre-processor Macros - * ------------ - * - * Each library project have differant pre-processor macros. - * - * - UNALIGNED_SUPPORT_DISABLE: - * - * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access - * - * - ARM_MATH_BIG_ENDIAN: - * - * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. - * - * - ARM_MATH_MATRIX_CHECK: - * - * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices - * - * - ARM_MATH_ROUNDING: - * - * Define macro ARM_MATH_ROUNDING for rounding on support functions - * - * - ARM_MATH_CMx: - * - * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target - * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and - * ARM_MATH_CM7 for building the library on cortex-M7. - * - * - ARM_MATH_ARMV8MxL: - * - * Define macro ARM_MATH_ARMV8MBL for building the library on ARMv8M Baseline target, ARM_MATH_ARMV8MBL for building library - * on ARMv8M Mainline target. - * - * - __FPU_PRESENT: - * - * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries. - * - * - __DSP_PRESENT: - * - * Initialize macro __DSP_PRESENT = 1 when ARMv8M Mainline core supports DSP instructions. - * - *
- * CMSIS-DSP in ARM::CMSIS Pack - * ----------------------------- - * - * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: - * |File/Folder |Content | - * |------------------------------|------------------------------------------------------------------------| - * |\b CMSIS\\Documentation\\DSP | This documentation | - * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | - * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | - * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | - * - *
- * Revision History of CMSIS-DSP - * ------------ - * Please refer to \ref ChangeLog_pg. - * - * Copyright Notice - * ------------ - * - * Copyright (C) 2010-2015 ARM Limited. All rights reserved. - */ - - -/** - * @defgroup groupMath Basic Math Functions - */ - -/** - * @defgroup groupFastMath Fast Math Functions - * This set of functions provides a fast approximation to sine, cosine, and square root. - * As compared to most of the other functions in the CMSIS math library, the fast math functions - * operate on individual values and not arrays. - * There are separate functions for Q15, Q31, and floating-point data. - * - */ - -/** - * @defgroup groupCmplxMath Complex Math Functions - * This set of functions operates on complex data vectors. - * The data in the complex arrays is stored in an interleaved fashion - * (real, imag, real, imag, ...). - * In the API functions, the number of samples in a complex array refers - * to the number of complex values; the array contains twice this number of - * real values. - */ - -/** - * @defgroup groupFilters Filtering Functions - */ - -/** - * @defgroup groupMatrix Matrix Functions - * - * This set of functions provides basic matrix math operations. - * The functions operate on matrix data structures. For example, - * the type - * definition for the floating-point matrix structure is shown - * below: - * 
- *     typedef struct
- *     {
- *       uint16_t numRows;     // number of rows of the matrix.
- *       uint16_t numCols;     // number of columns of the matrix.
- *       float32_t *pData;     // points to the data of the matrix.
- *     } arm_matrix_instance_f32;
- *
- * There are similar definitions for Q15 and Q31 data types. - * - * The structure specifies the size of the matrix and then points to - * an array of data. The array is of size numRows X numCols - * and the values are arranged in row order. That is, the - * matrix element (i, j) is stored at: - * 
- *     pData[i*numCols + j]
- *
- * - * \par Init Functions - * There is an associated initialization function for each type of matrix - * data structure. - * The initialization function sets the values of the internal structure fields. - * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() - * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. - * - * \par - * Use of the initialization function is optional. However, if initialization function is used - * then the instance structure cannot be placed into a const data section. - * To place the instance structure in a const data - * section, manually initialize the data structure. For example: - * 
- * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
- *
- * where nRows specifies the number of rows, nColumns - * specifies the number of columns, and pData points to the - * data array. - * - * \par Size Checking - * By default all of the matrix functions perform size checking on the input and - * output matrices. For example, the matrix addition function verifies that the - * two input matrices and the output matrix all have the same number of rows and - * columns. If the size check fails the functions return: - * 
- *     ARM_MATH_SIZE_MISMATCH
- *
- * Otherwise the functions return - * 
- *     ARM_MATH_SUCCESS
- *
- * There is some overhead associated with this matrix size checking. - * The matrix size checking is enabled via the \#define - * 
- *     ARM_MATH_MATRIX_CHECK
- *
- * within the library project settings. By default this macro is defined - * and size checking is enabled. By changing the project settings and - * undefining this macro size checking is eliminated and the functions - * run a bit faster. With size checking disabled the functions always - * return ARM_MATH_SUCCESS. - */ - -/** - * @defgroup groupTransforms Transform Functions - */ - -/** - * @defgroup groupController Controller Functions - */ - -/** - * @defgroup groupStats Statistics Functions - */ -/** - * @defgroup groupSupport Support Functions - */ - -/** - * @defgroup groupInterpolation Interpolation Functions - * These functions perform 1- and 2-dimensional interpolation of data. - * Linear interpolation is used for 1-dimensional data and - * bilinear interpolation is used for 2-dimensional data. - */ - -/** - * @defgroup groupExamples Examples - */ -#ifndef _ARM_MATH_H -#define _ARM_MATH_H - -/* ignore some GCC warnings */ -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" -#endif - -#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ - -#if defined(ARM_MATH_CM7) -#include "core_cm7.h" -#define ARM_MATH_DSP -#elif defined (ARM_MATH_CM4) -#include "core_cm4.h" -#define ARM_MATH_DSP -#elif defined (ARM_MATH_CM3) -#include "core_cm3.h" -#elif defined (ARM_MATH_CM0) -#include "core_cm0.h" -#define ARM_MATH_CM0_FAMILY -#elif defined (ARM_MATH_CM0PLUS) -#include "core_cm0plus.h" -#define ARM_MATH_CM0_FAMILY -#elif defined (ARM_MATH_ARMV8MBL) -#include "core_armv8mbl.h" -#define ARM_MATH_CM0_FAMILY -#elif defined (ARM_MATH_ARMV8MML) -#include "core_armv8mml.h" -#if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1)) -#define ARM_MATH_DSP -#endif -#else -#error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML" -#endif - -#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ -#include "string.h" -#include "math.h" -#ifdef __cplusplus -extern "C" -{ -#endif - - -/** - * @brief Macros required for reciprocal calculation in Normalized LMS - */ - -#define DELTA_Q31 (0x100) -#define DELTA_Q15 0x5 -#define INDEX_MASK 0x0000003F -#ifndef PI -#define PI 3.14159265358979f -#endif - -/** - * @brief Macros required for SINE and COSINE Fast math approximations - */ - -#define FAST_MATH_TABLE_SIZE 512 -#define FAST_MATH_Q31_SHIFT (32 - 10) -#define FAST_MATH_Q15_SHIFT (16 - 10) -#define CONTROLLER_Q31_SHIFT (32 - 9) -#define TABLE_SPACING_Q31 0x400000 -#define TABLE_SPACING_Q15 0x80 - -/** - * @brief Macros required for SINE and COSINE Controller functions - */ -/* 1.31(q31) Fixed value of 2/360 */ -/* -1 to +1 is divided into 360 values so total spacing is (2/360) */ -#define INPUT_SPACING 0xB60B61 - -/** - * @brief Macro for Unaligned Support - */ -#ifndef UNALIGNED_SUPPORT_DISABLE -#define ALIGN4 -#else -#if defined (__GNUC__) -#define ALIGN4 __attribute__((aligned(4))) -#else -#define ALIGN4 __align(4) -#endif -#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ - -/** - * @brief Error status returned by some functions in the library. - */ - -typedef enum { - ARM_MATH_SUCCESS = 0, /**< No error */ - ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ - ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ - ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ - ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ - ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ - ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ -} arm_status; - -/** - * @brief 8-bit fractional data type in 1.7 format. - */ -typedef int8_t q7_t; - -/** - * @brief 16-bit fractional data type in 1.15 format. - */ -typedef int16_t q15_t; - -/** - * @brief 32-bit fractional data type in 1.31 format. - */ -typedef int32_t q31_t; - -/** - * @brief 64-bit fractional data type in 1.63 format. - */ -typedef int64_t q63_t; - -/** - * @brief 32-bit floating-point type definition. - */ -typedef float float32_t; - -/** - * @brief 64-bit floating-point type definition. - */ -typedef double float64_t; - -/** - * @brief definition to read/write two 16 bit values. - */ -#if defined ( __CC_ARM ) -#define __SIMD32_TYPE int32_t __packed -#define CMSIS_UNUSED __attribute__((unused)) -#define CMSIS_INLINE __attribute__((always_inline)) - -#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) -#define __SIMD32_TYPE int32_t -#define CMSIS_UNUSED __attribute__((unused)) -#define CMSIS_INLINE __attribute__((always_inline)) - -#elif defined ( __GNUC__ ) -#define __SIMD32_TYPE int32_t -#define CMSIS_UNUSED __attribute__((unused)) -#define CMSIS_INLINE __attribute__((always_inline)) - -#elif defined ( __ICCARM__ ) -#define __SIMD32_TYPE int32_t __packed -#define CMSIS_UNUSED -#define CMSIS_INLINE - -#elif defined ( __TI_ARM__ ) -#define __SIMD32_TYPE int32_t -#define CMSIS_UNUSED __attribute__((unused)) -#define CMSIS_INLINE - -#elif defined ( __CSMC__ ) -#define __SIMD32_TYPE int32_t -#define CMSIS_UNUSED -#define CMSIS_INLINE - -#elif defined ( __TASKING__ ) -#define __SIMD32_TYPE __unaligned int32_t -#define CMSIS_UNUSED -#define CMSIS_INLINE - -#else -#error Unknown compiler -#endif - -#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) -#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) -#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) -#define __SIMD64(addr) (*(int64_t **) & (addr)) - -/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ -#if !defined (ARM_MATH_DSP) -/** - * @brief definition to pack two 16 bit values. - */ -#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ - (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) -#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ - (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) - -/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ -#endif /* !defined (ARM_MATH_DSP) */ - -/** -* @brief definition to pack four 8 bit values. -*/ -#ifndef ARM_MATH_BIG_ENDIAN - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) -#else - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) - -#endif - - -/** - * @brief Clips Q63 to Q31 values. - */ -CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31( - q63_t x) -{ - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; -} - -/** - * @brief Clips Q63 to Q15 values. - */ -CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15( - q63_t x) -{ - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); -} - -/** - * @brief Clips Q31 to Q7 values. - */ -CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7( - q31_t x) -{ - return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? - ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; -} - -/** - * @brief Clips Q31 to Q15 values. - */ -CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15( - q31_t x) -{ - return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? - ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; -} - -/** - * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. - */ - -CMSIS_INLINE __STATIC_INLINE q63_t mult32x64( - q63_t x, - q31_t y) -{ - return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + - (((q63_t) (x >> 32) * y))); -} - -/* - #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) - #define __CLZ __clz - #endif - */ -/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */ -#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ) -CMSIS_INLINE __STATIC_INLINE uint32_t __CLZ( - q31_t data); - -CMSIS_INLINE __STATIC_INLINE uint32_t __CLZ( - q31_t data) -{ - uint32_t count = 0; - uint32_t mask = 0x80000000; - - while ((data & mask) == 0) { - count += 1u; - mask = mask >> 1u; - } - - return (count); -} -#endif - -/** - * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. - */ - -CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31( - q31_t in, - q31_t* dst, - q31_t* pRecipTable) -{ - q31_t out; - uint32_t tempVal; - uint32_t index, i; - uint32_t signBits; - - if (in > 0) { - signBits = ((uint32_t) (__CLZ( in) - 1)); - } - else { - signBits = ((uint32_t) (__CLZ(-in) - 1)); - } - - /* Convert input sample to 1.31 format */ - in = (in << signBits); - - /* calculation of index for initial approximated Val */ - index = (uint32_t)(in >> 24); - index = (index & INDEX_MASK); - - /* 1.31 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0u; i < 2u; i++) { - tempVal = (uint32_t) (((q63_t) in * out) >> 31); - tempVal = 0x7FFFFFFFu - tempVal; - /* 1.31 with exp 1 */ - /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ - out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1u); -} - - -/** - * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. - */ -CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15( - q15_t in, - q15_t* dst, - q15_t* pRecipTable) -{ - q15_t out = 0; - uint32_t tempVal = 0; - uint32_t index = 0, i = 0; - uint32_t signBits = 0; - - if (in > 0) { - signBits = ((uint32_t)(__CLZ( in) - 17)); - } - else { - signBits = ((uint32_t)(__CLZ(-in) - 17)); - } - - /* Convert input sample to 1.15 format */ - in = (in << signBits); - - /* calculation of index for initial approximated Val */ - index = (uint32_t)(in >> 8); - index = (index & INDEX_MASK); - - /* 1.15 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0u; i < 2u; i++) { - tempVal = (uint32_t) (((q31_t) in * out) >> 15); - tempVal = 0x7FFFu - tempVal; - /* 1.15 with exp 1 */ - out = (q15_t) (((q31_t) out * tempVal) >> 14); - /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1); -} - - -/* - * @brief C custom defined intrinisic function for only M0 processors - */ -#if defined(ARM_MATH_CM0_FAMILY) -CMSIS_INLINE __STATIC_INLINE q31_t __SSAT( - q31_t x, - uint32_t y) -{ - int32_t posMax, negMin; - uint32_t i; - - posMax = 1; - for (i = 0; i < (y - 1); i++) { - posMax = posMax * 2; - } - - if (x > 0) { - posMax = (posMax - 1); - - if (x > posMax) { - x = posMax; - } - } - else { - negMin = -posMax; - - if (x < negMin) { - x = negMin; - } - } - return (x); -} -#endif /* end of ARM_MATH_CM0_FAMILY */ - - -/* - * @brief C custom defined intrinsic function for M3 and M0 processors - */ -/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ -#if !defined (ARM_MATH_DSP) - -/* - * @brief C custom defined QADD8 for M3 and M0 processors - */ -CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8( - uint32_t x, - uint32_t y) -{ - q31_t r, s, t, u; - - r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; - s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; - t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; - u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; - - return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); -} - - -/* - * @brief C custom defined QSUB8 for M3 and M0 processors - */ -CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8( - uint32_t x, - uint32_t y) -{ - q31_t r, s, t, u; - - r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; - s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; - t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; - u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; - - return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); -} - - -/* - * @brief C custom defined QADD16 for M3 and M0 processors - */ -CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16( - uint32_t x, - uint32_t y) -{ - /* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ - q31_t r = 0, s = 0; - - r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); -} - - -/* - * @brief C custom defined SHADD16 for M3 and M0 processors - */ -CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16( - uint32_t x, - uint32_t y) -{ - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); -} - - -/* - * @brief C custom defined QSUB16 for M3 and M0 processors - */ -CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16( - uint32_t x, - uint32_t y) -{ - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); -} - - -/* - * @brief C custom defined SHSUB16 for M3 and M0 processors - */ -CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16( - uint32_t x, - uint32_t y) -{ - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); -} - - -/* - * @brief C custom defined QASX for M3 and M0 processors - */ -CMSIS_INLINE __STATIC_INLINE uint32_t __QASX( - uint32_t x, - uint32_t y) -{ - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); -} - - -/* - * @brief C custom defined SHASX for M3 and M0 processors - */ -CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX( - uint32_t x, - uint32_t y) -{ - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); -} - - -/* - * @brief C custom defined QSAX for M3 and M0 processors - */ -CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX( - uint32_t x, - uint32_t y) -{ - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); -} - - -/* - * @brief C custom defined SHSAX for M3 and M0 processors - */ -CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX( - uint32_t x, - uint32_t y) -{ - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); -} - - -/* - * @brief C custom defined SMUSDX for M3 and M0 processors - */ -CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX( - uint32_t x, - uint32_t y) -{ - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); -} - -/* - * @brief C custom defined SMUADX for M3 and M0 processors - */ -CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX( - uint32_t x, - uint32_t y) -{ - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); -} - - -/* - * @brief C custom defined QADD for M3 and M0 processors - */ -CMSIS_INLINE __STATIC_INLINE int32_t __QADD( - int32_t x, - int32_t y) -{ - return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); -} - - -/* - * @brief C custom defined QSUB for M3 and M0 processors - */ -CMSIS_INLINE __STATIC_INLINE int32_t __QSUB( - int32_t x, - int32_t y) -{ - return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); -} - - -/* - * @brief C custom defined SMLAD for M3 and M0 processors - */ -CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD( - uint32_t x, - uint32_t y, - uint32_t sum) -{ - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + - ( ((q31_t)sum ) ) )); -} - - -/* - * @brief C custom defined SMLADX for M3 and M0 processors - */ -CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX( - uint32_t x, - uint32_t y, - uint32_t sum) -{ - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q31_t)sum ) ) )); -} - - -/* - * @brief C custom defined SMLSDX for M3 and M0 processors - */ -CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX( - uint32_t x, - uint32_t y, - uint32_t sum) -{ - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q31_t)sum ) ) )); -} - - -/* - * @brief C custom defined SMLALD for M3 and M0 processors - */ -CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD( - uint32_t x, - uint32_t y, - uint64_t sum) -{ - /* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ - return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + - ( ((q63_t)sum ) ) )); -} - - -/* - * @brief C custom defined SMLALDX for M3 and M0 processors - */ -CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX( - uint32_t x, - uint32_t y, - uint64_t sum) -{ - /* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ - return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q63_t)sum ) ) )); -} - - -/* - * @brief C custom defined SMUAD for M3 and M0 processors - */ -CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD( - uint32_t x, - uint32_t y) -{ - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); -} - - -/* - * @brief C custom defined SMUSD for M3 and M0 processors - */ -CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD( - uint32_t x, - uint32_t y) -{ - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); -} - - -/* - * @brief C custom defined SXTB16 for M3 and M0 processors - */ -CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16( - uint32_t x) -{ - return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | - ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); -} - -/* - * @brief C custom defined SMMLA for M3 and M0 processors - */ -CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA( - int32_t x, - int32_t y, - int32_t sum) -{ - return (sum + (int32_t) (((int64_t) x * y) >> 32)); -} - -#if 0 -/* - * @brief C custom defined PKHBT for unavailable DSP extension - */ -CMSIS_INLINE __STATIC_INLINE uint32_t __PKHBT( - uint32_t x, - uint32_t y, - uint32_t leftshift) -{ - return ( ((x ) & 0x0000FFFFUL) | - ((y << leftshift) & 0xFFFF0000UL) ); -} - -/* - * @brief C custom defined PKHTB for unavailable DSP extension - */ -CMSIS_INLINE __STATIC_INLINE uint32_t __PKHTB( - uint32_t x, - uint32_t y, - uint32_t rightshift) -{ - return ( ((x ) & 0xFFFF0000UL) | - ((y >> rightshift) & 0x0000FFFFUL) ); -} -#endif - -/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ -#endif /* !defined (ARM_MATH_DSP) */ - - -/** - * @brief Instance structure for the Q7 FIR filter. - */ -typedef struct { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q7_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q7_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ -} arm_fir_instance_q7; - -/** - * @brief Instance structure for the Q15 FIR filter. - */ -typedef struct { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q15_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ -} arm_fir_instance_q15; - -/** - * @brief Instance structure for the Q31 FIR filter. - */ -typedef struct { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q31_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ -} arm_fir_instance_q31; - -/** - * @brief Instance structure for the floating-point FIR filter. - */ -typedef struct { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - float32_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ -} arm_fir_instance_f32; - - -/** - * @brief Processing function for the Q7 FIR filter. - * @param[in] S points to an instance of the Q7 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ -void arm_fir_q7( - const arm_fir_instance_q7* S, - q7_t* pSrc, - q7_t* pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q7 FIR filter. - * @param[in,out] S points to an instance of the Q7 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed. - */ -void arm_fir_init_q7( - arm_fir_instance_q7* S, - uint16_t numTaps, - q7_t* pCoeffs, - q7_t* pState, - uint32_t blockSize); - - -/** - * @brief Processing function for the Q15 FIR filter. - * @param[in] S points to an instance of the Q15 FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ -void arm_fir_q15( - const arm_fir_instance_q15* S, - q15_t* pSrc, - q15_t* pDst, - uint32_t blockSize); - - -/** - * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ -void arm_fir_fast_q15( - const arm_fir_instance_q15* S, - q15_t* pSrc, - q15_t* pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 FIR filter. - * @param[in,out] S points to an instance of the Q15 FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if - * numTaps is not a supported value. - */ -arm_status arm_fir_init_q15( - arm_fir_instance_q15* S, - uint16_t numTaps, - q15_t* pCoeffs, - q15_t* pState, - uint32_t blockSize); - - -/** - * @brief Processing function for the Q31 FIR filter. - * @param[in] S points to an instance of the Q31 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ -void arm_fir_q31( - const arm_fir_instance_q31* S, - q31_t* pSrc, - q31_t* pDst, - uint32_t blockSize); - - -/** - * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ -void arm_fir_fast_q31( - const arm_fir_instance_q31* S, - q31_t* pSrc, - q31_t* pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q31 FIR filter. - * @param[in,out] S points to an instance of the Q31 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - */ -void arm_fir_init_q31( - arm_fir_instance_q31* S, - uint16_t numTaps, - q31_t* pCoeffs, - q31_t* pState, - uint32_t blockSize); - - -/** - * @brief Processing function for the floating-point FIR filter. - * @param[in] S points to an instance of the floating-point FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ -void arm_fir_f32( - const arm_fir_instance_f32* S, - float32_t* pSrc, - float32_t* pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the floating-point FIR filter. - * @param[in,out] S points to an instance of the floating-point FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - */ -void arm_fir_init_f32( - arm_fir_instance_f32* S, - uint16_t numTaps, - float32_t* pCoeffs, - float32_t* pState, - uint32_t blockSize); - - -/** - * @brief Instance structure for the Q15 Biquad cascade filter. - */ -typedef struct { - int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q15_t* pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q15_t* pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ -} arm_biquad_casd_df1_inst_q15; - -/** - * @brief Instance structure for the Q31 Biquad cascade filter. - */ -typedef struct { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q31_t* pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t* pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ -} arm_biquad_casd_df1_inst_q31; - -/** - * @brief Instance structure for the floating-point Biquad cascade filter. - */ -typedef struct { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t* pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t* pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ -} arm_biquad_casd_df1_inst_f32; - - -/** - * @brief Processing function for the Q15 Biquad cascade filter. - * @param[in] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ -void arm_biquad_cascade_df1_q15( - const arm_biquad_casd_df1_inst_q15* S, - q15_t* pSrc, - q15_t* pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 Biquad cascade filter. - * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - */ -void arm_biquad_cascade_df1_init_q15( - arm_biquad_casd_df1_inst_q15* S, - uint8_t numStages, - q15_t* pCoeffs, - q15_t* pState, - int8_t postShift); - - -/** - * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ -void arm_biquad_cascade_df1_fast_q15( - const arm_biquad_casd_df1_inst_q15* S, - q15_t* pSrc, - q15_t* pDst, - uint32_t blockSize); - - -/** - * @brief Processing function for the Q31 Biquad cascade filter - * @param[in] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ -void arm_biquad_cascade_df1_q31( - const arm_biquad_casd_df1_inst_q31* S, - q31_t* pSrc, - q31_t* pDst, - uint32_t blockSize); - - -/** - * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ -void arm_biquad_cascade_df1_fast_q31( - const arm_biquad_casd_df1_inst_q31* S, - q31_t* pSrc, - q31_t* pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q31 Biquad cascade filter. - * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - */ -void arm_biquad_cascade_df1_init_q31( - arm_biquad_casd_df1_inst_q31* S, - uint8_t numStages, - q31_t* pCoeffs, - q31_t* pState, - int8_t postShift); - - -/** - * @brief Processing function for the floating-point Biquad cascade filter. - * @param[in] S points to an instance of the floating-point Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ -void arm_biquad_cascade_df1_f32( - const arm_biquad_casd_df1_inst_f32* S, - float32_t* pSrc, - float32_t* pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the floating-point Biquad cascade filter. - * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ -void arm_biquad_cascade_df1_init_f32( - arm_biquad_casd_df1_inst_f32* S, - uint8_t numStages, - float32_t* pCoeffs, - float32_t* pState); - - -/** - * @brief Instance structure for the floating-point matrix structure. - */ -typedef struct { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float32_t* pData; /**< points to the data of the matrix. */ -} arm_matrix_instance_f32; - - -/** - * @brief Instance structure for the floating-point matrix structure. - */ -typedef struct { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float64_t* pData; /**< points to the data of the matrix. */ -} arm_matrix_instance_f64; - -/** - * @brief Instance structure for the Q15 matrix structure. - */ -typedef struct { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q15_t* pData; /**< points to the data of the matrix. */ -} arm_matrix_instance_q15; - -/** - * @brief Instance structure for the Q31 matrix structure. - */ -typedef struct { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q31_t* pData; /**< points to the data of the matrix. */ -} arm_matrix_instance_q31; - - -/** - * @brief Floating-point matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ -arm_status arm_mat_add_f32( - const arm_matrix_instance_f32* pSrcA, - const arm_matrix_instance_f32* pSrcB, - arm_matrix_instance_f32* pDst); - - -/** - * @brief Q15 matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ -arm_status arm_mat_add_q15( - const arm_matrix_instance_q15* pSrcA, - const arm_matrix_instance_q15* pSrcB, - arm_matrix_instance_q15* pDst); - - -/** - * @brief Q31 matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ -arm_status arm_mat_add_q31( - const arm_matrix_instance_q31* pSrcA, - const arm_matrix_instance_q31* pSrcB, - arm_matrix_instance_q31* pDst); - - -/** - * @brief Floating-point, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ -arm_status arm_mat_cmplx_mult_f32( - const arm_matrix_instance_f32* pSrcA, - const arm_matrix_instance_f32* pSrcB, - arm_matrix_instance_f32* pDst); - - -/** - * @brief Q15, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ -arm_status arm_mat_cmplx_mult_q15( - const arm_matrix_instance_q15* pSrcA, - const arm_matrix_instance_q15* pSrcB, - arm_matrix_instance_q15* pDst, - q15_t* pScratch); - - -/** - * @brief Q31, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ -arm_status arm_mat_cmplx_mult_q31( - const arm_matrix_instance_q31* pSrcA, - const arm_matrix_instance_q31* pSrcB, - arm_matrix_instance_q31* pDst); - - -/** - * @brief Floating-point matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ -arm_status arm_mat_trans_f32( - const arm_matrix_instance_f32* pSrc, - arm_matrix_instance_f32* pDst); - - -/** - * @brief Q15 matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ -arm_status arm_mat_trans_q15( - const arm_matrix_instance_q15* pSrc, - arm_matrix_instance_q15* pDst); - - -/** - * @brief Q31 matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ -arm_status arm_mat_trans_q31( - const arm_matrix_instance_q31* pSrc, - arm_matrix_instance_q31* pDst); - - -/** - * @brief Floating-point matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ -arm_status arm_mat_mult_f32( - const arm_matrix_instance_f32* pSrcA, - const arm_matrix_instance_f32* pSrcB, - arm_matrix_instance_f32* pDst); - - -/** - * @brief Q15 matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @param[in] pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ -arm_status arm_mat_mult_q15( - const arm_matrix_instance_q15* pSrcA, - const arm_matrix_instance_q15* pSrcB, - arm_matrix_instance_q15* pDst, - q15_t* pState); - - -/** - * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @param[in] pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ -arm_status arm_mat_mult_fast_q15( - const arm_matrix_instance_q15* pSrcA, - const arm_matrix_instance_q15* pSrcB, - arm_matrix_instance_q15* pDst, - q15_t* pState); - - -/** - * @brief Q31 matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ -arm_status arm_mat_mult_q31( - const arm_matrix_instance_q31* pSrcA, - const arm_matrix_instance_q31* pSrcB, - arm_matrix_instance_q31* pDst); - - -/** - * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ -arm_status arm_mat_mult_fast_q31( - const arm_matrix_instance_q31* pSrcA, - const arm_matrix_instance_q31* pSrcB, - arm_matrix_instance_q31* pDst); - - -/** - * @brief Floating-point matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ -arm_status arm_mat_sub_f32( - const arm_matrix_instance_f32* pSrcA, - const arm_matrix_instance_f32* pSrcB, - arm_matrix_instance_f32* pDst); - - -/** - * @brief Q15 matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ -arm_status arm_mat_sub_q15( - const arm_matrix_instance_q15* pSrcA, - const arm_matrix_instance_q15* pSrcB, - arm_matrix_instance_q15* pDst); - - -/** - * @brief Q31 matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ -arm_status arm_mat_sub_q31( - const arm_matrix_instance_q31* pSrcA, - const arm_matrix_instance_q31* pSrcB, - arm_matrix_instance_q31* pDst); - - -/** - * @brief Floating-point matrix scaling. - * @param[in] pSrc points to the input matrix - * @param[in] scale scale factor - * @param[out] pDst points to the output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ -arm_status arm_mat_scale_f32( - const arm_matrix_instance_f32* pSrc, - float32_t scale, - arm_matrix_instance_f32* pDst); - - -/** - * @brief Q15 matrix scaling. - * @param[in] pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ -arm_status arm_mat_scale_q15( - const arm_matrix_instance_q15* pSrc, - q15_t scaleFract, - int32_t shift, - arm_matrix_instance_q15* pDst); - - -/** - * @brief Q31 matrix scaling. - * @param[in] pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ -arm_status arm_mat_scale_q31( - const arm_matrix_instance_q31* pSrc, - q31_t scaleFract, - int32_t shift, - arm_matrix_instance_q31* pDst); - - -/** - * @brief Q31 matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ -void arm_mat_init_q31( - arm_matrix_instance_q31* S, - uint16_t nRows, - uint16_t nColumns, - q31_t* pData); - - -/** - * @brief Q15 matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ -void arm_mat_init_q15( - arm_matrix_instance_q15* S, - uint16_t nRows, - uint16_t nColumns, - q15_t* pData); - - -/** - * @brief Floating-point matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ -void arm_mat_init_f32( - arm_matrix_instance_f32* S, - uint16_t nRows, - uint16_t nColumns, - float32_t* pData); - - - -/** - * @brief Instance structure for the Q15 PID Control. - */ -typedef struct { - q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ -#if !defined (ARM_MATH_DSP) - q15_t A1; - q15_t A2; -#else - q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ -#endif - q15_t state[3]; /**< The state array of length 3. */ - q15_t Kp; /**< The proportional gain. */ - q15_t Ki; /**< The integral gain. */ - q15_t Kd; /**< The derivative gain. */ -} arm_pid_instance_q15; - -/** - * @brief Instance structure for the Q31 PID Control. - */ -typedef struct { - q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - q31_t A2; /**< The derived gain, A2 = Kd . */ - q31_t state[3]; /**< The state array of length 3. */ - q31_t Kp; /**< The proportional gain. */ - q31_t Ki; /**< The integral gain. */ - q31_t Kd; /**< The derivative gain. */ -} arm_pid_instance_q31; - -/** - * @brief Instance structure for the floating-point PID Control. - */ -typedef struct { - float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - float32_t A2; /**< The derived gain, A2 = Kd . */ - float32_t state[3]; /**< The state array of length 3. */ - float32_t Kp; /**< The proportional gain. */ - float32_t Ki; /**< The integral gain. */ - float32_t Kd; /**< The derivative gain. */ -} arm_pid_instance_f32; - - - -/** - * @brief Initialization function for the floating-point PID Control. - * @param[in,out] S points to an instance of the PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ -void arm_pid_init_f32( - arm_pid_instance_f32* S, - int32_t resetStateFlag); - - -/** - * @brief Reset function for the floating-point PID Control. - * @param[in,out] S is an instance of the floating-point PID Control structure - */ -void arm_pid_reset_f32( - arm_pid_instance_f32* S); - - -/** - * @brief Initialization function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ -void arm_pid_init_q31( - arm_pid_instance_q31* S, - int32_t resetStateFlag); - - -/** - * @brief Reset function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q31 PID Control structure - */ - -void arm_pid_reset_q31( - arm_pid_instance_q31* S); - - -/** - * @brief Initialization function for the Q15 PID Control. - * @param[in,out] S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ -void arm_pid_init_q15( - arm_pid_instance_q15* S, - int32_t resetStateFlag); - - -/** - * @brief Reset function for the Q15 PID Control. - * @param[in,out] S points to an instance of the q15 PID Control structure - */ -void arm_pid_reset_q15( - arm_pid_instance_q15* S); - - -/** - * @brief Instance structure for the floating-point Linear Interpolate function. - */ -typedef struct { - uint32_t nValues; /**< nValues */ - float32_t x1; /**< x1 */ - float32_t xSpacing; /**< xSpacing */ - float32_t* pYData; /**< pointer to the table of Y values */ -} arm_linear_interp_instance_f32; - -/** - * @brief Instance structure for the floating-point bilinear interpolation function. - */ -typedef struct { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - float32_t* pData; /**< points to the data table. */ -} arm_bilinear_interp_instance_f32; - -/** -* @brief Instance structure for the Q31 bilinear interpolation function. -*/ -typedef struct { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q31_t* pData; /**< points to the data table. */ -} arm_bilinear_interp_instance_q31; - -/** -* @brief Instance structure for the Q15 bilinear interpolation function. -*/ -typedef struct { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q15_t* pData; /**< points to the data table. */ -} arm_bilinear_interp_instance_q15; - -/** -* @brief Instance structure for the Q15 bilinear interpolation function. -*/ -typedef struct { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q7_t* pData; /**< points to the data table. */ -} arm_bilinear_interp_instance_q7; - - -/** - * @brief Q7 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ -void arm_mult_q7( - q7_t* pSrcA, - q7_t* pSrcB, - q7_t* pDst, - uint32_t blockSize); - - -/** - * @brief Q15 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ -void arm_mult_q15( - q15_t* pSrcA, - q15_t* pSrcB, - q15_t* pDst, - uint32_t blockSize); - - -/** - * @brief Q31 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ -void arm_mult_q31( - q31_t* pSrcA, - q31_t* pSrcB, - q31_t* pDst, - uint32_t blockSize); - - -/** - * @brief Floating-point vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ -void arm_mult_f32( - float32_t* pSrcA, - float32_t* pSrcB, - float32_t* pDst, - uint32_t blockSize); - - -/** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ -typedef struct { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t* pTwiddle; /**< points to the Sin twiddle factor table. */ - uint16_t* pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ -} arm_cfft_radix2_instance_q15; - -/* Deprecated */ -arm_status arm_cfft_radix2_init_q15( - arm_cfft_radix2_instance_q15* S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ -void arm_cfft_radix2_q15( - const arm_cfft_radix2_instance_q15* S, - q15_t* pSrc); - - -/** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ -typedef struct { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t* pTwiddle; /**< points to the twiddle factor table. */ - uint16_t* pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ -} arm_cfft_radix4_instance_q15; - -/* Deprecated */ -arm_status arm_cfft_radix4_init_q15( - arm_cfft_radix4_instance_q15* S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ -void arm_cfft_radix4_q15( - const arm_cfft_radix4_instance_q15* S, - q15_t* pSrc); - -/** - * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. - */ -typedef struct { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t* pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t* pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ -} arm_cfft_radix2_instance_q31; - -/* Deprecated */ -arm_status arm_cfft_radix2_init_q31( - arm_cfft_radix2_instance_q31* S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ -void arm_cfft_radix2_q31( - const arm_cfft_radix2_instance_q31* S, - q31_t* pSrc); - -/** - * @brief Instance structure for the Q31 CFFT/CIFFT function. - */ -typedef struct { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t* pTwiddle; /**< points to the twiddle factor table. */ - uint16_t* pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ -} arm_cfft_radix4_instance_q31; - -/* Deprecated */ -void arm_cfft_radix4_q31( - const arm_cfft_radix4_instance_q31* S, - q31_t* pSrc); - -/* Deprecated */ -arm_status arm_cfft_radix4_init_q31( - arm_cfft_radix4_instance_q31* S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ -typedef struct { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t* pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t* pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ -} arm_cfft_radix2_instance_f32; - -/* Deprecated */ -arm_status arm_cfft_radix2_init_f32( - arm_cfft_radix2_instance_f32* S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ -void arm_cfft_radix2_f32( - const arm_cfft_radix2_instance_f32* S, - float32_t* pSrc); - -/** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ -typedef struct { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t* pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t* pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ -} arm_cfft_radix4_instance_f32; - -/* Deprecated */ -arm_status arm_cfft_radix4_init_f32( - arm_cfft_radix4_instance_f32* S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ -void arm_cfft_radix4_f32( - const arm_cfft_radix4_instance_f32* S, - float32_t* pSrc); - -/** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ -typedef struct { - uint16_t fftLen; /**< length of the FFT. */ - const q15_t* pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t* pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ -} arm_cfft_instance_q15; - -void arm_cfft_q15( - const arm_cfft_instance_q15* S, - q15_t* p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ -typedef struct { - uint16_t fftLen; /**< length of the FFT. */ - const q31_t* pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t* pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ -} arm_cfft_instance_q31; - -void arm_cfft_q31( - const arm_cfft_instance_q31* S, - q31_t* p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ -typedef struct { - uint16_t fftLen; /**< length of the FFT. */ - const float32_t* pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t* pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ -} arm_cfft_instance_f32; - -void arm_cfft_f32( - const arm_cfft_instance_f32* S, - float32_t* p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/** - * @brief Instance structure for the Q15 RFFT/RIFFT function. - */ -typedef struct { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q15_t* pTwiddleAReal; /**< points to the real twiddle factor table. */ - q15_t* pTwiddleBReal; /**< points to the imag twiddle factor table. */ - const arm_cfft_instance_q15* pCfft; /**< points to the complex FFT instance. */ -} arm_rfft_instance_q15; - -arm_status arm_rfft_init_q15( - arm_rfft_instance_q15* S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - -void arm_rfft_q15( - const arm_rfft_instance_q15* S, - q15_t* pSrc, - q15_t* pDst); - -/** - * @brief Instance structure for the Q31 RFFT/RIFFT function. - */ -typedef struct { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q31_t* pTwiddleAReal; /**< points to the real twiddle factor table. */ - q31_t* pTwiddleBReal; /**< points to the imag twiddle factor table. */ - const arm_cfft_instance_q31* pCfft; /**< points to the complex FFT instance. */ -} arm_rfft_instance_q31; - -arm_status arm_rfft_init_q31( - arm_rfft_instance_q31* S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - -void arm_rfft_q31( - const arm_rfft_instance_q31* S, - q31_t* pSrc, - q31_t* pDst); - -/** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ -typedef struct { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint16_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - float32_t* pTwiddleAReal; /**< points to the real twiddle factor table. */ - float32_t* pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_f32* pCfft; /**< points to the complex FFT instance. */ -} arm_rfft_instance_f32; - -arm_status arm_rfft_init_f32( - arm_rfft_instance_f32* S, - arm_cfft_radix4_instance_f32* S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - -void arm_rfft_f32( - const arm_rfft_instance_f32* S, - float32_t* pSrc, - float32_t* pDst); - -/** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ -typedef struct { - arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ - uint16_t fftLenRFFT; /**< length of the real sequence */ - float32_t* pTwiddleRFFT; /**< Twiddle factors real stage */ -} arm_rfft_fast_instance_f32 ; - -arm_status arm_rfft_fast_init_f32 ( - arm_rfft_fast_instance_f32* S, - uint16_t fftLen); - -void arm_rfft_fast_f32( - arm_rfft_fast_instance_f32* S, - float32_t* p, float32_t* pOut, - uint8_t ifftFlag); - -/** - * @brief Instance structure for the floating-point DCT4/IDCT4 function. - */ -typedef struct { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - float32_t normalize; /**< normalizing factor. */ - float32_t* pTwiddle; /**< points to the twiddle factor table. */ - float32_t* pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_f32* pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_f32* pCfft; /**< points to the complex FFT instance. */ -} arm_dct4_instance_f32; - - -/** - * @brief Initialization function for the floating-point DCT4/IDCT4. - * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. - * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. - */ -arm_status arm_dct4_init_f32( - arm_dct4_instance_f32* S, - arm_rfft_instance_f32* S_RFFT, - arm_cfft_radix4_instance_f32* S_CFFT, - uint16_t N, - uint16_t Nby2, - float32_t normalize); - - -/** - * @brief Processing function for the floating-point DCT4/IDCT4. - * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ -void arm_dct4_f32( - const arm_dct4_instance_f32* S, - float32_t* pState, - float32_t* pInlineBuffer); - - -/** - * @brief Instance structure for the Q31 DCT4/IDCT4 function. - */ -typedef struct { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q31_t normalize; /**< normalizing factor. */ - q31_t* pTwiddle; /**< points to the twiddle factor table. */ - q31_t* pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q31* pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q31* pCfft; /**< points to the complex FFT instance. */ -} arm_dct4_instance_q31; - - -/** - * @brief Initialization function for the Q31 DCT4/IDCT4. - * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure - * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ -arm_status arm_dct4_init_q31( - arm_dct4_instance_q31* S, - arm_rfft_instance_q31* S_RFFT, - arm_cfft_radix4_instance_q31* S_CFFT, - uint16_t N, - uint16_t Nby2, - q31_t normalize); - - -/** - * @brief Processing function for the Q31 DCT4/IDCT4. - * @param[in] S points to an instance of the Q31 DCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ -void arm_dct4_q31( - const arm_dct4_instance_q31* S, - q31_t* pState, - q31_t* pInlineBuffer); - - -/** - * @brief Instance structure for the Q15 DCT4/IDCT4 function. - */ -typedef struct { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q15_t normalize; /**< normalizing factor. */ - q15_t* pTwiddle; /**< points to the twiddle factor table. */ - q15_t* pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q15* pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q15* pCfft; /**< points to the complex FFT instance. */ -} arm_dct4_instance_q15; - - -/** - * @brief Initialization function for the Q15 DCT4/IDCT4. - * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. - * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ -arm_status arm_dct4_init_q15( - arm_dct4_instance_q15* S, - arm_rfft_instance_q15* S_RFFT, - arm_cfft_radix4_instance_q15* S_CFFT, - uint16_t N, - uint16_t Nby2, - q15_t normalize); - - -/** - * @brief Processing function for the Q15 DCT4/IDCT4. - * @param[in] S points to an instance of the Q15 DCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ -void arm_dct4_q15( - const arm_dct4_instance_q15* S, - q15_t* pState, - q15_t* pInlineBuffer); - - -/** - * @brief Floating-point vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ -void arm_add_f32( - float32_t* pSrcA, - float32_t* pSrcB, - float32_t* pDst, - uint32_t blockSize); - - -/** - * @brief Q7 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ -void arm_add_q7( - q7_t* pSrcA, - q7_t* pSrcB, - q7_t* pDst, - uint32_t blockSize); - - -/** - * @brief Q15 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ -void arm_add_q15( - q15_t* pSrcA, - q15_t* pSrcB, - q15_t* pDst, - uint32_t blockSize); - - -/** - * @brief Q31 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ -void arm_add_q31( - q31_t* pSrcA, - q31_t* pSrcB, - q31_t* pDst, - uint32_t blockSize); - - -/** - * @brief Floating-point vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ -void arm_sub_f32( - float32_t* pSrcA, - float32_t* pSrcB, - float32_t* pDst, - uint32_t blockSize); - - -/** - * @brief Q7 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ -void arm_sub_q7( - q7_t* pSrcA, - q7_t* pSrcB, - q7_t* pDst, - uint32_t blockSize); - - -/** - * @brief Q15 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ -void arm_sub_q15( - q15_t* pSrcA, - q15_t* pSrcB, - q15_t* pDst, - uint32_t blockSize); - - -/** - * @brief Q31 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ -void arm_sub_q31( - q31_t* pSrcA, - q31_t* pSrcB, - q31_t* pDst, - uint32_t blockSize); - - -/** - * @brief Multiplies a floating-point vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scale scale factor to be applied - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ -void arm_scale_f32( - float32_t* pSrc, - float32_t scale, - float32_t* pDst, - uint32_t blockSize); - - -/** - * @brief Multiplies a Q7 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ -void arm_scale_q7( - q7_t* pSrc, - q7_t scaleFract, - int8_t shift, - q7_t* pDst, - uint32_t blockSize); - - -/** - * @brief Multiplies a Q15 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ -void arm_scale_q15( - q15_t* pSrc, - q15_t scaleFract, - int8_t shift, - q15_t* pDst, - uint32_t blockSize); - - -/** - * @brief Multiplies a Q31 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ -void arm_scale_q31( - q31_t* pSrc, - q31_t scaleFract, - int8_t shift, - q31_t* pDst, - uint32_t blockSize); - - -/** - * @brief Q7 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ -void arm_abs_q7( - q7_t* pSrc, - q7_t* pDst, - uint32_t blockSize); - - -/** - * @brief Floating-point vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ -void arm_abs_f32( - float32_t* pSrc, - float32_t* pDst, - uint32_t blockSize); - - -/** - * @brief Q15 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ -void arm_abs_q15( - q15_t* pSrc, - q15_t* pDst, - uint32_t blockSize); - - -/** - * @brief Q31 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ -void arm_abs_q31( - q31_t* pSrc, - q31_t* pDst, - uint32_t blockSize); - - -/** - * @brief Dot product of floating-point vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ -void arm_dot_prod_f32( - float32_t* pSrcA, - float32_t* pSrcB, - uint32_t blockSize, - float32_t* result); - - -/** - * @brief Dot product of Q7 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ -void arm_dot_prod_q7( - q7_t* pSrcA, - q7_t* pSrcB, - uint32_t blockSize, - q31_t* result); - - -/** - * @brief Dot product of Q15 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ -void arm_dot_prod_q15( - q15_t* pSrcA, - q15_t* pSrcB, - uint32_t blockSize, - q63_t* result); - - -/** - * @brief Dot product of Q31 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ -void arm_dot_prod_q31( - q31_t* pSrcA, - q31_t* pSrcB, - uint32_t blockSize, - q63_t* result); - - -/** - * @brief Shifts the elements of a Q7 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ -void arm_shift_q7( - q7_t* pSrc, - int8_t shiftBits, - q7_t* pDst, - uint32_t blockSize); - - -/** - * @brief Shifts the elements of a Q15 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ -void arm_shift_q15( - q15_t* pSrc, - int8_t shiftBits, - q15_t* pDst, - uint32_t blockSize); - - -/** - * @brief Shifts the elements of a Q31 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ -void arm_shift_q31( - q31_t* pSrc, - int8_t shiftBits, - q31_t* pDst, - uint32_t blockSize); - - -/** - * @brief Adds a constant offset to a floating-point vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ -void arm_offset_f32( - float32_t* pSrc, - float32_t offset, - float32_t* pDst, - uint32_t blockSize); - - -/** - * @brief Adds a constant offset to a Q7 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ -void arm_offset_q7( - q7_t* pSrc, - q7_t offset, - q7_t* pDst, - uint32_t blockSize); - - -/** - * @brief Adds a constant offset to a Q15 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ -void arm_offset_q15( - q15_t* pSrc, - q15_t offset, - q15_t* pDst, - uint32_t blockSize); - - -/** - * @brief Adds a constant offset to a Q31 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ -void arm_offset_q31( - q31_t* pSrc, - q31_t offset, - q31_t* pDst, - uint32_t blockSize); - - -/** - * @brief Negates the elements of a floating-point vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ -void arm_negate_f32( - float32_t* pSrc, - float32_t* pDst, - uint32_t blockSize); - - -/** - * @brief Negates the elements of a Q7 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ -void arm_negate_q7( - q7_t* pSrc, - q7_t* pDst, - uint32_t blockSize); - - -/** - * @brief Negates the elements of a Q15 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ -void arm_negate_q15( - q15_t* pSrc, - q15_t* pDst, - uint32_t blockSize); - - -/** - * @brief Negates the elements of a Q31 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ -void arm_negate_q31( - q31_t* pSrc, - q31_t* pDst, - uint32_t blockSize); - - -/** - * @brief Copies the elements of a floating-point vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ -void arm_copy_f32( - float32_t* pSrc, - float32_t* pDst, - uint32_t blockSize); - - -/** - * @brief Copies the elements of a Q7 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ -void arm_copy_q7( - q7_t* pSrc, - q7_t* pDst, - uint32_t blockSize); - - -/** - * @brief Copies the elements of a Q15 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ -void arm_copy_q15( - q15_t* pSrc, - q15_t* pDst, - uint32_t blockSize); - - -/** - * @brief Copies the elements of a Q31 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ -void arm_copy_q31( - q31_t* pSrc, - q31_t* pDst, - uint32_t blockSize); - - -/** - * @brief Fills a constant value into a floating-point vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ -void arm_fill_f32( - float32_t value, - float32_t* pDst, - uint32_t blockSize); - - -/** - * @brief Fills a constant value into a Q7 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ -void arm_fill_q7( - q7_t value, - q7_t* pDst, - uint32_t blockSize); - - -/** - * @brief Fills a constant value into a Q15 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ -void arm_fill_q15( - q15_t value, - q15_t* pDst, - uint32_t blockSize); - - -/** - * @brief Fills a constant value into a Q31 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ -void arm_fill_q31( - q31_t value, - q31_t* pDst, - uint32_t blockSize); - - -/** - * @brief Convolution of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - */ -void arm_conv_f32( - float32_t* pSrcA, - uint32_t srcALen, - float32_t* pSrcB, - uint32_t srcBLen, - float32_t* pDst); - - -/** - * @brief Convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - */ -void arm_conv_opt_q15( - q15_t* pSrcA, - uint32_t srcALen, - q15_t* pSrcB, - uint32_t srcBLen, - q15_t* pDst, - q15_t* pScratch1, - q15_t* pScratch2); - - -/** - * @brief Convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - */ -void arm_conv_q15( - q15_t* pSrcA, - uint32_t srcALen, - q15_t* pSrcB, - uint32_t srcBLen, - q15_t* pDst); - - -/** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ -void arm_conv_fast_q15( - q15_t* pSrcA, - uint32_t srcALen, - q15_t* pSrcB, - uint32_t srcBLen, - q15_t* pDst); - - -/** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - */ -void arm_conv_fast_opt_q15( - q15_t* pSrcA, - uint32_t srcALen, - q15_t* pSrcB, - uint32_t srcBLen, - q15_t* pDst, - q15_t* pScratch1, - q15_t* pScratch2); - - -/** - * @brief Convolution of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ -void arm_conv_q31( - q31_t* pSrcA, - uint32_t srcALen, - q31_t* pSrcB, - uint32_t srcBLen, - q31_t* pDst); - - -/** - * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ -void arm_conv_fast_q31( - q31_t* pSrcA, - uint32_t srcALen, - q31_t* pSrcB, - uint32_t srcBLen, - q31_t* pDst); - - -/** -* @brief Convolution of Q7 sequences. -* @param[in] pSrcA points to the first input sequence. -* @param[in] srcALen length of the first input sequence. -* @param[in] pSrcB points to the second input sequence. -* @param[in] srcBLen length of the second input sequence. -* @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. -* @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. -* @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). -*/ -void arm_conv_opt_q7( - q7_t* pSrcA, - uint32_t srcALen, - q7_t* pSrcB, - uint32_t srcBLen, - q7_t* pDst, - q15_t* pScratch1, - q15_t* pScratch2); - - -/** - * @brief Convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ -void arm_conv_q7( - q7_t* pSrcA, - uint32_t srcALen, - q7_t* pSrcB, - uint32_t srcBLen, - q7_t* pDst); - - -/** - * @brief Partial convolution of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ -arm_status arm_conv_partial_f32( - float32_t* pSrcA, - uint32_t srcALen, - float32_t* pSrcB, - uint32_t srcBLen, - float32_t* pDst, - uint32_t firstIndex, - uint32_t numPoints); - - -/** - * @brief Partial convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ -arm_status arm_conv_partial_opt_q15( - q15_t* pSrcA, - uint32_t srcALen, - q15_t* pSrcB, - uint32_t srcBLen, - q15_t* pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t* pScratch1, - q15_t* pScratch2); - - -/** - * @brief Partial convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ -arm_status arm_conv_partial_q15( - q15_t* pSrcA, - uint32_t srcALen, - q15_t* pSrcB, - uint32_t srcBLen, - q15_t* pDst, - uint32_t firstIndex, - uint32_t numPoints); - - -/** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ -arm_status arm_conv_partial_fast_q15( - q15_t* pSrcA, - uint32_t srcALen, - q15_t* pSrcB, - uint32_t srcBLen, - q15_t* pDst, - uint32_t firstIndex, - uint32_t numPoints); - - -/** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ -arm_status arm_conv_partial_fast_opt_q15( - q15_t* pSrcA, - uint32_t srcALen, - q15_t* pSrcB, - uint32_t srcBLen, - q15_t* pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t* pScratch1, - q15_t* pScratch2); - - -/** - * @brief Partial convolution of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ -arm_status arm_conv_partial_q31( - q31_t* pSrcA, - uint32_t srcALen, - q31_t* pSrcB, - uint32_t srcBLen, - q31_t* pDst, - uint32_t firstIndex, - uint32_t numPoints); - - -/** - * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ -arm_status arm_conv_partial_fast_q31( - q31_t* pSrcA, - uint32_t srcALen, - q31_t* pSrcB, - uint32_t srcBLen, - q31_t* pDst, - uint32_t firstIndex, - uint32_t numPoints); - - -/** - * @brief Partial convolution of Q7 sequences - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ -arm_status arm_conv_partial_opt_q7( - q7_t* pSrcA, - uint32_t srcALen, - q7_t* pSrcB, - uint32_t srcBLen, - q7_t* pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t* pScratch1, - q15_t* pScratch2); - - -/** - * @brief Partial convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ -arm_status arm_conv_partial_q7( - q7_t* pSrcA, - uint32_t srcALen, - q7_t* pSrcB, - uint32_t srcBLen, - q7_t* pDst, - uint32_t firstIndex, - uint32_t numPoints); - - -/** - * @brief Instance structure for the Q15 FIR decimator. - */ -typedef struct { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q15_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ -} arm_fir_decimate_instance_q15; - -/** - * @brief Instance structure for the Q31 FIR decimator. - */ -typedef struct { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q31_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ -} arm_fir_decimate_instance_q31; - -/** - * @brief Instance structure for the floating-point FIR decimator. - */ -typedef struct { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - float32_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ -} arm_fir_decimate_instance_f32; - - -/** - * @brief Processing function for the floating-point FIR decimator. - * @param[in] S points to an instance of the floating-point FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ -void arm_fir_decimate_f32( - const arm_fir_decimate_instance_f32* S, - float32_t* pSrc, - float32_t* pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the floating-point FIR decimator. - * @param[in,out] S points to an instance of the floating-point FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ -arm_status arm_fir_decimate_init_f32( - arm_fir_decimate_instance_f32* S, - uint16_t numTaps, - uint8_t M, - float32_t* pCoeffs, - float32_t* pState, - uint32_t blockSize); - - -/** - * @brief Processing function for the Q15 FIR decimator. - * @param[in] S points to an instance of the Q15 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ -void arm_fir_decimate_q15( - const arm_fir_decimate_instance_q15* S, - q15_t* pSrc, - q15_t* pDst, - uint32_t blockSize); - - -/** - * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ -void arm_fir_decimate_fast_q15( - const arm_fir_decimate_instance_q15* S, - q15_t* pSrc, - q15_t* pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 FIR decimator. - * @param[in,out] S points to an instance of the Q15 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ -arm_status arm_fir_decimate_init_q15( - arm_fir_decimate_instance_q15* S, - uint16_t numTaps, - uint8_t M, - q15_t* pCoeffs, - q15_t* pState, - uint32_t blockSize); - - -/** - * @brief Processing function for the Q31 FIR decimator. - * @param[in] S points to an instance of the Q31 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ -void arm_fir_decimate_q31( - const arm_fir_decimate_instance_q31* S, - q31_t* pSrc, - q31_t* pDst, - uint32_t blockSize); - -/** - * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ -void arm_fir_decimate_fast_q31( - arm_fir_decimate_instance_q31* S, - q31_t* pSrc, - q31_t* pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q31 FIR decimator. - * @param[in,out] S points to an instance of the Q31 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ -arm_status arm_fir_decimate_init_q31( - arm_fir_decimate_instance_q31* S, - uint16_t numTaps, - uint8_t M, - q31_t* pCoeffs, - q31_t* pState, - uint32_t blockSize); - - -/** - * @brief Instance structure for the Q15 FIR interpolator. - */ -typedef struct { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q15_t* pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q15_t* pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ -} arm_fir_interpolate_instance_q15; - -/** - * @brief Instance structure for the Q31 FIR interpolator. - */ -typedef struct { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q31_t* pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q31_t* pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ -} arm_fir_interpolate_instance_q31; - -/** - * @brief Instance structure for the floating-point FIR interpolator. - */ -typedef struct { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - float32_t* pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - float32_t* pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ -} arm_fir_interpolate_instance_f32; - - -/** - * @brief Processing function for the Q15 FIR interpolator. - * @param[in] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ -void arm_fir_interpolate_q15( - const arm_fir_interpolate_instance_q15* S, - q15_t* pSrc, - q15_t* pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 FIR interpolator. - * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ -arm_status arm_fir_interpolate_init_q15( - arm_fir_interpolate_instance_q15* S, - uint8_t L, - uint16_t numTaps, - q15_t* pCoeffs, - q15_t* pState, - uint32_t blockSize); - - -/** - * @brief Processing function for the Q31 FIR interpolator. - * @param[in] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ -void arm_fir_interpolate_q31( - const arm_fir_interpolate_instance_q31* S, - q31_t* pSrc, - q31_t* pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q31 FIR interpolator. - * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ -arm_status arm_fir_interpolate_init_q31( - arm_fir_interpolate_instance_q31* S, - uint8_t L, - uint16_t numTaps, - q31_t* pCoeffs, - q31_t* pState, - uint32_t blockSize); - - -/** - * @brief Processing function for the floating-point FIR interpolator. - * @param[in] S points to an instance of the floating-point FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ -void arm_fir_interpolate_f32( - const arm_fir_interpolate_instance_f32* S, - float32_t* pSrc, - float32_t* pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the floating-point FIR interpolator. - * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ -arm_status arm_fir_interpolate_init_f32( - arm_fir_interpolate_instance_f32* S, - uint8_t L, - uint16_t numTaps, - float32_t* pCoeffs, - float32_t* pState, - uint32_t blockSize); - - -/** - * @brief Instance structure for the high precision Q31 Biquad cascade filter. - */ -typedef struct { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q63_t* pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t* pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ -} arm_biquad_cas_df1_32x64_ins_q31; - - -/** - * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ -void arm_biquad_cas_df1_32x64_q31( - const arm_biquad_cas_df1_32x64_ins_q31* S, - q31_t* pSrc, - q31_t* pDst, - uint32_t blockSize); - - -/** - * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format - */ -void arm_biquad_cas_df1_32x64_init_q31( - arm_biquad_cas_df1_32x64_ins_q31* S, - uint8_t numStages, - q31_t* pCoeffs, - q63_t* pState, - uint8_t postShift); - - -/** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ -typedef struct { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t* pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float32_t* pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ -} arm_biquad_cascade_df2T_instance_f32; - -/** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ -typedef struct { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t* pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t* pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ -} arm_biquad_cascade_stereo_df2T_instance_f32; - -/** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ -typedef struct { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float64_t* pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float64_t* pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ -} arm_biquad_cascade_df2T_instance_f64; - - -/** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ -void arm_biquad_cascade_df2T_f32( - const arm_biquad_cascade_df2T_instance_f32* S, - float32_t* pSrc, - float32_t* pDst, - uint32_t blockSize); - - -/** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ -void arm_biquad_cascade_stereo_df2T_f32( - const arm_biquad_cascade_stereo_df2T_instance_f32* S, - float32_t* pSrc, - float32_t* pDst, - uint32_t blockSize); - - -/** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ -void arm_biquad_cascade_df2T_f64( - const arm_biquad_cascade_df2T_instance_f64* S, - float64_t* pSrc, - float64_t* pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ -void arm_biquad_cascade_df2T_init_f32( - arm_biquad_cascade_df2T_instance_f32* S, - uint8_t numStages, - float32_t* pCoeffs, - float32_t* pState); - - -/** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ -void arm_biquad_cascade_stereo_df2T_init_f32( - arm_biquad_cascade_stereo_df2T_instance_f32* S, - uint8_t numStages, - float32_t* pCoeffs, - float32_t* pState); - - -/** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ -void arm_biquad_cascade_df2T_init_f64( - arm_biquad_cascade_df2T_instance_f64* S, - uint8_t numStages, - float64_t* pCoeffs, - float64_t* pState); - - -/** - * @brief Instance structure for the Q15 FIR lattice filter. - */ -typedef struct { - uint16_t numStages; /**< number of filter stages. */ - q15_t* pState; /**< points to the state variable array. The array is of length numStages. */ - q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ -} arm_fir_lattice_instance_q15; - -/** - * @brief Instance structure for the Q31 FIR lattice filter. - */ -typedef struct { - uint16_t numStages; /**< number of filter stages. */ - q31_t* pState; /**< points to the state variable array. The array is of length numStages. */ - q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ -} arm_fir_lattice_instance_q31; - -/** - * @brief Instance structure for the floating-point FIR lattice filter. - */ -typedef struct { - uint16_t numStages; /**< number of filter stages. */ - float32_t* pState; /**< points to the state variable array. The array is of length numStages. */ - float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ -} arm_fir_lattice_instance_f32; - - -/** - * @brief Initialization function for the Q15 FIR lattice filter. - * @param[in] S points to an instance of the Q15 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ -void arm_fir_lattice_init_q15( - arm_fir_lattice_instance_q15* S, - uint16_t numStages, - q15_t* pCoeffs, - q15_t* pState); - - -/** - * @brief Processing function for the Q15 FIR lattice filter. - * @param[in] S points to an instance of the Q15 FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ -void arm_fir_lattice_q15( - const arm_fir_lattice_instance_q15* S, - q15_t* pSrc, - q15_t* pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q31 FIR lattice filter. - * @param[in] S points to an instance of the Q31 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ -void arm_fir_lattice_init_q31( - arm_fir_lattice_instance_q31* S, - uint16_t numStages, - q31_t* pCoeffs, - q31_t* pState); - - -/** - * @brief Processing function for the Q31 FIR lattice filter. - * @param[in] S points to an instance of the Q31 FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ -void arm_fir_lattice_q31( - const arm_fir_lattice_instance_q31* S, - q31_t* pSrc, - q31_t* pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the floating-point FIR lattice filter. - * @param[in] S points to an instance of the floating-point FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ -void arm_fir_lattice_init_f32( - arm_fir_lattice_instance_f32* S, - uint16_t numStages, - float32_t* pCoeffs, - float32_t* pState); - - -/** - * @brief Processing function for the floating-point FIR lattice filter. - * @param[in] S points to an instance of the floating-point FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ -void arm_fir_lattice_f32( - const arm_fir_lattice_instance_f32* S, - float32_t* pSrc, - float32_t* pDst, - uint32_t blockSize); - - -/** - * @brief Instance structure for the Q15 IIR lattice filter. - */ -typedef struct { - uint16_t numStages; /**< number of stages in the filter. */ - q15_t* pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q15_t* pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q15_t* pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ -} arm_iir_lattice_instance_q15; - -/** - * @brief Instance structure for the Q31 IIR lattice filter. - */ -typedef struct { - uint16_t numStages; /**< number of stages in the filter. */ - q31_t* pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q31_t* pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q31_t* pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ -} arm_iir_lattice_instance_q31; - -/** - * @brief Instance structure for the floating-point IIR lattice filter. - */ -typedef struct { - uint16_t numStages; /**< number of stages in the filter. */ - float32_t* pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - float32_t* pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - float32_t* pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ -} arm_iir_lattice_instance_f32; - - -/** - * @brief Processing function for the floating-point IIR lattice filter. - * @param[in] S points to an instance of the floating-point IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ -void arm_iir_lattice_f32( - const arm_iir_lattice_instance_f32* S, - float32_t* pSrc, - float32_t* pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the floating-point IIR lattice filter. - * @param[in] S points to an instance of the floating-point IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. - * @param[in] blockSize number of samples to process. - */ -void arm_iir_lattice_init_f32( - arm_iir_lattice_instance_f32* S, - uint16_t numStages, - float32_t* pkCoeffs, - float32_t* pvCoeffs, - float32_t* pState, - uint32_t blockSize); - - -/** - * @brief Processing function for the Q31 IIR lattice filter. - * @param[in] S points to an instance of the Q31 IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ -void arm_iir_lattice_q31( - const arm_iir_lattice_instance_q31* S, - q31_t* pSrc, - q31_t* pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q31 IIR lattice filter. - * @param[in] S points to an instance of the Q31 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process. - */ -void arm_iir_lattice_init_q31( - arm_iir_lattice_instance_q31* S, - uint16_t numStages, - q31_t* pkCoeffs, - q31_t* pvCoeffs, - q31_t* pState, - uint32_t blockSize); - - -/** - * @brief Processing function for the Q15 IIR lattice filter. - * @param[in] S points to an instance of the Q15 IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ -void arm_iir_lattice_q15( - const arm_iir_lattice_instance_q15* S, - q15_t* pSrc, - q15_t* pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 IIR lattice filter. - * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process per call. - */ -void arm_iir_lattice_init_q15( - arm_iir_lattice_instance_q15* S, - uint16_t numStages, - q15_t* pkCoeffs, - q15_t* pvCoeffs, - q15_t* pState, - uint32_t blockSize); - - -/** - * @brief Instance structure for the floating-point LMS filter. - */ -typedef struct { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that controls filter coefficient updates. */ -} arm_lms_instance_f32; - - -/** - * @brief Processing function for floating-point LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ -void arm_lms_f32( - const arm_lms_instance_f32* S, - float32_t* pSrc, - float32_t* pRef, - float32_t* pOut, - float32_t* pErr, - uint32_t blockSize); - - -/** - * @brief Initialization function for floating-point LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to the coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - */ -void arm_lms_init_f32( - arm_lms_instance_f32* S, - uint16_t numTaps, - float32_t* pCoeffs, - float32_t* pState, - float32_t mu, - uint32_t blockSize); - - -/** - * @brief Instance structure for the Q15 LMS filter. - */ -typedef struct { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ -} arm_lms_instance_q15; - - -/** - * @brief Initialization function for the Q15 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to the coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ -void arm_lms_init_q15( - arm_lms_instance_q15* S, - uint16_t numTaps, - q15_t* pCoeffs, - q15_t* pState, - q15_t mu, - uint32_t blockSize, - uint32_t postShift); - - -/** - * @brief Processing function for Q15 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ -void arm_lms_q15( - const arm_lms_instance_q15* S, - q15_t* pSrc, - q15_t* pRef, - q15_t* pOut, - q15_t* pErr, - uint32_t blockSize); - - -/** - * @brief Instance structure for the Q31 LMS filter. - */ -typedef struct { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ -} arm_lms_instance_q31; - - -/** - * @brief Processing function for Q31 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ -void arm_lms_q31( - const arm_lms_instance_q31* S, - q31_t* pSrc, - q31_t* pRef, - q31_t* pOut, - q31_t* pErr, - uint32_t blockSize); - - -/** - * @brief Initialization function for Q31 LMS filter. - * @param[in] S points to an instance of the Q31 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ -void arm_lms_init_q31( - arm_lms_instance_q31* S, - uint16_t numTaps, - q31_t* pCoeffs, - q31_t* pState, - q31_t mu, - uint32_t blockSize, - uint32_t postShift); - - -/** - * @brief Instance structure for the floating-point normalized LMS filter. - */ -typedef struct { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that control filter coefficient updates. */ - float32_t energy; /**< saves previous frame energy. */ - float32_t x0; /**< saves previous input sample. */ -} arm_lms_norm_instance_f32; - - -/** - * @brief Processing function for floating-point normalized LMS filter. - * @param[in] S points to an instance of the floating-point normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ -void arm_lms_norm_f32( - arm_lms_norm_instance_f32* S, - float32_t* pSrc, - float32_t* pRef, - float32_t* pOut, - float32_t* pErr, - uint32_t blockSize); - - -/** - * @brief Initialization function for floating-point normalized LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - */ -void arm_lms_norm_init_f32( - arm_lms_norm_instance_f32* S, - uint16_t numTaps, - float32_t* pCoeffs, - float32_t* pState, - float32_t mu, - uint32_t blockSize); - - -/** - * @brief Instance structure for the Q31 normalized LMS filter. - */ -typedef struct { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q31_t* recipTable; /**< points to the reciprocal initial value table. */ - q31_t energy; /**< saves previous frame energy. */ - q31_t x0; /**< saves previous input sample. */ -} arm_lms_norm_instance_q31; - - -/** - * @brief Processing function for Q31 normalized LMS filter. - * @param[in] S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ -void arm_lms_norm_q31( - arm_lms_norm_instance_q31* S, - q31_t* pSrc, - q31_t* pRef, - q31_t* pOut, - q31_t* pErr, - uint32_t blockSize); - - -/** - * @brief Initialization function for Q31 normalized LMS filter. - * @param[in] S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ -void arm_lms_norm_init_q31( - arm_lms_norm_instance_q31* S, - uint16_t numTaps, - q31_t* pCoeffs, - q31_t* pState, - q31_t mu, - uint32_t blockSize, - uint8_t postShift); - - -/** - * @brief Instance structure for the Q15 normalized LMS filter. - */ -typedef struct { - uint16_t numTaps; /**< Number of coefficients in the filter. */ - q15_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q15_t* recipTable; /**< Points to the reciprocal initial value table. */ - q15_t energy; /**< saves previous frame energy. */ - q15_t x0; /**< saves previous input sample. */ -} arm_lms_norm_instance_q15; - - -/** - * @brief Processing function for Q15 normalized LMS filter. - * @param[in] S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ -void arm_lms_norm_q15( - arm_lms_norm_instance_q15* S, - q15_t* pSrc, - q15_t* pRef, - q15_t* pOut, - q15_t* pErr, - uint32_t blockSize); - - -/** - * @brief Initialization function for Q15 normalized LMS filter. - * @param[in] S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ -void arm_lms_norm_init_q15( - arm_lms_norm_instance_q15* S, - uint16_t numTaps, - q15_t* pCoeffs, - q15_t* pState, - q15_t mu, - uint32_t blockSize, - uint8_t postShift); - - -/** - * @brief Correlation of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ -void arm_correlate_f32( - float32_t* pSrcA, - uint32_t srcALen, - float32_t* pSrcB, - uint32_t srcBLen, - float32_t* pDst); - - -/** -* @brief Correlation of Q15 sequences -* @param[in] pSrcA points to the first input sequence. -* @param[in] srcALen length of the first input sequence. -* @param[in] pSrcB points to the second input sequence. -* @param[in] srcBLen length of the second input sequence. -* @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. -* @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. -*/ -void arm_correlate_opt_q15( - q15_t* pSrcA, - uint32_t srcALen, - q15_t* pSrcB, - uint32_t srcBLen, - q15_t* pDst, - q15_t* pScratch); - - -/** - * @brief Correlation of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - -void arm_correlate_q15( - q15_t* pSrcA, - uint32_t srcALen, - q15_t* pSrcB, - uint32_t srcBLen, - q15_t* pDst); - - -/** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - -void arm_correlate_fast_q15( - q15_t* pSrcA, - uint32_t srcALen, - q15_t* pSrcB, - uint32_t srcBLen, - q15_t* pDst); - - -/** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - */ -void arm_correlate_fast_opt_q15( - q15_t* pSrcA, - uint32_t srcALen, - q15_t* pSrcB, - uint32_t srcBLen, - q15_t* pDst, - q15_t* pScratch); - - -/** - * @brief Correlation of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ -void arm_correlate_q31( - q31_t* pSrcA, - uint32_t srcALen, - q31_t* pSrcB, - uint32_t srcBLen, - q31_t* pDst); - - -/** - * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ -void arm_correlate_fast_q31( - q31_t* pSrcA, - uint32_t srcALen, - q31_t* pSrcB, - uint32_t srcBLen, - q31_t* pDst); - - -/** - * @brief Correlation of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - */ -void arm_correlate_opt_q7( - q7_t* pSrcA, - uint32_t srcALen, - q7_t* pSrcB, - uint32_t srcBLen, - q7_t* pDst, - q15_t* pScratch1, - q15_t* pScratch2); - - -/** - * @brief Correlation of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ -void arm_correlate_q7( - q7_t* pSrcA, - uint32_t srcALen, - q7_t* pSrcB, - uint32_t srcBLen, - q7_t* pDst); - - -/** - * @brief Instance structure for the floating-point sparse FIR filter. - */ -typedef struct { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - float32_t* pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t* pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ -} arm_fir_sparse_instance_f32; - -/** - * @brief Instance structure for the Q31 sparse FIR filter. - */ -typedef struct { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q31_t* pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t* pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ -} arm_fir_sparse_instance_q31; - -/** - * @brief Instance structure for the Q15 sparse FIR filter. - */ -typedef struct { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q15_t* pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t* pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ -} arm_fir_sparse_instance_q15; - -/** - * @brief Instance structure for the Q7 sparse FIR filter. - */ -typedef struct { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q7_t* pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q7_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t* pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ -} arm_fir_sparse_instance_q7; - - -/** - * @brief Processing function for the floating-point sparse FIR filter. - * @param[in] S points to an instance of the floating-point sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ -void arm_fir_sparse_f32( - arm_fir_sparse_instance_f32* S, - float32_t* pSrc, - float32_t* pDst, - float32_t* pScratchIn, - uint32_t blockSize); - - -/** - * @brief Initialization function for the floating-point sparse FIR filter. - * @param[in,out] S points to an instance of the floating-point sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ -void arm_fir_sparse_init_f32( - arm_fir_sparse_instance_f32* S, - uint16_t numTaps, - float32_t* pCoeffs, - float32_t* pState, - int32_t* pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - -/** - * @brief Processing function for the Q31 sparse FIR filter. - * @param[in] S points to an instance of the Q31 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ -void arm_fir_sparse_q31( - arm_fir_sparse_instance_q31* S, - q31_t* pSrc, - q31_t* pDst, - q31_t* pScratchIn, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q31 sparse FIR filter. - * @param[in,out] S points to an instance of the Q31 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ -void arm_fir_sparse_init_q31( - arm_fir_sparse_instance_q31* S, - uint16_t numTaps, - q31_t* pCoeffs, - q31_t* pState, - int32_t* pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - -/** - * @brief Processing function for the Q15 sparse FIR filter. - * @param[in] S points to an instance of the Q15 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ -void arm_fir_sparse_q15( - arm_fir_sparse_instance_q15* S, - q15_t* pSrc, - q15_t* pDst, - q15_t* pScratchIn, - q31_t* pScratchOut, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 sparse FIR filter. - * @param[in,out] S points to an instance of the Q15 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ -void arm_fir_sparse_init_q15( - arm_fir_sparse_instance_q15* S, - uint16_t numTaps, - q15_t* pCoeffs, - q15_t* pState, - int32_t* pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - -/** - * @brief Processing function for the Q7 sparse FIR filter. - * @param[in] S points to an instance of the Q7 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ -void arm_fir_sparse_q7( - arm_fir_sparse_instance_q7* S, - q7_t* pSrc, - q7_t* pDst, - q7_t* pScratchIn, - q31_t* pScratchOut, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q7 sparse FIR filter. - * @param[in,out] S points to an instance of the Q7 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ -void arm_fir_sparse_init_q7( - arm_fir_sparse_instance_q7* S, - uint16_t numTaps, - q7_t* pCoeffs, - q7_t* pState, - int32_t* pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - -/** - * @brief Floating-point sin_cos function. - * @param[in] theta input value in degrees - * @param[out] pSinVal points to the processed sine output. - * @param[out] pCosVal points to the processed cos output. - */ -void arm_sin_cos_f32( - float32_t theta, - float32_t* pSinVal, - float32_t* pCosVal); - - -/** - * @brief Q31 sin_cos function. - * @param[in] theta scaled input value in degrees - * @param[out] pSinVal points to the processed sine output. - * @param[out] pCosVal points to the processed cosine output. - */ -void arm_sin_cos_q31( - q31_t theta, - q31_t* pSinVal, - q31_t* pCosVal); - - -/** - * @brief Floating-point complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ -void arm_cmplx_conj_f32( - float32_t* pSrc, - float32_t* pDst, - uint32_t numSamples); - -/** - * @brief Q31 complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ -void arm_cmplx_conj_q31( - q31_t* pSrc, - q31_t* pDst, - uint32_t numSamples); - - -/** - * @brief Q15 complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ -void arm_cmplx_conj_q15( - q15_t* pSrc, - q15_t* pDst, - uint32_t numSamples); - - -/** - * @brief Floating-point complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ -void arm_cmplx_mag_squared_f32( - float32_t* pSrc, - float32_t* pDst, - uint32_t numSamples); - - -/** - * @brief Q31 complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ -void arm_cmplx_mag_squared_q31( - q31_t* pSrc, - q31_t* pDst, - uint32_t numSamples); - - -/** - * @brief Q15 complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ -void arm_cmplx_mag_squared_q15( - q15_t* pSrc, - q15_t* pDst, - uint32_t numSamples); - - -/** - * @ingroup groupController - */ - -/** - * @defgroup PID PID Motor Control - * - * A Proportional Integral Derivative (PID) controller is a generic feedback control - * loop mechanism widely used in industrial control systems. - * A PID controller is the most commonly used type of feedback controller. - * - * This set of functions implements (PID) controllers - * for Q15, Q31, and floating-point data types. The functions operate on a single sample - * of data and each call to the function returns a single processed value. - * S points to an instance of the PID control data structure. in - * is the input sample value. The functions return the output value. - * - * \par Algorithm: - * 
- *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
- *    A0 = Kp + Ki + Kd
- *    A1 = (-Kp ) - (2 * Kd )
- *    A2 = Kd
- * - * \par - * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant - * - * \par - * \image html PID.gif "Proportional Integral Derivative Controller" - * - * \par - * The PID controller calculates an "error" value as the difference between - * the measured output and the reference input. - * The controller attempts to minimize the error by adjusting the process control inputs. - * The proportional value determines the reaction to the current error, - * the integral value determines the reaction based on the sum of recent errors, - * and the derivative value determines the reaction based on the rate at which the error has been changing. - * - * \par Instance Structure - * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. - * A separate instance structure must be defined for each PID Controller. - * There are separate instance structure declarations for each of the 3 supported data types. - * - * \par Reset Functions - * There is also an associated reset function for each data type which clears the state array. - * - * \par Initialization Functions - * There is also an associated initialization function for each data type. - * The initialization function performs the following operations: - * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. - * - Zeros out the values in the state buffer. - * - * \par - * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. - * - * \par Fixed-Point Behavior - * Care must be taken when using the fixed-point versions of the PID Controller functions. - * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - -/** - * @addtogroup PID - * @{ - */ - -/** - * @brief Process function for the floating-point PID Control. - * @param[in,out] S is an instance of the floating-point PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - */ -CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32( - arm_pid_instance_f32* S, - float32_t in) -{ - float32_t out; - - /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ - out = (S->A0 * in) + - (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - -} - -/** - * @brief Process function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q31 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 64-bit accumulator. - * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. - * Thus, if the accumulator result overflows it wraps around rather than clip. - * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. - * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. - */ -CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31( - arm_pid_instance_q31* S, - q31_t in) -{ - q63_t acc; - q31_t out; - - /* acc = A0 * x[n] */ - acc = (q63_t) S->A0 * in; - - /* acc += A1 * x[n-1] */ - acc += (q63_t) S->A1 * S->state[0]; - - /* acc += A2 * x[n-2] */ - acc += (q63_t) S->A2 * S->state[1]; - - /* convert output to 1.31 format to add y[n-1] */ - out = (q31_t) (acc >> 31u); - - /* out += y[n-1] */ - out += S->state[2]; - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); -} - - -/** - * @brief Process function for the Q15 PID Control. - * @param[in,out] S points to an instance of the Q15 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using a 64-bit internal accumulator. - * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. - * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. - * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. - * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. - * Lastly, the accumulator is saturated to yield a result in 1.15 format. - */ -CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15( - arm_pid_instance_q15* S, - q15_t in) -{ - q63_t acc; - q15_t out; - -#if defined (ARM_MATH_DSP) - __SIMD32_TYPE* vstate; - - /* Implementation of PID controller */ - - /* acc = A0 * x[n] */ - acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - vstate = __SIMD32_CONST(S->state); - acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t) * vstate, (uint64_t)acc); -#else - /* acc = A0 * x[n] */ - acc = ((q31_t) S->A0) * in; - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - acc += (q31_t) S->A1 * S->state[0]; - acc += (q31_t) S->A2 * S->state[1]; -#endif - - /* acc += y[n-1] */ - acc += (q31_t) S->state[2] << 15; - - /* saturate the output */ - out = (q15_t) (__SSAT((acc >> 15), 16)); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); -} - -/** - * @} end of PID group - */ - - -/** - * @brief Floating-point matrix inverse. - * @param[in] src points to the instance of the input floating-point matrix structure. - * @param[out] dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ -arm_status arm_mat_inverse_f32( - const arm_matrix_instance_f32* src, - arm_matrix_instance_f32* dst); - - -/** - * @brief Floating-point matrix inverse. - * @param[in] src points to the instance of the input floating-point matrix structure. - * @param[out] dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ -arm_status arm_mat_inverse_f64( - const arm_matrix_instance_f64* src, - arm_matrix_instance_f64* dst); - - - -/** - * @ingroup groupController - */ - -/** - * @defgroup clarke Vector Clarke Transform - * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. - * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents - * in the two-phase orthogonal stator axis Ialpha and Ibeta. - * When Ialpha is superposed with Ia as shown in the figure below - * \image html clarke.gif Stator current space vector and its components in (a,b). - * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta - * can be calculated using only Ia and Ib. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeFormula.gif - * where Ia and Ib are the instantaneous stator phases and - * pIalpha and pIbeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - -/** - * @addtogroup clarke - * @{ - */ - -/** - * - * @brief Floating-point Clarke transform - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - */ -CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32( - float32_t Ia, - float32_t Ib, - float32_t* pIalpha, - float32_t* pIbeta) -{ - /* Calculate pIalpha using the equation, pIalpha = Ia */ - *pIalpha = Ia; - - /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ - *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); -} - - -/** - * @brief Clarke transform for Q31 version - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ -CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31( - q31_t Ia, - q31_t Ib, - q31_t* pIalpha, - q31_t* pIbeta) -{ - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIalpha from Ia by equation pIalpha = Ia */ - *pIalpha = Ia; - - /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); - - /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ - product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); - - /* pIbeta is calculated by adding the intermediate products */ - *pIbeta = __QADD(product1, product2); -} - -/** - * @} end of clarke group - */ - -/** - * @brief Converts the elements of the Q7 vector to Q31 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ -void arm_q7_to_q31( - q7_t* pSrc, - q31_t* pDst, - uint32_t blockSize); - - - -/** - * @ingroup groupController - */ - -/** - * @defgroup inv_clarke Vector Inverse Clarke Transform - * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeInvFormula.gif - * where pIa and pIb are the instantaneous stator phases and - * Ialpha and Ibeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - -/** - * @addtogroup inv_clarke - * @{ - */ - -/** -* @brief Floating-point Inverse Clarke transform -* @param[in] Ialpha input two-phase orthogonal vector axis alpha -* @param[in] Ibeta input two-phase orthogonal vector axis beta -* @param[out] pIa points to output three-phase coordinate a -* @param[out] pIb points to output three-phase coordinate b -*/ -CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t* pIa, - float32_t* pIb) -{ - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ - *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; -} - - -/** - * @brief Inverse Clarke transform for Q31 version - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] pIa points to output three-phase coordinate a - * @param[out] pIb points to output three-phase coordinate b - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the subtraction, hence there is no risk of overflow. - */ -CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t* pIa, - q31_t* pIb) -{ - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); - - /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); - - /* pIb is calculated by subtracting the products */ - *pIb = __QSUB(product2, product1); -} - -/** - * @} end of inv_clarke group - */ - -/** - * @brief Converts the elements of the Q7 vector to Q15 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ -void arm_q7_to_q15( - q7_t* pSrc, - q15_t* pDst, - uint32_t blockSize); - - - -/** - * @ingroup groupController - */ - -/** - * @defgroup park Vector Park Transform - * - * Forward Park transform converts the input two-coordinate vector to flux and torque components. - * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents - * from the stationary to the moving reference frame and control the spatial relationship between - * the stator vector current and rotor flux vector. - * If we consider the d axis aligned with the rotor flux, the diagram below shows the - * current vector and the relationship from the two reference frames: - * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkFormula.gif - * where Ialpha and Ibeta are the stator vector components, - * pId and pIq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - -/** - * @addtogroup park - * @{ - */ - -/** - * @brief Floating-point Park transform - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] pId points to output rotor reference frame d - * @param[out] pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * The function implements the forward Park transform. - * - */ -CMSIS_INLINE __STATIC_INLINE void arm_park_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t* pId, - float32_t* pIq, - float32_t sinVal, - float32_t cosVal) -{ - /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ - *pId = Ialpha * cosVal + Ibeta * sinVal; - - /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ - *pIq = -Ialpha * sinVal + Ibeta * cosVal; -} - - -/** - * @brief Park transform for Q31 version - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] pId points to output rotor reference frame d - * @param[out] pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition and subtraction, hence there is no risk of overflow. - */ -CMSIS_INLINE __STATIC_INLINE void arm_park_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t* pId, - q31_t* pIq, - q31_t sinVal, - q31_t cosVal) -{ - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Ialpha * cosVal) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * sinVal) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Ialpha * sinVal) */ - product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * cosVal) */ - product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); - - /* Calculate pId by adding the two intermediate products 1 and 2 */ - *pId = __QADD(product1, product2); - - /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ - *pIq = __QSUB(product4, product3); -} - -/** - * @} end of park group - */ - -/** - * @brief Converts the elements of the Q7 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ -void arm_q7_to_float( - q7_t* pSrc, - float32_t* pDst, - uint32_t blockSize); - - -/** - * @ingroup groupController - */ - -/** - * @defgroup inv_park Vector Inverse Park transform - * Inverse Park transform converts the input flux and torque components to two-coordinate vector. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkInvFormula.gif - * where pIalpha and pIbeta are the stator vector components, - * Id and Iq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - -/** - * @addtogroup inv_park - * @{ - */ - -/** -* @brief Floating-point Inverse Park transform -* @param[in] Id input coordinate of rotor reference frame d -* @param[in] Iq input coordinate of rotor reference frame q -* @param[out] pIalpha points to output two-phase orthogonal vector axis alpha -* @param[out] pIbeta points to output two-phase orthogonal vector axis beta -* @param[in] sinVal sine value of rotation angle theta -* @param[in] cosVal cosine value of rotation angle theta -*/ -CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32( - float32_t Id, - float32_t Iq, - float32_t* pIalpha, - float32_t* pIbeta, - float32_t sinVal, - float32_t cosVal) -{ - /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ - *pIalpha = Id * cosVal - Iq * sinVal; - - /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ - *pIbeta = Id * sinVal + Iq * cosVal; -} - - -/** - * @brief Inverse Park transform for Q31 version - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ -CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31( - q31_t Id, - q31_t Iq, - q31_t* pIalpha, - q31_t* pIbeta, - q31_t sinVal, - q31_t cosVal) -{ - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Id * cosVal) */ - product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Iq * sinVal) */ - product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Id * sinVal) */ - product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Iq * cosVal) */ - product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); - - /* Calculate pIalpha by using the two intermediate products 1 and 2 */ - *pIalpha = __QSUB(product1, product2); - - /* Calculate pIbeta by using the two intermediate products 3 and 4 */ - *pIbeta = __QADD(product4, product3); -} - -/** - * @} end of Inverse park group - */ - - -/** - * @brief Converts the elements of the Q31 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ -void arm_q31_to_float( - q31_t* pSrc, - float32_t* pDst, - uint32_t blockSize); - -/** - * @ingroup groupInterpolation - */ - -/** - * @defgroup LinearInterpolate Linear Interpolation - * - * Linear interpolation is a method of curve fitting using linear polynomials. - * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line - * - * \par - * \image html LinearInterp.gif "Linear interpolation" - * - * \par - * A Linear Interpolate function calculates an output value(y), for the input(x) - * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) - * - * \par Algorithm: - * 
- *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
- *       where x0, x1 are nearest values of input x
- *             y0, y1 are nearest values to output y
- *
- * - * \par - * This set of functions implements Linear interpolation process - * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single - * sample of data and each call to the function returns a single processed value. - * S points to an instance of the Linear Interpolate function data structure. - * x is the input sample value. The functions returns the output value. - * - * \par - * if x is outside of the table boundary, Linear interpolation returns first value of the table - * if x is below input range and returns last value of table if x is above range. - */ - -/** - * @addtogroup LinearInterpolate - * @{ - */ - -/** - * @brief Process function for the floating-point Linear Interpolation Function. - * @param[in,out] S is an instance of the floating-point Linear Interpolation structure - * @param[in] x input sample to process - * @return y processed output sample. - * - */ -CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32( - arm_linear_interp_instance_f32* S, - float32_t x) -{ - float32_t y; - float32_t x0, x1; /* Nearest input values */ - float32_t y0, y1; /* Nearest output values */ - float32_t xSpacing = S->xSpacing; /* spacing between input values */ - int32_t i; /* Index variable */ - float32_t* pYData = S->pYData; /* pointer to output table */ - - /* Calculation of index */ - i = (int32_t) ((x - S->x1) / xSpacing); - - if (i < 0) { - /* Iniatilize output for below specified range as least output value of table */ - y = pYData[0]; - } - else if ((uint32_t)i >= S->nValues) { - /* Iniatilize output for above specified range as last output value of table */ - y = pYData[S->nValues - 1]; - } - else { - /* Calculation of nearest input values */ - x0 = S->x1 + i * xSpacing; - x1 = S->x1 + (i + 1) * xSpacing; - - /* Read of nearest output values */ - y0 = pYData[i]; - y1 = pYData[i + 1]; - - /* Calculation of output */ - y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); - - } - - /* returns output value */ - return (y); -} - - -/** -* -* @brief Process function for the Q31 Linear Interpolation Function. -* @param[in] pYData pointer to Q31 Linear Interpolation table -* @param[in] x input sample to process -* @param[in] nValues number of table values -* @return y processed output sample. -* -* \par -* Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. -* This function can support maximum of table size 2^12. -* -*/ -CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31( - q31_t* pYData, - q31_t x, - uint32_t nValues) -{ - q31_t y; /* output */ - q31_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & (q31_t)0xFFF00000) >> 20); - - if (index >= (int32_t)(nValues - 1)) { - return (pYData[nValues - 1]); - } - else if (index < 0) { - return (pYData[0]); - } - else { - /* 20 bits for the fractional part */ - /* shift left by 11 to keep fract in 1.31 format */ - fract = (x & 0x000FFFFF) << 11; - - /* Read two nearest output values from the index in 1.31(q31) format */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract) and y is in 2.30 format */ - y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); - - /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ - y += ((q31_t) (((q63_t) y1 * fract) >> 32)); - - /* Convert y to 1.31 format */ - return (y << 1u); - } -} - - -/** - * - * @brief Process function for the Q15 Linear Interpolation Function. - * @param[in] pYData pointer to Q15 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ -CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15( - q15_t* pYData, - q31_t x, - uint32_t nValues) -{ - q63_t y; /* output */ - q15_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & (int32_t)0xFFF00000) >> 20); - - if (index >= (int32_t)(nValues - 1)) { - return (pYData[nValues - 1]); - } - else if (index < 0) { - return (pYData[0]); - } - else { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract) and y is in 13.35 format */ - y = ((q63_t) y0 * (0xFFFFF - fract)); - - /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ - y += ((q63_t) y1 * (fract)); - - /* convert y to 1.15 format */ - return (q15_t) (y >> 20); - } -} - - -/** - * - * @brief Process function for the Q7 Linear Interpolation Function. - * @param[in] pYData pointer to Q7 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - */ -CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7( - q7_t* pYData, - q31_t x, - uint32_t nValues) -{ - q31_t y; /* output */ - q7_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - uint32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - if (x < 0) { - return (pYData[0]); - } - index = (x >> 20) & 0xfff; - - if (index >= (nValues - 1)) { - return (pYData[nValues - 1]); - } - else { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index and are in 1.7(q7) format */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ - y = ((y0 * (0xFFFFF - fract))); - - /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ - y += (y1 * fract); - - /* convert y to 1.7(q7) format */ - return (q7_t) (y >> 20); - } -} - -/** - * @} end of LinearInterpolate group - */ - -/** - * @brief Fast approximation to the trigonometric sine function for floating-point data. - * @param[in] x input value in radians. - * @return sin(x). - */ -float32_t arm_sin_f32( - float32_t x); - - -/** - * @brief Fast approximation to the trigonometric sine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ -q31_t arm_sin_q31( - q31_t x); - - -/** - * @brief Fast approximation to the trigonometric sine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ -q15_t arm_sin_q15( - q15_t x); - - -/** - * @brief Fast approximation to the trigonometric cosine function for floating-point data. - * @param[in] x input value in radians. - * @return cos(x). - */ -float32_t arm_cos_f32( - float32_t x); - - -/** - * @brief Fast approximation to the trigonometric cosine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ -q31_t arm_cos_q31( - q31_t x); - - -/** - * @brief Fast approximation to the trigonometric cosine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ -q15_t arm_cos_q15( - q15_t x); - - -/** - * @ingroup groupFastMath - */ - - -/** - * @defgroup SQRT Square Root - * - * Computes the square root of a number. - * There are separate functions for Q15, Q31, and floating-point data types. - * The square root function is computed using the Newton-Raphson algorithm. - * This is an iterative algorithm of the form: - * 
- *      x1 = x0 - f(x0)/f'(x0)
- *
- * where x1 is the current estimate, - * x0 is the previous estimate, and - * f'(x0) is the derivative of f() evaluated at x0. - * For the square root function, the algorithm reduces to: - * 
- *     x0 = in/2                         [initial guess]
- *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
- *
- */ - - -/** - * @addtogroup SQRT - * @{ - */ - -/** - * @brief Floating-point square root function. - * @param[in] in input value. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ -CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32( - float32_t in, - float32_t* pOut) -{ - if (in >= 0.0f) { - -#if (__FPU_USED == 1) && defined ( __CC_ARM ) - *pOut = __sqrtf(in); -#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - *pOut = __builtin_sqrtf(in); -#elif (__FPU_USED == 1) && defined(__GNUC__) - *pOut = __builtin_sqrtf(in); -#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) - __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); -#else - *pOut = sqrtf(in); -#endif - - return (ARM_MATH_SUCCESS); - } - else { - *pOut = 0.0f; - return (ARM_MATH_ARGUMENT_ERROR); - } -} - - -/** - * @brief Q31 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ -arm_status arm_sqrt_q31( - q31_t in, - q31_t* pOut); - - -/** - * @brief Q15 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ -arm_status arm_sqrt_q15( - q15_t in, - q15_t* pOut); - -/** - * @} end of SQRT group - */ - - -/** - * @brief floating-point Circular write function. - */ -CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32( - int32_t* circBuffer, - int32_t L, - uint16_t* writeOffset, - int32_t bufferInc, - const int32_t* src, - int32_t srcInc, - uint32_t blockSize) -{ - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0u) { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if (wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; -} - - - -/** - * @brief floating-point Circular Read function. - */ -CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32( - int32_t* circBuffer, - int32_t L, - int32_t* readOffset, - int32_t bufferInc, - int32_t* dst, - int32_t* dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) -{ - uint32_t i = 0u; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0u) { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if (dst == (int32_t*) dst_end) { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if (rOffset >= L) { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; -} - - -/** - * @brief Q15 Circular write function. - */ -CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15( - q15_t* circBuffer, - int32_t L, - uint16_t* writeOffset, - int32_t bufferInc, - const q15_t* src, - int32_t srcInc, - uint32_t blockSize) -{ - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0u) { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if (wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; -} - - -/** - * @brief Q15 Circular Read function. - */ -CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15( - q15_t* circBuffer, - int32_t L, - int32_t* readOffset, - int32_t bufferInc, - q15_t* dst, - q15_t* dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) -{ - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0u) { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if (dst == (q15_t*) dst_end) { - dst = dst_base; - } - - /* Circularly update wOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if (rOffset >= L) { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; -} - - -/** - * @brief Q7 Circular write function. - */ -CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7( - q7_t* circBuffer, - int32_t L, - uint16_t* writeOffset, - int32_t bufferInc, - const q7_t* src, - int32_t srcInc, - uint32_t blockSize) -{ - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0u) { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if (wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; -} - - -/** - * @brief Q7 Circular Read function. - */ -CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7( - q7_t* circBuffer, - int32_t L, - int32_t* readOffset, - int32_t bufferInc, - q7_t* dst, - q7_t* dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) -{ - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0u) { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if (dst == (q7_t*) dst_end) { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if (rOffset >= L) { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; -} - - -/** - * @brief Sum of the squares of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void arm_power_q31( - q31_t* pSrc, - uint32_t blockSize, - q63_t* pResult); - - -/** - * @brief Sum of the squares of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void arm_power_f32( - float32_t* pSrc, - uint32_t blockSize, - float32_t* pResult); - - -/** - * @brief Sum of the squares of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void arm_power_q15( - q15_t* pSrc, - uint32_t blockSize, - q63_t* pResult); - - -/** - * @brief Sum of the squares of the elements of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void arm_power_q7( - q7_t* pSrc, - uint32_t blockSize, - q31_t* pResult); - - -/** - * @brief Mean value of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void arm_mean_q7( - q7_t* pSrc, - uint32_t blockSize, - q7_t* pResult); - - -/** - * @brief Mean value of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void arm_mean_q15( - q15_t* pSrc, - uint32_t blockSize, - q15_t* pResult); - - -/** - * @brief Mean value of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void arm_mean_q31( - q31_t* pSrc, - uint32_t blockSize, - q31_t* pResult); - - -/** - * @brief Mean value of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void arm_mean_f32( - float32_t* pSrc, - uint32_t blockSize, - float32_t* pResult); - - -/** - * @brief Variance of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void arm_var_f32( - float32_t* pSrc, - uint32_t blockSize, - float32_t* pResult); - - -/** - * @brief Variance of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void arm_var_q31( - q31_t* pSrc, - uint32_t blockSize, - q31_t* pResult); - - -/** - * @brief Variance of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void arm_var_q15( - q15_t* pSrc, - uint32_t blockSize, - q15_t* pResult); - - -/** - * @brief Root Mean Square of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void arm_rms_f32( - float32_t* pSrc, - uint32_t blockSize, - float32_t* pResult); - - -/** - * @brief Root Mean Square of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void arm_rms_q31( - q31_t* pSrc, - uint32_t blockSize, - q31_t* pResult); - - -/** - * @brief Root Mean Square of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void arm_rms_q15( - q15_t* pSrc, - uint32_t blockSize, - q15_t* pResult); - - -/** - * @brief Standard deviation of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void arm_std_f32( - float32_t* pSrc, - uint32_t blockSize, - float32_t* pResult); - - -/** - * @brief Standard deviation of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void arm_std_q31( - q31_t* pSrc, - uint32_t blockSize, - q31_t* pResult); - - -/** - * @brief Standard deviation of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ -void arm_std_q15( - q15_t* pSrc, - uint32_t blockSize, - q15_t* pResult); - - -/** - * @brief Floating-point complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ -void arm_cmplx_mag_f32( - float32_t* pSrc, - float32_t* pDst, - uint32_t numSamples); - - -/** - * @brief Q31 complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ -void arm_cmplx_mag_q31( - q31_t* pSrc, - q31_t* pDst, - uint32_t numSamples); - - -/** - * @brief Q15 complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ -void arm_cmplx_mag_q15( - q15_t* pSrc, - q15_t* pDst, - uint32_t numSamples); - - -/** - * @brief Q15 complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ -void arm_cmplx_dot_prod_q15( - q15_t* pSrcA, - q15_t* pSrcB, - uint32_t numSamples, - q31_t* realResult, - q31_t* imagResult); - - -/** - * @brief Q31 complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ -void arm_cmplx_dot_prod_q31( - q31_t* pSrcA, - q31_t* pSrcB, - uint32_t numSamples, - q63_t* realResult, - q63_t* imagResult); - - -/** - * @brief Floating-point complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ -void arm_cmplx_dot_prod_f32( - float32_t* pSrcA, - float32_t* pSrcB, - uint32_t numSamples, - float32_t* realResult, - float32_t* imagResult); - - -/** - * @brief Q15 complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ -void arm_cmplx_mult_real_q15( - q15_t* pSrcCmplx, - q15_t* pSrcReal, - q15_t* pCmplxDst, - uint32_t numSamples); - - -/** - * @brief Q31 complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ -void arm_cmplx_mult_real_q31( - q31_t* pSrcCmplx, - q31_t* pSrcReal, - q31_t* pCmplxDst, - uint32_t numSamples); - - -/** - * @brief Floating-point complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ -void arm_cmplx_mult_real_f32( - float32_t* pSrcCmplx, - float32_t* pSrcReal, - float32_t* pCmplxDst, - uint32_t numSamples); - - -/** - * @brief Minimum value of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] result is output pointer - * @param[in] index is the array index of the minimum value in the input buffer. - */ -void arm_min_q7( - q7_t* pSrc, - uint32_t blockSize, - q7_t* result, - uint32_t* index); - - -/** - * @brief Minimum value of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[in] pIndex is the array index of the minimum value in the input buffer. - */ -void arm_min_q15( - q15_t* pSrc, - uint32_t blockSize, - q15_t* pResult, - uint32_t* pIndex); - - -/** - * @brief Minimum value of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[out] pIndex is the array index of the minimum value in the input buffer. - */ -void arm_min_q31( - q31_t* pSrc, - uint32_t blockSize, - q31_t* pResult, - uint32_t* pIndex); - - -/** - * @brief Minimum value of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[out] pIndex is the array index of the minimum value in the input buffer. - */ -void arm_min_f32( - float32_t* pSrc, - uint32_t blockSize, - float32_t* pResult, - uint32_t* pIndex); - - -/** - * @brief Maximum value of a Q7 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ -void arm_max_q7( - q7_t* pSrc, - uint32_t blockSize, - q7_t* pResult, - uint32_t* pIndex); - - -/** - * @brief Maximum value of a Q15 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ -void arm_max_q15( - q15_t* pSrc, - uint32_t blockSize, - q15_t* pResult, - uint32_t* pIndex); - - -/** - * @brief Maximum value of a Q31 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ -void arm_max_q31( - q31_t* pSrc, - uint32_t blockSize, - q31_t* pResult, - uint32_t* pIndex); - - -/** - * @brief Maximum value of a floating-point vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ -void arm_max_f32( - float32_t* pSrc, - uint32_t blockSize, - float32_t* pResult, - uint32_t* pIndex); - - -/** - * @brief Q15 complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ -void arm_cmplx_mult_cmplx_q15( - q15_t* pSrcA, - q15_t* pSrcB, - q15_t* pDst, - uint32_t numSamples); - - -/** - * @brief Q31 complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ -void arm_cmplx_mult_cmplx_q31( - q31_t* pSrcA, - q31_t* pSrcB, - q31_t* pDst, - uint32_t numSamples); - - -/** - * @brief Floating-point complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ -void arm_cmplx_mult_cmplx_f32( - float32_t* pSrcA, - float32_t* pSrcB, - float32_t* pDst, - uint32_t numSamples); - - -/** - * @brief Converts the elements of the floating-point vector to Q31 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q31 output vector - * @param[in] blockSize length of the input vector - */ -void arm_float_to_q31( - float32_t* pSrc, - q31_t* pDst, - uint32_t blockSize); - - -/** - * @brief Converts the elements of the floating-point vector to Q15 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q15 output vector - * @param[in] blockSize length of the input vector - */ -void arm_float_to_q15( - float32_t* pSrc, - q15_t* pDst, - uint32_t blockSize); - - -/** - * @brief Converts the elements of the floating-point vector to Q7 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q7 output vector - * @param[in] blockSize length of the input vector - */ -void arm_float_to_q7( - float32_t* pSrc, - q7_t* pDst, - uint32_t blockSize); - - -/** - * @brief Converts the elements of the Q31 vector to Q15 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ -void arm_q31_to_q15( - q31_t* pSrc, - q15_t* pDst, - uint32_t blockSize); - - -/** - * @brief Converts the elements of the Q31 vector to Q7 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ -void arm_q31_to_q7( - q31_t* pSrc, - q7_t* pDst, - uint32_t blockSize); - - -/** - * @brief Converts the elements of the Q15 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ -void arm_q15_to_float( - q15_t* pSrc, - float32_t* pDst, - uint32_t blockSize); - - -/** - * @brief Converts the elements of the Q15 vector to Q31 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ -void arm_q15_to_q31( - q15_t* pSrc, - q31_t* pDst, - uint32_t blockSize); - - -/** - * @brief Converts the elements of the Q15 vector to Q7 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ -void arm_q15_to_q7( - q15_t* pSrc, - q7_t* pDst, - uint32_t blockSize); - - -/** - * @ingroup groupInterpolation - */ - -/** - * @defgroup BilinearInterpolate Bilinear Interpolation - * - * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. - * The underlying function f(x, y) is sampled on a regular grid and the interpolation process - * determines values between the grid points. - * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. - * Bilinear interpolation is often used in image processing to rescale images. - * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. - * - * Algorithm - * \par - * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. - * For floating-point, the instance structure is defined as: - * 
- *   typedef struct
- *   {
- *     uint16_t numRows;
- *     uint16_t numCols;
- *     float32_t *pData;
- * } arm_bilinear_interp_instance_f32;
- *
- * - * \par - * where numRows specifies the number of rows in the table; - * numCols specifies the number of columns in the table; - * and pData points to an array of size numRows*numCols values. - * The data table pTable is organized in row order and the supplied data values fall on integer indexes. - * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. - * - * \par - * Let (x, y) specify the desired interpolation point. Then define: - * 
- *     XF = floor(x)
- *     YF = floor(y)
- *
- * \par - * The interpolated output point is computed as: - * 
- *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
- *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
- *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
- *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
- *
- * Note that the coordinates (x, y) contain integer and fractional components. - * The integer components specify which portion of the table to use while the - * fractional components control the interpolation processor. - * - * \par - * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. - */ - -/** - * @addtogroup BilinearInterpolate - * @{ - */ - - -/** -* -* @brief Floating-point bilinear interpolation. -* @param[in,out] S points to an instance of the interpolation structure. -* @param[in] X interpolation coordinate. -* @param[in] Y interpolation coordinate. -* @return out interpolated value. -*/ -CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32( - const arm_bilinear_interp_instance_f32* S, - float32_t X, - float32_t Y) -{ - float32_t out; - float32_t f00, f01, f10, f11; - float32_t* pData = S->pData; - int32_t xIndex, yIndex, index; - float32_t xdiff, ydiff; - float32_t b1, b2, b3, b4; - - xIndex = (int32_t) X; - yIndex = (int32_t) Y; - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) { - return (0); - } - - /* Calculation of index for two nearest points in X-direction */ - index = (xIndex - 1) + (yIndex - 1) * S->numCols; - - - /* Read two nearest points in X-direction */ - f00 = pData[index]; - f01 = pData[index + 1]; - - /* Calculation of index for two nearest points in Y-direction */ - index = (xIndex - 1) + (yIndex) * S->numCols; - - - /* Read two nearest points in Y-direction */ - f10 = pData[index]; - f11 = pData[index + 1]; - - /* Calculation of intermediate values */ - b1 = f00; - b2 = f01 - f00; - b3 = f10 - f00; - b4 = f00 - f01 - f10 + f11; - - /* Calculation of fractional part in X */ - xdiff = X - xIndex; - - /* Calculation of fractional part in Y */ - ydiff = Y - yIndex; - - /* Calculation of bi-linear interpolated output */ - out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; - - /* return to application */ - return (out); -} - - -/** -* -* @brief Q31 bilinear interpolation. -* @param[in,out] S points to an instance of the interpolation structure. -* @param[in] X interpolation coordinate in 12.20 format. -* @param[in] Y interpolation coordinate in 12.20 format. -* @return out interpolated value. -*/ -CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31( - arm_bilinear_interp_instance_q31* S, - q31_t X, - q31_t Y) -{ - q31_t out; /* Temporary output */ - q31_t acc = 0; /* output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q31_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q31_t* pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) { - return (0); - } - - /* 20 bits for the fractional part */ - /* shift left xfract by 11 to keep 1.31 format */ - xfract = (X & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; - x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; - - /* 20 bits for the fractional part */ - /* shift left yfract by 11 to keep 1.31 format */ - yfract = (Y & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; - y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ - out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); - acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); - - /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); - - /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* Convert acc to 1.31(q31) format */ - return ((q31_t)(acc << 2)); -} - - -/** -* @brief Q15 bilinear interpolation. -* @param[in,out] S points to an instance of the interpolation structure. -* @param[in] X interpolation coordinate in 12.20 format. -* @param[in] Y interpolation coordinate in 12.20 format. -* @return out interpolated value. -*/ -CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15( - arm_bilinear_interp_instance_q15* S, - q31_t X, - q31_t Y) -{ - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q15_t x1, x2, y1, y2; /* Nearest output values */ - q31_t xfract, yfract; /* X, Y fractional parts */ - int32_t rI, cI; /* Row and column indices */ - q15_t* pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; - x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; - y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ - - /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ - /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ - out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); - acc = ((q63_t) out * (0xFFFFF - yfract)); - - /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); - acc += ((q63_t) out * (xfract)); - - /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* acc is in 13.51 format and down shift acc by 36 times */ - /* Convert out to 1.15 format */ - return ((q15_t)(acc >> 36)); -} - - -/** -* @brief Q7 bilinear interpolation. -* @param[in,out] S points to an instance of the interpolation structure. -* @param[in] X interpolation coordinate in 12.20 format. -* @param[in] Y interpolation coordinate in 12.20 format. -* @return out interpolated value. -*/ -CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7( - arm_bilinear_interp_instance_q7* S, - q31_t X, - q31_t Y) -{ - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q7_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q7_t* pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & (q31_t)0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; - x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & (q31_t)0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; - y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ - out = ((x1 * (0xFFFFF - xfract))); - acc = (((q63_t) out * (0xFFFFF - yfract))); - - /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ - out = ((x2 * (0xFFFFF - yfract))); - acc += (((q63_t) out * (xfract))); - - /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y1 * (0xFFFFF - xfract))); - acc += (((q63_t) out * (yfract))); - - /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y2 * (yfract))); - acc += (((q63_t) out * (xfract))); - - /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ - return ((q7_t)(acc >> 40)); -} - -/** - * @} end of BilinearInterpolate group - */ - - -/* SMMLAR */ -#define multAcc_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) - -/* SMMLSR */ -#define multSub_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) - -/* SMMULR */ -#define mult_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) - -/* SMMLA */ -#define multAcc_32x32_keep32(a, x, y) \ - a += (q31_t) (((q63_t) x * y) >> 32) - -/* SMMLS */ -#define multSub_32x32_keep32(a, x, y) \ - a -= (q31_t) (((q63_t) x * y) >> 32) - -/* SMMUL */ -#define mult_32x32_keep32(a, x, y) \ - a = (q31_t) (((q63_t) x * y ) >> 32) - - -#if defined ( __CC_ARM ) -/* Enter low optimization region - place directly above function definition */ -#if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) -#define LOW_OPTIMIZATION_ENTER \ - _Pragma ("push") \ - _Pragma ("O1") -#else -#define LOW_OPTIMIZATION_ENTER -#endif - -/* Exit low optimization region - place directly after end of function definition */ -#if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) -#define LOW_OPTIMIZATION_EXIT \ - _Pragma ("pop") -#else -#define LOW_OPTIMIZATION_EXIT -#endif - -/* Enter low optimization region - place directly above function definition */ -#define IAR_ONLY_LOW_OPTIMIZATION_ENTER - -/* Exit low optimization region - place directly after end of function definition */ -#define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) -#define LOW_OPTIMIZATION_ENTER -#define LOW_OPTIMIZATION_EXIT -#define IAR_ONLY_LOW_OPTIMIZATION_ENTER -#define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined ( __GNUC__ ) -#define LOW_OPTIMIZATION_ENTER \ - __attribute__(( optimize("-O1") )) -#define LOW_OPTIMIZATION_EXIT -#define IAR_ONLY_LOW_OPTIMIZATION_ENTER -#define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined ( __ICCARM__ ) -/* Enter low optimization region - place directly above function definition */ -#if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) -#define LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") -#else -#define LOW_OPTIMIZATION_ENTER -#endif - -/* Exit low optimization region - place directly after end of function definition */ -#define LOW_OPTIMIZATION_EXIT - -/* Enter low optimization region - place directly above function definition */ -#if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) -#define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") -#else -#define IAR_ONLY_LOW_OPTIMIZATION_ENTER -#endif - -/* Exit low optimization region - place directly after end of function definition */ -#define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined ( __TI_ARM__ ) -#define LOW_OPTIMIZATION_ENTER -#define LOW_OPTIMIZATION_EXIT -#define IAR_ONLY_LOW_OPTIMIZATION_ENTER -#define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined ( __CSMC__ ) -#define LOW_OPTIMIZATION_ENTER -#define LOW_OPTIMIZATION_EXIT -#define IAR_ONLY_LOW_OPTIMIZATION_ENTER -#define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined ( __TASKING__ ) -#define LOW_OPTIMIZATION_ENTER -#define LOW_OPTIMIZATION_EXIT -#define IAR_ONLY_LOW_OPTIMIZATION_ENTER -#define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#endif - - -#ifdef __cplusplus -} -#endif - - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -#endif /* _ARM_MATH_H */ - -/** - * - * End of file. - */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_armcc.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_armcc.h deleted file mode 100644 index 4617b1280..000000000 --- a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_armcc.h +++ /dev/null @@ -1,796 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armcc.h - * @brief CMSIS compiler ARMCC (ARM compiler V5) header file - * @version V5.0.1 - * @date 03. February 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_ARMCC_H -#define __CMSIS_ARMCC_H - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) -#error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* CMSIS compiler control architecture macros */ -#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ - (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) -#define __ARM_ARCH_6M__ 1 -#endif - -#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) -#define __ARM_ARCH_7M__ 1 -#endif - -#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) -#define __ARM_ARCH_7EM__ 1 -#endif - -/* __ARM_ARCH_8M_BASE__ not applicable */ -/* __ARM_ARCH_8M_MAIN__ not applicable */ - - -/* CMSIS compiler specific defines */ -#ifndef __ASM -#define __ASM __asm -#endif -#ifndef __INLINE -#define __INLINE __inline -#endif -#ifndef __STATIC_INLINE -#define __STATIC_INLINE static __inline -#endif -#ifndef __NO_RETURN -#define __NO_RETURN __declspec(noreturn) -#endif -#ifndef __USED -#define __USED __attribute__((used)) -#endif -#ifndef __WEAK -#define __WEAK __attribute__((weak)) -#endif -#ifndef __UNALIGNED_UINT32 -#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) -#endif -#ifndef __ALIGNED -#define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __PACKED -#define __PACKED __attribute__((packed)) -#endif -#ifndef __PACKED_STRUCT -#define __PACKED_STRUCT __packed struct -#endif - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -/* intrinsic void __enable_irq(); */ - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -/* intrinsic void __disable_irq(); */ - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xFFU); -} - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - register uint32_t __regBasePriMax __ASM("basepri_max"); - __regBasePriMax = (basePri & 0xFFU); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1U); -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#else - (void)fpscr; -#endif -} - -#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() do {\ - __schedule_barrier();\ - __isb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() do {\ - __schedule_barrier();\ - __dsb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() do {\ - __schedule_barrier();\ - __dmb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - - -/** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) -#define __RBIT __rbit -#else -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ - return(result); -} -#endif - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) -#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) -#else -#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) -#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) -#else -#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) -#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) -#else -#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) -#define __STREXB(value, ptr) __strex(value, ptr) -#else -#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) -#define __STREXH(value, ptr) __strex(value, ptr) -#else -#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) -#define __STREXW(value, ptr) __strex(value, ptr) -#else -#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __clrex - - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) -{ - rrx r0, r0 - bx lr -} -#endif - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRBT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRHT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRT(value, ptr) __strt(value, ptr) - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ - ((int64_t)(ARG3) << 32U) ) >> 32U)) - -#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCC_H */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_armclang.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_armclang.h deleted file mode 100644 index 6b21a5bea..000000000 --- a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_armclang.h +++ /dev/null @@ -1,1735 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armclang.h - * @brief CMSIS compiler ARMCLANG (ARM compiler V6) header file - * @version V5.0.1 - * @date 02. February 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_ARMCLANG_H -#define __CMSIS_ARMCLANG_H - -#ifndef __ARM_COMPAT_H -#include /* Compatibility header for ARM Compiler 5 intrinsics */ -#endif - -/* CMSIS compiler specific defines */ -#ifndef __ASM -#define __ASM __asm -#endif -#ifndef __INLINE -#define __INLINE __inline -#endif -#ifndef __STATIC_INLINE -#define __STATIC_INLINE static __inline -#endif -#ifndef __NO_RETURN -#define __NO_RETURN __attribute__((noreturn)) -#endif -#ifndef __USED -#define __USED __attribute__((used)) -#endif -#ifndef __WEAK -#define __WEAK __attribute__((weak)) -#endif -#ifndef __UNALIGNED_UINT32 -#pragma clang diagnostic push -#pragma clang diagnostic ignored "-Wpacked" -struct __attribute__((packed)) T_UINT32 { - uint32_t v; -}; -#pragma clang diagnostic pop -#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -#endif -#ifndef __ALIGNED -#define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __PACKED -#define __PACKED __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_STRUCT -#define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -/* intrinsic void __enable_irq(); see arm_compat.h */ - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -/* intrinsic void __disable_irq(); see arm_compat.h */ - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - -/** - \brief Get Process Stack Pointer Limit - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return(result); -} - - -#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ - (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Get Process Stack Pointer Limit (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -} - - -#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ - (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - - return(result); -} - - -#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ - (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Get Main Stack Pointer Limit (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -} - - -#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ - (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Set Main Stack Pointer Limit (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -} -#endif - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -/* #define __get_FPSCR __builtin_arm_get_fpscr */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - uint32_t result; - - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - return(result); -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -/* #define __set_FPSCR __builtin_arm_set_fpscr */ -__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "memory"); -#else - (void)fpscr; -#endif -} - -#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __builtin_arm_nop - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __builtin_arm_wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __builtin_arm_wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __builtin_arm_sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() __builtin_arm_isb(0xF); - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __builtin_arm_dsb(0xF); - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __builtin_arm_dmb(0xF); - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __builtin_bswap32 - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV16 __builtin_bswap16 /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */ -#if 0 -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} -#endif - - -/** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. - \param [in] value Value to reverse - \return Reversed value - */ -/* ToDo ARMCLANG: check if __builtin_bswap16 could be used */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ - int32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -/* ToDo ARMCLANG: check if __builtin_arm_rbit is supported */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ -#endif - return(result); -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __builtin_clz - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB (uint8_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH (uint16_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW (uint32_t)__builtin_arm_ldrex - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW (uint32_t)__builtin_arm_strex - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __builtin_arm_clrex - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __builtin_arm_ssat - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __builtin_arm_usat - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t* ptr) -{ - uint32_t result; - - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t* ptr) -{ - uint32_t result; - - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t* ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t* ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t* ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t* ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t* ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t* ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t* ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t* ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t* ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t* ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDAEXB (uint8_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDAEXH (uint16_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDAEX (uint32_t)__builtin_arm_ldaex - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXB (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXH (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEX (uint32_t)__builtin_arm_stlex - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ - ({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ - ({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u { - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u { - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u { - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u { - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#if 0 -#define __PKHBT(ARG1,ARG2,ARG3) \ - ({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ - ({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) -#endif - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCLANG_H */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_compiler.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_compiler.h deleted file mode 100644 index 89cd69027..000000000 --- a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_compiler.h +++ /dev/null @@ -1,231 +0,0 @@ -/**************************************************************************//** - * @file cmsis_compiler.h - * @brief CMSIS compiler generic header file - * @version V5.0.1 - * @date 30. January 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_COMPILER_H -#define __CMSIS_COMPILER_H - -#include - -/* - * ARM Compiler 4/5 - */ -#if defined ( __CC_ARM ) -#include "cmsis_armcc.h" - - -/* - * ARM Compiler 6 (armclang) - */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#include "cmsis_armclang.h" - - -/* - * GNU Compiler - */ -#elif defined ( __GNUC__ ) -#include "cmsis_gcc.h" - - -/* - * IAR Compiler - */ -#elif defined ( __ICCARM__ ) - -#ifndef __ASM -#define __ASM __asm -#endif -#ifndef __INLINE -#define __INLINE inline -#endif -#ifndef __STATIC_INLINE -#define __STATIC_INLINE static inline -#endif - -#include - -#ifndef __NO_RETURN -#define __NO_RETURN __noreturn -#endif -#ifndef __USED -#define __USED __root -#endif -#ifndef __WEAK -#define __WEAK __weak -#endif -#ifndef __UNALIGNED_UINT32 -__packed struct T_UINT32 { - uint32_t v; -}; -#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -#endif -#ifndef __ALIGNED -#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. -#define __ALIGNED(x) -#endif -#ifndef __PACKED -#define __PACKED __packed -#endif -#ifndef __PACKED_STRUCT -#define __PACKED_STRUCT __packed struct -#endif - - -/* - * TI ARM Compiler - */ -#elif defined ( __TI_ARM__ ) -#include - -#ifndef __ASM -#define __ASM __asm -#endif -#ifndef __INLINE -#define __INLINE inline -#endif -#ifndef __STATIC_INLINE -#define __STATIC_INLINE static inline -#endif -#ifndef __NO_RETURN -#define __NO_RETURN __attribute__((noreturn)) -#endif -#ifndef __USED -#define __USED __attribute__((used)) -#endif -#ifndef __WEAK -#define __WEAK __attribute__((weak)) -#endif -#ifndef __UNALIGNED_UINT32 -struct __attribute__((packed)) T_UINT32 { - uint32_t v; -}; -#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -#endif -#ifndef __ALIGNED -#define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __PACKED -#define __PACKED __attribute__((packed)) -#endif -#ifndef __PACKED_STRUCT -#define __PACKED_STRUCT struct __attribute__((packed)) -#endif - - -/* - * TASKING Compiler - */ -#elif defined ( __TASKING__ ) -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -#ifndef __ASM -#define __ASM __asm -#endif -#ifndef __INLINE -#define __INLINE inline -#endif -#ifndef __STATIC_INLINE -#define __STATIC_INLINE static inline -#endif -#ifndef __NO_RETURN -#define __NO_RETURN __attribute__((noreturn)) -#endif -#ifndef __USED -#define __USED __attribute__((used)) -#endif -#ifndef __WEAK -#define __WEAK __attribute__((weak)) -#endif -#ifndef __UNALIGNED_UINT32 -struct __packed__ T_UINT32 { - uint32_t v; -}; -#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -#endif -#ifndef __ALIGNED -#define __ALIGNED(x) __align(x) -#endif -#ifndef __PACKED -#define __PACKED __packed__ -#endif -#ifndef __PACKED_STRUCT -#define __PACKED_STRUCT struct __packed__ -#endif - - -/* - * COSMIC Compiler - */ -#elif defined ( __CSMC__ ) -#include - -#ifndef __ASM -#define __ASM _asm -#endif -#ifndef __INLINE -#define __INLINE inline -#endif -#ifndef __STATIC_INLINE -#define __STATIC_INLINE static inline -#endif -#ifndef __NO_RETURN -// NO RETURN is automatically detected hence no warning here -#define __NO_RETURN -#endif -#ifndef __USED -#warning No compiler specific solution for __USED. __USED is ignored. -#define __USED -#endif -#ifndef __WEAK -#define __WEAK __weak -#endif -#ifndef __UNALIGNED_UINT32 -@packed struct T_UINT32 { - uint32_t v; -}; -#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -#endif -#ifndef __ALIGNED -#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. -#define __ALIGNED(x) -#endif -#ifndef __PACKED -#define __PACKED @packed -#endif -#ifndef __PACKED_STRUCT -#define __PACKED_STRUCT @packed struct -#endif - - -#else -#error Unknown compiler. -#endif - - -#endif /* __CMSIS_COMPILER_H */ - diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_gcc.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_gcc.h deleted file mode 100644 index 919f26d15..000000000 --- a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_gcc.h +++ /dev/null @@ -1,1900 +0,0 @@ -/**************************************************************************//** - * @file cmsis_gcc.h - * @brief CMSIS compiler GCC header file - * @version V5.0.1 - * @date 02. February 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_GCC_H -#define __CMSIS_GCC_H - -/* ignore some GCC warnings */ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" - -/* CMSIS compiler specific defines */ -#ifndef __ASM -#define __ASM __asm -#endif -#ifndef __INLINE -#define __INLINE inline -#endif -#ifndef __STATIC_INLINE -#define __STATIC_INLINE static inline -#endif -#ifndef __NO_RETURN -#define __NO_RETURN __attribute__((noreturn)) -#endif -#ifndef __USED -#define __USED __attribute__((used)) -#endif -#ifndef __WEAK -#define __WEAK __attribute__((weak)) -#endif -#ifndef __UNALIGNED_UINT32 -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpacked" -#pragma GCC diagnostic ignored "-Wattributes" -struct __attribute__((packed)) T_UINT32 { - uint32_t v; -}; -#pragma GCC diagnostic pop -#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -#endif -#ifndef __ALIGNED -#define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __PACKED -#define __PACKED __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_STRUCT -#define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - -/** - \brief Get Process Stack Pointer Limit - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return(result); -} - - -#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ - (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Get Process Stack Pointer Limit (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -} - - -#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ - (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - - return(result); -} - - -#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ - (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Get Main Stack Pointer Limit (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -} - - -#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ - (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Set Main Stack Pointer Limit (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -} -#endif - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - uint32_t result; - - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - return(result); -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); -#else - (void)fpscr; -#endif -} - -#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_RW_REG(r) "+l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_RW_REG(r) "+r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -//__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) -//{ -// __ASM volatile ("nop"); -//} -#define __NOP() __ASM volatile ("nop") /* This implementation generates debug information */ - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -//__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) -//{ -// __ASM volatile ("wfi"); -//} -#define __WFI() __ASM volatile ("wfi") /* This implementation generates debug information */ - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -//__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) -//{ -// __ASM volatile ("wfe"); -//} -#define __WFE() __ASM volatile ("wfe") /* This implementation generates debug information */ - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -//__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) -//{ -// __ASM volatile ("sev"); -//} -#define __SEV() __ASM volatile ("sev") /* This implementation generates debug information */ - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb 0xF"::: "memory"); -} - - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb 0xF"::: "memory"); -} - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb 0xF"::: "memory"); -} - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (short)__builtin_bswap16(value); -#else - int32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ -#endif - return(result); -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __builtin_clz - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t* addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t* addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t* addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t* addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t* addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t* addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ - ({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ - ({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t* ptr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t* ptr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t* ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t* ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t* ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t* ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t* ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t* ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t* ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t* ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t* ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t* ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAEXB(volatile uint8_t* ptr) -{ - uint32_t result; - - __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAEXH(volatile uint16_t* ptr) -{ - uint32_t result; - - __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDAEX(volatile uint32_t* ptr) -{ - uint32_t result; - - __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t* ptr) -{ - uint32_t result; - - __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t* ptr) -{ - uint32_t result; - - __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEX(uint32_t value, volatile uint32_t* ptr) -{ - uint32_t result; - - __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); - return(result); -} - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (__ARM_FEATURE_DSP == 1) /* ToDo ARMCLANG: This should be ARCH >= ARMv7-M + SIMD */ - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ - ({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ - ({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u { - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u { - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u { - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u { - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#if 0 -#define __PKHBT(ARG1,ARG2,ARG3) \ - ({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ - ({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) -#endif - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#pragma GCC diagnostic pop - -#endif /* __CMSIS_GCC_H */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_armv8mbl.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_armv8mbl.h deleted file mode 100644 index 4e65d1d95..000000000 --- a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_armv8mbl.h +++ /dev/null @@ -1,1813 +0,0 @@ -/**************************************************************************//** - * @file core_armv8mbl.h - * @brief CMSIS ARMv8MBL Core Peripheral Access Layer Header File - * @version V5.0.1 - * @date 25. November 2016 - ******************************************************************************/ -/* - * Copyright (c) 2009-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) -#pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_ARMV8MBL_H_GENERIC -#define __CORE_ARMV8MBL_H_GENERIC - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_ARMv8MBL - @{ - */ - -/* CMSIS cmGrebe definitions */ -#define __ARMv8MBL_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ -#define __ARMv8MBL_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ -#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ - __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) -#if defined __TARGET_FPU_VFP -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#if defined __ARM_PCS_VFP -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __GNUC__ ) -#if defined (__VFP_FP__) && !defined(__SOFTFP__) -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __ICCARM__ ) -#if defined __ARMVFP__ -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __TI_ARM__ ) -#if defined __TI_VFP_SUPPORT__ -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __TASKING__ ) -#if defined __FPU_VFP__ -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __CSMC__ ) -#if ( __CSMC__ & 0x400U) -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV8MBL_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_ARMV8MBL_H_DEPENDANT -#define __CORE_ARMV8MBL_H_DEPENDANT - -#ifdef __cplusplus -extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES -#ifndef __ARMv8MBL_REV -#define __ARMv8MBL_REV 0x0000U -#warning "__ARMv8MBL_REV not defined in device header file; using default!" -#endif - -#ifndef __FPU_PRESENT -#define __FPU_PRESENT 0U -#warning "__FPU_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __MPU_PRESENT -#define __MPU_PRESENT 0U -#warning "__MPU_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __SAUREGION_PRESENT -#define __SAUREGION_PRESENT 0U -#warning "__SAUREGION_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __VTOR_PRESENT -#define __VTOR_PRESENT 0U -#warning "__VTOR_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __NVIC_PRIO_BITS -#define __NVIC_PRIO_BITS 2U -#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" -#endif - -#ifndef __Vendor_SysTickConfig -#define __Vendor_SysTickConfig 0U -#warning "__Vendor_SysTickConfig not defined in device header file; using default!" -#endif - -#ifndef __ETM_PRESENT -#define __ETM_PRESENT 0U -#warning "__ETM_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __MTB_PRESENT -#define __MTB_PRESENT 0U -#warning "__MTB_PRESENT not defined in device header file; using default!" -#endif - -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus -#define __I volatile /*!< Defines 'read only' permissions */ -#else -#define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group ARMv8MBL */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union { - struct { - uint32_t _reserved0: 28; /*!< bit: 0..27 Reserved */ - uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ - uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union { - struct { - uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union { - struct { - uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */ - uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1: 3; /*!< bit: 25..27 Reserved */ - uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ - uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union { - struct { - uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL: 1; /*!< bit: 1 Stack-pointer select */ - uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct { - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct { - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - uint32_t RESERVED0[6U]; - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct { - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct { - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - uint32_t RESERVED0[7U]; - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#endif -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct { - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED4[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ -#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ -#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ -#define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ -#define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ -#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ -#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ -#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - -#define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ -#define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ -#define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ -#define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ -#define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ -#endif - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifndef CMSIS_NVIC_VIRTUAL -/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for ARMv8-M Baseline */ -/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for ARMv8-M Baseline */ -#define NVIC_EnableIRQ __NVIC_EnableIRQ -#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ -#define NVIC_DisableIRQ __NVIC_DisableIRQ -#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ -#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ -#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -#define NVIC_GetActive __NVIC_GetActive -#define NVIC_SetPriority __NVIC_SetPriority -#define NVIC_GetPriority __NVIC_GetPriority -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifndef CMSIS_VECTAB_VIRTUAL -#define NVIC_SetVector __NVIC_SetVector -#define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else { - SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else { - return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - If VTOR is not present address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t* vectors = (uint32_t*)SCB->VTOR; -#else - uint32_t* vectors = (uint32_t*)0x0U; -#endif - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t* vectors = (uint32_t*)SCB->VTOR; -#else - uint32_t* vectors = (uint32_t*)0x0U; -#endif - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) { /* wait until reset */ - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else { - SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else { - return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_armv8mml.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_armv8mml.h deleted file mode 100644 index 273c3849c..000000000 --- a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_armv8mml.h +++ /dev/null @@ -1,2821 +0,0 @@ -/**************************************************************************//** - * @file core_armv8mml.h - * @brief CMSIS ARMv8MML Core Peripheral Access Layer Header File - * @version V5.0.2 - * @date 07. December 2016 - ******************************************************************************/ -/* - * Copyright (c) 2009-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) -#pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_ARMV8MML_H_GENERIC -#define __CORE_ARMV8MML_H_GENERIC - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_ARMv8MML - @{ - */ - -/* CMSIS ARMv8MML definitions */ -#define __ARMv8MML_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ -#define __ARMv8MML_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ -#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ - __ARMv8MML_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (81U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) -#if defined __TARGET_FPU_VFP -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#if defined __ARM_PCS_VFP -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined ( __GNUC__ ) -#if defined (__VFP_FP__) && !defined(__SOFTFP__) -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined ( __ICCARM__ ) -#if defined __ARMVFP__ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined ( __TI_ARM__ ) -#if defined __TI_VFP_SUPPORT__ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined ( __TASKING__ ) -#if defined __FPU_VFP__ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined ( __CSMC__ ) -#if ( __CSMC__ & 0x400U) -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV8MML_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_ARMV8MML_H_DEPENDANT -#define __CORE_ARMV8MML_H_DEPENDANT - -#ifdef __cplusplus -extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES -#ifndef __ARMv8MML_REV -#define __ARMv8MML_REV 0x0000U -#warning "__ARMv8MML_REV not defined in device header file; using default!" -#endif - -#ifndef __FPU_PRESENT -#define __FPU_PRESENT 0U -#warning "__FPU_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __MPU_PRESENT -#define __MPU_PRESENT 0U -#warning "__MPU_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __SAUREGION_PRESENT -#define __SAUREGION_PRESENT 0U -#warning "__SAUREGION_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __DSP_PRESENT -#define __DSP_PRESENT 0U -#warning "__DSP_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __NVIC_PRIO_BITS -#define __NVIC_PRIO_BITS 3U -#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" -#endif - -#ifndef __Vendor_SysTickConfig -#define __Vendor_SysTickConfig 0U -#warning "__Vendor_SysTickConfig not defined in device header file; using default!" -#endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus -#define __I volatile /*!< Defines 'read only' permissions */ -#else -#define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group ARMv8MML */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union { - struct { - uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */ - uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */ - uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ - uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ - uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union { - struct { - uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union { - struct { - uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0: 7; /*!< bit: 9..15 Reserved */ - uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1: 4; /*!< bit: 20..23 Reserved */ - uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT: 2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ - uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ - uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union { - struct { - uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL: 1; /*!< bit: 1 Stack-pointer select */ - uint32_t FPCA: 1; /*!< bit: 2 Floating-point context active */ - uint32_t SFPA: 1; /*!< bit: 3 Secure floating-point active */ - uint32_t _reserved1: 28; /*!< bit: 4..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ -#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ - -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct { - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED6[580U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct { - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ - uint32_t RESERVED3[92U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - uint32_t RESERVED7[6U]; - __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ - __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ - __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ - __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ - uint32_t RESERVED8[1U]; - __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ -#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ -#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ - -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ -#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ -#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Non-Secure Access Control Register Definitions */ -#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ -#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ - -#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ -#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ - -#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ -#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/* Instruction Tightly-Coupled Memory Control Register Definitions */ -#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ -#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ - -#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ -#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ - -#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ -#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ - -#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ - -/* Data Tightly-Coupled Memory Control Register Definitions */ -#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ -#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ - -#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ -#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ - -#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ -#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ - -#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ - -/* AHBP Control Register Definitions */ -#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ -#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ - -#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ -#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ - -/* L1 Cache Control Register Definitions */ -#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ -#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ - -#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ -#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ - -#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ -#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ - -/* AHBS Control Register Definitions */ -#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ -#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ - -#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ -#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ - -#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ -#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ - -/* Auxiliary Bus Fault Status Register Definitions */ -#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ -#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ - -#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ -#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ - -#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ -#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ - -#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ -#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ - -#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ -#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ - -#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ -#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct { - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ - __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct { - __OM union { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ - uint32_t RESERVED6[4U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Stimulus Port Register Definitions */ -#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ -#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ - -#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ -#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ -#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ - -#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ -#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ - uint32_t RESERVED32[934U]; - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ - uint32_t RESERVED33[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ -#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct { - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct { - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ - __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ - __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ - __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ - uint32_t RESERVED0[1]; - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#else - uint32_t RESERVED0[3]; -#endif - __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/* Secure Fault Status Register Definitions */ -#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ -#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ - -#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ -#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ - -#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ -#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ - -#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ -#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ - -#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ -#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ - -#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ -#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ - -#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ -#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ - -#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ -#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct { - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ -#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ - -#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ -#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ - -#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ -#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ - -#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ -#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ - -#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ -#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ - -#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ -#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ -#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ -#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct { - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED4[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ -#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ -#define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ -#endif - -#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ -#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ -#define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ -#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ -#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ -#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - -#define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ -#define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ -#define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ -#define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ -#define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ -#define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ -#endif - -#define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ -#define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifndef CMSIS_NVIC_VIRTUAL -#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping -#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping -#define NVIC_EnableIRQ __NVIC_EnableIRQ -#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ -#define NVIC_DisableIRQ __NVIC_DisableIRQ -#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ -#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ -#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -#define NVIC_GetActive __NVIC_GetActive -#define NVIC_SetPriority __NVIC_SetPriority -#define NVIC_GetPriority __NVIC_GetPriority -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifndef CMSIS_VECTAB_VIRTUAL -#define NVIC_SetVector __NVIC_SetVector -#define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else { - SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) { - return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else { - return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t* vectors = (uint32_t*)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t* vectors = (uint32_t*)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) { /* wait until reset */ - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Priority Grouping (non-secure) - \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB_NS->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB_NS->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping (non-secure) - \details Reads the priority grouping field from the non-secure NVIC when in secure state. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) -{ - return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else { - SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) { - return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else { - return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) { - return 2U; /* Double + Single precision FPU */ - } - else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { - return 1U; /* Single precision FPU */ - } - else { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) { /* ITM Port #0 enabled */ - while (ITM->PORT[0U].u32 == 0UL) { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } - else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV8MML_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm0.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm0.h deleted file mode 100644 index d06d984b7..000000000 --- a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm0.h +++ /dev/null @@ -1,850 +0,0 @@ -/**************************************************************************//** - * @file core_cm0.h - * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File - * @version V5.0.1 - * @date 25. November 2016 - ******************************************************************************/ -/* - * Copyright (c) 2009-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) -#pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM0_H_GENERIC -#define __CORE_CM0_H_GENERIC - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M0 - @{ - */ - -/* CMSIS CM0 definitions */ -#define __CM0_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ -#define __CM0_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ - __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) -#if defined __TARGET_FPU_VFP -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#if defined __ARM_PCS_VFP -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __GNUC__ ) -#if defined (__VFP_FP__) && !defined(__SOFTFP__) -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __ICCARM__ ) -#if defined __ARMVFP__ -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __TI_ARM__ ) -#if defined __TI_VFP_SUPPORT__ -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __TASKING__ ) -#if defined __FPU_VFP__ -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __CSMC__ ) -#if ( __CSMC__ & 0x400U) -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0_H_DEPENDANT -#define __CORE_CM0_H_DEPENDANT - -#ifdef __cplusplus -extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES -#ifndef __CM0_REV -#define __CM0_REV 0x0000U -#warning "__CM0_REV not defined in device header file; using default!" -#endif - -#ifndef __NVIC_PRIO_BITS -#define __NVIC_PRIO_BITS 2U -#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" -#endif - -#ifndef __Vendor_SysTickConfig -#define __Vendor_SysTickConfig 0U -#warning "__Vendor_SysTickConfig not defined in device header file; using default!" -#endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus -#define __I volatile /*!< Defines 'read only' permissions */ -#else -#define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M0 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union { - struct { - uint32_t _reserved0: 28; /*!< bit: 0..27 Reserved */ - uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ - uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union { - struct { - uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union { - struct { - uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */ - uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1: 3; /*!< bit: 25..27 Reserved */ - uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ - uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union { - struct { - uint32_t _reserved0: 1; /*!< bit: 0 Reserved */ - uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct { - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct { - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - uint32_t RESERVED0; - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifndef CMSIS_NVIC_VIRTUAL -/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0 */ -/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0 */ -#define NVIC_EnableIRQ __NVIC_EnableIRQ -#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ -#define NVIC_DisableIRQ __NVIC_DisableIRQ -#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ -#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ -#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ -#define NVIC_SetPriority __NVIC_SetPriority -#define NVIC_GetPriority __NVIC_GetPriority -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifndef CMSIS_VECTAB_VIRTUAL -#define NVIC_SetVector __NVIC_SetVector -#define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - Address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t* vectors = (uint32_t*)0x0U; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t* vectors = (uint32_t*)0x0U; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) { /* wait until reset */ - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm0plus.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm0plus.h deleted file mode 100644 index ebc43f3a1..000000000 --- a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm0plus.h +++ /dev/null @@ -1,975 +0,0 @@ -/**************************************************************************//** - * @file core_cm0plus.h - * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File - * @version V5.0.1 - * @date 25. November 2016 - ******************************************************************************/ -/* - * Copyright (c) 2009-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) -#pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM0PLUS_H_GENERIC -#define __CORE_CM0PLUS_H_GENERIC - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex-M0+ - @{ - */ - -/* CMSIS CM0+ definitions */ -#define __CM0PLUS_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ -#define __CM0PLUS_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ - __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) -#if defined __TARGET_FPU_VFP -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#if defined __ARM_PCS_VFP -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __GNUC__ ) -#if defined (__VFP_FP__) && !defined(__SOFTFP__) -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __ICCARM__ ) -#if defined __ARMVFP__ -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __TI_ARM__ ) -#if defined __TI_VFP_SUPPORT__ -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __TASKING__ ) -#if defined __FPU_VFP__ -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __CSMC__ ) -#if ( __CSMC__ & 0x400U) -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0PLUS_H_DEPENDANT -#define __CORE_CM0PLUS_H_DEPENDANT - -#ifdef __cplusplus -extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES -#ifndef __CM0PLUS_REV -#define __CM0PLUS_REV 0x0000U -#warning "__CM0PLUS_REV not defined in device header file; using default!" -#endif - -#ifndef __MPU_PRESENT -#define __MPU_PRESENT 0U -#warning "__MPU_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __VTOR_PRESENT -#define __VTOR_PRESENT 0U -#warning "__VTOR_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __NVIC_PRIO_BITS -#define __NVIC_PRIO_BITS 2U -#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" -#endif - -#ifndef __Vendor_SysTickConfig -#define __Vendor_SysTickConfig 0U -#warning "__Vendor_SysTickConfig not defined in device header file; using default!" -#endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus -#define __I volatile /*!< Defines 'read only' permissions */ -#else -#define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex-M0+ */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union { - struct { - uint32_t _reserved0: 28; /*!< bit: 0..27 Reserved */ - uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ - uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union { - struct { - uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union { - struct { - uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */ - uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1: 3; /*!< bit: 25..27 Reserved */ - uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ - uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union { - struct { - uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct { - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct { - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct { - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the Cortex-M0+ header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ -#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifndef CMSIS_NVIC_VIRTUAL -/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0+ */ -/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0+ */ -#define NVIC_EnableIRQ __NVIC_EnableIRQ -#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ -#define NVIC_DisableIRQ __NVIC_DisableIRQ -#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ -#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ -#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ -#define NVIC_SetPriority __NVIC_SetPriority -#define NVIC_GetPriority __NVIC_GetPriority -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifndef CMSIS_VECTAB_VIRTUAL -#define NVIC_SetVector __NVIC_SetVector -#define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - If VTOR is not present address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t* vectors = (uint32_t*)SCB->VTOR; -#else - uint32_t* vectors = (uint32_t*)0x0U; -#endif - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t* vectors = (uint32_t*)SCB->VTOR; -#else - uint32_t* vectors = (uint32_t*)0x0U; -#endif - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; - -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) { /* wait until reset */ - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm23.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm23.h deleted file mode 100644 index 513635a58..000000000 --- a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm23.h +++ /dev/null @@ -1,1813 +0,0 @@ -/**************************************************************************//** - * @file core_cm23.h - * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File - * @version V5.0.1 - * @date 25. November 2016 - ******************************************************************************/ -/* - * Copyright (c) 2009-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) -#pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM23_H_GENERIC -#define __CORE_CM23_H_GENERIC - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M23 - @{ - */ - -/* CMSIS cmGrebe definitions */ -#define __CM23_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ -#define __CM23_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ -#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ - __CM23_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (23U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) -#if defined __TARGET_FPU_VFP -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#if defined __ARM_PCS_VFP -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __GNUC__ ) -#if defined (__VFP_FP__) && !defined(__SOFTFP__) -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __ICCARM__ ) -#if defined __ARMVFP__ -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __TI_ARM__ ) -#if defined __TI_VFP_SUPPORT__ -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __TASKING__ ) -#if defined __FPU_VFP__ -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __CSMC__ ) -#if ( __CSMC__ & 0x400U) -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM23_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM23_H_DEPENDANT -#define __CORE_CM23_H_DEPENDANT - -#ifdef __cplusplus -extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES -#ifndef __CM23_REV -#define __CM23_REV 0x0000U -#warning "__CM23_REV not defined in device header file; using default!" -#endif - -#ifndef __FPU_PRESENT -#define __FPU_PRESENT 0U -#warning "__FPU_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __MPU_PRESENT -#define __MPU_PRESENT 0U -#warning "__MPU_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __SAUREGION_PRESENT -#define __SAUREGION_PRESENT 0U -#warning "__SAUREGION_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __VTOR_PRESENT -#define __VTOR_PRESENT 0U -#warning "__VTOR_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __NVIC_PRIO_BITS -#define __NVIC_PRIO_BITS 2U -#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" -#endif - -#ifndef __Vendor_SysTickConfig -#define __Vendor_SysTickConfig 0U -#warning "__Vendor_SysTickConfig not defined in device header file; using default!" -#endif - -#ifndef __ETM_PRESENT -#define __ETM_PRESENT 0U -#warning "__ETM_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __MTB_PRESENT -#define __MTB_PRESENT 0U -#warning "__MTB_PRESENT not defined in device header file; using default!" -#endif - -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus -#define __I volatile /*!< Defines 'read only' permissions */ -#else -#define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M23 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union { - struct { - uint32_t _reserved0: 28; /*!< bit: 0..27 Reserved */ - uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ - uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union { - struct { - uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union { - struct { - uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */ - uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1: 3; /*!< bit: 25..27 Reserved */ - uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ - uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union { - struct { - uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL: 1; /*!< bit: 1 Stack-pointer select */ - uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct { - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct { - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - uint32_t RESERVED0[6U]; - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct { - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct { - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - uint32_t RESERVED0[7U]; - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#endif -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct { - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED4[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ -#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ -#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ -#define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ -#define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ -#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ -#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ -#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - -#define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ -#define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ -#define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ -#define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ -#define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ -#endif - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifndef CMSIS_NVIC_VIRTUAL -/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ -/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ -#define NVIC_EnableIRQ __NVIC_EnableIRQ -#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ -#define NVIC_DisableIRQ __NVIC_DisableIRQ -#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ -#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ -#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -#define NVIC_GetActive __NVIC_GetActive -#define NVIC_SetPriority __NVIC_SetPriority -#define NVIC_GetPriority __NVIC_GetPriority -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifndef CMSIS_VECTAB_VIRTUAL -#define NVIC_SetVector __NVIC_SetVector -#define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else { - SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else { - return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - If VTOR is not present address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t* vectors = (uint32_t*)SCB->VTOR; -#else - uint32_t* vectors = (uint32_t*)0x0U; -#endif - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t* vectors = (uint32_t*)SCB->VTOR; -#else - uint32_t* vectors = (uint32_t*)0x0U; -#endif - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) { /* wait until reset */ - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else { - SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else { - return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM23_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm3.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm3.h deleted file mode 100644 index 8cbf329b8..000000000 --- a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm3.h +++ /dev/null @@ -1,1880 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V5.0.1 - * @date 30. January 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) -#pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM3_H_GENERIC -#define __CORE_CM3_H_GENERIC - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M3 - @{ - */ - -/* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ - __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (3U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) -#if defined __TARGET_FPU_VFP -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#if defined __ARM_PCS_VFP -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __GNUC__ ) -#if defined (__VFP_FP__) && !defined(__SOFTFP__) -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __ICCARM__ ) -#if defined __ARMVFP__ -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __TI_ARM__ ) -#if defined __TI_VFP_SUPPORT__ -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __TASKING__ ) -#if defined __FPU_VFP__ -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __CSMC__ ) -#if ( __CSMC__ & 0x400U) -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM3_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM3_H_DEPENDANT -#define __CORE_CM3_H_DEPENDANT - -#ifdef __cplusplus -extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES -#ifndef __CM3_REV -#define __CM3_REV 0x0200U -#warning "__CM3_REV not defined in device header file; using default!" -#endif - -#ifndef __MPU_PRESENT -#define __MPU_PRESENT 0U -#warning "__MPU_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __NVIC_PRIO_BITS -#define __NVIC_PRIO_BITS 3U -#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" -#endif - -#ifndef __Vendor_SysTickConfig -#define __Vendor_SysTickConfig 0U -#warning "__Vendor_SysTickConfig not defined in device header file; using default!" -#endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus -#define __I volatile /*!< Defines 'read only' permissions */ -#else -#define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M3 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union { - struct { - uint32_t _reserved0: 27; /*!< bit: 0..26 Reserved */ - uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ - uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ - uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union { - struct { - uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union { - struct { - uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0: 1; /*!< bit: 9 Reserved */ - uint32_t ICI_IT_1: 6; /*!< bit: 10..15 ICI/IT part 1 */ - uint32_t _reserved1: 8; /*!< bit: 16..23 Reserved */ - uint32_t T: 1; /*!< bit: 24 Thumb bit */ - uint32_t ICI_IT_2: 2; /*!< bit: 25..26 ICI/IT part 2 */ - uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ - uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ - uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ -#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ -#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union { - struct { - uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct { - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct { - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ -#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#else -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct { - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ -#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -#else - uint32_t RESERVED1[1U]; -#endif -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct { - __OM union { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct { - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct { - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct { - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ -#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL -#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE -#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" -#endif -#include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else -#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping -#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping -#define NVIC_EnableIRQ __NVIC_EnableIRQ -#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ -#define NVIC_DisableIRQ __NVIC_DisableIRQ -#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ -#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ -#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -#define NVIC_GetActive __NVIC_GetActive -#define NVIC_SetPriority __NVIC_SetPriority -#define NVIC_GetPriority __NVIC_GetPriority -#define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL -#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" -#endif -#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else -#define NVIC_SetVector __NVIC_SetVector -#define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t* vectors = (uint32_t*)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t* vectors = (uint32_t*)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) { /* wait until reset */ - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) { /* ITM Port #0 enabled */ - while (ITM->PORT[0U].u32 == 0UL) { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } - else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM3_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm33.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm33.h deleted file mode 100644 index 00de7795e..000000000 --- a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm33.h +++ /dev/null @@ -1,2821 +0,0 @@ -/**************************************************************************//** - * @file core_cm33.h - * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File - * @version V5.0.2 - * @date 07. December 2016 - ******************************************************************************/ -/* - * Copyright (c) 2009-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) -#pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM33_H_GENERIC -#define __CORE_CM33_H_GENERIC - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M33 - @{ - */ - -/* CMSIS CM33 definitions */ -#define __CM33_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ -#define __CM33_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ -#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ - __CM33_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (33U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) -#if defined __TARGET_FPU_VFP -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#if defined __ARM_PCS_VFP -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined ( __GNUC__ ) -#if defined (__VFP_FP__) && !defined(__SOFTFP__) -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined ( __ICCARM__ ) -#if defined __ARMVFP__ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined ( __TI_ARM__ ) -#if defined __TI_VFP_SUPPORT__ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined ( __TASKING__ ) -#if defined __FPU_VFP__ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined ( __CSMC__ ) -#if ( __CSMC__ & 0x400U) -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM33_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM33_H_DEPENDANT -#define __CORE_CM33_H_DEPENDANT - -#ifdef __cplusplus -extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES -#ifndef __CM33_REV -#define __CM33_REV 0x0000U -#warning "__CM33_REV not defined in device header file; using default!" -#endif - -#ifndef __FPU_PRESENT -#define __FPU_PRESENT 0U -#warning "__FPU_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __MPU_PRESENT -#define __MPU_PRESENT 0U -#warning "__MPU_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __SAUREGION_PRESENT -#define __SAUREGION_PRESENT 0U -#warning "__SAUREGION_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __DSP_PRESENT -#define __DSP_PRESENT 0U -#warning "__DSP_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __NVIC_PRIO_BITS -#define __NVIC_PRIO_BITS 3U -#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" -#endif - -#ifndef __Vendor_SysTickConfig -#define __Vendor_SysTickConfig 0U -#warning "__Vendor_SysTickConfig not defined in device header file; using default!" -#endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus -#define __I volatile /*!< Defines 'read only' permissions */ -#else -#define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M33 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union { - struct { - uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */ - uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */ - uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ - uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ - uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union { - struct { - uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union { - struct { - uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0: 7; /*!< bit: 9..15 Reserved */ - uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1: 4; /*!< bit: 20..23 Reserved */ - uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT: 2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ - uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ - uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union { - struct { - uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL: 1; /*!< bit: 1 Stack-pointer select */ - uint32_t FPCA: 1; /*!< bit: 2 Floating-point context active */ - uint32_t SFPA: 1; /*!< bit: 3 Secure floating-point active */ - uint32_t _reserved1: 28; /*!< bit: 4..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ -#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ - -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct { - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED6[580U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct { - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ - uint32_t RESERVED3[92U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - uint32_t RESERVED7[6U]; - __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ - __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ - __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ - __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ - uint32_t RESERVED8[1U]; - __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ -#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ -#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ - -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ -#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ -#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Non-Secure Access Control Register Definitions */ -#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ -#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ - -#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ -#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ - -#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ -#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/* Instruction Tightly-Coupled Memory Control Register Definitions */ -#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ -#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ - -#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ -#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ - -#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ -#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ - -#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ - -/* Data Tightly-Coupled Memory Control Register Definitions */ -#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ -#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ - -#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ -#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ - -#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ -#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ - -#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ - -/* AHBP Control Register Definitions */ -#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ -#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ - -#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ -#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ - -/* L1 Cache Control Register Definitions */ -#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ -#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ - -#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ -#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ - -#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ -#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ - -/* AHBS Control Register Definitions */ -#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ -#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ - -#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ -#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ - -#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ -#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ - -/* Auxiliary Bus Fault Status Register Definitions */ -#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ -#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ - -#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ -#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ - -#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ -#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ - -#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ -#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ - -#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ -#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ - -#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ -#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct { - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ - __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct { - __OM union { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ - uint32_t RESERVED6[4U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Stimulus Port Register Definitions */ -#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ -#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ - -#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ -#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ -#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ - -#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ -#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ - uint32_t RESERVED32[934U]; - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ - uint32_t RESERVED33[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ -#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct { - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct { - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ - __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ - __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ - __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ - uint32_t RESERVED0[1]; - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#else - uint32_t RESERVED0[3]; -#endif - __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/* Secure Fault Status Register Definitions */ -#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ -#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ - -#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ -#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ - -#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ -#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ - -#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ -#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ - -#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ -#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ - -#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ -#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ - -#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ -#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ - -#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ -#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct { - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ -#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ - -#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ -#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ - -#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ -#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ - -#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ -#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ - -#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ -#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ - -#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ -#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ -#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ -#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct { - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED4[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ -#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ -#define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ -#endif - -#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ -#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ -#define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ -#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ -#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ -#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - -#define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ -#define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ -#define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ -#define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ -#define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ -#define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ -#endif - -#define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ -#define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifndef CMSIS_NVIC_VIRTUAL -#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping -#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping -#define NVIC_EnableIRQ __NVIC_EnableIRQ -#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ -#define NVIC_DisableIRQ __NVIC_DisableIRQ -#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ -#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ -#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -#define NVIC_GetActive __NVIC_GetActive -#define NVIC_SetPriority __NVIC_SetPriority -#define NVIC_GetPriority __NVIC_GetPriority -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifndef CMSIS_VECTAB_VIRTUAL -#define NVIC_SetVector __NVIC_SetVector -#define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else { - SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) { - return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else { - return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t* vectors = (uint32_t*)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t* vectors = (uint32_t*)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) { /* wait until reset */ - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Priority Grouping (non-secure) - \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB_NS->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB_NS->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping (non-secure) - \details Reads the priority grouping field from the non-secure NVIC when in secure state. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) -{ - return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else { - SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) { - return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else { - return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) { - return 2U; /* Double + Single precision FPU */ - } - else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { - return 1U; /* Single precision FPU */ - } - else { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) { /* ITM Port #0 enabled */ - while (ITM->PORT[0U].u32 == 0UL) { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } - else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM33_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm4.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm4.h deleted file mode 100644 index f4c8011f8..000000000 --- a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm4.h +++ /dev/null @@ -1,2061 +0,0 @@ -/**************************************************************************//** - * @file core_cm4.h - * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V5.0.1 - * @date 30. January 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) -#pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM4_H_GENERIC -#define __CORE_CM4_H_GENERIC - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M4 - @{ - */ - -/* CMSIS CM4 definitions */ -#define __CM4_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ -#define __CM4_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ -#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ - __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (4U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) -#if defined __TARGET_FPU_VFP -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#if defined __ARM_PCS_VFP -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined ( __GNUC__ ) -#if defined (__VFP_FP__) && !defined(__SOFTFP__) -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined ( __ICCARM__ ) -#if defined __ARMVFP__ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined ( __TI_ARM__ ) -#if defined __TI_VFP_SUPPORT__ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined ( __TASKING__ ) -#if defined __FPU_VFP__ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined ( __CSMC__ ) -#if ( __CSMC__ & 0x400U) -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM4_H_DEPENDANT -#define __CORE_CM4_H_DEPENDANT - -#ifdef __cplusplus -extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES -#ifndef __CM4_REV -#define __CM4_REV 0x0000U -#warning "__CM4_REV not defined in device header file; using default!" -#endif - -#ifndef __FPU_PRESENT -#define __FPU_PRESENT 0U -#warning "__FPU_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __MPU_PRESENT -#define __MPU_PRESENT 0U -#warning "__MPU_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __NVIC_PRIO_BITS -#define __NVIC_PRIO_BITS 3U -#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" -#endif - -#ifndef __Vendor_SysTickConfig -#define __Vendor_SysTickConfig 0U -#warning "__Vendor_SysTickConfig not defined in device header file; using default!" -#endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus -#define __I volatile /*!< Defines 'read only' permissions */ -#else -#define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M4 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union { - struct { - uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */ - uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */ - uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ - uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ - uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union { - struct { - uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union { - struct { - uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0: 1; /*!< bit: 9 Reserved */ - uint32_t ICI_IT_1: 6; /*!< bit: 10..15 ICI/IT part 1 */ - uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1: 4; /*!< bit: 20..23 Reserved */ - uint32_t T: 1; /*!< bit: 24 Thumb bit */ - uint32_t ICI_IT_2: 2; /*!< bit: 25..26 ICI/IT part 2 */ - uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ - uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ - uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ -#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ -#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union { - struct { - uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA: 1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0: 29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct { - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct { - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct { - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ -#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ - -#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ -#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct { - __OM union { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct { - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct { - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct { - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct { - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ -#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ -#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL -#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE -#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" -#endif -#include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else -#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping -#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping -#define NVIC_EnableIRQ __NVIC_EnableIRQ -#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ -#define NVIC_DisableIRQ __NVIC_DisableIRQ -#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ -#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ -#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -#define NVIC_GetActive __NVIC_GetActive -#define NVIC_SetPriority __NVIC_SetPriority -#define NVIC_GetPriority __NVIC_GetPriority -#define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL -#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" -#endif -#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else -#define NVIC_SetVector __NVIC_SetVector -#define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t* vectors = (uint32_t*)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t* vectors = (uint32_t*)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) { /* wait until reset */ - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { - return 1U; /* Single precision FPU */ - } - else { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) { /* ITM Port #0 enabled */ - while (ITM->PORT[0U].u32 == 0UL) { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } - else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm7.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm7.h deleted file mode 100644 index c09acc824..000000000 --- a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm7.h +++ /dev/null @@ -1,2592 +0,0 @@ -/**************************************************************************//** - * @file core_cm7.h - * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File - * @version V5.0.1 - * @date 25. November 2016 - ******************************************************************************/ -/* - * Copyright (c) 2009-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) -#pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM7_H_GENERIC -#define __CORE_CM7_H_GENERIC - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M7 - @{ - */ - -/* CMSIS CM7 definitions */ -#define __CM7_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ -#define __CM7_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ -#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ - __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (7U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) -#if defined __TARGET_FPU_VFP -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#if defined __ARM_PCS_VFP -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined ( __GNUC__ ) -#if defined (__VFP_FP__) && !defined(__SOFTFP__) -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined ( __ICCARM__ ) -#if defined __ARMVFP__ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined ( __TI_ARM__ ) -#if defined __TI_VFP_SUPPORT__ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined ( __TASKING__ ) -#if defined __FPU_VFP__ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#elif defined ( __CSMC__ ) -#if ( __CSMC__ & 0x400U) -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -#define __FPU_USED 1U -#else -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#define __FPU_USED 0U -#endif -#else -#define __FPU_USED 0U -#endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM7_H_DEPENDANT -#define __CORE_CM7_H_DEPENDANT - -#ifdef __cplusplus -extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES -#ifndef __CM7_REV -#define __CM7_REV 0x0000U -#warning "__CM7_REV not defined in device header file; using default!" -#endif - -#ifndef __FPU_PRESENT -#define __FPU_PRESENT 0U -#warning "__FPU_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __MPU_PRESENT -#define __MPU_PRESENT 0U -#warning "__MPU_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __ICACHE_PRESENT -#define __ICACHE_PRESENT 0U -#warning "__ICACHE_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __DCACHE_PRESENT -#define __DCACHE_PRESENT 0U -#warning "__DCACHE_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __DTCM_PRESENT -#define __DTCM_PRESENT 0U -#warning "__DTCM_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __NVIC_PRIO_BITS -#define __NVIC_PRIO_BITS 3U -#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" -#endif - -#ifndef __Vendor_SysTickConfig -#define __Vendor_SysTickConfig 0U -#warning "__Vendor_SysTickConfig not defined in device header file; using default!" -#endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus -#define __I volatile /*!< Defines 'read only' permissions */ -#else -#define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M7 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union { - struct { - uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */ - uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */ - uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ - uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ - uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union { - struct { - uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union { - struct { - uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0: 1; /*!< bit: 9 Reserved */ - uint32_t ICI_IT_1: 6; /*!< bit: 10..15 ICI/IT part 1 */ - uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1: 4; /*!< bit: 20..23 Reserved */ - uint32_t T: 1; /*!< bit: 24 Thumb bit */ - uint32_t ICI_IT_2: 2; /*!< bit: 25..26 ICI/IT part 2 */ - uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ - uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ - uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ -#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ -#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union { - struct { - uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA: 1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0: 29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct { - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct { - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[1U]; - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - uint32_t RESERVED3[93U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - uint32_t RESERVED7[6U]; - __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ - __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ - __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ - __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ - uint32_t RESERVED8[1U]; - __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ - -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/* Instruction Tightly-Coupled Memory Control Register Definitions */ -#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ -#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ - -#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ -#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ - -#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ -#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ - -#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ - -/* Data Tightly-Coupled Memory Control Register Definitions */ -#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ -#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ - -#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ -#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ - -#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ -#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ - -#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ - -/* AHBP Control Register Definitions */ -#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ -#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ - -#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ -#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ - -/* L1 Cache Control Register Definitions */ -#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ -#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ - -#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ -#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ - -#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ -#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ - -/* AHBS Control Register Definitions */ -#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ -#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ - -#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ -#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ - -#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ -#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ - -/* Auxiliary Bus Fault Status Register Definitions */ -#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ -#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ - -#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ -#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ - -#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ -#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ - -#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ -#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ - -#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ -#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ - -#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ -#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct { - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ - -#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ -#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ - -#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ -#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct { - __OM union { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED3[981U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct { - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct { - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct { - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/* Media and FP Feature Register 2 Definitions */ - -/*@} end of group CMSIS_FPU */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct { - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ -#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ -#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifndef CMSIS_NVIC_VIRTUAL -#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping -#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping -#define NVIC_EnableIRQ __NVIC_EnableIRQ -#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ -#define NVIC_DisableIRQ __NVIC_DisableIRQ -#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ -#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ -#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -#define NVIC_GetActive __NVIC_GetActive -#define NVIC_SetPriority __NVIC_SetPriority -#define NVIC_GetPriority __NVIC_GetPriority -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifndef CMSIS_VECTAB_VIRTUAL -#define NVIC_SetVector __NVIC_SetVector -#define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else { - SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else { - return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t* vectors = (uint32_t*)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t* vectors = (uint32_t*)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) { /* wait until reset */ - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = SCB->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) { - return 2U; /* Double + Single precision FPU */ - } - else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { - return 1U; /* Single precision FPU */ - } - else { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## Cache functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_CacheFunctions Cache Functions - \brief Functions that configure Instruction and Data cache. - @{ - */ - -/* Cache Size ID Register Macros */ -#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) -#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) - - -/** - \brief Enable I-Cache - \details Turns on I-Cache - */ -__STATIC_INLINE void SCB_EnableICache (void) -{ -#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - __DSB(); - __ISB(); - SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ - __DSB(); - __ISB(); -#endif -} - - -/** - \brief Disable I-Cache - \details Turns off I-Cache - */ -__STATIC_INLINE void SCB_DisableICache (void) -{ -#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - __DSB(); - __ISB(); -#endif -} - - -/** - \brief Invalidate I-Cache - \details Invalidates I-Cache - */ -__STATIC_INLINE void SCB_InvalidateICache (void) -{ -#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; - __DSB(); - __ISB(); -#endif -} - - -/** - \brief Enable D-Cache - \details Turns on D-Cache - */ -__STATIC_INLINE void SCB_EnableDCache (void) -{ -#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); -#if defined ( __CC_ARM ) - __schedule_barrier(); -#endif - } while (ways-- != 0U); - } while(sets-- != 0U); - __DSB(); - - SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ - - __DSB(); - __ISB(); -#endif -} - - -/** - \brief Disable D-Cache - \details Turns off D-Cache - */ -__STATIC_INLINE void SCB_DisableDCache (void) -{ -#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - register uint32_t ccsidr; - register uint32_t sets; - register uint32_t ways; - - SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ - __DSB(); - - SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); -#if defined ( __CC_ARM ) - __schedule_barrier(); -#endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); -#endif -} - - -/** - \brief Invalidate D-Cache - \details Invalidates D-Cache - */ -__STATIC_INLINE void SCB_InvalidateDCache (void) -{ -#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); -#if defined ( __CC_ARM ) - __schedule_barrier(); -#endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); -#endif -} - - -/** - \brief Clean D-Cache - \details Cleans D-Cache - */ -__STATIC_INLINE void SCB_CleanDCache (void) -{ -#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | - ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); -#if defined ( __CC_ARM ) - __schedule_barrier(); -#endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); -#endif -} - - -/** - \brief Clean & Invalidate D-Cache - \details Cleans and Invalidates D-Cache - */ -__STATIC_INLINE void SCB_CleanInvalidateDCache (void) -{ -#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); -#if defined ( __CC_ARM ) - __schedule_barrier(); -#endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); -#endif -} - - -/** - \brief D-Cache Invalidate by address - \details Invalidates D-Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t* addr, int32_t dsize) -{ -#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t)addr; - int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCIMVAC = op_addr; - op_addr += (uint32_t)linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); -#endif -} - - -/** - \brief D-Cache Clean by address - \details Cleans D-Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t* addr, int32_t dsize) -{ -#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t) addr; - int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCCMVAC = op_addr; - op_addr += (uint32_t)linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); -#endif -} - - -/** - \brief D-Cache Clean and Invalidate by address - \details Cleans and invalidates D_Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t* addr, int32_t dsize) -{ -#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t) addr; - int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCCIMVAC = op_addr; - op_addr += (uint32_t)linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); -#endif -} - - -/*@} end of CMSIS_Core_CacheFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) { /* ITM Port #0 enabled */ - while (ITM->PORT[0U].u32 == 0UL) { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } - else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_sc000.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_sc000.h deleted file mode 100644 index ed1063364..000000000 --- a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_sc000.h +++ /dev/null @@ -1,976 +0,0 @@ -/**************************************************************************//** - * @file core_sc000.h - * @brief CMSIS SC000 Core Peripheral Access Layer Header File - * @version V5.0.1 - * @date 25. November 2016 - ******************************************************************************/ -/* - * Copyright (c) 2009-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) -#pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_SC000_H_GENERIC -#define __CORE_SC000_H_GENERIC - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup SC000 - @{ - */ - -/* CMSIS SC000 definitions */ -#define __SC000_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ -#define __SC000_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ -#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ - __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_SC (000U) /*!< Cortex secure core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) -#if defined __TARGET_FPU_VFP -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#if defined __ARM_PCS_VFP -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __GNUC__ ) -#if defined (__VFP_FP__) && !defined(__SOFTFP__) -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __ICCARM__ ) -#if defined __ARMVFP__ -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __TI_ARM__ ) -#if defined __TI_VFP_SUPPORT__ -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __TASKING__ ) -#if defined __FPU_VFP__ -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __CSMC__ ) -#if ( __CSMC__ & 0x400U) -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC000_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC000_H_DEPENDANT -#define __CORE_SC000_H_DEPENDANT - -#ifdef __cplusplus -extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES -#ifndef __SC000_REV -#define __SC000_REV 0x0000U -#warning "__SC000_REV not defined in device header file; using default!" -#endif - -#ifndef __MPU_PRESENT -#define __MPU_PRESENT 0U -#warning "__MPU_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __NVIC_PRIO_BITS -#define __NVIC_PRIO_BITS 2U -#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" -#endif - -#ifndef __Vendor_SysTickConfig -#define __Vendor_SysTickConfig 0U -#warning "__Vendor_SysTickConfig not defined in device header file; using default!" -#endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus -#define __I volatile /*!< Defines 'read only' permissions */ -#else -#define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group SC000 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union { - struct { - uint32_t _reserved0: 28; /*!< bit: 0..27 Reserved */ - uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ - uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union { - struct { - uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union { - struct { - uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */ - uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1: 3; /*!< bit: 25..27 Reserved */ - uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ - uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union { - struct { - uint32_t _reserved0: 1; /*!< bit: 0 Reserved */ - uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct { - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct { - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - uint32_t RESERVED1[154U]; - __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct { - uint32_t RESERVED0[2U]; - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct { - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the SC000 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ -#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifndef CMSIS_NVIC_VIRTUAL -/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ -/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ -#define NVIC_EnableIRQ __NVIC_EnableIRQ -#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ -#define NVIC_DisableIRQ __NVIC_DisableIRQ -#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ -#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ -#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ -#define NVIC_SetPriority __NVIC_SetPriority -#define NVIC_GetPriority __NVIC_GetPriority -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifndef CMSIS_VECTAB_VIRTUAL -#define NVIC_SetVector __NVIC_SetVector -#define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t* vectors = (uint32_t*)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t* vectors = (uint32_t*)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) { /* wait until reset */ - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC000_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_sc300.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_sc300.h deleted file mode 100644 index a1b17e1ce..000000000 --- a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_sc300.h +++ /dev/null @@ -1,1851 +0,0 @@ -/**************************************************************************//** - * @file core_sc300.h - * @brief CMSIS SC300 Core Peripheral Access Layer Header File - * @version V5.0.1 - * @date 25. November 2016 - ******************************************************************************/ -/* - * Copyright (c) 2009-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) -#pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_SC300_H_GENERIC -#define __CORE_SC300_H_GENERIC - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup SC3000 - @{ - */ - -/* CMSIS SC300 definitions */ -#define __SC300_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ -#define __SC300_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ -#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ - __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_SC (300U) /*!< Cortex secure core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) -#if defined __TARGET_FPU_VFP -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#if defined __ARM_PCS_VFP -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __GNUC__ ) -#if defined (__VFP_FP__) && !defined(__SOFTFP__) -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __ICCARM__ ) -#if defined __ARMVFP__ -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __TI_ARM__ ) -#if defined __TI_VFP_SUPPORT__ -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __TASKING__ ) -#if defined __FPU_VFP__ -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#elif defined ( __CSMC__ ) -#if ( __CSMC__ & 0x400U) -#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -#endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC300_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC300_H_DEPENDANT -#define __CORE_SC300_H_DEPENDANT - -#ifdef __cplusplus -extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES -#ifndef __SC300_REV -#define __SC300_REV 0x0000U -#warning "__SC300_REV not defined in device header file; using default!" -#endif - -#ifndef __MPU_PRESENT -#define __MPU_PRESENT 0U -#warning "__MPU_PRESENT not defined in device header file; using default!" -#endif - -#ifndef __NVIC_PRIO_BITS -#define __NVIC_PRIO_BITS 3U -#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" -#endif - -#ifndef __Vendor_SysTickConfig -#define __Vendor_SysTickConfig 0U -#warning "__Vendor_SysTickConfig not defined in device header file; using default!" -#endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus -#define __I volatile /*!< Defines 'read only' permissions */ -#else -#define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group SC300 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union { - struct { - uint32_t _reserved0: 27; /*!< bit: 0..26 Reserved */ - uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ - uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ - uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union { - struct { - uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union { - struct { - uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0: 1; /*!< bit: 9 Reserved */ - uint32_t ICI_IT_1: 6; /*!< bit: 10..15 ICI/IT part 1 */ - uint32_t _reserved1: 8; /*!< bit: 16..23 Reserved */ - uint32_t T: 1; /*!< bit: 24 Thumb bit */ - uint32_t ICI_IT_2: 2; /*!< bit: 25..26 ICI/IT part 2 */ - uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ - uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ - uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ -#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ -#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union { - struct { - uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct { - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct { - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - uint32_t RESERVED1[129U]; - __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct { - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - uint32_t RESERVED1[1U]; -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct { - __OM union { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct { - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct { - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct { - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ -#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifndef CMSIS_NVIC_VIRTUAL -#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping -#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping -#define NVIC_EnableIRQ __NVIC_EnableIRQ -#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ -#define NVIC_DisableIRQ __NVIC_DisableIRQ -#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ -#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ -#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -#define NVIC_GetActive __NVIC_GetActive -#define NVIC_SetPriority __NVIC_SetPriority -#define NVIC_GetPriority __NVIC_GetPriority -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifndef CMSIS_VECTAB_VIRTUAL -#define NVIC_SetVector __NVIC_SetVector -#define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) { - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t* vectors = (uint32_t*)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t* vectors = (uint32_t*)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) { /* wait until reset */ - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) { /* ITM Port #0 enabled */ - while (ITM->PORT[0U].u32 == 0UL) { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } - else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC300_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/tz_context.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/tz_context.h deleted file mode 100644 index cd6d8ab07..000000000 --- a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/tz_context.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (c) 2015-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * ---------------------------------------------------------------------------- - * - * $Date: 21. September 2016 - * $Revision: V1.0 - * - * Project: TrustZone for ARMv8-M - * Title: Context Management for ARMv8-M TrustZone - * - * Version 1.0 - * Initial Release - *---------------------------------------------------------------------------*/ - -#ifndef TZ_CONTEXT_H -#define TZ_CONTEXT_H - -#include - -#ifndef TZ_MODULEID_T -#define TZ_MODULEID_T -/// \details Data type that identifies secure software modules called by a process. -typedef uint32_t TZ_ModuleId_t; -#endif - -/// \details TZ Memory ID identifies an allocated memory slot. -typedef uint32_t TZ_MemoryId_t; - -/// Initialize secure context memory system -/// \return execution status (1: success, 0: error) -uint32_t TZ_InitContextSystem_S (void); - -/// Allocate context memory for calling secure software modules in TrustZone -/// \param[in] module identifies software modules called from non-secure mode -/// \return value != 0 id TrustZone memory slot identifier -/// \return value 0 no memory available or internal error -TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); - -/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); - -/// Load secure context (called on RTOS thread context switch) -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); - -/// Store secure context (called on RTOS thread context switch) -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); - -#endif // TZ_CONTEXT_H diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/dtype.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/dtype.h deleted file mode 100644 index c77078936..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/dtype.h +++ /dev/null @@ -1,33 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file: dtype.h -/// @author AE TEAM -/// @brief Define the data types to be used in the project, including the function -/// library and application code. Use the data types defined in this file. -//////////////////////////////////////////////////////////////////////////////// -#ifndef __DTYPE_H -#define __DTYPE_H //This is done to avoid including the header file repeatedly in the same file - - -//Defines the read and write characteristics of data, which is often used for storage limits of peripheral registers -#ifndef __I -#define __I volatile const //only read -#endif -#ifndef __O -#define __O volatile //only write -#endif -#ifndef __IO -#define __IO volatile //read write -#endif - -//Common data type definitions - -typedef unsigned char int8u; //haven't symbol8 bit integer variable -typedef signed char int8s; //have symbol8 bit integer variable -typedef unsigned short int16u; //haven't symbol16 bit integer variable -typedef signed short int16s; //have symbol16 bit integer variable -typedef unsigned int int32u; //haven't symbol32 bit integer variable -typedef signed int int32s; //have symbol32 bit integer variable -typedef float fp32; //Single-precision floating-point number (32-bit length) -typedef double fp64; //Double-precision floating-point number (64-bit length) - -#endif //__DTYPE_H diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_adc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_adc.h deleted file mode 100644 index dc0aa3d67..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_adc.h +++ /dev/null @@ -1,341 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_adc.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE ADC -/// FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#ifndef __HAL_ADC_H -#define __HAL_ADC_H - -// Files includes -#include "types.h" -#include "reg_adc.h" - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup ADC_HAL -/// @brief ADC HAL modules -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup ADC_Exported_Types -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ADC_Channels -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - ADC_Channel_0 = 0x00, ///< ADC Channel 0 - ADC_Channel_1 = 0x01, ///< ADC Channel 1 - ADC_Channel_2 = 0x02, ///< ADC Channel 2 - ADC_Channel_3 = 0x03, ///< ADC Channel 3 - ADC_Channel_4 = 0x04, ///< ADC Channel 4 - ADC_Channel_5 = 0x05, ///< ADC Channel 5 - ADC_Channel_6 = 0x06, ///< ADC Channel 6 - ADC_Channel_7 = 0x07, ///< ADC Channel 7 - - ADC_Channel_8 = 0x08, ///< ADC Channel 8 - ADC_Channel_9 = 0x09, ///< ADC Channel 9 - ADC_Channel_10 = 0x0A, ///< ADC Channel 10 - ADC_Channel_11 = 0x0B, ///< ADC Channel 11 - ADC_Channel_12 = 0x0C, ///< ADC Channel 12 - ADC_Channel_13 = 0x0D, ///< ADC Channel 13 - ADC_Channel_14 = 0x0E, ///< ADC Channel 14 - ADC_Channel_15 = 0x0F, ///< ADC Channel 15 - ADC_Channel_TempSensor = 0x0E, ///< Temperature sensor channel(ADC1) - ADC_Channel_VoltReference = 0x0F, ///< Internal reference voltage channel(ADC1) - ADC_Channel_Vrefint = 0x0F, ///< Internal reference voltage channel(ADC1) - -} ADCCHANNEL_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ADC_Sampling_Times -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - ADC_Samctl_1_5 = ADC_SMPR1_SAMCTL0_2_5, ///< ADC sample time select 1.5t - ADC_Samctl_2_5 = ADC_SMPR1_SAMCTL0_2_5, ///< ADC sample time select 2.5t - ADC_Samctl_3_5 = ADC_SMPR1_SAMCTL0_3_5, ///< ADC sample time select 3.5t - ADC_Samctl_4_5 = ADC_SMPR1_SAMCTL0_4_5, ///< ADC sample time select 4.5t - ADC_Samctl_5_5 = ADC_SMPR1_SAMCTL0_5_5, ///< ADC sample time select 5.5t - ADC_Samctl_6_5 = ADC_SMPR1_SAMCTL0_6_5, ///< ADC sample time select 6.5t - ADC_Samctl_7_5 = ADC_SMPR1_SAMCTL0_7_5, ///< ADC sample time select 7.5t - ADC_Samctl_8_5 = ADC_SMPR1_SAMCTL0_8_5, ///< ADC sample time select 7.5t - ADC_Samctl_13_5 = ADC_SMPR1_SAMCTL0_14_5, ///< ADC sample time select 13.5t - ADC_Samctl_14_5 = ADC_SMPR1_SAMCTL0_14_5, ///< ADC sample time select 14.5t - ADC_Samctl_28_5 = ADC_SMPR1_SAMCTL0_29_5, ///< ADC sample time select 28.5t - ADC_Samctl_29_5 = ADC_SMPR1_SAMCTL0_29_5, ///< ADC sample time select 29.5t - ADC_Samctl_41_5 = ADC_SMPR1_SAMCTL0_42_5, ///< ADC sample time select 41.5t - ADC_Samctl_42_5 = ADC_SMPR1_SAMCTL0_42_5, ///< ADC sample time select 42.5t - ADC_Samctl_55_5 = ADC_SMPR1_SAMCTL0_56_5, ///< ADC sample time select 55.5t - ADC_Samctl_56_5 = ADC_SMPR1_SAMCTL0_56_5, ///< ADC sample time select 56.5t - ADC_Samctl_71_5 = ADC_SMPR1_SAMCTL0_72_5, ///< ADC sample time select 71.5t - ADC_Samctl_72_5 = ADC_SMPR1_SAMCTL0_72_5, ///< ADC sample time select 72.5t - ADC_Samctl_239_5 = ADC_SMPR1_SAMCTL0_240_5, ///< ADC sample time select 239.5t - ADC_Samctl_240_5 = ADC_SMPR1_SAMCTL0_240_5 ///< ADC sample time select 240.5t -} ADCSAM_TypeDef; -//////////////////////////////////////////////////////////////////////////////// -/// @brief ADC_Resolution -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - ADC_Resolution_12b = ADC_CFGR_RSLTCTL_12, ///< ADC resolution select 12bit - ADC_Resolution_11b = ADC_CFGR_RSLTCTL_11, ///< ADC resolution select 11bit - ADC_Resolution_10b = ADC_CFGR_RSLTCTL_10, ///< ADC resolution select 10bit - ADC_Resolution_9b = ADC_CFGR_RSLTCTL_9, ///< ADC resolution select 9bit - ADC_Resolution_8b = ADC_CFGR_RSLTCTL_8 ///< ADC resolution select 8bit -} ADCRSL_TypeDef; -/// @brief ADC_Prescare -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - ADC_PCLK2_PRESCARE_3 = ADC_CFGR_PRE_3, ///< ADC preclk 3 - ADC_PCLK2_PRESCARE_5 = ADC_CFGR_PRE_5, ///< ADC preclk 5 - ADC_PCLK2_PRESCARE_7 = ADC_CFGR_PRE_7, ///< ADC preclk 7 - ADC_PCLK2_PRESCARE_9 = ADC_CFGR_PRE_9, ///< ADC preclk 9 - ADC_PCLK2_PRESCARE_11 = ADC_CFGR_PRE_11, ///< ADC preclk 11 - ADC_PCLK2_PRESCARE_13 = ADC_CFGR_PRE_13, ///< ADC preclk 13 - ADC_PCLK2_PRESCARE_15 = ADC_CFGR_PRE_15, ///< ADC preclk 15 - ADC_PCLK2_PRESCARE_17 = ADC_CFGR_PRE_17, ///< ADC preclk 17 - - ADC_PCLK2_PRESCARE_2 = ADC_CFGR_PRE_2, ///< ADC preclk 2 - ADC_PCLK2_PRESCARE_4 = ADC_CFGR_PRE_4, ///< ADC preclk 4 - ADC_PCLK2_PRESCARE_6 = ADC_CFGR_PRE_6, ///< ADC preclk 6 - ADC_PCLK2_PRESCARE_8 = ADC_CFGR_PRE_8, ///< ADC preclk 8 - ADC_PCLK2_PRESCARE_10 = ADC_CFGR_PRE_10, ///< ADC preclk 10 - ADC_PCLK2_PRESCARE_12 = ADC_CFGR_PRE_12, ///< ADC preclk 12 - ADC_PCLK2_PRESCARE_14 = ADC_CFGR_PRE_14, ///< ADC preclk 14 - ADC_PCLK2_PRESCARE_16 = ADC_CFGR_PRE_16 ///< ADC preclk 16 -} ADCPRE_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ADC_Conversion_Mode -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - ADC_Mode_Imm = ADC_CR_IMM, ///< ADC single convert mode - ADC_Mode_Scan = ADC_CR_SCAN, ///< ADC single period convert mode - ADC_Mode_Continue = ADC_CR_CONTINUE ///< ADC continue scan convert mode -} ADCMODE_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ADC_Extrenal_Trigger_Sources_For_Regular_Channels_Conversion -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - ADC1_ExternalTrigConv_T1_CC1 = ADC_CR_T1_CC1, - ADC1_ExternalTrigConv_T1_CC2 = ADC_CR_T1_CC2, - ADC1_ExternalTrigConv_T1_CC3 = ADC_CR_T1_CC3, - ADC1_ExternalTrigConv_T2_CC2 = ADC_CR_T2_CC2, - ADC1_ExternalTrigConv_T3_TRIG = ADC_CR_T3_TRIG, - ADC1_ExternalTrigConv_T3_CC1 = ADC_CR_T3_CC1, - ADC1_ExternalTrigConv_EXTI_11 = ADC_CR_EXTI_11, - ADC1_ExternalTrigConv_T1_CC4_CC5 = ADC_CR_T1_CC4_CC5, - ADC1_ExternalTrigConv_T1_TRIG = ADC_CR_T1_TRIG, - ADC1_ExternalTrigConv_T8_CC4 = ADC_CR_T8_CC4, - ADC1_ExternalTrigConv_T8_CC4_CC5 = ADC_CR_T8_CC4_CC5, - ADC1_ExternalTrigConv_T2_CC1 = ADC_CR_T2_CC1, - ADC1_ExternalTrigConv_T3_CC4 = ADC_CR_T3_CC4, - ADC1_ExternalTrigConv_T2_TRIG = ADC_CR_T2_TRIG, - ADC1_ExternalTrigConv_T8_CC5 = ADC_CR_T8_CC5, - ADC1_ExternalTrigConv_EXTI_15 = ADC_CR_EXTI_15, - ADC1_ExternalTrigConv_T1_CC4 = ADC_CR_TIM1_CC4, - ADC1_ExternalTrigConv_T1_CC5 = ADC_CR_TIM1_CC5 -} EXTERTRIG_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ADC_Data_Align -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - ADC_DataAlign_Right = ADC_CR_RIGHT, ///< ADC data left align - ADC_DataAlign_Left = ADC_CR_LEFT ///< ADC data right align -} ADCDATAALI_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ADC_Flags_Definition -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - ADC_IT_EOC = 1, ///< ADC conversion flag - ADC_FLAG_EOC = 1, - ADC_IT_AWD = 2, ///< ADC window comparator flag - ADC_FLAG_AWD = 2 -} ADCFLAG_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ADC_Trig_Edge -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - ADC_ADC_Trig_Edge_Dual = ADC_CR_TRG_EDGE_DUAL, ///< ADC trig edge dual mode down and up - ADC_ADC_Trig_Edge_Down = ADC_CR_TRG_EDGE_DOWN, ///< ADC trig edge single mode down - ADC_ADC_Trig_Edge_Up = ADC_CR_TRG_EDGE_UP, ///< ADC trig edge single mode up - ADC_ADC_Trig_Edge_Mask = ADC_CR_TRG_EDGE_MASK ///< ADC trig edge is mask, not allowed -} ADCTRIGEDGE_TypeDef; - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ADC_Scan_Direct -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - ADC_Scan_Direct_Up = ADC_CR_SCANDIR, ///< ADC scan from low channel to high channel - ADC_Scan_Direct_Down = 0 ///< ADC scan from High channel to low channel -} ADCSCANDIRECT_TypeDef; -//////////////////////////////////////////////////////////////////////////////// -/// @brief ADC_Trig_Shift -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - ADC_ADC_Trig_Shift_0 = ADC_CR_TRGSHIFT_0, ///< ADC trig shift bit is 0 - ADC_ADC_Trig_Shift_4 = ADC_CR_TRGSHIFT_4, ///< ADC trig shift bit is 4 - ADC_ADC_Trig_Shift_16 = ADC_CR_TRGSHIFT_16, ///< ADC trig shift bit is 16 - ADC_ADC_Trig_Shift_32 = ADC_CR_TRGSHIFT_32, ///< ADC trig shift bit is 32 - ADC_ADC_Trig_Shift_64 = ADC_CR_TRGSHIFT_64, ///< ADC trig shift bit is 64 - ADC_ADC_Trig_Shift_128 = ADC_CR_TRGSHIFT_128, ///< ADC trig shift bit is 128 - ADC_ADC_Trig_Shift_256 = ADC_CR_TRGSHIFT_256, ///< ADC trig shift bit is 256 - ADC_ADC_Trig_Shift_512 = ADC_CR_TRGSHIFT_512, ///< ADC trig shift bit is 512 -} ADCTRIGSHIFT_TypeDef; -//////////////////////////////////////////////////////////////////////////////// -/// @brief ADC_Inject_Sequence_Length the sequencer length for injected channels -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - ADC_Inject_Seqen_Len1 = 0, ///< ADC Injected Seqence length is 1 - ADC_Inject_Seqen_Len2 = 1, ///< ADC Injected Seqence length is 2 - ADC_Inject_Seqen_Len3 = 2, ///< ADC Injected Seqence length is 3 - ADC_Inject_Seqen_Len4 = 3, ///< ADC Injected Seqence length is 4 -} ADC_INJ_SEQ_LEN_TypeDef; -//////////////////////////////////////////////////////////////////////////////// -/// @brief ADC_Inject_Sequence_Length the sequencer length for injected channels -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - ADC_InjectedChannel_1 = 0x00, - ADC_InjectedChannel_2 = 0x04, - ADC_InjectedChannel_3 = 0x08, - ADC_InjectedChannel_4 = 0x0c, -} ADC_INJ_SEQ_Channel_TypeDef; -//////////////////////////////////////////////////////////////////////////////// -/// @brief ADC_Extrenal_Trigger_Sources_For_Regular_Channels_Conversion -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - ADC1_InjectExtTrigSrc_T1_TRGO = ADC_ANY_CR_JTRGSEL_TIM1_TRGO, ///< TIM1 TRGO - ADC1_InjectExtTrigSrc_T1_CC4 = ADC_ANY_CR_JTRGSEL_TIM1_CC4, ///< TIM1 CC4 - ADC1_InjectExtTrigSrc_T1_CC4_CC5 = ADC_ANY_CR_JTRGSEL_TIM1_CC4_CC5, ///< TIM1 CC4 and CC5 - ADC1_InjectExtTrigSrc_T2_CC1 = ADC_ANY_CR_JTRGSEL_TIM2_TIM4CC1, ///< TIM2 CC1 - ADC1_InjectExtTrigSrc_T3_CC4 = ADC_ANY_CR_JTRGSEL_TIM3_TIM5CC4, ///< TIM3 CC4 - ADC1_InjectExtTrigSrc_T8_CC4 = ADC_ANY_CR_JTRGSEL_TIM8_CC4, ///< TIM8 CC4 - ADC1_InjectExtTrigSrc_T8_CC4_CC5 = ADC_ANY_CR_JTRGSEL_TIM8_CC4_CC5, ///< TIM8 CC4 and CC5 - ADC1_InjectExtTrigSrc_EXTI_12 = ADC_ANY_CR_JTRGSEL_EXTI12, ///< EXTI12 - - ADC2_InjectExtTrigSrc_T1_TRGO = ADC_ANY_CR_JTRGSEL_TIM1_TRGO, ///< TIM1 TRGO - ADC2_InjectExtTrigSrc_T1_CC4 = ADC_ANY_CR_JTRGSEL_TIM1_CC4, ///< TIM1 CC4 - ADC2_InjectExtTrigSrc_T1_CC4_CC5 = ADC_ANY_CR_JTRGSEL_TIM1_CC4_CC5, ///< TIM1 CC4 and CC5 - ADC2_InjectExtTrigSrc_T2_CC1 = ADC_ANY_CR_JTRGSEL_TIM2_TIM4CC1, ///< TIM2 CC1 - ADC2_InjectExtTrigSrc_T3_CC4 = ADC_ANY_CR_JTRGSEL_TIM3_TIM5CC4, ///< TIM3 CC4 - ADC2_InjectExtTrigSrc_T8_CC4 = ADC_ANY_CR_JTRGSEL_TIM8_CC4, ///< TIM8 CC4 - ADC2_InjectExtTrigSrc_T8_CC4_CC5 = ADC_ANY_CR_JTRGSEL_TIM8_CC4_CC5, ///< TIM8 CC4 and CC5 - - ADC2_InjectExtTrigSrc_EXTI_12 = ADC_ANY_CR_JTRGSEL_EXTI12, ///< EXTI12 - ADC3_InjectExtTrigSrc_T1_TRGO = ADC_ANY_CR_JTRGSEL_TIM1_TRGO, ///< TIM1 TRGO - ADC3_InjectExtTrigSrc_T1_CC4 = ADC_ANY_CR_JTRGSEL_TIM1_CC4, ///< TIM1 CC4 - ADC3_InjectExtTrigSrc_T1_CC4_CC5 = ADC_ANY_CR_JTRGSEL_TIM1_CC4_CC5, ///< TIM1 CC4 and CC5 - ADC3_InjectExtTrigSrc_T4_CC1 = ADC_ANY_CR_JTRGSEL_TIM2_TIM4CC1, ///< TIM4 CC1 - ADC3_InjectExtTrigSrc_T5_CC4 = ADC_ANY_CR_JTRGSEL_TIM3_TIM5CC4, ///< TIM5 CC4 - ADC3_InjectExtTrigSrc_T8_CC4 = ADC_ANY_CR_JTRGSEL_TIM8_CC4, ///< TIM8 CC4 - ADC3_InjectExtTrigSrc_T8_CC4_CC5 = ADC_ANY_CR_JTRGSEL_TIM8_CC4_CC5, ///< TIM8 CC4 and CC5 - ADC3_InjectExtTrigSrc_EXTI_12 = ADC_ANY_CR_JTRGSEL_EXTI12, ///< EXTI12 -} EXTER_INJ_TRIG_TypeDef; - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ADC Init Structure definition -//////////////////////////////////////////////////////////////////////////////// -typedef struct { - u32 ADC_Resolution; ///< Convert data resolution - u32 ADC_PRESCARE; ///< Clock prescaler - u32 ADC_Mode; ///< ADC conversion mode - FunctionalState ADC_ContinuousConvMode; ///< Useless just for compatibility - u32 ADC_ExternalTrigConv; ///< External trigger source selection - u32 ADC_DataAlign; ///< Data alignmentn -} ADC_InitTypeDef; - -/// @} - - - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup ADC_Exported_Variables -/// @{ -#ifdef _HAL_ADC_C_ - -#define GLOBAL -#else -#define GLOBAL extern -#endif - -#undef GLOBAL -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup ADC_Exported_Functions -/// @{ -void ADC_DeInit(ADC_TypeDef* adc); -void ADC_Init(ADC_TypeDef* adc, ADC_InitTypeDef* init_struct); -void ADC_StructInit(ADC_InitTypeDef* init_struct); -void ADC_Cmd(ADC_TypeDef* adc, FunctionalState state); -void ADC_DMACmd(ADC_TypeDef* adc, FunctionalState state); -void ADC_ITConfig(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_interrupt, FunctionalState state); -void ADC_SoftwareStartConvCmd(ADC_TypeDef* adc, FunctionalState state); -void ADC_RegularChannelConfig(ADC_TypeDef* adc, u32 channel, u8 rank, u32 sample_time);//ADCSAM_TypeDef -void ADC_ExternalTrigConvCmd(ADC_TypeDef* adc, FunctionalState state); -void ADC_ExternalTrigConvConfig(ADC_TypeDef* adc, EXTERTRIG_TypeDef adc_external_trig_source); -#define ADC_ExternalTrigInjectedConvConfig ADC_ExternalTrigConvConfig -void ADC_AnalogWatchdogCmd(ADC_TypeDef* adc, FunctionalState state); -void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* adc, u16 high_threshold, u16 low_threshold); -void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* adc, ADCCHANNEL_TypeDef channel); -void ADC_TempSensorVrefintCmd(FunctionalState state); -void ADC_ClearITPendingBit(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_interrupt); -void ADC_ClearFlag(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_flag); - -u16 ADC_GetConversionValue(ADC_TypeDef* adc); - -FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* adc); -FlagStatus ADC_GetFlagStatus(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_flag); -ITStatus ADC_GetITStatus(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_interrupt); -void ADC_TempSensorCmd(FunctionalState state); -void ADC_VrefintCmd(FunctionalState state); -void exADC_TempSensorVrefintCmd(u32 chs, FunctionalState state); -void ADC_ANY_CH_Config(ADC_TypeDef* adc, u8 rank, ADCCHANNEL_TypeDef adc_channel); -void ADC_ANY_NUM_Config(ADC_TypeDef* adc, u8 num); -void ADC_ANY_Cmd(ADC_TypeDef* adc, FunctionalState state); -void ADC_AutoInjectedConvCmd(ADC_TypeDef* adc, FunctionalState state); -void ADC_ExternalTrigInjectedConvertConfig(ADC_TypeDef* adc, EXTER_INJ_TRIG_TypeDef ADC_ExtInjTrigSource); -void ADC_InjectedConvCmd(ADC_TypeDef* adc, FunctionalState state); -void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* adc, FunctionalState state); -void ADC_InjectedSequencerConfig(ADC_TypeDef* adc, u32 event, u32 sample_time); -void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* adc, ADC_INJ_SEQ_LEN_TypeDef Length); -void ADC_InjectedSequencerChannelConfig(ADC_TypeDef* adc, ADC_INJ_SEQ_Channel_TypeDef off_addr, ADCCHANNEL_TypeDef channel); -u16 ADC_GetInjectedConversionValue(ADC_TypeDef* adc, ADC_INJ_SEQ_Channel_TypeDef off_addr); -u16 ADC_GetInjectedCurrentConvertedValue(ADC_TypeDef* adc); -void ADC_SetInjectedOffset(ADC_TypeDef* adc, ADC_INJ_SEQ_Channel_TypeDef off_addr, u16 value); -u16 ADC_GetChannelConvertedValue(ADC_TypeDef* adc, ADCCHANNEL_TypeDef channel); -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -#endif -//////////////////////////////////////////////////////////////////////////////// - diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_bkp.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_bkp.h deleted file mode 100644 index 26a93d4a0..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_bkp.h +++ /dev/null @@ -1,130 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_bkp.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE BKP -/// FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#ifndef __HAL_BKP_H -#define __HAL_BKP_H - -// Files includes -#include "types.h" -#include "reg_bkp.h" - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup BKP_HAL -/// @brief BKP HAL modules -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup BKP_Exported_Types -/// @{ -//////////////////////////////////////////////////////////////////////////////// -/// @brief Data_Backup_Register -/// @anchor Data_Backup_Register - -typedef enum { - BKP_DR1 = 0x0010, - BKP_DR2 = 0x0014, - BKP_DR3 = 0x0018, - BKP_DR4 = 0x001C, - BKP_DR5 = 0x0020, - BKP_DR6 = 0x0024, - BKP_DR7 = 0x0028, - BKP_DR8 = 0x002C, - BKP_DR9 = 0x0030, - BKP_DR10 = 0x0034, - BKP_DR11 = 0x0038, - BKP_DR12 = 0x003C, - BKP_DR13 = 0x0040, - BKP_DR14 = 0x0044, - BKP_DR15 = 0x0048, - BKP_DR16 = 0x004C, - BKP_DR17 = 0x0050, - BKP_DR18 = 0x0054, - BKP_DR19 = 0x0058, - BKP_DR20 = 0x005C -} BKPDR_Typedef; - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Tamper_Pin_active_level -/// @anchor Tamper_Pin_active_level -typedef enum { - BKP_TamperPinLevel_High, ///< Tamper pin active on high level - BKP_TamperPinLevel_Low = BKP_CR_TPAL, ///< Tamper pin active on low level -} BKPTPAL_Typedef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief RTC_output_source_to_output_on_the_Tamper_pin -/// @anchor RTC_output_source_to_output_on_the_Tamper_pin -typedef enum { - BKP_RTCOutputSource_None = 0x0000, ///< No RTC output on the Tamper pin - BKP_RTCOutputSource_CalibClock = 0x0080, ///< Output the RTC clock with frequency divided by 64 on the Tamper pin - BKP_RTCOutputSource_Alarm = 0x0100, ///< Output the RTC Alarm pulse signal on the Tamper pin - BKP_RTCOutputSource_Second = 0x0300 ///< Output the RTC Second pulse signal on the Tamper pin -} BKPRTCOUTPUTSRC_Typedef; - - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup BKP_Exported_Variables -/// @{ -#ifdef _HAL_BKP_C_ -#define GLOBAL - -#else -#define GLOBAL extern -#endif - -#undef GLOBAL -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup BKP_Exported_Functions -/// @{ - -void BKP_WriteBackupRegister(BKPDR_Typedef bkp_dr, u16 data); -u16 BKP_ReadBackupRegister(BKPDR_Typedef bkp_dr); - -void BKP_DeInit(void); -void BKP_ClearFlag(void); -void BKP_ClearITPendingBit(void); -void BKP_TamperPinLevelConfig(BKPTPAL_Typedef tamper_pin_level); -void BKP_TamperPinCmd(FunctionalState state); -void BKP_ITConfig(FunctionalState state); -void BKP_RTCOutputConfig(BKPRTCOUTPUTSRC_Typedef rtc_output_source); -void BKP_SetRTCCalibrationValue(u8 calibration_value); - -ITStatus BKP_GetITStatus(void); -FlagStatus BKP_GetFlagStatus(void); -void exBKP_Init(void); -void exBKP_ImmWrite(BKPDR_Typedef bkp_dr, u16 data); -u16 exBKP_ImmRead(BKPDR_Typedef bkp_dr); -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -#endif // __HAL_BKP_H -//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_can.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_can.h deleted file mode 100644 index b7e1d4b42..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_can.h +++ /dev/null @@ -1,340 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_can.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE CAN -/// FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#ifndef __HAL_CAN_H -#define __HAL_CAN_H - -// Files includes -#include "types.h" -#include "reg_can.h" - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup CAN_HAL -/// @brief CAN HAL modules -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup CAN_Exported_Types -/// @{ - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief CAN_Initialization -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - CANINITFAILED = 0x00000000, ///< CAN initialization failed - CANINITOK = 0x00000001 ///< CAN initialization ok -} emCAN_INIT_Typedef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief CAN_sleep_constants -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - CANSLEEPFAILED = 0x00000000, ///< CAN did not enter the sleep mode - CANSLEEPOK = 0x00000001 ///< CAN entered the sleep mode -} emCAN_SLEEP_conts_Typedef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief CAN_wake_up_constants -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - CANWAKEUPFAILED = 0x00000000, ///< CAN did not leave the sleep mode - CANWAKEUPOK = 0x00000001 ///< CAN leaved the sleep mode -} emCAN_WAKE_conts_Typedef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief CAN_Mode -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - CAN_BASICMode = 0x00000000, - CAN_PELIMode = 0x00000080, - CAN_WorkMode = 0x00000080, - CAN_ResetMode = 0x00000001, - CAN_ListenOnlyMode = 0x00000002, - CAN_SeftTestMode = 0x00000004, - CAN_FilterMode_Singal = 0x00000008, - CAN_FilterMode_Double = 0x000000f7, - CAN_SleepMode = 0x00000010 -} emCAN_CAN_Mode_Typedef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief BASIC_CAN_interrupt -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - CAN_IT_RIE = CAN_CR_RIE, ///< Overflow interrupt enable - CAN_IT_TIE = CAN_CR_TIE, ///< Transmit interrupt enable - CAN_IT_EIE = CAN_CR_EIE, ///< Error interrupt enable - CAN_IT_OIE = CAN_CR_OIE ///< Receive interrupt enable -} emCAN_BASIC_IntEn_Typedef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief PELI_CAN_interrupt -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - CAN_IT_RI = CAN_IR_RI, ///< Overflow interrupt enable - CAN_IT_TI = CAN_IR_TI, ///< Transmit interrupt enable - CAN_IT_EI = CAN_IR_EI, ///< Error interrupt enable - CAN_IT_DOI = CAN_IR_DOI, ///< Receive interrupt enable - CAN_IT_WUI = 0x00001010, ///< Receive interrupt enable - CAN_IT_EPI = CAN_IR_EPI, ///< Receive interrupt enable - CAN_IT_ALI = CAN_IR_ALI, ///< Receive interrupt enable - CAN_IT_BEI = CAN_IR_BEI, ///< Receive interrupt enable - CAN_IT_ALL = 0xFFFF ///< Receive interrupt enable - -} emCAN_PELI_IntEn_Typedef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief CAN_Status -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - CAN_STATUS_RBS = CAN_SR_RBS, - CAN_STATUS_DOS = CAN_SR_DOS, - CAN_STATUS_TBS = CAN_SR_TBS, - CAN_STATUS_TCS = CAN_SR_TCS, - CAN_STATUS_RS = CAN_SR_RS, - CAN_STATUS_TS = CAN_SR_TS, - CAN_STATUS_ES = CAN_SR_ES, - CAN_STATUS_BS = CAN_SR_BS -} emCAN_Status_Typedef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief CAN_Command_register -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - CAN_TR = CAN_CMR_TR, ///< Transmission request - CAN_AT = CAN_CMR_AT, - CAN_RRB = CAN_CMR_RRB, - CAN_CDO = CAN_CMR_CDO -} emCAN_Command_Typedef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief CAN_Peli transmit frame definition -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - DataFrame = 0, ///< Data Frame - RemoteFrame = !DataFrame -} TransFrame; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief CAN_Basic init structure definition -//////////////////////////////////////////////////////////////////////////////// -typedef struct { - u8 SJW; - u8 BRP; - FlagStatus SAM; - u8 TESG2; - u8 TESG1; - FunctionalState GTS; - u8 CDCLK; - u8 CLOSE_OPEN_CLK; - u8 RXINTEN; - u8 CBP; -} CAN_Basic_InitTypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief CAN_Peli init structure definition -//////////////////////////////////////////////////////////////////////////////// -typedef struct { - u8 SJW; - u8 BRP; - FlagStatus SAM; - u8 TESG2; - u8 TESG1; - FunctionalState LOM; - FunctionalState STM; - FunctionalState SM; - FunctionalState SRR; - u32 EWLR; -} CAN_Peli_InitTypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief CAN_Basic filter init structure definition -//////////////////////////////////////////////////////////////////////////////// - -typedef struct { - u8 CAN_FilterId; ///< Specifies the filter identification number. This parameter can be a value between 0x00 and 0xFF. - u8 CAN_FilterMaskId; ///< Specifies the filter mask number or identification number, This parameter can be a value between - ///< 0x00 and 0xFF. -} CAN_Basic_FilterInitTypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief CAN_Peli filter init structure definition -//////////////////////////////////////////////////////////////////////////////// - -typedef struct { - u8 AFM; - u8 CAN_FilterId0; ///< Specifies the filter identification number, This parameter can be a value between 0x00 and 0xFF - u8 CAN_FilterId1; - u8 CAN_FilterId2; - u8 CAN_FilterId3; - u8 CAN_FilterMaskId0; ///< Specifies the filter mask number or identification number, This parameter can be a value between - ///< 0x00 and 0xFF - u8 CAN_FilterMaskId1; - u8 CAN_FilterMaskId2; - u8 CAN_FilterMaskId3; -} CAN_Peli_FilterInitTypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief CAN_Basic Tx message structure definition -//////////////////////////////////////////////////////////////////////////////// - -typedef struct { - u8 IDH; ///< Specifies the standard high identifier. This parameter can be a value between 0 to 0xFF. - u8 IDL; ///< Specifies the standard low identifier. This parameter can be a value between 0 to 0x7. - u8 RTR; ///< Specifies the type of frame for the message that will be transmitted. This parameter can be @TransFrame. - u8 DLC; ///< Specifies the length of the frame that will be transmitted. This parameter can be a value between 0 to 8. - u8 Data[8]; ///< Contains the data to be transmitted. It ranges from 0 to 0xFF. -} CanBasicTxMsg; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief CAN_Basic Rx message structure definition -//////////////////////////////////////////////////////////////////////////////// - -typedef struct { - u16 ID; ///< Specifies the standard identifier. This parameter can be a value between 0 to 0x7FF. - u8 RTR; ///< Specifies the type of frame for the received message. This parameter can be a value of @ref TransFrame - u8 DLC; ///< Specifies the length of the frame that will be received. This parameter can be a value between 0 to 8 - u8 Data[8]; ///< Contains the data to be received. It ranges from 0 to 0xFF. -} CanBasicRxMsg; - -/////////////////////////////////////////////////////////////////////////////// -/// @brief CAN_Peli_Tx message structure definition -/////////////////////////////////////////////////////////////////////////////// - -typedef struct { - u8 IDLL; ///< Specifies the extended identifier. - ///< This parameter can be a value between 0 to 0xFF. - u8 IDLH; - u8 IDHL; - u8 IDHH; - u8 FF; ///< Specifies the type of identifier for the message that will be transmitted. This parameter can be a value of @ref - ///< CAN_identifier_type - u8 RTR; ///< Specifies the type of frame for the message that will be transmitted. This parameter can be a value of @ref - ///< TransFrame. - u8 DLC; ///< Specifies the length of the frame that will be transmitted. This parameter can be a value between 0 to 8. - u8 Data[8]; ///< Contains the data to be transmitted. It ranges from 0 to 0xFF. -} CanPeliTxMsg; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief CAN Rx message structure definition -//////////////////////////////////////////////////////////////////////////////// -typedef struct { - u32 ID; ///< Specifies the extended identifier. This parameter can be a value between 0 to 0x1FFFFFFF. - u8 FF; ///< Specifies the type of identifier for the message that will be received. This parameter can be a value of @ref - ///< CAN_identifier_type. - u8 RTR; ///< Specifies the type of frame for the received message. This parameter can be a value of @ref TransFrame. - u8 DLC; ///< Specifies the length of the frame that will be received. This parameter can be a value between 0 to 8. - u8 Data[8]; ///< Contains the data to be received. It ranges from 0 to0xFF. -} CanPeliRxMsg; - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup CAN_Exported_Constants -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup parasmeter_of_CAN_transmission_register -/// @{ -#define CANTXFAILED (0x00U) ///< CAN transmission failed -#define CANTXOK (0x01U) ///< CAN transmission succeeded -#define CANTXPENDING (0x02U) ///< CAN transmission pending -#define CAN_NO_MB (0x04U) ///< CAN cell did not provide an empty mailbox -/// @} - - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup CAN_Exported_Variables -/// @{ -#ifdef _HAL_CAN_C_ - -#define GLOBAL -#else -#define GLOBAL extern -#endif - -#undef GLOBAL -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup CAN_Exported_Functions -/// @{ - -// Basic and Peli Work all need function --------------------------------------- - -void CAN_Mode_Cmd(CAN_TypeDef* can, u32 mode); -void CAN_ResetMode_Cmd(CAN_TypeDef* can, FunctionalState state); -void CAN_ClearDataOverflow(CAN_TypeDef* can); -void CAN_ClearITPendingBit(CAN_TypeDef* can); - -// Basic Work function --------------------------------------------------------- -void CAN_DeInit(CAN_TypeDef* can); -void CAN_FilterInit(CAN_Basic_FilterInitTypeDef* basic_filter_init_struct); -void CAN_StructInit(CAN_Basic_InitTypeDef* basic_init_struct); -void CAN_ITConfig(CAN_TypeDef* can, u32 it, FunctionalState state); -void CAN_CancelTransmit(CAN_TypeDef* can); -void CAN_FIFORelease(CAN_TypeDef* can); -void CAN_Receive(CAN_TypeDef* can, CanBasicRxMsg* basic_receive_message); - -u8 CAN_Transmit(CAN_TypeDef* can, CanBasicTxMsg* basic_transmit_message); -u8 CAN_Init(CAN_TypeDef* can, CAN_Basic_InitTypeDef* basic_init_struct); -u8 CAN_Sleep(CAN_TypeDef* can); -u8 CAN_WakeUp(CAN_TypeDef* can); - -FlagStatus CAN_GetFlagStatus(CAN_TypeDef* can, u32 flag); -ITStatus CAN_GetITStatus(CAN_TypeDef* can, u32 it); - -// Peli Work function ---------------------------------------------------------- -void CAN_Peli_SleepMode_Cmd(FunctionalState state); -void CAN_Peli_Init(CAN_Peli_InitTypeDef* init_struct); -void CAN_Peli_StructInit(CAN_Peli_InitTypeDef* peli_init_struct); -void CAN_Peli_FilterInit(CAN_Peli_FilterInitTypeDef* peli_filter_init_struct); -void CAN_Peli_FilterStructInit(CAN_Peli_FilterInitTypeDef* peli_filter_init_struct); -void CAN_Peli_Transmit(CanPeliTxMsg* peli_transmit_message); -void CAN_Peli_TransmitRepeat(CanPeliTxMsg* peli_transmit_message); -void CAN_Peli_Receive(CanPeliRxMsg* peli_receive_message); -void CAN_Peli_ITConfig(u32 it, FunctionalState state); -void CAN_AutoCfg_BaudParam(CAN_Peli_InitTypeDef* init_struct, u32 src_clk, u32 baud); - -u32 CAN_Peli_GetRxFIFOInfo(void); -u8 CAN_Peli_GetLastErrorCode(void); -u8 CAN_Peli_GetReceiveErrorCounter(void); -u8 CAN_Peli_GetLSBTransmitErrorCounter(void); - -ITStatus CAN_Peli_GetITStatus(u32 it); - - - -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -#endif -//////////////////////////////////////////////////////////////////////////////// - diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_comp.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_comp.h deleted file mode 100644 index 617318d53..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_comp.h +++ /dev/null @@ -1,228 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_comp.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE COMP -/// FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#ifndef __HAL_COMP_H -#define __HAL_COMP_H - - -// Files includes -#include "reg_common.h" -#include "reg_comp.h" - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup COMP_HAL -/// @brief COMP HAL modules -/// @{ -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup COMP_Exported_Types -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @brief COMP_InvertingInput -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - COMP_InvertingInput_IO0 = COMP_CSR_INM_0, ///< INM0 as COMP inverting input - COMP_InvertingInput_IO1 = COMP_CSR_INM_1, ///< INM1 as COMP inverting input - COMP_InvertingInput_IO2 = COMP_CSR_INM_2, ///< INM2 as COMP inverting input - COMP_InvertingInput_CRV = COMP_CSR_INM_3, ///< INM3 as COMP inverting input - COMP_InvertingInput_IO3 = COMP_CSR_INM_3, ///< INM3 as COMP inverting input -} EM_COMP_InvertingInput; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief COMP_NonInvertingInput -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - COMP_NonInvertingInput_IO0 = COMP_CSR_INP_INP0, ///< INP0 as COMP non-inverting input - COMP_NonInvertingInput_IO1 = COMP_CSR_INP_INP1, ///< INP1 as COMP non-inverting input - COMP_NonInvertingInput_IO2 = COMP_CSR_INP_INP2, ///< INP2 as COMP non-inverting input - COMP_NonInvertingInput_IO3 = COMP_CSR_INP_INP3, ///< INP3 as COMP non-inverting input -} EM_COMP_NonInvertingInput; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief COMP_Output -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - COMP_Output_None = 0x00000000, ///< No output - COMP_Output_TIM1BKIN = COMP_CSR_OUT_TIM1_BRAKE, ///< Timer1 brake input - COMP_Output_TIM1OCREFCLR = COMP_CSR_OUT_TIM1_OCREFCLR, ///< Timer1 ocrefclear input - COMP_Output_TIM1IC1 = COMP_CSR_OUT_TIM1_CAPTURE1, ///< Timer1 input capture 1 - COMP_Output_TIM2IC4 = COMP_CSR_OUT_TIM2_CAPTURE4, ///< Timer2 input capture 4 - COMP_Output_TIM2OCREFCLR = COMP_CSR_OUT_TIM2_OCREFCLR, ///< Timer2 ocrefclear input - COMP_Output_TIM3IC1 = COMP_CSR_OUT_TIM3_CAPTURE1, ///< Timer3 input capture 1 - COMP_Output_TIM3OCREFCLR = COMP_CSR_OUT_TIM3_OCREFCLR ///< Timer3 ocrefclear input -} EM_COMP_Output; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief COMP_OutputPoloarity -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - COMP_NonInverted = 0x00000000, ///< COMP non-inverting output - COMP_OutputPol_NonInverted = 0x00000000, - COMP_Inverted = 0x00008000, ///< COMP inverting output - COMP_OutputPol_Inverted = 0x00008000 -} EM_COMP_OutputPol; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief COMP_Hysteresis -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - COMP_Hysteresis_No = COMP_CSR_HYST_0, ///< Hysteresis Voltage: 0mV - COMP_Hysteresis_Low = COMP_CSR_HYST_15, ///< Hysteresis Voltage: 15mV - COMP_Hysteresis_Medium = COMP_CSR_HYST_30, ///< Hysteresis Voltage: 30mV - COMP_Hysteresis_High = COMP_CSR_HYST_90 ///< Hysteresis Voltage: 90mV -} EM_COMP_Hysteresis; -typedef enum { - COMP_Filter_0_Period = COMP_CSR_OFLT_0, ///< filter is ((u32)0x00000000) - COMP_Filter_2_Period = COMP_CSR_OFLT_1, ///< filter is ((u32)0x00040000) - COMP_Filter_4_Period = COMP_CSR_OFLT_2, ///< filter is ((u32)0x00080000) - COMP_Filter_8_Period = COMP_CSR_OFLT_3, ///< filter is ((u32)0x000C0000) - COMP_Filter_16_Period = COMP_CSR_OFLT_4, ///< filter is ((u32)0x00100000) - COMP_Filter_32_Period = COMP_CSR_OFLT_5, ///< filter is ((u32)0x00140000) - COMP_Filter_64_Period = COMP_CSR_OFLT_6, ///< filter is ((u32)0x00180000) - COMP_Filter_128_Period = COMP_CSR_OFLT_7, ///< filter is ((u32)0x001C0000) -} EM_COMP_FILT; -//////////////////////////////////////////////////////////////////////////////// -/// @brief COMP_Mode -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - COMP_Mode_HighSpeed = COMP_CSR_MODE_HIGHRATE, ///< Comparator high rate mode - COMP_Mode_MediumSpeed = COMP_CSR_MODE_MEDIUMRATE, ///< Comparator medium rate mode - COMP_Mode_LowPower = COMP_CSR_MODE_LOWPOWER, ///< Comparator low power mode - COMP_Mode_UltraLowPower = COMP_CSR_MODE_LOWESTPOWER ///< Comparator lowest power mode -} EM_COMP_Mode; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief COMP_OutputLevel -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - COMP_OutputLevel_High = COMP_CSR_OUT, ///< High output - COMP_OutputLevel_Low = 0x00000000 ///< Low output -} EM_COMP_OutputLevel; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief COMP Init structure definition -//////////////////////////////////////////////////////////////////////////////// -typedef struct { - union { - u32 COMP_InvertingInput; - u32 Invert; ///< Selects the inverting input of the comparator. - }; - union { - u32 COMP_NonInvertingInput; - u32 NonInvert; ///< Selects the non inverting input of the comparator. - }; - union { - u32 COMP_Output; - u32 Output; ///< Selects the output redirection of the comparator. - u32 BlankingSrce; ///< Selects the output blanking source of the comparator. - }; - union { - u32 COMP_OutputPol; - u32 OutputPol; ///< Selects the output polarity of the comparator. - }; - union { - u32 COMP_Hysteresis; - u32 Hysteresis; ///< Selects the hysteresis voltage of the comparator. - }; - union { - u32 COMP_Mode; - u32 Mode; ///< Selects the operating mode of the comparator and allows - }; - union { - u32 COMP_Filter; - u32 OFLT; ///< to adjust the speed/consumption. - }; -} COMP_InitTypeDef; - - - -typedef struct { - - FunctionalState COMP_Poll_En; ///< Selects the inverting input of the comparator. - - u32 COMP_Poll_Ch; ///< Selects the non inverting input of the comparator. - u32 COMP_Poll_Fixn; ///< Selects the output redirection of the comparator. - u32 COMP_Poll_Period; ///< Selects the output polarity of the comparator. - u32 COMP_Poll_Pout; ///< Selects the hysteresis voltage of the comparator. - -} COMP_POLL_InitTypeDef; -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup COMP_Exported_Constants -/// @{ -//////////////////////////////////////////////////////////////////////////////// -/// @brief COMP Init structure definition -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - COMP1 = (0x00000C), ///< Select comparator 1 - COMP2 = (0x000010), ///< Select comparator 2 -} COMP_Selection_TypeDef; - -#define COMP_BlankingSrce_None ((u32)0x00000000) -#define COMP_CSR_CLEAR_MASK ((u32)0x00000003) - -#define COMP_CSR_COMPSW1 ((u32)0x00000002) - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -///@defgroup COMP_Exported_Variables -/// @{ -#ifdef _HAL_COMP_C_ - -#define GLOBAL -#else -#define GLOBAL extern -#endif - -#undef GLOBAL -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup COMP_Exported_Functions -/// @{ - - -void COMP_DeInit(COMP_Selection_TypeDef selection); -void COMP_Init(COMP_Selection_TypeDef selection, COMP_InitTypeDef* init_struct); -void COMP_StructInit(COMP_InitTypeDef* init_struct); -void COMP_Cmd(COMP_Selection_TypeDef selection, FunctionalState state); -void COMP_SwitchCmd(COMP_Selection_TypeDef selection, FunctionalState state); -void COMP_LockConfig(COMP_Selection_TypeDef selection); - -u32 COMP_GetOutputLevel(COMP_Selection_TypeDef selection); - -void COMP_SetCrv(u8 crv_select, u8 crv_level); -#define SET_COMP_CRV COMP_SetCrv - - -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -#endif //__HAL_COMP_H -//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_conf.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_conf.h deleted file mode 100644 index 758c7a618..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_conf.h +++ /dev/null @@ -1,62 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_conf.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE GENERIC MICROCONTROLLER -/// FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

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-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#ifndef __HAL_CONF_H -#define __HAL_CONF_H -// Files includes -#include "mm32_device.h" - -#include "hal_adc.h" -#include "hal_bkp.h" -#include "hal_can.h" -#include "hal_comp.h" -#include "hal_crc.h" -#include "hal_crs.h" -#include "hal_dac.h" -#include "hal_dbg.h" -#include "hal_dma.h" -#include "hal_exti.h" -#include "hal_flash.h" -#include "hal_gpio.h" -#include "hal_i2c.h" -#include "hal_iwdg.h" -#include "hal_misc.h" -#include "hal_pwr.h" -#include "hal_rcc.h" -#include "hal_rtc.h" -#include "hal_spi.h" -#include "hal_syscfg.h" -#include "hal_tim.h" -#include "hal_uart.h" -#include "hal_uid.h" -#include "hal_wwdg.h" -#include "hal_redefine.h" -#include "hal_eth.h" -#include "hal_eth_conf.h" -#include "hal_fsmc.h" - -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -#endif //__HAL_CONF_H -//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crc.h deleted file mode 100644 index f5f3d6054..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crc.h +++ /dev/null @@ -1,84 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_crc.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE CRC -/// FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

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-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#ifndef __HAL_CRC_H -#define __HAL_CRC_H - -// Files includes -#include "types.h" -#include "reg_common.h" -#include "reg_crc.h" - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup CRC_HAL -/// @brief CRC HAL modules -/// @{ - - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup CRC_Exported_Types -/// @{ - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup CRC_Exported_Constants -/// @{ - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup CRC_Exported_Variables -/// @{ -#ifdef _HAL_CRC_C_ -#define GLOBAL - -#else -#define GLOBAL extern -#endif - -#undef GLOBAL -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup CRC_Exported_Functions -/// @{ -void CRC_ResetDR(void); -void CRC_SetIDRegister(u8 id_value); - -u32 CRC_CalcCRC(u32 data); -u32 CRC_CalcBlockCRC(u32* buffer, u32 length); -u32 CRC_GetCRC(void); - -u8 CRC_GetIDRegister(void); - -/// @} - -/// @} - -/// @} - - -//////////////////////////////////////////////////////////////////////////////// -#endif // __HAL_CRC_H -//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crs.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crs.h deleted file mode 100644 index d3c2a6cc5..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crs.h +++ /dev/null @@ -1,46 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_crs.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE CRS -/// FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

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-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#ifndef __HAL_CRS_H -#define __HAL_CRS_H - - -// Files includes -#include "types.h" -#include "reg_crs.h" - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup CRS_HAL -/// @brief CRS HAL modules -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup GPIO_Exported_Types -/// @{ - - - -//////////////////////////////////////////////////////////////////////////////// -#endif -//////////////////////////////////////////////////////////////////////////////// - diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dac.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dac.h deleted file mode 100644 index e538b20b7..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dac.h +++ /dev/null @@ -1,166 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_dac.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE DAC -/// FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

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-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#ifndef __HAL_DAC_H -#define __HAL_DAC_H - -// Files includes -#include "types.h" -#include "reg_dac.h" - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup DAC_HAL -/// @brief DAC HAL modules -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup DAC_Exported_Types -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @brief DAC_Trigger_Selection -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - DAC_Trigger_None = 0x00000000, - DAC_Trigger_T1_TRIG = (DAC_CR_TSEL1_TIM1_TRIG | DAC_CR_TEN1), - DAC_Trigger_T3_TRIG = (DAC_CR_TSEL1_TIM3_TRIG | DAC_CR_TEN1), - DAC_Trigger_T2_TRIG = (DAC_CR_TSEL1_TIM2_TRIG | DAC_CR_TEN1), - DAC_Trigger_T4_TRIG = (DAC_CR_TSEL1_TIM4_TRIG | DAC_CR_TEN1), - DAC_Trigger_Ext_IT9 = (DAC_CR_TSEL1_EXTI9 | DAC_CR_TEN1), - DAC_Trigger_Software = (DAC_CR_TSEL1_SOFTWARE) -} emDACTRIG_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief DAC_Wave_Generation -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - DAC_WaveGeneration_None = DAC_CR_WAVE1_NONE, - DAC_WaveGeneration_Noise = DAC_CR_WAVE1_NOISE, - DAC_WaveGeneration_Triangle = DAC_CR_WAVE1_TRIANGLE -} emDACWAVE_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief DAC_Mask_Amplitude -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - DAC_TriangleAmplitude_1 = DAC_CR_MAMP1_1, - DAC_TriangleAmplitude_3 = DAC_CR_MAMP1_3, - DAC_TriangleAmplitude_7 = DAC_CR_MAMP1_7, - DAC_TriangleAmplitude_15 = DAC_CR_MAMP1_15, - DAC_TriangleAmplitude_31 = DAC_CR_MAMP1_31, - DAC_TriangleAmplitude_63 = DAC_CR_MAMP1_63, - DAC_TriangleAmplitude_127 = DAC_CR_MAMP1_127, - DAC_TriangleAmplitude_255 = DAC_CR_MAMP1_255, - DAC_TriangleAmplitude_511 = DAC_CR_MAMP1_511, - DAC_TriangleAmplitude_1023 = DAC_CR_MAMP1_1023, - DAC_TriangleAmplitude_2047 = DAC_CR_MAMP1_2047, - DAC_TriangleAmplitude_4095 = DAC_CR_MAMP1_4095 -} emDACAMP_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief channel -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - DAC_Channel_1, ///< DAC channel 1 - DAC_Channel_2 = (u32)0x00000010 ///< DAC Channel 2 -} emDACCH_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief DAC_Data_Alignement -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - DAC_Align_12b_R = ((u32)0x00000000), - DAC_Align_12b_L = ((u32)0x00000004), - DAC_Align_8b_R = ((u32)0x00000008) -} emDACALIGN_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief DAC_Output_Buffer -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - DAC_OutputBuffer_Enable = 0x00000000, ///< DAC output buffer enable - DAC_OutputBuffer_Disable = DAC_CR_BOFF1 ///< DAC output buffer disable -} emDACBOFF_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief DAC Init structure definition -//////////////////////////////////////////////////////////////////////////////// -typedef struct { - emDACTRIG_TypeDef DAC_Trigger; - emDACWAVE_TypeDef DAC_WaveGeneration; - emDACAMP_TypeDef DAC_LFSRUnmask_TriangleAmplitude; - emDACBOFF_TypeDef DAC_OutputBuffer; -} DAC_InitTypeDef; - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup DAC_Exported_Constants -/// @{ -#define DHR12R1_Offset ((u32)0x00000008) -#define DHR12R2_Offset ((u32)0x00000014) -#define DHR12RD_Offset ((u32)0x00000020) -#define DOR_Offset ((u32)0x0000002C) - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup DAC_Exported_Variables -/// @{ -#ifdef _HAL_DAC_C_ -#define GLOBAL - -#else -#define GLOBAL extern -#endif - -#undef GLOBAL -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup DAC_Exported_Functions -/// @{ -void DAC_DeInit(void); -void DAC_Init(emDACCH_TypeDef channel, DAC_InitTypeDef* init_struct); -void DAC_StructInit(DAC_InitTypeDef* init_struct); -void DAC_Cmd(emDACCH_TypeDef channel, FunctionalState state); -void DAC_DMACmd(emDACCH_TypeDef channel, FunctionalState state); -void DAC_SoftwareTriggerCmd(emDACCH_TypeDef channel, FunctionalState state); -void DAC_DualSoftwareTriggerCmd(FunctionalState state); -void DAC_WaveGenerationCmd(emDACCH_TypeDef channel, emDACWAVE_TypeDef wave, FunctionalState state); -void DAC_SetChannel1Data(emDACALIGN_TypeDef alignement, u16 data); -void DAC_SetChannel2Data(emDACALIGN_TypeDef alignement, u16 data); -void DAC_SetDualChannelData(emDACALIGN_TypeDef alignement, u16 data2, u16 data1); - -u16 DAC_GetDataOutputValue(emDACCH_TypeDef channel); - -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -#endif // __HAL_DAC_H -//////////////////////////////////////////////////////////////////////////////// - diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dbg.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dbg.h deleted file mode 100644 index 0e9b41d1e..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dbg.h +++ /dev/null @@ -1,72 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_dbg.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE DBG -/// FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

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-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#ifndef __HAL_DBG_H -#define __HAL_DBG_H - -// Files includes -#include "types.h" -#include "reg_common.h" -#include "reg_dbg.h" - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup DBG_HAL -/// @brief DBG HAL modules -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup DBG_Exported_Types -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup DIV_Exported_Variables -/// @{ -#ifdef _HAL_DBG_C_ - -#define GLOBAL -#else -#define GLOBAL extern -#endif - -#undef GLOBAL -/// @} - - - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup DBG_Exported_Functions -/// @{ -void DBGMCU_Configure(u32 periph, FunctionalState state); - -/// @} - - -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -#endif // __HAL_DBG_H -//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_device.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_device.h deleted file mode 100644 index ff2133702..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_device.h +++ /dev/null @@ -1,41 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_device.h -/// @author AE team -/// @brief CMSIS Cortex-M Peripheral Access Layer for MindMotion -/// microcontroller devices -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

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-//////////////////////////////////////////////////////////////////////////////// - - -// Define to prevent recursive inclusion -#ifndef __HAL_DEVICE_H -#define __HAL_DEVICE_H - - - - - -#include "mm32_device.h" - - -#endif // __HAL_device_H - -/// @} - - -/// @} - -/// @} - - - diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dma.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dma.h deleted file mode 100644 index 892e750b5..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dma.h +++ /dev/null @@ -1,306 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_dma.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE DMA -/// FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

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-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#ifndef __HAL_DMA_H -#define __HAL_DMA_H -// Files includes -#include "types.h" -#include "reg_common.h" -#include "reg_dma.h" - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup DMA_HAL -/// @brief DMA HAL modules -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup DMA_Exported_Types -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @brief DMA data transfer direction Enumerate definition -/// @anchor DMA_data_transfer_direction -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - DMA_DIR_PeripheralSRC = 0U, - DMA_DIR_PeripheralDST = DMA_CCR_DIR // 0x00000010U -} DMA_data_transfer_direction_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief DMA peripheral incremented mode Enumerate definition -/// @anchor DMA_peripheral_incremented_mode -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - DMA_PeripheralInc_Disable = 0U, - DMA_PeripheralInc_Enable = DMA_CCR_PINC // 0x00000040U -} DMA_peripheral_incremented_mode_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief DMA memory incremented mode Enumerate definition -/// @anchor DMA_memory_incremented_mode -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - DMA_MemoryInc_Disable = 0U, - DMA_MemoryInc_Enable = DMA_CCR_MINC // 0x00000080U -} DMA_memory_incremented_mode_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief DMA peripheral data size Enumerate definition -/// @anchor DMA_peripheral_data_size -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - DMA_PeripheralDataSize_Byte = 0U, - DMA_PeripheralDataSize_HalfWord = DMA_CCR_PSIZE_HALFWORD, - DMA_PeripheralDataSize_Word = DMA_CCR_PSIZE_WORD -} DMA_peripheral_data_size_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief DMA memory data size Enumerate definition -/// @anchor DMA_memory_data_size -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - DMA_MemoryDataSize_Byte = 0U, - DMA_MemoryDataSize_HalfWord = DMA_CCR_MSIZE_HALFWORD, // 0x00000400U - DMA_MemoryDataSize_Word = DMA_CCR_MSIZE_WORD // 0x00000800U -} DMA_memory_data_size_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief DMA circular normal mode Enumerate definition -/// @anchor DMA_circular_normal_mode -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - DMA_Mode_Normal = 0U, - DMA_Mode_Circular = DMA_CCR_CIRC // 0x00000020U -} DMA_circular_normal_mode_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief DMA priority level Enumerate definition -/// @anchor DMA_priority_level -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - DMA_Priority_Low = 0U, - DMA_Priority_Medium = DMA_CCR_PL_Medium, // 0x00001000U - DMA_Priority_High = DMA_CCR_PL_High, // 0x00002000U - DMA_Priority_VeryHigh = DMA_CCR_PL_VeryHigh // 0x00003000U -} DMA_priority_level_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief DMA memory to memory Enumerate definition -/// @anchor DMA_memory_to_memory -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - DMA_M2M_Disable = 0U, - DMA_M2M_Enable = DMA_CCR_M2M // 0x00004000U -} DMA_memory_to_memory_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief DMA auto reload Enumerate definition -/// @anchor DMA_auto_reload -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - DMA_Auto_Reload_Disable = 0U, // - DMA_Auto_Reload_Enable = DMA_CCR_ARE -} DMA_auto_reload_TypeDef; -/// @brief DMA Interrupt Setting Enumerate definition -/// @anchor DMA_auto_reload -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - DMA_IT_TC = DMA_CCR_TCIE, //(0x00000002UL), - DMA_IT_HT = DMA_CCR_HTIE, //(0x00000004UL), - DMA_IT_TE = DMA_CCR_TEIE, //(0x00000008UL), -} DMA_Interrupt_EN_TypeDef; - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief DMA interrupts Enumerate definition -/// @anchor DMA_Flags -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - DMAx_IT_GLy = (0x00000001UL), - DMAx_IT_TCy = (0x00000002UL), - DMAx_IT_HTy = (0x00000004UL), - DMAx_IT_TEy = (0x00000008UL), - DMA1_IT_GL1 = (0x00000001UL), - DMA1_IT_TC1 = (0x00000002UL), - DMA1_IT_HT1 = (0x00000004UL), - DMA1_IT_TE1 = (0x00000008UL), - DMA1_IT_GL2 = (0x00000010UL), - DMA1_IT_TC2 = (0x00000020UL), - DMA1_IT_HT2 = (0x00000040UL), - DMA1_IT_TE2 = (0x00000080UL), - DMA1_IT_GL3 = (0x00000100UL), - DMA1_IT_TC3 = (0x00000200UL), - DMA1_IT_HT3 = (0x00000400UL), - DMA1_IT_TE3 = (0x00000800UL), - DMA1_IT_GL4 = (0x00001000UL), - DMA1_IT_TC4 = (0x00002000UL), - DMA1_IT_HT4 = (0x00004000UL), - DMA1_IT_TE4 = (0x00008000UL), - DMA1_IT_GL5 = (0x00010000UL), - DMA1_IT_TC5 = (0x00020000UL), - DMA1_IT_HT5 = (0x00040000UL), - DMA1_IT_TE5 = (0x00080000UL), - DMA1_IT_GL6 = (0x00100000UL), - DMA1_IT_TC6 = (0x00200000UL), - DMA1_IT_HT6 = (0x00400000UL), - DMA1_IT_TE6 = (0x00800000UL), - DMA1_IT_GL7 = (0x01000000UL), - DMA1_IT_TC7 = (0x02000000UL), - DMA1_IT_HT7 = (0x04000000UL), - DMA1_IT_TE7 = (0x08000000UL), - DMA2_IT_GL1 = (0x10000001UL), - DMA2_IT_TC1 = (0x10000002UL), - DMA2_IT_HT1 = (0x10000004UL), - DMA2_IT_TE1 = (0x10000008UL), - DMA2_IT_GL2 = (0x10000010UL), - DMA2_IT_TC2 = (0x10000020UL), - DMA2_IT_HT2 = (0x10000040UL), - DMA2_IT_TE2 = (0x10000080UL), - DMA2_IT_GL3 = (0x10000100UL), - DMA2_IT_TC3 = (0x10000200UL), - DMA2_IT_HT3 = (0x10000400UL), - DMA2_IT_TE3 = (0x10000800UL), - DMA2_IT_GL4 = (0x10001000UL), - DMA2_IT_TC4 = (0x10002000UL), - DMA2_IT_HT4 = (0x10004000UL), - DMA2_IT_TE4 = (0x10008000UL), - DMA2_IT_GL5 = (0x10010000UL), - DMA2_IT_TC5 = (0x10020000UL), - DMA2_IT_HT5 = (0x10040000UL), - DMA2_IT_TE5 = (0x10080000UL), -} DMA_Interrupts_TypeDef; -typedef enum { - DMAx_FLAG_GLy = (0x00000001UL), - DMAx_FLAG_TCy = (0x00000002UL), - DMAx_FLAG_HTy = (0x00000004UL), - DMAx_FLAG_TEy = (0x00000008UL), - DMA1_FLAG_GL1 = (0x00000001UL), - DMA1_FLAG_TC1 = (0x00000002UL), - DMA1_FLAG_HT1 = (0x00000004UL), - DMA1_FLAG_TE1 = (0x00000008UL), - DMA1_FLAG_GL2 = (0x00000010UL), - DMA1_FLAG_TC2 = (0x00000020UL), - DMA1_FLAG_HT2 = (0x00000040UL), - DMA1_FLAG_TE2 = (0x00000080UL), - DMA1_FLAG_GL3 = (0x00000100UL), - DMA1_FLAG_TC3 = (0x00000200UL), - DMA1_FLAG_HT3 = (0x00000400UL), - DMA1_FLAG_TE3 = (0x00000800UL), - DMA1_FLAG_GL4 = (0x00001000UL), - DMA1_FLAG_TC4 = (0x00002000UL), - DMA1_FLAG_HT4 = (0x00004000UL), - DMA1_FLAG_TE4 = (0x00008000UL), - DMA1_FLAG_GL5 = (0x00010000UL), - DMA1_FLAG_TC5 = (0x00020000UL), - DMA1_FLAG_HT5 = (0x00040000UL), - DMA1_FLAG_TE5 = (0x00080000UL), - DMA1_FLAG_GL6 = (0x00100000UL), - DMA1_FLAG_TC6 = (0x00200000UL), - DMA1_FLAG_HT6 = (0x00400000UL), - DMA1_FLAG_TE6 = (0x00800000UL), - DMA1_FLAG_GL7 = (0x01000000UL), - DMA1_FLAG_TC7 = (0x02000000UL), - DMA1_FLAG_HT7 = (0x04000000UL), - DMA1_FLAG_TE7 = (0x08000000UL), - DMA2_FLAG_GL1 = (0x10000001UL), - DMA2_FLAG_TC1 = (0x10000002UL), - DMA2_FLAG_HT1 = (0x10000004UL), - DMA2_FLAG_TE1 = (0x10000008UL), - DMA2_FLAG_GL2 = (0x10000010UL), - DMA2_FLAG_TC2 = (0x10000020UL), - DMA2_FLAG_HT2 = (0x10000040UL), - DMA2_FLAG_TE2 = (0x10000080UL), - DMA2_FLAG_GL3 = (0x10000100UL), - DMA2_FLAG_TC3 = (0x10000200UL), - DMA2_FLAG_HT3 = (0x10000400UL), - DMA2_FLAG_TE3 = (0x10000800UL), - DMA2_FLAG_GL4 = (0x10001000UL), - DMA2_FLAG_TC4 = (0x10002000UL), - DMA2_FLAG_HT4 = (0x10004000UL), - DMA2_FLAG_TE4 = (0x10008000UL), - DMA2_FLAG_GL5 = (0x10010000UL), - DMA2_FLAG_TC5 = (0x10020000UL), - DMA2_FLAG_HT5 = (0x10040000UL), - DMA2_FLAG_TE5 = (0x10080000UL), -} DMA_Flags_TypeDef; -//////////////////////////////////////////////////////////////////////////////// -/// @brief DMA Init structure definition -//////////////////////////////////////////////////////////////////////////////// -typedef struct { - u32 DMA_PeripheralBaseAddr; ///< the peripheral base address for DMA Channeln. - u32 DMA_MemoryBaseAddr; ///< the memory base address for DMA Channeln. - DMA_data_transfer_direction_TypeDef DMA_DIR; ///< the peripheral is the source or destination. - u32 DMA_BufferSize; ///< Specifies the buffer size, in data unit, of the Buffer size - DMA_peripheral_incremented_mode_TypeDef DMA_PeripheralInc; ///< Specifies whether the Peripheral address increment or not - DMA_memory_incremented_mode_TypeDef DMA_MemoryInc; ///< Specifies whether the memory address register is increment or not - DMA_peripheral_data_size_TypeDef DMA_PeripheralDataSize; ///< Specifies the Peripheral data width. - DMA_memory_data_size_TypeDef DMA_MemoryDataSize; ///< Specifies the Memory data width. - DMA_circular_normal_mode_TypeDef DMA_Mode; ///< Specifies the operation mode of the DMA Channeln circular or normal mode. - DMA_priority_level_TypeDef DMA_Priority; ///< Specifies the software priority for the DMA priority level - DMA_memory_to_memory_TypeDef DMA_M2M; ///< Specifies if the DMA Channeln will be used in memory-to-memory transfer. - DMA_auto_reload_TypeDef DMA_Auto_reload; ///< Specifies if the DMA Channeln will auto reload the CNDTR register -} DMA_InitTypeDef; - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup DMA_Exported_Variables -/// @{ -#ifdef _HAL_DMA_C_ - -#define GLOBAL -#else -#define GLOBAL extern -#endif - -#undef GLOBAL -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup DMA_Exported_Functions -/// @{ - -void DMA_DeInit(DMA_Channel_TypeDef* channel); -void DMA_Init(DMA_Channel_TypeDef* channel, DMA_InitTypeDef* init_struct); -void DMA_StructInit(DMA_InitTypeDef* init_struct); -void DMA_Cmd(DMA_Channel_TypeDef* channel, FunctionalState state); -void DMA_ITConfig(DMA_Channel_TypeDef* channel, DMA_Interrupt_EN_TypeDef it, FunctionalState state); -void DMA_ClearFlag(DMA_Flags_TypeDef flag); -void DMA_ClearITPendingBit(DMA_Interrupts_TypeDef it); -void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* channel, u16 length); -u16 DMA_GetCurrDataCounter(DMA_Channel_TypeDef* channel); -FlagStatus DMA_GetFlagStatus(DMA_Flags_TypeDef flag); -ITStatus DMA_GetITStatus(DMA_Interrupts_TypeDef it); - -void exDMA_SetPeripheralAddress(DMA_Channel_TypeDef* channel, u32 addr); -void exDMA_SetTransmitLen(DMA_Channel_TypeDef* channel, u16 len); -void exDMA_SetMemoryAddress(DMA_Channel_TypeDef* channel, u32 addr); - -/// @} - -/// @} - -/// @} -//////////////////////////////////////////////////////////////////////////////// -#endif //__HAL_DMA_H -//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_eth.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_eth.h deleted file mode 100644 index 4000bbaa5..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_eth.h +++ /dev/null @@ -1,729 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file HAL_eth.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE HAL_eth.h EXAMPLES. -/// //////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -#ifndef __HAL_ETH_H -#define __HAL_ETH_H - -// Files includes -#include "types.h" -#include "mm32_device.h" -#include "HAL_eth_conf.h" -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup ETH_HAL -/// @brief ETH HAL modules -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup ETH_Exported_Types -/// @{ - - -//////////////////////////////////////////////////////////////////////////////// - -//////////////////////////////////////////////////////////////////////////////// -// ETH | Header | Extra | VLAN tag | Payload | CRC | -// Size | 14 | 2 | 4 | 46 ~ 1500 | 4 | -#define ETH_MAX_PACKET_SIZE 1524 -#define ETH_HEADER 14 ///< MAC Dest Addr 6 byte + MAC Src Addr 6 byte + Lenth/Type 2 byte -#define ETH_EXTRA 2 -#define VLAN_TAG 4 -#define ETH_PAYLOAD_MIN 46 -#define ETH_PAYLOAD_MAX 1500 -#define JUMBO_FRAME_PAYLOAD 9000 - -#ifndef ETH_RX_BUF_SIZE -#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE -#endif - -#ifndef ETH_RX_BUF_NUM -#define ETH_RX_BUF_NUM 4 -#endif - -#ifndef ETH_TX_BUF_SIZE -#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE -#endif - -#ifndef ETH_TX_BUF_NUM -#define ETH_TX_BUF_NUM 4 -#endif - -#define ETH_DMA_RDES_FL_Pos 16 ///< Ethernet DMA Received Frame Length Position - -#define ETH_WAKEUP_REGISTER_LENGTH 8 ///< ETHERNET Remote Wake-up frame register length - -#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17 ///< ETHERNET Missed frames counter Shift - -#define ETH_DMA_TDES_COLLISION_COUNTSHIFT 3 ///< ETHERNET DMA Tx descriptors Collision Count Shift -#define ETH_DMA_TDES_BUFFER2_SIZESHIFT 11 ///< ETHERNET DMA Tx descriptors Buffer2 Size Shift - -#define ETH_DMA_RDES_FRAME_LENGTHSHIFT 16 ///< ETHERNET DMA Rx descriptors Frame Length Shift -#define ETH_DMA_RDES_BUFFER2_SIZESHIFT 11 ///< ETHERNET DMA Rx descriptors Buffer2 Size Shift - -///< ETHERNET errors -#define ETH_ERROR ((u32)0) -#define ETH_SUCCESS ((u32)1) - - -#ifdef _HAL_ETH_C_ -#define GLOBAL - -#else -#define GLOBAL extern -#endif - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH Init Structure Definition -//////////////////////////////////////////////////////////////////////////////// -typedef struct { - __IO u32 ETH_AutoNegotiation; - __IO u32 ETH_Watchdog; - __IO u32 ETH_Jabber; - __IO u32 ETH_InterFrameGap; - __IO u32 ETH_CarrierSense; - __IO u32 ETH_Speed; - __IO u32 ETH_ReceiveOwn; - __IO u32 ETH_LoopbackMode; - __IO u32 ETH_Mode; - __IO u32 ETH_ChecksumOffload; - __IO u32 ETH_RetryTransmission; - __IO u32 ETH_AutomaticPadCRCStrip; - __IO u32 ETH_BackOffLimit; - __IO u32 ETH_DeferralCheck; - __IO u32 ETH_ReceiveAll; - __IO u32 ETH_SourceAddrFilter; - __IO u32 ETH_PassControlFrames; - __IO u32 ETH_BroadcastFramesReception; - __IO u32 ETH_DestinationAddrFilter; - __IO u32 ETH_PromiscuousMode; - __IO u32 ETH_MulticastFramesFilter; - __IO u32 ETH_UnicastFramesFilter; - __IO u32 ETH_HashTableHigh; - __IO u32 ETH_HashTableLow; - __IO u32 ETH_PauseTime; - __IO u32 ETH_ZeroQuantaPause; - __IO u32 ETH_PauseLowThreshold; - __IO u32 ETH_UnicastPauseFrameDetect; - __IO u32 ETH_ReceiveFlowControl; - __IO u32 ETH_TransmitFlowControl; - __IO u32 ETH_VLANTagComparison; - __IO u32 ETH_VLANTagIdentifier; - __IO u32 ETH_DropTCPIPChecksumErrorFrame; - __IO u32 ETH_ReceiveStoreForward; - __IO u32 ETH_FlushReceivedFrame; - __IO u32 ETH_TransmitStoreForward; - __IO u32 ETH_TransmitThresholdControl; - __IO u32 ETH_ForwardErrorFrames; - __IO u32 ETH_ForwardUndersizedGoodFrames; - __IO u32 ETH_ReceiveThresholdControl; - __IO u32 ETH_SecondFrameOperate; - __IO u32 ETH_AddressAlignedBeats; - __IO u32 ETH_FixedBurst; - __IO u32 ETH_RxDMABurstLength; - __IO u32 ETH_TxDMABurstLength; - __IO u32 ETH_DescriptorSkipLength; - __IO u32 ETH_DMAArbitration; -} ETH_InitTypeDef; - -typedef struct { - __IO u32 CS; ///< Control and Status - __IO u32 BL; ///< Buffer1, Buffer2 lengths - __IO u32 BUF1ADDR; ///< Buffer1 address pointer - __IO u32 BUF2NDADDR; ///< Buffer2 or next descriptor address pointer - -#ifdef USE_ENHANCED_DMA_DESCRIPTORS ///< Enhanced ETHERNET DMA PTP Descriptors - __IO u32 ExtendedStatus; ///< Extended status for PTP receive descriptor - __IO u32 Reserved1; ///< Reserved - __IO u32 TimeStampLow; ///< Time Stamp Low value for transmit and receive - __IO u32 TimeStampHigh; ///< Time Stamp High value for transmit and receive -#endif -} ETH_DMADESCTypeDef; - -typedef struct { - __IO u32 len; - __IO u32 buf; - __IO ETH_DMADESCTypeDef* ptrDesc; -} FrameTypeDef; - -typedef struct { - __IO ETH_DMADESCTypeDef* ptrFS_Rx_Desc; ///< First Segment Rx Desc - __IO ETH_DMADESCTypeDef* ptrLS_Rx_Desc; ///< Last Segment Rx Desc - __IO u32 cnt; ///< Segment count -} ETH_DMA_Rx_Frame_infos; - - - -#define ETH_DMA_TDES_OWN ((u32)0x80000000) ///< OWN bit: descriptor is owned by DMA engine -#define ETH_DMA_TDES_ES ((u32)0x00008000) ///< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT -#define ETH_DMA_TDES_JT ((u32)0x00004000) ///< Jabber Timeout -#define ETH_DMA_TDES_FF ((u32)0x00002000) ///< Frame Flushed: DMA/MTL flushed the frame due to SW flush -#define ETH_DMA_TDES_LCA ((u32)0x00000800) ///< Loss of Carrier: carrier lost during transmission -#define ETH_DMA_TDES_NC ((u32)0x00000400) ///< No Carrier: no carrier signal from the transceiver -#define ETH_DMA_TDES_LCO ((u32)0x00000200) ///< Late Collision: transmission aborted due to collision -#define ETH_DMA_TDES_EC ((u32)0x00000100) ///< Excessive Collision: transmission aborted after 16 collisions -#define ETH_DMA_TDES_VF ((u32)0x00000080) ///< VLAN Frame -#define ETH_DMA_TDES_CC ((u32)0x00000078) ///< Collision Count -#define ETH_DMA_TDES_ED ((u32)0x00000004) ///< Excessive Deferral -#define ETH_DMA_TDES_UF ((u32)0x00000002) ///< Underflow Error: late data arrival from the memory -#define ETH_DMA_TDES_DB ((u32)0x00000001) ///< Deferred Bit - -#define ETH_DMA_TDES_IC ((u32)0x80000000) ///< Interrupt on Completion -#define ETH_DMA_TDES_LS ((u32)0x40000000) ///< Last Segment -#define ETH_DMA_TDES_FS ((u32)0x20000000) ///< First Segment -#define ETH_DMA_TDES_DC ((u32)0x04000000) ///< Disable CRC -#define ETH_DMA_TDES_TER ((u32)0x02000000) ///< Transmit end of ring -#define ETH_DMA_TDES_TCH ((u32)0x01000000) ///< Second Address Chained -#define ETH_DMA_TDES_DP ((u32)0x00800000) ///< Disable Padding -#define ETH_DMA_TDES_TBS2 ((u32)0x003FF800) ///< Transmit Buffer 2 Size -#define ETH_DMA_TDES_TBS1 ((u32)0x000007FF) ///< Transmit Buffer 1 Size - -#define ETH_DMA_TDES_B1AP ((u32)0xFFFFFFFF) ///< Buffer 1 Address Pointer - -#define ETH_DMA_TDES_B2AP ((u32)0xFFFFFFFF) ///< Buffer 2 Address Pointer - -#if defined(USE_ENHANCED_DMA_DESCRIPTORS) -#define ETH_DMA_PTP_TDES_TTSL ((u32)0xFFFFFFFF) ///< Transmit Time Stamp Low -#define ETH_DMA_PTP_TDES_TTSH ((u32)0xFFFFFFFF) ///< Transmit Time Stamp High -#endif - -#define ETH_DMA_RDES_OWN ((u32)0x80000000) ///< OWN bit: descriptor is owned by DMA engine -#define ETH_DMA_RDES_AFM ((u32)0x40000000) ///< DA Filter Fail for the rx frame -#define ETH_DMA_RDES_FL ((u32)0x3FFF0000) ///< Receive descriptor frame length -#define ETH_DMA_RDES_ES ((u32)0x00008000) ///< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE -#define ETH_DMA_RDES_DE ((u32)0x00004000) ///< Descriptor error: no more descriptors for receive frame -#define ETH_DMA_RDES_SAF ((u32)0x00002000) ///< SA Filter Fail for the received frame -#define ETH_DMA_RDES_LE ((u32)0x00001000) ///< Frame size not matching with length field -#define ETH_DMA_RDES_OE ((u32)0x00000800) ///< Overflow Error: Frame was damaged due to buffer overflow -#define ETH_DMA_RDES_VLAN ((u32)0x00000400) ///< VLAN Tag: received frame is a VLAN frame -#define ETH_DMA_RDES_FS ((u32)0x00000200) ///< First descriptor of the frame -#define ETH_DMA_RDES_LS ((u32)0x00000100) ///< Last descriptor of the frame -#define ETH_DMA_RDES_IPV4HCE ((u32)0x00000080) ///< IPC Checksum Error: Rx Ipv4 header checksum error -#define ETH_DMA_RDES_LC ((u32)0x00000040) ///< Late collision occurred during reception -#define ETH_DMA_RDES_FT ((u32)0x00000020) ///< Frame type - Ethernet, otherwise 802.3 -#define ETH_DMA_RDES_RWT ((u32)0x00000010) ///< Receive Watchdog Timeout: watchdog timer expired during reception -#define ETH_DMA_RDES_RE ((u32)0x00000008) ///< Receive error: error reported by MII interface -#define ETH_DMA_RDES_DBE ((u32)0x00000004) ///< Dribble bit error: frame contains non int multiple of 8 bits -#define ETH_DMA_RDES_CE ((u32)0x00000002) ///< CRC error -#define ETH_DMA_RDES_MAMPCE ((u32)0x00000001) ///< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error - -#define ETH_DMA_RDES_DIC ((u32)0x80000000) ///< Disable Interrupt on Completion -#define ETH_DMA_RDES_RER ((u32)0x02000000) ///< Receive End of Ring -#define ETH_DMA_RDES_RCH ((u32)0x01000000) ///< Second Address Chained -#define ETH_DMA_RDES_RBS2 ((u32)0x003FF800) ///< Receive Buffer2 Size -#define ETH_DMA_RDES_RBS1 ((u32)0x000007FF) ///< Receive Buffer1 Size - -#define ETH_DMA_RDES_B1AP ((u32)0xFFFFFFFF) ///< Buffer 1 Address Pointer - -#define ETH_DMA_RDES_B2AP ((u32)0xFFFFFFFF) ///< Buffer 2 Address Pointer - - -#if defined(USE_ENHANCED_DMA_DESCRIPTORS) -#define ETH_DMA_PTP_RDES_PTPV ((u32)0x00002000) ///< PTP Version -#define ETH_DMA_PTP_RDES_PTPFT ((u32)0x00001000) ///< PTP Frame Type -#define ETH_DMA_PTP_RDES_PTPMT ((u32)0x00000F00) ///< PTP Message Type -#define ETH_DMA_PTP_RDES_PTPMT_Sync ((u32)0x00000100) ///< SYNC message (all clock types) -#define ETH_DMA_PTP_RDES_PTPMT_FollowUp ((u32)0x00000200) ///< FollowUp message (all clock types) -#define ETH_DMA_PTP_RDES_PTPMT_DelayReq ((u32)0x00000300) ///< DelayReq message (all clock types) -#define ETH_DMA_PTP_RDES_PTPMT_DelayResp ((u32)0x00000400) ///< DelayResp message (all clock types) -#define ETH_DMA_PTP_RDES_PTPMT_PdelayReq_Announce ((u32)0x00000500) ///< PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) -#define ETH_DMA_PTP_RDES_PTPMT_PdelayResp_Manag ((u32)0x00000600) ///< PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) -#define ETH_DMA_PTP_RDES_PTPMT_PdelayRespFollowUp_Signal ((u32)0x00000700) ///< PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) -#define ETH_DMA_PTP_RDES_IPV6PR ((u32)0x00000080) ///< IPv6 Packet Received -#define ETH_DMA_PTP_RDES_IPV4PR ((u32)0x00000040) ///< IPv4 Packet Received -#define ETH_DMA_PTP_RDES_IPCB ((u32)0x00000020) ///< IP Checksum Bypassed -#define ETH_DMA_PTP_RDES_IPPE ((u32)0x00000010) ///< IP Payload Error -#define ETH_DMA_PTP_RDES_IPHE ((u32)0x00000008) ///< IP Header Error -#define ETH_DMA_PTP_RDES_IPPT ((u32)0x00000007) ///< IP Payload Type -#define ETH_DMA_PTP_RDES_IPPT_UDP ((u32)0x00000001) ///< UDP payload encapsulated in the IP datagram -#define ETH_DMA_PTP_RDES_IPPT_TCP ((u32)0x00000002) ///< TCP payload encapsulated in the IP datagram -#define ETH_DMA_PTP_RDES_IPPT_ICMP ((u32)0x00000003) ///< ICMP payload encapsulated in the IP datagram - - - -#define ETH_DMA_PTP_RDES_TTSL ((u32)0xFFFFFFFF) ///< Receive Time Stamp Low -#define ETH_DMA_PTP_RDES_TTSH ((u32)0xFFFFFFFF) ///< Receive Time Stamp High -#endif - -//////////////////////////////////////////////////////////////////////////////// -#define PHY_READ_TIMEOUT ((u32)0x0004FFFF) -#define PHY_WRITE_TIMEOUT ((u32)0x0004FFFF) - -#define PHY_BCR 0 ///< Transceiver Basic Control Register -#define PHY_BSR 1 ///< Transceiver Basic Status Register - -#define PHY_Reset ((u16)0x8000) ///< PHY Reset -#define PHY_Loopback ((u16)0x4000) ///< Select loop-back mode -#define PHY_FULLDUPLEX_100M ((u16)0x2100) ///< Set the full-duplex mode at 100 Mb/s -#define PHY_HALFDUPLEX_100M ((u16)0x2000) ///< Set the half-duplex mode at 100 Mb/s -#define PHY_FULLDUPLEX_10M ((u16)0x0100) ///< Set the full-duplex mode at 10 Mb/s -#define PHY_HALFDUPLEX_10M ((u16)0x0000) ///< Set the half-duplex mode at 10 Mb/s -#define PHY_AutoNegotiation ((u16)0x1000) ///< Enable auto-negotiation function -#define PHY_Restart_AutoNegotiation ((u16)0x0200) ///< Restart auto-negotiation function -#define PHY_Powerdown ((u16)0x0800) ///< Select the power down mode -#define PHY_Isolate ((u16)0x0400) ///< Isolate PHY from MII - -#define PHY_AutoNego_Complete ((u16)0x0020) ///< Auto-Negotiation process completed -#define PHY_Linked_Status ((u16)0x0004) ///< Valid link established -#define PHY_Jabber_detection ((u16)0x0002) ///< Jabber condition detected - -//////////////////////////////////////////////////////////////////////////////// -#define ETH_AutoNegotiation_Enable ((u32)0x00000001) -#define ETH_AutoNegotiation_Disable ((u32)0x00000000) - -#define ETH_Watchdog_Enable ((u32)0x00000000) -#define ETH_Watchdog_Disable ((u32)0x00800000) - -#define ETH_Jabber_Enable ((u32)0x00000000) -#define ETH_Jabber_Disable ((u32)0x00400000) - -#define ETH_InterFrameGap_96Bit ((u32)0x00000000) ///< minimum IFG between frames during transmission is 96Bit -#define ETH_InterFrameGap_88Bit ((u32)0x00020000) ///< minimum IFG between frames during transmission is 88Bit -#define ETH_InterFrameGap_80Bit ((u32)0x00040000) ///< minimum IFG between frames during transmission is 80Bit -#define ETH_InterFrameGap_72Bit ((u32)0x00060000) ///< minimum IFG between frames during transmission is 72Bit -#define ETH_InterFrameGap_64Bit ((u32)0x00080000) ///< minimum IFG between frames during transmission is 64Bit -#define ETH_InterFrameGap_56Bit ((u32)0x000A0000) ///< minimum IFG between frames during transmission is 56Bit -#define ETH_InterFrameGap_48Bit ((u32)0x000C0000) ///< minimum IFG between frames during transmission is 48Bit -#define ETH_InterFrameGap_40Bit ((u32)0x000E0000) ///< minimum IFG between frames during transmission is 40Bit - -#define ETH_CarrierSense_Enable ((u32)0x00000000) -#define ETH_CarrierSense_Disable ((u32)0x00010000) - -#define ETH_Speed_10M ((u32)0x00000000) -#define ETH_Speed_100M ((u32)0x00004000) - -#define ETH_ReceiveOwn_Enable ((u32)0x00000000) -#define ETH_ReceiveOwn_Disable ((u32)0x00002000) - -#define ETH_LoopbackMode_Enable ((u32)0x00001000) -#define ETH_LoopbackMode_Disable ((u32)0x00000000) - -#define ETH_Mode_FullDuplex ((u32)0x00000800) -#define ETH_Mode_HalfDuplex ((u32)0x00000000) - -#define ETH_ChecksumOffload_Enable ((u32)0x00000400) -#define ETH_ChecksumOffload_Disable ((u32)0x00000000) - -#define ETH_RetryTransmission_Enable ((u32)0x00000000) -#define ETH_RetryTransmission_Disable ((u32)0x00000200) - -#define ETH_AutomaticPadCRCStrip_Enable ((u32)0x00000080) -#define ETH_AutomaticPadCRCStrip_Disable ((u32)0x00000000) - -#define ETH_BackOffLimit_10 ((u32)0x00000000) -#define ETH_BackOffLimit_8 ((u32)0x00000020) -#define ETH_BackOffLimit_4 ((u32)0x00000040) -#define ETH_BackOffLimit_1 ((u32)0x00000060) - -#define ETH_DeferralCheck_Enable ((u32)0x00000010) -#define ETH_DeferralCheck_Disable ((u32)0x00000000) - -#define ETH_ReceiveAll_Enable ((u32)0x80000000) -#define ETH_ReceiveAll_Disable ((u32)0x00000000) - -#define ETH_SourceAddrFilter_Normal_Enable ((u32)0x00000200) -#define ETH_SourceAddrFilter_Inverse_Enable ((u32)0x00000300) -#define ETH_SourceAddrFilter_Disable ((u32)0x00000000) - -#define ETH_PassControlFrames_BlockAll ((u32)0x00000040) ///< MAC filters all control frames from reaching the application -#define ETH_PassControlFrames_ForwardAll ((u32)0x00000080) ///< MAC forwards all control frames to application even if they fail the Address Filter -#define ETH_PassControlFrames_ForwardPassedAddrFilter ((u32)0x000000C0) ///< MAC forwards control frames that pass the Address Filter. - -#define ETH_BroadcastFramesReception_Enable ((u32)0x00000000) -#define ETH_BroadcastFramesReception_Disable ((u32)0x00000020) - -#define ETH_DestinationAddrFilter_Normal ((u32)0x00000000) -#define ETH_DestinationAddrFilter_Inverse ((u32)0x00000008) - -#define ETH_PromiscuousMode_Enable ((u32)0x00000001) -#define ETH_PromiscuousMode_Disable ((u32)0x00000000) - -#define ETH_MulticastFramesFilter_PerfectHashTable ((u32)0x00000404) -#define ETH_MulticastFramesFilter_HashTable ((u32)0x00000004) -#define ETH_MulticastFramesFilter_Perfect ((u32)0x00000000) -#define ETH_MulticastFramesFilter_None ((u32)0x00000010) - -#define ETH_UnicastFramesFilter_PerfectHashTable ((u32)0x00000402) -#define ETH_UnicastFramesFilter_HashTable ((u32)0x00000002) -#define ETH_UnicastFramesFilter_Perfect ((u32)0x00000000) - -#define ETH_ZeroQuantaPause_Enable ((u32)0x00000000) -#define ETH_ZeroQuantaPause_Disable ((u32)0x00000080) - -#define ETH_PauseLowThreshold_Minus4 ((u32)0x00000000) ///< Pause time minus 4 slot times -#define ETH_PauseLowThreshold_Minus28 ((u32)0x00000010) ///< Pause time minus 28 slot times -#define ETH_PauseLowThreshold_Minus144 ((u32)0x00000020) ///< Pause time minus 144 slot times -#define ETH_PauseLowThreshold_Minus256 ((u32)0x00000030) ///< Pause time minus 256 slot times - -#define ETH_UnicastPauseFrameDetect_Enable ((u32)0x00000008) -#define ETH_UnicastPauseFrameDetect_Disable ((u32)0x00000000) - -#define ETH_ReceiveFlowControl_Enable ((u32)0x00000004) -#define ETH_ReceiveFlowControl_Disable ((u32)0x00000000) - -#define ETH_TransmitFlowControl_Enable ((u32)0x00000002) -#define ETH_TransmitFlowControl_Disable ((u32)0x00000000) - -#define ETH_VLANTagComparison_12Bit ((u32)0x00010000) -#define ETH_VLANTagComparison_16Bit ((u32)0x00000000) - -#define ETH_MAC_FLAG_TST ((u32)0x00000200) ///< Time stamp trigger flag (on MAC) -#define ETH_MAC_FLAG_MMCT ((u32)0x00000040) ///< MMC transmit flag -#define ETH_MAC_FLAG_MMCR ((u32)0x00000020) ///< MMC receive flag -#define ETH_MAC_FLAG_MMC ((u32)0x00000010) ///< MMC flag (on MAC) -#define ETH_MAC_FLAG_PMT ((u32)0x00000008) ///< PMT flag (on MAC) - -#define ETH_MAC_IT_TST ((u32)0x00000200) ///< Time stamp trigger interrupt (on MAC) -#define ETH_MAC_IT_MMCT ((u32)0x00000040) ///< MMC transmit interrupt -#define ETH_MAC_IT_MMCR ((u32)0x00000020) ///< MMC receive interrupt -#define ETH_MAC_IT_MMC ((u32)0x00000010) ///< MMC interrupt (on MAC) -#define ETH_MAC_IT_PMT ((u32)0x00000008) ///< PMT interrupt (on MAC) - -#define ETH_MAC_Address0 ((u32)0x00000000) -#define ETH_MAC_Address1 ((u32)0x00000008) -#define ETH_MAC_Address2 ((u32)0x00000010) -#define ETH_MAC_Address3 ((u32)0x00000018) - -#define ETH_MAC_AddressFilter_SA ((u32)0x00000000) -#define ETH_MAC_AddressFilter_DA ((u32)0x00000008) - -#define ETH_MAC_AddressMask_Byte6 ((u32)0x20000000) ///< Mask MAC Address high reg bits [15:8] -#define ETH_MAC_AddressMask_Byte5 ((u32)0x10000000) ///< Mask MAC Address high reg bits [7:0] -#define ETH_MAC_AddressMask_Byte4 ((u32)0x08000000) ///< Mask MAC Address low reg bits [31:24] -#define ETH_MAC_AddressMask_Byte3 ((u32)0x04000000) ///< Mask MAC Address low reg bits [23:16] -#define ETH_MAC_AddressMask_Byte2 ((u32)0x02000000) ///< Mask MAC Address low reg bits [15:8] -#define ETH_MAC_AddressMask_Byte1 ((u32)0x01000000) ///< Mask MAC Address low reg bits [70] - -//////////////////////////////////////////////////////////////////////////////// -#define ETH_DMA_TDES_LastSegment ((u32)0x40000000) ///< Last Segment -#define ETH_DMA_TDES_FirstSegment ((u32)0x20000000) ///< First Segment - -#define ETH_DMA_TDES_ChecksumByPass ((u32)0x00000000) ///< Checksum engine bypass -#define ETH_DMA_TDES_ChecksumIPV4Header ((u32)0x00400000) ///< IPv4 header checksum insertion -#define ETH_DMA_TDES_ChecksumTCPUDPICMPSegment ((u32)0x00800000) ///< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present -#define ETH_DMA_TDES_ChecksumTCPUDPICMPFull ((u32)0x00C00000) ///< TCP/UDP/ICMP checksum fully in hardware including pseudo header - -#define ETH_DMA_RDES_Buffer1 ((u32)0x00000000) ///< DMA Rx Desc Buffer1 -#define ETH_DMA_RDES_Buffer2 ((u32)0x00000001) ///< DMA Rx Desc Buffer2 - -#define ETH_DropTCPIPChecksumErrorFrame_Enable ((u32)0x00000000) -#define ETH_DropTCPIPChecksumErrorFrame_Disable ((u32)0x04000000) - -#define ETH_ReceiveStoreForward_Enable ((u32)0x02000000) -#define ETH_ReceiveStoreForward_Disable ((u32)0x00000000) - -#define ETH_FlushReceivedFrame_Enable ((u32)0x00000000) -#define ETH_FlushReceivedFrame_Disable ((u32)0x01000000) - -#define ETH_TransmitStoreForward_Enable ((u32)0x00200000) -#define ETH_TransmitStoreForward_Disable ((u32)0x00000000) - -#define ETH_TransmitThresholdControl_64Bytes ((u32)0x00000000) ///< threshold level of the MTL Transmit FIFO is 64 Bytes -#define ETH_TransmitThresholdControl_128Bytes ((u32)0x00004000) ///< threshold level of the MTL Transmit FIFO is 128 Bytes -#define ETH_TransmitThresholdControl_192Bytes ((u32)0x00008000) ///< threshold level of the MTL Transmit FIFO is 192 Bytes -#define ETH_TransmitThresholdControl_256Bytes ((u32)0x0000C000) ///< threshold level of the MTL Transmit FIFO is 256 Bytes -#define ETH_TransmitThresholdControl_40Bytes ((u32)0x00010000) ///< threshold level of the MTL Transmit FIFO is 40 Bytes -#define ETH_TransmitThresholdControl_32Bytes ((u32)0x00014000) ///< threshold level of the MTL Transmit FIFO is 32 Bytes -#define ETH_TransmitThresholdControl_24Bytes ((u32)0x00018000) ///< threshold level of the MTL Transmit FIFO is 24 Bytes -#define ETH_TransmitThresholdControl_16Bytes ((u32)0x0001C000) ///< threshold level of the MTL Transmit FIFO is 16 Bytes - -#define ETH_ForwardErrorFrames_Enable ((u32)0x00000080) -#define ETH_ForwardErrorFrames_Disable ((u32)0x00000000) - -#define ETH_ForwardUndersizedGoodFrames_Enable ((u32)0x00000040) -#define ETH_ForwardUndersizedGoodFrames_Disable ((u32)0x00000000) - -#define ETH_ReceiveThresholdControl_64Bytes ((u32)0x00000000) ///< threshold level of the MTL Receive FIFO is 64 Bytes -#define ETH_ReceiveThresholdControl_32Bytes ((u32)0x00000008) ///< threshold level of the MTL Receive FIFO is 32 Bytes -#define ETH_ReceiveThresholdControl_96Bytes ((u32)0x00000010) ///< threshold level of the MTL Receive FIFO is 96 Bytes -#define ETH_ReceiveThresholdControl_128Bytes ((u32)0x00000018) ///< threshold level of the MTL Receive FIFO is 128 Bytes - -#define ETH_SecondFrameOperate_Enable ((u32)0x00000004) -#define ETH_SecondFrameOperate_Disable ((u32)0x00000000) - -#define ETH_AddressAlignedBeats_Enable ((u32)0x02000000) -#define ETH_AddressAlignedBeats_Disable ((u32)0x00000000) - -#define ETH_FixedBurst_Enable ((u32)0x00010000) -#define ETH_FixedBurst_Disable ((u32)0x00000000) - -#define ETH_RxDMABurstLength_1Beat ((u32)0x00020000) ///< maximum number of beats to be transferred in one RxDMA transaction is 1 -#define ETH_RxDMABurstLength_2Beat ((u32)0x00040000) ///< maximum number of beats to be transferred in one RxDMA transaction is 2 -#define ETH_RxDMABurstLength_4Beat ((u32)0x00080000) ///< maximum number of beats to be transferred in one RxDMA transaction is 4 -#define ETH_RxDMABurstLength_8Beat ((u32)0x00100000) ///< maximum number of beats to be transferred in one RxDMA transaction is 8 -#define ETH_RxDMABurstLength_16Beat ((u32)0x00200000) ///< maximum number of beats to be transferred in one RxDMA transaction is 16 -#define ETH_RxDMABurstLength_32Beat ((u32)0x00400000) ///< maximum number of beats to be transferred in one RxDMA transaction is 32 -#define ETH_RxDMABurstLength_4xPBL_4Beat ((u32)0x01020000) ///< maximum number of beats to be transferred in one RxDMA transaction is 4 -#define ETH_RxDMABurstLength_4xPBL_8Beat ((u32)0x01040000) ///< maximum number of beats to be transferred in one RxDMA transaction is 8 -#define ETH_RxDMABurstLength_4xPBL_16Beat ((u32)0x01080000) ///< maximum number of beats to be transferred in one RxDMA transaction is 16 -#define ETH_RxDMABurstLength_4xPBL_32Beat ((u32)0x01100000) ///< maximum number of beats to be transferred in one RxDMA transaction is 32 -#define ETH_RxDMABurstLength_4xPBL_64Beat ((u32)0x01200000) ///< maximum number of beats to be transferred in one RxDMA transaction is 64 -#define ETH_RxDMABurstLength_4xPBL_128Beat ((u32)0x01400000) ///< maximum number of beats to be transferred in one RxDMA transaction is 128 - -#define ETH_TxDMABurstLength_1Beat ((u32)0x00000100) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 -#define ETH_TxDMABurstLength_2Beat ((u32)0x00000200) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 -#define ETH_TxDMABurstLength_4Beat ((u32)0x00000400) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 -#define ETH_TxDMABurstLength_8Beat ((u32)0x00000800) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 -#define ETH_TxDMABurstLength_16Beat ((u32)0x00001000) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 -#define ETH_TxDMABurstLength_32Beat ((u32)0x00002000) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 -#define ETH_TxDMABurstLength_4xPBL_4Beat ((u32)0x01000100) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 -#define ETH_TxDMABurstLength_4xPBL_8Beat ((u32)0x01000200) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 -#define ETH_TxDMABurstLength_4xPBL_16Beat ((u32)0x01000400) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 -#define ETH_TxDMABurstLength_4xPBL_32Beat ((u32)0x01000800) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 -#define ETH_TxDMABurstLength_4xPBL_64Beat ((u32)0x01001000) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 -#define ETH_TxDMABurstLength_4xPBL_128Beat ((u32)0x01002000) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 - -#define ETH_DMAArbitration_RoundRobin_RxTx_1_1 ((u32)0x00000000) -#define ETH_DMAArbitration_RoundRobin_RxTx_2_1 ((u32)0x00004000) -#define ETH_DMAArbitration_RoundRobin_RxTx_3_1 ((u32)0x00008000) -#define ETH_DMAArbitration_RoundRobin_RxTx_4_1 ((u32)0x0000C000) -#define ETH_DMAArbitration_RxPriorTx ((u32)0x00000002) - -#define ETH_DMA_FLAG_TST ((u32)0x20000000) ///< Time-stamp trigger interrupt (on DMA) -#define ETH_DMA_FLAG_PMT ((u32)0x10000000) ///< PMT interrupt (on DMA) -#define ETH_DMA_FLAG_MMC ((u32)0x08000000) ///< MMC interrupt (on DMA) -#define ETH_DMA_FLAG_DataTransferError ((u32)0x00800000) ///< Error bits 0-Rx DMA, 1-Tx DMA -#define ETH_DMA_FLAG_ReadWriteError ((u32)0x01000000) ///< Error bits 0-write trnsf, 1-read transfr -#define ETH_DMA_FLAG_AccessError ((u32)0x02000000) ///< Error bits 0-data buffer, 1-desc. access -#define ETH_DMA_FLAG_NIS ((u32)0x00010000) ///< Normal interrupt summary flag -#define ETH_DMA_FLAG_AIS ((u32)0x00008000) ///< Abnormal interrupt summary flag -#define ETH_DMA_FLAG_ER ((u32)0x00004000) ///< Early receive flag -#define ETH_DMA_FLAG_FBE ((u32)0x00002000) ///< Fatal bus error flag -#define ETH_DMA_FLAG_ET ((u32)0x00000400) ///< Early transmit flag -#define ETH_DMA_FLAG_RWT ((u32)0x00000200) ///< Receive watchdog timeout flag -#define ETH_DMA_FLAG_RPS ((u32)0x00000100) ///< Receive process stopped flag -#define ETH_DMA_FLAG_RBU ((u32)0x00000080) ///< Receive buffer unavailable flag -#define ETH_DMA_FLAG_R ((u32)0x00000040) ///< Receive flag -#define ETH_DMA_FLAG_TU ((u32)0x00000020) ///< Underflow flag -#define ETH_DMA_FLAG_RO ((u32)0x00000010) ///< Overflow flag -#define ETH_DMA_FLAG_TJT ((u32)0x00000008) ///< Transmit jabber timeout flag -#define ETH_DMA_FLAG_TBU ((u32)0x00000004) ///< Transmit buffer unavailable flag -#define ETH_DMA_FLAG_TPS ((u32)0x00000002) ///< Transmit process stopped flag -#define ETH_DMA_FLAG_T ((u32)0x00000001) ///< Transmit flag - -#define ETH_DMA_IT_TST ((u32)0x20000000) ///< Time-stamp trigger interrupt (on DMA) -#define ETH_DMA_IT_PMT ((u32)0x10000000) ///< PMT interrupt (on DMA) -#define ETH_DMA_IT_MMC ((u32)0x08000000) ///< MMC interrupt (on DMA) -#define ETH_DMA_IT_NIS ((u32)0x00010000) ///< Normal interrupt summary -#define ETH_DMA_IT_AIS ((u32)0x00008000) ///< Abnormal interrupt summary -#define ETH_DMA_IT_ER ((u32)0x00004000) ///< Early receive interrupt -#define ETH_DMA_IT_FBE ((u32)0x00002000) ///< Fatal bus error interrupt -#define ETH_DMA_IT_ET ((u32)0x00000400) ///< Early transmit interrupt -#define ETH_DMA_IT_RWT ((u32)0x00000200) ///< Receive watchdog timeout interrupt -#define ETH_DMA_IT_RPS ((u32)0x00000100) ///< Receive process stopped interrupt -#define ETH_DMA_IT_RBU ((u32)0x00000080) ///< Receive buffer unavailable interrupt -#define ETH_DMA_IT_R ((u32)0x00000040) ///< Receive interrupt -#define ETH_DMA_IT_TU ((u32)0x00000020) ///< Underflow interrupt -#define ETH_DMA_IT_RO ((u32)0x00000010) ///< Overflow interrupt -#define ETH_DMA_IT_TJT ((u32)0x00000008) ///< Transmit jabber timeout interrupt -#define ETH_DMA_IT_TBU ((u32)0x00000004) ///< Transmit buffer unavailable interrupt -#define ETH_DMA_IT_TPS ((u32)0x00000002) ///< Transmit process stopped interrupt -#define ETH_DMA_IT_T ((u32)0x00000001) ///< Transmit interrupt - -#define ETH_DMA_TransmitProcess_Stopped ((u32)0x00000000) ///< Stopped - Reset or Stop Tx Command issued -#define ETH_DMA_TransmitProcess_Fetching ((u32)0x00100000) ///< Running - fetching the Tx descriptor -#define ETH_DMA_TransmitProcess_Waiting ((u32)0x00200000) ///< Running - waiting for status -#define ETH_DMA_TransmitProcess_Reading ((u32)0x00300000) ///< Running - reading the data from host memory -#define ETH_DMA_TransmitProcess_Suspended ((u32)0x00600000) ///< Suspended - Tx Descriptor unavailable -#define ETH_DMA_TransmitProcess_Closing ((u32)0x00700000) ///< Running - closing Rx descriptor - -#define ETH_DMA_ReceiveProcess_Stopped ((u32)0x00000000) ///< Stopped - Reset or Stop Rx Command issued -#define ETH_DMA_ReceiveProcess_Fetching ((u32)0x00020000) ///< Running - fetching the Rx descriptor -#define ETH_DMA_ReceiveProcess_Waiting ((u32)0x00060000) ///< Running - waiting for packet -#define ETH_DMA_ReceiveProcess_Suspended ((u32)0x00080000) ///< Suspended - Rx Descriptor unavailable -#define ETH_DMA_ReceiveProcess_Closing ((u32)0x000A0000) ///< Running - closing descriptor -#define ETH_DMA_ReceiveProcess_Queuing ((u32)0x000E0000) ///< Running - queuing the receive frame into host memory - -#define ETH_DMA_Overflow_RxFIFOCounter ((u32)0x10000000) ///< Overflow bit for FIFO overflow counter -#define ETH_DMA_Overflow_MissedFrameCounter ((u32)0x00010000) ///< Overflow bit for missed frame counter - -//////////////////////////////////////////////////////////////////////////////// -#define ETH_PMT_FLAG_WUFFRPR ((u32)0x80000000) ///< Wake-Up Frame Filter Register Pointer Reset -#define ETH_PMT_FLAG_WUFR ((u32)0x00000040) ///< Wake-Up Frame Received -#define ETH_PMT_FLAG_MPR ((u32)0x00000020) ///< Magic Packet Received - -//////////////////////////////////////////////////////////////////////////////// -#define ETH_MMC_IT_TGF ((u32)0x00200000) ///< When Tx good frame counter reaches half the maximum value -#define ETH_MMC_IT_TGFMSC ((u32)0x00008000) ///< When Tx good multi col counter reaches half the maximum value -#define ETH_MMC_IT_TGFSC ((u32)0x00004000) ///< When Tx good single col counter reaches half the maximum value - -#define ETH_MMC_IT_RGUF ((u32)0x10020000) ///< When Rx good unicast frames counter reaches half the maximum value -#define ETH_MMC_IT_RFAE ((u32)0x10000040) ///< When Rx alignment error counter reaches half the maximum value -#define ETH_MMC_IT_RFCE ((u32)0x10000020) ///< When Rx crc error counter reaches half the maximum value - -#define ETH_MMCCR ((u32)0x00000100) ///< MMC CR register -#define ETH_MMCRIR ((u32)0x00000104) ///< MMC RIR register -#define ETH_MMCTIR ((u32)0x00000108) ///< MMC TIR register -#define ETH_MMCRIMR ((u32)0x0000010C) ///< MMC RIMR register -#define ETH_MMCTIMR ((u32)0x00000110) ///< MMC TIMR register -#define ETH_MMCTGFSCCR ((u32)0x0000014C) ///< MMC TGFSCCR register -#define ETH_MMCTGFMSCCR ((u32)0x00000150) ///< MMC TGFMSCCR register -#define ETH_MMCTGFCR ((u32)0x00000168) ///< MMC TGFCR register -#define ETH_MMCRFCECR ((u32)0x00000194) ///< MMC RFCECR register -#define ETH_MMCRFAECR ((u32)0x00000198) ///< MMC RFAECR register -#define ETH_MMCRGUFCR ((u32)0x000001C4) ///< MMC RGUFCR register - -//////////////////////////////////////////////////////////////////////////////// -#define ETH_PTP_FineUpdate ((u32)0x00000001) ///< Fine Update method -#define ETH_PTP_CoarseUpdate ((u32)0x00000000) ///< Coarse Update method - -#define ETH_PTP_FLAG_TSARU ((u32)0x00000020) ///< Addend Register Update -#define ETH_PTP_FLAG_TSITE ((u32)0x00000010) ///< Time Stamp Interrupt Trigger -#define ETH_PTP_FLAG_TSSTU ((u32)0x00000008) ///< Time Stamp Update -#define ETH_PTP_FLAG_TSSTI ((u32)0x00000004) ///< Time Stamp Initialize - -#define ETH_PTP_FLAG_TSTTR ((u32)0x10000002) ///< Time stamp target time reached -#define ETH_PTP_FLAG_TSSO ((u32)0x10000001) ///< Time stamp seconds overflow - -#define ETH_PTP_PositiveTime ((u32)0x00000000) ///< Positive time value -#define ETH_PTP_NegativeTime ((u32)0x80000000) ///< Negative time value - -#define ETH_PTPTSCR ((u32)0x00000700) ///< PTP TSCR register -#define ETH_PTPSSIR ((u32)0x00000704) ///< PTP SSIR register -#define ETH_PTPTSHR ((u32)0x00000708) ///< PTP TSHR register -#define ETH_PTPTSLR ((u32)0x0000070C) ///< PTP TSLR register -#define ETH_PTPTSHUR ((u32)0x00000710) ///< PTP TSHUR register -#define ETH_PTPTSLUR ((u32)0x00000714) ///< PTP TSLUR register -#define ETH_PTPTSAR ((u32)0x00000718) ///< PTP TSAR register -#define ETH_PTPTTHR ((u32)0x0000071C) ///< PTP TTHR register -#define ETH_PTPTTLR ((u32)0x00000720) ///< PTP TTLR register - -#define ETH_PTPTSSR ((u32)0x00000728) ///< PTP TSSR register - -#define ETH_PTP_OrdinaryClock ((u32)0x00000000) ///< Ordinary Clock -#define ETH_PTP_BoundaryClock ((u32)0x00010000) ///< Boundary Clock -#define ETH_PTP_EndToEndTransparentClock ((u32)0x00020000) ///< End To End Transparent Clock -#define ETH_PTP_PeerToPeerTransparentClock ((u32)0x00030000) ///< Peer To Peer Transparent Clock - -#define ETH_PTP_SnapshotMasterMessage ((u32)0x00008000) ///< Time stamp snapshot for message relevant to master enable -#define ETH_PTP_SnapshotEventMessage ((u32)0x00004000) ///< Time stamp snapshot for event message enable -#define ETH_PTP_SnapshotIPV4Frames ((u32)0x00002000) ///< Time stamp snapshot for IPv4 frames enable -#define ETH_PTP_SnapshotIPV6Frames ((u32)0x00001000) ///< Time stamp snapshot for IPv6 frames enable -#define ETH_PTP_SnapshotPTPOverEthernetFrames ((u32)0x00000800) ///< Time stamp snapshot for PTP over ethernet frames enable -#define ETH_PTP_SnapshotAllReceivedFrames ((u32)0x00000100) ///< Time stamp snapshot for all received frames enable - -#define ETH_MAC_ADDR_HBASE (ETH_BASE + 0x40) ///< ETHERNET MAC address high offset -#define ETH_MAC_ADDR_LBASE (ETH_BASE + 0x44) ///< ETHERNET MAC address low offset - -#define MACMIIAR_CR_MASK ((u32)0xFFFFFFE3) - -#define MACCR_CLEAR_MASK ((u32)0xFF20810F) -#define MACFCR_CLEAR_MASK ((u32)0x0000FF41) -#define DMAOMR_CLEAR_MASK ((u32)0xF8DE3F23) - - - -GLOBAL __IO ETH_DMADESCTypeDef* DMATxDescToSet; -GLOBAL __IO ETH_DMADESCTypeDef* DMARxDescToGet; - -GLOBAL ETH_DMA_Rx_Frame_infos RX_Frame_Descriptor; -GLOBAL __IO ETH_DMA_Rx_Frame_infos* DMA_RX_FRAME_infos; -GLOBAL __IO u32 Frame_Rx_index; - -#undef GLOBAL - -void ETH_DeInit(void); -void ETH_StructInit(ETH_InitTypeDef* ptr); -u32 ETH_Init(ETH_InitTypeDef* ptr, u16 phy_addr); -void ETH_Start(void); -void ETH_Stop(void); -void ETH_MACTransmissionCmd(FunctionalState sta); -void ETH_MACReceptionCmd(FunctionalState sta); -FlagStatus ETH_GetFlowControlBusyStatus(void); -void ETH_InitiatePauseControlFrame(void); -void ETH_BackPressureActivationCmd(FunctionalState sta); -void ETH_MACAddressConfig(u32 reg_addr, u8* mac_addr); -void ETH_GetMACAddress(u32 reg_addr, u8* mac_addr); -void ETH_MACAddressPerfectFilterCmd(u32 reg_addr, FunctionalState sta); -void ETH_MACAddressFilterConfig(u32 reg_addr, u32 sta); -void ETH_MACAddressMaskBytesFilterConfig(u32 reg_addr, u32 mask_byte); -FrameTypeDef ETH_Get_Received_Frame(void); -FrameTypeDef ETH_Get_Received_Frame_interrupt(void); -u32 ETH_Prepare_Transmit_Descriptors(u16 len); -void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef* ptr_desc, u8* buf, u32 cnt); -u32 ETH_CheckFrameReceived(void); -void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef* ptr_desc, u8* buf, u32 cnt); -FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef* ptr_desc, u32 flag); -u32 ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef* ptr_desc); -void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef* ptr_desc); -void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta); -void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef* ptr_desc, u32 val); -void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef* ptr_desc, u32 val); -void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta); -void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta); -void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta); -void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef* ptr_desc, u32 buf1_size, u32 buf2_size); -FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef* ptr_desc, u32 flag); -void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef* ptr_desc); -u32 ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef* ptr_desc); -void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta); -u32 ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef* ptr_desc, u32 buf); -u32 ETH_GetRxPktSize(ETH_DMADESCTypeDef* ptr_desc); -void ETH_SoftwareReset(void); -FlagStatus ETH_GetSoftwareResetStatus(void); -FlagStatus ETH_GetDMAFlagStatus(u32 flag); -void ETH_DMAClearFlag(u32 flag); -void ETH_DMAITConfig(u32 it, FunctionalState sta); -ITStatus ETH_GetDMAITStatus(u32 it); -void ETH_DMAClearITPendingBit(u32 it); -u32 ETH_GetTransmitProcessState(void); -u32 ETH_GetReceiveProcessState(void); -void ETH_FlushTransmitFIFO(void); -FlagStatus ETH_GetFlushTransmitFIFOStatus(void); -void ETH_DMATransmissionCmd(FunctionalState sta); -void ETH_DMAReceptionCmd(FunctionalState sta); -FlagStatus ETH_GetDMAOverflowStatus(u32 val); -u32 ETH_GetRxOverflowMissedFrameCounter(void); -u32 ETH_GetBufferUnavailableMissedFrameCounter(void); -u32 ETH_GetCurrentTxDescStartAddress(void); -u32 ETH_GetCurrentRxDescStartAddress(void); -u32 ETH_GetCurrentTxBufferAddress(void); -u32 ETH_GetCurrentRxBufferAddress(void); -void ETH_ResumeDMATransmission(void); -void ETH_ResumeDMAReception(void); -void ETH_SetReceiveWatchdogTimer(u8 val); -u16 ETH_ReadPHYRegister(u16 addr, u16 reg); -u16 ETH_WritePHYRegister(u16 addr, u16 reg, u16 val); -u32 ETH_PHYLoopBackCmd(u16 addr, FunctionalState sta); -void ETH_ResetWakeUpFrameFilterRegisterPointer(void); -void ETH_SetWakeUpFrameFilterRegister(u32* buf); -void ETH_GlobalUnicastWakeUpCmd(FunctionalState sta); -FlagStatus ETH_GetPMTFlagStatus(u32 flag); -void ETH_WakeUpFrameDetectionCmd(FunctionalState sta); -void ETH_MagicPacketDetectionCmd(FunctionalState sta); -void ETH_PowerDownCmd(FunctionalState sta); -void ETH_MMCCounterFullPreset(void); -void ETH_MMCCounterHalfPreset(void); -void ETH_MMCCounterFreezeCmd(FunctionalState sta); -void ETH_MMCResetOnReadCmd(FunctionalState sta); -void ETH_MMCCounterRolloverCmd(FunctionalState sta); -void ETH_MMCCountersReset(void); -void ETH_MMCITConfig(u32 it, FunctionalState sta); -ITStatus ETH_GetMMCITStatus(u32 it); -u32 ETH_GetMMCRegister(u32 reg); - -/// @} - -/// @} - -/// @} -//////////////////////////////////////////////////////////////////////////////// -#endif //__HAL_ETH_H -//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_eth_conf.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_eth_conf.h deleted file mode 100644 index f00e17e63..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_eth_conf.h +++ /dev/null @@ -1,68 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_eth_conf.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE hal_eth_conf.h EXAMPLES. -/// //////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -#ifndef __HAL_ETH_CONF_H -#define __HAL_ETH_CONF_H -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup ETH_HAL -/// @brief ETH HAL modules -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup ETH_Exported_Types -/// @{ - - -// #define USE_ENHANCED_DMA_DESCRIPTORS -// #define CUSTOM_DRIVER_BUFFERS_CONFIG -#define DP83848 - -#ifdef CUSTOM_DRIVER_BUFFERS_CONFIG -#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE -#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE -#define ETH_RX_BUF_NUM 4 -#define ETH_TX_BUF_NUM 4 -#endif - -//////////////////////////////////////////////////////////////////////////////// -#if defined(DP83848) -#define PHY_SR ((u16)0x10) -#define PHY_SR_LINKSTATUS ((u16)0x0001) -#define PHY_SPEED_STATUS ((u16)0x0002) -#define PHY_DUPLEX_STATUS ((u16)0x0004) - -#define PHY_MICR ((u16)0x11) -#define PHY_MICR_INT_EN ((u16)0x0002) -#define PHY_MICR_INT_OE ((u16)0x0001) - -#define PHY_MISR ((u16)0x12) -#define PHY_MISR_LINK_INT_EN ((u16)0x0020) -#define PHY_LINK_STATUS ((u16)0x2000) -#endif - -/// @} - -/// @} - -/// @} -//////////////////////////////////////////////////////////////////////////////// -#endif //__HAL_ETH_CONF_H -//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_exti.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_exti.h deleted file mode 100644 index a90daff9c..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_exti.h +++ /dev/null @@ -1,181 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_exti.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE EXTI -/// FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#ifndef __HAL_EXTI_H -#define __HAL_EXTI_H - -// Files includes -#include "types.h" -#include "reg_common.h" -#include "reg_exti.h" - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup EXTI_HAL -/// @brief EXTI HAL modules -/// @{ - - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup EXTI_Exported_Types -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @brief EXTI mode enumeration -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - EXTI_Mode_Interrupt = 0x00, ///< EXTI interrupt mode - EXTI_Mode_Event = 0x04 ///< EXTI event mode -} EXTIMode_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief EXTI Trigger enumeration -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - EXTI_Trigger_Rising = 0x08, ///< EXTI rising edge triggering - EXTI_Trigger_Falling = 0x0C, ///< EXTI falling edge triggering - EXTI_Trigger_Rising_Falling = 0x10 ///< EXTI rising and falling edge triggers -} EXTITrigger_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief EXTI Init Structure definition -//////////////////////////////////////////////////////////////////////////////// -typedef struct { - u32 EXTI_Line; ///< Specifies the EXTI lines to be enabled or disabled. - ///< This parameter can be any combination of @ref EXTI_Lines - EXTIMode_TypeDef EXTI_Mode; ///< Specifies the mode for the EXTI lines. - ///< This parameter can be a value of @ref EXTIMode_TypeDef - EXTITrigger_TypeDef EXTI_Trigger; ///< Specifies the trigger signal active edge for the EXTI lines. - ///< This parameter can be a value of @ref EXTIMode_TypeDef - FunctionalState EXTI_LineCmd; ///< Specifies the new state of the selected EXTI lines. - ///< This parameter can be set either to ENABLE or DISABLE -} EXTI_InitTypeDef; - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup EXTI_Exported_Constants -/// @{ - - - -#define EXTI_LineNone ((u32)0x0000000) ///< No interrupt selected -#define EXTI_Line0 ((u32)0x0000001) ///< External interrupt line 0 -#define EXTI_Line1 ((u32)0x0000002) ///< External interrupt line 1 -#define EXTI_Line2 ((u32)0x0000004) ///< External interrupt line 2 -#define EXTI_Line3 ((u32)0x0000008) ///< External interrupt line 3 -#define EXTI_Line4 ((u32)0x0000010) ///< External interrupt line 4 -#define EXTI_Line5 ((u32)0x0000020) ///< External interrupt line 5 -#define EXTI_Line6 ((u32)0x0000040) ///< External interrupt line 6 -#define EXTI_Line7 ((u32)0x0000080) ///< External interrupt line 7 -#define EXTI_Line8 ((u32)0x0000100) ///< External interrupt line 8 -#define EXTI_Line9 ((u32)0x0000200) ///< External interrupt line 9 -#define EXTI_Line10 ((u32)0x0000400) ///< External interrupt line 10 -#define EXTI_Line11 ((u32)0x0000800) ///< External interrupt line 11 -#define EXTI_Line12 ((u32)0x0001000) ///< External interrupt line 12 -#define EXTI_Line13 ((u32)0x0002000) ///< External interrupt line 13 -#define EXTI_Line14 ((u32)0x0004000) ///< External interrupt line 14 -#define EXTI_Line15 ((u32)0x0008000) ///< External interrupt line 15 -#define EXTI_Line16 ((u32)0x0010000) ///< External interrupt line 16 Connected to the PVD Output -#define EXTI_Line17 ((u32)0x0020000) ///< External interrupt line 17 Connected to the RTC Alarm event -#define EXTI_Line18 ((u32)0x0040000) ///< External interrupt line 18 Connected to the USB Wakeup from suspend event -#define EXTI_Line19 ((u32)0x0080000) ///< External interrupt line 19 -#define EXTI_Line20 ((u32)0x0100000) ///< External interrupt line 20 -#define EXTI_Line21 ((u32)0x0200000) ///< External interrupt line 21 -#define EXTI_Line22 ((u32)0x0400000) ///< External interrupt line 22 -#define EXTI_Line23 ((u32)0x0800000) ///< External interrupt line 23 -#define EXTI_Line24 ((u32)0x1000000) ///< External interrupt line 24 - -#define EXTI_PortSourceGPIOA (0x00U) -#define EXTI_PortSourceGPIOB (0x01U) -#define EXTI_PortSourceGPIOC (0x02U) -#define EXTI_PortSourceGPIOD (0x03U) -#define EXTI_PortSourceGPIOE (0x04U) -#define EXTI_PortSourceGPIOF (0x05U) - -#define EXTI_PinSource0 (0x00U) -#define EXTI_PinSource1 (0x01U) -#define EXTI_PinSource2 (0x02U) -#define EXTI_PinSource3 (0x03U) -#define EXTI_PinSource4 (0x04U) -#define EXTI_PinSource5 (0x05U) -#define EXTI_PinSource6 (0x06U) -#define EXTI_PinSource7 (0x07U) -#define EXTI_PinSource8 (0x08U) -#define EXTI_PinSource9 (0x09U) -#define EXTI_PinSource10 (0x0AU) -#define EXTI_PinSource11 (0x0BU) -#define EXTI_PinSource12 (0x0CU) -#define EXTI_PinSource13 (0x0DU) -#define EXTI_PinSource14 (0x0EU) -#define EXTI_PinSource15 (0x0FU) - - - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup EXTI_Exported_Variables -/// @{ - -#ifdef _HAL_EXTI_C_ - -#define GLOBAL -#else -#define GLOBAL extern -#endif - -#undef GLOBAL - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup EXTI_Exported_Functions -/// @{ - -FlagStatus EXTI_GetFlagStatus(u32 line); -ITStatus EXTI_GetITStatus(u32 line); - -void EXTI_DeInit(void); -void EXTI_Init(EXTI_InitTypeDef* init_struct); -void EXTI_StructInit(EXTI_InitTypeDef* init_struct); -void EXTI_GenerateSWInterrupt(u32 line); -void EXTI_ClearFlag(u32 line); -void EXTI_ClearITPendingBit(u32 line); -void exEXTI_LineDisable(u32 line); -u32 exEXTI_GetAllFlagStatus(void); - - -void EXTI_MemoryRemapConfig(u32 memory_remap); -void EXTI_LineConfig(u8 port_source_gpio, u8 pin_source); - - -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -#endif // __HAL_EXTI_H -//////////////////////////////////////////////////////////////////////////////// - - - diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_flash.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_flash.h deleted file mode 100644 index ee313dee7..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_flash.h +++ /dev/null @@ -1,230 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_flash.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE FLASH -/// FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#ifndef __HAL_FLASH_H -#define __HAL_FLASH_H - -// Files includes -#include "types.h" -#include "reg_common.h" -#include "reg_flash.h" - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup FLASH_HAL -/// @brief FLASH HAL modules -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup FLASH_Exported_Types -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @brief FLASH Status -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - FLASH_BUSY = 1, ///< FLASH busy status - FLASH_ERROR_PG, ///< FLASH programming error status - FLASH_ERROR_WRP, ///< FLASH write protection error status - FLASH_COMPLETE, ///< FLASH end of operation status - FLASH_TIMEOUT ///< FLASH Last operation timed out status -} FLASH_Status; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief FLASH Latency -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - FLASH_Latency_0 = FLASH_ACR_LATENCY_0, ///< FLASH Zero Latency cycle - FLASH_Latency_1 = FLASH_ACR_LATENCY_1, ///< FLASH One Latency cycle - FLASH_Latency_2 = FLASH_ACR_LATENCY_2, ///< FLASH Two Latency cycles - FLASH_Latency_3 = FLASH_ACR_LATENCY_3 ///< FLASH Three Latency cycles -} FLASH_Latency_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Half_Cycle_Enable_Disable -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - FLASH_HalfCycleAccess_Enable = FLASH_ACR_HLFCYA, ///< FLASH Half Cycle Enable - FLASH_HalfCycleAccess_Disable = (s32)~FLASH_ACR_HLFCYA ///< FLASH Half Cycle Disable -} FLASH_HalfCycleAccess_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Prefetch_Buffer_Enable_Disable -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - FLASH_PrefetchBuffer_Enable = FLASH_ACR_PRFTBE, ///< FLASH Prefetch Buffer Enable - FLASH_PrefetchBuffer_Disable = (s32)~FLASH_ACR_PRFTBE ///< FLASH Prefetch Buffer Disable -} FLASH_PrefetchBuffer_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Option_Bytes_IWatchdog -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - OB_IWDG_SW = 0x0001, ///< Software IWDG selected - OB_IWDG_HW = 0x0000 ///< Hardware IWDG selected -} OB_IWDG_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Option_Bytes_nRST_STOP -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - OB_STOP_NoRST = 0x0002, ///< No reset generated when entering in STOP - OB_STOP_RST = 0x0000 ///< Reset generated when entering in STOP -} OB_STOP_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Option_Bytes_nRST_STDBY -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - OB_STDBY_NoRST = 0x0004, ///< No reset generated when entering in STANDBY - OB_STDBY_RST = 0x0000 ///< Reset generated when entering in STANDBY -} OB_STDBY_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief FLASH_Interrupts -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - FLASH_IT_ERROR = FLASH_CR_ERRIE, ///< FPEC error interrupt source - FLASH_IT_EOP = FLASH_CR_EOPIE ///< End of FLASH Operation Interrupt source -} FLASH_IT_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief FLASH_Flags -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - FLASH_FLAG_EOP = FLASH_SR_EOP, ///< FLASH End of Operation flag - FLASH_FLAG_PGERR = FLASH_SR_PGERR, ///< FLASH Program error flag - FLASH_FLAG_WRPRTERR = FLASH_SR_WRPRTERR, ///< FLASH Write protected error flag - FLASH_FLAG_BSY = FLASH_SR_BUSY, ///< FLASH Busy flag - FLASH_FLAG_OPTERR = FLASH_OBR_OPTERR ///< FLASH Option Byte error flag -} FLASH_FLAG_TypeDef; - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup FLASH_Exported_Constants -/// @{ - - -#define RDP_Key ((u16)0x00A5) -#define FLASH_KEY1 ((u32)0x45670123) -#define FLASH_KEY2 ((u32)0xCDEF89AB) -#define EraseTimeout ((u32)0x00000FFF) -#define ProgramTimeout ((u32)0x0000000F) - -#define FLASH_WRProt_Pages0to3 ((u32)0x00000001) ///< Write protection of page 0 to 3 -#define FLASH_WRProt_Pages4to7 ((u32)0x00000002) ///< Write protection of page 4 to 7 -#define FLASH_WRProt_Pages8to11 ((u32)0x00000004) ///< Write protection of page 8 to 11 -#define FLASH_WRProt_Pages12to15 ((u32)0x00000008) ///< Write protection of page 12 to 15 -#define FLASH_WRProt_Pages16to19 ((u32)0x00000010) ///< Write protection of page 16 to 19 -#define FLASH_WRProt_Pages20to23 ((u32)0x00000020) ///< Write protection of page 20 to 23 -#define FLASH_WRProt_Pages24to27 ((u32)0x00000040) ///< Write protection of page 24 to 27 -#define FLASH_WRProt_Pages28to31 ((u32)0x00000080) ///< Write protection of page 28 to 31 -#define FLASH_WRProt_Pages32to35 ((u32)0x00000100) ///< Write protection of page 32 to 35 -#define FLASH_WRProt_Pages36to39 ((u32)0x00000200) ///< Write protection of page 36 to 39 -#define FLASH_WRProt_Pages40to43 ((u32)0x00000400) ///< Write protection of page 40 to 43 -#define FLASH_WRProt_Pages44to47 ((u32)0x00000800) ///< Write protection of page 44 to 47 -#define FLASH_WRProt_Pages48to51 ((u32)0x00001000) ///< Write protection of page 48 to 51 -#define FLASH_WRProt_Pages52to55 ((u32)0x00002000) ///< Write protection of page 52 to 55 -#define FLASH_WRProt_Pages56to59 ((u32)0x00004000) ///< Write protection of page 56 to 59 -#define FLASH_WRProt_Pages60to63 ((u32)0x00008000) ///< Write protection of page 60 to 63 -#define FLASH_WRProt_Pages64to67 ((u32)0x00010000) ///< Write protection of page 64 to 67 -#define FLASH_WRProt_Pages68to71 ((u32)0x00020000) ///< Write protection of page 68 to 71 -#define FLASH_WRProt_Pages72to75 ((u32)0x00040000) ///< Write protection of page 72 to 75 -#define FLASH_WRProt_Pages76to79 ((u32)0x00080000) ///< Write protection of page 76 to 79 -#define FLASH_WRProt_Pages80to83 ((u32)0x00100000) ///< Write protection of page 80 to 83 -#define FLASH_WRProt_Pages84to87 ((u32)0x00200000) ///< Write protection of page 84 to 87 -#define FLASH_WRProt_Pages88to91 ((u32)0x00400000) ///< Write protection of page 88 to 91 -#define FLASH_WRProt_Pages92to95 ((u32)0x00800000) ///< Write protection of page 92 to 95 -#define FLASH_WRProt_Pages96to99 ((u32)0x01000000) ///< Write protection of page 96 to 99 -#define FLASH_WRProt_Pages100to103 ((u32)0x02000000) ///< Write protection of page 100 to 103 -#define FLASH_WRProt_Pages104to107 ((u32)0x04000000) ///< Write protection of page 104 to 107 -#define FLASH_WRProt_Pages108to111 ((u32)0x08000000) ///< Write protection of page 108 to 111 -#define FLASH_WRProt_Pages112to115 ((u32)0x10000000) ///< Write protection of page 112 to 115 -#define FLASH_WRProt_Pages116to119 ((u32)0x20000000) ///< Write protection of page 115 to 119 -#define FLASH_WRProt_Pages120to123 ((u32)0x40000000) ///< Write protection of page 120 to 123 -#define FLASH_WRProt_Pages124to127 ((u32)0x80000000) ///< Write protection of page 124 to 127 - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup FLASH_Exported_Variables -/// @{ - -#ifdef _HAL_FLASH_C_ - -#define GLOBAL -#else -#define GLOBAL extern -#endif - -#undef GLOBAL - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup FLASH_Exported_Functions -/// @{ -void FLASH_SetLatency(FLASH_Latency_TypeDef latency); -void FLASH_HalfCycleAccessCmd(FLASH_HalfCycleAccess_TypeDef half_cycle_access); -void FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_TypeDef prefetch_buffer); -void FLASH_Unlock(void); -void FLASH_Lock(void); -void FLASH_OPTB_Enable(void); -void FLASH_ITConfig(FLASH_IT_TypeDef interrupt, FunctionalState state); -void FLASH_ClearFlag(u16 flag); -void exFLASH_EraseEE(u32 page_address); -void exFLASH_ProgramEE(u16* buf, u32 address, u16 len); -void exFLASH_WriteEE(u16* buf, u32 page_address, u16 len); -void* exFLASH_Locate(u32 page_address, u16 len); -void* exFLASH_ReadEE(u32 page_address, u16 len); - -u8 exFLASH_FindEmpty(u16* ptr, u16 len); -u32 FLASH_GetUserOptionByte(void); -u32 FLASH_GetWriteProtectionOptionByte(void); - -FLASH_Status FLASH_ErasePage(u32 page_address); -FLASH_Status FLASH_EraseAllPages(void); -FLASH_Status FLASH_EraseOptionBytes(void); -FLASH_Status FLASH_EraseProtect(void); -FLASH_Status FLASH_ProgramHalfWord(u32 address, u16 data); -FLASH_Status FLASH_ProgramWord(u32 address, u32 data); -FLASH_Status FLASH_ProgramOptionHalfWord(u32 address, u16 data); -FLASH_Status FLASH_ProgramOptionByteData(u32 address, u8 data); -FLASH_Status FLASH_ProgramProtect(u32 address, u16 data); -FLASH_Status FLASH_EnableWriteProtection(u32 page); -FLASH_Status FLASH_UserOptionByteConfig(OB_IWDG_TypeDef ob_iwdg, OB_STOP_TypeDef ob_stop, OB_STDBY_TypeDef ob_standby); -FLASH_Status FLASH_GetStatus(void); -FLASH_Status FLASH_WaitForLastOperation(u32 time_out); -FLASH_Status FLASH_ReadOutProtection(FunctionalState state); -FlagStatus FLASH_GetPrefetchBufferStatus(void); -FlagStatus FLASH_GetFlagStatus(u16 flag); - -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -#endif //__HAL_FLASH_H -//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_fsmc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_fsmc.h deleted file mode 100644 index dbfe38166..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_fsmc.h +++ /dev/null @@ -1,147 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_fsmc.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SDIO -/// FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#ifndef __HAL_FSMC_H -#define __HAL_FSMC_H - -// Files includes -#include "types.h" -#include "reg_common.h" -#include "reg_fsmc.h" - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup FSMC_HAL -/// @brief FSMC HAL modules -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup FSMC_Exported_Types -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @brief FSMC_interrupts_define -//////////////////////////////////////////////////////////////////////////////// - - - - - -// Timing parameter configuration register set selection register set0 register set1 register set2 - -#define FSMC_TimingRegSelect_0 ((u32)0x00000000) -#define FSMC_TimingRegSelect_1 ((u32)0x00000100) -#define FSMC_TimingRegSelect_2 ((u32)0x00000200) - -// Capacity of external device -#define FSMC_MemSize_None ((u32)0x00000000) -#define FSMC_MemSize_64KB ((u32)0x00000001) -#define FSMC_MemSize_128KB ((u32)0x00000002) -#define FSMC_MemSize_256KB ((u32)0x00000002) -#define FSMC_MemSize_512KB ((u32)0x00000004) -#define FSMC_MemSize_1MB ((u32)0x00000005) -#define FSMC_MemSize_2MB ((u32)0x00000006) -#define FSMC_MemSize_4MB ((u32)0x00000007) -#define FSMC_MemSize_8MB ((u32)0x00000008) -#define FSMC_MemSize_16MB ((u32)0x00000009) -#define FSMC_MemSize_32MB ((u32)0x0000000A) -#define FSMC_MemSize_64MB ((u32)0x0000000B) -#define FSMC_MemSize_128MB ((u32)0x0000000C) -#define FSMC_MemSize_256MB ((u32)0x0000000D) -#define FSMC_MemSize_512MB ((u32)0x0000000E) -#define FSMC_MemSize_1GB ((u32)0x0000000F) -#define FSMC_MemSize_2GB ((u32)0x00000010) -#define FSMC_MemSize_4GB ((u32)0x00000011) - - -// Memory data bus bit width setting -typedef enum { - FSMC_DataWidth_16bits = (0x0000), //16bits - FSMC_DataWidth_32bits = (0x0001), //32bits - FSMC_DataWidth_64bits = (0x0002), //64bits - FSMC_DataWidth_128bits = (0x0003), //128bits - FSMC_DataWidth_8bits = (0x0004), //8bits -} FSMC_NORSRAM_DataWidth_TypeDef; - -typedef enum { - FSMC_NORSRAM_BANK0 = 0, - FSMC_NORSRAM_BANK1 = 1, - FSMC_NORSRAM_BANK2 = 2, -} FSMC_NORSRAM_BANK_TypeDef; - -typedef struct { - u32 FSMC_SMReadPipe; //sm_read_pipe[1:0] The cycle of latching read data, that is, the cycle when ready_resp is pulled high - - u32 FSMC_ReadyMode; //Select whether the hready_resp signal comes from the FSMC IP internal or external DEVICE, only for writing and reading external DEVICE operations. - //0: Internal FSMC 1: External DEVICE (ie from FSMC_NWAIT) - u32 FSMC_WritePeriod; //Write cycle - - u32 FSMC_WriteHoldTime; //Address/data hold time during write operation - - u32 FSMC_AddrSetTime; //Address establishment time - - u32 FSMC_ReadPeriod; //Read cycle - - FSMC_NORSRAM_DataWidth_TypeDef FSMC_DataWidth; - -} FSMC_NORSRAM_Bank_InitTypeDef; - -typedef struct { - u32 FSMC_Mode; - u32 FSMC_TimingRegSelect; - u32 FSMC_MemSize; - u32 FSMC_MemType; - u32 FSMC_AddrDataMode; -} FSMC_InitTypeDef; - - -#define FSMC_MemType_SDRAM ((u32)0x0<<5) -#define FSMC_MemType_NorSRAM ((u32)0x1<<5) -#define FSMC_MemType_FLASH ((u32)0x2<<5) -#define FSMC_MemType_RESERVED ((u32)0x3<<5) -//SYSCFG_CFGR1 -#define FSMC_Mode_6800 ((u32)0x40000000) -#define FSMC_Mode_8080 ((u32)0x20000000) -#define FSMC_Mode_NorFlash ((u32)0x00000000) - -#define FSMC_AddrDataMUX ((u32)0x00000000) -#define FSMC_AddrDataDeMUX ((u32)0x10000000) - - - - -void FSMC_NORSRAMStructInit(FSMC_InitTypeDef* init_struct); -void FSMC_NORSRAM_BankStructInit(FSMC_NORSRAM_Bank_InitTypeDef* init_struct); -void FSMC_NORSRAMInit(FSMC_InitTypeDef* init_struct); -void FSMC_NORSRAM_Bank_Init(FSMC_NORSRAM_Bank_InitTypeDef* FSMC_Bank_InitStruct, FSMC_NORSRAM_BANK_TypeDef bank); - - - -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -#endif // __HAL_FSMC_H -//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_gpio.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_gpio.h deleted file mode 100644 index b28afd839..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_gpio.h +++ /dev/null @@ -1,198 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_gpio.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE GPIO -/// FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#ifndef __HAL_GPIO_H -#define __HAL_GPIO_H - -// Files includes -#include "types.h" -#include "reg_gpio.h" - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup GPIO_HAL -/// @brief GPIO HAL modules -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup GPIO_Exported_Types -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Output Maximum frequency selection -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - GPIO_Speed_50MHz = 1, ///< Maximum speed is 50MHz - GPIO_Speed_20MHz, ///< Maximum speed is 20MHz - GPIO_Speed_10MHz ///< Maximum speed is 10MHz -} GPIOSpeed_TypeDef; - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configuration Mode enumeration -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - GPIO_Mode_AIN = 0x00, ///< Analog input - GPIO_Mode_FLOATING = 0x04, ///< Floating input - GPIO_Mode_IPD = 0x28, ///< Pull down input - GPIO_Mode_IPU = 0x48, ///< Pull up input - GPIO_Mode_Out_OD = 0x14, ///< Universal open drain output - GPIO_Mode_Out_PP = 0x10, ///< Universal push-pull output - GPIO_Mode_AF_OD = 0x1C, ///< Multiplex open drain output - GPIO_Mode_AF_PP = 0x18 ///< Multiplexed push-pull output -} GPIOMode_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Bit_SET and Bit_RESET enumeration -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - Bit_RESET = 0, ///< bit reset - Bit_SET ///< bit set -} BitAction; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief GPIO Init structure definition -//////////////////////////////////////////////////////////////////////////////// -typedef struct { - u16 GPIO_Pin; ///< GPIO_Pin - GPIOSpeed_TypeDef GPIO_Speed; ///< GPIO_Speed - GPIOMode_TypeDef GPIO_Mode; ///< GPIO_Mode -} GPIO_InitTypeDef; - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup GPIO_Exported_Constants -/// @{ - -#define GPIO_Speed_2MHz GPIO_Speed_20MHz - -#define GPIO_Pin_0 (0x0001U) ///< Pin 0 selected -#define GPIO_Pin_1 (0x0002U) ///< Pin 1 selected -#define GPIO_Pin_2 (0x0004U) ///< Pin 2 selected -#define GPIO_Pin_3 (0x0008U) ///< Pin 3 selected -#define GPIO_Pin_4 (0x0010U) ///< Pin 4 selected -#define GPIO_Pin_5 (0x0020U) ///< Pin 5 selected -#define GPIO_Pin_6 (0x0040U) ///< Pin 6 selected -#define GPIO_Pin_7 (0x0080U) ///< Pin 7 selected -#define GPIO_Pin_8 (0x0100U) ///< Pin 8 selected -#define GPIO_Pin_9 (0x0200U) ///< Pin 9 selected -#define GPIO_Pin_10 (0x0400U) ///< Pin 10 selected -#define GPIO_Pin_11 (0x0800U) ///< Pin 11 selected -#define GPIO_Pin_12 (0x1000U) ///< Pin 12 selected -#define GPIO_Pin_13 (0x2000U) ///< Pin 13 selected -#define GPIO_Pin_14 (0x4000U) ///< Pin 14 selected -#define GPIO_Pin_15 (0x8000U) ///< Pin 15 selected -#define GPIO_Pin_All (0xFFFFU) ///< All pins selected - - -#define GPIO_AF_0 (0x00U) ///< Alternative function 0 -#define GPIO_AF_1 (0x01U) ///< Alternative function 1 -#define GPIO_AF_2 (0x02U) ///< Alternative function 2 -#define GPIO_AF_3 (0x03U) ///< Alternative function 3 -#define GPIO_AF_4 (0x04U) ///< Alternative function 4 -#define GPIO_AF_5 (0x05U) ///< Alternative function 5 -#define GPIO_AF_6 (0x06U) ///< Alternative function 6 -#define GPIO_AF_7 (0x07U) ///< Alternative function 7 -#define GPIO_AF_8 (0x08U) ///< Alternative function 8 -#define GPIO_AF_9 (0x09U) ///< Alternative function 9 -#define GPIO_AF_10 (0x0AU) ///< Alternative function 10 -#define GPIO_AF_11 (0x0BU) ///< Alternative function 11 -#define GPIO_AF_12 (0x0CU) ///< Alternative function 12 -#define GPIO_AF_13 (0x0DU) ///< Alternative function 13 -#define GPIO_AF_14 (0x0EU) ///< Alternative function 14 -#define GPIO_AF_15 (0x0FU) ///< Alternative function 15 -#define GPIO_PortSourceGPIOA (0x00U) -#define GPIO_PortSourceGPIOB (0x01U) -#define GPIO_PortSourceGPIOC (0x02U) -#define GPIO_PortSourceGPIOD (0x03U) - -#define GPIO_PinSource0 (0x00U) -#define GPIO_PinSource1 (0x01U) -#define GPIO_PinSource2 (0x02U) -#define GPIO_PinSource3 (0x03U) -#define GPIO_PinSource4 (0x04U) -#define GPIO_PinSource5 (0x05U) -#define GPIO_PinSource6 (0x06U) -#define GPIO_PinSource7 (0x07U) -#define GPIO_PinSource8 (0x08U) -#define GPIO_PinSource9 (0x09U) -#define GPIO_PinSource10 (0x0AU) -#define GPIO_PinSource11 (0x0BU) -#define GPIO_PinSource12 (0x0CU) -#define GPIO_PinSource13 (0x0DU) -#define GPIO_PinSource14 (0x0EU) -#define GPIO_PinSource15 (0x0FU) - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup GPIO_Exported_Variables -/// @{ - -#ifdef _HAL_GPIO_C_ - -#define GLOBAL -#else -#define GLOBAL extern -#endif - - - -#undef GLOBAL - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup GPIO_Exported_Functions -/// @{ -void GPIO_DeInit(GPIO_TypeDef* gpio); -void GPIO_AFIODeInit(void); -void GPIO_Init(GPIO_TypeDef* gpio, GPIO_InitTypeDef* init_struct); -void GPIO_StructInit(GPIO_InitTypeDef* init_struct); -void GPIO_SetBits(GPIO_TypeDef* gpio, u16 pin); -void GPIO_ResetBits(GPIO_TypeDef* gpio, u16 pin); -void GPIO_WriteBit(GPIO_TypeDef* gpio, u16 pin, BitAction value); -void GPIO_Write(GPIO_TypeDef* gpio, u16 value); -void GPIO_PinLock(GPIO_TypeDef* gpio, u16 pin, FunctionalState state); -void GPIO_PinLockConfig(GPIO_TypeDef* gpio, u16 pin); -bool GPIO_ReadInputDataBit(GPIO_TypeDef* gpio, u16 pin); -bool GPIO_ReadOutputDataBit(GPIO_TypeDef* gpio, u16 pin); - -u16 GPIO_ReadInputData(GPIO_TypeDef* gpio); -u16 GPIO_ReadOutputData(GPIO_TypeDef* gpio); - - -void GPIO_PinAFConfig(GPIO_TypeDef* gpio, u8 pin, u8 alternate_function); - -void exGPIO_PinAFConfig(GPIO_TypeDef* gpio, u16 pin, s32 remap, s8 alternate_function); - - -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -#endif // __HAL_GPIO_H -//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_i2c.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_i2c.h deleted file mode 100644 index 42a9ab55f..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_i2c.h +++ /dev/null @@ -1,255 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_i2c.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE I2C -/// FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#ifndef __HAL_I2C_H -#define __HAL_I2C_H - -// Files includes -#include "types.h" -#include "reg_i2c.h" - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup I2C_HAL -/// @brief I2C HAL modules -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup I2C_Exported_Types -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup DRV_Exported_Constants -/// @{ - -#define I2C_OWN_ADDRESS 0x20 - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief I2C Init structure definition -//////////////////////////////////////////////////////////////////////////////// -typedef struct { - union { - u16 Mode; ///< Specifies the I2C mode. This parameter can be a value of I2C_mode. - u16 I2C_Mode; - }; - union { - u16 Speed; ///< Specifies the I2C speed. This parameter can be a value of I2C_speed. - u16 I2C_Speed; - }; - union { - u16 OwnAddress; ///< Specifies the first device own address. This parameter can be a 7-bit or 10-bit address. - u16 I2C_OwnAddress; - }; - - union { - u32 ClockSpeed; ///< Specifies the clock speed. - u32 I2C_ClockSpeed; - }; -} I2C_InitTypeDef; -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup I2C_Exported_Constants -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @brief I2C DMA Direction -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - RDMAE_SET = 1, // 1 - DMA read - TDMAE_SET // 2 - DMA transmit -} I2C_DMA_Dir_TypeDef; -//////////////////////////////////////////////////////////////////////////////// -/// @brief I2C Transfer Direction -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - I2C_Direction_Transmitter, // I2C Transmitter - I2C_Direction_Receiver // I2C Receiver -} I2C_Trans_Dir_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief I2C Acknowledged Address -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - I2C_AcknowledgedAddress_7bit = 0x4000, // 7-bit address - I2C_AcknowledgedAddress_10bit = 0xC000 // 10-bit address -} I2C_ACKaddr_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup I2C_Private_Defines -/// @{ -#define INTR_MASK ((u16)0xC000) -#define FLAG_Mask ((u32)0x00793FFF) -#define IC_TAR_ENDUAL_Set ((u16)0x1000) -#define IC_TAR_ENDUAL_Reset ((u16)0xEFFF) -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup I2C_modes -/// @{ -#define TX_EMPTY_CTRL I2C_CR_EMPINT -#define IC_SLAVE_DISABLE I2C_CR_SLAVEDIS -#define IC_RESTART_EN I2C_CR_REPEN -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup I2C_interrupts_definition -/// @{ -#define I2C_IT_RX_UNDER ((u16)0x0001) -#define I2C_IT_RX_OVER ((u16)0x0002) -#define I2C_IT_RX_FULL ((u16)0x0004) -#define I2C_IT_TX_OVER ((u16)0x0008) -#define I2C_IT_TX_EMPTY ((u16)0x0010) -#define I2C_IT_RD_REQ ((u16)0x0020) -#define I2C_IT_TX_ABRT ((u16)0x0040) -#define I2C_IT_RX_DONE ((u16)0x0080) -#define I2C_IT_ACTIVITY ((u16)0x0100) -#define I2C_IT_STOP_DET ((u16)0x0200) -#define I2C_IT_START_DET ((u16)0x0400) -#define I2C_IT_GEN_CALL ((u16)0x0800) -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup I2C_flags_definition -/// @{ -#define I2C_FLAG_RX_UNDER ((u16)0x0001) -#define I2C_FLAG_RX_OVER ((u16)0x0002) -#define I2C_FLAG_RX_FULL ((u16)0x0004) -#define I2C_FLAG_TX_OVER ((u16)0x0008) -#define I2C_FLAG_TX_EMPTY ((u16)0x0010) -#define I2C_FLAG_RD_REQ ((u16)0x0020) -#define I2C_FLAG_TX_ABRT ((u16)0x0040) -#define I2C_FLAG_RX_DONE ((u16)0x0080) -#define I2C_FLAG_ACTIVITY ((u16)0x0100) -#define I2C_FLAG_STOP_DET ((u16)0x0200) -#define I2C_FLAG_START_DET ((u16)0x0400) -#define I2C_FLAG_GEN_CALL ((u16)0x0800) -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup I2C_Events -/// @{ -#define I2C_EVENT_RX_UNDER ((u16)0x0001) -#define I2C_EVENT_RX_OVER ((u16)0x0002) -#define I2C_EVENT_RX_FULL ((u16)0x0004) -#define I2C_EVENT_TX_OVER ((u16)0x0008) -#define I2C_EVENT_TX_EMPTY ((u16)0x0010) -#define I2C_EVENT_RD_REQ ((u16)0x0020) -#define I2C_EVENT_TX_ABRT ((u16)0x0040) -#define I2C_EVENT_RX_DONE ((u16)0x0080) -#define I2C_EVENT_ACTIVITY ((u16)0x0100) -#define I2C_EVENT_STOP_DET ((u16)0x0200) -#define I2C_EVENT_START_DET ((u16)0x0400) -#define I2C_EVENT_GEN_CALL ((u16)0x0800) -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup I2C_Statusflags_definition -/// @{ -#define I2C_STATUS_FLAG_ACTIVITY ((u16)0x8001) -#define I2C_STATUS_FLAG_TFNF ((u16)0x8002) -#define I2C_STATUS_FLAG_TFE ((u16)0x8004) -#define I2C_STATUS_FLAG_RFNE ((u16)0x8008) -#define I2C_STATUS_FLAG_RFF ((u16)0x8010) -#define I2C_STATUS_FLAG_M_ACTIVITY ((u16)0x8020) -#define I2C_STATUS_FLAG_S_ACTIVITY ((u16)0x8040) -/// @} - - - -#define IC_SLAVE_ENABLE (0x0000<<6) -#define IC_7BITADDR_MASTER (0x0000<<4) -#define IC_7BITADDR_SLAVE (0x0000<<3) -#define I2C_Speed_STANDARD ((u16)0x0002) -#define I2C_Speed_FAST ((u16)0x0004) -#define I2C_Mode_MASTER ((u16)0x0001) -#define I2C_Mode_SLAVE ((u16)0x0000) -#define CMD_READ ((u16)0x0100) -#define CMD_WRITE ((u16)0x0000) -#define I2C_Mode_I2C ((u16)0x0000) - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup I2C_Exported_Variables -/// @{ -#ifdef _HAL_I2C_C_ - -#define GLOBAL - -static u8 I2C_CMD_DIR = 0; -u16 I2C_DMA_DIR = 0; - -#else -#define GLOBAL extern -#endif - -#undef GLOBAL -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup I2C_Exported_Functions -/// @{ -void I2C_DeInit(I2C_TypeDef* i2c); -void I2C_Init(I2C_TypeDef* i2c, I2C_InitTypeDef* init_struct); -void I2C_StructInit(I2C_InitTypeDef* init_struct); -void I2C_Cmd(I2C_TypeDef* i2c, FunctionalState state); -void I2C_DMACmd(I2C_TypeDef* i2c, FunctionalState state); -void I2C_GenerateSTART(I2C_TypeDef* i2c, FunctionalState state); -void I2C_GenerateSTOP(I2C_TypeDef* i2c, FunctionalState state); -void I2C_OwnAddress2Config(I2C_TypeDef* i2c, u8 addr); -void I2C_DualAddressCmd(I2C_TypeDef* i2c, FunctionalState state); -void I2C_GeneralCallCmd(I2C_TypeDef* i2c, FunctionalState state); -void I2C_ITConfig(I2C_TypeDef* i2c, u16 it, FunctionalState state); -void I2C_SendData(I2C_TypeDef* i2c, u8 dat); -void I2C_ReadCmd(I2C_TypeDef* i2c); -void I2C_Send7bitAddress(I2C_TypeDef* i2c, u8 addr, u8 dir); -void I2C_ClearFlag(I2C_TypeDef* i2c, u32 flag); -void I2C_ClearITPendingBit(I2C_TypeDef* i2c, u32 it); - -u8 I2C_ReceiveData(I2C_TypeDef* i2c); -u16 I2C_ReadRegister(I2C_TypeDef* i2c, u8 reg); -u32 I2C_GetLastEvent(I2C_TypeDef* i2c); - -ErrorStatus I2C_CheckEvent(I2C_TypeDef* i2c, u32 event); -FlagStatus I2C_GetFlagStatus(I2C_TypeDef* i2c, u32 flag); -ITStatus I2C_GetITStatus(I2C_TypeDef* i2c, u32 it); - -//////////////////////////////////////////////////////////////////////////////// -// Extended function interface -//////////////////////////////////////////////////////////////////////////////// -void I2C_SendSlaveAddress(I2C_TypeDef* i2c, u8 addr); -void I2C_SlaveConfigure(I2C_TypeDef* i2c, FunctionalState state); -void I2C_DMAConfigure(I2C_TypeDef* i2c, u8 dir); - - -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -#endif //__HAL_I2C_H -//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_iwdg.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_iwdg.h deleted file mode 100644 index e0b86d7b7..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_iwdg.h +++ /dev/null @@ -1,130 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_iwdg.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE IWDG -/// FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

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-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#ifndef __HAL_IWDG_H -#define __HAL_IWDG_H - -// Files includes -#include "types.h" -#include "reg_iwdg.h" -#include "reg_common.h" - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup IWDG_HAL -/// @brief IWDG HAL modules -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup IWDG_Exported_Constants -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @brief IWDG prescaler -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - IWDG_Prescaler_4 = IWDG_PR_PRE_DIV4, - IWDG_Prescaler_8 = IWDG_PR_PRE_DIV8, - IWDG_Prescaler_16 = IWDG_PR_PRE_DIV16, - IWDG_Prescaler_32 = IWDG_PR_PRE_DIV32, - IWDG_Prescaler_64 = IWDG_PR_PRE_DIV64, - IWDG_Prescaler_128 = IWDG_PR_PRE_DIV128, - IWDG_Prescaler_256 = IWDG_PR_PRE_DIV256 -} IWDGPrescaler_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief IWDG flag -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - IWDG_FLAG_PVU = 0x0001, // IWDG prescaler value update flag - IWDG_FLAG_RVU = 0x0002 // IWDG counter reload value update flag -} IWDGFlag_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Write access to IWDG_PR and IWDG_RLR registers -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - IWDG_WriteAccess_Enable = 0x5555, // Enable write - IWDG_WriteAccess_Disable = 0x0000 // Disable write -} IWDGWriteAccess_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief IWDG Key Reload -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - KR_KEY_Reload = 0xAAAA, // Reload value - KR_KEY_Enable = 0xCCCC // Start IWDG -} IWDGKey_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief IWDG Overflow Configration -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - IWDG_Overflow_Reset = 0, // - IWDG_Overflow_Interrupt = IWDG_CR_IRQSEL // -} IWDGOverflowConfig_TypeDef; - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup IWDG_Exported_Variables -/// @{ -#ifdef _HAL_IWDG_C_ -#define GLOBAL - -#else -#define GLOBAL extern -#endif - - -#undef GLOBAL -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup IWDG_Exported_Functions -/// @{ -FlagStatus IWDG_GetFlagStatus(u16 flag); - -void IWDG_WriteAccessCmd(u16 write_access); -void IWDG_SetPrescaler(u8 prescaler); -void IWDG_SetReload(u16 reload); -u32 IWDG_GetReload(void); -void IWDG_ReloadCounter(void); -void IWDG_Enable(void); -void PVU_CheckStatus(void); -void RVU_CheckStatus(void); - -void IWDG_OverflowConfig(IWDGOverflowConfig_TypeDef overflow_config); -void IWDG_ClearITPendingBit(void); -void IWDG_EnableIT(void); -void IWDG_Reset(void); -void IWDG_ClearIT(void); - -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -#endif // __HAL_IWDG_H -//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_misc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_misc.h deleted file mode 100644 index 0b7429963..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_misc.h +++ /dev/null @@ -1,128 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_misc.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE NVIC -/// FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

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-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#ifndef __HAL_MISC_H -#define __HAL_MISC_H - -// Files includes -#include "types.h" -#include "reg_common.h" - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup NVIC_HAL -/// @brief NVIC HAL modules -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup NVIC_Exported_Types -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @brief NVIC Init Structure definition -//////////////////////////////////////////////////////////////////////////////// -typedef struct { - u8 NVIC_IRQChannel; - u8 NVIC_IRQChannelPreemptionPriority; - u8 NVIC_IRQChannelSubPriority; - FunctionalState NVIC_IRQChannelCmd; -} NVIC_InitTypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief NVIC New Init Structure definition -//////////////////////////////////////////////////////////////////////////////// -typedef struct { - u8 NVIC_IRQChannel; - u8 NVIC_IRQChannelPreemptionPriority; // Cortex-M0 not used - u8 NVIC_IRQChannelSubPriority; - FunctionalState NVIC_IRQChannelCmd; -} exNVIC_Init_TypeDef; - -/// @} -//////////////////////////////////////////////////////////////////////////////// - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup NVIC_Exported_Constants -/// @{ - -#define NVIC_VectTab_RAM (0x20000000U) -#define NVIC_VectTab_FLASH (0x08000000U) - -#define NVIC_LP_SEVONPEND (0x10U) -#define NVIC_LP_SLEEPDEEP (0x04U) -#define NVIC_LP_SLEEPONEXIT (0x02U) - -#define NVIC_PriorityGroup_0 (0x0700U) // 0 bits for pre-emption priority 4 bits for subpriority -#define NVIC_PriorityGroup_1 (0x0600U) // 1 bits for pre-emption priority 3 bits for subpriority -#define NVIC_PriorityGroup_2 (0x0500U) // 2 bits for pre-emption priority 2 bits for subpriority -#define NVIC_PriorityGroup_3 (0x0400U) // 3 bits for pre-emption priority 1 bits for subpriority -#define NVIC_PriorityGroup_4 (0x0300U) // 4 bits for pre-emption priority 0 bits for subpriority - -#define AIRCR_VECTKEY_MASK (0x05FA0000U) - -#define SysTick_CLKSource_HCLK_Div8 (0xFFFFFFFBU) - - -#define SysTick_CLKSource_EXTCLK (0xFFFFFFFBU) -#define SysTick_CLKSource_HCLK (0x00000004U) -/// @} - - - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup NVIC_Exported_Variables -/// @{ - -#ifdef _HAL_NVIC_C_ - -#define GLOBAL -#else -#define GLOBAL extern -#endif - -#undef GLOBAL - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup NVIC_Exported_Functions -/// @{ - -void NVIC_PriorityGroupConfig(u32 priority_group); -void NVIC_SetVectorTable(u32 vect_tab, u32 offset); - -void NVIC_SystemLPConfig(u8 low_power_mode, FunctionalState state); -void NVIC_Init(NVIC_InitTypeDef* init_struct); - -void SysTick_CLKSourceConfig(u32 systick_clk_source); - -void exNVIC_Init(exNVIC_Init_TypeDef* init_struct); - -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -#endif // __HAL_NVIC_H -//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_pwr.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_pwr.h deleted file mode 100644 index f7837ca8d..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_pwr.h +++ /dev/null @@ -1,156 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_pwr.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE PWR -/// FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#ifndef __HAL_PWR_H -#define __HAL_PWR_H - -// Files includes -#include "types.h" -#include "reg_pwr.h" -#include "reg_syscfg.h" -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup PWR_HAL -/// @brief PWR HAL modules -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup PWR_Exported_Types -/// @{ - -typedef enum { - emWUP_Pin1 = 0, - emWUP_Pin2 = 1, - emWUP_Pin3, - emWUP_Pin4, - emWUP_Pin5, - emWUP_Pin6, -} emWUP_Pin_Typedef; -//////////////////////////////////////////////////////////////////////////////// -/// @brief PVD_detection_level - -typedef enum { - emPVD_LEVEL0 = SYSCFG_PDETCSR_PLS_1V7, - emPVD_LEVEL1 = SYSCFG_PDETCSR_PLS_2V0, - emPVD_LEVEL2 = SYSCFG_PDETCSR_PLS_2V3, - emPVD_LEVEL3 = SYSCFG_PDETCSR_PLS_2V6, - emPVD_LEVEL4 = SYSCFG_PDETCSR_PLS_2V9, - emPVD_LEVEL5 = SYSCFG_PDETCSR_PLS_3V2, - emPVD_LEVEL6 = SYSCFG_PDETCSR_PLS_3V5, - emPVD_LEVEL7 = SYSCFG_PDETCSR_PLS_3V8, - emPVD_LEVEL8 = SYSCFG_PDETCSR_PLS_4V1, - emPVD_LEVEL9 = SYSCFG_PDETCSR_PLS_4V4, - emPVD_LEVEL10 = SYSCFG_PDETCSR_PLS_4V7 -} emPVD_Level_Typedef; -#define PWR_PVDLevel_1V7 SYSCFG_PDETCSR_PLS_1V7 -#define PWR_PVDLevel_2V0 SYSCFG_PDETCSR_PLS_2V0 -#define PWR_PVDLevel_2V3 SYSCFG_PDETCSR_PLS_2V3 -#define PWR_PVDLevel_2V6 SYSCFG_PDETCSR_PLS_2V6 -#define PWR_PVDLevel_2V9 SYSCFG_PDETCSR_PLS_2V9 -#define PWR_PVDLevel_3V2 SYSCFG_PDETCSR_PLS_3V2 -#define PWR_PVDLevel_3V5 SYSCFG_PDETCSR_PLS_3V5 -#define PWR_PVDLevel_3V8 SYSCFG_PDETCSR_PLS_3V8 -#define PWR_PVDLevel_4V1 SYSCFG_PDETCSR_PLS_4V1 -#define PWR_PVDLevel_4V4 SYSCFG_PDETCSR_PLS_4V4 -#define PWR_PVDLevel_4V7 SYSCFG_PDETCSR_PLS_4V7 -/// @brief Regulator_state_is_STOP_mode -typedef enum { - PWR_Regulator_ON = 0x00000000, - PWR_Regulator_LowPower = 0x00000001 - -} emPWR_Reg_Stop_mode_Typedef; - -/// @brief STOP_mode_entry -typedef enum { - PWR_STOPEntry_WFI = 0x00000001, - PWR_STOPEntry_WFE = 0x00000002 - -} emPWR_STOP_ModeEn_Typedef; - -/// @brief Low Power Mode -typedef enum { - LP_STOP_MODE = 0, - LP_SLEEP_MODE = 1, - LP_STANDBY_MODE = 2 -} emPWR_LP_Mode_Typedef; - -/// @brief Wait_for_mode -typedef enum { - LP_WFI, - LP_WFE -} emPWR_Wait_Mode_Typedef; -//typedef enum { -// PWR_FLAG_WU = PWR_CSR_WUF, -// PWR_FLAG_SB = PWR_CSR_SBF, - -// PWR_FLAG_PVDO = PWR_CSR_PVDO - - -//} emPWR_PWR_Flag_Typedef; - - -/// @} - -/////////////////////////////////////////////////////////////////////////////// -/// @defgroup PWR_Exported_Variables -/// @{ - -#ifdef _HAL_PWR_C_ - -#define GLOBAL -#else -#define GLOBAL extern -#endif - -#undef GLOBAL - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup PWR_Exported_Functions -/// @{ - -void PWR_DeInit(void); - -void PWR_BackupAccessCmd(FunctionalState state); - -void PWR_PVDCmd(FunctionalState state); -void PWR_PVDLevelConfig(emPVD_Level_Typedef pvd_level); -void PWR_WakeUpPinCmd(FunctionalState state); -void PWR_EnterSTOPMode(emPWR_Reg_Stop_mode_Typedef regulator, emPWR_STOP_ModeEn_Typedef stop_entry); -void PWR_EnterSTANDBYMode(void); - - -void PWR_ClearFlag(u32 flag); -FlagStatus PWR_GetFlagStatus(u32 flag); -FlagStatus PWR_GetPVDOFlagStatus(u32 flag); -void exPWR_EnterLowPowerMode(emPWR_LP_Mode_Typedef lp_mode, emPWR_Wait_Mode_Typedef wait_mode); - -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -#endif // __HAL_PWR_H -//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rcc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rcc.h deleted file mode 100644 index deb916d4c..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rcc.h +++ /dev/null @@ -1,329 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_rcc.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE RCC -/// FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#ifndef __HAL_RCC_H -#define __HAL_RCC_H - -// Files includes -#include "types.h" -#include "reg_common.h" -#include "mm32_reg.h" - - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup RCC_HAL -/// @brief RCC HAL modules -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup RCC_Exported_Types -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup RCC_Exported_Constants -/// @{ - - -/// @} - - - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup RCC_Exported_Enumeration -/// @{ - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief HSE configuration -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - RCC_HSE_OFF = 0, // HSE OFF - RCC_HSE_ON = RCC_CR_HSEON, // HSE ON - RCC_HSE_Bypass = RCC_CR_HSEBYP // HSE Bypass -} RCCHSE_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Used for flags -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - CR_REG_INDEX = 1, // - BDCR_REG_INDEX = 2, // - CSR_REG_INDEX = 3, // - RCC_FLAG_MASK = 0x1FU // -} RCC_RegisterFlag_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief RCC Flag -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - // Flags in the CR register - RCC_FLAG_HSIRDY = ((u8)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)), ///< Internal High Speed clock ready flag - RCC_FLAG_HSERDY = ((u8)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)), ///< External High Speed clock ready flag - - RCC_FLAG_PLLRDY = ((u8)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)), ///< PLL clock ready flag - - // Flags in the CSR register - RCC_FLAG_LSIRDY = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)), ///< Internal Low Speed oscillator Ready - RCC_FLAG_PINRST = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)), ///< PIN reset flag - RCC_FLAG_PORRST = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_Pos)), ///< POR/PDR reset flag - RCC_FLAG_SFTRST = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)), ///< Software Reset flag - RCC_FLAG_IWDGRST = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)), ///< Independent Watchdog reset flag - RCC_FLAG_WWDGRST = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)), ///< Window watchdog reset flag - - // Flags in the BDCR register - RCC_FLAG_LSERDY = ((u8)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)) ///< External Low Speed oscillator Ready -} RCC_FLAG_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief System clock source -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - RCC_HSI = 0, // Set HSI as systemCLOCK - RCC_HSE = 1, // Set HSE as systemCLOCK - RCC_PLL = 2, // Set PLL as systemCLOCK - RCC_LSI = 3 // Set LSI as systemCLOCK -} SYSCLK_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief PLL entry clock source -//////////////////////////////////////////////////////////////////////////////// - -typedef enum { - RCC_HSI_Div4 = 0, - RCC_HSI_Div = 0, - RCC_HSE_Div1 = RCC_PLLCFGR_PLLSRC, - RCC_HSE_Div2 = (RCC_PLLCFGR_PLLXTPRE | RCC_PLLCFGR_PLLSRC), -} RCC_PLLSource_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief PLL multiplication factor -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - RCC_PLLMul_2 = 0x00000000U, - RCC_PLLMul_3 = 0x00040000U, - RCC_PLLMul_4 = 0x00080000U, - RCC_PLLMul_5 = 0x000C0000U, - RCC_PLLMul_6 = 0x00100000U, - RCC_PLLMul_7 = 0x00140000U, - RCC_PLLMul_8 = 0x00180000U, - RCC_PLLMul_9 = 0x001C0000U, - RCC_PLLMul_10 = 0x00200000U, - RCC_PLLMul_11 = 0x00240000U, - RCC_PLLMul_12 = 0x00280000U, - RCC_PLLMul_13 = 0x002C0000U, - RCC_PLLMul_14 = 0x00300000U, - RCC_PLLMul_15 = 0x00340000U, - RCC_PLLMul_16 = 0x00380000U -} RCC_PLLMul_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief AHB clock source -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - RCC_SYSCLK_Div1 = RCC_CFGR_HPRE_DIV1, - RCC_SYSCLK_Div2 = RCC_CFGR_HPRE_DIV2, - RCC_SYSCLK_Div4 = RCC_CFGR_HPRE_DIV4, - RCC_SYSCLK_Div8 = RCC_CFGR_HPRE_DIV8, - RCC_SYSCLK_Div16 = RCC_CFGR_HPRE_DIV16, - RCC_SYSCLK_Div64 = RCC_CFGR_HPRE_DIV64, - RCC_SYSCLK_Div128 = RCC_CFGR_HPRE_DIV128, - RCC_SYSCLK_Div256 = RCC_CFGR_HPRE_DIV256, - RCC_SYSCLK_Div512 = RCC_CFGR_HPRE_DIV512 -} RCC_AHB_CLK_TypeDef; -//////////////////////////////////////////////////////////////////////////////// -/// @brief APB1 and APB2clock source -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - RCC_HCLK_Div1 = RCC_CFGR_PPRE1_DIV1, - RCC_HCLK_Div2 = RCC_CFGR_PPRE1_DIV2, - RCC_HCLK_Div4 = RCC_CFGR_PPRE1_DIV4, - RCC_HCLK_Div8 = RCC_CFGR_PPRE1_DIV8, - RCC_HCLK_Div16 = RCC_CFGR_PPRE1_DIV16 -} RCC_APB1_APB2_CLK_TypeDef; -//////////////////////////////////////////////////////////////////////////////// -/// @brief USB Device clock source -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - RCC_USBCLKSource_PLLCLK_Div1 = 0, - RCC_USBCLKSource_PLLCLK_Div2 = 1, - RCC_USBCLKSource_PLLCLK_Div3 = 2, - RCC_USBCLKSource_PLLCLK_Div4 = 3 -} RCC_USBCLKSOURCE_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ADC clock source -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - RCC_PCLK2_Div2 = (0x00000000), - RCC_PCLK2_Div4 = (0x00004000), - RCC_PCLK2_Div6 = (0x00008000), - RCC_PCLK2_Div8 = (0x0000C000) -} RCC_ADCCLKSOURCE_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief LSE configuration -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - RCC_LSE_OFF = 0, // LSE OFF - RCC_LSE_ON = RCC_BDCR_LSEON, // LSE ON - RCC_LSE_Bypass = RCC_BDCR_LSEBYP // LSE Bypass -} RCC_LSE_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief RTC clock source -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - RCC_RTCCLKSource_LSE = RCC_BDCR_RTCSEL_LSE, - RCC_RTCCLKSource_LSI = RCC_BDCR_RTCSEL_LSI, - RCC_RTCCLKSource_HSE_Div128 = RCC_BDCR_RTCSEL_HSE -} RCC_RTCCLKSOURCE_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Clock source to output on MCO pin -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - RCC_MCO_NoClock = RCC_CFGR_MCO_NOCLOCK, - RCC_MCO_LSI = RCC_CFGR_MCO_LSI, - RCC_MCO_LSE = RCC_CFGR_MCO_LSE, - RCC_MCO_SYSCLK = RCC_CFGR_MCO_SYSCLK, - RCC_MCO_HSI = RCC_CFGR_MCO_HSI, - RCC_MCO_HSE = RCC_CFGR_MCO_HSE, - RCC_MCO_PLLCLK_Div2 = RCC_CFGR_MCO_PLL -} RCC_MCO_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief RCC Interrupt source -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - RCC_IT_LSIRDY = RCC_CIR_LSIRDYF, - RCC_IT_LSERDY = RCC_CIR_LSERDYF, - RCC_IT_HSIRDY = RCC_CIR_HSIRDYF, - RCC_IT_HSERDY = RCC_CIR_HSERDYF, - RCC_IT_PLLRDY = RCC_CIR_PLLRDYF, - RCC_IT_CSS = RCC_CIR_CSSF -} RCC_IT_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief RCC clock frequency type definition -//////////////////////////////////////////////////////////////////////////////// -typedef struct { - u32 SYSCLK_Frequency; ///< returns SYSCLK clock frequency. - u32 HCLK_Frequency; ///< returns hclk clock frequency. - u32 PCLK1_Frequency; ///< returns PCLK1 clock frequency. - u32 PCLK2_Frequency; ///< returns PCLK2 clock frequency. - u32 ADCCLK_Frequency; ///< returns ADCCLK clock frequency. -} RCC_ClocksTypeDef; -/// @} - -/// @} - - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup RCC_Exported_Variables -/// @{ -#ifdef _HAL_RCC_C_ - -#define GLOBAL -#else -#define GLOBAL extern -#endif - -#undef GLOBAL -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup RCC_Exported_Functions -/// @{ -void RCC_DeInit(void); -void RCC_HSEConfig(RCCHSE_TypeDef state); -void RCC_HSICmd(FunctionalState state); -void RCC_SYSCLKConfig(SYSCLK_TypeDef sys_clk_src); -void RCC_PLLDMDNConfig(u32 plldn, u32 plldm); -void RCC_PLLConfig(RCC_PLLSource_TypeDef pll_src, RCC_PLLMul_TypeDef pll_mul); -void RCC_PLLCmd(FunctionalState state); -void RCC_HCLKConfig(RCC_AHB_CLK_TypeDef sys_clk); -void RCC_PCLK1Config(RCC_APB1_APB2_CLK_TypeDef hclk); -void RCC_PCLK2Config(RCC_APB1_APB2_CLK_TypeDef hclk); -void RCC_USBCLKConfig(RCC_USBCLKSOURCE_TypeDef usb_clk_src); -void RCC_ADCCLKConfig(RCC_ADCCLKSOURCE_TypeDef pclk2); -void RCC_LSICmd(FunctionalState state); - -void RCC_RTCCLKCmd(FunctionalState state); -void RCC_LSEConfig(RCC_LSE_TypeDef state); -void RCC_RTCCLKConfig(RCC_RTCCLKSOURCE_TypeDef rtc_clk_src); -void RCC_BackupResetCmd(FunctionalState state); - -void RCC_GetClocksFreq(RCC_ClocksTypeDef* clk); -void RCC_AHBPeriphClockCmd(u32 ahb_periph, FunctionalState state); -void RCC_AHB2PeriphClockCmd(u32 ahb_periph, FunctionalState state); -void RCC_AHB3PeriphClockCmd(u32 ahb_periph, FunctionalState state); -void RCC_AHBPeriphResetCmd(u32 ahb_periph, FunctionalState state); -void RCC_AHB2PeriphResetCmd(u32 ahb_periph, FunctionalState state); -void RCC_AHB3PeriphResetCmd(u32 ahb_periph, FunctionalState state); -void RCC_APB2PeriphClockCmd(u32 apb2_periph, FunctionalState state); -void RCC_APB1PeriphClockCmd(u32 apb1_periph, FunctionalState state); -void RCC_APB2PeriphResetCmd(u32 apb2_periph, FunctionalState state); -void RCC_APB1PeriphResetCmd(u32 apb1_periph, FunctionalState state); - -void RCC_ClockSecuritySystemCmd(FunctionalState state); -void RCC_MCOConfig(RCC_MCO_TypeDef mco_src); -void RCC_ClearFlag(void); -void RCC_ITConfig(RCC_IT_TypeDef it, FunctionalState state); -void RCC_ClearITPendingBit(u8 it); - -u8 RCC_GetSYSCLKSource(void); -u32 RCC_GetSysClockFreq(void); -u32 RCC_GetHCLKFreq(void); - -u32 RCC_GetPCLK1Freq(void); -u32 RCC_GetPCLK2Freq(void); -FlagStatus RCC_GetFlagStatus(RCC_FLAG_TypeDef flag); -ErrorStatus RCC_WaitForHSEStartUp(void); -ErrorStatus RCC_WaitForFlagStartUp(RCC_FLAG_TypeDef flag); -ITStatus RCC_GetITStatus(RCC_IT_TypeDef it); - -//////////////////////////////////////////////////////////////////////////////// -// Extended function interface -//////////////////////////////////////////////////////////////////////////////// -//ErrorStatus exRCC_Init(RCCInitStruct_TypeDef* para); -void exRCC_SystickDisable(void); -void exRCC_SystickEnable(u32 sys_tick_period); -void exRCC_APB1PeriphReset(u32 apb1_periph); -void exRCC_APB2PeriphReset(u32 apb2_periph); -void exRCC_BackupReset(void); -void RCC_ADC_ClockCmd(ADC_TypeDef* peripheral, FunctionalState state); -void RCC_GPIO_ClockCmd(GPIO_TypeDef* peripheral, FunctionalState state); -/// @} - -/// @} - -/// @} - - - - -//////////////////////////////////////////////////////////////////////////////// -#endif // __HAL_RCC_H -//////////////////////////////////////////////////////////////////////////////// - - diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_redefine.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_redefine.h deleted file mode 100644 index da5295c78..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_redefine.h +++ /dev/null @@ -1,102 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_redefine.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE REDEFINE -/// FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#ifndef __HAL_REDEFINE_H -#define __HAL_REDEFINE_H - -// Files includes - - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -/////////////////////////////////////1/////////////////////////////////////////// -/// @defgroup REDEFINE_HAL -/// @brief REDEFINE HAL modules -/// @{ - - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup REDEFINE_Exported_Types -/// @{ -/// - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup REDEFINE_Exported_Constants -/// @{ -//Lib redefine - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief HAL_lib Version compatibility definition -//////////////////////////////////////////////////////////////////////////////// - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM compatibility definition -//////////////////////////////////////////////////////////////////////////////// - -#define TIM_TRGOSource_Reset TIM_TRIGSource_Reset -#define TIM_TRGOSource_Enable TIM_TRIGSource_Enable -#define TIM_TRGOSource_Update TIM_TRIGSource_Update -#define TIM_TRGOSource_OC1 TIM_TRIGSource_OC1 -#define TIM_TRGOSource_OC1Ref TIM_TRIGSource_OC1Ref -#define TIM_TRGOSource_OC2Ref TIM_TRIGSource_OC2Ref -#define TIM_TRGOSource_OC3Ref TIM_TRIGSource_OC3Ref -#define TIM_TRGOSource_OC4Ref TIM_TRIGSource_OC4Ref -///< The UG bit in the TIM_EGR register is used as the trigger output (TRIG). -///< The Counter Enable CEN is used as the trigger output (TRIG). -///< The update event is used as the trigger output (TRIG). -///< The trigger output sends a positive pulse when the CC1IF flag ///< is to be set, as soon as a capture or compare match occurs (TRIG). -///< OC1REF signal is used as the trigger output (TRIG). -///< OC2REF signal is used as the trigger output (TRIG). -///< OC3REF signal is used as the trigger output (TRIG). -///< OC4REF signal is used as the trigger output (TRIG). -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup REDEFINE_Exported_Variables -/// @{ -#ifdef _HAL_REDEFINE_C_ - -#define GLOBAL -#else -#define GLOBAL extern -#endif - -#undef GLOBAL -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup REDEFINE_Exported_Functions -/// @{ - - - -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -#endif // __HAL_REDEFINE_H -//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rtc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rtc.h deleted file mode 100644 index fcf48d569..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rtc.h +++ /dev/null @@ -1,114 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_rtc.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE RTC -/// FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#ifndef __HAL_RTC_H -#define __HAL_RTC_H - -// Files includes -#include "types.h" -#include "reg_common.h" -#include "reg_rtc.h" - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup RTC_HAL -/// @brief RTC HAL modules -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup RTC_Exported_Types -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @brief RTC_interrupts_define -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - RTC_IT_OW = RTC_CR_OWIE, ///< Overflow interrupt - RTC_IT_ALR = RTC_CR_ALRIE, ///< Alarm interrupt - RTC_IT_SEC = RTC_CR_SECIE ///< Second interrupt -} RTC_IT_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief RTC_interrupts_flags -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - RTC_FLAG_RTOFF = RTC_CSR_RTOFF, ///< RTC Operation OFF flag - RTC_FLAG_RSF = RTC_CSR_RSF, ///< Registers Synchronized flag - RTC_FLAG_OW = RTC_CSR_OWF, ///< Overflow flag - RTC_FLAG_ALR = RTC_CSR_ALRF, ///< Alarm flag - RTC_FLAG_SEC = RTC_CSR_SECF ///< Second flag -} RTC_FLAG_TypeDef; -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup RTC_Exported_Constants -/// @{ - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup RTC_Exported_Variables -/// @{ - -#ifdef _HAL_RTC_C_ - -#define GLOBAL -#else -#define GLOBAL extern -#endif - -GLOBAL bool accessRTC; - - -#undef GLOBAL - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup RTC_Exported_Functions -/// @{ -void RTC_ITConfig(RTC_IT_TypeDef it, FunctionalState state); -void RTC_ClearFlag(RTC_FLAG_TypeDef flag); -void RTC_ClearITPendingBit(RTC_IT_TypeDef it); -void RTC_EnterConfigMode(void); -void RTC_SetCounter(u32 count); -void RTC_SetPrescaler(u32 prescaler); -void RTC_SetAlarm(u32 alarm); -void RTC_ExitConfigMode(void); -void RTC_WaitForLastTask(void); -void RTC_WaitForSynchro(void); - -u32 RTC_GetCounter(void); -u32 RTC_GetDivider(void); - -FlagStatus RTC_GetFlagStatus(RTC_FLAG_TypeDef flag); -ITStatus RTC_GetITStatus(RTC_IT_TypeDef it); - -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -#endif // __HAL_RTC_H -//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_sdio.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_sdio.h deleted file mode 100644 index 199ccc4c6..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_sdio.h +++ /dev/null @@ -1,503 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_gpio.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE GPIO -/// FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#ifndef __HAL_SDIO_H -#define __HAL_SDIO_H - -// Files includes -#include "mm32_reg.h" - - - -#ifdef __cplusplus -extern "C" { -#endif -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup GPIO_HAL -/// @brief GPIO HAL modules -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup GPIO_Exported_Types -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Output Maximum frequency selection -//////////////////////////////////////////////////////////////////////////////// -#define SDIO_FLAG_CCRCFAIL ((u32)0x00000001) -#define SDIO_FLAG_DCRCFAIL ((u32)0x00000002) -#define SDIO_FLAG_CTIMEOUT ((u32)0x00000004) -#define SDIO_FLAG_DTIMEOUT ((u32)0x00000008) -#define SDIO_FLAG_TXUNDERR ((u32)0x00000010) -#define SDIO_FLAG_RXOVERR ((u32)0x00000020) -#define SDIO_FLAG_CMDREND ((u32)0x00000040) -#define SDIO_FLAG_CMDSENT ((u32)0x00000080) -#define SDIO_FLAG_DATAEND ((u32)0x00000100) -#define SDIO_FLAG_STBITERR ((u32)0x00000200) -#define SDIO_FLAG_DBCKEND ((u32)0x00000400) -#define SDIO_FLAG_CMDACT ((u32)0x00000800) -#define SDIO_FLAG_TXACT ((u32)0x00001000) -#define SDIO_FLAG_RXACT ((u32)0x00002000) -#define SDIO_FLAG_TXFIFOHE ((u32)0x00004000) -#define SDIO_FLAG_RXFIFOHF ((u32)0x00008000) -#define SDIO_FLAG_TXFIFOF ((u32)0x00010000) -#define SDIO_FLAG_RXFIFOF ((u32)0x00020000) -#define SDIO_FLAG_TXFIFOE ((u32)0x00040000) -#define SDIO_FLAG_RXFIFOE ((u32)0x00080000) -#define SDIO_FLAG_TXDAVL ((u32)0x00100000) -#define SDIO_FLAG_RXDAVL ((u32)0x00200000) -#define SDIO_FLAG_SDIOIT ((u32)0x00400000) -#define SDIO_FLAG_CEATAEND ((u32)0x00800000) - - - -//////////////////////////////////////////////////////////////////////////////////////////////////// -//SDIO working mode define ,SDIO working mode definition, set through the SD_SetDevice Mode function. -#define SD_POLLING_MODE 0 /// Query mode. In this mode, it is recommended to increase the setting of SDIO_TRANSFER_CLK_DIV if there are problems with reading and writing. -#define SD_DMA_MODE 1 /// In DMA mode, it is recommended to increase the setting of SDIO_TRANSFER_CLK_DIV if there are problems with reading and writing. - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SDIO Various error enumeration definitions -//////////////////////////////////////////////////////////////////////////////// - -typedef enum { - SD_CMD_CRC_FAIL = 1, ///< Command response received (but CRC check failed) - SD_DATA_CRC_FAIL, ///< Data bock sent/received (CRC check Failed) - SD_CMD_RSP_TIMEOUT, ///< Command response timeout - SD_DATA_TIMEOUT, ///< Data time out - SD_TX_UNDERRUN, ///< Transmit FIFO under-run - SD_RX_OVERRUN, ///< Receive FIFO over-run - SD_START_BIT_ERR, ///< Start bit not detected on all data signals in widE bus mode - SD_CMD_OUT_OF_RANGE, ///< CMD's argument was out of range. - SD_ADDR_MISALIGNED, ///< Misaligned address - SD_BLOCK_LEN_ERR, ///< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length - SD_ERASE_SEQ_ERR, ///< An error in the sequence of erase command occurs. - SD_BAD_ERASE_PARAM, ///< An Invalid selection for erase groups - SD_WRITE_PROT_VIOLATION, ///< Attempt to program a write protect block - SD_LOCK_UNLOCK_FAILED, ///< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card - SD_COM_CRC_FAILED, ///< CRC check of the previous command failed - SD_ILLEGAL_CMD, ///< Command is not legal for the card state - SD_CARD_ECC_FAILED, ///< Card internal ECC was applied but failed to correct the data - SD_CC_ERROR, ///< Internal card controller error - SD_GENERAL_UNKNOWN_ERROR, ///< General or Unknown error - SD_STREAM_READ_UNDERRUN, ///< The card could not sustain data transfer in stream read operation. - SD_STREAM_WRITE_OVERRUN, ///< The card could not sustain data programming in stream mode - SD_CID_CSD_OVERWRITE, ///< CID/CSD overwrite error - SD_WP_ERASE_SKIP, ///< only partial address space was erased - SD_CARD_ECC_DISABLED, ///< Command has been executed without using internal ECC - SD_ERASE_RESET, ///< Erase sequence was cleared before executing because an out of erase sequence command was received - SD_AKE_SEQ_ERROR, ///< Error in sequence of authentication. - SD_INVALID_VOLTRANGE, ///< SD invalid voltage range, - SD_ADDR_OUT_OF_RANGE, ///< SD addresses are out of range, - SD_SWITCH_ERROR, ///< SD switch error, - SD_SDIO_DISABLED, ///< SD SDIO disability, - SD_SDIO_FUNCTION_BUSY, ///< SD SDIO function busy, - SD_SDIO_FUNCTION_FAILED, ///< SD SDIO failed, - SD_SDIO_UNKNOWN_FUNCTION, ///< SDIO unknown function, - SD_INTERNAL_ERROR, ///< SD internal error, - SD_NOT_CONFIGURED, ///< SD is not configured, - SD_REQUEST_PENDING, ///< The SD request waits, - SD_REQUEST_NOT_APPLICABLE, ///< The SD requirement does not apply, - SD_INVALID_PARAMETER, ///< Invalid SD parameter, - SD_UNSUPPORTED_FEATURE, ///< Features not supported by SD, - SD_UNSUPPORTED_HW, ///< HW not supported by SD, - SD_ERROR, ///< SD error - SD_OK = 0 ///< SD OK -} SD_Error; -//////////////////////////////////////////////////////////////////////////////// -/// @brief SD card CSD register data -//////////////////////////////////////////////////////////////////////////////// -typedef struct { - u8 CSDStruct; ///< CSD structure - u8 SysSpecVersion; ///< System specification version - u8 Reserved1; ///< Reserved - u8 TAAC; ///< Data read access-time 1 - u8 NSAC; ///< Data read access-time 2 in CLK cycles - u8 MaxBusClkFrec; ///< Max. bus clock frequency - u16 CardComdClasses; ///< Card command classes - u8 RdBlockLen; ///< Max. read data block length - u8 PartBlockRead; ///< Partial blocks for read allowed - u8 WrBlockMisalign; ///< Write block misalignment - u8 RdBlockMisalign; ///< Read block misalignment - u8 DSRImpl; ///< DSR implemented - u8 Reserved2; ///< Reserved - u32 DeviceSize; ///< Device Size - u8 MaxRdCurrentVDDMin; ///< Max. read current @ VDD min - u8 MaxRdCurrentVDDMax; ///< Max. read current @ VDD max - u8 MaxWrCurrentVDDMin; ///< Max. write current @ VDD min - u8 MaxWrCurrentVDDMax; ///< Max. write current @ VDD max - u8 DeviceSizeMul; ///< Device size multiplier - u8 EraseGrSize; ///< Erase group size - u8 EraseGrMul; ///< Erase group size multiplier - u8 WrProtectGrSize; ///< Write protect group size - u8 WrProtectGrEnable; ///< Write protect group enable - u8 ManDeflECC; ///< Manufacturer default ECC - u8 WrSpeedFact; ///< Write speed factor - u8 MaxWrBlockLen; ///< Max. write data block length - u8 WriteBlockPaPartial; ///< Partial blocks for write allowed - u8 Reserved3; ///< Reserded - u8 ContentProtectAppli; ///< Content protection application - u8 FileFormatGrouop; ///< File format group - u8 CopyFlag; ///< Copy flag (OTP) - u8 PermWrProtect; ///< Permanent write protection - u8 TempWrProtect; ///< Temporary write protection - u8 FileFormat; ///< File Format - u8 ECC; ///< ECC code - u8 CSD_CRC; ///< CSD CRC - u8 Reserved4; ///< always 1 -} SD_CSD; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SD card CID register data -//////////////////////////////////////////////////////////////////////////////// -typedef struct { - u8 ManufacturerID; ///< ManufacturerID - u16 OEM_AppliID; ///< OEM/Application ID - u32 ProdName1; ///< Product Name part1 - u8 ProdName2; ///< Product Name part2 - u8 ProdRev; ///< Product Revision - u32 ProdSN; ///< Product Serial Number - u8 Reserved1; ///< Reserved1 - u16 ManufactDate; ///< Manufacturing Date - u8 CID_CRC; ///< CID CRC - u8 Reserved2; ///< always 1 -} SD_CID; -//////////////////////////////////////////////////////////////////////////////// -/// @brief SD state -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - SD_CARD_READY = ((u32)0x00000001), - SD_CARD_IDENTIFICATION = ((u32)0x00000002), - SD_CARD_STANDBY = ((u32)0x00000003), - SD_CARD_TRANSFER = ((u32)0x00000004), - SD_CARD_SENDING = ((u32)0x00000005), - SD_CARD_RECEIVING = ((u32)0x00000006), - SD_CARD_PROGRAMMING = ((u32)0x00000007), - SD_CARD_DISCONNECTED = ((u32)0x00000008), - SD_CARD_ERROR = ((u32)0x000000FF) -} SDCardState; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SD message ,include CSD,CID data -//////////////////////////////////////////////////////////////////////////////// -typedef struct { - SD_CSD SD_csd; - SD_CID SD_cid; - long long CardCapacity; - u32 CardBlockSize; - u16 RCA; - u8 CardType; -} SD_CardInfo; -//////////////////////////////////////////////////////////////////////////////// -/// @brief SDIO init -//////////////////////////////////////////////////////////////////////////////// -typedef struct { - u8 SDIO_MDEN; - u8 SDIO_DATWT; - u8 SDIO_SelPTSM; - u8 SDIO_CLKSP; - u8 SDIO_OUTM; - u8 SDIO_SelSM; - u8 SDIO_OPMSel; -} SDIO_InitTypeDef; - -typedef struct { - u32 SDIO_Argument; ///Specifies the SDIO command argument which is sent - ///to a card as part of a command message. If a command - ///contains an argument, it must be loaded into this register - ///before writing the command to the command register - - u32 SDIO_CmdIndex; ///Specifies the SDIO command index. It must be lower than 0x40. - - u32 SDIO_Response; ///Specifies the SDIO response type. - ///This parameter can be a value of @ref SDIO_Response_Type - - u32 SDIO_Wait; ///Specifies whether SDIO wait-for-interrupt request is enabled or disabled. - ///This parameter can be a value of @ref SDIO_Wait_Interrupt_State - -/// u32 SDIO_CPSM; ///Specifies whether SDIO Command path state machine (CPSM) - ///is enabled or disabled. - ///This parameter can be a value of @ref SDIO_CPSM_State -} SDIO_CmdInitTypeDef; -typedef struct { - u32 SDIO_DataTimeOut; // < Specifies the data timeout period in card bus clock periods. - // - u32 SDIO_DataLength; // < Specifies the number of data bytes to be transferred. - // - u32 SDIO_DataBlockSize; // < Specifies the data block size for block transfer. - // This parameter can be a value of @ref SDIO_Data_Block_Size - // - u32 SDIO_TransferDir; // < Specifies the data transfer direction, whether the transfer - // is a read or write. - // This parameter can be a value of @ref SDIO_Transfer_Direction - // -// u32 SDIO_TransferMode; // < Specifies whether data transfer is in stream or block mode. -// // This parameter can be a value of @ref SDIO_Transfer_Type -// // -// u32 SDIO_DPSM; // < Specifies whether SDIO Data path state machine (DPSM) -// // is enabled or disabled. -// // This parameter can be a value of @ref SDIO_DPSM_State -} SDIO_DataInitTypeDef; - - - -extern SD_CardInfo SDCardInfo; -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup SDIO ָinstruction set -/// @{ -#define SD_CMD_GO_IDLE_STATE ((u8)0) -#define SD_CMD_SEND_OP_COND ((u8)1) -#define SD_CMD_ALL_SEND_CID ((u8)2) -#define SD_CMD_SET_REL_ADDR ((u8)3) -#define SD_CMD_SET_DSR ((u8)4) -#define SD_CMD_SDIO_SEN_OP_COND ((u8)5) -#define SD_CMD_HS_SWITCH ((u8)6) -#define SD_CMD_SEL_DESEL_CARD ((u8)7) -#define SD_CMD_HS_SEND_EXT_CSD ((u8)8) -#define SD_CMD_SEND_CSD ((u8)9) -#define SD_CMD_SEND_CID ((u8)10) -#define SD_CMD_READ_DAT_UNTIL_STOP ((u8)11) -#define SD_CMD_STOP_TRANSMISSION ((u8)12) -#define SD_CMD_SEND_STATUS ((u8)13) -#define SD_CMD_HS_BUSTEST_READ ((u8)14) -#define SD_CMD_GO_INACTIVE_STATE ((u8)15) -#define SD_CMD_SET_BLOCKLEN ((u8)16) -#define SD_CMD_READ_SINGLE_BLOCK ((u8)17) -#define SD_CMD_READ_MULT_BLOCK ((u8)18) -#define SD_CMD_HS_BUSTEST_WRITE ((u8)19) -#define SD_CMD_WRITE_DAT_UNTIL_STOP ((u8)20) -#define SD_CMD_SET_BLOCK_COUNT ((u8)23) -#define SD_CMD_WRITE_SINGLE_BLOCK ((u8)24) -#define SD_CMD_WRITE_MULT_BLOCK ((u8)25) -#define SD_CMD_PROG_CID ((u8)26) -#define SD_CMD_PROG_CSD ((u8)27) -#define SD_CMD_SET_WRITE_PROT ((u8)28) -#define SD_CMD_CLR_WRITE_PROT ((u8)29) -#define SD_CMD_SEND_WRITE_PROT ((u8)30) -#define SD_CMD_SD_ERASE_GRP_START ((u8)32) -#define SD_CMD_SD_ERASE_GRP_END ((u8)33) -#define SD_CMD_ERASE_GRP_START ((u8)35) -#define SD_CMD_ERASE_GRP_END ((u8)36) -#define SD_CMD_ERASE ((u8)38) -#define SD_CMD_FAST_IO ((u8)39) -#define SD_CMD_GO_IRQ_STATE ((u8)40) -#define SD_CMD_LOCK_UNLOCK ((u8)42) -#define SD_CMD_APP_CMD ((u8)55) -#define SD_CMD_GEN_CMD ((u8)56) -#define SD_CMD_NO_CMD ((u8)64) -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup Following commands are SD Card Specific commands. -/// @{ -#define SD_CMD_APP_SD_SET_BUSWIDTH ((u8)6) -#define SD_CMD_SD_APP_STAUS ((u8)13) -#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((u8)22) -#define SD_CMD_SD_APP_OP_COND ((u8)41) -#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((u8)42) -#define SD_CMD_SD_APP_SEND_SCR ((u8)51) -#define SD_CMD_SDIO_RW_DIRECT ((u8)52) -#define SD_CMD_SDIO_RW_EXTENDED ((u8)53) - -#define SD_CMD_SD_APP_GET_MKB ((u8)43) -#define SD_CMD_SD_APP_GET_MID ((u8)44) -#define SD_CMD_SD_APP_SET_CER_RN1 ((u8)45) -#define SD_CMD_SD_APP_GET_CER_RN2 ((u8)46) -#define SD_CMD_SD_APP_SET_CER_RES2 ((u8)47) -#define SD_CMD_SD_APP_GET_CER_RES1 ((u8)48) -#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((u8)18) -#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((u8)25) -#define SD_CMD_SD_APP_SECURE_ERASE ((u8)38) -#define SD_CMD_SD_APP_CHANGE_SECURE_AREA ((u8)49) -#define SD_CMD_SD_APP_SECURE_WRITE_MKB ((u8)48) -/// @} -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup SD support define. -/// @{ -#define SDIO_STD_CAPACITY_SD_CARD_V1_1 ((u32)0x00000000) -#define SDIO_STD_CAPACITY_SD_CARD_V2_0 ((u32)0x00000001) -#define SDIO_HIGH_CAPACITY_SD_CARD ((u32)0x00000002) -#define SDIO_MULTIMEDIA_CARD ((u32)0x00000003) -#define SDIO_SECURE_DIGITAL_IO_CARD ((u32)0x00000004) -#define SDIO_HIGH_SPEED_MULTIMEDIA_CARD ((u32)0x00000005) -#define SDIO_SECURE_DIGITAL_IO_COMBO_CARD ((u32)0x00000006) -#define SDIO_HIGH_CAPACITY_MMC_CARD ((u32)0x00000007) -/// @} - -#ifndef NULL -#define NULL 0 -#endif -#define SDIO_STATIC_FLAGS ((u32)0x000005FF) -#define SDIO_CMD0TIMEOUT ((u32)0x00010000) -#define SDIO_DATATIMEOUT ((u32)0xFFFFFFFF) -#define SDIO_FIFO_Address ((u32)0x40018080) - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup Mask for errors Card Status R1 (OCR Register) -/// @{ -#define SD_OCR_ADDR_OUT_OF_RANGE ((u32)0x80000000) -#define SD_OCR_ADDR_MISALIGNED ((u32)0x40000000) -#define SD_OCR_BLOCK_LEN_ERR ((u32)0x20000000) -#define SD_OCR_ERASE_SEQ_ERR ((u32)0x10000000) -#define SD_OCR_BAD_ERASE_PARAM ((u32)0x08000000) -#define SD_OCR_WRITE_PROT_VIOLATION ((u32)0x04000000) -#define SD_OCR_LOCK_UNLOCK_FAILED ((u32)0x01000000) -#define SD_OCR_COM_CRC_FAILED ((u32)0x00800000) -#define SD_OCR_ILLEGAL_CMD ((u32)0x00400000) -#define SD_OCR_CARD_ECC_FAILED ((u32)0x00200000) -#define SD_OCR_CC_ERROR ((u32)0x00100000) -#define SD_OCR_GENERAL_UNKNOWN_ERROR ((u32)0x00080000) -#define SD_OCR_STREAM_READ_UNDERRUN ((u32)0x00040000) -#define SD_OCR_STREAM_WRITE_OVERRUN ((u32)0x00020000) -#define SD_OCR_CID_CSD_OVERWRIETE ((u32)0x00010000) -#define SD_OCR_WP_ERASE_SKIP ((u32)0x00008000) -#define SD_OCR_CARD_ECC_DISABLED ((u32)0x00004000) -#define SD_OCR_ERASE_RESET ((u32)0x00002000) -#define SD_OCR_AKE_SEQ_ERROR ((u32)0x00000008) -#define SD_OCR_ERRORBITS ((u32)0xFDFFE008) -/// @} -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup Masks for R6 Response -/// @{ -#define SD_R6_GENERAL_UNKNOWN_ERROR ((u32)0x00002000) -#define SD_R6_ILLEGAL_CMD ((u32)0x00004000) -#define SD_R6_COM_CRC_FAILED ((u32)0x00008000) -/// @} -#define SD_VOLTAGE_WINDOW_SD ((u32)0x80100000) -#define SD_HIGH_CAPACITY ((u32)0x40000000) -#define SD_STD_CAPACITY ((u32)0x00000000) -#define SD_CHECK_PATTERN ((u32)0x000001AA) -#define SD_VOLTAGE_WINDOW_MMC ((u32)0x80FF8000) - -#define SD_MAX_VOLT_TRIAL ((u32)0x0000FFFF) -#define SD_ALLZERO ((u32)0x00000000) - -#define SD_WIDE_BUS_SUPPORT ((u32)0x00040000) -#define SD_SINGLE_BUS_SUPPORT ((u32)0x00010000) -#define SD_CARD_LOCKED ((u32)0x02000000) -#define SD_CARD_PROGRAMMING ((u32)0x00000007) -#define SD_CARD_RECEIVING ((u32)0x00000006) -#define SD_DATATIMEOUT ((u32)0xFFFFFFFF) -#define SD_0TO7BITS ((u32)0x000000FF) -#define SD_8TO15BITS ((u32)0x0000FF00) -#define SD_16TO23BITS ((u32)0x00FF0000) -#define SD_24TO31BITS ((u32)0xFF000000) -#define SD_MAX_DATA_LENGTH ((u32)0x01FFFFFF) - -#define SD_HALFFIFO ((u32)0x00000008) -#define SD_HALFFIFOBYTES ((u32)0x00000020) - -#define SD_CCCC_LOCK_UNLOCK ((u32)0x00000080) -#define SD_CCCC_WRITE_PROT ((u32)0x00000040) -#define SD_CCCC_ERASE ((u32)0x00000020) - - -#define SDIO_SEND_IF_COND ((u32)0x00000008) - -#define SDIO_Response_No ((u32)0x00) -#define SDIO_Response_Short ((u32)0x01) -#define SDIO_Response_Long ((u32)0x03) - -#define SDIO_DataBlockSize_1b ((u32)0x00000000) -#define SDIO_DataBlockSize_2b ((u32)0x00000001) -#define SDIO_DataBlockSize_4b ((u32)0x00000002) -#define SDIO_DataBlockSize_8b ((u32)0x00000003) -#define SDIO_DataBlockSize_16b ((u32)0x00000004) -#define SDIO_DataBlockSize_32b ((u32)0x00000005) -#define SDIO_DataBlockSize_64b ((u32)0x00000006) -#define SDIO_DataBlockSize_128b ((u32)0x00000007) -#define SDIO_DataBlockSize_256b ((u32)0x00000008) -#define SDIO_DataBlockSize_512b ((u32)0x00000009) -#define SDIO_DataBlockSize_1024b ((u32)0x0000000A) -#define SDIO_DataBlockSize_2048b ((u32)0x0000000B) -#define SDIO_DataBlockSize_4096b ((u32)0x0000000C) -#define SDIO_DataBlockSize_8192b ((u32)0x0000000D) -#define SDIO_DataBlockSize_16384b ((u32)0x0000000E) -//Define the data block length when the block data transfer mode is selected: -//0000: (0 decimal) lock length = 2^0 = 1 byte -//0001: (1 decimal) lock length = 2^1 = 2 bytes -//0010: (2 decimal) lock length = 2^2 = 4 bytes -//0011: (3 decimal) lock length = 2^3 = 8 bytes -//0100: (4 decimal) lock length = 2^4 = 16 bytes -//0101: (5 decimal) lock length = 2^5 = 32 bytes -//0110: (6 decimal) lock length = 2^6 = 64 bytes -//0111: (7 decimal) lock length = 2^7 = 128 bytes -//1000: (8 decimal) lock length = 2^8 = 256 bytes -//1001: (9 decimal) lock length = 2^9 = 512 bytes -//1010: (10 decimal) lock length = 2^10 = 1024 bytes -//1011: (11 decimal) lock length = 2^11 = 2048 bytes -//1100: (12 decimal) lock length = 2^12 = 4096 bytes -//1101: (13 decimal) lock length = 2^13 = 8192 bytes -//1110: (14 decimal) lock length = 2^14 = 16384 bytes -//1111: (15 decimal) reserved - - -#define SDIO_TransferDir_ToCard ((u32)0x00000000) -#define SDIO_TransferDir_ToSDIO ((u32)0x00000002) - -#define SDIO_Wait_No ((u32)0x00000000) // SDIO No Wait, TimeOut is enabled -#define SDIO_Wait_IT ((u32)0x00000100) //SDIO Wait Interrupt Request -#define SDIO_Wait_Pend ((u32)0x00000200) // SDIO Wait End of transfer - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup I2C_Exported_Functions -/// @{ -void SDIO_DeInit(void); -void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct); -void SDIO_ClockSet(u32 value); -void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct); -void SDIO_ITConfig(u32 SDIO_IT, FunctionalState state); -void SDIO_CRCConfig(u32 SDIO_CRC, FunctionalState state); -void SDIO_Clock_Set(u8 clkdiv); -void SDIO_Send_Cmd(u8 cmdindex, u8 waitrsp, u32 arg); -SD_Error SD_PowerOFF(void); -SD_Error CmdError(void); -SD_Error CmdResp2Error(void); -SD_Error CmdResp3Error(void); -SD_Error CmdResp6Error(u8 cmd, u16* prca); -SD_Error CmdResp7Error(void); -SD_Error CmdResp1Error(u8 cmd); -void SDIO_Send_Data_Cfg(u32 datatimeout, u32 datalen, u8 blksize, u8 dir); -void SDIO_ClearITPendingBit(u32 SDIO_IT); -FlagStatus SDIO_GetFlagStatus(u32 SDIO_FLAG); -u32 SDIO_GetTimeOutCounter(void); -u32 SDIO_ReadData(void); -void SDIO_WriteData(u32 tempbuff); -void SDIO_DMACmd(FunctionalState state); -/// @} - - -#ifdef __cplusplus -} -#endif - - -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -#endif -//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_spi.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_spi.h deleted file mode 100644 index db1a9aa30..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_spi.h +++ /dev/null @@ -1,351 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_spi.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SPI -/// FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#ifndef __HAL_SPI_H -#define __HAL_SPI_H - -// Files includes -#include "types.h" -#include "reg_spi.h" - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup SPI_HAL -/// @brief SPI HAL modules -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup SPI_Exported_Types -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SPI mode enum definition -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - SPI_Mode_Slave = 0x0000, ///< SPI slave mode - SPI_Mode_Master = SPI_GCR_MODE ///< SPI master mode -} SPI_Mode_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SPI data size enum definition -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - SPI_DataSize_8b = 0x0000, ///< 8 bits valid data - SPI_DataSize_32b = SPI_GCR_DWSEL ///< 32 bits valid data -} SPI_DataSize_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SPI clock polarity enum definition -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - SPI_CPOL_Low = 0x0000, ///< The clock is low in idle state. - SPI_CPOL_High = SPI_CCR_CPOL ///< The clock is high in idle state. -} SPI_CPOL_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SPI clock phase enum definition -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - SPI_CPHA_2Edge = 0x0000, ///< Data sampling starts from the second clock edge. - SPI_CPHA_1Edge = SPI_CCR_CPHA ///< Data sampling starts from the first clock edge. -} SPI_CPHA_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SPI nss control mode enum definition -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - SPI_NSS_Soft = 0x0000, - SPI_NSS_Hard = SPI_GCR_NSS -} SPI_NSS_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SPI baud rate prescaler enum definition -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - SPI_BaudRatePrescaler_2 = 0x0002, ///< SCK clock devide by 2 - SPI_BaudRatePrescaler_4 = 0x0004, ///< SCK clock devide by 4 - SPI_BaudRatePrescaler_8 = 0x0008, ///< SCK clock devide by 7 - SPI_BaudRatePrescaler_16 = 0x0010, ///< SCK clock devide by 16 - SPI_BaudRatePrescaler_32 = 0x0020, ///< SCK clock devide by 32 - SPI_BaudRatePrescaler_64 = 0x0040, ///< SCK clock devide by 64 - SPI_BaudRatePrescaler_128 = 0x0080, ///< SCK clock devide by 128 - SPI_BaudRatePrescaler_256 = 0x0100 ///< SCK clock devide by 256 -} SPI_BaudRatePrescaler_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SPI first bit enum definition -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - SPI_FirstBit_MSB = 0x0000, ///< Data transfers start from MSB - SPI_FirstBit_LSB = SPI_CCR_LSBFE ///< Data transfers start from LSB -} SPI_FirstBit_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SPI FIFO trigger level enum definition -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - SPI_RXTLF = SPI_GCR_RXTLF_Half, ///< RX FIFO trigger level - SPI_TXTLF = SPI_GCR_TXTLF_Half ///< TX FIFO trigger level -} SPI_TLF_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SPI bit derection enum definition -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - SPI_Direction_Rx, ///< Receive enable - SPI_Direction_Tx, ///< Transmit enable - SPI_Disable_Rx, ///< Receive disable - SPI_Disable_Tx ///< Transmit disable -} SPI_Direction_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SPI flag enum definition -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - SPI_FLAG_RXAVL = SPI_SR_RXAVL, ///< Receive 1 byte available data flag - SPI_FLAG_TXEPT = SPI_SR_TXEPT, ///< Transmitter empty flag - SPI_FLAG_TXFULL = SPI_SR_TXFULL, ///< Transmitter FIFO full status flag - SPI_FLAG_RXAVL_4BYTE = SPI_SR_RXAVL_4BYTE ///< Receive 4 bytes available data flag -} SPI_FLAG_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SPI slave mode data edge adjust enum definition -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - SPI_SlaveAdjust_LOW, ///< SPI slave mode data edge adjust in low speed mode - SPI_SlaveAdjust_FAST ///< SPI slave mode data edge adjust in fast speed mode -} SPI_SlaveAdjust_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SPI data edge adjust enum definition -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - SPI_DataEdgeAdjust_LOW, ///< SPI data edge adjust in low speed mode - SPI_DataEdgeAdjust_FAST ///< SPI data edge adjust in fast speed mode -} SPI_DataEdgeAdjust_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SPI interruput enum definition -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - SPI_IT_TXEPT = 0x40, ///< Transmitter empty interrupt - SPI_IT_RXFULL = 0x20, ///< RX FIFO full interrupt - SPI_IT_RXMATCH = 0x10, ///< Receive data match the RXDNR number interrut - SPI_IT_RXOERR = 0x08, ///< Receive overrun error interrupt - SPI_IT_UNDERRUN = 0x04, ///< Underrun interrupt - SPI_IT_RX = 0x02, ///< Receive available data interrupt - SPI_IT_TX = 0x01 ///< Transmit FIFO available interrupt -} SPI_IT_TypeDef; - - -typedef enum { - I2S_Standard_Phillips = 0x0000, - I2S_Standard_MSB = 0x0010, - I2S_Standard_LSB = 0x0020, - I2S_Standard_PCMShort = 0x0030, - I2S_Standard_PCMLong = 0x00B0, -} SPI_I2S_STANDARD_TypeDef; - - -typedef enum { - I2S_DataFormat_16b = 0x0000, - I2S_DataFormat_16bextended = 0x0001, - I2S_DataFormat_24b = 0x0003, - I2S_DataFormat_32b = 0x0005, -} SPI_I2S_DATAFORMAT_TypeDef; -typedef enum { - I2S_AudioFreq_192k = (192000), - I2S_AudioFreq_96k = (96000), - I2S_AudioFreq_48k = (48000), - I2S_AudioFreq_44k = (44100), - I2S_AudioFreq_32k = (32000), - I2S_AudioFreq_24k = (24000), - I2S_AudioFreq_22k = (22050), - I2S_AudioFreq_16k = (16000), - I2S_AudioFreq_11k = (11025), - I2S_AudioFreq_12k = (12000), - I2S_AudioFreq_8k = (8000), - I2S_AudioFreq_4k = (4000), - I2S_AudioFreq_Default = (2), -} SPI_I2S_AUDIO_FREQ_TypeDef; -typedef enum { - I2S_Mode_SlaveTx = 0x0000, - I2S_Mode_SlaveRx = 0x0100, - I2S_Mode_MasterTx = 0x0200, - I2S_Mode_MasterRx = 0x0300, -} SPI_I2S_TRANS_MODE_TypeDef; - -typedef enum { - I2S_MCLKOutput_Enable = 0x0800, - I2S_MCLKOutput_Disable = 0x0000, -} SPI_I2S_MCLK_OUTPUT_TypeDef; - -typedef enum { - I2S_CPOL_Low = 0x0000, ///< The clock is low in idle state. - I2S_CPOL_High = SPI_CCR_CPOL ///< The clock is high in idle state. -} SPI_I2S_CPOL_TypeDef; - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SPI Init structure definition -//////////////////////////////////////////////////////////////////////////////// -typedef struct { - SPI_Mode_TypeDef SPI_Mode; ///< Specifies the SPI operating mode - SPI_DataSize_TypeDef SPI_DataSize; ///< Specifies the SPI available data size - u8 SPI_DataWidth; ///< SPI data length - SPI_CPOL_TypeDef SPI_CPOL; ///< Specifies the serial clock steady state - SPI_CPHA_TypeDef SPI_CPHA; ///< Specifies the clock active edge for the bit capture - SPI_NSS_TypeDef SPI_NSS; ///< Specifies whether the NSS signal is managed by hardware or by software - SPI_BaudRatePrescaler_TypeDef SPI_BaudRatePrescaler; ///< Specifies the Baud Rate prescaler value which will be - ///< used to configure the transmit and receive SCK clock - SPI_FirstBit_TypeDef SPI_FirstBit; ///< Specifies whether data transfers start from MSB or LSB bit - // u16 SPI_length; -} SPI_InitTypeDef; -//////////////////////////////////////////////////////////////////////////////// -/// @brief I2S Init structure definition -//////////////////////////////////////////////////////////////////////////////// -typedef struct { - SPI_I2S_TRANS_MODE_TypeDef I2S_Mode; ///< Specifies the I2S operating mode. - SPI_I2S_STANDARD_TypeDef I2S_Standard; ///< Specifies the standard used for the I2S communication. - SPI_I2S_DATAFORMAT_TypeDef I2S_DataFormat; ///< Specifies the data format for the I2S communication. - SPI_I2S_MCLK_OUTPUT_TypeDef I2S_MCLKOutput; ///< Specifies whether the I2S MCLK output is enabled or not. - SPI_I2S_AUDIO_FREQ_TypeDef I2S_AudioFreq; ///< Specifies the frequency selected for the I2S communication. - SPI_I2S_CPOL_TypeDef I2S_CPOL; ///< Specifies the idle state of the I2S clock. -} I2S_InitTypeDef; -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup SPI_Exported_Constants -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup SPI_Register_Mask -/// @{ - -#define GCR_Mask ((u32)0x0FFF) -#define CCR_Mask ((u32)0x003F) -#define BRR_Mask ((u32)0xFFFF) -#define ECR_Mask ((u32)0x001F) - -/// @} - - -// SPI_7bit_8bit data width -#define SPI_DataWidth_1b ((u16)0x0001) -#define SPI_DataWidth_2b ((u16)0x0002) -#define SPI_DataWidth_3b ((u16)0x0003) -#define SPI_DataWidth_4b ((u16)0x0004) -#define SPI_DataWidth_5b ((u16)0x0005) -#define SPI_DataWidth_6b ((u16)0x0006) -#define SPI_DataWidth_7b ((u16)0x0007) -#define SPI_DataWidth_8b ((u16)0x0008) -#define SPI_DataWidth_9b ((u16)0x0009) -#define SPI_DataWidth_10b ((u16)0x000a) -#define SPI_DataWidth_11b ((u16)0x000b) -#define SPI_DataWidth_12b ((u16)0x000c) -#define SPI_DataWidth_13b ((u16)0x000d) -#define SPI_DataWidth_14b ((u16)0x000e) -#define SPI_DataWidth_15b ((u16)0x000f) -#define SPI_DataWidth_16b ((u16)0x0010) -#define SPI_DataWidth_17b ((u16)0x0011) -#define SPI_DataWidth_18b ((u16)0x0012) -#define SPI_DataWidth_19b ((u16)0x0013) -#define SPI_DataWidth_20b ((u16)0x0014) -#define SPI_DataWidth_21b ((u16)0x0015) -#define SPI_DataWidth_22b ((u16)0x0016) -#define SPI_DataWidth_23b ((u16)0x0017) -#define SPI_DataWidth_24b ((u16)0x0018) -#define SPI_DataWidth_25b ((u16)0x0019) -#define SPI_DataWidth_26b ((u16)0x001a) -#define SPI_DataWidth_27b ((u16)0x001b) -#define SPI_DataWidth_28b ((u16)0x001c) -#define SPI_DataWidth_29b ((u16)0x001d) -#define SPI_DataWidth_30b ((u16)0x001e) -#define SPI_DataWidth_31b ((u16)0x001f) -#define SPI_DataWidth_32b ((u16)0x0000) - - - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup SPI_Exported_Variables -/// @{ - -#ifdef _HAL_SPI_C_ -#define GLOBAL -#else -#define GLOBAL extern -#endif - -#undef GLOBAL - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup SPI_Exported_Functions -/// @{ - -void SPI_DeInit(SPI_TypeDef* spi); -void SPI_Init(SPI_TypeDef* spi, SPI_InitTypeDef* init_struct); -void SPI_StructInit(SPI_InitTypeDef* init_struct); -void SPI_Cmd(SPI_TypeDef* spi, FunctionalState state); -void SPI_ITConfig(SPI_TypeDef* spi, u8 interrupt, FunctionalState state); -void SPI_DMACmd(SPI_TypeDef* spi, FunctionalState state); -void SPI_FifoTrigger(SPI_TypeDef* spi, SPI_TLF_TypeDef fifo_trigger_value, FunctionalState state); -void SPI_SendData(SPI_TypeDef* spi, u32 data); -void SPI_CSInternalSelected(SPI_TypeDef* spi, FunctionalState state); -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* spi, SPI_NSS_TypeDef nss); - -void SPI_BiDirectionalLineConfig(SPI_TypeDef* spi, SPI_Direction_TypeDef direction); -void SPI_ClearITPendingBit(SPI_TypeDef* spi, SPI_IT_TypeDef interrupt); -void SPI_RxBytes(SPI_TypeDef* spi, u16 number); -void SPI_SlaveAdjust(SPI_TypeDef* spi, SPI_SlaveAdjust_TypeDef adjust_value); - -bool SPI_DataSizeConfig(SPI_TypeDef* spi, u8 data_size); -void SPI_DataSizeTypeConfig(SPI_TypeDef* spi, SPI_DataSize_TypeDef SPI_DataSize); -u32 SPI_ReceiveData(SPI_TypeDef* spi); - -FlagStatus SPI_GetFlagStatus(SPI_TypeDef* spi, SPI_FLAG_TypeDef flag); - -ITStatus SPI_GetITStatus(SPI_TypeDef* spi, SPI_IT_TypeDef interrupt); - -//////////////////////////////////////////////////////////////////////////////// -// Extended function interface -//////////////////////////////////////////////////////////////////////////////// -void exSPI_ITCmd(SPI_TypeDef* spi, FunctionalState state); -void exSPI_ITConfig(SPI_TypeDef* spi, SPI_IT_TypeDef interrput, FunctionalState state); -void exSPI_DMACmd(SPI_TypeDef* spi, FunctionalState state); -void exSPI_CSInternalSelected(SPI_TypeDef* spi, FunctionalState state); -void exSPI_DataEdgeAdjust(SPI_TypeDef* spi, SPI_DataEdgeAdjust_TypeDef adjust_value); -void I2S_Cmd(SPI_TypeDef* spi, FunctionalState state); -void I2S_Init(SPI_TypeDef* spi, I2S_InitTypeDef* I2S_InitStruct); -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -#endif //__HAL_SPI_H -//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_syscfg.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_syscfg.h deleted file mode 100644 index e034f9626..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_syscfg.h +++ /dev/null @@ -1,83 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_syscfg.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE EXTI -/// FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#ifndef __HAL_SYSCFG_H -#define __HAL_SYSCFG_H - -// Files includes -#include "types.h" -#include "mm32_device.h" -#include "hal_EXTI.H" -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup SYSCFG_HAL -/// @brief SYSCFG HAL modules -/// @{ - - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup SYSCFG_Exported_Types -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SYSCFG mode enumeration -//////////////////////////////////////////////////////////////////////////////// -// @defgroup SYSCFG_Memory_Remap_Config -#define SYSCFG_MemoryRemap_Flash ((u8)0x00) -#define SYSCFG_MemoryRemap_SystemMemory ((u8)0x01) -#define SYSCFG_MemoryRemap_SRAM ((u8)0x03) - - - - -/// -/// @} -/// - - - - -// Exported macro ------------------------------------------------------------ -// Exported functions ------------------------------------------------------- - -// Function used to set the SYSCFG configuration to the default reset state -#define SYSCFG_DeInit EXTI_DeInit -#define SYSCFG_MemoryRemapConfig EXTI_MemoryRemapConfig -#define SYSCFG_EXTILineConfig EXTI_LineConfig -u32 SYSCFG_GetPendingIT(u32 ITSourceLine); -void SYSCFG_BreakConfig(u32 SYSCFG_Break); -FlagStatus SYSCFG_GetFlagStatus(u32 SYSCFG_Flag); -void SYSCFG_ClearFlag(u32 SYSCFG_Flag); - - -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -#endif //__HAL_SYSCFG_H -//////////////////////////////////////////////////////////////////////////////// - - - diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_tim.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_tim.h deleted file mode 100644 index 4e57960dd..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_tim.h +++ /dev/null @@ -1,755 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_tim.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE TIM -/// FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#ifndef __HAL_TIM_H -#define __HAL_TIM_H - -// Files includes -#include "types.h" -#include "reg_tim.h" - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup TIM_HAL -/// @brief TIM HAL modules -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup TIM_Exported_Types -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_Channel -/// @anchor TIM_Channel -typedef enum { - TIM_Channel_1 = 0x0000, ///< TIM Channel 1 - TIM_Channel_2 = 0x0004, ///< TIM Channel 2 - TIM_Channel_3 = 0x0008, ///< TIM Channel 3 - TIM_Channel_4 = 0x000C, ///< TIM Channel 4 - TIM_Channel_5 = 0x0010 ///< TIM Channel 5 -} TIMCHx_Typedef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_Counter_Mode -/// @anchor TIM_Counter_Mode -typedef enum { - TIM_CounterMode_Up = 0x0000, ///< TIM Up Counting Mode - TIM_CounterMode_Down = TIM_CR1_DIR, ///< TIM Down Counting Mode - TIM_CounterMode_CenterAligned1 = TIM_CR1_CMS_CENTERALIGNED1, ///< TIM Center Aligned Mode1 - TIM_CounterMode_CenterAligned2 = TIM_CR1_CMS_CENTERALIGNED2, ///< TIM Center Aligned Mode2 - TIM_CounterMode_CenterAligned3 = TIM_CR1_CMS_CENTERALIGNED3 ///< TIM Center Aligned Mode3 -} TIMCOUNTMODE_Typedef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_Output_Compare_and_PWM_modes_and_Forced_Action -/// @anchor TIM_Output_Compare_and_PWM_modes_and_Forced_Action -typedef enum { - TIM_OCMode_Timing = 0x0000, ///< Output compare mode: Timing - TIM_OCMode_Active = 0x0010, ///< Output compare mode: Active - TIM_OCMode_Inactive = 0x0020, ///< Output compare mode: Inactive - TIM_OCMode_Toggle = 0x0030, ///< Output compare mode: Toggle - TIM_OCMode_PWM1 = 0x0060, ///< Output compare mode: PWM1 - TIM_OCMode_PWM2 = 0x0070, ///< Output compare mode: PWM2 - TIM_ForcedAction_Active = 0x0050, ///< Force active level on OCnREF - TIM_ForcedAction_InActive = 0x0040 ///< Force inactive level on OCnREF -} TIMOCMODE_Typedef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_Clock_Division_CKD -/// @anchor TIM_Clock_Division_CKD -typedef enum { - TIM_CKD_DIV1 = TIM_CR1_CKD_DIV1, ///< TDTS = Tck_tim - TIM_CKD_DIV2 = TIM_CR1_CKD_DIV2, ///< TDTS = 2 * Tck_tim - TIM_CKD_DIV4 = TIM_CR1_CKD_DIV4 ///< TDTS = 4 * Tck_tim -} TIMCKD_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_Internal_Trigger_Selection -/// @anchor TIM_Internal_Trigger_Selection -typedef enum { - TIM_TS_ITR0 = TIM_SMCR_TS_ITR0, ///< Internal Trigger 0 - TIM_TS_ITR1 = TIM_SMCR_TS_ITR1, ///< Internal Trigger 1 - TIM_TS_ITR2 = TIM_SMCR_TS_ITR2, ///< Internal Trigger 2 - TIM_TS_ITR3 = TIM_SMCR_TS_ITR3, ///< Internal Trigger 3 - TIM_TS_TI1F_ED = TIM_SMCR_TS_TI1F_ED, ///< TI1 Edge Detector - TIM_TS_TI1FP1 = TIM_SMCR_TS_TI1FP1, ///< Filtered Timer Input 1 - TIM_TS_TI2FP2 = TIM_SMCR_TS_TI2FP2, ///< Filtered Timer Input 2 - TIM_TS_ETRF = TIM_SMCR_TS_ETRF ///< TI1 Edge Detector -} TIMTS_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_Trigger_Output_Source -/// @anchor TIM_Trigger_Output_Source -typedef enum { - TIM_TRIGSource_Reset = TIM_CR2_MMS_RESET, ///< The UG bit in the TIM_EGR register is used as the trigger output (TRIG). - TIM_TRIGSource_Enable = TIM_CR2_MMS_ENABLE, ///< The Counter Enable CEN is used as the trigger output (TRIG). - TIM_TRIGSource_Update = TIM_CR2_MMS_UPDATE, ///< The update event is used as the trigger output (TRIG). - TIM_TRIGSource_OC1 = TIM_CR2_MMS_OC1, ///< The trigger output sends a positive pulse when the CC1IF flag - ///< is to be set, as soon as a capture or compare match occurs (TRIG). - TIM_TRIGSource_OC1Ref = TIM_CR2_MMS_OC1REF, ///< OC1REF signal is used as the trigger output (TRIG). - TIM_TRIGSource_OC2Ref = TIM_CR2_MMS_OC2REF, ///< OC2REF signal is used as the trigger output (TRIG). - TIM_TRIGSource_OC3Ref = TIM_CR2_MMS_OC3REF, ///< OC3REF signal is used as the trigger output (TRIG). - TIM_TRIGSource_OC4Ref = TIM_CR2_MMS_OC4REF ///< OC4REF signal is used as the trigger output (TRIG). -} TIMMMS_Typedef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_Slave_Mode -/// @anchor TIM_Slave_Mode -typedef enum { - TIM_SlaveMode_Reset = TIM_SMCR_SMS_RESET, ///< Rising edge of the selected trigger signal (TRGI) re-initializes - ///< the counter and triggers an update of the registers. - TIM_SlaveMode_Gated = TIM_SMCR_SMS_GATED, ///< The counter clock is enabled when the trigger signal (TRGI) is high. - TIM_SlaveMode_Trigger = TIM_SMCR_SMS_TRIGGER, ///< The counter starts at a rising edge of the trigger TRGI. - TIM_SlaveMode_External1 = TIM_SMCR_SMS_EXTERNAL1 ///< Rising edges of the selected trigger (TRGI) clock the counter. -} TIMSMSMODE_Typedef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_Event_Source -/// @anchor TIM_Event_Source -typedef enum { - TIM_EventSource_Update = TIM_EGR_UG, ///< Timer update Event source - TIM_EventSource_CC1 = TIM_EGR_CC1G, ///< Timer Capture Compare 1 Event source - TIM_EventSource_CC2 = TIM_EGR_CC2G, ///< Timer Capture Compare 2 Event source - TIM_EventSource_CC3 = TIM_EGR_CC3G, ///< Timer Capture Compare 3 Event source - TIM_EventSource_CC4 = TIM_EGR_CC4G, ///< Timer Capture Compare 4 Event source - TIM_EventSource_COM = TIM_EGR_COMG, ///< Timer COM event source - TIM_EventSource_Trigger = TIM_EGR_TG, ///< Timer Trigger Event source - TIM_EventSource_Break = TIM_EGR_BG, ///< Timer Break event source - TIM_EventSource_CC5 = (s32)0x00010000, ///< Timer Capture Compare 5 Event source -} TIMEGR_Typedef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_External_Trigger_Prescaler -/// @anchor TIM_External_Trigger_Prescaler -typedef enum { - TIM_ExtTRGPSC_OFF = TIM_SMCR_ETPS_OFF, ///< ETRP Prescaler OFF - TIM_ExtTRGPSC_DIV2 = TIM_SMCR_ETPS_DIV2, ///< ETRP frequency divided by 2 - TIM_ExtTRGPSC_DIV4 = TIM_SMCR_ETPS_DIV4, ///< ETRP frequency divided by 4 - TIM_ExtTRGPSC_DIV8 = TIM_SMCR_ETPS_DIV8 ///< ETRP frequency divided by 8 -} TIMEXTTRGPSC_Typedef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_TIx_External_Clock_Source -/// @anchor TIM_TIx_External_Clock_Source -typedef enum { - TIM_TIxExternalCLK1Source_TI1 = TIM_SMCR_TS_TI1FP1, ///< Filtered Timer Input 1 - TIM_TIxExternalCLK1Source_TI2 = TIM_SMCR_TS_TI2FP2, ///< Filtered Timer Input 2 - TIM_TIxExternalCLK1Source_TI1ED = TIM_SMCR_TS_TI1F_ED ///< TI1 Edge Detector -} TIM_TIEXTCLKSRC_Typedef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Lock_level -/// @anchor Lock_level -typedef enum { - TIM_LOCKLevel_OFF = TIM_BDTR_LOCK_OFF, ///< No bit is write protected. - TIM_LOCKLevel_1 = TIM_BDTR_LOCK_1, ///< DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 - ///< register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written. - TIM_LOCKLevel_2 = TIM_BDTR_LOCK_2, ///< LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER - ///< register, as s32 as the related channel is configured in output through the CCxS - ///< bits) as well as OSSR and OSSI bits can no longer be written. - TIM_LOCKLevel_3 = TIM_BDTR_LOCK_3 ///< LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, - ///< as s32 as the related channel is configured in output through the CCxS bits) - ///< can no longer be written. -} TIMLOCKLEVEL_Typedef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_One_Pulse_Mode -/// @anchor TIM_One_Pulse_Mode -typedef enum { - TIM_OPMode_Repetitive = 0, ///< Counter is not stopped at update event - TIM_OPMode_Single = TIM_CR1_OPM ///< Counter stops counting at the next update event (clearing the bit CEN) -} TIMOPMODE_Typedef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_Output_Compare_Polarity -/// @anchor TIM_Output_Compare_Polarity -typedef enum { - TIM_OCPolarity_High, ///< Output Compare active high - TIM_OCPolarity_Low = TIM_CCER_CC1P ///< Output Compare active low -} TIMCCxP_Typedef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_Output_Compare_N_Polarity -/// @anchor TIM_Output_Compare_N_Polarity -typedef enum { - TIM_OCNPolarity_High, ///< Output Compare active high - TIM_OCNPolarity_Low = TIM_CCER_CC1NP ///< Output Compare active low -} TIMCCxNP_Typedef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_Output_Compare_state -/// @anchor TIM_Output_Compare_state -typedef enum { - TIM_OutputState_Disable = 0, ///< Output Compare Disable - TIM_OutputState_Enable = TIM_CCER_CC1EN ///< Output Compare Enable -} TIMOUTPUTSTATE_Typedef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_Output_Compare_N_state -/// @anchor TIM_Output_Compare_N_state -typedef enum { - TIM_OutputNState_Disable = 0, ///< Output Compare N Disable - TIM_OutputNState_Enable = TIM_CCER_CC1NEN ///< Output Compare N Enable -} TIMOUTPUTNSTATE_Typedef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_Capture_Compare_state -/// @anchor TIM_Capture_Compare_state -typedef enum { - TIM_CCx_Disable = 0, ///< Capture/Compare Enable - TIM_CCx_Enable = TIM_CCER_CC1EN ///< Capture/Compare Enable -} TIMCCxE_Typedef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_Capture_Compare_N_state -/// @anchor TIM_Capture_Compare_N_state -typedef enum { - TIM_CCxN_Disable = 0, ///< Capture/Compare N Enable - TIM_CCxN_Enable = TIM_CCER_CC1NEN ///< Capture/Compare N Enable -} TIMCCxNE_Typedef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Break_Input_enable_disable -/// @anchor Break_Input_enable_disable -typedef enum { - TIM_Break_Disable = 0, ///< Break inputs (BRK and CSS clock failure event) disabled - TIM_Break_Enable = TIM_BDTR_BKEN ///< Break inputs (BRK and CSS clock failure event) enabled -} TIMBKE_Typedef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Break_Polarity -/// @anchor Break_Polarity -typedef enum { - TIM_BreakPolarity_Low = 0, ///< Break input BRK is active low - TIM_BreakPolarity_High = TIM_BDTR_BKP ///< Break input BRK is active high -} TIMBKP_Typedef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_AOE_Bit_Set_Reset -/// @anchor TIM_AOE_Bit_Set_Reset -typedef enum { - TIM_AutomaticOutput_Disable = 0, ///< MOE can be set only by software. - TIM_AutomaticOutput_Enable = TIM_BDTR_AOEN ///< MOE can be set by software or automatically at the next - ///< update event (if the break input is not be active). -} TIMAOE_Typedef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_DOE_Bit_Set_Reset -/// @anchor TIM_DOE_Bit_Set_Reset -typedef enum { - TIM_DirectOutput_Disable = 0, ///< Direct output disable, output waiting for dead time - TIM_DirectOutput_Enable = TIM_BDTR_DOEN ///< Direct output enable, no longer waiting for output after dead time -} TIMDOE_Typedef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief OSSI_Off_State_Selection_for_Idle_mode_state -/// @anchor OSSI_Off_State_Selection_for_Idle_mode_state -typedef enum { - TIM_OSSIState_Disable = 0, ///< When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0). - TIM_OSSIState_Enable = TIM_BDTR_OSSI ///< When inactive, OC/OCN outputs are forced first with their idle level - ///< as soon as CCxE=1 or CCxNE=1. OC/OCN enable output signal=1). -} TIMOSSI_Typedef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief OSSR_Off_State_Selection_for_Run_mode_state -/// @anchor OSSR_Off_State_Selection_for_Run_mode_state -typedef enum { - TIM_OSSRState_Disable = 0, ///< When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0). - TIM_OSSRState_Enable = TIM_BDTR_OSSR ///< When inactive, OC/OCN outputs are enabled with their inactive level - ///< as soon as CCxE=1 or CCxNE=1. Then, OC/OCN enable output signal=1. -} TIMOSSR_Typedef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_Output_Compare_Idle_State -/// @anchor TIM_Output_Compare_Idle_State -typedef enum { - TIM_OCIdleState_Reset = 0, ///< OCn=0 (after a dead-time if OCnN is implemented) when MOE=0.(n= 0 : 4) - TIM_OCIdleState_Set = TIM_CR2_OIS1 ///< OCn=1 (after a dead-time if OCnN is implemented) when MOE=0.(n= 0 : 4) -} TIMOIS_Typedef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_Output_Compare_N_Idle_State -/// @anchor TIM_Output_Compare_N_Idle_State -typedef enum { - TIM_OCNIdleState_Reset = 0, ///< OCnN=0 after a dead-time when MOE=0.(n= 0 : 4) - TIM_OCNIdleState_Set = TIM_CR2_OIS1N ///< OCnN=1 after a dead-time when MOE=0.(n= 0 : 4) -} TIMOISN_Typedef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_Input_Capture_Selection -/// @anchor TIM_Input_Capture_Selection -typedef enum { - TIM_ICSelection_DirectTI = TIM_CCMR1_CC1S_DIRECTTI, - TIM_ICSelection_IndirectTI = TIM_CCMR1_CC1S_INDIRECTTI, - TIM_ICSelection_TRC = TIM_CCMR1_CC1S_TRC ///< TIM Input is selected to be connected to TRC. -} TIMICSEL_Typedef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_Input_Capture_Prescaler -/// @anchor TIM_Input_Capture_Prescaler -typedef enum { - TIM_ICPSC_DIV1 = 0x0000, ///< no prescaler - TIM_ICPSC_DIV2 = 0x0004, ///< capture is done once every 2 events - TIM_ICPSC_DIV4 = 0x0008, ///< capture is done once every 4 events - TIM_ICPSC_DIV8 = 0x000C ///< capture is done once every 8 events -} TIMICPSC_Typedef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_Input_Capture_Polarity -/// @anchor TIM_Input_Capture_Polarity -typedef enum { - TIM_ICPolarity_Rising = 0, ///< IC Rising edge - TIM_ICPolarity_Falling = TIM_CCER_CC1P, ///< IC Falling edge - TIM_ICPolarity_BothEdge = TIM_CCER_CC1P | TIM_CCER_CC1NP -} TIMICP_Typedef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_External_Trigger_Polarity -/// @anchor TIM_External_Trigger_Polarity -typedef enum { - TIM_ExtTRGPolarity_NonInverted = 0, ///< Active high or rising edge active - TIM_ExtTRGPolarity_Inverted = TIM_SMCR_ETP ///< Active low or falling edge active -} TIMETP_Typedef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_Prescaler_Reload_Mode -/// @anchor TIM_Prescaler_Reload_Mode -typedef enum { - TIM_PSCReloadMode_Update = 0, ///< The Prescaler is loaded at the update event - TIM_PSCReloadMode_Immediate = TIM_EGR_UG ///< The Prescaler is loaded immediately -} TIMUG_Typedef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_Encoder_Mode -/// @anchor TIM_Encoder_Mode -typedef enum { - TIM_EncoderMode_TI1 = TIM_SMCR_SMS_ENCODER1, ///< Counter counts on TI1FP1 edge depending on TI2FP2 level. - TIM_EncoderMode_TI2 = TIM_SMCR_SMS_ENCODER2, ///< Counter counts on TI2FP2 edge depending on TI1FP1 level. - TIM_EncoderMode_TI12 = TIM_SMCR_SMS_ENCODER3 ///< Counter counts on both TI1FP1 and TI2FP2 edges depending - ///< on the level of the other input. -} TIMSMSENCODER_Typedef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_Update_Source -/// @anchor TIM_Update_Source -typedef enum { - TIM_UpdateSource_Global = 0, ///< Source of update is counter overflow/underflow. - TIM_UpdateSource_Regular = TIM_CR1_URS ///< Source of update is the counter overflow/underflow - ///< or the setting of UG bit, or an update generation - ///< through the slave mode controller. -} TIMURS_Typedef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_Output_Compare_Preload_State -/// @anchor TIM_Output_Compare_Preload_State -typedef enum { - TIM_OCPreload_Disable = 0, ///< TIM output compare preload disable - TIM_OCPreload_Enable = TIM_CCMR1_OC1PEN ///< TIM output compare preload enable -} TIMOCPE_Typedef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_Output_Compare_Fast_State -/// @anchor TIM_Output_Compare_Fast_State -typedef enum { - TIM_OCFast_Disable = 0, ///< TIM output compare fast disable - TIM_OCFast_Enable = TIM_CCMR1_OC1FEN, ///< TIM output compare fast enable -} TIMOCFE_Typedef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_Output_Compare_Clear_State -/// @anchor TIM_Output_Compare_Clear_State -typedef enum { - TIM_OCClear_Disable = 0, ///< TIM Output clear disable - TIM_OCClear_Enable = TIM_CCMR1_OC1CEN ///< TIM Output clear enable -} TIMOCCE_Typedef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_Master_Slave_Mode -/// @anchor TIM_Master_Slave_Mode -typedef enum { - TIM_MasterSlaveMode_Disable = 0, ///< No action - TIM_MasterSlaveMode_Enable = TIM_SMCR_MSM ///< synchronization between the current timer and its slaves (through TRIG) -} TIMMSM_Typedef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_interrupt_sources -/// @anchor TIM_Master_Slave_Mode -typedef enum { - TIM_IT_Update = TIM_DIER_UI, ///< TIM update Interrupt source - TIM_IT_CC1 = TIM_DIER_CC1I, ///< TIM Capture Compare 1 Interrupt source - TIM_IT_CC2 = TIM_DIER_CC2I, ///< TIM Capture Compare 2 Interrupt source - TIM_IT_CC3 = TIM_DIER_CC3I, ///< TIM Capture Compare 3 Interrupt source - TIM_IT_CC4 = TIM_DIER_CC4I, ///< TIM Capture Compare 4 Interrupt source - TIM_IT_COM = TIM_DIER_COMI, ///< TIM Commutation Interrupt source - TIM_IT_Trigger = TIM_DIER_TI, ///< TIM Trigger Interrupt source - TIM_IT_Break = TIM_DIER_BI ///< TIM Break Interrupt source - , TIM_IT_CC5 = TIM_DIER_CC5I ///< TIM Capture Compare 5 Interrupt source -} TIMIT_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_Flags -/// @anchor TIM_Flags -typedef enum { - TIM_FLAG_Update = TIM_SR_UI, ///< TIM update Flag - TIM_FLAG_CC1 = TIM_SR_CC1I, ///< TIM Capture Compare 1 Flag - TIM_FLAG_CC2 = TIM_SR_CC2I, ///< TIM Capture Compare 2 Flag - TIM_FLAG_CC3 = TIM_SR_CC3I, ///< TIM Capture Compare 3 Flag - TIM_FLAG_CC4 = TIM_SR_CC4I, ///< TIM Capture Compare 4 Flag - TIM_FLAG_COM = TIM_SR_COMI, ///< TIM Commutation Flag - TIM_FLAG_Trigger = TIM_SR_TI, ///< TIM Trigger Flag - TIM_FLAG_Break = TIM_SR_BI, ///< TIM Break Flag - TIM_FLAG_CC1OF = TIM_SR_CC1O, ///< TIM Capture Compare 1 overcapture Flag - TIM_FLAG_CC2OF = TIM_SR_CC2O, ///< TIM Capture Compare 2 overcapture Flag - TIM_FLAG_CC3OF = TIM_SR_CC3O, ///< TIM Capture Compare 3 overcapture Flag - TIM_FLAG_CC4OF = TIM_SR_CC4O ///< TIM Capture Compare 4 overcapture Flag - , TIM_FLAG_CC5 = TIM_SR_CC5I ///< TIM Capture Compare 5 Flag -} TIMFLAG_Typedef; -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_DMA_sources -/// @anchor TIM_DMA_sources -typedef enum { - TIM_DMA_Update = TIM_DIER_UD, ///< TIM update Interrupt source - TIM_DMA_CC1 = TIM_DIER_CC1D, ///< TIM Capture Compare 1 DMA source - TIM_DMA_CC2 = TIM_DIER_CC2D, ///< TIM Capture Compare 2 DMA source - TIM_DMA_CC3 = TIM_DIER_CC3D, ///< TIM Capture Compare 3 DMA source - TIM_DMA_CC4 = TIM_DIER_CC4D, ///< TIM Capture Compare 4 DMA source - TIM_DMA_COM = TIM_DIER_COMD, ///< TIM Commutation DMA source - TIM_DMA_Trigger = TIM_DIER_TD ///< TIM Trigger DMA source -} TIMDMASRC_Typedef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_DMA_Base_address -/// @anchor TIM_DMA_Base_address -typedef enum { - TIM_DMABase_CR1 = 0x0000, - TIM_DMABase_CR2 = 0x0001, - TIM_DMABase_SMCR = 0x0002, - TIM_DMABase_DIER = 0x0003, - TIM_DMABase_SR = 0x0004, - TIM_DMABase_EGR = 0x0005, - TIM_DMABase_CCMR1 = 0x0006, - TIM_DMABase_CCMR2 = 0x0007, - TIM_DMABase_CCER = 0x0008, - TIM_DMABase_CNT = 0x0009, - TIM_DMABase_PSC = 0x000A, - TIM_DMABase_ARR = 0x000B, - TIM_DMABase_RCR = 0x000C, - TIM_DMABase_CCR1 = 0x000D, - TIM_DMABase_CCR2 = 0x000E, - TIM_DMABase_CCR3 = 0x000F, - TIM_DMABase_CCR4 = 0x0010, - TIM_DMABase_BDTR = 0x0011, - TIM_DMABase_DCR = 0x0012 -} TIMDMABASE_Typedef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_DMA_Burst_Length -/// @anchor TIM_DMA_Burst_Length -typedef enum { - TIM_DMABurstLength_1Byte = 0x0000, - TIM_DMABurstLength_2Bytes = 0x0100, - TIM_DMABurstLength_3Bytes = 0x0200, - TIM_DMABurstLength_4Bytes = 0x0300, - TIM_DMABurstLength_5Bytes = 0x0400, - TIM_DMABurstLength_6Bytes = 0x0500, - TIM_DMABurstLength_7Bytes = 0x0600, - TIM_DMABurstLength_8Bytes = 0x0700, - TIM_DMABurstLength_9Bytes = 0x0800, - TIM_DMABurstLength_10Bytes = 0x0900, - TIM_DMABurstLength_11Bytes = 0x0A00, - TIM_DMABurstLength_12Bytes = 0x0B00, - TIM_DMABurstLength_13Bytes = 0x0C00, - TIM_DMABurstLength_14Bytes = 0x0D00, - TIM_DMABurstLength_15Bytes = 0x0E00, - TIM_DMABurstLength_16Bytes = 0x0F00, - TIM_DMABurstLength_17Bytes = 0x1000, - TIM_DMABurstLength_18Bytes = 0x1100 -} TIMDMABURSTLENGTH_Typedef; -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM Time Base Init structure definition -/// @note This structure is used with all tim. -//////////////////////////////////////////////////////////////////////////////// -typedef struct { - u16 TIM_Prescaler; ///< Specifies the prescaler value used to divide the TIM clock. - ///< This parameter can be a number between 0x0000 and 0xFFFF - TIMCOUNTMODE_Typedef TIM_CounterMode; ///< Specifies the counter mode. - ///< This parameter can be a value of @ref TIM_Counter_Mode - u32 TIM_Period; ///< Specifies the period value to be loaded into the active - ///< Auto-Reload Register at the next update event. - ///< This parameter must be a number between 0x0000 and 0xFFFF/0xFFFFFFFF. - ///< @note 0xFFFFFFFF is valid only for MM32 32bit Timers: eg.TIM2 or TIM5. - TIMCKD_TypeDef TIM_ClockDivision; ///< Specifies the clock division. - ///< This parameter can be a value of @ref TIM_Clock_Division_CKD - u8 TIM_RepetitionCounter; ///< Specifies the repetition counter value. Each time the RCR downcounter - ///< reaches zero, an update event is generated and counting restarts - ///< from the RCR value (N). - ///< This means in PWM mode that (N+1) corresponds to: - ///< - the number of PWM periods in edge-aligned mode - ///< - the number of half PWM period in center-aligned mode - ///< This parameter must be a number between 0x00 and 0xFF. - ///< @note This parameter is valid only for TIM1 and TIM8. -} TIM_TimeBaseInitTypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM Output Compare Init structure definition -//////////////////////////////////////////////////////////////////////////////// -typedef struct { - TIMOCMODE_Typedef TIM_OCMode; ///< Specifies the TIM mode. - ///< This parameter can be a value of TIM_Output_Compare_and_PWM_modes - TIMOUTPUTSTATE_Typedef TIM_OutputState; ///< Specifies the TIM Output Compare state. - ///< This parameter can be a value of TIM_Output_Compare_state - TIMOUTPUTNSTATE_Typedef TIM_OutputNState; ///< Specifies the TIM complementary Output Compare state. - ///< This parameter can be a value of TIM_Output_Compare_N_state - ///< @note This parameter is valid only for TIM1 and TIM8. - u32 TIM_Pulse; ///< Specifies the pulse value to be loaded into the Capture Compare Register. - ///< This parameter can be a number between 0x0000 and 0xFFFF/0xFFFFFFFF - ///< @note 0xFFFFFFFF is valid only for MM32 32bit Timers: eg.TIM2 or TIM5. - TIMCCxP_Typedef TIM_OCPolarity; ///< Specifies the output polarity. - ///< This parameter can be a value of @ref TIM_Output_Compare_Polarity - TIMCCxNP_Typedef TIM_OCNPolarity; ///< Specifies the complementary output polarity. - ///< This parameter can be a value of @ref TIM_Output_Compare_N_Polarity - ///< @note This parameter is valid only for TIM1 and TIM8. - TIMOIS_Typedef TIM_OCIdleState; ///< Specifies the TIM Output Compare pin state during Idle state. - ///< This parameter can be a value of @ref TIM_Output_Compare_Idle_State - ///< @note This parameter is valid only for TIM1 and TIM8. - TIMOISN_Typedef TIM_OCNIdleState; ///< Specifies the TIM Output Compare pin state during Idle state. - ///< This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State - ///< @note This parameter is valid only for TIM1 and TIM8. -} TIM_OCInitTypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM Input Capture Init structure definition -//////////////////////////////////////////////////////////////////////////////// -typedef struct { - TIMCHx_Typedef TIM_Channel; ///< Specifies the TIM channel. - ///< This parameter can be a value of @ref TIM_Channel - TIMICP_Typedef TIM_ICPolarity; ///< Specifies the active edge of the input signal. - ///< This parameter can be a value of @ref TIM_Input_Capture_Polarity - TIMICSEL_Typedef TIM_ICSelection; ///< Specifies the input. - ///< This parameter can be a value of @ref TIM_Input_Capture_Selection - TIMICPSC_Typedef TIM_ICPrescaler; ///< Specifies the Input Capture Prescaler. - ///< This parameter can be a value of @ref TIM_Input_Capture_Prescaler - u16 TIM_ICFilter; ///< Specifies the input capture filter. - ///< This parameter can be a number between 0x0 and 0xF -} TIM_ICInitTypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief BDTR structure definition -/// @note This structure is used only with TIM1 and TIM8. -//////////////////////////////////////////////////////////////////////////////// -typedef struct { - TIMOSSR_Typedef TIM_OSSRState; ///< Specifies the Off-State selection used in Run mode. - ///< This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state - TIMOSSI_Typedef TIM_OSSIState; ///< Specifies the Off-State used in Idle state. - ///< This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state - TIMLOCKLEVEL_Typedef TIM_LOCKLevel; ///< Specifies the LOCK level parameters. - ///< This parameter can be a value of @ref Lock_level - u16 TIM_DeadTime; ///< Specifies the delay time between the switching-off and - ///< the switching-on of the outputs. - ///< This parameter can be a number between 0x00 and 0xFF - TIMBKE_Typedef TIM_Break; ///< Specifies whether the TIM Break input is enabled or not. - ///< This parameter can be a value of @ref Break_Input_enable_disable - TIMBKP_Typedef TIM_BreakPolarity; ///< Specifies the TIM Break Input pin polarity. - ///< This parameter can be a value of @ref Break_Polarity - TIMAOE_Typedef TIM_AutomaticOutput; ///< Specifies whether the TIM Automatic Output feature is enabled or not. - ///< This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset -} TIM_BDTRInitTypeDef; -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup TIM_Exported_Variables -/// @{ -#ifdef _HAL_TIM_C_ -#define GLOBAL - -static void TI1_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter); -static void TI2_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter); -static void TI3_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter); -static void TI4_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter); - - -#else -#define GLOBAL extern -#endif - -#undef GLOBAL -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup TIM_Exported_Functions -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -//================= TimeBase management ====================================== -void TIM_DeInit(TIM_TypeDef* tim); -void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* init_struct); -void TIM_TimeBaseInit(TIM_TypeDef* tim, TIM_TimeBaseInitTypeDef* init_struct); -void TIM_PrescalerConfig(TIM_TypeDef* tim, u16 prescaler, TIMUG_Typedef reload_mode); -void TIM_CounterModeConfig(TIM_TypeDef* tim, TIMCOUNTMODE_Typedef counter_mode); -void TIM_SetCounter(TIM_TypeDef* tim, u32 counter); -void TIM_SetAutoreload(TIM_TypeDef* tim, u16 auto_reload); -void TIM_UpdateDisableConfig(TIM_TypeDef* tim, FunctionalState state); -void TIM_UpdateRequestConfig(TIM_TypeDef* tim, TIMURS_Typedef source); -void TIM_ARRPreloadConfig(TIM_TypeDef* tim, FunctionalState state); -void TIM_SelectOnePulseMode(TIM_TypeDef* tim, TIMOPMODE_Typedef mode); -void TIM_SetClockDivision(TIM_TypeDef* tim, TIMCKD_TypeDef clock_div); -void TIM_Cmd(TIM_TypeDef* tim, FunctionalState state); - -u32 TIM_GetCounter(TIM_TypeDef* tim); -u16 TIM_GetPrescaler(TIM_TypeDef* tim); - -//================= Advanced-control timers specific features ================ -void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* init_struct); -void TIM_BDTRConfig(TIM_TypeDef* tim, TIM_BDTRInitTypeDef* init_struct); -void TIM_CtrlPWMOutputs(TIM_TypeDef* tim, FunctionalState state); - -//================= Output Compare management ================================ -void TIM_OCStructInit(TIM_OCInitTypeDef* init_struct); -void TIM_OC1Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct); -void TIM_OC2Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct); -void TIM_OC3Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct); -void TIM_OC4Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct); -void TIM_SelectOCxM(TIM_TypeDef* tim, TIMCHx_Typedef channel, TIMOCMODE_Typedef mode); -void TIM_SetCompare1(TIM_TypeDef* tim, u32 compare); -void TIM_SetCompare2(TIM_TypeDef* tim, u32 compare); -void TIM_SetCompare3(TIM_TypeDef* tim, u32 compare); -void TIM_SetCompare4(TIM_TypeDef* tim, u32 compare); -void TIM_ForcedOC1Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action); -void TIM_ForcedOC2Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action); -void TIM_ForcedOC3Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action); -void TIM_ForcedOC4Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action); -void TIM_CCPreloadControl(TIM_TypeDef* tim, FunctionalState state); -void TIM_OC1PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload); -void TIM_OC2PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload); -void TIM_OC3PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload); -void TIM_OC4PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload); -void TIM_OC1FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast); -void TIM_OC2FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast); -void TIM_OC3FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast); -void TIM_OC4FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast); -void TIM_ClearOC1Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear); -void TIM_ClearOC2Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear); -void TIM_ClearOC3Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear); -void TIM_ClearOC4Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear); -void TIM_OC1PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity); -void TIM_OC1NPolarityConfig(TIM_TypeDef* tim, TIMCCxNP_Typedef polarity); -void TIM_OC2PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity); -void TIM_OC2NPolarityConfig(TIM_TypeDef* tim, TIMCCxNP_Typedef polarity); -void TIM_OC3PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity); -void TIM_OC3NPolarityConfig(TIM_TypeDef* tim, TIMCCxNP_Typedef polarity); -void TIM_OC4PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity); -void TIM_CCxCmd(TIM_TypeDef* tim, TIMCHx_Typedef channel, TIMCCxE_Typedef ccx_en); -void TIM_CCxNCmd(TIM_TypeDef* tim, TIMCHx_Typedef channel, TIMCCxNE_Typedef ccxn_en); -void TIM_SelectCOM(TIM_TypeDef* tim, FunctionalState state); - -//================= Input Capture management ================================= -void TIM_ICStructInit(TIM_ICInitTypeDef* init_struct); -void TIM_ICInit(TIM_TypeDef* tim, TIM_ICInitTypeDef* init_struct); -void TIM_PWMIConfig(TIM_TypeDef* tim, TIM_ICInitTypeDef* init_struct); -void TIM_SetIC1Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc); -void TIM_SetIC2Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc); -void TIM_SetIC3Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc); -void TIM_SetIC4Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc); - -u32 TIM_GetCapture1(TIM_TypeDef* tim); -u32 TIM_GetCapture2(TIM_TypeDef* tim); -u32 TIM_GetCapture3(TIM_TypeDef* tim); -u32 TIM_GetCapture4(TIM_TypeDef* tim); - -//================= Interrupts, DMA and flags management ===================== -void TIM_ITConfig(TIM_TypeDef* tim, u32 it, FunctionalState state);//TIMIT_TypeDef -void TIM_GenerateEvent(TIM_TypeDef* tim, TIMEGR_Typedef source); -void TIM_ClearFlag(TIM_TypeDef* tim, TIMFLAG_Typedef flag); -void TIM_ClearITPendingBit(TIM_TypeDef* tim, u32 it);//TIMIT_TypeDef -void TIM_DMAConfig(TIM_TypeDef* tim, TIMDMABASE_Typedef dma_base, TIMDMABURSTLENGTH_Typedef length); -void TIM_DMACmd(TIM_TypeDef* tim, TIMDMASRC_Typedef source, FunctionalState state); -void TIM_SelectCCDMA(TIM_TypeDef* tim, FunctionalState state); -FlagStatus TIM_GetFlagStatus(TIM_TypeDef* tim, TIMFLAG_Typedef flag); -ITStatus TIM_GetITStatus(TIM_TypeDef* tim, TIMIT_TypeDef it); - -//================= Clocks management ======================================== -void TIM_InternalClockConfig(TIM_TypeDef* tim); -void TIM_ITRxExternalClockConfig(TIM_TypeDef* tim, TIMTS_TypeDef source); -void TIM_TIxExternalClockConfig(TIM_TypeDef* tim, TIM_TIEXTCLKSRC_Typedef source, TIMICP_Typedef polarity, u16 filter); -void TIM_ETRClockMode1Config(TIM_TypeDef* tim, TIMEXTTRGPSC_Typedef psc, TIMETP_Typedef polarity, u16 filter); -void TIM_ETRClockMode2Config(TIM_TypeDef* tim, TIMEXTTRGPSC_Typedef psc, TIMETP_Typedef polarity, u16 filter); - -//================= Synchronization management =============================== -void TIM_SelectInputTrigger(TIM_TypeDef* tim, TIMTS_TypeDef source); -void TIM_SelectOutputTrigger(TIM_TypeDef* tim, TIMMMS_Typedef source); -void TIM_SelectSlaveMode(TIM_TypeDef* tim, TIMSMSMODE_Typedef mode); -void TIM_SelectMasterSlaveMode(TIM_TypeDef* tim, TIMMSM_Typedef mode); -void TIM_ETRConfig(TIM_TypeDef* tim, TIMEXTTRGPSC_Typedef psc, TIMETP_Typedef polarity, u16 filter); - -//================= Specific interface management ============================ -void TIM_EncoderInterfaceConfig(TIM_TypeDef* tim, - TIMSMSENCODER_Typedef encoder_mode, - TIMICP_Typedef ic1_polarity, - TIMICP_Typedef iC2_polarity); -void TIM_SelectHallSensor(TIM_TypeDef* tim, FunctionalState state); - -//================= extend Channel IC management ============================== -void TIM_SetIC1Plority(TIM_TypeDef* tim, TIMICP_Typedef pol); -void TIM_SetIC2Plority(TIM_TypeDef* tim, TIMICP_Typedef pol); -void TIM_SetIC3Plority(TIM_TypeDef* tim, TIMICP_Typedef pol); -void TIM_SetIC4Plority(TIM_TypeDef* tim, TIMICP_Typedef pol); - -#define exTIM_SetIC1Plority TIM_SetIC1Plority -#define exTIM_SetIC2Plority TIM_SetIC2Plority -#define exTIM_SetIC3Plority TIM_SetIC3Plority -#define exTIM_SetIC4Plority TIM_SetIC4Plority -//================= extend Channel 5 management ============================== - -void TIM_SetCompare5(TIM_TypeDef* tim, u32 compare); -void TIM_OC5Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct); -void TIM_OC5PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload); -void TIM_OC5PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity); -void TIM_OC5FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast); -void TIM_ClearOC5Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear); -u32 TIM_GetCapture5(TIM_TypeDef* tim); - -#define exTIM_SetCompare5 TIM_SetCompare5 -#define exTIM_OC5Init TIM_OC5Init -#define exTIM_OC5PreloadConfig TIM_OC5PreloadConfig -#define exTIM_OC5PolarityConfig TIM_OC5PolarityConfig -#define exTIM_OC5FastConfig TIM_OC5FastConfig -#define exTIM_ClearOC5Ref TIM_ClearOC5Ref -#define exTIM_GetCapture5 TIM_GetCapture5 - -//============= extend Advanced-control timers specific features ============== -void TIM_DirectOutput(TIM_TypeDef* tim, FunctionalState state); -#define exTIM_DirectOutput TIM_DirectOutput -void TIM_PWMShiftConfig(TIM_TypeDef* tim, u32 it, FunctionalState state); -void TIM_SetCCR1FALL(TIM_TypeDef* tim, u32 shift); -void TIM_SetCCR2FALL(TIM_TypeDef* tim, u32 shift); -void TIM_SetCCR3FALL(TIM_TypeDef* tim, u32 shift); -void TIM_SetCCR4FALL(TIM_TypeDef* tim, u32 shift); -void TIM_SetCCR5FALL(TIM_TypeDef* tim, u32 shift); -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -#endif // __HAL_TIM_H -//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_uart.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_uart.h deleted file mode 100644 index a46f234e0..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_uart.h +++ /dev/null @@ -1,211 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_uart.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE UART -/// FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#ifndef __HAL_UART_H -#define __HAL_UART_H - -// Files includes -#include "reg_uart.h" - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -/////////////////////////////////////1/////////////////////////////////////////// -/// @defgroup UART_HAL -/// @brief UART HAL modules -/// @{ - - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup UART_Exported_Types -/// @{ -/// - -//////////////////////////////////////////////////////////////////////////////// -/// @brief UART Word Length Enumerate definition -/// @anchor UART_Word_Length -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - UART_WordLength_5b = 0U, - UART_WordLength_6b = 1U << UART_CCR_CHAR_Pos, - UART_WordLength_7b = 2U << UART_CCR_CHAR_Pos, - UART_WordLength_8b = 3U << UART_CCR_CHAR_Pos -} UART_WordLength_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief UART Stop Bits Enumerate definition -/// @anchor UART_Stop_Bits -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - UART_StopBits_1 = 0U, - UART_StopBits_2 = UART_CCR_SPB, - - UART_StopBits_0_5 = UART_CCR_SPB1, - UART_StopBits_1_5 = UART_CCR_SPB1 | UART_CCR_SPB0, -} UART_Stop_Bits_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief UART Parity Enumerate definition -/// @anchor UART_Parity -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - UART_Parity_No = 0U, - UART_Parity_Even = UART_CCR_PEN | UART_CCR_PSEL, - UART_Parity_Odd = UART_CCR_PEN -} UART_Parity_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief UART Hardware Flow Control Enumerate definition -/// @anchor UART_Hardware_Flow_Control -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - UART_HWFlowControl_None = 0U, - - // UART_HWFlowControl_RTS = UART_GCR_AUTOFLOW, - // UART_HWFlowControl_CTS = UART_GCR_AUTOFLOW, - - UART_HWFlowControl_RTS_CTS = UART_GCR_AUTOFLOW -} UART_HW_FLOWCONTROL_TypeDef; - -typedef enum { - UART_WakeUp_IdleLine = 0U, // - UART_WakeUp_AddressMark = UART_CCR_WAKE -} UART_WakeUp_TypeDef; - -typedef enum { - UART_9bit_Polarity_Low = 0U, // - UART_9bit_Polarity_High = UART_CCR_B8POL -} UART_9bit_Polarity_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief UART Auto BaudRate definition -//////////////////////////////////////////////////////////////////////////////// -typedef enum { - Data_F8 = 0, - Data_FE, - ABRMODE_FALLING_TO_RISINGEDGE1BIT, - ABRMODE_FALLING_TO_RISINGEDGE2BIT, - ABRMODE_FALLING_TO_RISINGEDGE4BIT, - ABRMODE_FALLING_TO_RISINGEDGE8BIT, - ABRMODE_FALLING_TO_FALLINGEDGE2BIT, - ABRMODE_FALLING_TO_FALLINGEDGE4BIT, - ABRMODE_FALLING_TO_FALLINGEDGE8BIT, - ABRMODE_STARTBIT, - ABRMODE_VALUE0X55, - ABRMODE_VALUE0x7F, - ABRMODE_VALUE0X80, - ABRMODE_VALUE0XF7, - ABRMODE_VALUE0XF8 = Data_F8, - ABRMODE_VALUE0XFE = Data_FE, - ABRMODE_VALUE0XFF, -} UART_AutoBaud_TypeDef; -//////////////////////////////////////////////////////////////////////////////// -/// @brief UART Init Structure definition -//////////////////////////////////////////////////////////////////////////////// -typedef struct { - union { - u32 BaudRate; ///< This member configures the UART communication baud rate. - u32 UART_BaudRate; - }; - union { - UART_WordLength_TypeDef WordLength; ///< Specifies the number of data bits transmitted or received in a frame. - u16 UART_WordLength; - }; - union { - UART_Stop_Bits_TypeDef StopBits; ///< Specifies the number of stop bits transmitted. - u16 UART_StopBits; - }; - union { - UART_Parity_TypeDef Parity; ///< Specifies the parity mode. - u16 UART_Parity; - }; - union { - u16 Mode; ///< Specifies wether the Receive or Transmit mode is - u16 UART_Mode; - }; - union { - UART_HW_FLOWCONTROL_TypeDef HWFlowControl; ///< Specifies wether the hardware flow control mode is enabled or disabled. - u16 UART_HardwareFlowControl; - }; -} UART_InitTypeDef; - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup UART_Exported_Constants -/// @{ - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup UART_Exported_Variables -/// @{ -#ifdef _HAL_UART_C_ - -#define GLOBAL -#else -#define GLOBAL extern -#endif - -#undef GLOBAL -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup UART_Exported_Functions -/// @{ -void UART_DeInit(UART_TypeDef* uart); -void UART_Init(UART_TypeDef* uart, UART_InitTypeDef* init_struct); -void UART_StructInit(UART_InitTypeDef* init_struct); -void UART_Cmd(UART_TypeDef* uart, FunctionalState state); -void UART_ITConfig(UART_TypeDef* uart, u16 it, FunctionalState state); -void UART_DMACmd(UART_TypeDef* uart, u16 dma_request, FunctionalState state); -void UART_SendData(UART_TypeDef* uart, u16 Data); -void UART_ClearITPendingBit(UART_TypeDef* uart, u16 it); - -u16 UART_ReceiveData(UART_TypeDef* uart); -FlagStatus UART_GetFlagStatus(UART_TypeDef* uart, u16 flag); - -ITStatus UART_GetITStatus(UART_TypeDef* uart, u16 it); - -void UART_WakeUpConfig(UART_TypeDef* uart, UART_WakeUp_TypeDef mode); -void UART_ReceiverWakeUpCmd(UART_TypeDef* uart, FunctionalState state); -void UART_SetRXAddress(UART_TypeDef* uart, u8 address); -void UART_SetRXMASK(UART_TypeDef* uart, u8 address); -void UART_Enable9bit(UART_TypeDef* uart, FunctionalState state); -void UART_Set9bitLevel(UART_TypeDef* uart, FunctionalState state); -void UART_Set9bitPolarity(UART_TypeDef* uart, UART_9bit_Polarity_TypeDef polarity); -void UART_Set9bitAutomaticToggle(UART_TypeDef* uart, FunctionalState state); -void UART_HalfDuplexCmd(UART_TypeDef* uart, FunctionalState state); -void UART_SetGuardTime(UART_TypeDef* uart, u8 guard_time); -void UART_SmartCardCmd(UART_TypeDef* uart, FunctionalState state); -void UART_SmartCardNACKCmd(UART_TypeDef* uart, FunctionalState state); -void UART_SendBreak(UART_TypeDef* uart); -void UART_AutoBaudRateCmd(UART_TypeDef* uart, FunctionalState state); -void UART_AutoBaudRateSet(UART_TypeDef* uart, UART_AutoBaud_TypeDef value, FunctionalState state); - -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -#endif // __HAL_UART_H -//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_uid.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_uid.h deleted file mode 100644 index 2dba789d2..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_uid.h +++ /dev/null @@ -1,71 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_uid.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE UID -/// FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#ifndef __HAL_UID_H -#define __HAL_UID_H - -// Files includes -#include "types.h" -#include "reg_common.h" - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup UID_HAL -/// @brief UID HAL modules -/// @{ - - -/////////////////////////////////////1/////////////////////////////////////////// -/// @defgroup UID_Exported_Variables -/// @{ -#ifdef _HAL_UID_C_ -#define GLOBAL - -#else -#define GLOBAL extern - - -#endif -GLOBAL u8 device_id_data[12]; - -#undef GLOBAL - - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup UID_Exported_Functions -/// @{ -void GetChipUID(void); - -/// @} - - - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -#endif // __HAL_UID_H -//////////////////////////////////////////////////////////////////////////////// - diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_ver.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_ver.h deleted file mode 100644 index 773af5631..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_ver.h +++ /dev/null @@ -1,89 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_ver.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE UART -/// FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#ifndef __HAL_VER_H -#define __HAL_VER_H - -// Files includes -#include "reg_common.h" -#include "reg_dbg.h" - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -/////////////////////////////////////1/////////////////////////////////////////// -/// @defgroup UART_HAL -/// @brief UART HAL modules -/// @{ - - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup UART_Exported_Types -/// @{ -/// - -//////////////////////////////////////////////////////////////////////////////// -/// @brief UART Word Length Enumerate definition -/// @anchor UART_Word_Length -//////////////////////////////////////////////////////////////////////////////// - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup UART_Exported_Constants -/// @{ - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup UART_Exported_Variables -/// @{ -#ifdef _HAL_VER_C_ - -#define GLOBAL -#else -#define GLOBAL extern -#endif - -#undef GLOBAL -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup UART_Exported_Functions -/// @{ - -u32 Get_MM32LibVersion(void); -u32 Get_ChipsetREVID(void); -u32 Get_ChipsetDEVID(void); -u32 Get_ChipsetUIDw0(void); -u32 Get_ChipsetUIDw1(void); -u32 Get_ChipsetUIDw2(void); - - - -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -#endif // __HAL_VER_H -//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_wwdg.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_wwdg.h deleted file mode 100644 index 287ddd5c8..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_wwdg.h +++ /dev/null @@ -1,90 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_wwdg.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE WWDG -/// FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT O -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDER -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#ifndef __HAL_WWDG_H -#define __HAL_WWDG_H - -// Files includes -#include "types.h" -#include "reg_wwdg.h" - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup WWDG_HAL -/// @brief WWDG HAL modules -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup WWDG_Exported_Types -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @brief WWDG_Prescaler -/// @anchor WWDG_Prescaler - -typedef enum { - WWDG_Prescaler_1 = WWDG_CFGR_WDGTB_1, - WWDG_Prescaler_2 = WWDG_CFGR_WDGTB_2, - WWDG_Prescaler_4 = WWDG_CFGR_WDGTB_4, - WWDG_Prescaler_8 = WWDG_CFGR_WDGTB_8 -} WWDG_Prescaler_Typedef; - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup WWDG_Exported_Variables -/// @{ - -#ifdef _HAL_WWDG_C_ - -#define GLOBAL -#else -#define GLOBAL extern -#endif - -#undef GLOBAL - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup WWDG_Exported_Functions -/// @{ - -void WWDG_DeInit(void); -void WWDG_SetPrescaler(u32 prescaler); -void WWDG_SetWindowValue(u8 window_value); -void WWDG_EnableIT(void); -void WWDG_SetCounter(u8 count); -u32 WWDG_GetCounter(void); -void WWDG_Enable(u8 count); -FlagStatus WWDG_GetFlagStatus(void); -void WWDG_ClearFlag(void); - -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -#endif // __HAL_WWDG_H -//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_adc.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_adc.c deleted file mode 100644 index 503e91a67..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_adc.c +++ /dev/null @@ -1,563 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_adc.c -/// @author AE TEAM -/// @brief THIS FILE PROVIDES ALL THE ADC FIRMWARE FUNCTIONS. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#define _HAL_ADC_C_ - -// Files includes -#include "hal_adc.h" -#include "hal_rcc.h" - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup ADC_HAL -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup ADC_Exported_Functions -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Deinitializes the adc peripheral registers to their default -/// reset values. -/// @param adc: select the ADC peripheral. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void ADC_DeInit(ADC_TypeDef* adc) -{ - - switch (*(vu32*)&adc) { - - case ADC1_BASE: - exRCC_APB2PeriphReset(RCC_APB2ENR_ADC1); - break; - case ADC2_BASE: - exRCC_APB2PeriphReset(RCC_APB2ENR_ADC2); - break; - case ADC3_BASE: - exRCC_APB2PeriphReset(RCC_APB2ENR_ADC3); - break; - default: - break; - } -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Initializes the adc peripheral according to the specified parameters -/// in the init_struct, Please use this function if you want to be -/// compatible with older versions of the library. -/// @param adc: select the ADC peripheral. -/// @param init_struct: pointer to an ADC_InitTypeDef structure that contains -/// the configuration information for the specified ADC peripheral. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void ADC_Init(ADC_TypeDef* adc, ADC_InitTypeDef* init_struct) -{ - adc->ADCFG &= ~(ADC_CFGR_PRE | ADC_CFGR_RSLTCTL); - adc->ADCFG |= (u32)(init_struct->ADC_PRESCARE) | init_struct->ADC_Resolution; - - adc->ADCR &= ~(ADC_CR_ALIGN | ADC_CR_MODE | ADC_CR_TRGSEL); - adc->ADCR |= ((u32)init_struct->ADC_DataAlign) | init_struct->ADC_ExternalTrigConv | ((u32)init_struct->ADC_Mode); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Fills each init_struct member with its default value. -/// @param init_struct : pointer to an ADC_InitTypeDef structure which will be -/// initialized. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void ADC_StructInit(ADC_InitTypeDef* init_struct) -{ - init_struct->ADC_Resolution = ADC_Resolution_12b; - init_struct->ADC_PRESCARE = ADC_PCLK2_PRESCARE_2; - init_struct->ADC_Mode = ADC_CR_IMM; //ADC_Mode_Single; - init_struct->ADC_ContinuousConvMode = DISABLE; // useless - init_struct->ADC_ExternalTrigConv = ADC1_ExternalTrigConv_T1_CC1; - init_struct->ADC_DataAlign = ADC_DataAlign_Right; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the specified ADC peripheral. -/// @param adc:select the ADC peripheral. -/// @param state: new state of the adc peripheral. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void ADC_Cmd(ADC_TypeDef* adc, FunctionalState state) -{ - (state) ? (adc->ADCFG |= ADC_CFGR_ADEN) : (adc->ADCFG &= ~ADC_CFGR_ADEN); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the specified ADC DMA request. -/// @param adc: select the ADC peripheral. -/// @param state: New state of the selected ADC DMA transfer. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void ADC_DMACmd(ADC_TypeDef* adc, FunctionalState state) -{ - (state) ? (adc->ADCR |= ADC_CR_DMAEN) : (adc->ADCR &= ~ADC_CR_DMAEN); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the specified ADC interrupts. -/// @param adc: select the ADC peripheral. -/// @param adc_interrupt: specifies the ADC interrupt sources to be enabled or disabled. -/// @param state: New state of the specified ADC interrupts. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void ADC_ITConfig(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_interrupt, FunctionalState state) -{ - if (adc_interrupt == ADC_IT_EOC) - (state) ? (adc->ADCR |= ADC_CR_ADIE) : (adc->ADCR &= ~ADC_CR_ADIE); - else - (state) ? (adc->ADCR |= ADC_CR_ADWIE) : (adc->ADCR &= ~ADC_CR_ADWIE); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the selected ADC software start conversion . -/// @param adc: select the ADC peripheral. -/// @param state: New state of the selected ADC software start conversion. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void ADC_SoftwareStartConvCmd(ADC_TypeDef* adc, FunctionalState state) -{ - (state) ? (adc->ADCR |= ADC_CR_ADST) : (adc->ADCR &= ~ADC_CR_ADST); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Gets the selected ADC Software start conversion Status. -/// @param adc: select the ADC peripheral. -/// @retval The new state of ADC software start conversion (SET or RESET). -//////////////////////////////////////////////////////////////////////////////// -FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* adc) -{ - return (((adc->ADCR & ADC_CR_ADST) != (u32)RESET) ? SET : RESET); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enable the selected ADC channel and configure its sample time. Please -/// use this function if you want to be compatible with older versions -/// of the library. -/// @param adc: select the ADC peripheral. -/// @param channel: the ADC channel to configure. -/// @param sample_time: the ADC Channel n Sample time to configure. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void ADC_RegularChannelConfig(ADC_TypeDef* adc, u32 channel, u8 rank, u32 sample_time) //ADCSAM_TypeDef -{ - - u32 tempchan; - sample_time = sample_time & 0xF; - tempchan = channel; - if(tempchan > 8) { - tempchan = tempchan & 0xF; - tempchan = tempchan - 8; - adc->SMPR2 &= ~(0xF << tempchan); - adc->SMPR2 |= (sample_time << tempchan); - } - else { - adc->SMPR1 &= ~(0xF << tempchan); - adc->SMPR1 |= (sample_time << tempchan); - } - adc->ADCHS &= ~(1 << channel); - adc->ADCHS |= (1 << channel); - - if (channel & ADC_CHSR_CHT) - ADC_TempSensorVrefintCmd(ENABLE); - else if (channel & ADC_CHSR_CHV) - ADC_TempSensorVrefintCmd(ENABLE); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the adc conversion through external trigger. -/// @param adc: select the ADC peripheral. -/// @param state: New state of the selected ADC external trigger. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void ADC_ExternalTrigConvCmd(ADC_TypeDef* adc, FunctionalState state) -{ - (state) ? (adc->ADCR |= ADC_CR_TRGEN) : (adc->ADCR &= ~ADC_CR_TRGEN); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the adc external trigger for injected channels conversion. -/// @param adc: select the ADC peripheral. -/// @param adc_external_trig_source: Configuring the external trigger source -/// for the ADC. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void ADC_ExternalTrigConvConfig(ADC_TypeDef* adc, EXTERTRIG_TypeDef adc_external_trig_source) -{ - adc->ADCR &= ~ADC_CR_TRGSEL; - adc->ADCR |= adc_external_trig_source; -} - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Returns the last adc conversion result data for regular channel. -/// @param adc: select the ADC peripheral. -/// @retval The data conversion value. -//////////////////////////////////////////////////////////////////////////////// -u16 ADC_GetConversionValue(ADC_TypeDef* adc) -{ - return (u16)adc->ADDATA; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Returns the last ADC conversion result data in dual mode. -/// @param None -/// @retval The Data conversion value. -//////////////////////////////////////////////////////////////////////////////// -u32 ADC_GetDualModeConversionValue() -{ - return (*(vu32*)ADC1_BASE); -} - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the analog watchdog. -/// @param adc: to select the ADC peripheral. -/// @param state: New state of the selected ADC analog watchdog. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void ADC_AnalogWatchdogCmd(ADC_TypeDef* adc, FunctionalState state) -{ - (state) ? (adc->ADCFG |= ADC_CFGR_ADWEN) : (adc->ADCFG &= ~ADC_CFGR_ADWEN); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the high and low thresholds of the analog watchdog. -/// @param adc: select the ADC peripheral. -/// @param high_threshold: the ADC analog watchdog High threshold value. -/// This parameter must be a 12bit value. -/// @param low_threshold: the ADC analog watchdog Low threshold value. -/// This parameter must be a 12bit value. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* adc, u16 high_threshold, u16 low_threshold) -{ - u32 tempThreshold; - tempThreshold = high_threshold; - adc->ADCMPR = (tempThreshold << 16) | low_threshold; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the analog watchdog guarded single channel -/// @param adc: select the ADC peripheral. -/// @param channel: the ADC channel to configure for the analog watchdog. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* adc, ADCCHANNEL_TypeDef channel) -{ - adc->ADCR &= ~ADC_CR_CMPCH; - adc->ADCR |= (channel << ADC_CR_CMPCH_Pos); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the temperature sensor and Vrefint channel. -/// @param state: New state of the temperature sensor. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void ADC_TempSensorVrefintCmd(FunctionalState state) -{ - (state) ? (ADC1->ADCFG |= (ADC_CFGR_TEN | ADC_CFGR_VEN)) - : (ADC1->ADCFG &= ~(ADC_CFGR_TEN | ADC_CFGR_VEN)); -} - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the temperature sensor . -/// @param state: New state of the temperature sensor. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void ADC_TempSensorCmd(FunctionalState state) -{ - ADC_TempSensorVrefintCmd(state); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the Vrefint channel. -/// @param state: New state of the Vrefint channel. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void ADC_VrefintCmd(FunctionalState state) -{ - ADC_TempSensorVrefintCmd(state); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the temperature sensor and Vrefint channel. -/// @param chs: temperature sensor bit & Vrefint bit. -/// @param state: New state of the temperature sensor. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void exADC_TempSensorVrefintCmd(u32 chs, FunctionalState state) -{ - if (chs & ADC_CHSR_CHT) { - (state) ? (ADC1->ADCFG |= ADC_CFGR_TEN) - : (ADC1->ADCFG &= ~ADC_CFGR_TEN); - } - else if (chs & ADC_CHSR_CHV) { - (state) ? (ADC1->ADCFG |= ADC_CFGR_VEN) - : (ADC1->ADCFG &= ~ADC_CFGR_VEN); - } - -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Checks whether the specified ADC flag is set or not. -/// @param adc: select the ADC peripheral. -/// @param adc_flag: specifies the flag to check. -/// @retval The New state of adc_flag (SET or RESET). -//////////////////////////////////////////////////////////////////////////////// -FlagStatus ADC_GetFlagStatus(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_flag) -{ - return (adc_flag == ADC_IT_EOC) ? ((adc->ADSTA & ADC_SR_ADIF) ? SET : RESET) : ((adc->ADSTA & ADC_SR_ADWIF) ? SET : RESET); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Clears the adc's pending flags. -/// @param adc: select the ADC peripheral. -/// @param adc_flag: specifies the flag to clear. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void ADC_ClearFlag(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_flag) -{ - (adc_flag == ADC_IT_EOC) ? (adc->ADSTA |= ADC_SR_ADIF) : (adc->ADSTA |= ADC_SR_ADWIF); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Checks whether the specified adc's interrupt has occurred or not. -/// @param adc: select the ADC peripheral. -/// @param adc_interrupt: specifies the ADC interrupt source to check. -/// @retval The new state of adc_interrupt (SET or RESET). -//////////////////////////////////////////////////////////////////////////////// -ITStatus ADC_GetITStatus(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_interrupt) -{ - return (adc_interrupt == ADC_IT_EOC) ? ((adc->ADSTA & ADC_SR_ADIF) ? SET : RESET) : ((adc->ADSTA & ADC_SR_ADWIF) ? SET : RESET); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Clears the adc's interrupt pending bits. -/// @param adc: select the ADC peripheral. -/// @param adc_interrupt: specifies the ADC interrupt pending bit to clear. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void ADC_ClearITPendingBit(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_interrupt) -{ - (adc_interrupt == ADC_IT_EOC) ? (adc->ADSTA |= ADC_SR_ADIF) : (adc->ADSTA |= ADC_SR_ADWIF); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the adc any channels conversion rank and channel. -/// @param adc: select the ADC peripheral. -/// @param rank: rank can be 0x0~0xf for the convert sequence. -/// @param adc_channel: Configuring the target channel to be converted. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void ADC_ANY_CH_Config(ADC_TypeDef* adc, u8 rank, ADCCHANNEL_TypeDef adc_channel) -{ - rank = rank & 0xF; - if(rank < 8) { - adc->CHANY0 &= ~(0x0F << (4 * rank)); - adc->CHANY0 |= (adc_channel << (4 * rank)); - } - else { - adc->CHANY1 &= ~(0x0F << (4 * (rank - 8))); - adc->CHANY1 |= (adc_channel << (4 * (rank - 8))); - } -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the adc any channels conversion Max rank number -/// @param adc: select the ADC peripheral. -/// @param num: Configuring the max rank number for the ADC. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void ADC_ANY_NUM_Config(ADC_TypeDef* adc, u8 num) -{ - if(num > 15) num = 15; //15 ? 16 need to be confirmed - adc->ANYCFG = num; -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the ANY channel converter. -/// @param state: enable or disable the ANY channel converter mode. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void ADC_ANY_Cmd(ADC_TypeDef* adc, FunctionalState state) -{ - (state) ? (adc->ANYCR |= ADC1_CHANY_CR_MDEN) : (adc->ANYCR &= ~ADC1_CHANY_CR_MDEN); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the selected ADC automatic injected group -/// conversion after regular one. -/// @param adc: where x can be 1, 2 or 3 to select the ADC peripheral. -/// @param state: new state of the selected ADC auto injected conversion -/// This parameter can be: ENABLE or DISABLE. -/// @retval None -//////////////////////////////////////////////////////////////////////////////// -void ADC_AutoInjectedConvCmd(ADC_TypeDef* adc, FunctionalState state) -{ - (state) ? (adc->ANYCR |= ADC_ANY_CR_JAUTO) : (adc->ANYCR &= ~ADC_ANY_CR_JAUTO); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the adc external trigger for injected channels conversion. -/// @param adc: where x can be 1, 2 or 3 to select the ADC peripheral. -/// @param ADC_ExtInjTrigSource: specifies the ADC trigger to start injected conversion. - -/// @retval None -//////////////////////////////////////////////////////////////////////////////// -void ADC_ExternalTrigInjectedConvertConfig(ADC_TypeDef* adc, EXTER_INJ_TRIG_TypeDef ADC_ExtInjTrigSource) -{ - u32 tmpreg = 0; - // Get the old register value - tmpreg = adc->ANYCR; - // Clear the old external event selection for injected group - tmpreg &= ADC_ANY_CR_JTRGSEL; - // Set the external event selection for injected group - tmpreg |= ADC_ExtInjTrigSource; - // Store the new register value - adc->ANYCR = tmpreg; -} - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the adc injected channels conversion through -/// external trigger -/// @param adc: where x can be 1, 2 or 3 to select the ADC peripheral. -/// @param state: new state of the selected ADC external trigger start of -/// injected conversion. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None -//////////////////////////////////////////////////////////////////////////////// -void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* adc, FunctionalState state) -{ - (state) ? (adc->ANYCR |= ADC_ANY_CR_JTRGEN) : (adc->ANYCR &= ~ADC_ANY_CR_JTRGEN); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the selected ADC start of the injected -/// channels conversion. -/// @param adc: where x can be 1, 2 or 3 to select the ADC peripheral. -/// @param state: new state of the selected ADC software start injected conversion. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None -//////////////////////////////////////////////////////////////////////////////// -void ADC_InjectedConvCmd(ADC_TypeDef* adc, FunctionalState state) -{ - (state) ? (adc->ANYCR |= ADC_ANY_CR_JCEN) : (adc->ANYCR &= ~ADC_ANY_CR_JCEN); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the selected ADC start of the injected -/// channels conversion. -/// @param adc: where x can be 1, 2 or 3 to select the ADC peripheral. -/// @param NewState: new state of the selected ADC software start injected conversion. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None -//////////////////////////////////////////////////////////////////////////////// -void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* adc, FunctionalState state) -{ - (state) ? (adc->ANYCR |= ADC_ANY_CR_JADST) : (adc->ANYCR &= ~ADC_ANY_CR_JADST); -} - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enable the selected ADC channel and configure its sample time. Please -/// use this function if you want to be compatible with older versions -/// of the library. -/// @param adc: select the ADC peripheral. -/// @param event: the ADC external event to configure. -/// @param sample_time: the ADC Channel n Sample time to configure. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void ADC_InjectedSequencerConfig(ADC_TypeDef* adc, u32 event, u32 sample_time) -{ - adc->ANYCR &= ~(ADC_ANY_CR_JCEN | ADC_ANY_CR_CHANY_MDEN | ADC_ANY_CR_JTRGSEL_EXTI12 \ - | ADC_ANY_CR_JTRGSHIFT_512 | ADC_ANY_CR_JTRGEN); - adc->ANYCR |= (ADC_ANY_CR_JCEN | ADC_ANY_CR_CHANY_MDEN | sample_time | event | ADC_ANY_CR_JTRGEN); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Injection channel length configuration. -/// @param adc: select the ADC peripheral. -/// @param Length: Injection channel length. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* adc, ADC_INJ_SEQ_LEN_TypeDef Length) -{ - adc->JSQR &= ~(0x03 << ADC_JSQR_JL_Pos); - adc->JSQR |= Length << ADC_JSQR_JL_Pos; -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Injection channel configuration. -/// @param adc : select the ADC peripheral. -/// @param off_addr : Injection channel offset address. -/// @param channel: The sampling channel. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void ADC_InjectedSequencerChannelConfig(ADC_TypeDef* adc, ADC_INJ_SEQ_Channel_TypeDef off_addr, ADCCHANNEL_TypeDef channel) -{ - adc->JSQR &= ~(0x1F << (off_addr >> 2) * 5); - adc->JSQR |= (channel << (off_addr >> 2) * 5); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Injection channel converted value. -/// @param adc : select the ADC peripheral. -/// @param off_addr : Injection channel offset address. -/// @retval value. -//////////////////////////////////////////////////////////////////////////////// -u16 ADC_GetInjectedConversionValue(ADC_TypeDef* adc, ADC_INJ_SEQ_Channel_TypeDef off_addr) -{ - u32 value; - value = (*(vu32*)(*(vu32*)&adc + 0xB0 + off_addr)) - (*(vu32*)(*(vu32*)&adc + 0x7C + off_addr)); - - return (u16)value; -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Injection current converted value. -/// @param adc : select the ADC peripheral. -/// @retval value. Returns the last adc conversion result data for injected channel. -//////////////////////////////////////////////////////////////////////////////// -u16 ADC_GetInjectedCurrentConvertedValue(ADC_TypeDef* adc) -{ - return (u16)adc->JDATA; -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Injection channel compensation configuration. -/// @param adc : select the ADC peripheral. -/// @param off_addr : Injection channel. -/// @param value : compensation value. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void ADC_SetInjectedOffset(ADC_TypeDef* adc, ADC_INJ_SEQ_Channel_TypeDef off_addr, u16 value) -{ - *(vu32*)(*(vu32*)&adc + 0x7C + off_addr) = value; -} - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Get channel convertion result. -/// @param adc : select the ADC peripheral. -/// @param channel : Converted channel. -/// @retval The Data conversion value. -//////////////////////////////////////////////////////////////////////////////// -u16 ADC_GetChannelConvertedValue(ADC_TypeDef* adc, ADCCHANNEL_TypeDef channel) -{ - return (u16)(*(vu32*) ((u32)adc + 0x18 + ((u32)channel << 2))); -} - -/// @} - -/// @} - -/// @} - diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_bkp.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_bkp.c deleted file mode 100644 index 323971dd3..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_bkp.c +++ /dev/null @@ -1,231 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_bkp.c -/// @author AE TEAM -/// @brief THIS FILE PROVIDES ALL THE BKP FIRMWARE FUNCTIONS. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#define _HAL_BKP_C_ - -// Files includes -#include "types.h" -#include "hal_pwr.h" -#include "hal_rcc.h" -#include "hal_bkp.h" - - - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup BKP_HAL -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup BKP_Exported_Functions -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Deinitializes the BKP peripheral registers to their default reset -/// values. -/// @param None. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void BKP_DeInit(void) -{ - RCC_BackupResetCmd(ENABLE); - RCC_BackupResetCmd(DISABLE); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the Tamper Pin active level. -/// @param tamper_pin_level: specifies the Tamper Pin active level. -/// This parameter can be one of the following values: -/// @arg BKP_TamperPinLevel_High: Tamper pin active on high level -/// @arg BKP_TamperPinLevel_Low: Tamper pin active on low level -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void BKP_TamperPinLevelConfig(BKPTPAL_Typedef tamper_pin_level) -{ - BKP->CR = tamper_pin_level; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the Tamper Pin activation. -/// @param state: new state of the Tamper Pin activation. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void BKP_TamperPinCmd(FunctionalState state) -{ - (state) ? SET_BIT(BKP->CR, BKP_CR_TPE) : CLEAR_BIT(BKP->CR, BKP_CR_TPE); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the Tamper Pin Interrupt. -/// @param state: new state of the Tamper Pin Interrupt. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void BKP_ITConfig(FunctionalState state) -{ - (state) ? SET_BIT(BKP->CSR, BKP_CSR_TPIE) : CLEAR_BIT(BKP->CSR, BKP_CSR_TPIE); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Select the RTC output source to output on the Tamper pin. -/// @param rtc_output_source: specifies the RTC output source. -/// This parameter can be one of the following values: -/// @arg BKP_RTCOutputSource_None: no RTC output on the Tamper pin. -/// @arg BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency -/// divided by 64 on the Tamper pin. -/// @arg BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on -/// the Tamper pin. -/// @arg BKP_RTCOutputSource_Second: output the RTC Second pulse signal on -/// the Tamper pin. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void BKP_RTCOutputConfig(BKPRTCOUTPUTSRC_Typedef rtc_output_source) -{ - MODIFY_REG(BKP->RTCCR, BKP_RTCCR_CCO | BKP_RTCCR_ASOE | BKP_RTCCR_ASOS, rtc_output_source); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Sets RTC Clock Calibration value. -/// @param calibration_value: specifies the RTC Clock Calibration value. -/// This parameter must be a number between 0 and 0x7F. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void BKP_SetRTCCalibrationValue(u8 calibration_value) -{ - MODIFY_REG(BKP->RTCCR, BKP_RTCCR_CAL, calibration_value); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Checks whether the Tamper Pin Event flag is set or not. -/// @param None. -/// @retval State: The new state of the Tamper Pin Event flag (SET or RESET). -//////////////////////////////////////////////////////////////////////////////// -FlagStatus BKP_GetFlagStatus(void) -{ - return ((BKP->CSR & BKP_CSR_TEF) ? SET : RESET); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Clears Tamper Pin Event pending flag. -/// @param None. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void BKP_ClearFlag(void) -{ - SET_BIT(BKP->CSR, BKP_CSR_CTE); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Checks whether the Tamper Pin Interrupt has occurred or not. -/// @param None. -/// @retval State: The new state of the Tamper Pin Interrupt (SET or RESET). -//////////////////////////////////////////////////////////////////////////////// -ITStatus BKP_GetITStatus(void) -{ - return ((BKP->CSR & BKP_CSR_TIF) ? SET : RESET); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Clears Tamper Pin Interrupt pending bit. -/// @param None. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void BKP_ClearITPendingBit(void) -{ - SET_BIT(BKP->CSR, BKP_CSR_CTI); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Writes user data to the specified data Backup Register. -/// @param bkp_dr: specifies the data Backup Register. -/// This parameter can be BKP_DRx where x:[1, 10] -/// @param data: data to write -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void BKP_WriteBackupRegister(BKPDR_Typedef bkp_dr, u16 data) -{ - *(vu16*)(BKP_BASE + bkp_dr) = data; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Reads data from the specified data Backup Register. -/// @param bkp_dr: specifies the data Backup Register. -/// This parameter can be BKP_DRx where x:[1, 10] -/// @retval data: The content of the specified data Backup Register -//////////////////////////////////////////////////////////////////////////////// -u16 BKP_ReadBackupRegister(BKPDR_Typedef bkp_dr) -{ - return (*(vu16*)(BKP_BASE + bkp_dr)); -} -//////////////////////////////////////////////////////////////////////////////// -// Extended function interface -//////////////////////////////////////////////////////////////////////////////// -/// @brief Initializes the BKP peripheral, enable access to the backup -/// registers. -/// @param None. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void exBKP_Init(void) -{ - RCC_APB1PeriphClockCmd(RCC_APB1ENR_PWR, ENABLE); - //COMMON_EnableIpClock(emCLOCK_PWR); - RCC_APB1PeriphClockCmd(RCC_APB1ENR_BKP, ENABLE); - //COMMON_EnableIpClock(emCLOCK_BKP); - - RCC->BDCR |= RCC_BDCR_DBP; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Writes user data to the specified data Backup Register immediately. -/// @param bkp_dr: specifies the data Backup Register. -/// This parameter can be BKP_DRx where x:[1, 10] -/// @param data: data to write -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void exBKP_ImmWrite(BKPDR_Typedef bkp_dr, u16 dat) -{ - RCC->BDCR |= RCC_BDCR_DBP; - *(vu16*)(BKP_BASE + bkp_dr) = dat; - RCC->BDCR &= ~RCC_BDCR_DBP; - -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Reads data from the specified data Backup Register immediately. -/// @param bkp_dr: specifies the data Backup Register. -/// This parameter can be BKP_DRx where x:[1, 10] -/// @retval data: The content of the specified data Backup Register -//////////////////////////////////////////////////////////////////////////////// -u16 exBKP_ImmRead(BKPDR_Typedef bkp_dr) -{ - u16 dat; - RCC->BDCR |= RCC_BDCR_DBP; - dat = (*(vu16*)(BKP_BASE + bkp_dr)); - RCC->BDCR &= ~RCC_BDCR_DBP; - return dat; -} - -/// @} - -/// @} - -/// @} diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_can.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_can.c deleted file mode 100644 index 9dd85df29..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_can.c +++ /dev/null @@ -1,696 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_can.c -/// @author AE TEAM -/// @brief THIS FILE PROVIDES ALL THE CAN FIRMWARE FUNCTIONS. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#define __HAL_CAN_C - -// Files includes -#include "hal_can.h" -#include "hal_rcc.h" - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup CAN_HAL -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup CAN_Exported_Functions -/// @{ - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Deinitializes the CAN peripheral registers to their default reset -/// values. -/// @param can: select the CAN peripheral. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void CAN_DeInit(CAN_TypeDef* can) -{ - exRCC_APB1PeriphReset(RCC_APB1ENR_CAN); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Initializes the CAN peripheral according to the specified -/// parameters in the CAN_InitStruct. -/// @param can: select the CAN peripheral. -/// @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that -/// contains the configuration information for the CAN peripheral. -/// @retval Constant indicates initialization succeed which will be -/// CANINITFAILED or CANINITOK. -//////////////////////////////////////////////////////////////////////////////// -u8 CAN_Init(CAN_TypeDef* can, CAN_Basic_InitTypeDef* init_struct) -{ - u8 InitStatus = CANINITFAILED; - - can->BTR0 = ((u32)(init_struct->SJW) << 6) | ((u32)(init_struct->BRP)); - can->BTR1 = ((u32)(init_struct->SAM) << 7) | ((u32)(init_struct->TESG2) << 4) | ((u32)(init_struct->TESG1)); - - if (init_struct->GTS == ENABLE) { - can->CMR |= (u32)CAN_SleepMode; - InitStatus = CANINITFAILED; - } - else { - can->CMR &= ~(u32)CAN_SleepMode; - InitStatus = CANINITOK; - } - - (init_struct->GTS == ENABLE) ? (can->CMR |= (u32)CAN_SleepMode) : (can->CMR &= ~(u32)CAN_SleepMode); - - can->CDR |= - ((init_struct->CBP) << 6) | ((init_struct->RXINTEN) << 5) | ((init_struct->CLOSE_OPEN_CLK) << 3) | (init_struct->CDCLK); - - return InitStatus; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the CAN_Basic reception filter according to the specified -/// parameters in the basic_filter_init_struct. -/// @param basic_filter_init_struct: pointer to a CAN_Basic_FilterInitTypeDef -/// structure that contains the configuration information. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void CAN_FilterInit(CAN_Basic_FilterInitTypeDef* basic_filter_init_struct) -{ - // Filter Mode - CAN1->ACR = basic_filter_init_struct->CAN_FilterId; - CAN1->AMR = basic_filter_init_struct->CAN_FilterMaskId; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Fills each init_struct member with its default value. -/// @param init_struct : pointer to a CAN_Basic_InitTypeDef structure which will be initialized. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void CAN_StructInit(CAN_Basic_InitTypeDef* init_struct) -{ - // Reset CAN_Basic init structure parameters values - - // initialize the BRP member(where can be set with (0..63)) - init_struct->BRP = 0x0; - // initialize the SJW member(where can be set with (0..3)) - init_struct->SJW = 0x0; - // Initialize the TESG1 member(where can be set with (0..15)) - init_struct->TESG1 = 0x0; - // Initialize the TESG2 member(where can be set with(0..7)) - init_struct->TESG2 = 0x0; - // Initialize the SAM member(where can be set (SET or RESET)) - init_struct->SAM = RESET; - // Initialize the GTS member to Sleep Mode(where can be set (ENABLE or - // DISABLE)) - init_struct->GTS = DISABLE; - // Initialize the external pin CLKOUT frequence - init_struct->CDCLK = 0x0; - // Initialize the external clk is open or close - init_struct->CLOSE_OPEN_CLK = 0x0; - // Initialize the TX1 pin work as rx interrupt output - init_struct->RXINTEN = 0x0; - // Initialize the CBP of CDR register - init_struct->CBP = 0x0; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the specified CAN interrupts. -/// @param can: select the CAN peripheral. -/// @param it: specifies the CAN interrupt sources to be enabled or -/// disabled. -/// This parameter can be: CAN_IT_OIE, CAN_IT_EIE, CAN_IT_TIE, -/// CAN_IT_RIE. -/// @param state: new state of the CAN interrupts. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void CAN_ITConfig(CAN_TypeDef* can, u32 it, FunctionalState state) -{ - (state) ? (can->CR |= it) : (can->CR &= ~it); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Initiates and transmits a CAN frame message. -/// @param can:select the CAN peripheral. -/// @param TxMessage: pointer to a structure which contains CAN Id, CAN DLC and -/// CAN data. -/// @retval CANTXOK if the CAN driver transmits the message -//////////////////////////////////////////////////////////////////////////////// -u8 CAN_Transmit(CAN_TypeDef* can, CanBasicTxMsg* basic_transmit_message) -{ - can->TXID0 = (basic_transmit_message->IDH); - can->TXID1 = (basic_transmit_message->IDL << 5) | (basic_transmit_message->RTR << 4) | (basic_transmit_message->DLC); - if ((FunctionalState)(basic_transmit_message->RTR) != ENABLE) { - can->TXDR0 = basic_transmit_message->Data[0]; - can->TXDR1 = basic_transmit_message->Data[1]; - can->TXDR2 = basic_transmit_message->Data[2]; - can->TXDR3 = basic_transmit_message->Data[3]; - can->TXDR4 = basic_transmit_message->Data[4]; - can->TXDR5 = basic_transmit_message->Data[5]; - can->TXDR6 = basic_transmit_message->Data[6]; - can->TXDR7 = basic_transmit_message->Data[7]; - } - - can->CMR = CAN_CMR_TR; - - return (can->SR & 0x01); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Cancels a transmit request. -/// @param can: select the CAN peripheral. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void CAN_CancelTransmit(CAN_TypeDef* can) -{ - // abort transmission - can->CMR = CAN_AT; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Releases the specified receive FIFO. -/// @param can: select the CAN peripheral. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void CAN_FIFORelease(CAN_TypeDef* can) -{ - // Release FIFO - can->CMR |= (u32)CAN_RRB; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Receives a correct CAN frame. -/// @param can: select the CAN peripheral. -/// @param RxMessage: pointer to a structure receive frame which contains CAN -/// Id,CAN DLC, CAN data and FMI number. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void CAN_Receive(CAN_TypeDef* can, CanBasicRxMsg* basic_receive_message) -{ - u16 tempid; - - basic_receive_message->RTR = (u8)((can->RXID1) >> 4) & 0x1; - basic_receive_message->DLC = (u8)((can->RXID1) & 0xf); - tempid = (u16)(((can->RXID1) & 0xe0) >> 5); - tempid |= (u16)(can->RXID0 << 3); - basic_receive_message->ID = tempid; - basic_receive_message->Data[0] = CAN1->RXDR0; - basic_receive_message->Data[1] = CAN1->RXDR1; - basic_receive_message->Data[2] = CAN1->RXDR2; - basic_receive_message->Data[3] = CAN1->RXDR3; - basic_receive_message->Data[4] = CAN1->RXDR4; - basic_receive_message->Data[5] = CAN1->RXDR5; - basic_receive_message->Data[6] = CAN1->RXDR6; - basic_receive_message->Data[7] = CAN1->RXDR7; - CAN_FIFORelease(can); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Select the Sleep mode or not in Basic workmode -/// @param state to go into the Sleep mode or go out -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -u8 CAN_Sleep(CAN_TypeDef* can) -{ - can->CMR |= CAN_SleepMode; - // At this step, sleep mode status - return (u8)((can->CMR & 0x10) == CAN_SleepMode) ? CANSLEEPOK : CANSLEEPFAILED; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Wakes the CAN up. -/// @param can: where x can be 1 to select the CAN peripheral. -/// @retval CANWAKEUPOK if sleep mode left, CANWAKEUPFAILED in an other case. -//////////////////////////////////////////////////////////////////////////////// -u8 CAN_WakeUp(CAN_TypeDef* can) -{ - // Wake up request - can->CMR &= ~CAN_SleepMode; - return (u8)((can->CMR & 0x01) == 0) ? CANWAKEUPOK : CANWAKEUPFAILED; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Checks whether the specified CAN flag is set or not. -/// @param can: select the CAN peripheral. -/// @param flag: specifies the flag to check. -/// This parameter can be one of the following values: -/// @arg CAN_STATUS_RBS: Receive buffer status -/// @arg CAN_STATUS_DOS: Data overflow status -/// @arg CAN_STATUS_TBS: Transmit buffer status -/// @arg CAN_STATUS_TCS: Transmit complete status -/// @arg CAN_STATUS_RS: Receiving status -/// @arg CAN_STATUS_TS: Transmiting status -/// @arg CAN_STATUS_ES: Error status -/// @arg CAN_STATUS_BS: bus status, close or open -/// @retval The new state of CAN_FLAG (SET or RESET). -//////////////////////////////////////////////////////////////////////////////// -FlagStatus CAN_GetFlagStatus(CAN_TypeDef* can, u32 flag) -{ - return (FlagStatus)(((can->SR & flag) == flag) ? SET : RESET); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Checks whether the specified CAN interrupt has occurred or not. -/// @param can: where x can be 1 to select the CAN peripheral. -/// @param it: specifies the CAN interrupt source to check. -/// This parameter can be one of the following values: -/// @arg CAN_IT_RI: Receive FIFO not empty Interrupt -/// @arg CAN_IT_TI: Transmit Interrupt -/// @arg CAN_IT_EI: ERROR Interrupt -/// @arg CAN_IT_DOI: Data voerflow Interrupt -/// @arg CAN_IT_WUI: Wakeup Interrupt -/// @arg CAN_IT_ALL: use it can enble all Interrupt -/// @retval The current state of it (SET or RESET). -//////////////////////////////////////////////////////////////////////////////// -ITStatus CAN_GetITStatus(CAN_TypeDef* can, u32 it) -{ - return (ITStatus)((can->IR & it) != it) ? RESET : SET; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Select the can work as peli mode or basic mode -/// @param can: where x can be 1 or 2 to to select the CAN peripheral. -/// @param CAN_MODE: specifies the work mode:CAN_BASICMode,CAN_PELIMode -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void CAN_Mode_Cmd(CAN_TypeDef* can, u32 mode) -{ - can->CDR |= mode; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Select the Reset mode or not -/// @param can: where x can be 1 or 2 to to select the CAN peripheral. -/// @param state to go into the Reset mode or go out -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void CAN_ResetMode_Cmd(CAN_TypeDef* can, FunctionalState state) -{ - (state == ENABLE) ? (can->CR |= CAN_ResetMode) : (can->CR &= ~CAN_ResetMode); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Clear the data overflow. -/// @param can: where x can be 1 or 2 to to select the CAN peripheral. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void CAN_ClearDataOverflow(CAN_TypeDef* can) -{ - can->CMR |= (u32)CAN_CDO; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Clears the CAN's IT pending. -/// @param can: where x can be 1 or 2 to to select the CAN peripheral. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void CAN_ClearITPendingBit(CAN_TypeDef* can) -{ - u32 temp = 0; - temp = temp; - temp = can->IR; // read this register clear all interrupt -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Select the Sleep mode or not in Peli workmode -/// @param state to go into the Sleep mode or go out -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void CAN_Peli_SleepMode_Cmd(FunctionalState state) -{ - (state == ENABLE) ? (CAN1_PELI->MOD |= CAN_SleepMode) : (CAN1_PELI->MOD &= ~CAN_SleepMode); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Fills each CAN1_PELI_InitStruct member with its default value. -/// @param init_struct : pointer to a CAN_Peli_InitTypeDef structure -/// which will be initialized. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void CAN_Peli_StructInit(CAN_Peli_InitTypeDef* init_struct) -{ - //--------------- Reset CAN_Peli init structure parameters values - //--------------- - init_struct->BRP = 0x0; // initialize the BRP member(where can be set with (0..63)) - init_struct->SJW = 0x0; // initialize the SJW member(where can be set with (0..3)) - init_struct->TESG1 = 0x0; // Initialize the TESG1 member(where can be set with (0..15)) - init_struct->TESG2 = 0x0; // Initialize the TESG2 member(where can be set with(0..7)) - init_struct->SAM = RESET; // Initialize the SAM member(where can be set (SET or RESET)) - init_struct->LOM = DISABLE; // Initialize the LOM member - init_struct->STM = DISABLE; // Initialize the STM member - init_struct->SM = DISABLE; // Initialize the SM member - init_struct->SRR = DISABLE; - init_struct->EWLR = 0x96; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Initializes the CAN_Peli peripheral according to the specified -/// parameters in the init_struct. -/// @param init_struct: pointer to a CAN_Peli_InitTypeDef structure that -/// contains the configuration information for the CAN peripheral in the peli workmode. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void CAN_Peli_Init(CAN_Peli_InitTypeDef* init_struct) -{ - CAN1_PELI->BTR0 = ((u32)init_struct->SJW << 6) | ((u32)init_struct->BRP); - CAN1_PELI->BTR1 = ((u32)init_struct->SAM << 7) | ((u32)init_struct->TESG2 << 4) | ((u32)init_struct->TESG1); - if (init_struct->LOM == ENABLE) - CAN1_PELI->MOD |= (u32)CAN_ListenOnlyMode; - else - CAN1_PELI->MOD &= ~(u32)CAN_ListenOnlyMode; - if (init_struct->STM == ENABLE) - CAN1_PELI->MOD |= (u32)CAN_SeftTestMode; - else - CAN1_PELI->MOD &= ~(u32)CAN_SeftTestMode; - if (init_struct->SM == ENABLE) - CAN1_PELI->MOD |= (u32)CAN_SleepMode; - else - CAN1_PELI->MOD &= ~(u32)CAN_SleepMode; - CAN1_PELI->EWLR = (u32)init_struct->EWLR; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the CAN_Peli reception filter according to the specified -/// parameters in the peli_filter_init_struct. -/// @param peli_filter_init_struct: pointer to a CAN_Peli_FilterInitTypeDef -/// structure that contains the configuration information. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void CAN_Peli_FilterInit(CAN_Peli_FilterInitTypeDef* peli_filter_init_struct) -{ - (peli_filter_init_struct->AFM == CAN_FilterMode_Singal) ? (CAN1_PELI->MOD |= (u32)CAN_FilterMode_Singal) - : (CAN1_PELI->MOD &= (u32)CAN_FilterMode_Double); - - CAN1_PELI->FF = peli_filter_init_struct->CAN_FilterId0; - CAN1_PELI->ID0 = peli_filter_init_struct->CAN_FilterId1; - CAN1_PELI->ID1 = peli_filter_init_struct->CAN_FilterId2; - CAN1_PELI->DATA0 = peli_filter_init_struct->CAN_FilterId3; - - CAN1_PELI->DATA1 = peli_filter_init_struct->CAN_FilterMaskId0; - CAN1_PELI->DATA2 = peli_filter_init_struct->CAN_FilterMaskId1; - CAN1_PELI->DATA3 = peli_filter_init_struct->CAN_FilterMaskId2; - CAN1_PELI->DATA4 = peli_filter_init_struct->CAN_FilterMaskId3; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Fills each peli_filter_init_struct member with its default value. -/// @param peli_filter_init_struct: pointer to a CAN_InitTypeDef structure -/// which ill be initialized. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void CAN_Peli_FilterStructInit(CAN_Peli_FilterInitTypeDef* peli_filter_init_struct) -{ - peli_filter_init_struct->CAN_FilterId0 = 0; - peli_filter_init_struct->CAN_FilterId1 = 0; - peli_filter_init_struct->CAN_FilterId2 = 0; - peli_filter_init_struct->CAN_FilterId3 = 0; - - peli_filter_init_struct->CAN_FilterMaskId0 = 0; - peli_filter_init_struct->CAN_FilterMaskId1 = 0; - peli_filter_init_struct->CAN_FilterMaskId2 = 0; - peli_filter_init_struct->CAN_FilterMaskId3 = 0; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Initiates and transmits a CAN frame message. -/// @param TxMessage: pointer to a structure which contains CAN Id, CAN DLC and -/// CAN data. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void CAN_Peli_Transmit(CanPeliTxMsg* peli_transmit_message) -{ - CAN1_PELI->FF = (peli_transmit_message->FF << 7) | (peli_transmit_message->RTR << 6) | (peli_transmit_message->DLC); - if (((FunctionalState)peli_transmit_message->FF) != ENABLE) { - CAN1_PELI->ID0 = (peli_transmit_message->IDHH); - - CAN1_PELI->ID1 = (peli_transmit_message->IDHL & 0xE0); - if ((FunctionalState)(peli_transmit_message->RTR) != ENABLE) { - CAN1_PELI->DATA0 = peli_transmit_message->Data[0]; - CAN1_PELI->DATA1 = peli_transmit_message->Data[1]; - CAN1_PELI->DATA2 = peli_transmit_message->Data[2]; - CAN1_PELI->DATA3 = peli_transmit_message->Data[3]; - CAN1_PELI->DATA4 = peli_transmit_message->Data[4]; - CAN1_PELI->DATA5 = peli_transmit_message->Data[5]; - CAN1_PELI->DATA6 = peli_transmit_message->Data[6]; - CAN1_PELI->DATA7 = peli_transmit_message->Data[7]; - } - } - else { - CAN1_PELI->ID0 = peli_transmit_message->IDHH; - CAN1_PELI->ID1 = peli_transmit_message->IDHL; - CAN1_PELI->DATA0 = peli_transmit_message->IDLH; - CAN1_PELI->DATA1 = peli_transmit_message->IDLL; - if ((FunctionalState)(peli_transmit_message->RTR) != ENABLE) { - CAN1_PELI->DATA2 = peli_transmit_message->Data[0]; - CAN1_PELI->DATA3 = peli_transmit_message->Data[1]; - CAN1_PELI->DATA4 = peli_transmit_message->Data[2]; - CAN1_PELI->DATA5 = peli_transmit_message->Data[3]; - CAN1_PELI->DATA6 = peli_transmit_message->Data[4]; - CAN1_PELI->DATA7 = peli_transmit_message->Data[5]; - CAN1_PELI->DATA8 = peli_transmit_message->Data[6]; - CAN1_PELI->DATA9 = peli_transmit_message->Data[7]; - } - } - - (CAN1_PELI->MOD & CAN_MOD_STM) ? (CAN1->CMR = CAN_CMR_GTS | CAN_CMR_AT) : (CAN1->CMR = CAN_CMR_TR | CAN_CMR_AT); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Initiates and transmits a CAN frame message. -/// @param TxMessage: pointer to a structure which contains CAN Id, CAN DLC and -/// CAN data. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void CAN_Peli_TransmitRepeat(CanPeliTxMsg* peli_transmit_message) -{ - CAN1_PELI->FF = (peli_transmit_message->FF << 7) | (peli_transmit_message->RTR << 6) | (peli_transmit_message->DLC); - if (((FunctionalState)peli_transmit_message->FF) != ENABLE) { - CAN1_PELI->ID0 = (peli_transmit_message->IDHH); - - CAN1_PELI->ID1 = (peli_transmit_message->IDHL & 0xE0); - if ((FunctionalState)(peli_transmit_message->RTR) != ENABLE) { - CAN1_PELI->DATA0 = peli_transmit_message->Data[0]; - CAN1_PELI->DATA1 = peli_transmit_message->Data[1]; - CAN1_PELI->DATA2 = peli_transmit_message->Data[2]; - CAN1_PELI->DATA3 = peli_transmit_message->Data[3]; - CAN1_PELI->DATA4 = peli_transmit_message->Data[4]; - CAN1_PELI->DATA5 = peli_transmit_message->Data[5]; - CAN1_PELI->DATA6 = peli_transmit_message->Data[6]; - CAN1_PELI->DATA7 = peli_transmit_message->Data[7]; - } - } - else { - CAN1_PELI->ID0 = peli_transmit_message->IDHH; - CAN1_PELI->ID1 = peli_transmit_message->IDHL; - CAN1_PELI->DATA0 = peli_transmit_message->IDLH; - CAN1_PELI->DATA1 = peli_transmit_message->IDLL; - if ((FunctionalState)(peli_transmit_message->RTR) != ENABLE) { - CAN1_PELI->DATA2 = peli_transmit_message->Data[0]; - CAN1_PELI->DATA3 = peli_transmit_message->Data[1]; - CAN1_PELI->DATA4 = peli_transmit_message->Data[2]; - CAN1_PELI->DATA5 = peli_transmit_message->Data[3]; - CAN1_PELI->DATA6 = peli_transmit_message->Data[4]; - CAN1_PELI->DATA7 = peli_transmit_message->Data[5]; - CAN1_PELI->DATA8 = peli_transmit_message->Data[6]; - CAN1_PELI->DATA9 = peli_transmit_message->Data[7]; - } - } - - (CAN1_PELI->MOD & CAN_MOD_STM) ? (CAN1->CMR = CAN_CMR_GTS | CAN_CMR_AT) : (CAN1->CMR = CAN_CMR_TR); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Receives a correct CAN frame. -/// @param RxMessage: pointer to a structure receive frame which contains CAN -/// Id,CAN DLC, CAN data and FMI number. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void CAN_Peli_Receive(CanPeliRxMsg* peli_receive_message) -{ - u32 tempid; - peli_receive_message->FF = (CAN1_PELI->FF) >> 7; - peli_receive_message->RTR = ((CAN1_PELI->FF) >> 6) & 0x1; - peli_receive_message->DLC = (CAN1_PELI->FF) & 0xf; - - if (((FunctionalState)peli_receive_message->FF) != ENABLE) { - tempid = (u32)(CAN1_PELI->ID1 >> 5); - tempid |= (u32)(CAN1_PELI->ID0 << 3); - peli_receive_message->ID = tempid; - peli_receive_message->Data[0] = CAN1_PELI->DATA0; - peli_receive_message->Data[1] = CAN1_PELI->DATA1; - peli_receive_message->Data[2] = CAN1_PELI->DATA2; - peli_receive_message->Data[3] = CAN1_PELI->DATA3; - peli_receive_message->Data[4] = CAN1_PELI->DATA4; - peli_receive_message->Data[5] = CAN1_PELI->DATA5; - peli_receive_message->Data[6] = CAN1_PELI->DATA6; - peli_receive_message->Data[7] = CAN1_PELI->DATA7; - } - else { - tempid = (u32)((CAN1_PELI->DATA1 & 0xf8) >> 3); - tempid |= (u32)(CAN1_PELI->DATA0 << 5); - tempid |= (u32)(CAN1_PELI->ID1 << 13); - tempid |= (u32)(CAN1_PELI->ID0 << 21); - peli_receive_message->ID = tempid; - peli_receive_message->Data[0] = CAN1_PELI->DATA2; - peli_receive_message->Data[1] = CAN1_PELI->DATA3; - peli_receive_message->Data[2] = CAN1_PELI->DATA4; - peli_receive_message->Data[3] = CAN1_PELI->DATA5; - peli_receive_message->Data[4] = CAN1_PELI->DATA6; - peli_receive_message->Data[5] = CAN1_PELI->DATA7; - peli_receive_message->Data[6] = CAN1_PELI->DATA8; - peli_receive_message->Data[7] = CAN1_PELI->DATA9; - } - CAN_FIFORelease(CAN1); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Get available current informatoin in receive FIFO only in Peli -/// workmode. -/// @retval The value in reg RMC -//////////////////////////////////////////////////////////////////////////////// -u32 CAN_Peli_GetRxFIFOInfo(void) -{ - return CAN1_PELI->RMC; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Returns the CAN's last error code (LEC). -/// @retval Error code: -/// - CAN_ERRORCODE_NoErr: No Error -/// - CAN_ERRORCODE_StuffErr: Stuff Error -/// - CAN_ERRORCODE_FormErr: Form Error -/// - CAN_ERRORCODE_ACKErr : Acknowledgment Error -/// - CAN_ERRORCODE_BitRecessiveErr: Bit Recessive Error -/// - CAN_ERRORCODE_BitDominantErr: Bit Dominant Error -/// - CAN_ERRORCODE_CRCErr: CRC Error -/// - CAN_ERRORCODE_SoftwareSetErr: Software Set Error -//////////////////////////////////////////////////////////////////////////////// -u8 CAN_Peli_GetLastErrorCode(void) -{ - // Return the error code - return (u8)CAN1_PELI->ECC; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Returns the CAN Receive Error Counter (REC). -/// @note In case of an error during reception, this counter is incremented -/// by 1 or by 8 depending on the error condition as defined by the CAN -/// standard. After every successful reception, the counter is -/// decremented by 1 or reset to 120 if its value was higher than 128. -/// When the counter value exceeds 127, the CAN controller enters the -/// error passive state. -/// @retval CAN Receive Error Counter. -//////////////////////////////////////////////////////////////////////////////// -u8 CAN_Peli_GetReceiveErrorCounter(void) -{ - // Return the Receive Error Counter - return (u8)(CAN1_PELI->RXERR); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Returns the LSB of the 9-bit can Transmit Error Counter(TEC). -/// @retval LSB of the 8-bit CAN Transmit Error Counter. -//////////////////////////////////////////////////////////////////////////////// -u8 CAN_Peli_GetLSBTransmitErrorCounter(void) -{ - // Return the LSB of the 8-bit CAN Transmit Error Counter(TEC) - return (u8)(CAN1_PELI->TXERR); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the specified CAN interrupts in peli workmode. -/// @param it: specifies the CAN interrupt sources to be enabled or -/// disabled. -/// This parameter can be: -/// @arg CAN_IT_RI: Receive FIFO not empty Interrupt -/// @arg CAN_IT_TI: Transmit Interrupt -/// @arg CAN_IT_EI: ERROR Interrupt -/// @arg CAN_IT_DOI: Data voerflow Interrupt -/// @arg CAN_IT_WUI: Wakeup Interrupt -/// @arg CAN_IT_EPI(only Peli): passive error Interrupt -/// @arg CAN_IT_ALI(only Peli): arbiter lose Interrupt -/// @arg CAN_IT_BEI(only Peli): bus error Interrupt -/// @arg CAN_IT_ALL: use it can enble all Interrupt -/// @param state: new state of the CAN interrupts. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void CAN_Peli_ITConfig(u32 it, FunctionalState state) -{ - (state) ? (CAN1_PELI->IER |= it) : (CAN1_PELI->IER &= ~it); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Checks whether the specified CAN interrupt has occurred or not. -/// @param it: specifies the CAN interrupt source to check. -/// This parameter can be one of the following values: -/// @arg CAN_IT_RI: Receive FIFO not empty Interrupt -/// @arg CAN_IT_TI: Transmit Interrupt -/// @arg CAN_IT_EI: ERROR Interrupt -/// @arg CAN_IT_DOI: Data voerflow Interrupt -/// @arg CAN_IT_WUI: Wakeup Interrupt -/// @arg CAN_IT_EPI(only Peli): passive error Interrupt -/// @arg CAN_IT_ALI(only Peli): arbiter lose Interrupt -/// @arg CAN_IT_BEI(only Peli): bus error Interrupt -/// @arg CAN_IT_ALL: use it can enble all Interrupt -/// @retval The current state of it (SET or RESET). -//////////////////////////////////////////////////////////////////////////////// -ITStatus CAN_Peli_GetITStatus(u32 it) -{ - return (ITStatus)(((CAN1_PELI->IR & it) != it) ? RESET : SET); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Config CAN_Peli_InitTypeDef baud parameter. -/// @param CAN_Peli_InitTypeDef: CAN struct. -/// @param src_clk: CAN module clock. -/// @param baud: specified baud. -/// @retval The current state of it (SET or RESET). -//////////////////////////////////////////////////////////////////////////////// -void CAN_AutoCfg_BaudParam(CAN_Peli_InitTypeDef* init_struct, u32 src_clk, u32 baud) -{ - u32 i, value = baud, record = 1; - u32 remain = 0, sumPrescaler = 0; - while ((baud == 0) || (src_clk == 0)) - ; - sumPrescaler = src_clk / baud; - sumPrescaler = sumPrescaler / 2; - for (i = 25; i > 3; i--) { - remain = sumPrescaler - ((sumPrescaler / i) * i); - if (remain == 0) { - record = i; - break; - } - else { - if (remain < value) { - value = remain; - record = i; - } - } - } - init_struct->SJW = 0; - init_struct->BRP = (sumPrescaler / record) - 1; - init_struct->TESG2 = (record - 3) / 3; - init_struct->TESG1 = (record - 3) - init_struct->TESG2; -} - -/// @} - -/// @} - -/// @} - - - diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_comp.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_comp.c deleted file mode 100644 index b55558263..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_comp.c +++ /dev/null @@ -1,226 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_comp.c -/// @author AE TEAM -/// @brief THIS FILE PROVIDES ALL THE COMP FIRMWARE FUNCTIONS. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

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-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#define _HAL_COMP_C_ - -// Files includes -#include "hal_comp.h" - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup COMP_HAL -/// @{ - - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup COMP_Exported_Functions -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Deinitializes COMP peripheral registers to their default reset -/// values. -/// @param selection: the selected comparator. -/// select the COMP peripheral. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void COMP_DeInit(COMP_Selection_TypeDef selection) -{ - *(vu32*)(COMP_BASE + selection) = 0; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Initializes the COMP peripheral according to the specified -/// @param selection: the selected comparator. -/// select the COMP peripheral. -/// @param init_struct: pointer to an COMP_InitTypeDef structure that -/// contains the configuration information for the specified COMP -/// peripheral. -/// - COMP_InvertingInput specifies the inverting input of COMP -/// - COMP_NonInvertingInput specifies the non inverting input of COMP -/// - COMP_Output connect COMP output to selected timer -/// input (Input capture / Output Compare Reference Clear / Break -/// Input) -/// - COMP_BlankingSrce specifies the blanking source of COMP -/// - COMP_OutputPol select output polarity -/// - COMP_Hysteresis configures COMP hysteresis value -/// - COMP_Mode configures COMP power mode -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void COMP_Init(COMP_Selection_TypeDef selection, COMP_InitTypeDef* init_struct) -{ - *(vu32*)(COMP_BASE + selection) = init_struct->Invert | - init_struct->NonInvert | - init_struct->Output | - init_struct->OutputPol | - init_struct->BlankingSrce | - init_struct->Hysteresis | - init_struct->Mode | - init_struct->OFLT; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Fills each init_struct member with its default value. -/// @param init_struct: pointer to an COMP_InitTypeDef structure which will -/// be initialized. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void COMP_StructInit(COMP_InitTypeDef* init_struct) -{ - - init_struct->Invert = COMP_InvertingInput_IO1; - init_struct->NonInvert = COMP_NonInvertingInput_IO1; - init_struct->Output = COMP_Output_None; - init_struct->BlankingSrce = COMP_BlankingSrce_None; - init_struct->OutputPol = COMP_NonInverted; - init_struct->Hysteresis = COMP_Hysteresis_No; - init_struct->Mode = COMP_Mode_UltraLowPower; - init_struct->OFLT = COMP_Filter_4_Period; ///< to adjust the speed/consumption. -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enable or disable the COMP peripheral. -/// @param selection: the selected comparator. -/// select the COMP peripheral. -/// @param NewState: new state of the COMP peripheral. -/// This parameter can be: ENABLE or DISABLE. -/// When enabled, the comparator compares the non inverting input with -/// the inverting input and the comparison result is available on -/// comparator output. -/// When disabled, the comparator doesn't perform comparison and the -/// output level is low. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void COMP_Cmd(COMP_Selection_TypeDef selection, FunctionalState state) -{ - (state) ? (*(vu32*)(COMP_BASE + selection) |= COMP_CSR_EN) : - (*(vu32*)(COMP_BASE + selection) &= ~COMP_CSR_EN); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Select CRV param. -/// @param crv_select: Select source for CRV. -/// @param crv_level: Set level for CRV. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void COMP_SetCrv(u8 crv_select, u8 crv_level) -{ - u32 temreg = 0; - temreg = COMP->CRV; - temreg &= ~COMP_CRV_MASK; - // Load config to CRV and enable - temreg |= crv_select | crv_level | (1 << 4); - COMP->CRV = temreg; -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Close or Open the SW1 switch. -/// @param selection: the selected comparator. -/// select the COMP peripheral. -/// @param state: new state of the COMP peripheral. -/// This parameter can be: ENABLE or DISABLE. -/// When enabled, the comparator compares the non inverting input with -/// the inverting input and the comparison result is available on -/// comparator output. -/// When disabled, the comparator doesn't perform comparison and the -/// output level is low. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void COMP_SwitchCmd(COMP_Selection_TypeDef selection, FunctionalState state) -{ - (state) ? - (*(vu32*)(COMP_BASE + selection) |= COMP_CSR_COMPSW1) : - (*(vu32*)(COMP_BASE + selection) &= ~COMP_CSR_COMPSW1); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Return the output level (high or low) of the selected comparator. -/// The output level depends on the selected polarity. -/// If the polarity is not inverted: -/// - Comparator output is low when the non-inverting input is at a -/// lower voltage than the inverting input -/// - Comparator output is high when the non-inverting input is at a -/// higher voltage than the inverting input -/// If the polarity is inverted: -/// - Comparator output is high when the non-inverting input is at a -/// lower voltage than the inverting input -/// - Comparator output is low when the non-inverting input is at a -/// higher voltage than the inverting input -/// @param comp: the selected comparator. -/// select the COMP peripheral. -/// @retval The selected comparator output level: low or high. -//////////////////////////////////////////////////////////////////////////////// -u32 COMP_GetOutputLevel(COMP_Selection_TypeDef selection) -{ - return (((*(vu32*)(COMP_BASE + selection) & COMP_CSR_STA) != 0) ? - COMP_OutputLevel_High : - COMP_OutputLevel_Low ); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Lock the selected comparator (COMP1/COMP2) configuration. -/// @param selection: the selected comparator. -/// select the COMP peripheral. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void COMP_LockConfig(COMP_Selection_TypeDef selection) -{ - *(vu32*)(COMP_BASE + selection) |= COMP_CSR_LOCK; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enable or disable the COMP register. -/// @param state: new state of the COMP peripheral. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void exCOMP_CrvCmd(FunctionalState state) -{ - (state) ? (COMP->CRV |= COMP_CRV_EN_ENABLE) : (COMP->CRV &= ~COMP_CRV_EN_ENABLE); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Select comparator external reference voltage. -/// @param selection: the selected external reference voltage. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void exCOMP_SwitchCrv(u32 crv) -{ - COMP->CRV |= crv; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Select comparator external reference voltage source. -/// @param selection: the selected external reference voltage source. -/// This parameter can be: COMP_CRV_SRC_AVDD or COMP_CRV_SRC_VREF. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void exCOMP_CrvSrc(u32 src) -{ - COMP->CRV |= src; -} - - - - - -/// @} - -/// @} - -/// @} diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_crc.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_crc.c deleted file mode 100644 index 817698bf5..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_crc.c +++ /dev/null @@ -1,108 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_crc.c -/// @author AE TEAM -/// @brief THIS FILE PROVIDES ALL THE CRC FIRMWARE FUNCTIONS. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

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-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#define _HAL_CRC_C_ - -// Files includes -#include "hal_crc.h" - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup CRC_HAL -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup CRC_Exported_Functions -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Resets the CRC Data register (DR). -/// @param None. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void CRC_ResetDR() -{ - CRC->CR = CRC_CR_RESET; -} -//#pragma optimize(0) -//////////////////////////////////////////////////////////////////////////////// -/// @brief Computes the 32-bit CRC of a given data word(32-bit). -/// @param Data: data word(32-bit) to compute its CRC -/// @retval 32-bit CRC -//////////////////////////////////////////////////////////////////////////////// -u32 CRC_CalcCRC(u32 data) -{ - CRC->DR = data; - return (CRC->DR); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). -/// @param buffer: pointer to the buffer containing the data to be computed -/// @param length: length of the buffer to be computed -/// @retval 32-bit CRC -//////////////////////////////////////////////////////////////////////////////// -u32 CRC_CalcBlockCRC(u32* buffer, u32 length) -{ - u32 i; - for (i = 0; i < length; i++) { - CRC->DR = buffer[i]; - } - return (CRC->DR); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Returns the current CRC value. -/// @param None. -/// @retval 32-bit CRC -//////////////////////////////////////////////////////////////////////////////// -u32 CRC_GetCRC(void) -{ - return (CRC->DR); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Stores a 8-bit data in the Independent Data(ID) register. -/// @param id_value: 8-bit value to be stored in the ID register -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void CRC_SetIDRegister(u8 id_value) -{ - CRC->IDR = id_value; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Returns the 8-bit data stored in the Independent Data(ID) register -/// @param None. -/// @retval 8-bit value of the ID register -//////////////////////////////////////////////////////////////////////////////// -u8 CRC_GetIDRegister() -{ - return (CRC->IDR); -} - -/// @} - -/// @} - -/// @} - - diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_crs.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_crs.c deleted file mode 100644 index 10b26d353..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_crs.c +++ /dev/null @@ -1,43 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_crs.c -/// @author AE TEAM -/// @brief THIS FILE PROVIDES ALL THE CRS FIRMWARE FUNCTIONS. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#define _HAL_CRS_C_ - -// Files includes -#include "hal_rcc.h" -#include "hal_crs.h" - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup CRS_HAL -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup CRS_Exported_Functions -/// @{ - -/// @} - -/// @} - -/// @} - - diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dac.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dac.c deleted file mode 100644 index b3583f155..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dac.c +++ /dev/null @@ -1,184 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_dac.c -/// @author AE TEAM -/// @brief THIS FILE PROVIDES ALL THE DAC FIRMWARE FUNCTIONS. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#define _HAL_DAC_C_ - -// Files includes -#include "hal_dac.h" -#include "hal_rcc.h" - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup DAC_HAL -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup DAC_Exported_Functions -/// @{ - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Deinitializes the DAC peripheral registers to their default reset values. -/// @param None. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void DAC_DeInit(void) -{ - exRCC_APB1PeriphReset(RCC_APB1ENR_DAC); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Initializes the DAC peripheral according to the specified parameters in the DAC_InitStruct. -/// @param channel: the selected DAC channel. -/// @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that contains the configuration information for the specified -/// DAC channel. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void DAC_Init(emDACCH_TypeDef channel, DAC_InitTypeDef* init_struct) -{ - DAC->CR &= ~((DAC_CR_BOFF1 | DAC_CR_TEN1 | DAC_CR_TSEL1 | DAC_CR_WAVE1 | DAC_CR_MAMP1) << channel); - DAC->CR |= (((u32)(init_struct->DAC_Trigger) | (u32)(init_struct->DAC_WaveGeneration) | - (u32)(init_struct->DAC_LFSRUnmask_TriangleAmplitude) | (u32)(init_struct->DAC_OutputBuffer)) - << channel); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Fills each DAC_InitStruct member with its default value. -/// @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will be initialized. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void DAC_StructInit(DAC_InitTypeDef* init_struct) -{ - init_struct->DAC_Trigger = DAC_Trigger_None; - init_struct->DAC_WaveGeneration = DAC_WaveGeneration_None; - init_struct->DAC_LFSRUnmask_TriangleAmplitude = DAC_TriangleAmplitude_1; - init_struct->DAC_OutputBuffer = DAC_OutputBuffer_Enable; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the specified DAC channel. -/// @param channel: the selected DAC channel. -/// @param state: new state of the DAC channel. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void DAC_Cmd(emDACCH_TypeDef channel, FunctionalState state) -{ - (state) ? (DAC->CR |= DAC_CR_EN1 << channel) : (DAC->CR &= ~(DAC_CR_EN1 << channel)); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the specified DAC channel DMA request. -/// @param channel: the selected DAC channel. -/// @param state: new state of the selected DAC channel DMA request. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void DAC_DMACmd(emDACCH_TypeDef channel, FunctionalState state) -{ - (state) ? (DAC->CR |= DAC_CR_DMAEN1 << channel) : (DAC->CR &= ~(DAC_CR_DMAEN1 << channel)); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the selected DAC channel software trigger. -/// @param channel: the selected DAC channel. -/// @param state: new state of the selected DAC channel software trigger. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void DAC_SoftwareTriggerCmd(emDACCH_TypeDef channel, FunctionalState state) -{ - (state) ? (DAC->SWTRIGR |= (DAC_SWTRIGR_SWTRIG1 << (channel >> 4))) - : (DAC->SWTRIGR &= ~(DAC_SWTRIGR_SWTRIG1 << (channel >> 4))); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables simultaneously the two DAC channels software triggers. -/// @param state: new state of the DAC channels software triggers. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void DAC_DualSoftwareTriggerCmd(FunctionalState state) -{ - (state) ? (DAC->SWTRIGR |= (DAC_SWTRIGR_SWTRIG1 | DAC_SWTRIGR_SWTRIG2)) - : (DAC->SWTRIGR &= ~(DAC_SWTRIGR_SWTRIG1 | DAC_SWTRIGR_SWTRIG2)); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the selected DAC channel wave generation. -/// @param channel: the selected DAC channel. -/// @param wave: Specifies the wave type to enable or disable. -/// @param state: new state of the selected DAC channel wave generation. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void DAC_WaveGenerationCmd(emDACCH_TypeDef channel, emDACWAVE_TypeDef wave, FunctionalState state) -{ - (state) ? (DAC->CR |= wave << channel) : (DAC->CR &= ~(wave << channel)); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Set the specified data holding register value for DAC channel1. -/// @param alignement: Specifies the data alignement for DAC channel1. -/// @param data : data to be loaded in the selected data holding register. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void DAC_SetChannel1Data(emDACALIGN_TypeDef alignement, u16 data) -{ - *((u32*)(DAC_BASE + DHR12R1_Offset + alignement)) = data; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Set the specified data holding register value for DAC channel2. -/// @param alignement: Specifies the data alignement for DAC channel2. -/// @param data : data to be loaded in the selected data holding -/// register. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void DAC_SetChannel2Data(emDACALIGN_TypeDef alignement, u16 data) -{ - *((u32*)(DAC_BASE + DHR12R2_Offset + alignement)) = data; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Set the specified data holding register value for dual channel DAC. -/// @param alignement: Specifies the data alignement for dual channel DAC. -/// @param data2: data for DAC Channel2 to be loaded in the selected data holding register. -/// @param data1: data for DAC Channel1 to be loaded in the selected data holding register. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void DAC_SetDualChannelData(emDACALIGN_TypeDef alignement, u16 data2, u16 data1) -{ - u32 data = ((alignement == DAC_Align_8b_R) ? ((data2 << 8) | data1) : ((data2 << 16) | data1)); - *((u32*)(DAC_BASE + DHR12RD_Offset + alignement)) = data; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Returns the last data output value of the selected DAC cahnnel. -/// @param channel: the selected DAC channel. -/// @retval The selected DAC channel data output value. -//////////////////////////////////////////////////////////////////////////////// -u16 DAC_GetDataOutputValue(emDACCH_TypeDef channel) -{ - return (*(vu32*)(DAC_BASE + DOR_Offset + (channel >> 2))); -} -/// @} - -/// @} - -/// @} - - diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dbg.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dbg.c deleted file mode 100644 index b51d13214..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dbg.c +++ /dev/null @@ -1,53 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_dbg.c -/// @author AE TEAM -/// @brief THIS FILE PROVIDES ALL THE DBG FIRMWARE FUNCTIONS. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#define _HAL_DBG_C - -// Files includes -#include "types.h" -#include "hal_dbg.h" - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup DBG_HAL -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup DBG_Exported_Functions -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the specified DBG peripheral. -/// @param periph: DBG peripheral. -/// @param state: new state of the specified DBG peripheral. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void DBGMCU_Configure(u32 periph, FunctionalState state) -{ - (state) ? (DBGMCU->CR |= periph) : (DBGMCU->CR &= ~periph); -} - -/// @} - -/// @} - -/// @} diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dma.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dma.c deleted file mode 100644 index 5ec0dc95a..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dma.c +++ /dev/null @@ -1,319 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_dma.c -/// @author AE TEAM -/// @brief THIS FILE PROVIDES ALL THE DMA FIRMWARE FUNCTIONS. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - - - - - - -// Define to prevent recursive inclusion -#define _HAL_DMA_C_ - -// Files includes -#include "types.h" -#include "hal_dma.h" - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup DMA_HAL -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup DMA_Exported_Functions -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Deinitializes the DMA Channeln registers to their default reset -/// values. -/// @param select the DMA Channel. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void DMA_DeInit(DMA_Channel_TypeDef* channel) -{ - channel->CCR &= ~DMA_CCR_EN; - channel->CCR = 0; - channel->CNDTR = 0; - channel->CPAR = 0; - channel->CMAR = 0; - if((*(vu32*)&channel) >= (*(vu32*)DMA2_Channel1_BASE)) { - DMA2->IFCR |= (u32)0x0F << (((*(vu32*)&channel & (u32)0xff) - 8) / 5); - } - else { - DMA1->IFCR |= (u32)0x0F << (((*(vu32*)&channel & (u32)0xff) - 8) / 5); - } -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Initializes the DMA Channeln according to the specified -/// parameters in the init_struct. -/// @param select the DMA Channel. -/// @param init_struct: pointer to a DMA_InitTypeDef structure that -/// contains the configuration information for the specified DMA -/// Channel. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void DMA_Init(DMA_Channel_TypeDef* channel, DMA_InitTypeDef* init_struct) -{ - MODIFY_REG( - channel->CCR, - (DMA_CCR_DIR | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL | DMA_CCR_M2M), - ((u32)init_struct->DMA_DIR | (u32)init_struct->DMA_Mode | (u32)init_struct->DMA_PeripheralInc | - (u32)init_struct->DMA_MemoryInc | (u32)init_struct->DMA_PeripheralDataSize | (u32)init_struct->DMA_MemoryDataSize | - (u32)init_struct->DMA_Priority | (u32)init_struct->DMA_M2M)); - - MODIFY_REG(channel->CCR, DMA_CCR_ARE, init_struct->DMA_Auto_reload); - channel->CNDTR = init_struct->DMA_BufferSize; - channel->CPAR = init_struct->DMA_PeripheralBaseAddr; - channel->CMAR = init_struct->DMA_MemoryBaseAddr; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Fills each init_struct member with its default value. -/// @param init_struct : pointer to a DMA_InitTypeDef structure which will -/// be initialized. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void DMA_StructInit(DMA_InitTypeDef* init_struct) -{ - init_struct->DMA_PeripheralBaseAddr = 0; - init_struct->DMA_MemoryBaseAddr = 0; - init_struct->DMA_DIR = DMA_DIR_PeripheralSRC; - init_struct->DMA_BufferSize = 0; - init_struct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; - init_struct->DMA_MemoryInc = DMA_MemoryInc_Disable; - init_struct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; - init_struct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; - init_struct->DMA_Mode = DMA_Mode_Normal; - init_struct->DMA_Priority = DMA_Priority_Low; - init_struct->DMA_M2M = DMA_M2M_Disable; - - init_struct->DMA_Auto_reload = DMA_Auto_Reload_Disable; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the specified DMA Channeln. -/// @param channel: select the DMA Channel. -/// @param state: new state of the DMA Channeln. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void DMA_Cmd(DMA_Channel_TypeDef* channel, FunctionalState state) -{ - MODIFY_REG(channel->CCR, DMA_CCR_EN, state << DMA_CCR_EN_Pos); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the specified DMA Channeln interrupts. -/// @param channel: select the DMA Channel. -/// @param it: specifies the DMA interrupts sources to be enabled -/// or disabled. -/// This parameter can be any combination of the following values: -/// @arg DMA_IT_TC: Transfer complete interrupt mask -/// @arg DMA_IT_HT: Half transfer interrupt mask -/// @arg DMA_IT_TE: Transfer error interrupt mask -/// @param state: new state of the specified DMA interrupts. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void DMA_ITConfig(DMA_Channel_TypeDef* channel, DMA_Interrupt_EN_TypeDef it, FunctionalState state) -{ - (state) ? (channel->CCR |= it) : (channel->CCR &= ~it); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Sets the number of data units in the select the DMA Channel . -/// @param channel: select the DMA Channel -/// @param DataNumber: The number of data units in the current DMAy Channelx -/// transfer. -/// @note This function can only be used when the DMAy_Channelx is disabled. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* channel, u16 length) -{ - channel->CNDTR = length; -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Returns the number of remaining data units in the current -/// DMA Channeln transfer. -/// @param channel: select the DMA Channel. -/// @retval The number of remaining data units in the current DMA Channeln -/// transfer. -//////////////////////////////////////////////////////////////////////////////// -u16 DMA_GetCurrDataCounter(DMA_Channel_TypeDef* channel) -{ - return channel->CNDTR; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Checks whether the specified DMA Channeln flag is set or not. -/// @param flag: specifies the flag to check. -/// This parameter can be one of the following values: -/// @arg DMA1_FLAG_GLn: DMA1 Channeln global flag(n = 1..7). -/// @arg DMA1_FLAG_TCn: DMA1 Channeln transfer complete flag(n = 1..7). -/// @arg DMA1_FLAG_HTn: DMA1 Channeln half transfer flag(n = 1..7). -/// @arg DMA1_FLAG_TEn: DMA1 Channeln transfer error flag(n = 1..7). -/// @arg DMA2_FLAG_GLn: DMA1 Channeln global flag(n = 1..5). -/// @arg DMA2_FLAG_TCn: DMA1 Channeln transfer complete flag(n = 1..5). -/// @arg DMA2_FLAG_HTn: DMA1 Channeln half transfer flag(n = 1..5). -/// @arg DMA2_FLAG_TEn: DMA1 Channeln transfer error flag(n = 1..5). -/// @retval The new state of DMAy_FLAG (SET or RESET). -//////////////////////////////////////////////////////////////////////////////// -FlagStatus DMA_GetFlagStatus(DMA_Flags_TypeDef flag) -{ - if(flag >= DMA2_FLAG_GL1 ) { - return (DMA2->ISR & flag) ? SET : RESET; - } - return (DMA1->ISR & flag) ? SET : RESET; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Clears the DMA Channeln's pending flags. -/// @param flag: specifies the flag to clear. -/// This parameter can be any combination (for the same DMA) of the -/// following values: -/// @arg DMA1_FLAG_GLn: DMA1 Channeln global flag(n = 1..7). -/// @arg DMA1_FLAG_TCn: DMA1 Channeln transfer complete flag(n = 1..7). -/// @arg DMA1_FLAG_HTn: DMA1 Channeln half transfer flag(n = 1..7). -/// @arg DMA1_FLAG_TEn: DMA1 Channeln transfer error flag(n = 1..7). -/// @arg DMA2_FLAG_GLn: DMA1 Channeln global flag(n = 1..5). -/// @arg DMA2_FLAG_TCn: DMA1 Channeln transfer complete flag(n = 1..5). -/// @arg DMA2_FLAG_HTn: DMA1 Channeln half transfer flag(n = 1..5). -/// @arg DMA2_FLAG_TEn: DMA1 Channeln transfer error flag(n = 1..5). -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void DMA_ClearFlag(DMA_Flags_TypeDef flag) -{ - if(flag >= DMA2_FLAG_GL1 ) { - DMA2->IFCR = flag; - return ; - } - DMA1->IFCR = flag; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Checks whether the specified DMA Channeln interrupt has occurred or -/// not. -/// @param it: specifies the DMA interrupt source to check. -/// This parameter can be one of the following values: -/// @arg DMA1_IT_GLn: DMA1 Channeln global interrupt(n = 1..7). -/// @arg DMA1_IT_TCn: DMA1 Channeln transfer complete interrupt(n = 1..7). -/// @arg DMA1_IT_HTn: DMA1 Channeln half transfer interrupt(n = 1..7). -/// @arg DMA1_IT_TEn: DMA1 Channeln transfer error interrupt(n = 1..7). -/// @arg DMA2_IT_GLn: DMA1 Channeln global flag(n = 1..5). -/// @arg DMA2_IT_TCn: DMA1 Channeln transfer complete flag(n = 1..5). -/// @arg DMA2_IT_HTn: DMA1 Channeln half transfer flag(n = 1..5). -/// @arg DMA2_IT_TEn: DMA1 Channeln transfer error flag(n = 1..5). -/// @retval The new state of DMAy_IT (SET or RESET). -//////////////////////////////////////////////////////////////////////////////// -ITStatus DMA_GetITStatus(DMA_Interrupts_TypeDef it) -{ - if(it >= DMA2_IT_GL1 ) { - return (DMA2->ISR & it) ? SET : RESET; - } - return (DMA1->ISR & it) ? SET : RESET; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Clears the DMA Channeln's interrupt pending bits. -/// @param it: specifies the DMA interrupt pending bit to clear. -/// This parameter can be any combination (for the same DMA) of the -/// following values: -/// @arg DMA1_IT_GLn: DMA1 Channeln global interrupt(n = 1..7). -/// @arg DMA1_IT_TCn: DMA1 Channeln transfer complete interrupt(n = 1..7). -/// @arg DMA1_IT_HTn: DMA1 Channeln half transfer interrupt(n = 1..7). -/// @arg DMA1_IT_TEn: DMA1 Channeln transfer error interrupt(n = 1..7). -/// @arg DMA2_IT_GLn: DMA1 Channeln global flag(n = 1..5). -/// @arg DMA2_IT_TCn: DMA1 Channeln transfer complete flag(n = 1..5). -/// @arg DMA2_IT_HTn: DMA1 Channeln half transfer flag(n = 1..5). -/// @arg DMA2_IT_TEn: DMA1 Channeln transfer error flag(n = 1..5). -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void DMA_ClearITPendingBit(DMA_Interrupts_TypeDef it) -{ - if(it >= DMA2_IT_GL1 ) { - DMA2->IFCR = it; - return ; - } - DMA1->IFCR = it; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Set the DMA Channeln's Peripheral address. -/// @param channel : where n can be 1 to 7 for DMA1 to select the DMA Channel. -/// @param address : DMA Peripheral address. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void exDMA_SetPeripheralAddress(DMA_Channel_TypeDef* channel, u32 address) -{ - channel->CPAR = address; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Set the DMA Channeln's Peripheral address. -/// @param channel : select the DMA Channel. -/// @param length : Transmit lengths. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void exDMA_SetTransmitLen(DMA_Channel_TypeDef* channel, u16 length) -{ - channel->CNDTR = length; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Set the DMA Channeln's Peripheral address. -/// @param channel :select the DMA Channel. -/// @param address : DMA memery address. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void exDMA_SetMemoryAddress(DMA_Channel_TypeDef* channel, u32 address) -{ - channel->CMAR = address; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Clears the DMA Channeln's interrupt pending bits. -/// @param it: specifies the DMA interrupt pending bit to clear. -/// This parameter can be any combination (for the same DMA) of the -/// following values: -/// @arg DMA1_IT_GLn: DMA1 Channeln global interrupt(n = 1..7). -/// @arg DMA1_IT_TCn: DMA1 Channeln transfer complete interrupt(n = 1..7). -/// @arg DMA1_IT_HTn: DMA1 Channeln half transfer interrupt(n = 1..7). -/// @arg DMA1_IT_TEn: DMA1 Channeln transfer error interrupt(n = 1..7). -/// @arg DMA2_IT_GLn: DMA1 Channeln global flag(n = 1..5). -/// @arg DMA2_IT_TCn: DMA1 Channeln transfer complete flag(n = 1..5). -/// @arg DMA2_IT_HTn: DMA1 Channeln half transfer flag(n = 1..5). -/// @arg DMA2_IT_TEn: DMA1 Channeln transfer error flag(n = 1..5). -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void exDMA_ClearITPendingBit(DMA_Channel_TypeDef* channel, u32 it) -{ - if(it >= DMA2_IT_GL1 ) { - DMA2->IFCR |= (u32)0x0F << (((*(vu32*)&channel & (u32)0xff) - 8) / 5); - DMA2->IFCR = it; - return ; - } - DMA1->IFCR |= (u32)0x0F << (((*(vu32*)&channel & (u32)0xff) - 8) / 5); - DMA1->IFCR = it; -} -/// @} - -/// @} - -/// @} diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_eth.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_eth.c deleted file mode 100644 index ca662e978..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_eth.c +++ /dev/null @@ -1,836 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_eth.c -/// @author AE TEM -/// @brief THIS FILE PROVIDES ALL THE HAL_eth.c EXAMPLE. -/// //////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -#define _HAL_ETH_C_ -#include "hal_rcc.h" -#include "hal_eth.h" -#include "reg_eth.h" - - -void ETH_DeInit(void) -{ - RCC_AHBPeriphResetCmd(RCC_AHBENR_ETHMAC, ENABLE); - RCC_AHBPeriphResetCmd(RCC_AHBENR_ETHMAC, DISABLE); -} - -void ETH_StructInit(ETH_InitTypeDef* ptr) -{ - ptr->ETH_AutoNegotiation = ETH_AutoNegotiation_Enable; ///< PHY Auto-negotiation enabled - ptr->ETH_Watchdog = ETH_Watchdog_Enable; ///< MAC watchdog enabled: cuts off long frame - ptr->ETH_Jabber = ETH_Jabber_Enable; ///< MAC Jabber enabled in Half-duplex mode - ptr->ETH_InterFrameGap = ETH_InterFrameGap_96Bit; ///< Ethernet interframe gap set to 96 bits - ptr->ETH_CarrierSense = ETH_CarrierSense_Enable; ///< Carrier Sense Enabled in Half-Duplex mode - ptr->ETH_Speed = ETH_Speed_100M; ///< PHY speed configured to 100Mbit/s - ptr->ETH_ReceiveOwn = ETH_ReceiveOwn_Enable; ///< Receive own Frames in Half-Duplex mode enabled - ptr->ETH_LoopbackMode = ETH_LoopbackMode_Disable; ///< MAC MII loopback disabled - ptr->ETH_Mode = ETH_Mode_FullDuplex; ///< Full-Duplex mode selected - ptr->ETH_ChecksumOffload = ETH_ChecksumOffload_Disable; ///< IPv4 and TCP/UDP/ICMP frame Checksum Offload disabled - ptr->ETH_RetryTransmission = ETH_RetryTransmission_Enable; ///< Retry Transmission enabled for half-duplex mode - ptr->ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable; ///< Automatic PAD/CRC strip disable - ptr->ETH_BackOffLimit = ETH_BackOffLimit_10; ///< half-duplex mode retransmission Backoff time_limit = 10 slot time - ptr->ETH_DeferralCheck = ETH_DeferralCheck_Disable; ///< half-duplex mode Deferral check disabled - ptr->ETH_ReceiveAll = ETH_ReceiveAll_Disable; ///< Receive all frames disabled - ptr->ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable; ///< Source address filtering (on the optional MAC addresses) disabled - ptr->ETH_PassControlFrames = ETH_PassControlFrames_BlockAll; ///< Do not forward control frames that do not pass the address filtering - ptr->ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable; ///< Disable reception of Broadcast frames - ptr->ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal; ///< Normal Destination address filtering (not reverse addressing) - ptr->ETH_PromiscuousMode = ETH_PromiscuousMode_Disable; ///< Promiscuous address filtering mode disabled - ptr->ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect; ///< Perfect address filtering for multicast addresses - ptr->ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect; ///< Perfect address filtering for unicast addresses - ptr->ETH_HashTableHigh = 0x0; ///< Initialize hash table high and low regs - ptr->ETH_HashTableLow = 0x0; - ptr->ETH_PauseTime = 0x0; ///< Flow control config (flow control disabled) - ptr->ETH_ZeroQuantaPause = ETH_ZeroQuantaPause_Enable; - ptr->ETH_PauseLowThreshold = ETH_PauseLowThreshold_Minus4; - ptr->ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable; - ptr->ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable; - ptr->ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable; - ptr->ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit; ///< VLANtag config (VLAN field not checked) - ptr->ETH_VLANTagIdentifier = 0x0; - - ptr->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable; ///< Drops frames with with TCP/IP checksum errors - ptr->ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable; ///< Store and forward mode enabled for receive - ptr->ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Enable; ///< Flush received frame that created FIFO overflow - ptr->ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable; ///< Store and forward mode enabled for transmit - ptr->ETH_TransmitThresholdControl = ETH_ReceiveThresholdControl_64Bytes; ///< Threshold TXFIFO level set to 64 bytes (used when threshold mode is enabled) - ptr->ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable; ///< Disable forwarding frames with errors (short frames, CRC,...) - ptr->ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable; ///< Disable undersized good frames - ptr->ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes; ///< Threshold RXFIFO level set to 64 bytes (used when Cut through mode is enabled) - ptr->ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable; ///< Disable Operate on second frame (transmit a second frame to FIFO without waiting status of previous frame - ptr->ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable; ///< DMA works on 32-bit aligned start source and destinations addresses - ptr->ETH_FixedBurst = ETH_FixedBurst_Enable; ///< Enabled Fixed Burst Mode (mix of INC4, INC8, INC16 and SINGLE DMA transactions - ptr->ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat; ///< DMA transfer max burst length = 32 beats = 32 x 32bits - ptr->ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat; - ptr->ETH_DescriptorSkipLength = 0x0; ///< DMA Ring mode skip length = 0 - ptr->ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_1_1; ///< Equal priority (round-robin) between transmit and receive DMA engines -} - -u32 ETH_Init(ETH_InitTypeDef* ptr, u16 phy_addr) -{ - u32 hclk = RCC_GetHCLKFreq(); - u32 reg = ETH->MACMIIAR & MACMIIAR_CR_MASK; - u32 temp_val = 0; - hclk = 100000000; - //////////////////////////////////////////////////////////////////////////// - if (hclk >= 20000000 && hclk < 35000000) { - reg |= ETH_MACMIIAR_CR_Div16; ///< HCLK 20 ~ 35 MHz, /16 - } - else if (hclk >= 35000000 && hclk < 60000000) { - reg |= ETH_MACMIIAR_CR_Div26; ///< HCLK 35 ~ 60 MHz, /26 - } - else if (hclk >= 60000000 && hclk < 100000000) { - reg |= ETH_MACMIIAR_CR_Div42; ///< HCLK 60 ~ 100 MHz, /42 - } - else if (hclk >= 100000000 && hclk < 150000000) { - reg |= ETH_MACMIIAR_CR_Div62; ///< HCLK 100 ~ 150 MHz, /62 - } - else { - reg |= ETH_MACMIIAR_CR_Div102; ///< HCLK 150 ~ 168 MHz, /102 - } - - ETH->MACMIIAR = reg; - - //////////////////////////////////////////////////////////////////////////// - ETH_WritePHYRegister(phy_addr, PHY_BCR, PHY_Reset); - if (ptr->ETH_AutoNegotiation != ETH_AutoNegotiation_Disable) { - // Wait for linked status - while (!(ETH_ReadPHYRegister(phy_addr, PHY_BSR) & PHY_Linked_Status)); - ETH_WritePHYRegister(phy_addr, PHY_BCR, PHY_AutoNegotiation); - // Enable Auto-Negitation - while (!(ETH_ReadPHYRegister(phy_addr, PHY_BSR) & PHY_AutoNego_Complete)) { - - } - // Read the result of the Auto-Negitation - temp_val = ETH_ReadPHYRegister(phy_addr, 31); - - if ((temp_val & 0x1C) == 0x4) { - ptr->ETH_Speed = ETH_Speed_10M; - ptr->ETH_Mode = ETH_Mode_HalfDuplex; - SYSCFG->CFGR2 &= ~(1 << 21); - } - else if((temp_val & 0x1C) == 0x14) { - ptr->ETH_Speed = ETH_Speed_10M; - ptr->ETH_Mode = ETH_Mode_FullDuplex; - SYSCFG->CFGR2 |= 1 << 21; - } - else if((temp_val & 0x1C) == 0x8) { - ptr->ETH_Speed = ETH_Speed_100M; - ptr->ETH_Mode = ETH_Mode_HalfDuplex; - SYSCFG->CFGR2 &= ~(1 << 21); - } - else if((temp_val & 0x1C) == 0x18) { - ptr->ETH_Speed = ETH_Speed_100M; - ptr->ETH_Mode = ETH_Mode_FullDuplex; - SYSCFG->CFGR2 |= 1 << 21; - } - } - else { - ETH_WritePHYRegister(phy_addr, PHY_BCR, ((u16)(ptr->ETH_Mode >> 3) | - (u16)(ptr->ETH_Speed >> 1))); - if(ptr->ETH_Speed == ETH_Speed_10M) { - SYSCFG->CFGR2 &= ~(1 << 21); - } - else { - SYSCFG->CFGR2 |= 1 << 21; - } - } - - //////////////////////////////////////////////////////////////////////////// - ETH->MACCR = ETH->MACCR & MACCR_CLEAR_MASK | (ptr->ETH_Watchdog | - ptr->ETH_Jabber | - ptr->ETH_InterFrameGap | - ptr->ETH_CarrierSense | - ptr->ETH_Speed | - ptr->ETH_ReceiveOwn | - ptr->ETH_LoopbackMode | - ptr->ETH_Mode | - ptr->ETH_ChecksumOffload | - ptr->ETH_RetryTransmission | - ptr->ETH_AutomaticPadCRCStrip | - ptr->ETH_DeferralCheck); - - ETH->MACFFR = ptr->ETH_ReceiveAll | - ptr->ETH_SourceAddrFilter | - ptr->ETH_PassControlFrames | - ptr->ETH_BroadcastFramesReception | - ptr->ETH_DestinationAddrFilter | - ptr->ETH_PromiscuousMode | - ptr->ETH_MulticastFramesFilter | - ptr->ETH_UnicastFramesFilter; - - ETH->MACHTHR = ptr->ETH_HashTableHigh; - ETH->MACHTLR = ptr->ETH_HashTableLow; - - ETH->MACFCR = ETH->MACFCR & MACFCR_CLEAR_MASK | ((ptr->ETH_PauseTime << ETH_MACFCR_PT_Pos) | - ptr->ETH_ZeroQuantaPause | - ptr->ETH_PauseLowThreshold | - ptr->ETH_UnicastPauseFrameDetect | - ptr->ETH_ReceiveFlowControl | - ptr->ETH_TransmitFlowControl); - - ETH->MACVLANTR = ptr->ETH_VLANTagComparison | ptr->ETH_VLANTagIdentifier; - - ETH->DMAOMR = 0x00200004; - ETH->DMAIER = 0x0001A040; - ETH->DMABMR = ( ptr->ETH_AddressAlignedBeats | - ptr->ETH_FixedBurst | - ptr->ETH_RxDMABurstLength | // !! if 4xPBL is selected for Tx or Rx it is applied for the other - ptr->ETH_TxDMABurstLength | - ptr->ETH_DescriptorSkipLength << 2 | - ptr->ETH_DMAArbitration);// | -// ETH_DMABMR_USP); // Enable use of separate PBL for Rx and Tx - - return ETH_SUCCESS; -} - -void ETH_Start(void) -{ - ETH_MACTransmissionCmd(ENABLE); - ETH_MACReceptionCmd(ENABLE); - ETH_FlushTransmitFIFO(); - ETH_DMATransmissionCmd(ENABLE); - ETH_DMAReceptionCmd(ENABLE); -} - -void ETH_Stop(void) -{ - ETH_DMATransmissionCmd(DISABLE); - ETH_DMAReceptionCmd(DISABLE); - ETH_MACReceptionCmd(DISABLE); - ETH_FlushTransmitFIFO(); - ETH_MACTransmissionCmd(DISABLE); -} - -void ETH_MACTransmissionCmd(FunctionalState sta) -{ - sta ? (ETH->MACCR |= ETH_MACCR_TE) : (ETH->MACCR &= ~ETH_MACCR_TE); -} - -void ETH_MACReceptionCmd(FunctionalState sta) -{ - sta ? (ETH->MACCR |= ETH_MACCR_RE) : (ETH->MACCR &= ~ETH_MACCR_RE); -} - -FlagStatus ETH_GetFlowControlBusyStatus(void) -{ - return (FlagStatus)(ETH->MACFCR & ETH_MACFCR_FCBBPA); -} - -void ETH_InitiatePauseControlFrame(void) -{ - ETH->MACFCR |= ETH_MACFCR_FCBBPA; -} - -void ETH_BackPressureActivationCmd(FunctionalState sta) -{ - sta ? (ETH->MACFCR |= ETH_MACFCR_FCBBPA) : (ETH->MACFCR &= ~ETH_MACFCR_FCBBPA); -} - -void ETH_MACAddressConfig(u32 reg_addr, u8* mac_addr) -{ - *(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr) = - (u32)mac_addr[5] << 8 | - (u32)mac_addr[4]; - - *(__IO u32*)(ETH_MAC_ADDR_LBASE + reg_addr) = - (u32)mac_addr[3] << 24 | - (u32)mac_addr[2] << 16 | - (u32)mac_addr[1] << 8 | - (u32)mac_addr[0]; -} - -void ETH_GetMACAddress(u32 reg_addr, u8* mac_addr) -{ - mac_addr[5] = *(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr) >> 8 & 0xFF; - mac_addr[4] = *(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr) & 0xFF; - mac_addr[3] = *(__IO u32*)(ETH_MAC_ADDR_LBASE + reg_addr) >> 24 & 0xFF; - mac_addr[2] = *(__IO u32*)(ETH_MAC_ADDR_LBASE + reg_addr) >> 16 & 0xFF; - mac_addr[1] = *(__IO u32*)(ETH_MAC_ADDR_LBASE + reg_addr) >> 8 & 0xFF; - mac_addr[0] = *(__IO u32*)(ETH_MAC_ADDR_LBASE + reg_addr) & 0xFF; -} - -void ETH_MACAddressPerfectFilterCmd(u32 reg_addr, FunctionalState sta) -{ - sta ? ((*(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr)) |= ETH_MACA1HR_AE) : - ((*(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr)) &= ~ETH_MACA1HR_AE); -} - -void ETH_MACAddressFilterConfig(u32 reg_addr, u32 sta) -{ - sta ? ((*(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr)) |= ETH_MACA1HR_SA) : - ((*(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr)) |= ETH_MACA1HR_SA); -} - -void ETH_MACAddressMaskBytesFilterConfig(u32 reg_addr, u32 mask_byte) -{ - (*(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr)) &= ~ETH_MACA1HR_MBC; - - (*(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr)) |= mask_byte; -} - -FrameTypeDef ETH_Get_Received_Frame(void) -{ - FrameTypeDef frame; - - frame.len = ((DMARxDescToGet->CS & ETH_DMA_RDES_FL) >> ETH_DMA_RDES_FL_Pos) - 4; - frame.buf = (DMA_RX_FRAME_infos->ptrFS_Rx_Desc)->BUF1ADDR; - frame.ptrDesc = DMA_RX_FRAME_infos->ptrFS_Rx_Desc; - - - DMARxDescToGet = (ETH_DMADESCTypeDef*)(DMARxDescToGet->BUF2NDADDR); - - return frame; -} - -FrameTypeDef ETH_Get_Received_Frame_interrupt(void) -{ - FrameTypeDef frame = {0}; - __IO u32 desc_cnt = 0; - - while(!(DMARxDescToGet->CS & ETH_DMA_RDES_OWN) && desc_cnt < ETH_RX_BUF_NUM) { - desc_cnt++; - - if ( (DMARxDescToGet->CS & ETH_DMA_RDES_FS) && - !(DMARxDescToGet->CS & ETH_DMA_RDES_LS)) { - DMA_RX_FRAME_infos->ptrFS_Rx_Desc = DMARxDescToGet; - DMA_RX_FRAME_infos->cnt = 1; - DMARxDescToGet = (ETH_DMADESCTypeDef*)(DMARxDescToGet->BUF2NDADDR); - - } - else if ( (DMARxDescToGet->CS & ETH_DMA_RDES_FS) && - (DMARxDescToGet->CS & ETH_DMA_RDES_LS)) { - DMA_RX_FRAME_infos->cnt++; - DMARxDescToGet = (ETH_DMADESCTypeDef*)(DMARxDescToGet->BUF2NDADDR); - } - else { - DMA_RX_FRAME_infos->ptrLS_Rx_Desc = DMARxDescToGet; - DMA_RX_FRAME_infos->cnt++; - - if (DMA_RX_FRAME_infos->cnt == 1) - DMA_RX_FRAME_infos->ptrFS_Rx_Desc = DMARxDescToGet; - - frame.len = ((DMARxDescToGet->CS & ETH_DMA_RDES_FL) >> ETH_DMA_RDES_FL_Pos) - 4; - - frame.buf = (DMA_RX_FRAME_infos->cnt > 1) ? - (DMA_RX_FRAME_infos->ptrFS_Rx_Desc->BUF1ADDR) : - (DMARxDescToGet->BUF1ADDR); - - frame.ptrDesc = DMA_RX_FRAME_infos->ptrFS_Rx_Desc; - - DMARxDescToGet = (ETH_DMADESCTypeDef*)(DMARxDescToGet->BUF2NDADDR); - - return frame; - } - } - - return frame; -} - -u32 ETH_Prepare_Transmit_Descriptors(u16 len) -{ - u32 cnt = 0, i = 0; - __IO ETH_DMADESCTypeDef* temp_desc = DMATxDescToSet; - - if (DMATxDescToSet->CS & ETH_DMA_TDES_OWN) - return ETH_ERROR; - - if(len > ETH_TX_BUF_SIZE) { - cnt = len / ETH_TX_BUF_SIZE; - - if (len % ETH_TX_BUF_SIZE) - cnt++; - } - else { - cnt = 1; - } - - if (cnt == 1) { - temp_desc->BL &= ~(ETH_DMA_TDES_FS | ETH_DMA_TDES_LS | ETH_DMA_TDES_TBS1); - - temp_desc->BL |= ETH_DMA_TDES_FS | - ETH_DMA_TDES_LS | - (len & ETH_DMA_TDES_TBS1); - - temp_desc->CS |= ETH_DMA_TDES_OWN; - temp_desc = (ETH_DMADESCTypeDef*)(temp_desc->BUF2NDADDR); - } - else { - for (i = 0; i < cnt; i++) { - temp_desc->BL &= ~(ETH_DMA_TDES_FS | ETH_DMA_TDES_LS); - - if (i == 0) - temp_desc->BL |= ETH_DMA_TDES_FS; - - temp_desc->BL = ETH_TX_BUF_SIZE & ETH_DMA_TDES_TBS1; - - if (i == (cnt - 1)) { - temp_desc->BL &= ~ETH_DMA_TDES_TBS1; - temp_desc->BL |= ETH_DMA_TDES_LS | - ((len - (cnt - 1) * ETH_TX_BUF_SIZE) & ETH_DMA_TDES_TBS1); - } - - temp_desc->CS |= ETH_DMA_TDES_OWN; - temp_desc = (ETH_DMADESCTypeDef*)(temp_desc->BUF2NDADDR); - } - } - - DMATxDescToSet = temp_desc; - - if (ETH->DMASR & ETH_DMASR_TBUS) { - ETH->DMASR = ETH_DMASR_TBUS; - ETH->DMATPDR = 0; - } - - return ETH_SUCCESS; -} - -void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef* ptr_desc, u8* buf, u32 cnt) -{ - u32 i = 0; - ETH_DMADESCTypeDef* temp_desc; - - DMARxDescToGet = ptr_desc; - - for (i = 0; i < cnt; i++) { - temp_desc = ptr_desc + i; - temp_desc->CS = ETH_DMA_RDES_OWN; - temp_desc->BL = ETH_DMA_RDES_RCH | ETH_RX_BUF_SIZE; - temp_desc->BUF1ADDR = (u32)&buf[i * ETH_RX_BUF_SIZE]; - - if (i < cnt - 1) { - temp_desc->BUF2NDADDR = (u32)(ptr_desc + i + 1); - } - else { - temp_desc->BUF2NDADDR = (u32)(ptr_desc); - } - } - - ETH->DMARDLAR = (u32)ptr_desc; - - DMA_RX_FRAME_infos = &RX_Frame_Descriptor; -} - -u32 ETH_CheckFrameReceived(void) -{ - if(!(DMARxDescToGet->CS & ETH_DMA_RDES_OWN) && - (DMARxDescToGet->CS & ETH_DMA_RDES_LS)) { - - DMA_RX_FRAME_infos->cnt++; - - if (DMA_RX_FRAME_infos->cnt == 1) { - DMA_RX_FRAME_infos->ptrFS_Rx_Desc = DMARxDescToGet; - } - DMA_RX_FRAME_infos->ptrLS_Rx_Desc = DMARxDescToGet; - return 1; - } - else if ( !(DMARxDescToGet->CS & ETH_DMA_RDES_OWN) && - !(DMARxDescToGet->CS & ETH_DMA_RDES_LS) && - (DMARxDescToGet->CS & ETH_DMA_RDES_FS)) { - DMA_RX_FRAME_infos->ptrFS_Rx_Desc = DMARxDescToGet; - DMA_RX_FRAME_infos->ptrLS_Rx_Desc = (void*)0; - DMA_RX_FRAME_infos->cnt = 1; - } - else if ( !(DMARxDescToGet->CS & ETH_DMA_RDES_OWN) && - !(DMARxDescToGet->CS & ETH_DMA_RDES_LS) && - !(DMARxDescToGet->CS & ETH_DMA_RDES_FS)) { - DMA_RX_FRAME_infos->cnt++; - DMARxDescToGet = (ETH_DMADESCTypeDef*)(DMARxDescToGet->BUF2NDADDR); - } - - return 0; -} - -void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef* ptr_desc, u8* buf, u32 cnt) -{ - u32 i = 0; - ETH_DMADESCTypeDef* temp_desc; - - DMATxDescToSet = ptr_desc; - - for (i = 0; i < cnt; i++) { - temp_desc = ptr_desc + i; - temp_desc->BL = ETH_DMA_TDES_TCH; - temp_desc->BUF1ADDR = (u32)(&buf[i * ETH_TX_BUF_SIZE]); - - if (i < cnt - 1) { - temp_desc->BUF2NDADDR = (u32)(ptr_desc + i + 1); - } - else { - temp_desc->BUF2NDADDR = (u32)(ptr_desc); - } - } - - ETH->DMATDLAR = (u32)ptr_desc; -} - -FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef* ptr_desc, u32 flag) -{ - return (FlagStatus)(ptr_desc->CS & flag); -} - -u32 ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef* ptr_desc) -{ - return (ptr_desc->CS & ETH_DMA_TDES_CC) >> ETH_DMA_TDES_COLLISION_COUNTSHIFT; -} - -void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef* ptr_desc) -{ - ptr_desc->CS |= ETH_DMA_TDES_OWN; -} - -void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta) -{ - sta ? (ptr_desc->BL |= ETH_DMA_TDES_IC) : (ptr_desc->BL &= ~ETH_DMA_TDES_IC); -} - -void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef* ptr_desc, u32 val) -{ - ptr_desc->CS |= val; -} - -void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef* ptr_desc, u32 val) -{ - ptr_desc->CS |= val; -} - -void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta) -{ - sta ? (ptr_desc->BL &= ~ETH_DMA_TDES_DC) : (ptr_desc->BL |= ETH_DMA_TDES_DC); -} - -void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta) -{ - sta ? (ptr_desc->BL |= ETH_DMA_TDES_TCH) : (ptr_desc->BL &= ~ETH_DMA_TDES_TCH); -} - -void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta) -{ - sta ? (ptr_desc->BL &= ~ETH_DMA_TDES_DP) : (ptr_desc->BL |= ETH_DMA_TDES_DP); -} - -void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef* ptr_desc, u32 buf1_size, u32 buf2_size) -{ - ptr_desc->BL |= buf1_size | (buf2_size << ETH_DMA_TDES_BUFFER2_SIZESHIFT); -} - -FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef* ptr_desc, u32 flag) -{ - return (FlagStatus)(ptr_desc->CS & flag); -} - -void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef* ptr_desc) -{ - ptr_desc->CS |= ETH_DMA_RDES_OWN; -} - -u32 ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef* ptr_desc) -{ - return (ptr_desc->CS & ETH_DMA_RDES_FL) >> ETH_DMA_RDES_FRAME_LENGTHSHIFT; -} - -void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta) -{ - sta ? (ptr_desc->CS &= ~ETH_DMA_RDES_DIC) : (ptr_desc->CS |= ETH_DMA_RDES_DIC); -} - -u32 ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef* ptr_desc, u32 buf) -{ - return (buf != ETH_DMA_RDES_Buffer1 ? - ((ptr_desc->BL & ETH_DMA_RDES_RBS2) >> ETH_DMA_RDES_BUFFER2_SIZESHIFT) : - (ptr_desc->BL & ETH_DMA_RDES_RBS1)); -} - -u32 ETH_GetRxPktSize(ETH_DMADESCTypeDef* ptr_desc) -{ - u32 len = 0; - - if ( !(ptr_desc->CS & ETH_DMA_RDES_OWN) && - !(ptr_desc->CS & ETH_DMA_RDES_ES) && - (ptr_desc->CS & ETH_DMA_RDES_LS)) { - len = ETH_GetDMARxDescFrameLength(ptr_desc); - } - - return len; -} - -//////////////////////////////////////////////////////////////////////////////// -void ETH_SoftwareReset(void) -{ - ETH->DMABMR |= ETH_DMABMR_SR; -} - -FlagStatus ETH_GetSoftwareResetStatus(void) -{ - return (FlagStatus)(ETH->DMABMR & ETH_DMABMR_SR); -} - -FlagStatus ETH_GetDMAFlagStatus(u32 flag) -{ - return (FlagStatus)(ETH->DMASR & flag); -} - -void ETH_DMAClearFlag(u32 flag) -{ - ETH->DMASR = flag; -} - -void ETH_DMAITConfig(u32 it, FunctionalState sta) -{ - sta ? (ETH->DMAIER |= it) : (ETH->DMAIER &= ~it); -} - -ITStatus ETH_GetDMAITStatus(u32 it) -{ - return (ITStatus)(ETH->DMASR & it); -} - -void ETH_DMAClearITPendingBit(u32 it) -{ - ETH->DMASR = it; -} - -u32 ETH_GetTransmitProcessState(void) -{ - return ETH->DMASR & ETH_DMASR_TS; -} - -u32 ETH_GetReceiveProcessState(void) -{ - return ETH->DMASR & ETH_DMASR_RS; -} - -void ETH_FlushTransmitFIFO(void) -{ - ETH->DMAOMR |= ETH_DMAOMR_FTF; -} - -FlagStatus ETH_GetFlushTransmitFIFOStatus(void) -{ - return (FlagStatus)(ETH->DMAOMR & ETH_DMAOMR_FTF); -} - -void ETH_DMATransmissionCmd(FunctionalState sta) -{ - sta ? (ETH->DMAOMR |= ETH_DMAOMR_ST) : (ETH->DMAOMR &= ~ETH_DMAOMR_ST); -} - -void ETH_DMAReceptionCmd(FunctionalState sta) -{ - sta ? (ETH->DMAOMR |= ETH_DMAOMR_SR) : (ETH->DMAOMR &= ~ETH_DMAOMR_SR); -} - -FlagStatus ETH_GetDMAOverflowStatus(u32 val) -{ - return (FlagStatus)(ETH->DMAMFBOCR & val); -} - -u32 ETH_GetRxOverflowMissedFrameCounter(void) -{ - return (ETH->DMAMFBOCR & ETH_DMAMFBOCR_MFA) >> - ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT; -} - -u32 ETH_GetBufferUnavailableMissedFrameCounter(void) -{ - return ETH->DMAMFBOCR & ETH_DMAMFBOCR_MFC; -} - -u32 ETH_GetCurrentTxDescStartAddress(void) -{ - return ETH->DMACHTDR; -} - -u32 ETH_GetCurrentRxDescStartAddress(void) -{ - return ETH->DMACHRDR; -} - -u32 ETH_GetCurrentTxBufferAddress(void) -{ - return ETH->DMACHTBAR; -} - -u32 ETH_GetCurrentRxBufferAddress(void) -{ - return ETH->DMACHRBAR; -} - -void ETH_ResumeDMATransmission(void) -{ - ETH->DMATPDR = 0; -} - -void ETH_ResumeDMAReception(void) -{ - ETH->DMARPDR = 0; -} - -void ETH_SetReceiveWatchdogTimer(u8 val) -{ - ETH->DMARSWTR = val; -} - -//////////////////////////////////////////////////////////////////////////////// -u16 ETH_ReadPHYRegister(u16 addr, u16 reg) -{ - u32 dat; - // Set phy address and reg address, clear write flag - ETH->MACMIIAR = (((ETH->MACMIIAR & ~MACMIIAR_CR_MASK) | - (addr << ETH_MACMIIAR_PA_Pos & ETH_MACMIIAR_PA) | - (reg << ETH_MACMIIAR_MR_Pos & ETH_MACMIIAR_MR)) & - (~ETH_MACMIIAR_MW)) | ETH_MACMIIAR_MB; - - // Check busy flag - while(ETH->MACMIIAR & ETH_MACMIIAR_MB); - dat = (u16)ETH->MACMIIDR; - if(dat == 0xFFFF) { - dat = 0; - } - return dat; -} - -u16 ETH_WritePHYRegister(u16 addr, u16 reg, u16 val) -{ - // Load data - ETH->MACMIIDR = val; - - // Set phy address, reg address and write flag - ETH->MACMIIAR = (ETH->MACMIIAR & ~MACMIIAR_CR_MASK) | - (addr << ETH_MACMIIAR_PA_Pos & ETH_MACMIIAR_PA) | - (reg << ETH_MACMIIAR_MR_Pos & ETH_MACMIIAR_MR) | - ETH_MACMIIAR_MW | - ETH_MACMIIAR_MB; - - // Check busy flag - while(ETH->MACMIIAR & ETH_MACMIIAR_MB); - - return ETH->MACMIIDR; -} - -u32 ETH_PHYLoopBackCmd(u16 addr, FunctionalState sta) -{ - u16 temp_val = ETH_ReadPHYRegister(addr, PHY_BCR); - - sta ? (temp_val |= PHY_Loopback) : (temp_val &= ~PHY_Loopback); - - if(ETH_WritePHYRegister(addr, PHY_BCR, temp_val)) - return ETH_SUCCESS; - - return ETH_ERROR; -} - -//////////////////////////////////////////////////////////////////////////////// - -void ETH_ResetWakeUpFrameFilterRegisterPointer(void) -{ - ETH->MACPMTCSR |= ETH_MACPMTCSR_WFFRPR; -} - -void ETH_SetWakeUpFrameFilterRegister(u32* buf) -{ - u32 i = 0; - - for (i = 0; i < ETH_WAKEUP_REGISTER_LENGTH; i++) { - ETH->MACRWUFFR = buf[i]; - } -} - -void ETH_GlobalUnicastWakeUpCmd(FunctionalState sta) -{ - sta ? (ETH->MACPMTCSR |= ETH_MACPMTCSR_GU) : (ETH->MACPMTCSR &= ~ETH_MACPMTCSR_GU); -} - -FlagStatus ETH_GetPMTFlagStatus(u32 flag) -{ - return (FlagStatus)(ETH->MACPMTCSR & flag); -} - -void ETH_WakeUpFrameDetectionCmd(FunctionalState sta) -{ - sta ? (ETH->MACPMTCSR |= ETH_MACPMTCSR_WFE) : (ETH->MACPMTCSR &= ~ETH_MACPMTCSR_WFE); -} - -void ETH_MagicPacketDetectionCmd(FunctionalState sta) -{ - sta ? (ETH->MACPMTCSR |= ETH_MACPMTCSR_MPE) : (ETH->MACPMTCSR &= ~ETH_MACPMTCSR_MPE); -} - -void ETH_PowerDownCmd(FunctionalState sta) -{ - sta ? (ETH->MACPMTCSR |= ETH_MACPMTCSR_PD) : (ETH->MACPMTCSR &= ~ETH_MACPMTCSR_PD); -} - -//////////////////////////////////////////////////////////////////////////////// - -void ETH_MMCCounterFullPreset(void) -{ - ETH->MMCCR |= ETH_MMCCR_MCFHP | ETH_MMCCR_MCP; -} - -void ETH_MMCCounterHalfPreset(void) -{ - ETH->MMCCR &= ~ETH_MMCCR_MCFHP; - - ETH->MMCCR |= ETH_MMCCR_MCP; -} - -void ETH_MMCCounterFreezeCmd(FunctionalState sta) -{ - sta ? (ETH->MMCCR |= ETH_MMCCR_MCF) : (ETH->MMCCR &= ~ETH_MMCCR_MCF); -} - -void ETH_MMCResetOnReadCmd(FunctionalState sta) -{ - sta ? (ETH->MMCCR |= ETH_MMCCR_ROR) : (ETH->MMCCR &= ~ETH_MMCCR_ROR); -} - -void ETH_MMCCounterRolloverCmd(FunctionalState sta) -{ - sta ? (ETH->MMCCR &= ~ETH_MMCCR_CSR) : (ETH->MMCCR |= ETH_MMCCR_CSR); -} - -void ETH_MMCCountersReset(void) -{ - ETH->MMCCR |= ETH_MMCCR_CR; -} - -void ETH_MMCITConfig(u32 it, FunctionalState sta) -{ - if (it & 0x10000000) { - it &= 0xEFFFFFFF; - - sta ? (ETH->MMCRIMR &= ~it) : (ETH->MMCRIMR |= it); - } - else { - sta ? (ETH->MMCTIMR &= ~it) : (ETH->MMCTIMR |= it); - } -} - -ITStatus ETH_GetMMCITStatus(u32 it) -{ - if (it & 0x10000000) { - return (ITStatus)((ETH->MMCRIR & it) && !(ETH->MMCRIMR & it)); - } - else { - return (ITStatus)((ETH->MMCTIR & it) && !(ETH->MMCTIMR & it)); - } -} - -u32 ETH_GetMMCRegister(u32 reg) -{ - return *(vu32*)(ETH_BASE + reg); -} diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_exti.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_exti.c deleted file mode 100644 index 409d84d80..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_exti.c +++ /dev/null @@ -1,222 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_exti.c -/// @author AE TEAM -/// @brief THIS FILE PROVIDES ALL THE EXTI FIRMWARE FUNCTIONS. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#define _HAL_EXTI_C_ - -// Files includes -#include "hal_exti.h" - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup EXTI_HAL -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup EXTI_Exported_Functions -/// @{ - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Deinitializes the EXTI peripheral registers to their default reset -/// values. -/// @param None. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Deinitializes the EXTI registers to their default reset values. -/// @param None. -/// @retval None. -/// @note MEM_MODE bits are not affected by APB reset. -/// @note MEM_MODE bits took the value from the user option bytes. -/// @note CFGR2 register is not affected by APB reset. -/// @note CLABBB configuration bits are locked when set. -/// @note To unlock the configuration, perform a system reset. -//////////////////////////////////////////////////////////////////////////////// -void EXTI_DeInit(void) -{ - u16 i; - // Clear all - exEXTI_LineDisable(~0x00000000); - - // rc_w1 - EXTI->PR = EXTI->PR; - - // Set EXTI_CFGR1 register to reset value without affecting MEM_MODE bits - EXTI->CFGR &= EXTI_CFGR_MEMMODE; - - // Set EXTICRx registers to reset value - for (i = 0; i < 4; i++) { - EXTI->CR[i] = 0; - } -} - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Selects the GPIO pin used as EXTI Line. -/// @param port_source_gpio: selects the GPIO port to be used as source for EXTI lines . -/// @param pin_source: specifies the EXTI line to be configured. -/// @note This parameter can be pin_source where x can be: -/// For MCU: (0..15) for GPIOA, GPIOB, (13..15) for GPIOC and (0..1, 6..7) for GPIOD. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void EXTI_LineConfig(u8 port_source_gpio, u8 pin_source) -{ - EXTI->CR[pin_source >> 0x02] &= ~(0x0F << (0x04 * (pin_source & 0x03))); - EXTI->CR[pin_source >> 0x02] |= ((port_source_gpio) << (0x04 * (pin_source & 0x03))); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Initializes the EXTI peripheral according to the specified -/// parameters in the init_struct. -/// @param init_struct: pointer to a EXTI_InitTypeDef structure that -/// contains the configuration information for the EXTI peripheral. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void EXTI_Init(EXTI_InitTypeDef* init_struct) -{ - if (init_struct->EXTI_LineCmd != DISABLE) { - EXTI->IMR &= ~init_struct->EXTI_Line; - EXTI->EMR &= ~init_struct->EXTI_Line; - if (init_struct->EXTI_Mode == EXTI_Mode_Interrupt) { - EXTI->IMR |= init_struct->EXTI_Line; - } - else { - EXTI->EMR |= init_struct->EXTI_Line; - } - EXTI->RTSR &= ~init_struct->EXTI_Line; - EXTI->FTSR &= ~init_struct->EXTI_Line; - if (init_struct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) { - EXTI->RTSR |= init_struct->EXTI_Line; - EXTI->FTSR |= init_struct->EXTI_Line; // Rising and Faling afio - } - else if (init_struct->EXTI_Trigger == EXTI_Trigger_Rising) { - EXTI->RTSR |= init_struct->EXTI_Line; - } - else { - EXTI->FTSR |= init_struct->EXTI_Line; - } - } - else { - if (init_struct->EXTI_Mode == EXTI_Mode_Interrupt) { - EXTI->IMR &= ~init_struct->EXTI_Line; - } - else { - EXTI->EMR &= ~init_struct->EXTI_Line; - } - } -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Fills each init_struct member with its reset value. -/// @param init_struct: pointer to a EXTI_InitTypeDef structure which will -/// be initialized. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void EXTI_StructInit(EXTI_InitTypeDef* init_struct) -{ - init_struct->EXTI_Line = EXTI_LineNone; - init_struct->EXTI_Mode = EXTI_Mode_Interrupt; - init_struct->EXTI_Trigger = EXTI_Trigger_Falling; - init_struct->EXTI_LineCmd = DISABLE; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Generates a Software interrupt on selected EXTI line. -/// @param line: specifies the EXTI line on which the software interrupt -/// will be generated. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void EXTI_GenerateSWInterrupt(u32 line) -{ - EXTI->SWIER |= line; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Checks whether the specified EXTI line flag is set or not. -/// @param line: specifies the EXTI line flag to check. -/// @retval The new state of line (SET or RESET). -//////////////////////////////////////////////////////////////////////////////// -FlagStatus EXTI_GetFlagStatus(u32 line) -{ - return (EXTI->PR & line) ? SET : RESET; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Clears the EXTI's line pending flags. -/// @param line: specifies the EXTI lines flags to clear. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void EXTI_ClearFlag(u32 line) -{ - EXTI->PR = line; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Checks whether the specified EXTI line is asserted or not. -/// @param line: specifies the EXTI line to check. -/// @retval The new state of line (SET or RESET). -//////////////////////////////////////////////////////////////////////////////// -ITStatus EXTI_GetITStatus(u32 line) -{ - return ((EXTI->PR & line) && (EXTI->IMR & line)) ? SET : RESET; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Clears the EXTI's line pending bits. -/// @param line: specifies the EXTI lines to clear. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void EXTI_ClearITPendingBit(u32 line) -{ - EXTI->PR = line; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief EXTI Line Disable -/// @param line: specifies the EXTI lines to clear. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void exEXTI_LineDisable(u32 line) -{ - EXTI->IMR &= ~line; - EXTI->EMR &= ~line; - EXTI->RTSR &= ~line; - EXTI->FTSR &= ~line; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Clears the EXTI's line all pending bits. -/// @param None. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -u32 exEXTI_GetAllFlagStatus(void) -{ - return EXTI->PR; -} - -/// @} - -/// @} - -/// @} - diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_flash.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_flash.c deleted file mode 100644 index ecdc8be3a..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_flash.c +++ /dev/null @@ -1,548 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_flash.c -/// @author AE TEAM -/// @brief THIS FILE PROVIDES ALL THE FLASH FIRMWARE FUNCTIONS. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#define _HAL_FLASH_C_ - -// Files includes -#include "hal_flash.h" - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup FLASH_HAL -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup FLASH_Exported_Functions -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Sets the code latency value. -/// @note This function can be used for all MM32 devices. -/// @param latency: specifies the FLASH Latency value. -/// This parameter can be one of the following values: -/// @arg FLASH_Latency_0: FLASH Zero Latency cycle -/// @arg FLASH_Latency_1: FLASH One Latency cycle -/// @arg FLASH_Latency_2: FLASH Two Latency cycles -/// @arg FLASH_Latency_3: FLASH Three Latency cycles -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void FLASH_SetLatency(FLASH_Latency_TypeDef latency) -{ - FLASH->ACR = (FLASH->ACR & (~FLASH_ACR_LATENCY)) | latency; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the Half cycle flash access. -/// @note This function can be used for all MM32 devices. -/// @param half_cycle_access: specifies the FLASH Half cycle Access mode. -/// This parameter can be one of the following values: -/// @arg FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable -/// @arg FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void FLASH_HalfCycleAccessCmd(FLASH_HalfCycleAccess_TypeDef half_cycle_access) -{ - FLASH->ACR &= ~FLASH_ACR_HLFCYA; - FLASH->ACR |= half_cycle_access; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the Prefetch Buffer. -/// @note This function can be used for all MM32 devices. -/// @param prefetch_buffer: specifies the Prefetch buffer status. -/// This parameter can be one of the following values: -/// @arg FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable -/// @arg FLASH_PrefetchBuffer_Disable: FLASH Prefetch Buffer Disable -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_TypeDef prefetch_buffer) -{ - FLASH->ACR &= ~FLASH_ACR_PRFTBE; - FLASH->ACR |= prefetch_buffer; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Locks the FLASH Program Erase Controller. -/// @note This function can be used for all MM32 devices. -/// @param None. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void FLASH_Lock(void) -{ - FLASH->CR |= FLASH_CR_LOCK; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Unlocks the FLASH Program Erase Controller. -/// @note This function can be used for all MM32 devices. -/// @param None. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void FLASH_Unlock() -{ - FLASH->KEYR = FLASH_KEY1; - FLASH->KEYR = FLASH_KEY2; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enable to program the FLASH Option Byte. -/// @note This function can be used for all MM32 devices. -/// @param None. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void FLASH_OPTB_Enable(void) -{ - FLASH->OPTKEYR = FLASH_KEY1; - FLASH->OPTKEYR = FLASH_KEY2; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Erases a specified FLASH page. -/// @note This function can be used for all MM32 devices. -/// @param page_address: The page address to be erased. -/// @retval FLASH Status: The returned value can be: FLASH_BUSY, -/// FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. -//////////////////////////////////////////////////////////////////////////////// -FLASH_Status FLASH_ErasePage(u32 page_address) -{ - FLASH->CR |= FLASH_CR_PER; - FLASH->AR = page_address; - FLASH->CR |= FLASH_CR_STRT; - return FLASH_WaitForLastOperation(EraseTimeout); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Erases all FLASH pages. -/// @note This function can be used for all MM32 devices. -/// @param None. -/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, -/// FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. -//////////////////////////////////////////////////////////////////////////////// -FLASH_Status FLASH_EraseAllPages() -{ - FLASH->AR = FLASH_BASE; - FLASH->CR |= (FLASH_CR_MER | FLASH_CR_STRT); - return FLASH_WaitForLastOperation(EraseTimeout); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Erases the FLASH option bytes. -/// @note This function can be used for all MM32 devices. -/// @param None. -/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, -/// FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. -//////////////////////////////////////////////////////////////////////////////// -FLASH_Status FLASH_EraseOptionBytes() -{ - FLASH_OPTB_Enable(); - FLASH->AR = OB_BASE; - FLASH->CR |= (FLASH_CR_OPTER | FLASH_CR_STRT); - return FLASH_WaitForLastOperation(EraseTimeout); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Programs a half word at a specified address. -/// @note This function can be used for all MM32 devices. -/// @param address: specifies the address to be programmed. -/// @param data: specifies the data to be programmed. -/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, -/// FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. -//////////////////////////////////////////////////////////////////////////////// -FLASH_Status FLASH_ProgramHalfWord(u32 address, u16 data) -{ - FLASH->CR |= FLASH_CR_PG; - - *(vu16*)address = data; - - - return FLASH_WaitForLastOperation(ProgramTimeout); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Programs a word at a specified address. -/// @note This function can be used for all MM32 devices. -/// @param address: specifies the address to be programmed. -/// @param data: specifies the data to be programmed. -/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, -/// FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. -//////////////////////////////////////////////////////////////////////////////// -FLASH_Status FLASH_ProgramWord(u32 address, u32 data) -{ - FLASH_Status ret = FLASH_ProgramHalfWord(address, data); - if (ret == FLASH_COMPLETE) { - ret = FLASH_ProgramHalfWord(address + 2, data >> 16); - } - return ret; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Programs a byte at a specified Option Byte Data address. -/// @note This function can be used for all MM32 devices. -/// @param address: specifies the address to be programmed. -/// This parameter can be 0x1FFFF804 or 0x1FFFF806. -/// @param data: specifies the data to be programmed. -/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, -/// FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. -//////////////////////////////////////////////////////////////////////////////// -FLASH_Status FLASH_ProgramOptionByteData(u32 address, u8 data) -{ - FLASH_Status ret; - __IO u16 temp; - FLASH_OPTB_Enable(); - FLASH->CR |= FLASH_CR_OPTPG; - temp = (u16)(~data); - temp = (temp << 8) & 0xFF00; - temp = temp | (u16)data; - address = address & (~0x1); - *(vu16*)address = temp; - ret = FLASH_WaitForLastOperation(ProgramTimeout); - - return ret; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Programs a half word at a specified Option Byte Data address. -/// @note This function can be used for all MM32 devices. -/// @param address: specifies the address to be programmed. -/// This parameter can be 0x1FFFF804 or 0x1FFFF806. -/// @param data: specifies the data to be programmed. -/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, -/// FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. -//////////////////////////////////////////////////////////////////////////////// -FLASH_Status FLASH_ProgramOptionHalfWord(u32 address, u16 data) -{ - FLASH_Status ret; - FLASH_OPTB_Enable(); - FLASH->CR |= FLASH_CR_OPTPG; - *(vu16*)address = data; - ret = FLASH_WaitForLastOperation(ProgramTimeout); - - return ret; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Read protection for the specified address -/// @note This function can be used for all MM32 devices. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -FLASH_Status FLASH_ProgramProtect(u32 address, u16 data) -{ - return FLASH_ProgramOptionHalfWord(address, data); - -// FLASH_Status ret; -// ret = FLASH_ProgramOptionHalfWord(address, 0x7F80); -// -// if (ret == FLASH_COMPLETE) { -// ret = FLASH_ProgramOptionHalfWord(address + 2, 0xFF00); -// } -// return ret; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Write protection for the specified address -/// @note This function can be used for all MM32 devices. -/// @param page: specifies the address of the pages to be write -/// protected. -/// This parameter is (0x01 << ((Absolute address - 0x08000000)/0x1000)) -/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, -/// FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. -//////////////////////////////////////////////////////////////////////////////// -FLASH_Status FLASH_EnableWriteProtection(u32 page) -{ - FLASH_Status ret; - u8 i; - for (i = 0; i < 4; i++) { - ret = FLASH_ProgramOptionHalfWord((OB_BASE + 8 + i * 2), ~(page >> (i * 8))); - if (ret != FLASH_COMPLETE) { - break; - } - } - return ret; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. -/// @note This function can be used for all MM32 devices. -/// @param ob_iwdg: Selects the IWDG mode -/// @param ob_stop: Reset event when entering STOP mode. -/// @param standby: Reset event when entering Standby mode. -/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, -/// FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. -//////////////////////////////////////////////////////////////////////////////// -FLASH_Status FLASH_UserOptionByteConfig(OB_IWDG_TypeDef ob_iwdg, OB_STOP_TypeDef ob_stop, OB_STDBY_TypeDef standby) -{ - FLASH_OPTB_Enable(); - FLASH->CR |= FLASH_CR_OPTPG; - OB->USER = ob_iwdg; - OB->USER |= ob_stop; - OB->USER |= standby; - OB->USER |= 0xF8; - // OB->USER = iwdg | stop | stdby | 0xF8; - return FLASH_WaitForLastOperation(ProgramTimeout); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Returns the FLASH User Option Bytes values. -/// @note This function can be used for all MM32 devices. -/// @param None. -/// @retval The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1) -/// and RST_STDBY(Bit2). -//////////////////////////////////////////////////////////////////////////////// -u32 FLASH_GetUserOptionByte() -{ - return (FLASH->OBR >> 2); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Returns the FLASH Write Protection Option Bytes Register value. -/// @note This function can be used for all MM32 devices. -/// @param None. -/// @retval The FLASH Write Protection Option Bytes Register value. -//////////////////////////////////////////////////////////////////////////////// -u32 FLASH_GetWriteProtectionOptionByte() -{ - return (FLASH->WRPR); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Checks whether the FLASH Prefetch Buffer status is set or not. -/// @note This function can be used for all MM32 devices. -/// @param None. -/// @retval FLASH Prefetch Buffer Status (SET or RESET). -//////////////////////////////////////////////////////////////////////////////// -FlagStatus FLASH_GetPrefetchBufferStatus(void) -{ - return (FLASH->ACR & FLASH_ACR_PRFTBS) ? SET : RESET; -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the specified FLASH interrupts. -/// @note This function can be used for all MM32 devices. -/// @param interrupt: specifies the FLASH interrupt sources to be enabled or -/// disabled. -/// @param state: new state of the specified Flash interrupts. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void FLASH_ITConfig(FLASH_IT_TypeDef interrupt, FunctionalState state) -{ - (state) ? (FLASH->CR |= interrupt) : (FLASH->CR &= ~interrupt); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Checks whether the specified FLASH flag is set or not. -/// @note This function can be used for all MM32 devices. -/// @param flag: specifies the FLASH flags to clear. -/// This parameter can be one of the following values: -/// @arg FLASH_FLAG_BSY: FLASH Busy flag -/// @arg FLASH_FLAG_PGERR: FLASH Program error flag -/// @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag -/// @arg FLASH_FLAG_EOP: FLASH End of Operation flag -/// @arg FLASH_FLAG_OPTERR: FLASH Option Byte error flag -/// @retval The new state of FLASH_FLAG (SET or RESET). -//////////////////////////////////////////////////////////////////////////////// -FlagStatus FLASH_GetFlagStatus(u16 flag) -{ - return ((flag == FLASH_FLAG_OPTERR) ? (FLASH->OBR & FLASH_FLAG_OPTERR) : (FLASH->SR & flag)) ? SET : RESET; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Clears the FLASH's pending flags. -/// @note This function can be used for all MM32 devices. -/// @param flag: specifies the FLASH flags to clear. -/// This parameter can be any combination of the following values: -/// @arg FLASH_FLAG_PGERR: FLASH Program error flag -/// @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag -/// @arg FLASH_FLAG_EOP: FLASH End of Operation flag -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void FLASH_ClearFlag(u16 flag) -{ - FLASH->SR = flag; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Returns the FLASH Status. -/// @note This function can be used for all MM32 devices. -/// @param None. -/// @retval FLASH Status: The returned value can be: FLASH_BUSY, -/// FLASH_ERROR_PG, FLASH_ERROR_WRP or FLASH_COMPLETE. -//////////////////////////////////////////////////////////////////////////////// -FLASH_Status FLASH_GetStatus() -{ - return (FLASH_Status)((FLASH->SR & FLASH_FLAG_BSY)) - ? FLASH_BUSY - : ((FLASH->SR & FLASH_FLAG_PGERR) ? FLASH_ERROR_PG - : ((FLASH->SR & FLASH_FLAG_WRPRTERR) ? FLASH_ERROR_WRP : FLASH_COMPLETE)); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Waits for a Flash operation to complete or a TIMEOUT to occur. -/// @note This function can be used for all MM32 devices -/// @param time_out: FLASH programming time_out -/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, -/// FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. -//////////////////////////////////////////////////////////////////////////////// -FLASH_Status FLASH_WaitForLastOperation(u32 time_out) -{ - u32 i; - FLASH_Status ret; - do { - ret = FLASH_GetStatus(); - time_out--; - for (i = 0xFF; i != 0; i--) - ; - } while ((ret == FLASH_BUSY) && (time_out != 0x00)); - - FLASH->CR = 0; - FLASH->SR = FLASH_SR_EOP | FLASH_SR_WRPRTERR | FLASH_SR_PGERR; - return (FLASH_Status)((time_out == 0x00) ? FLASH_TIMEOUT : ret); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Erases a specified FLASH page. -/// @note This function can be used for all MM32 devices. -/// @param Page_Address: The page address to be erased. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void exFLASH_EraseEE(u32 page_address) -{ - FLASH_Unlock(); - FLASH_ErasePage(page_address); - FLASH_Lock(); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Programs a buffer at a specified address. -/// @note This function can be used for all MM32 devices. -/// @param *buf: the pointer of the buffer to be programmed. -/// @param addr: specifies the address to be programmed. -/// @param len: the number of bytes in the buffer. -/// This parameter can only be even. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void exFLASH_ProgramEE(u16* buf, u32 addr, u16 len) -{ - u16 i; - FLASH_Unlock(); - for (i = 0; i < len / 2; i++) { - FLASH_ProgramHalfWord(addr, *buf); - addr += 2; - buf++; - } - FLASH_Lock(); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Determine if the data that at the ptr address with the length is len -/// is empty. -/// @note This function can be used for all MM32 devices. -/// @param *ptr: the pointer of the starting address. -/// @param len: the number of bytes. -/// This parameter can only be even. -/// @retval 1 presents the data is empty, -/// 0 presents the data has been written. -//////////////////////////////////////////////////////////////////////////////// -u8 exFLASH_FindEmpty(u16* ptr, u16 len) -{ - u16 i; - for (i = 0; i < (len / 2); i++) { - if (*(ptr + i) != 0xffff) - return 0; - } - return 1; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Locate the writable area on the specified address. -/// @note This function can be used for all MM32 devices. -/// @param page_address: specifies the beginning of the EEprom. -/// The EEprom can be some continuously pages in the flash. -/// @param len: the number of bytes to be written. -/// This parameter can only be even. -/// @retval the pointer of the starting address. -//////////////////////////////////////////////////////////////////////////////// -void* exFLASH_Locate(u32 page_address, u16 len) -{ - u16 i; - u16* ptr = (u16*)page_address; - for (i = 0; i < (0x0800 / len); i++) { - if (exFLASH_FindEmpty(ptr, len)) { - if (i == 0) - return 0; - break; - } - ptr += len / 2; - } - return ptr; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Programs a buffer at a specified address. -/// @note This function can be used for all MM32 devices. -/// @param *buf: the pointer of the buffer to be programmed. -/// @param page_address: specifies the beginning of the EEprom. -/// The EEprom can be some continuously pages in the flash. -/// @param len: the number of bytes in the buffer. -/// This parameter can only be even. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void exFLASH_WriteEE(u16* buf, u32 page_address, u16 len) -{ - u16* ptr = exFLASH_Locate(page_address, len); - if (ptr == 0) { - exFLASH_EraseEE(page_address + 0x000); - exFLASH_EraseEE(page_address + 0x400); - exFLASH_ProgramEE(buf, page_address, len); - } - else { - if (ptr == (u16*)(page_address + ((0x0400 / len) - 1) * len)) { - exFLASH_EraseEE(page_address + 0x400); - exFLASH_ProgramEE(buf, (u32)ptr, len); - } - else if (ptr == (u16*)(page_address + 0x0800)) { - exFLASH_EraseEE(page_address + 0x000); - exFLASH_ProgramEE(buf, (u32)page_address, len); - } - else { - exFLASH_ProgramEE(buf, (u32)ptr, len); - } - } -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Read the beginning address of the last written data. -/// @note This function can be used for all MM32 devices. -/// @param page_address: specifies the beginning of the EEprom. -/// The EEprom can be some continuously pages in the flash. -/// @param len: the number of bytes have been written. -/// This parameter can only be even. -/// @retval the beginning address of the last written data. -/// 0 presents that this is the first time to use this as EEprom. -//////////////////////////////////////////////////////////////////////////////// -void* exFLASH_ReadEE(u32 page_address, u16 len) -{ - u16* ptr = exFLASH_Locate(page_address, len); - return (ptr == 0) ? 0 : (ptr - len / 2); -} - -/// @} - -/// @} - -/// @} diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_fsmc.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_fsmc.c deleted file mode 100644 index b4b665a0b..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_fsmc.c +++ /dev/null @@ -1,124 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_fsmc.c -/// @author AE TEAM -/// @brief THIS FILE PROVIDES ALL THE FSMC FIRMWARE FUNCTIONS. -/// Interface with SRAM, PSRAM, NOR memories -/// Interrupts and flags management -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#define _HAL_FSMC_C_ - -// Files includes -#include "reg_rcc.h" -#include "reg_syscfg.h" -#include "hal_fsmc.h" - - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup FSMC_HAL -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup FSMC_Exported_Functions -/// @{ - - -void FSMC_NORSRAMStructInit(FSMC_InitTypeDef* init_struct) -{ - init_struct->FSMC_Mode = FSMC_Mode_NorFlash; - init_struct->FSMC_AddrDataMode = FSMC_AddrDataDeMUX; - - init_struct->FSMC_TimingRegSelect = FSMC_TimingRegSelect_0; - init_struct->FSMC_MemSize = FSMC_MemSize_64MB; - init_struct->FSMC_MemType = FSMC_MemType_NorSRAM; -} -void FSMC_NORSRAM_BankStructInit(FSMC_NORSRAM_Bank_InitTypeDef* init_struct) -{ - - init_struct->FSMC_SMReadPipe = 0; - init_struct->FSMC_ReadyMode = 0; - init_struct->FSMC_WritePeriod = 0x2; - init_struct->FSMC_WriteHoldTime = 1; - init_struct->FSMC_AddrSetTime = 3; - init_struct->FSMC_ReadPeriod = 0x1; - init_struct->FSMC_DataWidth = FSMC_DataWidth_16bits; -} -void FSMC_NORSRAMInit(FSMC_InitTypeDef* init_struct) -{ - SYSCFG->CFGR &= ~(SYSCFG_CFGR_FSMC_MODE | SYSCFG_CFGR_FSMC_AF_ADDR | SYSCFG_CFGR_FSMC_SYNC_EN); - SYSCFG->CFGR |= (u32)init_struct->FSMC_Mode | \ - (u32)init_struct->FSMC_AddrDataMode; - - FSMC->SMSKR = (u32)init_struct->FSMC_TimingRegSelect | \ - (u32)init_struct->FSMC_MemSize | \ - (u32)init_struct->FSMC_MemType; -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Initialize the FSMC_NORSRAM Timing according to the specified -/// parameters in the FSMC_NORSRAM_TimingTypeDef -/// @param FSMC_Bank_InitStruct: Timing Pointer to NORSRAM Timing structure -/// @param Bank: NORSRAM bank number -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void FSMC_NORSRAM_Bank_Init(FSMC_NORSRAM_Bank_InitTypeDef* FSMC_Bank_InitStruct, FSMC_NORSRAM_BANK_TypeDef bank) -{ - // Set FSMC_NORSRAM device timing parameters - if(bank == FSMC_NORSRAM_BANK0) { - FSMC->SMTMGR_SET0 = (u32)(FSMC_Bank_InitStruct->FSMC_SMReadPipe << FSMC_SMTMGR_SET_SM_READ_PIPE_Pos) | \ - (u32)(FSMC_Bank_InitStruct->FSMC_ReadyMode << FSMC_SMTMGR_SET_READ_MODE_Pos) | \ - (u32)(FSMC_Bank_InitStruct->FSMC_WritePeriod << FSMC_SMTMGR_SET_T_WP_Pos) | \ - (u32)(FSMC_Bank_InitStruct->FSMC_WriteHoldTime << FSMC_SMTMGR_SET_T_WR_Pos) | \ - (u32)(FSMC_Bank_InitStruct->FSMC_AddrSetTime << FSMC_SMTMGR_SET_T_AS_Pos) | \ - (u32)(FSMC_Bank_InitStruct->FSMC_ReadPeriod << FSMC_SMTMGR_SET_T_RC_Pos ) ; - FSMC->SMCTLR &= ~FSMC_SMCTLR_SM_DATA_WIDTH_SET0; - FSMC->SMCTLR |= (FSMC_Bank_InitStruct->FSMC_DataWidth) << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos; - } - else if(bank == FSMC_NORSRAM_BANK1) { - FSMC->SMTMGR_SET1 = (u32)(FSMC_Bank_InitStruct->FSMC_SMReadPipe << FSMC_SMTMGR_SET_SM_READ_PIPE_Pos) | \ - (u32)(FSMC_Bank_InitStruct->FSMC_ReadyMode << FSMC_SMTMGR_SET_READ_MODE_Pos) | \ - (u32)(FSMC_Bank_InitStruct->FSMC_WritePeriod << FSMC_SMTMGR_SET_T_WP_Pos) | \ - (u32)(FSMC_Bank_InitStruct->FSMC_WriteHoldTime << FSMC_SMTMGR_SET_T_WR_Pos) | \ - (u32)(FSMC_Bank_InitStruct->FSMC_AddrSetTime << FSMC_SMTMGR_SET_T_AS_Pos) | \ - (u32)(FSMC_Bank_InitStruct->FSMC_ReadPeriod << FSMC_SMTMGR_SET_T_RC_Pos ) ; - FSMC->SMCTLR &= ~FSMC_SMCTLR_SM_DATA_WIDTH_SET1; - FSMC->SMCTLR |= (FSMC_Bank_InitStruct->FSMC_DataWidth) << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos; - } - else if(bank == FSMC_NORSRAM_BANK2) { - FSMC->SMTMGR_SET2 = (u32)(FSMC_Bank_InitStruct->FSMC_SMReadPipe << FSMC_SMTMGR_SET_SM_READ_PIPE_Pos) | \ - (u32)(FSMC_Bank_InitStruct->FSMC_ReadyMode << FSMC_SMTMGR_SET_READ_MODE_Pos) | \ - (u32)(FSMC_Bank_InitStruct->FSMC_WritePeriod << FSMC_SMTMGR_SET_T_WP_Pos) | \ - (u32)(FSMC_Bank_InitStruct->FSMC_WriteHoldTime << FSMC_SMTMGR_SET_T_WR_Pos) | \ - (u32)(FSMC_Bank_InitStruct->FSMC_AddrSetTime << FSMC_SMTMGR_SET_T_AS_Pos) | \ - (u32)(FSMC_Bank_InitStruct->FSMC_ReadPeriod << FSMC_SMTMGR_SET_T_RC_Pos ) ; - FSMC->SMCTLR &= ~FSMC_SMCTLR_SM_DATA_WIDTH_SET2; - FSMC->SMCTLR |= (FSMC_Bank_InitStruct->FSMC_DataWidth) << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos; - } -} - - - - -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_gpio.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_gpio.c deleted file mode 100644 index 4363338f3..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_gpio.c +++ /dev/null @@ -1,344 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_gpio.c -/// @author AE TEAM -/// @brief THIS FILE PROVIDES ALL THE GPIO FIRMWARE FUNCTIONS. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#define _HAL_GPIO_C_ - -// Files includes -#include "reg_exti.h" -#include "hal_rcc.h" -#include "hal_gpio.h" - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup GPIO_HAL -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup GPIO_Exported_Functions -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Deinitializes the gpio peripheral registers to their default reset -/// values. -/// @param gpio: select the GPIO peripheral. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void GPIO_DeInit(GPIO_TypeDef* gpio) -{ - switch (*(vu32*)&gpio) { - case (u32)GPIOA: - RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOA, DISABLE); - break; - case (u32)GPIOB: - RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOB, DISABLE); - break; - case (u32)GPIOC: - RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOC, DISABLE); - break; - case (u32)GPIOD: - RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOD, DISABLE); - break; - case (u32)GPIOE: - RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOE, DISABLE); - break; - default: - break; - } -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Deinitializes the Alternate Functions (remap, event control -/// and EXTI configuration) registers to their default reset values. -/// @param None. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void GPIO_AFIODeInit() -{ - GPIOA->AFRL = 0xFFFFFFFF; - GPIOA->AFRH = 0xF00FFFFF; // PA14:SWCLK, PA13:PSWDIO - GPIOB->AFRL = 0xFFFFFFFF; - GPIOB->AFRH = 0xFFFFFFFF; - GPIOC->AFRL = 0xFFFFFFFF; - GPIOC->AFRH = 0xFFFFFFFF; - GPIOD->AFRL = 0xFFFFFFFF; - GPIOD->AFRH = 0xFFFFFFFF; - GPIOE->AFRL = 0xFFFFFFFF; - GPIOE->AFRH = 0xFFFFFFFF; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Initializes the gpio peripheral according to the specified -/// parameters in the init_struct. -/// @param gpio: select the GPIO peripheral. -/// @param init_struct: pointer to a GPIO_InitTypeDef structure that -/// contains the configuration information for the specified GPIO -/// peripheral. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void GPIO_Init(GPIO_TypeDef* gpio, GPIO_InitTypeDef* init_struct) -{ - u8 idx; - u8 i; - u32 tmp; - __IO u32* reg ; - - // 1x - u32 dat = init_struct->GPIO_Mode & 0x0F; - if (init_struct->GPIO_Mode & 0x10) - dat |= init_struct->GPIO_Speed; - - // 0x - reg = &gpio->CRL; - for (i = 0; i < 8; i++) { - idx = i * 4; - if ((init_struct->GPIO_Pin) & (1 << i)) { - *reg = (*reg & ~(0xF << idx)) | (dat << idx); - } - } - - reg = &gpio->CRH; - tmp = init_struct->GPIO_Pin >> 8; - for (i = 0; i < 8; i++) { - idx = i * 4; - if (tmp & (1 << i)) { - *reg = (*reg & ~(0xF << idx)) | (dat << idx); - } - } - - // 2x,4x - if (init_struct->GPIO_Mode == GPIO_Mode_IPD) - gpio->BRR |= init_struct->GPIO_Pin; - else if (init_struct->GPIO_Mode == GPIO_Mode_IPU) - gpio->BSRR |= init_struct->GPIO_Pin; -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Fills each init_struct member with its default value. -/// @param init_struct : pointer to a GPIO_InitTypeDef structure -/// which will be initialized. -/// @retval : None -//////////////////////////////////////////////////////////////////////////////// -void GPIO_StructInit(GPIO_InitTypeDef* init_struct) -{ - // Reset GPIO init structure parameters values - init_struct->GPIO_Pin = GPIO_Pin_All; - init_struct->GPIO_Speed = GPIO_Speed_2MHz; - init_struct->GPIO_Mode = GPIO_Mode_FLOATING; -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Reads the input data of specified GPIO port pin. -/// @param gpio: select the GPIO peripheral. -/// @param pin: specifies the port pin to be read. -/// This parameter can be GPIO_Pin_x where x can be (0..15). -/// @retval The input port pin value. -//////////////////////////////////////////////////////////////////////////////// -bool GPIO_ReadInputDataBit(GPIO_TypeDef* gpio, u16 pin) -{ - return ((gpio->IDR & pin)) ? Bit_SET : Bit_RESET; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Reads all GPIO port pins input data. -/// @param gpio: select the GPIO peripheral. -/// @retval GPIO port input data value. -//////////////////////////////////////////////////////////////////////////////// -u16 GPIO_ReadInputData(GPIO_TypeDef* gpio) -{ - return gpio->IDR; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Reads the output data of specified GPIO port pin. -/// @param gpio: select the GPIO peripheral. -/// @param pin: specifies the port bit to be read. -/// This parameter can be GPIO_Pin_x where x can be (0..15). -/// @retval The output port pin value. -//////////////////////////////////////////////////////////////////////////////// -bool GPIO_ReadOutputDataBit(GPIO_TypeDef* gpio, u16 pin) -{ - return (gpio->ODR & pin) ? Bit_SET : Bit_RESET; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Reads all GPIO port pins output data. -/// @param gpio: select the GPIO peripheral. -/// @retval GPIO port output data value. -//////////////////////////////////////////////////////////////////////////////// -u16 GPIO_ReadOutputData(GPIO_TypeDef* gpio) -{ - return gpio->ODR; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Sets the selected GPIO port pin. -/// @param gpio: where x can be (A..D) to select the GPIO peripheral. -/// @param pin: specifies the port pins to be written. -/// This parameter can be any combination of GPIO_Pin_x where x can be -/// (0..15). -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void GPIO_SetBits(GPIO_TypeDef* gpio, u16 pin) -{ - gpio->BSRR = pin; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Clears the selected GPIO port bit. -/// @param gpio: where x can be (A..D) to select the GPIO peripheral. -/// @param pin: specifies the port pins to be written. -/// This parameter can be any combination of GPIO_Pin_x where x can be -/// (0..15). -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void GPIO_ResetBits(GPIO_TypeDef* gpio, u16 pin) -{ - gpio->BRR = pin; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Sets or clears the selected GPIO port pin. -/// @param gpio: select the GPIO peripheral. -/// @param pin: specifies the port bit to be written. -/// This parameter can be one of GPIO_Pin_x where x can be (0..15). -/// @param value: specifies the value to be written to the selected bit. -/// This parameter can be one of the BitAction enum values: -/// @arg Bit_RESET: to clear the port pin -/// @arg Bit_SET: to set the port pin -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void GPIO_WriteBit(GPIO_TypeDef* gpio, u16 pin, BitAction value) -{ - (value) ? (gpio->BSRR = pin) : (gpio->BRR = pin); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Writes data to all GPIO port pins. -/// @param gpio: where x can be (A..D) to select the GPIO peripheral. -/// @param value: specifies the value to be written to the port output data -/// register. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void GPIO_Write(GPIO_TypeDef* gpio, u16 value) -{ - gpio->ODR = value; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Locks GPIO Pins configuration. -/// @param gpio: to select the GPIO peripheral. -/// @param pin: specifies the port bit to be written. -/// This parameter can be any combination of GPIO_Pin_x where x can be -/// (0..15). -/// @param state: new lock state of the port pin. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void GPIO_PinLock(GPIO_TypeDef* gpio, u16 pin, FunctionalState state) -{ - (state) ? (gpio->LCKR |= pin) : (gpio->LCKR &= ~pin); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Locks GPIO Pins configuration registers until next system reset. -/// @param gpio: to select the GPIO peripheral. -/// @param pin: specifies the port bit to be written. -/// This parameter can be any combination of GPIO_Pin_x where x can be -/// (0..15). -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void GPIO_PinLockConfig(GPIO_TypeDef* gpio, u16 pin) -{ - gpio->LCKR = GPIO_LCKR_LCKK | pin; - gpio->LCKR = pin; - gpio->LCKR = GPIO_LCKR_LCKK | pin; - gpio->LCKR; - gpio->LCKR; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the port pin remapping. -/// @param remap: selects the pin to remap. -/// @param mask: the corresponding remapping mask of the remapping pin. -/// @param state: new state of the port pin remapping. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Writes data to the specified GPIO data port. -/// @param gpio: select the GPIO peripheral. -/// @param pin: specifies the pin for the Alternate function. -/// This parameter can be GPIO_PinSourcex where x can be (0..15) for -/// GPIOA, GPIOB, GPIOD and (0..12) for GPIOC . -/// @param alternate_function: selects the pin to used as Alternate function. -/// This parameter can be the GPIO_AF_x where x can be (0..7). -/// @note The pin should be used for Digital IP. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void GPIO_PinAFConfig(GPIO_TypeDef* gpio, u8 pin, u8 alternate_function) -{ - u8 shift = (pin & 0x07) * 4; - u32* ptr = (pin < 8) ? (u32*)&gpio->AFRL : (u32*)&gpio->AFRH; - *ptr = (*ptr & ~(0x0F << shift)) | (alternate_function << shift); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Set the remap function and AF function of the GPIO pin. -/// @param gpio:select the GPIO peripheral. -/// @param pin: specifies the pin for the Alternate function. -/// This parameter can be GPIO_Pin_x where x can be (0..15) for -/// GPIOA, GPIOB, GPIOD and (0..12) for GPIOC . -/// @param remap: selects the pin to remap. -/// @param alternate_function: selects the pin to used as Alternate function. -/// This parameter can be the GPIO_AF_x where x can be (0..7). -/// @note The pin should be used for Digital IP. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void exGPIO_PinAFConfig(GPIO_TypeDef* gpio, u16 pin, s32 remap, s8 alternate_function) -{ - u8 i; - u8 shift; - u32* ptr; - - if (alternate_function >= 0) { - for (i = 0; i < 32; i++) { - if (pin & 0x01) { - pin = i; - break; - } - pin >>= 1; - } - - shift = (pin & 0x07) * 4; - ptr = (pin < 8) ? (u32*)&gpio->AFRL : (u32*)&gpio->AFRH; - *ptr = (*ptr & ~(0x0F << shift)) | (alternate_function << shift); - } -} - - -/// @} - -/// @} - -/// @} - diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_i2c.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_i2c.c deleted file mode 100644 index 855236a63..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_i2c.c +++ /dev/null @@ -1,526 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_i2c.c -/// @author AE TEAM -/// @brief THIS FILE PROVIDES ALL THE I2C FIRMWARE FUNCTIONS. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#define _HAL_I2C_C_ - -// Files includes -#include "hal_i2c.h" -#include "hal_rcc.h" - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup I2C_HAL -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup I2C_Exported_Functions -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Deinitializes the i2c peripheral registers to their default -/// reset values. -/// @param i2c: where n can be 1 or 2 to select the I2C peripheral. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void I2C_DeInit(I2C_TypeDef* i2c) -{ - switch (*(vu32*)&i2c) { - case (u32)I2C1: // I2C1_BASE: - exRCC_APB1PeriphReset(RCC_APB1ENR_I2C1); - break; - case (u32)I2C2: // I2C2_BASE: - exRCC_APB1PeriphReset(RCC_APB1ENR_I2C2); - break; - default: - break; - } -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Initializes the i2c peripheral according to the specified -/// parameters in the init_struct. -/// @param i2c: select the I2C peripheral. -/// @param init_struct: pointer to a I2C_InitTypeDef structure that -/// contains the configuration information for the specified -/// I2C peripheral. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void I2C_Init(I2C_TypeDef* i2c, I2C_InitTypeDef* init_struct) -{ - u32 pclk1 = HSI_VALUE; - u32 minSclLowTime = 0; - u32 i2cPeriod = 0; - u32 pclk1Period = 0; - - - i2c->IC_ENABLE &= ~I2C_ENR_ENABLE; - - - pclk1 = RCC_GetPCLK1Freq(); - pclk1Period = 1000000000 / pclk1; - i2cPeriod = 1000000000 / init_struct->I2C_ClockSpeed; - - minSclLowTime = pclk1 / init_struct->I2C_ClockSpeed ; - i2cPeriod = 82 / pclk1Period; - - if (init_struct->I2C_ClockSpeed <= 100000) { - i2c->IC_SS_SCL_LCNT = (minSclLowTime - 13 - i2cPeriod) / 2; - i2c->IC_SS_SCL_HCNT = (minSclLowTime - 13 - i2cPeriod - i2c->IC_SS_SCL_LCNT); - } - else { - i2c->IC_FS_SCL_LCNT = (minSclLowTime - 13 - i2cPeriod ) / 2 + 4; - i2c->IC_FS_SCL_HCNT = (minSclLowTime - 13 - i2c->IC_FS_SCL_LCNT - i2cPeriod); - } - - i2c->IC_CON &= ~(I2C_CR_EMPINT | \ - I2C_CR_SLAVEDIS | \ - I2C_CR_REPEN | \ - I2C_CR_MASTER10 | \ - I2C_CR_SLAVE10 | \ - I2C_CR_FAST | \ - I2C_CR_MASTER); - - i2c->IC_CON = I2C_CR_EMPINT | \ - I2C_CR_REPEN | \ - ((init_struct->I2C_Speed == I2C_CR_FAST) ? I2C_CR_FAST : I2C_CR_STD) | \ - ((init_struct->I2C_Mode) ? I2C_CR_MASTER : 0x00); - i2c->IC_INTR_MASK &= INTR_MASK; - - i2c->IC_RX_TL = 0x00; - i2c->IC_TX_TL = 0x00; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Fills each init_struct member with its default value. -/// @param init_struct: pointer to an I2C_InitTypeDef structure -/// which will be initialized. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void I2C_StructInit(I2C_InitTypeDef* init_struct) -{ - init_struct->I2C_Mode = I2C_CR_MASTER; - init_struct->I2C_OwnAddress = I2C_OWN_ADDRESS; - init_struct->I2C_Speed = I2C_CR_STD; - init_struct->I2C_ClockSpeed = 100000; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the specified I2C peripheral. -/// @param i2c: select the I2C peripheral. -/// @param state: new state of the i2c peripheral. This parameter -/// can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void I2C_Cmd(I2C_TypeDef* i2c, FunctionalState state) -{ - (state) ? (i2c->IC_ENABLE |= I2C_ENR_ENABLE) : (i2c->IC_ENABLE &= ~I2C_ENR_ENABLE); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the specified I2C DMA requests. -/// @param i2c: select the I2C peripheral. -/// @param state: new state of the I2C DMA transfer. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void I2C_DMACmd(I2C_TypeDef* i2c, FunctionalState state) -{ - if (state) { - if (I2C_DMA_DIR == TDMAE_SET) - i2c->IC_DMA_CR |= TDMAE_SET; - - else - i2c->IC_DMA_CR |= RDMAE_SET; - } - else - i2c->IC_DMA_CR &= ~(I2C_DMA_RXEN | I2C_DMA_TXEN); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Generates i2c communication START condition. -/// @param i2c: select the I2C peripheral. -/// @param state: new state of the I2C START condition generation. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void I2C_GenerateSTART(I2C_TypeDef* i2c, FunctionalState state) -{ - (state) ? (i2c->IC_CON |= I2C_CR_REPEN) : (i2c->IC_CON &= ~I2C_CR_REPEN); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Generates i2c communication STOP condition. -/// @param i2c: select the I2C peripheral. -/// @param state: new state of the I2C STOP condition generation. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void I2C_GenerateSTOP(I2C_TypeDef* i2c, FunctionalState state) -{ - u16 overTime = 3000; - - i2c->IC_ENABLE |= I2C_ENR_ABORT; - - while (i2c->IC_ENABLE & I2C_ENR_ABORT) { - if (overTime-- == 0) - break; - } - i2c->IC_CLR_TX_ABRT; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the specified I2C own address2. -/// @param i2c: select the I2C peripheral. -/// @param addr: specifies the 7bit I2C own address2. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void I2C_OwnAddress2Config(I2C_TypeDef* i2c, u8 addr) -{ - MODIFY_REG(i2c->IC_TAR, (u16)I2C_TAR_ADDR, (u16)(addr >> 1)); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the specified I2C dual addressing mode. -/// @param i2c: select the I2C peripheral. -/// @param state: new state of the I2C dual addressing mode. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void I2C_DualAddressCmd(I2C_TypeDef* i2c, FunctionalState state) -{ - (state) ? (i2c->IC_TAR |= IC_TAR_ENDUAL_Set) : (i2c->IC_TAR &= IC_TAR_ENDUAL_Reset); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the specified I2C general call feature. -/// @param i2c: select the I2C peripheral. -/// @param state: new state of the I2C General call. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void I2C_GeneralCallCmd(I2C_TypeDef* i2c, FunctionalState state) -{ - (state) ? (i2c->IC_TAR |= I2C_TAR_SPECIAL) : (i2c->IC_TAR &= ~I2C_TAR_SPECIAL); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the specified I2C interrupts. -/// @param i2c: select the I2C peripheral. -/// @param it: specifies the I2C interrupts sources to be enabled -/// or disabled. -/// This parameter can be any combination of the following values: -/// @arg I2C_IT_RX_UNDER : Rx Buffer is empty interrupt mask -/// @arg I2C_IT_RX_OVER : RX Buffer Overrun interrupt mask -/// @arg I2C_IT_RX_FULL : Rx buffer full interrupt mask -/// @arg I2C_IT_TX_OVER : TX Buffer Overrun interrupt mask -/// @arg I2C_IT_TX_EMPTY : TX_FIFO empty interrupt mask -/// @arg I2C_IT_RD_REQ : I2C work as slave or master interrupt mask -/// @arg I2C_IT_TX_ABRT : TX error interrupt mask(Master mode) -/// @arg I2C_IT_RX_DONE : Master not ack interrupt mask(slave mode) -/// @arg I2C_IT_ACTIVITY : I2C activity interrupt mask -/// @arg I2C_IT_STOP_DET : stop condition interrupt mask -/// @arg I2C_IT_START_DET : start condition interrupt mask -/// @arg I2C_IT_GEN_CALL : a general call address and ack interrupt mask -/// @param state: new state of the specified I2C interrupts. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void I2C_ITConfig(I2C_TypeDef* i2c, u16 it, FunctionalState state) -{ - if (it == I2C_IT_RX_FULL) - I2C_ReadCmd(i2c); - (state) ? SET_BIT(i2c->IC_INTR_MASK, it) : CLEAR_BIT(i2c->IC_INTR_MASK, (u16)it); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Sends a data byte through the i2c peripheral. -/// @param i2c: select the I2C peripheral. -/// @param dat: Byte to be transmitted.. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void I2C_SendData(I2C_TypeDef* i2c, u8 dat) -{ - i2c->IC_DATA_CMD = dat; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Returns the most recent received data by the i2c peripheral. -/// @param i2c: select the I2C peripheral. -/// @retval The value of the received data. -//////////////////////////////////////////////////////////////////////////////// -void I2C_ReadCmd(I2C_TypeDef* i2c) -{ - i2c->IC_DATA_CMD = I2C_DR_CMD; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Returns the most recent received data by the i2c peripheral. -/// @param i2c: select the I2C peripheral. -/// @retval The value of the received data. -//////////////////////////////////////////////////////////////////////////////// -u8 I2C_ReceiveData(I2C_TypeDef* i2c) -{ - I2C_CMD_DIR = 0; - return (u8)i2c->IC_DATA_CMD; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Transmits the address byte to select the slave device. -/// @param i2c: select the I2C peripheral. -/// @param addr: specifies the slave address which will be transmitted -/// @param dir: specifies whether the I2C device will be a -/// Transmitter or a Receiver. -/// This parameter can be one of the following values -/// @arg I2C_Direction_Transmitter: Transmitter mode -/// @arg I2C_Direction_Receiver: Receiver mode -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void I2C_Send7bitAddress(I2C_TypeDef* i2c, u8 addr, u8 dir) -{ - i2c->IC_TAR = addr >> 1; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Reads the specified I2C register and returns its value. -/// @param i2c: select the I2C peripheral. -/// @param reg: specifies the register to read. -/// This parameter can be one of the following values: -/// @retval The value of the read register. -//////////////////////////////////////////////////////////////////////////////// -u16 I2C_ReadRegister(I2C_TypeDef* i2c, u8 reg) -{ - return (*(vu16*)(*((u32*)&i2c) + reg)); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Returns the last i2c Event. -/// @param i2c: select the I2C peripheral. -/// @retval The last event -//////////////////////////////////////////////////////////////////////////////// -u32 I2C_GetLastEvent(I2C_TypeDef* i2c) -{ - return (u32)i2c->IC_RAW_INTR_STAT & FLAG_Mask; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Checks whether the last i2c Event is equal to the one passed -/// as parameter. -/// @param i2c: select the I2C peripheral. -/// @param event: specifies the event to be checked. -/// This parameter can be one of the following values: -/// @arg I2C_EVENT_RX_UNDER : Rx Buffer is empty event -/// @arg I2C_EVENT_RX_OVER : RX Buffer Overrun event -/// @arg I2C_EVENTT_RX_FULL : Rx buffer full event -/// @arg I2C_EVENT_TX_OVER : TX Buffer Overrun event -/// @arg I2C_EVENT_TX_EMPTY : TX_FIFO empty event -/// @arg I2C_EVENT_RD_REQ : I2C work as slave or master event -/// @arg I2C_EVENT_TX_ABRT : TX error event(Master mode) -/// @arg I2C_EVENT_RX_DONE : Master not ack event(slave mode) -/// @arg I2C_EVENT_ACTIVITY : I2C activity event -/// @arg I2C_EVENT_STOP_DET : stop condition event -/// @arg I2C_EVENT_START_DET: start condition event -/// @arg I2C_EVENT_GEN_CALL : a general call address and ack event -/// - SUCCESS: Last event is equal to the I2C_EVENT -/// - ERROR: Last event is different from the I2C_EVENT -//////////////////////////////////////////////////////////////////////////////// -ErrorStatus I2C_CheckEvent(I2C_TypeDef* i2c, u32 event) -{ - if ((event == I2C_EVENT_RX_FULL) && (I2C_CMD_DIR == 0)) { - i2c->IC_DATA_CMD = I2C_DR_CMD; - I2C_CMD_DIR = 1; - } - - return (ErrorStatus)((i2c->IC_RAW_INTR_STAT & event) == event); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Checks whether the specified I2C flag is set or not. -/// @param i2c: select the I2C peripheral. -/// @param flag: specifies the flag to check. -/// This parameter can be one of the following values: -/// @arg I2C_FLAG_RX_UNDER : Rx Buffer is empty flag -/// @arg I2C_FLAG_RX_OVER : RX Buffer Overrun flag -/// @arg I2C_FLAG_RX_FULL : Rx buffer full flag -/// @arg I2C_FLAG_TX_OVER : TX Buffer Overrun flag -/// @arg I2C_FLAG_TX_EMPTY : TX_FIFO empty flag -/// @arg I2C_FLAG_RD_REQ : I2C work as slave or master flag -/// @arg I2C_FLAG_TX_ABRT : TX error flag(Master mode) -/// @arg I2C_FLAG_RX_DONE : Master not ack flag(slave mode) -/// @arg I2C_FLAG_ACTIVITY : I2C activity flag -/// @arg I2C_FLAG_STOP_DET : stop condition flag -/// @arg I2C_FLAG_START_DET: start condition flag -/// @arg I2C_FLAG_GEN_CALL : a general call address and ack flag -/// @retval The new state of I2C_FLAG (SET or RESET). -//////////////////////////////////////////////////////////////////////////////// -FlagStatus I2C_GetFlagStatus(I2C_TypeDef* i2c, u32 flag) -{ - if (flag & 0x8000) - return ((i2c->IC_STATUS & flag) ? SET : RESET); - - if ((flag == I2C_FLAG_RX_FULL) && (I2C_CMD_DIR == 0)) { - i2c->IC_DATA_CMD = I2C_DR_CMD; - I2C_CMD_DIR = 1; - } - return (((i2c->IC_RAW_INTR_STAT & flag)) ? SET : RESET); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Clears the i2c's pending flags. -/// @param i2c: select the I2C peripheral. -/// @param flag: specifies the flag to clear. -/// This parameter can be any combination of the following values: -/// @arg I2C_FLAG_RX_UNDER : Rx Buffer is empty flag -/// @arg I2C_FLAG_RX_OVER : RX Buffer Overrun flag -/// @arg I2C_FLAG_RX_FULL : Rx buffer full flag -/// @arg I2C_FLAG_TX_OVER : TX Buffer Overrun flag -/// @arg I2C_FLAG_TX_EMPTY : TX_FIFO empty flag -/// @arg I2C_FLAG_RD_REQ : I2C work as slave or master flag -/// @arg I2C_FLAG_TX_ABRT : TX error flag(Master mode) -/// @arg I2C_FLAG_RX_DONE : Master not ack flag(slave mode) -/// @arg I2C_FLAG_ACTIVITY : I2C activity flag -/// @arg I2C_FLAG_STOP_DET : stop condition flag -/// @arg I2C_FLAG_START_DET: start condition flag -/// @arg I2C_FLAG_GEN_CALL : a general call address and ack flag -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void I2C_ClearFlag(I2C_TypeDef* i2c, u32 flag) -{ - if ((flag & I2C_FLAG_RX_UNDER) == I2C_FLAG_RX_UNDER) - i2c->IC_CLR_RX_UNDER; - if ((flag & I2C_FLAG_RX_OVER) == I2C_FLAG_RX_OVER) - i2c->IC_CLR_RX_OVER; - if ((flag & I2C_FLAG_TX_OVER) == I2C_FLAG_TX_OVER) - i2c->IC_CLR_TX_OVER; - if ((flag & I2C_FLAG_RD_REQ) == I2C_FLAG_RD_REQ) - i2c->IC_CLR_RD_REQ; - if ((flag & I2C_FLAG_TX_ABRT) == I2C_FLAG_TX_ABRT) - i2c->IC_CLR_TX_ABRT; - if ((flag & I2C_FLAG_RX_DONE) == I2C_FLAG_RX_DONE) - i2c->IC_CLR_RX_DONE; - if ((flag & I2C_FLAG_ACTIVITY) == I2C_FLAG_ACTIVITY) - i2c->IC_CLR_ACTIVITY; - if ((flag & I2C_FLAG_STOP_DET) == I2C_FLAG_STOP_DET) - i2c->IC_CLR_STOP_DET; - if ((flag & I2C_FLAG_START_DET) == I2C_FLAG_START_DET) - i2c->IC_CLR_START_DET; - if ((flag & I2C_FLAG_GEN_CALL) == I2C_FLAG_GEN_CALL) - i2c->IC_CLR_GEN_CALL; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Checks whether the specified I2C interrupt has occurred or not. -/// @param i2c: select the I2C peripheral. -/// @param it: specifies the interrupt source to check. -/// This parameter can be one of the following values: -/// @arg I2C_IT_RX_UNDER : Rx Buffer is empty interrupt -/// @arg I2C_IT_RX_OVER : RX Buffer Overrun interrupt -/// @arg I2C_IT_RX_FULL : Rx buffer full interrupt -/// @arg I2C_IT_TX_OVER : TX Buffer Overrun interrupt -/// @arg I2C_IT_TX_EMPTY : TX_FIFO empty interrupt -/// @arg I2C_IT_RD_REQ : I2C work as slave or master interrupt -/// @arg I2C_IT_TX_ABRT : TX error interrupt (Master mode) -/// @arg I2C_IT_RX_DONE : Master not ack interrupt (slave mode) -/// @arg I2C_IT_ACTIVITY : I2C activity interrupt -/// @arg I2C_IT_STOP_DET : stop condition interrupt -/// @arg I2C_IT_START_DET: start condition interrupt -/// @arg I2C_IT_GEN_CALL : a general call address and ack interrupt -/// @retval The new state of I2C_IT (SET or RESET). -//////////////////////////////////////////////////////////////////////////////// -ITStatus I2C_GetITStatus(I2C_TypeDef* i2c, u32 it) -{ - return ((i2c->IC_RAW_INTR_STAT & it) ? SET : RESET); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Clears the i2c interrupt pending bits. -/// @param i2c: select the I2C peripheral. -/// @param it: specifies the interrupt pending bit to clear. -/// This parameter can be any combination of the following values: -/// @arg I2C_IT_RX_UNDER : Rx Buffer is empty interrupt -/// @arg I2C_IT_RX_OVER : RX Buffer Overrun interrupt -/// @arg I2C_IT_RX_FULL : Rx buffer full interrupt -/// @arg I2C_IT_TX_OVER : TX Buffer Overrun interrupt -/// @arg I2C_IT_TX_EMPTY : TX_FIFO empty interrupt -/// @arg I2C_IT_RD_REQ : I2C work as slave or master interrupt -/// @arg I2C_IT_TX_ABRT : TX error interrupt (Master mode) -/// @arg I2C_IT_RX_DONE : Master not ack interrupt (slave mode) -/// @arg I2C_IT_ACTIVITY : I2C activity interrupt -/// @arg I2C_IT_STOP_DET : stop condition interrupt -/// @arg I2C_IT_START_DET: start condition interrupt -/// @arg I2C_IT_GEN_CALL : a general call address and ack interrupt -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void I2C_ClearITPendingBit(I2C_TypeDef* i2c, u32 it) -{ - if ((it & I2C_IT_RX_UNDER) == I2C_FLAG_RX_UNDER) - i2c->IC_CLR_RX_UNDER; - if ((it & I2C_IT_RX_OVER) == I2C_FLAG_RX_OVER) - i2c->IC_CLR_RX_OVER; - if ((it & I2C_IT_TX_OVER) == I2C_FLAG_TX_OVER) - i2c->IC_CLR_TX_OVER; - if ((it & I2C_IT_RD_REQ) == I2C_FLAG_RD_REQ) - i2c->IC_CLR_RD_REQ; - if ((it & I2C_IT_TX_ABRT) == I2C_FLAG_TX_ABRT) - i2c->IC_CLR_TX_ABRT; - if ((it & I2C_IT_RX_DONE) == I2C_FLAG_RX_DONE) - i2c->IC_CLR_RX_DONE; - if ((it & I2C_IT_ACTIVITY) == I2C_FLAG_ACTIVITY) - i2c->IC_CLR_ACTIVITY; - if ((it & I2C_IT_STOP_DET) == I2C_FLAG_STOP_DET) - i2c->IC_CLR_STOP_DET; - if ((it & I2C_IT_START_DET) == I2C_FLAG_START_DET) - i2c->IC_CLR_START_DET; - if ((it & I2C_IT_GEN_CALL) == I2C_FLAG_GEN_CALL) - i2c->IC_CLR_GEN_CALL; -} - -//////////////////////////////////////////////////////////////////////////////// -// -// New Function Interface -// -//////////////////////////////////////////////////////////////////////////////// - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures slave address. -/// @param i2c: select the I2C peripheral. -/// @param addr: specifies the slave address which will be transmitted -/// This parameter can be one of the following values -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void I2C_SendSlaveAddress(I2C_TypeDef* i2c, u8 addr) -{ - WRITE_REG(i2c->IC_SAR, addr >> 1); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the I2C slave mode. -/// @param i2c: select the I2C peripheral. -/// @param state: new state of the specified I2C interrupts. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void I2C_SlaveConfigure(I2C_TypeDef* i2c, FunctionalState state) -{ - (state) ? CLEAR_BIT(i2c->IC_CON, I2C_CR_SLAVEDIS) : SET_BIT(i2c->IC_CON, I2C_CR_SLAVEDIS); -} -/// @} - -/// @} - -/// @} diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_iwdg.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_iwdg.c deleted file mode 100644 index 06b49fb24..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_iwdg.c +++ /dev/null @@ -1,208 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_iwdg.c -/// @author AE TEAM -/// @brief THIS FILE PROVIDES ALL THE IWDG FIRMWARE FUNCTIONS. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#define _HAL_IWDG_C_ - -// Files includes -#include "hal_iwdg.h" - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup IWDG_HAL -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup IWDG_Exported_Functions -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables write access to IWDG_PR and IWDG_RLR -/// registers. -/// @param write_access: new state of write access to IWDG_PR and -/// IWDG_RLR registers. -/// This parameter can be one of the following values: -/// @arg IWDG_WriteAccess_Enable: Enable write access to -/// IWDG_PR and IWDG_RLR registers -/// @arg IWDG_WriteAccess_Disable: Disable write access to -/// IWDG_PR and IWDG_RLR registers -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void IWDG_WriteAccessCmd(u16 write_access) -{ - IWDG->KR = write_access; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Sets IWDG Prescaler value. -/// @param prescaler: specifies the IWDG Prescaler value. -/// This parameter can be one of the following values: -/// @arg IWDG_Prescaler_4: IWDG prescaler set to 4 -/// @arg IWDG_Prescaler_8: IWDG prescaler set to 8 -/// @arg IWDG_Prescaler_16: IWDG prescaler set to 16 -/// @arg IWDG_Prescaler_32: IWDG prescaler set to 32 -/// @arg IWDG_Prescaler_64: IWDG prescaler set to 64 -/// @arg IWDG_Prescaler_128: IWDG prescaler set to 128 -/// @arg IWDG_Prescaler_256: IWDG prescaler set to 256 -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void IWDG_SetPrescaler(u8 prescaler) -{ - IWDG->PR = prescaler; - PVU_CheckStatus(); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Set IWDG reload value. -/// @param reload: specifies the IWDG reload value. -/// This parameter must be a number between 0 and 0x0FFF. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void IWDG_SetReload(u16 reload) -{ - IWDG->RLR = reload; - RVU_CheckStatus(); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Get IWDG reload value. -/// @param None. -/// @retval reload: specifies the IWDG reload value. -//////////////////////////////////////////////////////////////////////////////// -u32 IWDG_GetReload(void) -{ - return IWDG->RLR; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Reloads IWDG counter with value defined in the reload register -/// (write access to IWDG_PR and IWDG_RLR registers disabled). -/// @param None. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void IWDG_ReloadCounter(void) -{ - IWDG->KR = KR_KEY_Reload; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers -/// disabled). -/// @param None. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void IWDG_Enable(void) -{ - IWDG->KR = KR_KEY_Enable; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Checks whether the specified IWDG flag is set or not. -/// @param flag: specifies the flag to check. -/// This parameter can be one of the following values: -/// @arg IWDG_FLAG_PVU: Prescaler Value Update on going -/// @arg IWDG_FLAG_RVU: reload Value Update on going -/// @retval The new state of flag (SET or RESET). -//////////////////////////////////////////////////////////////////////////////// -FlagStatus IWDG_GetFlagStatus(u16 flag) -{ - return ((IWDG->SR & flag) != (u32)RESET) ? SET : RESET; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Checks prescaler value has been updated. -/// @param None. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void PVU_CheckStatus(void) -{ - while (IWDG_GetFlagStatus(IWDG_FLAG_PVU) == SET); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Checks count relead value has been updated. -/// @param None. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RVU_CheckStatus(void) -{ - while (IWDG_GetFlagStatus(IWDG_FLAG_RVU) == SET); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief IWDG overflow configuration. -/// @param overflow_config -/// @arg IWDG_Overflow_Interrupt: Interrupt after overflow. -/// @arg IWDG_Overflow_Reset: Reset after overflow. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void IWDG_OverflowConfig(IWDGOverflowConfig_TypeDef overflow_config) -{ - IWDG->CR &= ~IWDG_CR_IRQSEL; - IWDG->CR |= overflow_config; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Clear interrupt flag -/// @param None. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void IWDG_ClearITPendingBit(void) -{ - IWDG->CR |= IWDG_CR_IRQCLR;//write 1 clear interrupt Flag -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Clear interrupt flag -/// @param None. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void IWDG_ClearIT(void) -{ - IWDG->CR |= IWDG_CR_IRQCLR;//write 1 clear interrupt Flag -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enable IWDG interrupt function -/// @param None. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void IWDG_EnableIT(void) -{ - IWDG->CR |= IWDG_CR_IRQSEL; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Disable IWDG interrupt function -/// @param None. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void IWDG_Reset(void) -{ - IWDG->CR &= ~IWDG_CR_IRQSEL; -} - - - -/// @} - -/// @} - -/// @} diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_misc.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_misc.c deleted file mode 100644 index 598d6d07e..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_misc.c +++ /dev/null @@ -1,147 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_misc.c -/// @author AE TEAM -/// @brief THIS FILE PROVIDES ALL THE MSIC FIRMWARE FUNCTIONS. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#define _HAL_MISC_C_ - -// Files includes -#include "hal_misc.h" - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MSIC_HAL -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MISC_Exported_Functions -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Set the NVIC interrupt vector table. -/// @param vect_tab -/// This parameter can be any combination of the following values: -/// @arg NVIC_VectTab_RAM -/// @arg NVIC_VectTab_FLASH -/// @param offset -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void NVIC_SetVectorTable(u32 vect_tab, u32 offset) -{ - SCB->VTOR = vect_tab | (offset & (u32)0x1FFFFF80); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Set the NVIC interrupt priority group. -/// @param priority_group -/// This parameter can be any combination of the following values: -/// @arg NVIC_PriorityGroup_0 -/// @arg NVIC_PriorityGroup_1 -/// @arg NVIC_PriorityGroup_2 -/// @arg NVIC_PriorityGroup_3 -/// @arg NVIC_PriorityGroup_4 -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void NVIC_PriorityGroupConfig(u32 priority_group) -{ - SCB->AIRCR = AIRCR_VECTKEY_MASK | priority_group; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief NVIC initialization. -/// @param init_struct -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void NVIC_Init(NVIC_InitTypeDef* init_struct) -{ - if (init_struct->NVIC_IRQChannelCmd != DISABLE) { - u32 pri = (SCB_AIRCR_PRIGROUP & ~(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk)) >> SCB_AIRCR_PRIGROUP_Pos; - - pri = (((u32)init_struct->NVIC_IRQChannelPreemptionPriority << (0x4 - pri)) | - (init_struct->NVIC_IRQChannelSubPriority & (0x0F >> pri))) - << 0x04; - - NVIC->IP[init_struct->NVIC_IRQChannel] = pri; - NVIC->ISER[init_struct->NVIC_IRQChannel >> 0x05] = 0x01 << (init_struct->NVIC_IRQChannel & 0x1F); - } - else { - NVIC->ICER[init_struct->NVIC_IRQChannel >> 0x05] = 0x01 << (init_struct->NVIC_IRQChannel & 0x1F); - } - -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief NVIC initialized extension function. -/// @param init_struct -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void exNVIC_Init(exNVIC_Init_TypeDef* init_struct) -{ - u32 pri; - - if (init_struct->NVIC_IRQChannelCmd != DISABLE) { - pri = (SCB_AIRCR_PRIGROUP & ~(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk)) >> SCB_AIRCR_PRIGROUP_Pos; - - pri = (((u32)init_struct->NVIC_IRQChannelPreemptionPriority << (0x4 - pri)) | - (init_struct->NVIC_IRQChannelSubPriority & (0x0F >> pri))) << 0x04; - - NVIC->IP[init_struct->NVIC_IRQChannel] = pri; - NVIC->ISER[init_struct->NVIC_IRQChannel >> 0x05] = 0x01 << (init_struct->NVIC_IRQChannel & 0x1F); - } - else { - NVIC->ICER[init_struct->NVIC_IRQChannel >> 0x05] = 0x01 << (init_struct->NVIC_IRQChannel & 0x1F); - } - -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief System low power mode configuration. -/// @param low_power_mode -/// This parameter can be any combination of the following values: -/// @arg NVIC_LP_SEVONPEND -/// @arg NVIC_LP_SLEEPDEEP -/// @arg NVIC_LP_SLEEPONEXIT -/// @param state: new state of the low power mode. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void NVIC_SystemLPConfig(u8 low_power_mode, FunctionalState state) -{ - (state) ? (SCB->SCR |= low_power_mode) : (SCB->SCR &= ~(u32)low_power_mode); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SysTick clock source configuration. -/// @param systick_clk_source -/// This parameter can be any combination of the following values: -/// @arg SysTick_CLKSource_EXTCLK -/// @arg SysTick_CLKSource_HCLK -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void SysTick_CLKSourceConfig(u32 systick_clk_source) -{ - (systick_clk_source == SysTick_CLKSource_HCLK) ? (SysTick->CTRL |= SysTick_CLKSource_HCLK) \ - : (SysTick->CTRL &= ~SysTick_CLKSource_HCLK); -} - -/// @} - -/// @} - -/// @} diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_pwr.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_pwr.c deleted file mode 100644 index e39bf3f31..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_pwr.c +++ /dev/null @@ -1,215 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_pwr.c -/// @author AE TEAM -/// @brief THIS FILE PROVIDES ALL THE PWR FIRMWARE FUNCTIONS. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#define __HAL_PWR_C_ - -// Files includes -#include "hal_pwr.h" -#include "hal_rcc.h" -#include "hal_syscfg.h" -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup PWR_HAL -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup PWR_Exported_Functions -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Deinitializes the PWR peripheral registers to their default reset -/// values. -/// @param None. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void PWR_DeInit(void) -{ - exRCC_APB1PeriphReset(RCC_APB1ENR_PWR); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables access to the RTC and backup registers. -/// @param state: new state of the access to the RTC and backup -/// registers. This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void PWR_BackupAccessCmd(FunctionalState state) -{ - (state) ? (RCC->BDCR |= RCC_BDCR_DBP) : (RCC->BDCR &= ~RCC_BDCR_DBP); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the Power Voltage Detector(PVD). -/// @param state: new state of the PVD. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void PWR_PVDCmd(FunctionalState state) -{ - (state) ? (SYSCFG->PDETCSR |= SYSCFG_PDETCSR_PVDE) : (SYSCFG->PDETCSR &= ~SYSCFG_PDETCSR_PVDE); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the voltage threshold detected by the Power Voltage -/// Detector(PVD). -/// @param pvd_level: specifies the PVD detection level -/// This parameter can be one of the following values: -/// @arg emPVD_LEVEL0 : PVD detection level set to 1.7V -/// @arg emPVD_LEVEL1 : PVD detection level set to 2.0V -/// @arg emPVD_LEVEL2 : PVD detection level set to 2.3V -/// @arg emPVD_LEVEL3 : PVD detection level set to 2.6V -/// @arg emPVD_LEVEL4 : PVD detection level set to 2.9V -/// @arg emPVD_LEVEL5 : PVD detection level set to 3.2V -/// @arg emPVD_LEVEL6 : PVD detection level set to 3.5V -/// @arg emPVD_LEVEL7 : PVD detection level set to 3.8V -/// @arg emPVD_LEVEL8 : PVD detection level set to 4.1V -/// @arg emPVD_LEVEL9 : PVD detection level set to 4.4V -/// @arg emPVD_LEVEL10: PVD detection level set to 4.7V -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void PWR_PVDLevelConfig(emPVD_Level_Typedef pvd_level) -{ - SYSCFG->PDETCSR = (SYSCFG->PDETCSR & (~SYSCFG_PDETCSR_PLS)) | pvd_level; -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the WakeUp Pin functionality. -/// @param state: new state of the WakeUp Pin functionality. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void PWR_WakeUpPinCmd(FunctionalState state) -{ - (state != DISABLE) ? (PWR->CR2 |= PWR_CR2_EWUP1) : (PWR->CSR &= ~PWR_CR2_EWUP1); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the WakeUp Pin functionality. -/// @param state: new state of the WakeUp Pin functionality. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void PWR_WakeUpPinXCmd(emWUP_Pin_Typedef pin, FunctionalState state) -{ - (state != DISABLE) ? (PWR->CR2 |= (PWR_CR2_EWUP1 << pin)) : (PWR->CSR &= ~(PWR_CR2_EWUP1 << pin)); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enters STOP mode. -/// @param regulator: specifies the regulator state in STOP mode. -/// This parameter can be one of the following values: -/// @arg PWR_Regulator_ON: STOP mode with regulator ON -/// @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode. -/// @param stop_entry: specifies if STOP mode in entered with WFI or WFE -/// instruction. -/// This parameter can be one of the following values: -/// @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction -/// @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void PWR_EnterSTOPMode(emPWR_Reg_Stop_mode_Typedef regulator, emPWR_STOP_ModeEn_Typedef stop_entry) -{ - - MODIFY_REG(PWR->CR, PWR_CR_LDPS, regulator); - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - if(stop_entry == PWR_STOPEntry_WFI) { - __WFI(); - } - else { - __WFE(); - } -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enters STANDBY mode. -/// @param None. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void PWR_EnterSTANDBYMode(void) -{ - PWR->CR |= PWR_CR_PDDS; - PWR->SCR |= PWR_SCR_CWUF1 | PWR_SCR_CWUF2 | PWR_SCR_CWUF3 | PWR_SCR_CWUF4 | PWR_SCR_CWUF5 | PWR_SCR_CWUF6; - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - -#if defined(__CC_ARM) - __force_stores(); -#endif - __WFI(); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Checks whether the specified PWR flag is set or not. -/// @param flag: specifies the flag to check. -/// This parameter can be one of the following values: -/// @arg PWR_FLAG_WU: Wake Up flag -/// @arg PWR_FLAG_SB: StandBy flag -/// @arg PWR_FLAG_PVDO: PVD Output -/// @retval The new state of PWR_FLAG (SET or RESET). -//////////////////////////////////////////////////////////////////////////////// -FlagStatus PWR_GetPVDOFlagStatus(u32 flag) -{ - return (FlagStatus)(SYSCFG->PDETCSR & flag); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Clears the PWR's pending flags. -/// @param flag: specifies the flag to clear. -/// This parameter can be one of the following values: -/// @arg PWR_FLAG_WU: Wake Up flag -/// @arg PWR_FLAG_SB: StandBy flag -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void PWR_ClearPVDOFlag(u32 flag) -{ - PWR->CR |= flag << 2; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Checks whether the specified PWR flag is set or not. -/// @param flag: specifies the flag to check. -/// This parameter can be one of the following values: -/// @arg PWR_FLAG_WU: Wake Up flag -/// @arg PWR_FLAG_SB: StandBy flag -/// @arg PWR_FLAG_PVDO: PVD Output -/// @retval The new state of PWR_FLAG (SET or RESET). -//////////////////////////////////////////////////////////////////////////////// -FlagStatus PWR_GetFlagStatus(u32 flag) -{ - return (FlagStatus)(PWR->CSR & flag); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Clears the PWR's pending flags. -/// @param flag: specifies the flag to clear. -/// This parameter can be one of the following values: -/// @arg PWR_FLAG_WU: Wake Up flag -/// @arg PWR_FLAG_SB: StandBy flag -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void PWR_ClearFlag(u32 flag) -{ - PWR->CR |= flag << 2; -} - -/// @} - -/// @} - -/// @} diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rcc.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rcc.c deleted file mode 100644 index 5e2bd1a85..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rcc.c +++ /dev/null @@ -1,995 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_rcc.c -/// @author AE TEAM -/// @brief THIS FILE PROVIDES ALL THE RCC FIRMWARE FUNCTIONS. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#define _HAL_RCC_C_ - -// Files includes -#include "mm32_reg.h" -#include "hal_rcc.h" - - - -u8 tbPresc[] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup RCC_HAL -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup RCC_Exported_Functions -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Resets the RCC clock configuration to default state. -/// @param None. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RCC_DeInit() -{ - SET_BIT(RCC->CR, RCC_CR_HSION); - CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW); - CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON ); - CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL_DN | RCC_PLLCFGR_PLL_DP); - CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); - CLEAR_REG(RCC->CFGR); - CLEAR_REG(RCC->CIR); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the External High Speed oscillator (HSE). -/// @param state: specifies the new state of HSE. -/// This parameter can be one of the following values: -/// @arg RCC_HSE_OFF: HSE oscillator OFF -/// @arg RCC_HSE_ON: HSE oscillator ON -/// @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RCC_HSEConfig(RCCHSE_TypeDef state) -{ - RCC->CR &= ~(RCC_CR_HSEBYP | RCC_CR_HSEON); - switch (state) { - case RCC_HSE_Bypass: - RCC->CR |= RCC_CR_HSEBYP; - RCC->CR |= RCC_CR_HSEON; - break; - case RCC_HSE_ON: - RCC->CR |= RCC_CR_HSEON; - break; - default: - break; - } -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Checks whether the specified RCC flag is set or not. -/// @param flag: specifies the flag to check. -/// This parameter can be one of the following values: -/// @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready -/// @arg RCC_FLAG_HSERDY: HSE oscillator clock ready -/// @arg RCC_FLAG_PLLRDY: PLL clock ready -/// @arg RCC_FLAG_LSERDY: LSE oscillator clock ready -/// @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready -/// @arg RCC_FLAG_PINRST: Pin reset -/// @arg RCC_FLAG_PORRST: POR/PDR reset -/// @arg RCC_FLAG_SFTRST: Software reset -/// @arg RCC_FLAG_IWDGRST: Independent Watchdog reset -/// @arg RCC_FLAG_WWDGRST: Window Watchdog reset -/// @arg RCC_FLAG_LPWRRST: Low Power reset -/// @retval The new state of flag (SET or RESET). -//////////////////////////////////////////////////////////////////////////////// -FlagStatus RCC_GetFlagStatus(RCC_FLAG_TypeDef flag) -{ - return ((((flag >> 5) == CR_REG_INDEX) ? RCC->CR : (((flag >> 5) == BDCR_REG_INDEX) ? RCC->BDCR : RCC->CSR)) & - (1 << (flag & 0x1F))) - ? SET : RESET; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Waits for HSE start-up. -/// @param None. -/// @retval An ErrorStatus enumuration value: -/// - SUCCESS: HSE oscillator is stable and ready to use -/// - ERROR: HSE oscillator not yet ready -//////////////////////////////////////////////////////////////////////////////// -ErrorStatus RCC_WaitForHSEStartUp(void) -{ - u32 StartUpCounter = 0; - - FlagStatus HSEStatus; - - do { - HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); - StartUpCounter++; - } while ((HSEStatus == RESET) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - return (ErrorStatus)(RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) ? SUCCESS : ERROR; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Waits for flag start-up. -/// @param flag: specifies the flag to check. -/// This parameter can be one of the following values: -/// @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready -/// @arg RCC_FLAG_HSERDY: HSE oscillator clock ready -/// @arg RCC_FLAG_PLLRDY: PLL clock ready -/// @arg RCC_FLAG_LSERDY: LSE oscillator clock ready -/// @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready -/// @arg RCC_FLAG_PINRST: Pin reset -/// @arg RCC_FLAG_PORRST: POR/PDR reset -/// @arg RCC_FLAG_SFTRST: Software reset -/// @arg RCC_FLAG_IWDGRST: Independent Watchdog reset -/// @arg RCC_FLAG_WWDGRST: Window Watchdog reset -/// @retval An ErrorStatus enumuration value: -/// - SUCCESS: HSE oscillator is stable and ready to use -/// - ERROR: HSE oscillator not yet ready -//////////////////////////////////////////////////////////////////////////////// -ErrorStatus RCC_WaitForFlagStartUp(RCC_FLAG_TypeDef flag) -{ - u32 StartUpCounter = 0; - - while (RCC_GetFlagStatus(flag) == RESET) { - if (StartUpCounter++ > HSE_STARTUP_TIMEOUT) { - return ERROR; - } - } - return SUCCESS; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the Internal High Speed oscillator (HSI). -/// @param state: new state of the HSI. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RCC_HSICmd(FunctionalState state) -{ - MODIFY_REG(RCC->CR, RCC_CR_HSION, (state << RCC_CR_HSION_Pos)); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the system clock (SYSCLK). -/// @param sys_clk_source: specifies the clock source used as system -/// clock. This parameter can be one of the following values: -/// @arg RCC_HSI: specifies HSI as system clock -/// @arg RCC_HSE: specifies HSE as system clock -/// @arg RCC_PLL: specifies PLL as system clock -/// @arg RCC_LSI: specifies LSI as system clock -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RCC_SYSCLKConfig(SYSCLK_TypeDef sys_clk_source) -{ - MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (sys_clk_source << RCC_CFGR_SW_Pos)); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the PLL clock source and DM DN factor. -/// This function must be used only when the PLL is disabled. -/// @param plldn: specifies the PLL multiplication factor. -/// This parameter can be RCC_PLLMul_x where x:[31:26] -/// @param plldm: specifies the PLL Divsior factor. -/// This parameter can be RCC_Divsior_x where x:[22:20] -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RCC_PLLDMDNConfig(u32 plldn, u32 plldm) -{ - MODIFY_REG(RCC->PLLCFGR, (RCC_PLLCFGR_PLL_DN | RCC_PLLCFGR_PLL_DP), ((plldn << RCC_PLLCFGR_PLL_DN_Pos) | (plldm << RCC_PLLCFGR_PLL_DP_Pos))); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the PLL. -/// The PLL can not be disabled if it is used as system clock. -/// @param state: new state of the PLL. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RCC_PLLCmd(FunctionalState state) -{ - MODIFY_REG(RCC->CR, RCC_CR_PLLON, (state << RCC_CR_PLLON_Pos)); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the PLL clock source and multiplication factor. -/// This function must be used only when the PLL is disabled. -/// @param pll_src: specifies the PLL entry clock source. -/// This parameter can be one of the following values: -/// @arg RCC_HSI_Div4: HSI oscillator clock divided -/// by 4 selected as PLL clock entry -/// @arg RCC_HSE_Div1: HSE oscillator clock selected -/// as PLL clock entry -/// @arg RCC_HSE_Div2: HSE oscillator clock divided -/// by 2 selected as PLL clock entry -/// @param pll_mul: specifies the PLL multiplication factor. -/// This parameter can be RCC_PLLMul_x where x:[31:26][22:20] -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RCC_PLLConfig(RCC_PLLSource_TypeDef pll_src, RCC_PLLMul_TypeDef pll_mul) -{ - const u8 DNDM_Item[] = {0x07, 0x03, 0x05, 0x01, 0x07, 0x01, 0x09, 0x01, // Frclk*8/4 ; Frclk*6/2 ; Frclk*8/2 ; Frclk*10/2; - 0x0B, 0x01, 0x0D, 0x01, 0x0F, 0x01, 0x11, 0x01, // Frclk*12/2; Frclk*14/2; Frclk*16/2; Frclk*18/2; - 0x13, 0x01, 0x15, 0x01, 0x17, 0x01, 0x19, 0x01, // Frclk*20/2; Frclk*22/2; Frclk*24/2; Frclk*26/2; - 0x1B, 0x01, 0x1D, 0x01, 0x1F, 0x01 - }; // Frclk*28/2; Frclk*30/2; // Frclk*32/2; - MODIFY_REG(RCC->PLLCFGR, (RCC_PLLCFGR_PLLXTPRE | RCC_PLLCFGR_PLLSRC), pll_src); - RCC_PLLDMDNConfig((u32)DNDM_Item[pll_mul >> 17], (u32)DNDM_Item[(pll_mul >> 17) + 1]); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the USB clock (USBCLK). -/// @param usb_clk_src: specifies the USB clock source. -/// This clock is derived from the PLL output. -/// This parameter can be one of the following values: -/// @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source -/// @arg RCC_USBCLKSource_PLLCLK_Div2: PLL clock divided by 2 selected as USB -/// clock source -/// @arg RCC_USBCLKSource_PLLCLK_Div3: PLL clock divided by 3 selected as USB -/// clock source -/// @arg RCC_USBCLKSource_PLLCLK_Div4: PLL clock divided by 4 selected as USB -/// clock source -/// @arg RCC_USBCLKSource_PLLCLK_Div5: PLL clock divided by 5 selected as USB -/// clock source -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RCC_USBCLKConfig(RCC_USBCLKSOURCE_TypeDef usb_clk_src) -{ - MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (usb_clk_src << RCC_CFGR_USBPRE_Pos)); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Returns the clock source used as system clock. -/// @param None. -/// @retval The clock source used as system clock. The returned value can -/// be one of the following: -/// - 0x00: HSI/6 used as system clock -/// - 0x04: HSE used as system clock -/// - 0x08: PLL used as system clock -//////////////////////////////////////////////////////////////////////////////// -u8 RCC_GetSYSCLKSource(void) -{ - return ((u8)READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the AHB clock (hclk). -/// @param sys_clk: defines the AHB clock divider. This clock is derived -/// from the system clock (SYSCLK). -/// This parameter can be one of the following values: -/// @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK -/// @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2 -/// @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4 -/// @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8 -/// @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16 -/// @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64 -/// @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128 -/// @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 -/// @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512 -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RCC_HCLKConfig(RCC_AHB_CLK_TypeDef sys_clk) -{ - MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, sys_clk); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the Low Speed APB clock (pclk1). -/// @param hclk: defines the APB1 clock divider. This clock is derived from -/// the AHB clock (hclk). -/// This parameter can be one of the following values: -/// @arg RCC_HCLK_Div1: APB1 clock = hclk -/// @arg RCC_HCLK_Div2: APB1 clock = hclk/2 -/// @arg RCC_HCLK_Div4: APB1 clock = hclk/4 -/// @arg RCC_HCLK_Div8: APB1 clock = hclk/8 -/// @arg RCC_HCLK_Div16: APB1 clock = hclk/16 -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RCC_PCLK1Config(RCC_APB1_APB2_CLK_TypeDef hclk) -{ - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, hclk); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the High Speed APB clock (pclk2). -/// @param hclk: defines the APB2 clock divider. This clock is derived from -/// the AHB clock (hclk). -/// This parameter can be one of the following values: -/// @arg RCC_HCLK_Div1: APB2 clock = hclk -/// @arg RCC_HCLK_Div2: APB2 clock = hclk/2 -/// @arg RCC_HCLK_Div4: APB2 clock = hclk/4 -/// @arg RCC_HCLK_Div8: APB2 clock = hclk/8 -/// @arg RCC_HCLK_Div16: APB2 clock = hclk/16 -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RCC_PCLK2Config(RCC_APB1_APB2_CLK_TypeDef hclk) -{ - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (hclk << 3)); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the ADC clock (ADCCLK). -/// @param pclk2: defines the ADC clock divider. This clock is derived from -/// the APB2 clock (pclk2). -/// This parameter can be one of the following values: -/// @arg RCC_PCLK2_Div2: ADC clock = pclk2/2 -/// @arg RCC_PCLK2_Div4: ADC clock = pclk2/4 -/// @arg RCC_PCLK2_Div6: ADC clock = pclk2/6 -/// @arg RCC_PCLK2_Div8: ADC clock = pclk2/8 -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RCC_ADCCLKConfig(RCC_ADCCLKSOURCE_TypeDef pclk2) -{ - MODIFY_REG(RCC->CFGR, ADC_CFGR_PRE, pclk2); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the External Low Speed oscillator (LSE). -/// @param state: specifies the new state of the LSE. -/// This parameter can be one of the following values: -/// @arg RCC_LSE_OFF: LSE oscillator OFF -/// @arg RCC_LSE_ON: LSE oscillator ON -/// @arg RCC_LSE_Bypass: LSE oscillator bypassed with external -/// clock -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RCC_LSEConfig(RCC_LSE_TypeDef state) -{ - RCC->BDCR &= ~(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON); - - switch (state) { - case RCC_LSE_Bypass: - RCC->BDCR |= RCC_BDCR_LSEBYP; - RCC->BDCR |= RCC_BDCR_LSEON; - break; - case RCC_LSE_ON: - RCC->BDCR |= RCC_BDCR_LSEON; - break; - default: - break; - } -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the RTC clock (RTCCLK). -/// Once the RTC clock is selected it can be changed unless the -/// Backup domain is reset. -/// @param rtc_clk_src: specifies the RTC clock source. -/// This parameter can be one of the following values: -/// @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock -/// @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock -/// @arg RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 -/// selected as RTC clock -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RCC_RTCCLKConfig(RCC_RTCCLKSOURCE_TypeDef rtc_clk_src) -{ - MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, rtc_clk_src); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the RTC clock. -/// This function must be used only after the RTC clock was -/// selected using the RCC_RTCCLKConfig function. -/// @param state: new state of the RTC clock. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RCC_RTCCLKCmd(FunctionalState state) -{ - MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCEN, (state << RCC_BDCR_RTCEN_Pos)); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the Internal Low Speed oscillator (LSI). -/// LSI can not be disabled if the IWDG is running. -/// @param state: new state of the LSI. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RCC_LSICmd(FunctionalState state) -{ -// u32 j; - MODIFY_REG(RCC->CSR, RCC_CSR_LSION | RCC_CSR_LSIOENLV, RCC_CSR_LSIOENLV | (state << RCC_CSR_LSION_Pos)); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Returns the clock frequency of different on chip clocks. -/// @param None. -/// @retval sys_clk : System clock frequency -//////////////////////////////////////////////////////////////////////////////// -u32 RCC_GetSysClockFreq(void) -{ - u32 result; - u32 clock, mul, div; - switch (RCC->CFGR & RCC_CFGR_SWS) { - case RCC_CFGR_SWS_LSI: - result = LSI_VALUE; - break; - - case RCC_CFGR_SWS_HSE: - result = HSE_VALUE; - break; - - case RCC_CFGR_SWS_PLL: - clock = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC) ? (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLXTPRE) ? (HSE_VALUE >> 1) : HSE_VALUE) - : HSI_VALUE_PLL_ON; - mul = ((RCC->PLLCFGR & (u32)RCC_PLLCFGR_PLL_DN) >> RCC_PLLCFGR_PLL_DN_Pos) + 1; - div = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL_DP) >> RCC_PLLCFGR_PLL_DP_Pos) + 1; - - result = clock * mul / div; - break; - default: - result = HSI_VALUE; - break; - } - return result; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Returns the hclk frequency of different on chip clocks. -/// @param None. -/// @retval hclk frequency -//////////////////////////////////////////////////////////////////////////////// -u32 RCC_GetHCLKFreq(void) -{ - return (RCC_GetSysClockFreq() >> tbPresc[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Returns the pclk1 frequency of different on chip clocks. -/// @param None. -/// @retval pclk1 frequency -//////////////////////////////////////////////////////////////////////////////// -u32 RCC_GetPCLK1Freq(void) -{ - return (RCC_GetHCLKFreq() >> tbPresc[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Returns the pclk2 frequency of different on chip clocks. -/// @param None. -/// @retval pclk2 frequency -//////////////////////////////////////////////////////////////////////////////// -u32 RCC_GetPCLK2Freq(void) -{ - return (RCC_GetHCLKFreq() >> tbPresc[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Returns the frequency of different on chip clocks. -/// @param clk: pointer to a RCC_ClocksTypeDef structure which -/// will hold the clocks frequency. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RCC_GetClocksFreq(RCC_ClocksTypeDef* clk) -{ - u8 tbADCPresc[] = {2, 4, 6, 8}; - - clk->SYSCLK_Frequency = RCC_GetSysClockFreq(); - clk->HCLK_Frequency = RCC_GetHCLKFreq(); - clk->PCLK1_Frequency = RCC_GetPCLK1Freq(); - clk->PCLK2_Frequency = RCC_GetPCLK2Freq(); - - clk->ADCCLK_Frequency = clk->PCLK2_Frequency / tbADCPresc[(RCC->CFGR & ADC_CFGR_PRE) >> ADC_CFGR_PRE_Pos]; - -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the AHB peripheral clock. -/// @param ahb_periph: specifies the AHB peripheral to gates its clock. -/// This parameter can be any combination of the following values: -/// @param state: new state of the specified peripheral clock. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RCC_AHBPeriphClockCmd(u32 ahb_periph, FunctionalState state) -{ - (state) ? (RCC->AHBENR |= ahb_periph) : (RCC->AHBENR &= ~ahb_periph); -} -/// @param state: new state of the specified peripheral clock. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RCC_AHB2PeriphClockCmd(u32 ahb_periph, FunctionalState state) -{ - (state) ? (RCC->AHB2ENR |= ahb_periph) : (RCC->AHB2ENR &= ~ahb_periph); -} -/// @param state: new state of the specified peripheral clock. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RCC_AHB3PeriphClockCmd(u32 ahb_periph, FunctionalState state) -{ - (state) ? (RCC->AHB3ENR |= ahb_periph) : (RCC->AHB3ENR &= ~ahb_periph); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the High Speed APB (APB2) peripheral clock. -/// @param apb2_periph: specifies the APB2 peripheral to gates its -/// clock. -/// This parameter can be any combination of the following values: -/// @param state: new state of the specified peripheral clock. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RCC_APB2PeriphClockCmd(u32 apb2_periph, FunctionalState state) -{ - (state) ? (RCC->APB2ENR |= apb2_periph) : (RCC->APB2ENR &= ~apb2_periph); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the Low Speed APB (APB1) peripheral clock. -/// @param apb1_periph: specifies the APB1 peripheral to gates its -/// clock. -/// This parameter can be any combination of the following values: -/// @param state: new state of the specified peripheral clock. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RCC_APB1PeriphClockCmd(u32 apb1_periph, FunctionalState state) -{ - (state) ? (RCC->APB1ENR |= apb1_periph) : (RCC->APB1ENR &= ~apb1_periph); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Forces or releases High Speed APB (APB2) peripheral reset. -/// @param apb2_periph: specifies the APB2 peripheral to reset. -/// This parameter can be any combination of the following values: -/// @param state: new state of the specified peripheral reset. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RCC_APB2PeriphResetCmd(u32 apb2_periph, FunctionalState state) -{ - (state) ? (RCC->APB2RSTR |= apb2_periph) : (RCC->APB2RSTR &= ~apb2_periph); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Forces or releases Low Speed APB (APB1) peripheral reset. -/// @param apb1_periph: specifies the APB1 peripheral to reset. -/// This parameter can be any combination of the following values: -/// @param state: new state of the specified peripheral clock. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RCC_APB1PeriphResetCmd(u32 apb1_periph, FunctionalState state) -{ - (state) ? (RCC->APB1RSTR |= apb1_periph) : (RCC->APB1RSTR &= ~apb1_periph); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Forces or releases Low Speed AHB peripheral reset. -/// @param ahb_periph: specifies the AHB peripheral to reset. -/// This parameter can be any combination of the following values: -/// @param state: new state of the specified peripheral clock. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RCC_AHBPeriphResetCmd(u32 ahb_periph, FunctionalState state) -{ - (state) ? (RCC->AHBRSTR |= ahb_periph) : (RCC->AHBRSTR &= ~ahb_periph); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Forces or releases Low Speed AHB2 peripheral reset. -/// @param ahb_periph: specifies the AHB peripheral to reset. -/// This parameter can be any combination of the following values: -/// @param state: new state of the specified peripheral clock. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RCC_AHB2PeriphResetCmd(u32 ahb_periph, FunctionalState state) -{ - (state) ? (RCC->AHB2RSTR |= ahb_periph) : (RCC->AHB2RSTR &= ~ahb_periph); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Forces or releases Low Speed AHB2 peripheral reset. -/// @param ahb_periph: specifies the AHB peripheral to reset. -/// This parameter can be any combination of the following values: -/// @param state: new state of the specified peripheral clock. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RCC_AHB3PeriphResetCmd(u32 ahb_periph, FunctionalState state) -{ - (state) ? (RCC->AHB3RSTR |= ahb_periph) : (RCC->AHB3RSTR &= ~ahb_periph); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Forces or releases the Backup domain reset. -/// @param state: new state of the Backup domain reset. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RCC_BackupResetCmd(FunctionalState state) -{ - MODIFY_REG(RCC->BDCR, RCC_BDCR_BDRST, (state << RCC_BDCR_BDRST_Pos)); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the Clock Security System. -/// @param state: new state of the Clock Security System.. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RCC_ClockSecuritySystemCmd(FunctionalState state) -{ - MODIFY_REG(RCC->CR, RCC_CR_CSSON, (state << RCC_CR_CSSON_Pos)); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Selects the clock source to output on MCO pin. -/// @param mco_src: specifies the clock source to output. -/// This parameter can be one of the following values: -/// @arg RCC_MCO_NoClock: No clock selected -/// @arg RCC_MCO_LSI: LSI oscillator clock selected -/// @arg RCC_MCO_LSE: LSE oscillator clock selected -/// @arg RCC_MCO_SYSCLK: System clock selected -/// @arg RCC_MCO_HSI: HSI oscillator clock selected -/// @arg RCC_MCO_HSE: HSE oscillator clock selected -/// @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RCC_MCOConfig(RCC_MCO_TypeDef mco_src) -{ - MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, mco_src); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Clears the RCC reset flags. -/// The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, -/// RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, -/// RCC_FLAG_LPWRRST -/// @param None. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RCC_ClearFlag(void) -{ - SET_BIT(RCC->CSR, RCC_CSR_RMVF); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the specified RCC interrupts. -/// @param it: specifies the RCC interrupt sources to be enabled or -/// disabled. -/// This parameter can be any combination of the following values: -/// @arg RCC_IT_LSIRDY: LSI ready interrupt -/// @arg RCC_IT_LSERDY: LSE ready interrupt -/// @arg RCC_IT_HSIRDY: HSI ready interrupt -/// @arg RCC_IT_HSERDY: HSE ready interrupt -/// @arg RCC_IT_PLLRDY: PLL ready interrupt -/// @param state: new state of the specified RCC interrupts. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RCC_ITConfig(RCC_IT_TypeDef it, FunctionalState state) -{ - (state) ? SET_BIT(RCC->CIR, it << RCC_CIR_LSIRDYIE_Pos) : CLEAR_BIT(RCC->CIR, it << RCC_CIR_LSIRDYIE_Pos); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Checks whether the specified RCC interrupt has occurred or not. -/// @param it: specifies the RCC interrupt source to check. -/// This parameter can be one of the following values: -/// @arg RCC_IT_LSIRDY: LSI ready interrupt -/// @arg RCC_IT_LSERDY: LSE ready interrupt -/// @arg RCC_IT_HSIRDY: HSI ready interrupt -/// @arg RCC_IT_HSERDY: HSE ready interrupt -/// @arg RCC_IT_PLLRDY: PLL ready interrupt -/// @arg RCC_IT_CSS: Clock Security System interrupt -/// @retval The new state of it (SET or RESET). -//////////////////////////////////////////////////////////////////////////////// -ITStatus RCC_GetITStatus(RCC_IT_TypeDef it) -{ - return (ITStatus)READ_BIT(RCC->CIR, (it << RCC_CIR_LSIRDYF_Pos)); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Clears the RCC�?interrupt pending bits. -/// @param it: specifies the interrupt pending bit to clear. -/// This parameter can be any combination of the following values: -/// @arg RCC_IT_LSIRDY: LSI ready interrupt -/// @arg RCC_IT_LSERDY: LSE ready interrupt -/// @arg RCC_IT_HSIRDY: HSI ready interrupt -/// @arg RCC_IT_HSERDY: HSE ready interrupt -/// @arg RCC_IT_PLLRDY: PLL ready interrupt -/// @arg RCC_IT_CSS: Clock Security System interrupt -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RCC_ClearITPendingBit(u8 it) -{ - SET_BIT(RCC->CIR, (it << RCC_CIR_LSIRDYC_Pos)); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Forces or releases Low Speed APB (APB1) peripheral reset. -/// @param apb1_periph: specifies the APB1 peripheral to reset. -/// This parameter can be any combination of the following values: -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RCC_APB1PeriphReset(u32 apb1_periph) -{ - RCC->APB1RSTR |= apb1_periph; - RCC->APB1RSTR &= ~apb1_periph; -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Forces or releases Low Speed APB (APB2) peripheral reset. -/// @param apb2_periph: specifies the APB2 peripheral to reset. -/// This parameter can be any combination of the following values: -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RCC_APB2PeriphReset(u32 apb2_periph) -{ - RCC->APB2RSTR |= apb2_periph; - RCC->APB2RSTR &= ~apb2_periph; -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Forces or releases High Speed AHB (AHB1) peripheral reset. -/// @param ahb1_periph: specifies the AHB1 peripheral to reset. -/// This parameter can be any combination of the following values: -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RCC_AHBPeriphReset(u32 ahb1_periph) -{ - RCC->AHBRSTR |= ahb1_periph; - RCC->AHBRSTR &= ~ahb1_periph; -} -//////////////////////////////////////////////////////////////////////////////// -// -// New Function Interface -// -//////////////////////////////////////////////////////////////////////////////// - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Forces or releases Low Speed APB (APB1) peripheral reset. -/// @param apb1_periph: specifies the APB1 peripheral to reset. -/// This parameter can be any combination of the following values: -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void exRCC_APB1PeriphReset(u32 apb1_periph) -{ - RCC->APB1RSTR |= apb1_periph; - RCC->APB1RSTR &= ~apb1_periph; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief -/// @param -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void exRCC_BackupReset() -{ -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Forces or releases High Speed APB (APB2) peripheral reset. -/// @param apb2_periph: specifies the APB2 peripheral to reset. -/// This parameter can be any combination of the following values: -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void exRCC_APB2PeriphReset(u32 apb2_periph) -{ - RCC->APB2RSTR |= apb2_periph; - RCC->APB2RSTR &= ~apb2_periph; -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Forces or releases High Speed AHB (AHB1) peripheral reset. -/// @param ahb1_periph: specifies the AHB1 peripheral to reset. -/// This parameter can be any combination of the following values: -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void exRCC_AHBPeriphReset(u32 ahb1_periph) -{ - RCC->AHBRSTR |= ahb1_periph; - RCC->AHBRSTR &= ~ahb1_periph; -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Disable systick -/// @param None. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void exRCC_SystickDisable() -{ - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enable systick -/// @param None. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void exRCC_SystickEnable(u32 sys_tick_period) -{ - SysTick_Config(RCC_GetHCLKFreq() / 1000000 * sys_tick_period); -} - -/* -(state) ? (RCC->AHBENR |= ahb_periph) : (RCC->AHBENR &= ~ahb_periph); -(state) ? (RCC->APB1ENR |= apb1_periph) : (RCC->APB1ENR &= ~apb1_periph); -(state) ? (RCC->APB2ENR |= apb2_periph) : (RCC->APB2ENR &= ~apb2_periph); -*/ - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the specified ADC peripheral Clock. -/// @param peripheral:select the ADC peripheral. -/// @param state: new state of the ADC peripheral. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RCC_ADC_ClockCmd(ADC_TypeDef* peripheral, FunctionalState state) -{ - switch (*(vu32*)&peripheral) { - - case ADC1_BASE: - (state) ? (RCC->APB2ENR |= RCC_APB2ENR_ADC1) : (RCC->APB2ENR &= ~RCC_APB2ENR_ADC1); - break; - case ADC2_BASE: - (state) ? (RCC->APB2ENR |= RCC_APB2ENR_ADC2) : (RCC->APB2ENR &= ~RCC_APB2ENR_ADC2); - break; - case ADC3_BASE: - (state) ? (RCC->APB2ENR |= RCC_APB2ENR_ADC3) : (RCC->APB2ENR &= ~RCC_APB2ENR_ADC3); - break; - default: - break; - } - -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the specified BKP peripheral Clock. -/// @param peripheral:select the BKP peripheral. -/// @param state: new state of the BKP peripheral. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RCC_BKP_ClockCmd(BKP_TypeDef* peripheral, FunctionalState state) -{ - if(BKP == peripheral) { - (state) ? (RCC->APB1ENR |= RCC_APB1ENR_BKP) : (RCC->APB1ENR &= ~RCC_APB1ENR_BKP); - (state) ? (RCC->APB1ENR |= RCC_APB1ENR_PWR) : (RCC->APB1ENR &= ~RCC_APB1ENR_PWR); - } -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the specified CAN peripheral Clock. -/// @param peripheral:select the CAN peripheral. -/// @param state: new state of the CAN peripheral. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RCC_CAN_ClockCmd(CAN_TypeDef* peripheral, FunctionalState state) -{ - if(CAN1 == peripheral) { - (state) ? (RCC->APB1ENR |= RCC_APB1ENR_CAN) : (RCC->APB1ENR &= ~RCC_APB1ENR_CAN); - } -} - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the specified COMP peripheral Clock. -/// @param peripheral:select the COMP peripheral. -/// @param state: new state of the COMP peripheral. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RCC_COMP_ClockCmd(COMP_TypeDef* peripheral, FunctionalState state) -{ - if(COMP == peripheral) { - (state) ? (RCC->APB2ENR |= RCC_APB2ENR_COMP) : (RCC->APB2ENR &= ~RCC_APB2ENR_COMP); - } -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the specified CRC peripheral Clock. -/// @param peripheral:select the CRC peripheral. -/// @param state: new state of the CRC peripheral. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RCC_CRC_ClockCmd(CRC_TypeDef* peripheral, FunctionalState state) -{ - if(CRC == peripheral) { - (state) ? (RCC->AHBENR |= RCC_AHBENR_CRC) : (RCC->AHBENR &= ~RCC_AHBENR_CRC); - } -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the specified DAC peripheral Clock. -/// @param peripheral:select the DAC peripheral. -/// @param state: new state of the DAC peripheral. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RCC_DAC_ClockCmd(DAC_TypeDef* peripheral, FunctionalState state) -{ - if(DAC == peripheral) { - (state) ? (RCC->APB1ENR |= RCC_APB1ENR_DAC) : (RCC->APB1ENR &= ~RCC_APB1ENR_DAC); - } -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the specified DMA peripheral Clock. -/// @param peripheral:select the DMA peripheral. -/// @param state: new state of the DMA peripheral. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RCC_DMA_ClockCmd(DMA_TypeDef* peripheral, FunctionalState state) -{ - if(DMA1 == peripheral) { - (state) ? (RCC->AHBENR |= RCC_AHBENR_DMA1) : (RCC->AHBENR &= ~RCC_AHBENR_DMA1); - } - if(DMA2 == peripheral) { - (state) ? (RCC->AHBENR |= RCC_AHBENR_DMA2) : (RCC->AHBENR &= ~RCC_AHBENR_DMA2); - } -} - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the specified GPIO peripheral Clock. -/// @param peripheral:select the GPIO peripheral. -/// @param state: new state of the GPIO peripheral. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RCC_GPIO_ClockCmd(GPIO_TypeDef* peripheral, FunctionalState state) -{ - switch (*(vu32*)&peripheral) { - case (u32)GPIOA: - (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOA) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOA); - break; - case (u32)GPIOB: - (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOB) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOB); - break; - case (u32)GPIOC: - (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOC) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOC); - break; - case (u32)GPIOD: - (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOD) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOD); - break; - case (u32)GPIOE: - (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOE) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOE); - break; - case (u32)GPIOF: - (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOF) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOF); - break; - case (u32)GPIOG: - (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOG) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOG); - break; - case (u32)GPIOH: - (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOH) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOH); - break; - default: - break; - } -} - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Deinitializes the uart peripheral registers to their -/// default reset values. -/// @param peripheral: Select the UART or the UART peripheral. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RCC_UART_ClockCmd(UART_TypeDef* peripheral, FunctionalState state) -{ - if(UART2 == peripheral) { - (state) ? (RCC->APB1ENR |= RCC_APB1ENR_UART2) : (RCC->APB1ENR &= ~RCC_APB1ENR_UART2);//exRCC_APB1PeriphReset(RCC_APB1ENR_UART2); - } - if(UART1 == peripheral) { - (state) ? (RCC->APB2ENR |= RCC_APB2ENR_UART1) : (RCC->APB2ENR &= ~RCC_APB2ENR_UART1);//exRCC_APB2PeriphReset(RCC_APB2ENR_UART1); - } - if(UART3 == peripheral) { - (state) ? (RCC->APB1ENR |= RCC_APB1ENR_UART3) : (RCC->APB1ENR &= ~RCC_APB1ENR_UART3);//exRCC_APB1PeriphReset(RCC_APB1ENR_UART3); - } - if(UART4 == peripheral) { - (state) ? (RCC->APB1ENR |= RCC_APB1ENR_UART4) : (RCC->APB1ENR &= ~RCC_APB1ENR_UART4);//exRCC_APB1PeriphReset(RCC_APB1ENR_UART4); - } - if(UART5 == peripheral) { - (state) ? (RCC->APB1ENR |= RCC_APB1ENR_UART5) : (RCC->APB1ENR &= ~RCC_APB1ENR_UART5);//exRCC_APB1PeriphReset(RCC_APB1ENR_UART5); - } - if(UART6 == peripheral) { - (state) ? (RCC->APB2ENR |= RCC_APB2ENR_UART6) : (RCC->APB2ENR &= ~RCC_APB2ENR_UART6);//exRCC_APB2PeriphReset(RCC_APB2ENR_UART6); - } - if(UART7 == peripheral) { - (state) ? (RCC->APB1ENR |= RCC_APB1ENR_UART7) : (RCC->APB1ENR &= ~RCC_APB1ENR_UART7);//exRCC_APB1PeriphReset(RCC_APB1ENR_UART7); - } - if(UART8 == peripheral) { - (state) ? (RCC->APB1ENR |= RCC_APB1ENR_UART8) : (RCC->APB1ENR &= ~RCC_APB1ENR_UART8);//exRCC_APB1PeriphReset(RCC_APB1ENR_UART8); - } -} -/// @} - -/// @} - -/// @} diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rtc.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rtc.c deleted file mode 100644 index b02c6750b..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rtc.c +++ /dev/null @@ -1,234 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_rtc.c -/// @author AE TEAM -/// @brief THIS FILE PROVIDES ALL THE RTC FIRMWARE FUNCTIONS. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#define _HAL_RTC_C_ - -// Files includes -#include "hal_rtc.h" - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup RTC_HAL -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup RTC_Exported_Functions -/// @{ - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the specified RTC interrupts. -/// @param it: specifies the RTC interrupts sources to be enabled or -/// disabled. -/// This parameter can be any combination of the following values: -/// @arg RTC_IT_OW: Overflow interrupt -/// @arg RTC_IT_ALR: Alarm interrupt -/// @arg RTC_IT_SEC: Second interrupt -/// @param state: new state of the specified RTC interrupts. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RTC_ITConfig(RTC_IT_TypeDef it, FunctionalState state) -{ - (state == ENABLE) ? (RTC->CR |= it) : (RTC->CR &= (u16)~it); -// RTC_WaitForLastTask(); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enters the RTC configuration mode. -/// @param None. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RTC_EnterConfigMode(void) -{ -// PWR->CR |= PWR_CR_DBP; - RTC->CSR |= RTC_CSR_CNF; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Exits from the RTC configuration mode. -/// @param None. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RTC_ExitConfigMode(void) -{ - RTC->CSR &= ~RTC_CSR_CNF; - while (!(RTC->CSR & RTC_CSR_RTOFF)); -// PWR->CR &= ~PWR_CR_DBP; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Gets the RTC counter value. -/// @param None. -/// @retval RTC counter value. -//////////////////////////////////////////////////////////////////////////////// -u32 RTC_GetCounter(void) -{ - u32 dat = RTC->CNTH << 16; - return (RTC->CNTL | dat); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Sets the RTC counter value. -/// @param count: RTC counter new value. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RTC_SetCounter(u32 count) -{ - RTC_EnterConfigMode();//RTC->CSR |= RTC_CSR_CNF; - RTC->CNTH = count >> 16; - RTC->CNTL = count; - RTC_ExitConfigMode();//RTC->CSR &= ~RTC_CSR_CNF; -// while (!(RTC->CSR & RTC_CSR_RTOFF)); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Sets the RTC prescaler value. -/// @param prescaler: RTC prescaler new value. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RTC_SetPrescaler(u32 prescaler) -{ - RTC_EnterConfigMode();//RTC->CSR |= RTC_CSR_CNF; - RTC->PRLH = prescaler >> 16; - RTC->PRLL = prescaler; - RTC_ExitConfigMode();//RTC->CSR &= ~RTC_CSR_CNF; -// while (!(RTC->CSR & RTC_CSR_RTOFF)); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Sets the RTC alarm value. -/// @param alarm: RTC alarm new value. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RTC_SetAlarm(u32 alarm) -{ - RTC_EnterConfigMode();//RTC->CSR |= RTC_CSR_CNF; - RTC->ALRH = alarm >> 16; - RTC->ALRL = alarm; - RTC_ExitConfigMode();//RTC->CSR &= ~RTC_CSR_CNF; -// while (!(RTC->CSR & RTC_CSR_RTOFF)); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Gets the RTC divider value. -/// @param None. -/// @retval RTC Divider value. -//////////////////////////////////////////////////////////////////////////////// -u32 RTC_GetDivider(void) -{ - u32 dat = ((u32)(RTC->DIVH & RTC_DIVH_DIV) << 16); - return (RTC->DIVL | dat); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Waits until last write operation on RTC registers has finished. -/// @note This function must be called before any write to RTC registers. -/// @param None. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RTC_WaitForLastTask(void) -{ - while (!(RTC->CSR & RTC_CSR_RTOFF)); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL) -/// are synchronized with RTC APB clock. -/// @note This function must be called before any read operation after an APB -/// reset or an APB clock stop. -/// @param None. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RTC_WaitForSynchro(void) -{ - RTC->CSR &= ~RTC_CSR_RSF; - while (!(RTC->CSR & RTC_CSR_RSF)); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Checks whether the specified RTC flag is set or not. -/// @param flag: specifies the flag to check. -/// This parameter can be one the following values: -/// @arg RTC_FLAG_RTOFF: RTC Operation OFF flag -/// @arg RTC_FLAG_RSF: Registers Synchronized flag -/// @arg RTC_FLAG_OW: Overflow flag -/// @arg RTC_FLAG_ALR: Alarm flag -/// @arg RTC_FLAG_SEC: Second flag -/// @retval The state of RTC_FLAG (SET or RESET). -///////////////////////////////////////////////////////////////////////////////// -FlagStatus RTC_GetFlagStatus(RTC_FLAG_TypeDef flag) -{ - return (FlagStatus)(RTC->CSR & flag); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Clears the RTC's pending flags. -/// @param flag: specifies the flag to clear. -/// This parameter can be any combination of the following values: -/// @arg RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only -/// after an APB reset or an APB Clock stop. -/// @arg RTC_FLAG_OW: Overflow flag -/// @arg RTC_FLAG_ALR: Alarm flag -/// @arg RTC_FLAG_SEC: Second flag -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RTC_ClearFlag(RTC_FLAG_TypeDef flag) -{ - RTC->CSR &= ~flag; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Checks whether the specified RTC interrupt has occurred or not. -/// @param it: specifies the RTC interrupts sources to check. -/// This parameter can be one of the following values: -/// @arg RTC_IT_OW: Overflow interrupt -/// @arg RTC_IT_ALR: Alarm interrupt -/// @arg RTC_IT_SEC: Second interrupt -/// @retval The state of the RTC_IT (SET or RESET). -//////////////////////////////////////////////////////////////////////////////// -ITStatus RTC_GetITStatus(RTC_IT_TypeDef it) -{ - return (ITStatus)(RTC->CSR & it); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Clears the RTC's interrupt pending bits. -/// @param it: specifies the interrupt pending bit to clear. -/// This parameter can be any combination of the following values: -/// @arg RTC_IT_OW: Overflow interrupt -/// @arg RTC_IT_ALR: Alarm interrupt -/// @arg RTC_IT_SEC: Second interrupt -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void RTC_ClearITPendingBit(RTC_IT_TypeDef it) -{ -// RTC_EnterConfigMode();//RTC->CSR |= RTC_CSR_CNF; - RTC->CSR &= ~it; -// RTC_ExitConfigMode();//RTC->CSR &= ~RTC_CSR_CNF; -} - - -/// @} - -/// @} - -/// @} diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_sdio.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_sdio.c deleted file mode 100644 index 4b1bd70ee..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_sdio.c +++ /dev/null @@ -1,527 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_sdio.c -/// @author AE TEAM -/// @brief THIS FILE PROVIDES ALL THE SDIO FIRMWARE FUNCTIONS. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#define _HAL_SDIO_C_ -#include "reg_sdio.h" -#include "hal_sdio.h" -#include "hal_rcc.h" - - - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup SDIO_HAL -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup SDIO_Exported_Functions -/// @{ -//////////////////////////////////////////////////////////////////////////////// -/// @brief Deinitializes the SDIO peripheral registers to their default reset -/// values. -/// @param None. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void SDIO_DeInit(void) -{ - RCC_AHBPeriphResetCmd(RCC_AHBRSTR_SDIO, ENABLE); - RCC_AHBPeriphResetCmd(RCC_AHBRSTR_SDIO, DISABLE); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Fills each SDIO_InitStruct member with its default value. -/// @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which -/// will be initialized. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct) -{ - // SDIO_InitStruct members default value - SDIO_InitStruct->SDIO_MDEN = 0; - SDIO_InitStruct->SDIO_DATWT = 0; - SDIO_InitStruct->SDIO_SelPTSM = 0; - SDIO_InitStruct->SDIO_CLKSP = 0; - SDIO_InitStruct->SDIO_OUTM = 0; - SDIO_InitStruct->SDIO_SelSM = 0; - SDIO_InitStruct->SDIO_OPMSel = 0; -} - - -/// -/// @brief Fills each SDIO_DataInitStruct member with its default value. -/// @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure which -/// will be initialized. -/// @retval None -/// -void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct) -{ - /* SDIO_DataInitStruct members default value */ - SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF; - SDIO_DataInitStruct->SDIO_DataLength = 0x00; - SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b; - SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard; -// SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block; -// SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable; -} - -/// -/// @brief Initializes the SDIO data path according to the specified -/// parameters in the SDIO_DataInitStruct. -/// @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that -/// contains the configuration information for the SDIO command. -/// @retval None -/// -//void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct) -//{ -// u32 tmpreg = 0; - -// /*---------------------------- SDIO DTIMER Configuration ---------------------*/ -// /* Set the SDIO Data TimeOut value */ -// SDIO->MMC_TIMEOUTCNT = SDIO_DataInitStruct->SDIO_DataTimeOut; - -// /*---------------------------- SDIO DLEN Configuration -----------------------*/ -// /* Set the SDIO DataLength value */ -// SDIO->MMC_BYTECNTL = SDIO_DataInitStruct->SDIO_DataLength; - -// /*---------------------------- SDIO DCTRL Configuration ----------------------*/ -// /* Get the SDIO DCTRL value */ -// tmpreg = SDIO->DCTRL; -// /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */ -// tmpreg &= DCTRL_CLEAR_MASK; -// /* Set DEN bit according to SDIO_DPSM value */ -// /* Set DTMODE bit according to SDIO_TransferMode value */ -// /* Set DTDIR bit according to SDIO_TransferDir value */ -// /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */ -// tmpreg |= (u32)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir;// -// //| SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM; - -// /* Write to SDIO DCTRL */ -// SDIO->DCTRL = tmpreg; -//} -//////////////////////////////////////////////////////////////////////////////// -/// @brief The frequency division factor is configured to generate the SDIO clock. -/// @param value : 1MHz = Fhclk/((mmc_cardsel[5 : 0] + 1) × 2) -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void SDIO_ClockSet(u32 value) -{ -// SDIO->MMC_CARDSEL &= ~SDIO_MMC_CARDSEL_MASK; - SDIO->MMC_CARDSEL = (SDIO_MMC_CARDSEL_CTREN | SDIO_MMC_CARDSEL_ENPCLK | (value & 0x3F)); -// SDIO->MMC_CARDSEL = 0xC0+0x2F;//0xdf; -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Initializes the SDIO peripheral according to the specified -/// parameters in the SDIO_InitStruct. -/// @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure -/// that contains the configuration information for the SDIO peripheral. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct) -{ - SDIO->MMC_CTRL &= 0x700; - SDIO->MMC_CTRL |= (SDIO_InitStruct->SDIO_OPMSel | SDIO_InitStruct->SDIO_SelSM | - SDIO_InitStruct->SDIO_OUTM | SDIO_InitStruct->SDIO_CLKSP | - SDIO_InitStruct->SDIO_SelPTSM | SDIO_InitStruct->SDIO_DATWT | - SDIO_InitStruct->SDIO_MDEN); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the SDIO interrupts. -/// @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled. -/// state : new state of the specified SDIO interrupts. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void SDIO_ITConfig(u32 SDIO_IT, FunctionalState state) -{ - (state) ? (SDIO->MMC_INT_MASK |= SDIO_IT) : (SDIO->MMC_INT_MASK &= ~SDIO_IT); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the SDIO CRC. -/// @param SDIO_CRC: specifies the SDIO CRC sources to be enabled or disabled. -/// state : new state of the specified SDIO CRC. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void SDIO_CRCConfig(u32 SDIO_CRC, FunctionalState state) -{ - (state) ? (SDIO->MMC_CRCCTL |= SDIO_CRC) : (SDIO->MMC_CRCCTL &= ~SDIO_CRC); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Port transfer speed mode. -/// @param clkdiv : High/low speed. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void SDIO_Clock_Set(u8 clkdiv) -{ - SDIO->MMC_CTRL &= ~SDIO_MMC_CTRL_SelPTSM; - (clkdiv) ? (SDIO->MMC_CTRL |= SDIO_MMC_CTRL_SelPTSM) : (SDIO->MMC_CTRL &= ~SDIO_MMC_CTRL_SelPTSM); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Turn off the SDIO switch. -/// @param None. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -SD_Error SD_PowerOFF(void) -{ - SDIO->MMC_CARDSEL &= ~(SDIO_MMC_CARDSEL_ENPCLK | SDIO_MMC_CARDSEL_CTREN); - return SD_OK; -} -/// -/// @brief Fills each SDIO_CmdInitStruct member with its default value. -/// @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef -/// structure which will be initialized. -/// @retval None -/// -void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct) -{ - /* SDIO_CmdInitStruct members default value */ - SDIO_CmdInitStruct->SDIO_Argument = 0x00; - SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00; - SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No; - SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No; -// SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SDIO sends command functions. -/// @param cmdindex : Type the command. -/// waitrsp : Expected correspondence. -/// arg : parameter. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void SDIO_Send_Cmd(u8 cmdindex, u8 waitrsp, u32 arg) -{ - SDIO->CMD_BUF0 = (arg >> 0) & 0xFF; - SDIO->CMD_BUF1 = (arg >> 8) & 0xFF; - SDIO->CMD_BUF2 = (arg >> 16) & 0xFF; - SDIO->CMD_BUF3 = (arg >> 24) & 0xFF; - SDIO->CMD_BUF4 = 0x40 | cmdindex; - SDIO->CLR_MMC_INT |= 0; - SDIO->MMC_IO = SDIO_MMC_IO_AUTOTR; - while(1) { - if(SDIO->CLR_MMC_INT & SDIO_CLR_MMC_INT_CMDDMC) { - SDIO->CLR_MMC_INT |= SDIO_CLR_MMC_INT_CMDDMC; - break; - } - } - if(waitrsp == SDIO_Response_Short) { - SDIO->MMC_IO = SDIO_MMC_IO_AUTOCLKG | \ - SDIO_MMC_IO_AUTOTR | \ - SDIO_MMC_IO_RESPCMDSEL; - } - else if(waitrsp == SDIO_Response_Long) { - SDIO->MMC_IO = SDIO_MMC_IO_AUTOCLKG | \ - SDIO_MMC_IO_AUTOTR | \ - SDIO_MMC_IO_RESPCMDSEL | \ - SDIO_MMC_IO_CID_CSDRD; - } - else { - } -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Check the execution status of CMD0. -/// @param None. -/// @retval card error code. -//////////////////////////////////////////////////////////////////////////////// -SD_Error CmdError(void) -{ - SD_Error errorstatus = SD_OK; - u32 timeout = SDIO_CMD0TIMEOUT; - while (timeout--) { - if(((SDIO->MMC_IO & SDIO_MMC_IO_RESPCMDSEL) == 0) && ((SDIO->MMC_IO & SDIO_MMC_IO_AUTOTR) == 0)) - break; - } - if (timeout == 0) - return SD_CMD_RSP_TIMEOUT; - SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_MASK; - return errorstatus; -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Check the error status of the R1 response. -/// @param cmd : Current command. -/// @retval card error code. -//////////////////////////////////////////////////////////////////////////////// -SD_Error CmdResp1Error(u8 cmd) -{ - u32 status; - u32 response; - while(1) { - status = SDIO->CLR_MMC_INT ; - if(status & (SDIO_CLR_MMC_INT_CRCEMC | SDIO_CLR_MMC_INT_CRNTMC | SDIO_CLR_MMC_INT_CMDDMC)) - break; - } - if(status & SDIO_CLR_MMC_INT_CRNTMC) { - SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRNTMC; - return SD_CMD_RSP_TIMEOUT; - } - if(status & (SDIO_CLR_MMC_INT_CRCEMC)) { - SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRCEMC; - return SD_CMD_CRC_FAIL; - } - SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_MASK; - - if((SDIO->CMD_BUF4 & 0x3F) != cmd) { - return SD_ILLEGAL_CMD; - } - response = SDIO->CMD_BUF3 << 24 | SDIO->CMD_BUF2 << 16 | SDIO->CMD_BUF1 << 8 | SDIO->CMD_BUF0; - return (SD_Error)(response & SD_OCR_ERRORBITS); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Check the execution status of CMD2. -/// @param None. -/// @retval card error code. -//////////////////////////////////////////////////////////////////////////////// -SD_Error CmdResp2Error(void) -{ - SD_Error errorstatus = SD_OK; - u32 status; - u32 timeout = SDIO_CMD0TIMEOUT; - while(timeout--) { - status = SDIO->CLR_MMC_INT ; - if(status & (SDIO_CLR_MMC_INT_CRCEMC | SDIO_CLR_MMC_INT_CRNTMC | SDIO_CLR_MMC_INT_CMDDMC)) - break; - } - if((timeout == 0) || (status & SDIO_CLR_MMC_INT_CRNTMC)) { - errorstatus = SD_CMD_RSP_TIMEOUT; - SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRNTMC; - return errorstatus; - } - if(status & SDIO_CLR_MMC_INT_CRCEMC) { - errorstatus = SD_CMD_CRC_FAIL; - SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRCEMC; - } - SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_MASK; - return errorstatus; -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Check the execution status of CMD3. -/// @param None. -/// @retval card error code. -//////////////////////////////////////////////////////////////////////////////// -SD_Error CmdResp3Error(void) -{ - u32 status; - while(1) { - status = SDIO->CLR_MMC_INT ; - if(status & (SDIO_CLR_MMC_INT_CRCEMC | SDIO_CLR_MMC_INT_CRNTMC | SDIO_CLR_MMC_INT_CMDDMC)) - break; - } - if(status & SDIO_CLR_MMC_INT_CRNTMC) { - SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRNTMC; - return SD_CMD_RSP_TIMEOUT; - } - SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_MASK; - return SD_OK; -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Check the execution status of CMD6. -/// @param None. -/// @retval card error code. -//////////////////////////////////////////////////////////////////////////////// -SD_Error CmdResp6Error(u8 cmd, u16* prca) -{ - SD_Error errorstatus = SD_OK; - u32 status; - u32 rspr1; - while(1) { - status = SDIO->CLR_MMC_INT ; - if(status & (SDIO_CLR_MMC_INT_CRCEMC | SDIO_CLR_MMC_INT_CRNTMC | SDIO_CLR_MMC_INT_CMDDMC)) - break; - } - if(status & SDIO_CLR_MMC_INT_CRNTMC) { - SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRNTMC; - return SD_CMD_RSP_TIMEOUT; - } - if(status & SDIO_CLR_MMC_INT_CRCEMC) { - SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRCEMC; - return SD_CMD_CRC_FAIL; - } - if((SDIO->CMD_BUF4 & 0x3F) != cmd) { - return SD_ILLEGAL_CMD; - } - SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_MASK; - rspr1 = SDIO->CMD_BUF3 << 24 | SDIO->CMD_BUF2 << 16 | SDIO->CMD_BUF1 << 8 | SDIO->CMD_BUF0; - if(SD_ALLZERO == (rspr1 & (SD_R6_GENERAL_UNKNOWN_ERROR | SD_R6_ILLEGAL_CMD | SD_R6_COM_CRC_FAILED))) { - *prca = (u16)(rspr1 >> 16); - return errorstatus; - } - if(rspr1 & SD_R6_GENERAL_UNKNOWN_ERROR) { - return SD_GENERAL_UNKNOWN_ERROR; - } - if(rspr1 & SD_R6_ILLEGAL_CMD) { - return SD_ILLEGAL_CMD; - } - if(rspr1 & SD_R6_COM_CRC_FAILED) { - return SD_COM_CRC_FAILED; - } - return errorstatus; -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Check the execution status of CMD7. -/// @param None. -/// @retval card error code. -//////////////////////////////////////////////////////////////////////////////// -SD_Error CmdResp7Error(void) -{ - SD_Error errorstatus = SD_OK; - u32 status; - u32 timeout = SDIO_CMD0TIMEOUT; - while(timeout--) { - status = SDIO->CLR_MMC_INT ; - if(status & (SDIO_CLR_MMC_INT_CRCEMC | SDIO_CLR_MMC_INT_CRNTMC | SDIO_CLR_MMC_INT_CMDDMC)) - break; - } - if((timeout == 0) || (status & SDIO_CLR_MMC_INT_CRNTMC)) { //timeout - errorstatus = SD_CMD_RSP_TIMEOUT; - SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRNTMC; - return errorstatus; - } - if(status & SDIO_CLR_MMC_INT_CMDDMC) { - errorstatus = SD_OK; - SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CMDDMC; - } - return errorstatus; -} - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Write data direction block size configuration. -/// @param datatimeout : maximum latency. -/// datalen : data len -/// blksize : block count. -/// dir : direction -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void SDIO_Send_Data_Cfg(u32 datatimeout, u32 datalen, u8 blksize, u8 dir) -{ - u32 tmpreg, tmpreg1, tmpreg2 = 0; - tmpreg = SDIO->MMC_IO_MBCTL; - tmpreg1 = SDIO->MMC_IO; - tmpreg &= ~(SDIO_MMC_IO_MBCTL_BTSSel | SDIO_MMC_IO_MBCTL_SPMBDTR | SDIO_MMC_IO_MBCTL_SMBDTD); - if (datatimeout < 100) { - SDIO->MMC_TIMEOUTCNT = datatimeout; - } - else if (datatimeout < 10000) { - SDIO->MMC_TIMEOUTCNT = datatimeout / 100; - tmpreg |= SDIO_MMC_IO_MBCTL_BTSSel; - } - else if (datatimeout < 1000000) { - SDIO->MMC_TIMEOUTCNT = datatimeout / 10000; - tmpreg |= SDIO_MMC_IO_MBCTL_BTSSel_2; - } - else { - SDIO->MMC_TIMEOUTCNT = datatimeout / 1000000; - tmpreg |= SDIO_MMC_IO_MBCTL_BTSSel; - } - SDIO->MMC_BYTECNTL = datalen & 0x1FFFFFF; ; - SDIO->MMC_BLOCKCNT = blksize; - if (dir == 0) { - tmpreg |= SDIO_MMC_IO_MBCTL_SMBDTD; - tmpreg1 |= SDIO_MMC_IO_TRANSFDIR; - tmpreg2 |= SDIO_BUF_CTLL_SBAD; - } - else { - tmpreg &= ~(SDIO_MMC_IO_MBCTL_SMBDTD); - tmpreg1 &= ~(SDIO_MMC_IO_TRANSFDIR); - tmpreg2 &= ~(SDIO_BUF_CTLL_SBAD); - } - SDIO->MMC_IO_MBCTL = tmpreg; - SDIO->MMC_IO = tmpreg1; - SDIO->BUF_CTL = tmpreg2; -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Clears the SDIO's Flag pending bits. -/// @param SDIO_IT: specifies the flag pending bit to clear. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void SDIO_ClearFlag(u32 SDIO_FLAG) -{ - SDIO->CLR_MMC_INT |= SDIO_FLAG; -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Clears the SDIO's interrupt pending bits. -/// @param SDIO_IT: specifies the interrupt pending bit to clear. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void SDIO_ClearITPendingBit(u32 SDIO_IT) -{ - SDIO->CLR_MMC_INT |= SDIO_IT; -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Checks whether the specified SDIO flag is set or not. -/// @param SDIO_FLAG: specifies the flag to check. -/// @retval The new state of SDIO_FLAG (SET or RESET). -//////////////////////////////////////////////////////////////////////////////// -FlagStatus SDIO_GetFlagStatus(u32 SDIO_FLAG) -{ - return ((SDIO->CLR_MMC_INT & SDIO_FLAG) ? SET : RESET); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Reads the value of the data transfer timeout count -/// @param None. -/// @retval timeout count. -//////////////////////////////////////////////////////////////////////////////// -u32 SDIO_GetTimeOutCounter(void) -{ - return (SDIO->MMC_TIMEOUTCNT & 0xFF); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Read one data word from FIFO. -/// @param None. -/// @retval Data received. -//////////////////////////////////////////////////////////////////////////////// -u32 SDIO_ReadData(void) -{ - return SDIO->FIFO; -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Write one data word to FIFO. -/// @param tempbuff : Write data. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void SDIO_WriteData(u32 tempbuff) -{ - SDIO->FIFO = tempbuff; -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Returns number of remaining data bytes to be transferred. -/// @param None -/// @retval Number of remaining data bytes to be transferred -//////////////////////////////////////////////////////////////////////////////// -u32 SDIO_GetDataCounter(void) -{ - return SDIO->MMC_BYTECNTL; -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enable or Dsiable DMA . -/// @param tempbuff : Write data. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void SDIO_DMACmd(FunctionalState state) -{ - (state) ? ((SDIO->BUF_CTL |= SDIO_BUF_CTLL_DMAHEN), SDIO->BUF_CTL &= (~(SDIO_BUF_CTLL_DRM))) : (SDIO->BUF_CTL &= ~SDIO_BUF_CTLL_DMAHEN); -} - - -/// @} - -/// @} - -/// @} - diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_spi.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_spi.c deleted file mode 100644 index 3d8c286a3..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_spi.c +++ /dev/null @@ -1,648 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_spi.c -/// @author AE TEAM -/// @brief THIS FILE PROVIDES ALL THE SPI FIRMWARE FUNCTIONS. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#define _HAL_SPI_C_ -#include -// Files includes -#include "hal_spi.h" -#include "hal_rcc.h" - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup SPI_HAL -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -///@addtogroup SPI_Exported_Functions -///@{ - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Deinitializes the spi peripheral registers to their -/// default reset values. -/// @param spi: Select the SPI peripheral. -/// This parameter can be one of the following values: -/// SPI1, SPI2. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void SPI_DeInit(SPI_TypeDef* spi) -{ - switch (*(vu32*)&spi) { - case (u32)SPI2: // SPI2_BASE: - RCC_APB1PeriphResetCmd(RCC_APB1ENR_SPI2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1ENR_SPI2, DISABLE); - break; - case (u32)SPI3: // SPI3_BASE: - RCC_APB1PeriphResetCmd(RCC_APB1ENR_SPI3, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1ENR_SPI3, DISABLE); - break; - case (u32)SPI1: // SPI1_BASE: - RCC_APB2PeriphResetCmd(RCC_APB2ENR_SPI1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2ENR_SPI1, DISABLE); - break; - default: - break; - } -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Initializes the spi peripheral according to the specified -/// parameters in the init_struct . -/// @param spi: Select the SPI peripheral. -/// This parameter can be one of the following values: -/// SPI1, SPI2. -/// @param init_struct: pointer to a SPI_InitTypeDef structure -/// that contains the configuration information for the -/// specified SPI peripheral. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void SPI_Init(SPI_TypeDef* spi, SPI_InitTypeDef* init_struct) -{ - if (init_struct->SPI_DataSize == SPI_DataSize_32b) { - SET_BIT(spi->GCR, SPI_GCR_DWSEL); - } - else { - CLEAR_BIT(spi->GCR, SPI_GCR_DWSEL); - } - MODIFY_REG(spi->GCR, SPI_GCR_NSS, init_struct->SPI_NSS); - MODIFY_REG(spi->GCR, SPI_GCR_MODE, init_struct->SPI_Mode); - MODIFY_REG(spi->CCR, SPI_CCR_LSBFE, init_struct->SPI_FirstBit); - MODIFY_REG(spi->CCR, SPI_CCR_CPOL, init_struct->SPI_CPOL); - MODIFY_REG(spi->CCR, SPI_CCR_CPHA, init_struct->SPI_CPHA); - - SET_BIT(spi->CCR, SPI_CCR_SPILEN); - - MODIFY_REG(spi->BRR, BRR_Mask, init_struct->SPI_BaudRatePrescaler); - - if (init_struct->SPI_DataWidth >= 32) { - MODIFY_REG(spi->ECR, ECR_Mask, 0); - } - else { - MODIFY_REG(spi->ECR, ECR_Mask, init_struct->SPI_DataWidth); - } -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Fills each init_struct member with its default value. -/// @param init_struct: pointer to a SPI_InitTypeDef structure -/// which will be initialized. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void SPI_StructInit(SPI_InitTypeDef* init_struct) -{ - init_struct->SPI_Mode = SPI_Mode_Slave; - init_struct->SPI_DataSize = SPI_DataSize_8b; - init_struct->SPI_DataWidth = 8; - init_struct->SPI_CPOL = SPI_CPOL_Low; - init_struct->SPI_CPHA = SPI_CPHA_1Edge; - init_struct->SPI_NSS = SPI_NSS_Soft; - init_struct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; - init_struct->SPI_FirstBit = SPI_FirstBit_MSB; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the specified SPI peripheral. -/// @param spi: Select the SPI peripheral. -/// This parameter can be one of the following values: -/// SPI1, SPI2. -/// @param state: new state of the spi peripheral. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void SPI_Cmd(SPI_TypeDef* spi, FunctionalState state) -{ - (state) ? SET_BIT(spi->GCR, SPI_GCR_SPIEN) : CLEAR_BIT(spi->GCR, SPI_GCR_SPIEN); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the specified SPI interrupts. -/// @param spi: Select the SPI peripheral. -/// This parameter can be one of the following values:SPI1, SPI2. -/// @param interrupt: specifies the SPI interrupt sources to be -/// enabled or disabled. -/// This parameter can be one of the following values: -/// @arg SPI_IT_TXEPT: Transmitter empty interrupt -/// @arg SPI_IT_RXFULL: RX FIFO full interrupt -/// @arg SPI_IT_RXMATCH: Receive data match the RXDNR number interrupt -/// @arg SPI_IT_RXOERR: Receive overrun error interrupt -/// @arg SPI_IT_UNDERRUN: underrun interrupt -/// @arg SPI_IT_RX: Receive data available interrupt -/// @arg SPI_IT_TX: Transmit FIFO available interrupt -/// @param state: new state of the specified spi interrupts. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void SPI_ITConfig(SPI_TypeDef* spi, u8 interrupt, FunctionalState state) -{ - if (state) { - SET_BIT(spi->GCR, (u32)SPI_GCR_IEN); - SET_BIT(spi->IER, (u32)interrupt); - } - else { - CLEAR_BIT(spi->IER, interrupt); - CLEAR_BIT(spi->GCR, SPI_GCR_IEN); - } -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the SPI DMA interface. -/// @param spi: Select the SPI peripheral. -/// This parameter can be one of the following values: -/// SPI1, SPI2. -/// @param state: new state of the DMA Request sources. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void SPI_DMACmd(SPI_TypeDef* spi, FunctionalState state) -{ - (state) ? SET_BIT(spi->GCR, SPI_GCR_DMAEN) : CLEAR_BIT(spi->GCR, SPI_GCR_DMAEN); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief configure tn Fifo trigger level bit. -/// @param spi: Select the SPI peripheral. -/// This parameter can be one of the following values: -/// SPI1, SPI2. -/// @param fifo_trigger_value: specifies the Fifo trigger level -/// This parameter can be any combination of the following values: -/// SPI_TXTLF : SPI TX FIFO Trigger value set -/// SPI_RXTLF : SPI RX FIFO Trigger value set -/// @param state: new state of the selected SPI transfer request. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void SPI_FifoTrigger(SPI_TypeDef* spi, SPI_TLF_TypeDef fifo_trigger_value, FunctionalState state) -{ - (state) ? SET_BIT(spi->GCR, (u32)fifo_trigger_value) : CLEAR_BIT(spi->GCR, (u32)fifo_trigger_value); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Transmits a Data through the spi peripheral. -/// @param spi: Select the SPI peripheral. -/// This parameter can be one of the following values: -/// SPI1, SPI2. -/// @param data : Data to be transmitted. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void SPI_SendData(SPI_TypeDef* spi, u32 data) -{ - u16 templen; - __asm volatile("cpsid i"); - - WRITE_REG(spi->TDR, data); - - templen = READ_REG(spi->ECR); - if(templen == 0) - templen = 32; - if (templen > 8) - WRITE_REG(spi->TDR, data >> 8); - if (templen > 16) - WRITE_REG(spi->TDR, data >> 16); - if (templen > 24) - WRITE_REG(spi->TDR, data >> 24); - __asm volatile("cpsie i"); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Returns the most recent received data by the spi peripheral. -/// @param spi: Select the SPI peripheral. -/// This parameter can be one of the following values: -/// SPI1, SPI2. -/// @retval The value of the received data. -//////////////////////////////////////////////////////////////////////////////// -u32 SPI_ReceiveData(SPI_TypeDef* spi) -{ - u32 temp; - u8 templen; - __asm volatile("cpsid i"); - - temp = READ_REG(spi->RDR); - - templen = READ_REG(spi->ECR); - if(templen == 0) - templen = 32; - if (templen > 8) - temp |= (u32)(READ_REG(spi->RDR) << 8); - if (templen > 16) - temp |= (u32)(READ_REG(spi->RDR) << 16); - if (templen > 24) - temp |= (u32)(READ_REG(spi->RDR) << 24); - - __asm volatile("cpsie i"); - - return temp; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Slave chip csn single by selected -/// @param spi: Select the SPI peripheral. -/// This parameter can be one of the following values: -/// SPI1, SPI2. -/// @param state: new state of the selected SPI CS pin -/// request. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void SPI_CSInternalSelected(SPI_TypeDef* spi, FunctionalState state) -{ - (state) ? CLEAR_BIT(spi->NSSR, SPI_NSSR_NSS) : SET_BIT(spi->NSSR, SPI_NSSR_NSS); // illogical -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the NSS pin control mode for the selected SPI. -/// @param spi: Select the SPI peripheral. -/// This parameter can be one of the following values: -/// SPI1, SPI2. -/// @param nss: specifies the SPI NSS internal state. -/// This parameter can be one of the following values: -/// @arg SPI_NSS_Soft: NSS pin control by software -/// @arg SPI_NSS_Hard: NSS pin control by hardware -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* spi, SPI_NSS_TypeDef nss) -{ - (nss != SPI_NSS_Soft) ? SET_BIT(spi->GCR, SPI_NSS_Hard) : CLEAR_BIT(spi->GCR, SPI_NSS_Hard); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the data size for the selected SPI. -/// @param spi: Select the SPI peripheral. -/// This parameter can be one of the following values: -/// SPI1, SPI2. -/// @param data_size: specifies the SPI data size. -/// This parameter can be one of the following values: -/// 0 to 31, 0 = 32b, 1 = 1b, 2 = 2b -/// @arg DataSize : 0 to 31 -/// @retval None. -/// @retval None. -bool SPI_DataSizeConfig(SPI_TypeDef* spi, u8 data_size) -{ - if (data_size > 32) - return false; - data_size &= 0x1F; - WRITE_REG(spi->ECR, data_size); - return true; -} - -////////////////////////////////////////////////////////////////////////////////// -void SPI_DataSizeTypeConfig(SPI_TypeDef* spi, SPI_DataSize_TypeDef SPI_DataSize) -{ - CLEAR_BIT(spi->GCR, (u32)SPI_DataSize_32b); - SET_BIT(spi->GCR, (u32)SPI_DataSize); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Selects the data transfer direction in bi-directional mode -/// for the specified SPI. -/// @param spi: Select the SPI peripheral. -/// This parameter can be one of the following values: -/// SPI1, SPI2. -/// @param direction: specifies the data transfer direction in -/// bi-directional mode. -/// This parameter can be one of the following values: -/// @arg SPI_Direction_Tx: Selects Tx transmission direction -/// @arg SPI_Direction_Rx: Selects Rx receive direction -/// @arg SPI_Disable_Tx: Selects Rx receive direction -/// @arg SPI_Disable_Rx: Selects Rx receive direction -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void SPI_BiDirectionalLineConfig(SPI_TypeDef* spi, SPI_Direction_TypeDef direction) -{ - switch (direction) { - case SPI_Direction_Rx: - SET_BIT(spi->GCR, SPI_GCR_RXEN); - break; - case SPI_Direction_Tx: - SET_BIT(spi->GCR, SPI_GCR_TXEN); - break; - case SPI_Disable_Rx: - CLEAR_BIT(spi->GCR, SPI_GCR_RXEN); - break; - case SPI_Disable_Tx: - CLEAR_BIT(spi->GCR, SPI_GCR_TXEN); - break; - default: - break; - } -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Checks whether the specified SPI flag is set or not. -/// @param spi: Select the SPI peripheral. -/// This parameter can be one of the following values: -/// SPI1, SPI2. -/// @param flag: specifies the SPI flag to check. -/// This parameter can be one of the following values: -/// @arg SPI_FLAG_RXAVL: Rx buffer has bytes flag -/// @arg SPI_FLAG_TXEPT: Tx buffer and tx shifter empty flag -/// @arg SPI_FLAG_TXFULL: Tx buffer full flag -/// @arg SPI_FLAG_RXAVL_4BYTE: Receive available 4 byte data message flag. -/// @retval The new state of SPI_FLAG (SET or RESET). -//////////////////////////////////////////////////////////////////////////////// -FlagStatus SPI_GetFlagStatus(SPI_TypeDef* spi, SPI_FLAG_TypeDef flag) -{ -// u8 number; - return (spi->SR & flag) ? SET : RESET; -// if (spi->ECR == 8 || spi->ECR == 0) -// return (spi->SR & SPI_FLAG) ? SET : RESET; -// else { -// if ((spi->ECR > 0) && (spi->ECR <= 8)) -// number = 1; -// else if ((spi->ECR) <= 16) -// number = 2; -// else if ((spi->ECR) <= 24) -// number = 3; -// else if (((spi->ECR) <= 31) || (spi->ECR == 0)) -// number = 4; -// return (((spi->SR & 0xf00) >> 8) >= number) ? SET : RESET; -// } -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Checks whether the specified SPI interrupt has occurred or not. -/// @param spi: Select the SPI peripheral. -/// This parameter can be one of the following values: -/// SPI1, SPI2. -/// @param interrupt: specifies the SPI interrupt source to check. -/// This parameter can be one of the following values: -/// @arg SPI_IT_TX: Tx buffer empty interrupt -/// @arg SPI_IT_RX: Rx buffer interrupt -/// @arg SPI_IT_UNDERRUN: under Error interrupt in slave mode -/// @arg SPI_IT_RXOVER: RX OVER Error interrupt -/// @arg SPI_IT_RXMATCH: spectials rx data numbers interrupt -/// @arg SPI_IT_RXFULL: Rx buffer full interrupt -/// @arg SPI_IT_TXEPT: Tx buffer and tx shifter empty interrupt -/// @retval The new state of SPI_IT (SET or RESET). -//////////////////////////////////////////////////////////////////////////////// -ITStatus SPI_GetITStatus(SPI_TypeDef* spi, SPI_IT_TypeDef interrupt) -{ - return (spi->ISR & interrupt) ? SET : RESET; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Clears the spi interrupt pending bit. -/// @param spi: Select the SPI peripheral. -/// This parameter can be one of the following values: -/// SPI1, SPI2. -/// @param interrupt: specifies the SPI interrupt pending bit to clear. -/// @arg SPI_IT_TX: Tx buffer empty interrupt -/// @arg SPI_IT_RX: Rx buffer interrupt -/// @arg SPI_IT_UNDERRUN: under Error interrupt in slave mode -/// @arg SPI_IT_RXOVER: RX OVER Error interrupt -/// @arg SPI_IT_RXMATCH: spectials rx data numbers interrupt -/// @arg SPI_IT_RXFULL: Rx buffer full interrupt -/// @arg SPI_IT_TXEPT: Tx buffer and tx shifter empty interrupt -/// This function clears only ERR intetrrupt pending bit. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void SPI_ClearITPendingBit(SPI_TypeDef* spi, SPI_IT_TypeDef interrupt) -{ - SET_BIT(spi->ICR, interrupt); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SPI Hole a count Received bytes in next receive process. -/// @param spi: Select the SPI peripheral. -/// This parameter can be one of the following values: -/// SPI1, SPI2. -/// @param number: specifies the SPI receive Number. -/// This parament can be 1-65535. -/// This function can use only in SPI master single receive mode. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void SPI_RxBytes(SPI_TypeDef* spi, u16 number) -{ - WRITE_REG(spi->RDNR, number); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief slave mode tx data transmit phase adjust set. -/// @param spi: Select the SPI peripheral. -/// This parameter can be one of the following values: -/// SPI1, SPI2. -/// @param adjust_value: slave mode tx data transmit phase adjust enum. -/// This parament can be : -/// SPI_SlaveAdjust_FAST: fast speed use -/// SPI_SlaveAdjust_LOW: low speed use -/// This function can use only in SPI master single receive mode. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void SPI_SlaveAdjust(SPI_TypeDef* spi, SPI_SlaveAdjust_TypeDef adjust_value) -{ - (adjust_value) ? SET_BIT(spi->CCR, SPI_CCR_RXEDGE) : CLEAR_BIT(spi->CCR, SPI_CCR_RXEDGE); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables all SPI interrupts. -/// @param spi: Select the SPI peripheral. -/// This parameter can be one of the following values: -/// SPI1, SPI2. -/// @param state: new state of all spi interrupts. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void exSPI_ITCmd(SPI_TypeDef* spi, FunctionalState state) -{ - (state) ? SET_BIT(spi->IER, (u32)SPI_GCR_IEN) : CLEAR_BIT(spi->IER, (u32)SPI_GCR_IEN); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the specified SPI interrupts. -/// @param spi: Select the SPI peripheral. -/// This parameter can be one of the following values: -/// SPI1, SPI2. -/// @param interrupt: specifies the SPI interrupt sources to be enabled or disabled. -/// This parameter can be one of the following values: -/// @arg SPI_IT_TXEPT: Transmitter empty interrupt -/// @arg SPI_IT_RXFULL: RX FIFO full interrupt -/// @arg SPI_IT_RXMATCH: Receive data match the RXDNR number interrupt -/// @arg SPI_IT_RXOERR: Receive overrun error interrupt -/// @arg SPI_IT_UNDERRUN: underrun interrupt -/// @arg SPI_IT_RX: Receive data available interrupt -/// @arg SPI_IT_TX: Transmit FIFO available interrupt -/// @param state: new state of the specified spi interrupts. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void exSPI_ITConfig(SPI_TypeDef* spi, SPI_IT_TypeDef interrupt, FunctionalState state) -{ - (state) ? SET_BIT(spi->IER, (u32)interrupt) : CLEAR_BIT(spi->IER, (u32)interrupt); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the SPI DMA request. -/// @param spi: Select the SPI peripheral. -/// This parameter can be one of the following values: -/// SPI1, SPI2. -/// @param state: new state of the DMA Request. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void exSPI_DMACmd(SPI_TypeDef* spi, FunctionalState state) -{ - (state) ? SET_BIT(spi->GCR, SPI_GCR_DMAEN) : CLEAR_BIT(spi->GCR, SPI_GCR_DMAEN); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Set or reset Slave chip csn signal output -/// @param spi: Select the SPI peripheral. -/// This parameter can be one of the following values: -/// SPI1, SPI2. -/// @param state: new state of Slave chip csn signal output. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void exSPI_CSInternalSelected(SPI_TypeDef* spi, FunctionalState state) -{ - (state) ? CLEAR_BIT(spi->NSSR, SPI_NSSR_NSS) : SET_BIT(spi->NSSR, SPI_NSSR_NSS); // illogical -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief tx data and rx data phase adjust. -/// @param spi: Select the SPI peripheral. -/// This parameter can be one of the following values: -/// SPI1, SPI2. -/// @param adjust_value: choose adjust mode. -/// This parament can be : -/// SPI_DataEdgeAdjust_LOW, -/// SPI_DataEdgeAdjust_FAST -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void exSPI_DataEdgeAdjust(SPI_TypeDef* spi, SPI_DataEdgeAdjust_TypeDef adjust_value) -{ - // master mode - if (spi->GCR & SPI_GCR_MODE) { - adjust_value ? SET_BIT(spi->CCR, SPI_CCR_RXEDGE) : CLEAR_BIT(spi->CCR, SPI_CCR_RXEDGE); - } - // slave mode - else { - adjust_value ? SET_BIT(spi->CCR, SPI_CCR_TXEDGE) : CLEAR_BIT(spi->CCR, SPI_CCR_TXEDGE); - } -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Set or reset i2s -/// @param spi: Select the SPI peripheral. -/// This parameter can be one of the following values: -/// SPI1, SPI2, SPI3. -/// @param state: new state of Slave chip csn signal output. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void I2S_Cmd(SPI_TypeDef* spi, FunctionalState state) -{ - (state) ? SET_BIT(spi->CFGR, I2S_CFGR_SPI_I2S) : CLEAR_BIT(spi->CFGR, I2S_CFGR_SPI_I2S); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief i2s Config -/// @param spi: Select the SPI peripheral. -/// This parameter can be one of the following values: -/// SPI1, SPI2, SPI3. -/// @param state: new state of Slave chip csn signal output. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void I2S_Init(SPI_TypeDef* spi, I2S_InitTypeDef* I2S_InitStruct) -{ - u32 i2sdiv = 2; - u32 tmpreg = 0; - u32 packetlength = 1; - u32 result = 0, yushu = 0; - u32 sourceclock = 0; - RCC_ClocksTypeDef RCC_Clocks; - - if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) { - i2sdiv = 2; - } - else { - if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) { - packetlength = 1; - } - else { - packetlength = 2; - } - RCC_GetClocksFreq(&RCC_Clocks); - - if((SPI2 == spi) || (SPI3 == spi)) { - sourceclock = RCC_Clocks.PCLK1_Frequency; - } - else { - sourceclock = RCC_Clocks.PCLK2_Frequency; - } - if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) { - result = (sourceclock) / (256 * (I2S_InitStruct->I2S_AudioFreq)); - yushu = (sourceclock) % (256 * (I2S_InitStruct->I2S_AudioFreq)); - if(yushu > (128 * (I2S_InitStruct->I2S_AudioFreq))) { - result = result + 1; - } - i2sdiv = result; - if ((i2sdiv < 2) || (i2sdiv > 0x1FF)) { - i2sdiv = 2; - } - } - else { - result = (sourceclock) / (16 * 2 * packetlength * (I2S_InitStruct->I2S_AudioFreq)); - yushu = (sourceclock) % (16 * 2 * packetlength * (I2S_InitStruct->I2S_AudioFreq)); - if(yushu > ((16 * packetlength * (I2S_InitStruct->I2S_AudioFreq)))) { - result = result + 1; - } - if ((i2sdiv < 1) || (i2sdiv > 0x1FF)) { - i2sdiv = 1; - } - } - } - if(I2S_CPOL_High == I2S_InitStruct->I2S_CPOL) { - spi->CCTL |= SPI_CCR_CPOL; - } - else { - spi->CCTL &= ~SPI_CCR_CPOL; - } - - spi->CFGR = 0x2 << I2S_CFGR_I2SDIV_Pos; - - if((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterTx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_MasterRx)) { - spi->GCTL |= SPI_GCR_MODE; - } - else { - spi->GCTL &= ~SPI_GCR_MODE; - } - if((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterTx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveTx)) { - spi->GCTL |= SPI_GCR_TXEN; - spi->GCTL &= ~SPI_GCR_RXEN; - } - else { - spi->GCTL &= ~SPI_GCR_TXEN; - spi->GCTL |= SPI_GCR_RXEN; - } -// tmpreg = spi->GCTL; -// tmpreg &= ~(1 << 2); -// tmpreg |= (u16)(I2S_InitStruct->I2S_Mode); -// spi->GCTL = tmpreg; -// - tmpreg = 0; - tmpreg |= (i2sdiv << I2S_CFGR_I2SDIV_Pos) | \ - (I2S_InitStruct->I2S_MCLKOutput) | \ - (I2S_CFGR_SPI_I2S) | \ - (I2S_InitStruct->I2S_Standard) | \ - (I2S_InitStruct->I2S_DataFormat); - spi->CFGR &= ~I2S_CFGR_I2SDIV; - spi->CFGR |= tmpreg; - -} -/// @} - -/// @} - -/// @} diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_tim.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_tim.c deleted file mode 100644 index e798bc46a..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_tim.c +++ /dev/null @@ -1,1875 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_tim.c -/// @author AE TEAM -/// @brief THIS FILE PROVIDES ALL THE TIM FIRMWARE FUNCTIONS. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#define _HAL_TIM_C_ - -// Files includes -#include "hal_rcc.h" -#include "hal_tim.h" - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup TIM_HAL -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup TIM_Exported_Functions -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Deinitializes the tim peripheral registers to their default reset values. -/// @param tim: select the TIM peripheral. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_DeInit(TIM_TypeDef* tim) -{ - switch (*(vu32*)&tim) { - case (u32)TIM1: - exRCC_APB2PeriphReset(RCC_APB2ENR_TIM1); - break; - case (u32)TIM2: - exRCC_APB1PeriphReset(RCC_APB1ENR_TIM2); - break; - case (u32)TIM3: - exRCC_APB1PeriphReset(RCC_APB1ENR_TIM3); - break; - case (u32)TIM4: - exRCC_APB1PeriphReset(RCC_APB1ENR_TIM4); - break; - - case (u32)TIM5: - exRCC_APB1PeriphReset(RCC_APB1ENR_TIM5); - break; - case (u32)TIM6: - exRCC_APB1PeriphReset(RCC_APB1ENR_TIM6); - break; - case (u32)TIM7: - exRCC_APB1PeriphReset(RCC_APB1ENR_TIM7); - break; - - case (u32)TIM8: - exRCC_APB2PeriphReset(RCC_APB2ENR_TIM8); - break; - - default: - break; - } -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Initializes the tim Time Base Unit peripheral according to -/// the specified parameters in the init_struct. -/// @param tim: select the TIM peripheral. -/// @param init_struct: pointer to a TIM_TimeBaseInitTypeDef -/// structure that contains the configuration information for the -/// specified TIM peripheral. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_TimeBaseInit(TIM_TypeDef* tim, TIM_TimeBaseInitTypeDef* init_struct) -{ - MODIFY_REG(tim->CR1, TIM_CR1_CKD, init_struct->TIM_ClockDivision); - - if ((tim == TIM1) || (tim == TIM2) || (tim == TIM3) || (tim == TIM4) || (tim == TIM5) || (tim == TIM8)) - MODIFY_REG(tim->CR1, TIM_CR1_CMS | TIM_CR1_DIR, init_struct->TIM_CounterMode); - - if ((tim == TIM1) || (tim == TIM8) ) - - MODIFY_REG(tim->RCR, TIM_RCR_REP, init_struct->TIM_RepetitionCounter); - - WRITE_REG(tim->ARR, init_struct->TIM_Period); - WRITE_REG(tim->PSC, init_struct->TIM_Prescaler); - WRITE_REG(tim->EGR, TIM_PSCReloadMode_Immediate); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Initializes the tim Channel1 according to the specified -/// parameters in the init_struct. -/// @param tim: select the TIM peripheral. -/// @param init_struct: pointer to a TIM_OCInitTypeDef structure that -/// contains the configuration information for the specified TIM peripheral. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_OC1Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct) -{ - MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC1M, init_struct->TIM_OCMode); - MODIFY_REG(tim->CCER, TIM_CCER_CC1P | TIM_CCER_CC1EN, \ - ((u32)init_struct->TIM_OCPolarity) | ((u32)init_struct->TIM_OutputState)); - WRITE_REG(tim->CCR1, init_struct->TIM_Pulse); - - if ((tim == TIM1) || (tim == TIM8)) { - MODIFY_REG(tim->CCER, TIM_CCER_CC1NP | TIM_CCER_CC1NEN, \ - ((u32)init_struct->TIM_OCNPolarity) | ((u32)init_struct->TIM_OutputNState)); - MODIFY_REG(tim->CR2, TIM_CR2_OIS1 | TIM_CR2_OIS1N, \ - ((u32)init_struct->TIM_OCIdleState) | ((u32)init_struct->TIM_OCNIdleState)); - } -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Initializes the tim Channel2 according to the specified -/// parameters in the init_struct. -/// @param tim: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. -/// @param init_struct: pointer to a TIM_OCInitTypeDef structure that -/// contains the configuration information for the specified TIM peripheral. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_OC2Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct) -{ - MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC2M, init_struct->TIM_OCMode << 8); - MODIFY_REG(tim->CCER, TIM_CCER_CC2EN | TIM_CCER_CC2P, \ - (init_struct->TIM_OCPolarity << 4) | (init_struct->TIM_OutputState << 4)); - WRITE_REG(tim->CCR2, init_struct->TIM_Pulse); - - if ((tim == TIM1) || (tim == TIM8)) { - MODIFY_REG(tim->CCER, TIM_CCER_CC2NP | TIM_CCER_CC2NEN, \ - (init_struct->TIM_OCNPolarity << 4) | (init_struct->TIM_OutputNState << 4)); - MODIFY_REG(tim->CR2, TIM_CR2_OIS2 | TIM_CR2_OIS2N, \ - (init_struct->TIM_OCIdleState << 2) | (init_struct->TIM_OCNIdleState << 2)); - } -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Initializes the tim Channel3 according to the specified -/// parameters in the init_struct. -/// @param tim: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. -/// @param init_struct: pointer to a TIM_OCInitTypeDef structure that -/// contains the configuration information for the specified TIM peripheral. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_OC3Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct) -{ - MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC3M, init_struct->TIM_OCMode); - MODIFY_REG(tim->CCER, TIM_CCER_CC3EN | TIM_CCER_CC3P, \ - (init_struct->TIM_OCPolarity << 8) | (init_struct->TIM_OutputState << 8)); - WRITE_REG(tim->CCR3, init_struct->TIM_Pulse); - - if ((tim == TIM1) || (tim == TIM8)) { - MODIFY_REG(tim->CCER, TIM_CCER_CC3NP | TIM_CCER_CC3NEN, \ - (init_struct->TIM_OCNPolarity << 8) | (init_struct->TIM_OutputNState << 8)); - MODIFY_REG(tim->CR2, TIM_CR2_OIS3 | TIM_CR2_OIS3N, \ - (init_struct->TIM_OCIdleState << 4) | (init_struct->TIM_OCNIdleState << 4)); - } -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Initializes the tim Channel4 according to the specified -/// parameters in the init_struct. -/// @param tim:select the TIM peripheral. -/// @param init_struct: pointer to a TIM_OCInitTypeDef structure that -/// contains the configuration information for the specified TIM peripheral. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_OC4Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct) -{ - MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC4M, (init_struct->TIM_OCMode) << 8); - MODIFY_REG(tim->CCER, TIM_CCER_CC4EN | TIM_CCER_CC4P, \ - (init_struct->TIM_OCPolarity << 12) | (init_struct->TIM_OutputState << 12)); - WRITE_REG(tim->CCR4, init_struct->TIM_Pulse); - - if ((tim == TIM1) || (tim == TIM8)) - MODIFY_REG(tim->CR2, TIM_CR2_OIS4, init_struct->TIM_OCIdleState << 6); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Initializes the TIM peripheral according to the specified -/// parameters in the init_struct. -/// @param tim: select the TIM peripheral. -/// @param init_struct: pointer to a TIM_ICInitTypeDef structure that -/// contains the configuration information for the specified TIM peripheral. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_ICInit(TIM_TypeDef* tim, TIM_ICInitTypeDef* init_struct) -{ - switch (init_struct->TIM_Channel) { - case TIM_Channel_1: - TI1_Configure(tim, init_struct->TIM_ICPolarity, init_struct->TIM_ICSelection, init_struct->TIM_ICFilter); - TIM_SetIC1Prescaler(tim, init_struct->TIM_ICPrescaler); - break; - case TIM_Channel_2: - TI2_Configure(tim, init_struct->TIM_ICPolarity, init_struct->TIM_ICSelection, init_struct->TIM_ICFilter); - TIM_SetIC2Prescaler(tim, init_struct->TIM_ICPrescaler); - break; - case TIM_Channel_3: - TI3_Configure(tim, init_struct->TIM_ICPolarity, init_struct->TIM_ICSelection, init_struct->TIM_ICFilter); - TIM_SetIC3Prescaler(tim, init_struct->TIM_ICPrescaler); - break; - case TIM_Channel_4: - TI4_Configure(tim, init_struct->TIM_ICPolarity, init_struct->TIM_ICSelection, init_struct->TIM_ICFilter); - TIM_SetIC4Prescaler(tim, init_struct->TIM_ICPrescaler); - break; - default: - break; - } -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the TIM peripheral according to the specified -/// parameters in the init_struct to measure an external PWM signal. -/// @param tim: select the TIM peripheral. -/// @param init_struct: pointer to a TIM_ICInitTypeDef structure that -/// contains the configuration information for the specified TIM peripheral. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_PWMIConfig(TIM_TypeDef* tim, TIM_ICInitTypeDef* init_struct) -{ - u16 icoppositepolarity = TIM_ICPolarity_Rising; - u16 icoppositeselection = TIM_ICSelection_DirectTI; - icoppositepolarity = (init_struct->TIM_ICPolarity == TIM_ICPolarity_Rising) ? TIM_ICPolarity_Falling : TIM_ICPolarity_Rising; - icoppositeselection = - (init_struct->TIM_ICSelection == TIM_ICSelection_DirectTI) ? TIM_ICSelection_IndirectTI : TIM_ICSelection_DirectTI; - if (init_struct->TIM_Channel == TIM_Channel_1) { - TI1_Configure(tim, init_struct->TIM_ICPolarity, init_struct->TIM_ICSelection, init_struct->TIM_ICFilter); - TIM_SetIC1Prescaler(tim, init_struct->TIM_ICPrescaler); - TI2_Configure(tim, icoppositepolarity, icoppositeselection, init_struct->TIM_ICFilter); - TIM_SetIC2Prescaler(tim, init_struct->TIM_ICPrescaler); - } - else { - TI2_Configure(tim, init_struct->TIM_ICPolarity, init_struct->TIM_ICSelection, init_struct->TIM_ICFilter); - TIM_SetIC2Prescaler(tim, init_struct->TIM_ICPrescaler); - TI1_Configure(tim, icoppositepolarity, icoppositeselection, init_struct->TIM_ICFilter); - TIM_SetIC1Prescaler(tim, init_struct->TIM_ICPrescaler); - } -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the: Break feature, dead time, Lock level, the OSSI, -/// the OSSR State and the AOE(automatic output enable). -/// @param tim: select the TIM -/// @param init_struct: pointer to a TIM_BDTRInitTypeDef structure that -/// contains the BDTR Register configuration information for the TIM peripheral. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_BDTRConfig(TIM_TypeDef* tim, TIM_BDTRInitTypeDef* init_struct) -{ - tim->BDTR = (u32)init_struct->TIM_OSSRState | init_struct->TIM_OSSIState | init_struct->TIM_LOCKLevel | - init_struct->TIM_DeadTime | init_struct->TIM_Break | init_struct->TIM_BreakPolarity | - init_struct->TIM_AutomaticOutput; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Fills each init_struct member with its default value. -/// @param init_struct : pointer to a TIM_TimeBaseInitTypeDef -/// structure which will be initialized. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* init_struct) -{ - init_struct->TIM_Period = 0xFFFFFFFF; - init_struct->TIM_Prescaler = 0x0000; - init_struct->TIM_ClockDivision = TIM_CKD_DIV1; - init_struct->TIM_CounterMode = TIM_CounterMode_Up; - init_struct->TIM_RepetitionCounter = 0x00; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Fills each init_struct member with its default value. -/// @param init_struct : pointer to a TIM_OCInitTypeDef structure which will -/// be initialized. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_OCStructInit(TIM_OCInitTypeDef* init_struct) -{ - init_struct->TIM_OCMode = TIM_OCMode_Timing; - init_struct->TIM_OutputState = TIM_OutputState_Disable; - init_struct->TIM_OutputNState = TIM_OutputNState_Disable; - init_struct->TIM_Pulse = 0x00000000; - init_struct->TIM_OCPolarity = TIM_OCPolarity_High; - init_struct->TIM_OCNPolarity = TIM_OCNPolarity_High; - init_struct->TIM_OCIdleState = TIM_OCIdleState_Reset; - init_struct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Fills each init_struct member with its default value. -/// @param init_struct: pointer to a TIM_ICInitTypeDef structure which will -/// be initialized. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_ICStructInit(TIM_ICInitTypeDef* init_struct) -{ - init_struct->TIM_Channel = TIM_Channel_1; - init_struct->TIM_ICPolarity = TIM_ICPolarity_Rising; - init_struct->TIM_ICSelection = TIM_ICSelection_DirectTI; - init_struct->TIM_ICPrescaler = TIM_ICPSC_DIV1; - init_struct->TIM_ICFilter = 0x00; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Fills each init_struct member with its default value. -/// @param init_struct: pointer to a TIM_BDTRInitTypeDef structure which -/// will be initialized. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* init_struct) -{ - init_struct->TIM_OSSRState = TIM_OSSRState_Disable; - init_struct->TIM_OSSIState = TIM_OSSIState_Disable; - init_struct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; - init_struct->TIM_DeadTime = 0x00; - init_struct->TIM_Break = TIM_Break_Disable; - init_struct->TIM_BreakPolarity = TIM_BreakPolarity_Low; - init_struct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the specified TIM peripheral. -/// @param tim: where x can be 1 to 17 to select the tim peripheral. -/// @param state: new state of the tim peripheral. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_Cmd(TIM_TypeDef* tim, FunctionalState state) -{ - (state) ? SET_BIT(tim->CR1, TIM_CR1_CEN) : CLEAR_BIT(tim->CR1, TIM_CR1_CEN); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the TIM peripheral Main Outputs. -/// @param tim: where x can be 1, 8, 16 or 17 to select the tim peripheral. -/// @param state: new state of the TIM peripheral Main Outputs. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_CtrlPWMOutputs(TIM_TypeDef* tim, FunctionalState state) -{ - (state) ? SET_BIT(tim->BDTR, TIM_BDTR_MOEN) : CLEAR_BIT(tim->BDTR, TIM_BDTR_MOEN); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the specified TIM interrupts. -/// @param tim: select the tim peripheral. -/// @param it: specifies the TIM interrupts sources to be enabled or disabled. -/// This parameter can be any combination of the following values: -/// @arg TIM_IT_Update: TIM update Interrupt source -/// @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source -/// @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source -/// @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source -/// @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source -/// @arg TIM_IT_COM: TIM Commutation Interrupt source -/// @arg TIM_IT_Trigger: TIM Trigger Interrupt source -/// @arg TIM_IT_Break: TIM Break Interrupt source -/// @note -/// - Partial timer can have TIM_IT_Update or TIM_IT_CC1. -/// - TIM_IT_Break is used only with partial timer. -/// - TIM_IT_COM is used only with partial timer. -/// @param state: new state of the TIM interrupts. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_ITConfig(TIM_TypeDef* tim, u32 it, FunctionalState state) //TIMIT_TypeDef -{ - (state) ? SET_BIT(tim->DIER, it) : CLEAR_BIT(tim->DIER, it); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the tim event to be generate by software. -/// @param tim: select the TIM peripheral. -/// @param source: specifies the event source. -/// This parameter can be one or more of the following values: -/// @arg TIM_EventSource_Update: Timer update Event source -/// @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source -/// @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source -/// @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source -/// @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source -/// @arg TIM_EventSource_COM: Timer COM event source -/// @arg TIM_EventSource_Trigger: Timer Trigger Event source -/// @arg TIM_EventSource_Break: Timer Break event source -/// @note -/// - TIM_EventSource_COM and TIM_EventSource_Break are used only with partial timer. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_GenerateEvent(TIM_TypeDef* tim, TIMEGR_Typedef source) -{ - WRITE_REG(tim->EGR, source); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the tim's DMA interface. -/// @param tim: select the TIM peripheral. -/// @param dma_base: DMA Base address. -/// This parameter can be one of the following values: -/// @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR, -/// TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR, -/// TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER, -/// TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR, -/// TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2, -/// TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR, -/// TIM_DMABase_DCR. -/// @param length: DMA Burst length. -/// This parameter can be one value between: -/// TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_DMAConfig(TIM_TypeDef* tim, TIMDMABASE_Typedef dma_base, TIMDMABURSTLENGTH_Typedef length) -{ - WRITE_REG(tim->DCR, ((u32)dma_base) | ((u32)length)); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the tim's DMA Requests. -/// @param tim: select the TIM peripheral. -/// @param source: specifies the DMA Request sources. -/// This parameter can be any combination of the following values: -/// @arg TIM_DMA_Update: TIM update Interrupt source -/// @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source -/// @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source -/// @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source -/// @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source -/// @arg TIM_DMA_COM: TIM Commutation DMA source -/// @arg TIM_DMA_Trigger: TIM Trigger DMA source -/// @param state: new state of the DMA Request sources. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_DMACmd(TIM_TypeDef* tim, TIMDMASRC_Typedef source, FunctionalState state) -{ - (state) ? SET_BIT(tim->DIER, source) : CLEAR_BIT(tim->DIER, source); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the tim internal Clock -/// @param tim: select the TIM peripheral. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_InternalClockConfig(TIM_TypeDef* tim) -{ - CLEAR_BIT(tim->SMCR, TIM_SMCR_SMS); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the tim Internal Trigger as External Clock -/// @param tim: select the TIM peripheral. -/// @param source: Trigger source. -/// This parameter can be one of the following values: -/// @arg TIM_TS_ITR0: Internal Trigger 0 -/// @arg TIM_TS_ITR1: Internal Trigger 1 -/// @arg TIM_TS_ITR2: Internal Trigger 2 -/// @arg TIM_TS_ITR3: Internal Trigger 3 -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_ITRxExternalClockConfig(TIM_TypeDef* tim, TIMTS_TypeDef source) -{ - TIM_SelectInputTrigger(tim, source); - SET_BIT(tim->SMCR, TIM_SlaveMode_External1); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the tim Trigger as External Clock -/// @param tim: select the TIM peripheral. -/// @param source: Trigger source. -/// This parameter can be one of the following values: -/// @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector -/// @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1 -/// @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2 -/// @param polarity: specifies the TIx Polarity. -/// This parameter can be one of the following values: -/// @arg TIM_ICPolarity_Rising -/// @arg TIM_ICPolarity_Falling -/// @param filter : specifies the filter value. -/// This parameter must be a value between 0x0 and 0xF. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_TIxExternalClockConfig(TIM_TypeDef* tim, TIM_TIEXTCLKSRC_Typedef source, TIMICP_Typedef polarity, u16 filter) -{ - (source == TIM_TIxExternalCLK1Source_TI2) ? (TI2_Configure(tim, polarity, TIM_ICSelection_DirectTI, filter)) - : (TI1_Configure(tim, polarity, TIM_ICSelection_DirectTI, filter)); - TIM_SelectInputTrigger(tim, (TIMTS_TypeDef)source); - SET_BIT(tim->SMCR, TIM_SlaveMode_External1); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the tim External Trigger (ETR). -/// @param tim: select the TIM peripheral. -/// @param psc: The external Trigger Prescaler. -/// This parameter can be one of the following values: -/// @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. -/// @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. -/// @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. -/// @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. -/// @param polarity: The external Trigger Polarity. -/// This parameter can be one of the following values: -/// @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. -/// @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. -/// @param filter: External Trigger Filter. -/// This parameter must be a value between 0x00 and 0x0F -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_ETRConfig(TIM_TypeDef* tim, TIMEXTTRGPSC_Typedef psc, TIMETP_Typedef polarity, u16 filter) -{ - CLEAR_BIT(tim->SMCR, TIM_SMCR_ECEN); - MODIFY_REG(tim->SMCR, TIM_SMCR_ETP, polarity); - MODIFY_REG(tim->SMCR, TIM_SMCR_ETPS, psc); - MODIFY_REG(tim->SMCR, TIM_SMCR_ETF, filter << 8); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the External clock Mode1 -/// @param tim: select the TIM peripheral. -/// @param psc: The external Trigger Prescaler. -/// This parameter can be one of the following values: -/// @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. -/// @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. -/// @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. -/// @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. -/// @param polarity: The external Trigger Polarity. -/// This parameter can be one of the following values: -/// @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. -/// @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. -/// @param filter: External Trigger Filter. -/// This parameter must be a value between 0x00 and 0x0F -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_ETRClockMode1Config(TIM_TypeDef* tim, TIMEXTTRGPSC_Typedef psc, TIMETP_Typedef polarity, u16 filter) -{ - TIM_ETRConfig(tim, psc, polarity, filter); - MODIFY_REG(tim->SMCR, TIM_SMCR_TS | TIM_SMCR_SMS, ((u32)TIM_TS_ETRF) | ((u32)TIM_SlaveMode_External1)); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the External clock Mode2 -/// @param tim: select the TIM peripheral. -/// @param psc: The external Trigger Prescaler. -/// This parameter can be one of the following values: -/// @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. -/// @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. -/// @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. -/// @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. -/// @param polarity: The external Trigger Polarity. -/// This parameter can be one of the following values: -/// @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. -/// @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. -/// @param filter: External Trigger Filter. -/// This parameter must be a value between 0x00 and 0x0F -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_ETRClockMode2Config(TIM_TypeDef* tim, TIMEXTTRGPSC_Typedef psc, TIMETP_Typedef polarity, u16 filter) -{ - TIM_ETRConfig(tim, psc, polarity, filter); - SET_BIT(tim->SMCR, TIM_SMCR_ECEN); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the tim Prescaler. -/// @param tim: select the TIM peripheral. -/// @param prescaler: specifies the Prescaler Register value -/// @param reloadMode: specifies the TIM Prescaler Reload mode -/// This parameter can be one of the following values: -/// @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event. -/// @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediately. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_PrescalerConfig(TIM_TypeDef* tim, u16 prescaler, TIMUG_Typedef reloadMode) -{ - WRITE_REG(tim->PSC, prescaler); - WRITE_REG(tim->EGR, reloadMode); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Specifies the tim Counter Mode to be used. -/// @param tim:select the TIM peripheral. -/// @param counter_mode: specifies the Counter Mode to be used -/// This parameter can be one of the following values: -/// @arg TIM_CounterMode_Up: TIM Up Counting Mode -/// @arg TIM_CounterMode_Down: TIM Down Counting Mode -/// @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 -/// @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 -/// @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_CounterModeConfig(TIM_TypeDef* tim, TIMCOUNTMODE_Typedef counter_mode) -{ - MODIFY_REG(tim->CR1, TIM_CR1_CMS | TIM_CR1_DIR, counter_mode); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Selects the Input Trigger source -/// @param tim: select the TIM peripheral. -/// @param source: The Input Trigger source. -/// This parameter can be one of the following values: -/// @arg TIM_TS_ITR0: Internal Trigger 0 -/// @arg TIM_TS_ITR1: Internal Trigger 1 -/// @arg TIM_TS_ITR2: Internal Trigger 2 -/// @arg TIM_TS_ITR3: Internal Trigger 3 -/// @arg TIM_TS_TI1F_ED: TI1 Edge Detector -/// @arg TIM_TS_TI1FP1: Filtered Timer Input 1 -/// @arg TIM_TS_TI2FP2: Filtered Timer Input 2 -/// @arg TIM_TS_ETRF: External Trigger input -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_SelectInputTrigger(TIM_TypeDef* tim, TIMTS_TypeDef source) -{ - MODIFY_REG(tim->SMCR, TIM_SMCR_TS, source); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the tim Encoder Interface. -/// @param tim: select the TIM peripheral. -/// @param encoder_mode: specifies the tim Encoder Mode. -/// This parameter can be one of the following values: -/// @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level. -/// @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level. -/// @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending -/// on the level of the other input. -/// @param ic1_polarity: specifies the IC1 Polarity -/// This parameter can be one of the following values: -/// @arg TIM_ICPolarity_Falling: IC Falling edge. -/// @arg TIM_ICPolarity_Rising: IC Rising edge. -/// @param ic2_polarity: specifies the IC2 Polarity -/// This parameter can be one of the following values: -/// @arg TIM_ICPolarity_Falling: IC Falling edge. -/// @arg TIM_ICPolarity_Rising: IC Rising edge. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_EncoderInterfaceConfig(TIM_TypeDef* tim, - TIMSMSENCODER_Typedef encoder_mode, - TIMICP_Typedef ic1_polarity, - TIMICP_Typedef ic2_polarity) -{ - MODIFY_REG(tim->SMCR, TIM_SMCR_SMS, encoder_mode); - MODIFY_REG(tim->CCMR1, TIM_CCMR1_CC1S | TIM_CCMR1_CC2S, TIM_CCMR1_CC1S_DIRECTTI | TIM_CCMR1_CC2S_DIRECTTI); - MODIFY_REG(tim->CCER, TIM_CCER_CC1P | TIM_CCER_CC2P, ic1_polarity | (ic2_polarity << 4)); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Forces the tim output 1 waveform to active or inactive level. -/// @param tim: select the TIM peripheral. -/// @param forced_action: specifies the forced Action to be set to the output waveform. -/// This parameter can be one of the following values: -/// @arg TIM_ForcedAction_Active: Force active level on OC1REF -/// @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_ForcedOC1Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action) -{ - MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC1M, forced_action); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Forces the tim output 2 waveform to active or inactive level. -/// @param tim: select the TIM peripheral. -/// @param forced_action: specifies the forced Action to be set to the output waveform. -/// This parameter can be one of the following values: -/// @arg TIM_ForcedAction_Active: Force active level on OC2REF -/// @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_ForcedOC2Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action) -{ - MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC2M, forced_action << 8); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Forces the tim output 3 waveform to active or inactive level. -/// @param tim: select the TIM peripheral. -/// @param forced_action: specifies the forced Action to be set to the output waveform. -/// This parameter can be one of the following values: -/// @arg TIM_ForcedAction_Active: Force active level on OC3REF -/// @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_ForcedOC3Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action) -{ - MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC3M, forced_action); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Forces the tim output 4 waveform to active or inactive level. -/// @param tim: select the TIM peripheral. -/// @param forced_action: specifies the forced Action to be set to the output waveform. -/// This parameter can be one of the following values: -/// @arg TIM_ForcedAction_Active: Force active level on OC4REF -/// @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_ForcedOC4Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action) -{ - MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC4M, forced_action << 8); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables tim peripheral Preload register on ARR. -/// @param tim: select the TIM peripheral. -/// @param state: new state of the tim peripheral Preload register -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_ARRPreloadConfig(TIM_TypeDef* tim, FunctionalState state) -{ - (state) ? SET_BIT(tim->CR1, TIM_CR1_ARPEN) : CLEAR_BIT(tim->CR1, TIM_CR1_ARPEN); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Selects the TIM peripheral Commutation event. -/// @param tim: select the tim peripheral. -/// @param state: new state of the Commutation event. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_SelectCOM(TIM_TypeDef* tim, FunctionalState state) -{ - (state) ? SET_BIT(tim->CR2, TIM_CR2_CCUS) : CLEAR_BIT(tim->CR2, TIM_CR2_CCUS); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Selects the tim peripheral Capture Compare DMA source. -/// @param tim: select the TIM peripheral. -/// @param state: new state of the Capture Compare DMA source -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_SelectCCDMA(TIM_TypeDef* tim, FunctionalState state) -{ - (state) ? SET_BIT(tim->CR2, TIM_CR2_CCDS) : CLEAR_BIT(tim->CR2, TIM_CR2_CCDS); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit. -/// @param tim: select the tim peripheral. -/// @param state: new state of the Capture Compare Preload Control bit -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_CCPreloadControl(TIM_TypeDef* tim, FunctionalState state) -{ - (state) ? SET_BIT(tim->CR2, TIM_CR2_CCPC) : CLEAR_BIT(tim->CR2, TIM_CR2_CCPC); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the tim peripheral Preload register on CCR1. -/// @param tim: select the TIM peripheral. -/// @param preload: new state of the tim peripheral Preload register -/// This parameter can be one of the following values: -/// @arg TIM_OCPreload_Enable -/// @arg TIM_OCPreload_Disable -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_OC1PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload) -{ - MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC1PEN, preload); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the tim peripheral Preload register on CCR2. -/// @param tim: select the TIM peripheral. -/// @param preload: new state of the tim peripheral Preload register -/// This parameter can be one of the following values: -/// @arg TIM_OCPreload_Enable -/// @arg TIM_OCPreload_Disable -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_OC2PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload) -{ - MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC2PEN, preload << 8); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the tim peripheral Preload register on CCR3. -/// @param tim: select the TIM peripheral. -/// @param preload: new state of the tim peripheral Preload register -/// This parameter can be one of the following values: -/// @arg TIM_OCPreload_Enable -/// @arg TIM_OCPreload_Disable -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_OC3PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload) -{ - MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC3PEN, preload); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the tim peripheral Preload register on CCR4. -/// @param tim: select the TIM peripheral. -/// @param preload: new state of the tim peripheral Preload register -/// This parameter can be one of the following values: -/// @arg TIM_OCPreload_Enable -/// @arg TIM_OCPreload_Disable -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_OC4PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload) -{ - MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC4PEN, preload << 8); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the tim Output Compare 1 Fast feature. -/// @param tim: select the TIM peripheral. -/// @param fast: new state of the Output Compare Fast Enable Bit. -/// This parameter can be one of the following values: -/// @arg TIM_OCFast_Enable: TIM output compare fast enable -/// @arg TIM_OCFast_Disable: TIM output compare fast disable -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_OC1FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast) -{ - MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC1FEN, fast); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the tim Output Compare 2 Fast feature. -/// @param tim: select the TIM peripheral. -/// @param fast: new state of the Output Compare Fast Enable Bit. -/// This parameter can be one of the following values: -/// @arg TIM_OCFast_Enable: TIM output compare fast enable -/// @arg TIM_OCFast_Disable: TIM output compare fast disable -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_OC2FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast) -{ - MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC2FEN, fast << 8); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the tim Output Compare 3 Fast feature. -/// @param tim: select the TIM peripheral. -/// @param fast: new state of the Output Compare Fast Enable Bit. -/// This parameter can be one of the following values: -/// @arg TIM_OCFast_Enable: TIM output compare fast enable -/// @arg TIM_OCFast_Disable: TIM output compare fast disable -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_OC3FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast) -{ - MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC3FEN, fast); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the tim Output Compare 4 Fast feature. -/// @param tim: select the TIM peripheral. -/// @param fast: new state of the Output Compare Fast Enable Bit. -/// This parameter can be one of the following values: -/// @arg TIM_OCFast_Enable: TIM output compare fast enable -/// @arg TIM_OCFast_Disable: TIM output compare fast disable -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_OC4FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast) -{ - MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC4FEN, fast << 8); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Clears or safeguards the OCREF1 signal on an external event -/// @param tim: select the TIM peripheral. -/// @param clear: new state of the Output Compare Clear Enable Bit. -/// This parameter can be one of the following values: -/// @arg TIM_OCClear_Enable: TIM Output clear enable -/// @arg TIM_OCClear_Disable: TIM Output clear disable -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_ClearOC1Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear) -{ - MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC1CEN, clear); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Clears or safeguards the OCREF2 signal on an external event -/// @param tim: select the TIM peripheral. -/// @param clear: new state of the Output Compare Clear Enable Bit. -/// This parameter can be one of the following values: -/// @arg TIM_OCClear_Enable: TIM Output clear enable -/// @arg TIM_OCClear_Disable: TIM Output clear disable -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_ClearOC2Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear) -{ - MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC2CEN, clear << 8); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Clears or safeguards the OCREF3 signal on an external event -/// @param tim: select the TIM peripheral. -/// @param clear: new state of the Output Compare Clear Enable Bit. -/// This parameter can be one of the following values: -/// @arg TIM_OCClear_Enable: TIM Output clear enable -/// @arg TIM_OCClear_Disable: TIM Output clear disable -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_ClearOC3Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear) -{ - MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC3CEN, clear); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Clears or safeguards the OCREF4 signal on an external event -/// @param tim: select the TIM peripheral. -/// @param clear: new state of the Output Compare Clear Enable Bit. -/// This parameter can be one of the following values: -/// @arg TIM_OCClear_Enable: TIM Output clear enable -/// @arg TIM_OCClear_Disable: TIM Output clear disable -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_ClearOC4Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear) -{ - MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC4CEN, clear << 8); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the tim channel 1 polarity. -/// @param tim: select the TIM peripheral. -/// @param polarity: specifies the OC1 Polarity -/// This parameter can be one of the following values: -/// @arg TIM_OCPolarity_High: Output Compare active high -/// @arg TIM_OCPolarity_Low: Output Compare active low -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_OC1PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity) -{ - MODIFY_REG(tim->CCER, TIM_CCER_CC1P, polarity); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the tim Channel 1N polarity. -/// @param tim: select the TIM peripheral. -/// @param polarity: specifies the OC1N Polarity -/// This parameter can be one of the following values: -/// @arg TIM_OCNPolarity_High: Output Compare active high -/// @arg TIM_OCNPolarity_Low: Output Compare active low -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_OC1NPolarityConfig(TIM_TypeDef* tim, TIMCCxNP_Typedef polarity) -{ - MODIFY_REG(tim->CCER, TIM_CCER_CC1NP, polarity); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the tim channel 2 polarity. -/// @param tim: select the TIM peripheral. -/// @param polarity: specifies the OC2 Polarity -/// This parameter can be one of the following values: -/// @arg TIM_OCPolarity_High: Output Compare active high -/// @arg TIM_OCPolarity_Low: Output Compare active low -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_OC2PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity) -{ - MODIFY_REG(tim->CCER, TIM_CCER_CC2P, polarity << 4); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the tim Channel 2N polarity. -/// @param tim: select the TIM peripheral. -/// @param polarity: specifies the OC2N Polarity -/// This parameter can be one of the following values: -/// @arg TIM_OCNPolarity_High: Output Compare active high -/// @arg TIM_OCNPolarity_Low: Output Compare active low -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_OC2NPolarityConfig(TIM_TypeDef* tim, TIMCCxNP_Typedef polarity) -{ - MODIFY_REG(tim->CCER, TIM_CCER_CC2NP, polarity << 4); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the tim channel 3 polarity. -/// @param tim: select the TIM peripheral. -/// @param polarity: specifies the OC3 Polarity -/// This parameter can be one of the following values: -/// @arg TIM_OCPolarity_High: Output Compare active high -/// @arg TIM_OCPolarity_Low: Output Compare active low -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_OC3PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity) -{ - MODIFY_REG(tim->CCER, TIM_CCER_CC3P, polarity << 8); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the tim Channel 3N polarity. -/// @param tim: select the TIM peripheral. -/// @param polarity: specifies the OC3N Polarity -/// This parameter can be one of the following values: -/// @arg TIM_OCNPolarity_High: Output Compare active high -/// @arg TIM_OCNPolarity_Low: Output Compare active low -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_OC3NPolarityConfig(TIM_TypeDef* tim, TIMCCxNP_Typedef polarity) -{ - MODIFY_REG(tim->CCER, TIM_CCER_CC3NP, polarity << 8); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the tim channel 4 polarity. -/// @param tim: select the TIM peripheral. -/// @param polarity: specifies the OC4 Polarity -/// This parameter can be one of the following values: -/// @arg TIM_OCPolarity_High: Output Compare active high -/// @arg TIM_OCPolarity_Low: Output Compare active low -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_OC4PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity) -{ - MODIFY_REG(tim->CCER, TIM_CCER_CC4P, polarity << 12); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the TIM Capture Compare Channel x. -/// @param tim: select the TIM peripheral. -/// @param channel: specifies the TIM Channel -/// This parameter can be one of the following values: -/// @arg TIM_Channel_1: TIM Channel 1 -/// @arg TIM_Channel_2: TIM Channel 2 -/// @arg TIM_Channel_3: TIM Channel 3 -/// @arg TIM_Channel_4: TIM Channel 4 -/// @arg TIM_Channel_5: TIM Channel 5(Only for some MM32 TIM1/8) -/// @param TIM_CCx: specifies the TIM Channel CCxE bit new state. -/// This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_CCxCmd(TIM_TypeDef* tim, TIMCHx_Typedef channel, TIMCCxE_Typedef ccx_en) -{ - MODIFY_REG(tim->CCER, TIM_CCER_CC1EN << channel, ccx_en << channel); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the TIM Capture Compare Channel xN. -/// @param tim: select the TIM peripheral. -/// @param channel: specifies the TIM Channel -/// This parameter can be one of the following values: -/// @arg TIM_Channel_1: TIM Channel 1 -/// @arg TIM_Channel_2: TIM Channel 2 -/// @arg TIM_Channel_3: TIM Channel 3 -/// @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state. -/// This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_CCxNCmd(TIM_TypeDef* tim, TIMCHx_Typedef channel, TIMCCxNE_Typedef ccxn_en) -{ - if (channel != TIM_Channel_4) - MODIFY_REG(tim->CCER, TIM_CCER_CC1NEN << channel, ccxn_en << channel); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Selects the TIM Output Compare Mode. -/// @note This function disables the selected channel before changing the Output -/// Compare Mode. -/// User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions. -/// @param tim: select the TIM peripheral. -/// @param channel: specifies the TIM Channel -/// This parameter can be one of the following values: -/// @arg TIM_Channel_1: TIM Channel 1 -/// @arg TIM_Channel_2: TIM Channel 2 -/// @arg TIM_Channel_3: TIM Channel 3 -/// @arg TIM_Channel_4: TIM Channel 4 -/// @param mode: specifies the TIM Output Compare Mode. -/// This parameter can be one of the following values: -/// @arg TIM_OCMode_Timing -/// @arg TIM_OCMode_Active -/// @arg TIM_OCMode_Toggle -/// @arg TIM_OCMode_PWM1 -/// @arg TIM_OCMode_PWM2 -/// @arg TIM_ForcedAction_Active -/// @arg TIM_ForcedAction_InActive -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_SelectOCxM(TIM_TypeDef* tim, TIMCHx_Typedef channel, TIMOCMODE_Typedef mode) -{ - CLEAR_BIT(tim->CCER, TIM_CCER_CC1EN << channel); - switch (channel) { - case TIM_Channel_1: - MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC1M, mode); - break; - case TIM_Channel_2: - MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC2M, mode << 8); - break; - case TIM_Channel_3: - MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC3M, mode); - break; - case TIM_Channel_4: - MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC4M, mode << 8); - break; - default: - break; - } -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or Disables the tim Update event. -/// @param tim: select the TIM peripheral. -/// @param state: new state of the tim UDIS bit -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_UpdateDisableConfig(TIM_TypeDef* tim, FunctionalState state) -{ - (state) ? SET_BIT(tim->CR1, TIM_CR1_UDIS) : CLEAR_BIT(tim->CR1, TIM_CR1_UDIS); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the tim Update Request Interrupt source. -/// @param tim: select the TIM peripheral. -/// @param source: specifies the Update source. -/// This parameter can be one of the following values: -/// @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow -/// or the setting of UG bit, or an update generation -/// through the slave mode controller. -/// @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_UpdateRequestConfig(TIM_TypeDef* tim, TIMURS_Typedef source) -{ - MODIFY_REG(tim->CR1, TIM_CR1_URS, source); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the tim's Hall sensor interface. -/// @param tim: select the TIM peripheral. -/// @param state: new state of the tim Hall sensor interface. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_SelectHallSensor(TIM_TypeDef* tim, FunctionalState state) -{ - (state) ? SET_BIT(tim->CR2, TIM_CR2_TI1S) : CLEAR_BIT(tim->CR2, TIM_CR2_TI1S); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Selects the tim's One Pulse Mode. -/// @param tim: select the TIM peripheral. -/// @param mode: specifies the OPM Mode to be used. -/// This parameter can be one of the following values: -/// @arg TIM_OPMode_Single -/// @arg TIM_OPMode_Repetitive -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_SelectOnePulseMode(TIM_TypeDef* tim, TIMOPMODE_Typedef mode) -{ - MODIFY_REG(tim->CR1, TIM_CR1_OPM, mode); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Selects the tim Trigger Output Mode. -/// @param tim:select the TIM peripheral. -/// @param source: specifies the Trigger Output source. -/// This paramter can be one of the following values: -/// - For all tim -/// @arg TIM_TRIGSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRIG). -/// @arg TIM_TRIGSource_Enable: The Counter Enable CEN is used as the trigger output (TRIG). -/// @arg TIM_TRIGSource_Update: The update event is selected as the trigger output (TRIG). -/// @arg TIM_TRIGSource_OC1: The trigger output sends a positive pulse when the CC1IF flag -/// is to be set, as soon as a capture or compare match occurs (TRIG). -/// @arg TIM_TRIGSource_OC1Ref: OC1REF signal is used as the trigger output (TRIG). -/// @arg TIM_TRIGSource_OC2Ref: OC2REF signal is used as the trigger output (TRIG). -/// @arg TIM_TRIGSource_OC3Ref: OC3REF signal is used as the trigger output (TRIG). -/// @arg TIM_TRIGSource_OC4Ref: OC4REF signal is used as the trigger output (TRIG). -/// -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_SelectOutputTrigger(TIM_TypeDef* tim, TIMMMS_Typedef source) -{ - MODIFY_REG(tim->CR2, TIM_CR2_MMS, source); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Selects the tim Slave Mode. -/// @param tim: select the TIM peripheral. -/// @param mode: specifies the Timer Slave Mode. -/// This parameter can be one of the following values: -/// @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes -/// the counter and triggers an update of the registers. -/// @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high. -/// @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI. -/// @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_SelectSlaveMode(TIM_TypeDef* tim, TIMSMSMODE_Typedef mode) -{ - MODIFY_REG(tim->SMCR, TIM_SMCR_SMS, mode); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Sets or Resets the tim Master/Slave Mode. -/// @param tim: select the TIM peripheral. -/// @param mode: specifies the Timer Master Slave Mode. -/// This parameter can be one of the following values: -/// @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer -/// and its slaves (through TRIG). -/// @arg TIM_MasterSlaveMode_Disable: No action -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_SelectMasterSlaveMode(TIM_TypeDef* tim, TIMMSM_Typedef mode) -{ - MODIFY_REG(tim->SMCR, TIM_SMCR_MSM, mode); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Sets the tim Counter Register value -/// @param tim: select the TIM peripheral. -/// @param auto_reload: specifies the Counter register new value. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_SetAutoreload(TIM_TypeDef* tim, u16 auto_reload) -{ - WRITE_REG(tim->ARR, auto_reload); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Sets the tim Input Capture 1 prescaler. -/// @param tim: select the TIM peripheral. -/// @param psc: specifies the Input Capture1 prescaler new value. -/// This parameter can be one of the following values: -/// @arg TIM_ICPSC_DIV1: no prescaler -/// @arg TIM_ICPSC_DIV2: capture is done once every 2 events -/// @arg TIM_ICPSC_DIV4: capture is done once every 4 events -/// @arg TIM_ICPSC_DIV8: capture is done once every 8 events -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_SetIC1Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc) -{ - MODIFY_REG(tim->CCMR1, TIM_CCMR1_IC1PSC, psc); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Sets the tim Input Capture 2 prescaler. -/// @param tim: select the TIM peripheral. -/// @param psc: specifies the Input Capture2 prescaler new value. -/// This parameter can be one of the following values: -/// @arg TIM_ICPSC_DIV1: no prescaler -/// @arg TIM_ICPSC_DIV2: capture is done once every 2 events -/// @arg TIM_ICPSC_DIV4: capture is done once every 4 events -/// @arg TIM_ICPSC_DIV8: capture is done once every 8 events -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_SetIC2Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc) -{ - MODIFY_REG(tim->CCMR1, TIM_CCMR1_IC2PSC, psc << 8); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Sets the tim Input Capture 3 prescaler. -/// @param tim: select the TIM peripheral. -/// @param psc: specifies the Input Capture3 prescaler new value. -/// This parameter can be one of the following values: -/// @arg TIM_ICPSC_DIV1: no prescaler -/// @arg TIM_ICPSC_DIV2: capture is done once every 2 events -/// @arg TIM_ICPSC_DIV4: capture is done once every 4 events -/// @arg TIM_ICPSC_DIV8: capture is done once every 8 events -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_SetIC3Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc) -{ - MODIFY_REG(tim->CCMR2, TIM_CCMR2_IC3PSC, psc); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Sets the tim Input Capture 4 prescaler. -/// @param tim: select the TIM peripheral. -/// @param psc: specifies the Input Capture4 prescaler new value. -/// This parameter can be one of the following values: -/// @arg TIM_ICPSC_DIV1: no prescaler -/// @arg TIM_ICPSC_DIV2: capture is done once every 2 events -/// @arg TIM_ICPSC_DIV4: capture is done once every 4 events -/// @arg TIM_ICPSC_DIV8: capture is done once every 8 events -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_SetIC4Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc) -{ - MODIFY_REG(tim->CCMR2, TIM_CCMR2_IC4PSC, psc << 8); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Sets the tim Clock Division value. -/// @param tim: select -/// the TIM peripheral. -/// @param clock_div: specifies the clock division value. -/// This parameter can be one of the following value: -/// @arg TIM_CKD_DIV1: TDTS = Tck_tim -/// @arg TIM_CKD_DIV2: TDTS = 2 * Tck_tim -/// @arg TIM_CKD_DIV4: TDTS = 4 * Tck_tim -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_SetClockDivision(TIM_TypeDef* tim, TIMCKD_TypeDef clock_div) -{ - MODIFY_REG(tim->CR1, TIM_CR1_CKD, clock_div); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Sets the tim Counter Register value -/// @param tim: select the TIM peripheral. -/// @param counter: specifies the Counter register new value. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_SetCounter(TIM_TypeDef* tim, u32 counter) -{ - if ((tim == TIM2) || (tim == TIM5)) - WRITE_REG(tim->CNT, (u32)counter); - else - WRITE_REG(tim->CNT, (u16)counter); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Sets the tim Capture Compare1 Register value -/// @param tim: select the TIM peripheral. -/// @param compare: specifies the Capture Compare1 register new value. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_SetCompare1(TIM_TypeDef* tim, u32 compare) -{ - if ((tim == TIM2) || (tim == TIM5)) - WRITE_REG(tim->CCR1, (u32)compare); - else - WRITE_REG(tim->CCR1, (u16)compare); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Sets the tim Capture Compare2 Register value -/// @param tim: select the TIM peripheral. -/// @param compare: specifies the Capture Compare2 register new value. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_SetCompare2(TIM_TypeDef* tim, u32 compare) -{ - if ((tim == TIM2) || (tim == TIM5)) - WRITE_REG(tim->CCR2, (u32)compare); - else - WRITE_REG(tim->CCR2, (u16)compare); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Sets the tim Capture Compare3 Register value -/// @param tim: select the TIM peripheral. -/// @param compare: specifies the Capture Compare3 register new value. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_SetCompare3(TIM_TypeDef* tim, u32 compare) -{ - if ((tim == TIM2) || (tim == TIM5)) - WRITE_REG(tim->CCR3, (u32)compare); - else - WRITE_REG(tim->CCR3, (u16)compare); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Sets the tim Capture Compare4 Register value -/// @param tim: select the TIM peripheral. -/// @param compare: specifies the Capture Compare4 register new value. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_SetCompare4(TIM_TypeDef* tim, u32 compare) -{ - if ((tim == TIM2) || (tim == TIM5)) - WRITE_REG(tim->CCR4, (u32)compare); - else - WRITE_REG(tim->CCR4, (u16)compare); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Gets the tim Input Capture 1 value. -/// @param tim: select the TIM peripheral. -/// @retval Value: Capture Compare 1 Register value. -//////////////////////////////////////////////////////////////////////////////// -u32 TIM_GetCapture1(TIM_TypeDef* tim) -{ - return tim->CCR1; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Gets the tim Input Capture 2 value. -/// @param tim: select the TIM peripheral. -/// @retval Value: Capture Compare 2 Register value. -//////////////////////////////////////////////////////////////////////////////// -u32 TIM_GetCapture2(TIM_TypeDef* tim) -{ - return tim->CCR2; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Gets the tim Input Capture 3 value. -/// @param tim: select the TIM peripheral. -/// @retval Value: Capture Compare 3 Register value. -//////////////////////////////////////////////////////////////////////////////// -u32 TIM_GetCapture3(TIM_TypeDef* tim) -{ - return tim->CCR3; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Gets the tim Input Capture 4 value. -/// @param tim: select the TIM peripheral. -/// @retval Value: Capture Compare 4 Register value. -//////////////////////////////////////////////////////////////////////////////// -u32 TIM_GetCapture4(TIM_TypeDef* tim) -{ - return tim->CCR4; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Gets the tim Counter value. -/// @param tim: select the TIM peripheral. -/// @retval Value: Counter Register value. -//////////////////////////////////////////////////////////////////////////////// -u32 TIM_GetCounter(TIM_TypeDef* tim) -{ - return tim->CNT; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Gets the tim Prescaler value. -/// @param tim: select the TIM peripheral. -/// @retval Value: Prescaler Register value. -//////////////////////////////////////////////////////////////////////////////// -u16 TIM_GetPrescaler(TIM_TypeDef* tim) -{ - return tim->PSC; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Checks whether the specified TIM flag is set or not. -/// @param tim: select the TIM peripheral. -/// @param flag: specifies the flag to check. -/// This parameter can be one of the following values: -/// @arg TIM_FLAG_Update: TIM update Flag -/// @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag -/// @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag -/// @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag -/// @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag -/// @arg TIM_FLAG_COM: TIM Commutation Flag -/// @arg TIM_FLAG_Trigger: TIM Trigger Flag -/// @arg TIM_FLAG_Break: TIM Break Flag -/// @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag -/// @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag -/// @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag -/// @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag -/// @note -/// - TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. -/// - TIM_FLAG_Break is used only with TIM1 and TIM8. -/// - TIM_FLAG_COM is used only with TIM1, TIM8, TIM16 and TIM17. -/// @retval State: The new state of TIM_FLAG (SET or RESET). -//////////////////////////////////////////////////////////////////////////////// -FlagStatus TIM_GetFlagStatus(TIM_TypeDef* tim, TIMFLAG_Typedef flag) -{ - return ((tim->SR & flag) ? SET : RESET); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Clears the tim's pending flags. -/// @param tim: select the TIM peripheral. -/// @param flag: specifies the flag bit to clear. -/// This parameter can be any combination of the following values: -/// @arg TIM_FLAG_Update: TIM update Flag -/// @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag -/// @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag -/// @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag -/// @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag -/// @arg TIM_FLAG_COM: TIM Commutation Flag -/// @arg TIM_FLAG_Trigger: TIM Trigger Flag -/// @arg TIM_FLAG_Break: TIM Break Flag -/// @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag -/// @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag -/// @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag -/// @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag -/// @note -/// - TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. -/// - TIM_FLAG_Break is used only with TIM1 and TIM8. -/// - TIM_FLAG_COM is used only with TIM1, TIM8, TIM16 and TIM17. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_ClearFlag(TIM_TypeDef* tim, TIMFLAG_Typedef flag) -{ - CLEAR_BIT(tim->SR, flag); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Checks whether the TIM interrupt has occurred or not. -/// @param tim: select the TIM peripheral. -/// @param it: specifies the TIM interrupt source to check. -/// This parameter can be one of the following values: -/// @arg TIM_IT_Update: TIM update Interrupt source -/// @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source -/// @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source -/// @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source -/// @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source -/// @arg TIM_IT_COM: TIM Commutation Interrupt source -/// @arg TIM_IT_Trigger: TIM Trigger Interrupt source -/// @arg TIM_IT_Break: TIM Break Interrupt source -/// @note -/// - TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. -/// - TIM_IT_Break is used only with TIM1 and TIM8. -/// - TIM_IT_COM is used only with TIM1, TIM8, TIM16 and TIM17. -/// @retval State: The new state of the TIM_IT(SET or RESET). -//////////////////////////////////////////////////////////////////////////////// -ITStatus TIM_GetITStatus(TIM_TypeDef* tim, TIMIT_TypeDef it) -{ - return (((tim->SR & it) && (tim->DIER & it)) ? SET : RESET); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Clears the tim's interrupt pending bits. -/// @param tim: select the TIM peripheral. -/// @param it: specifies the pending bit to clear. -/// This parameter can be any combination of the following values: -/// @arg TIM_IT_Update: TIM1 update Interrupt source -/// @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source -/// @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source -/// @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source -/// @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source -/// @arg TIM_IT_COM: TIM Commutation Interrupt source -/// @arg TIM_IT_Trigger: TIM Trigger Interrupt source -/// @arg TIM_IT_Break: TIM Break Interrupt source -/// @note -/// - TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. -/// - TIM_IT_Break is used only with TIM1 and TIM8. -/// - TIM_IT_COM is used only with TIM1, TIM8, TIM16 and TIM17. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_ClearITPendingBit(TIM_TypeDef* tim, u32 it) //TIMIT_TypeDef -{ - CLEAR_BIT(tim->SR, it); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the tim channel 1 polarity. -/// @param tim: select the TIM peripheral. -/// @param polarity: specifies the IC1 Polarity -/// This parameter can be one of the following values: -/// @arg TIM_ICPolarity_Rising -/// @arg TIM_ICPolarity_Falling -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_SetIC1Plority(TIM_TypeDef* tim, TIMICP_Typedef pol) -{ - (pol) ? SET_BIT(tim->CCER, TIM_CCER_CC1P) : CLEAR_BIT(tim->CCER, TIM_CCER_CC1P); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the tim channel 2 polarity. -/// @param tim: select the TIM peripheral. -/// @param polarity: specifies the IC2 Polarity -/// This parameter can be one of the following values: -/// @arg TIM_ICPolarity_Rising -/// @arg TIM_ICPolarity_Falling -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_SetIC2Plority(TIM_TypeDef* tim, TIMICP_Typedef pol) -{ - (pol) ? SET_BIT(tim->CCER, TIM_CCER_CC2P) : CLEAR_BIT(tim->CCER, TIM_CCER_CC2P); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the tim channel 3 polarity. -/// @param tim: select the TIM peripheral. -/// @param polarity: specifies the IC3 Polarity -/// This parameter can be one of the following values: -/// @arg TIM_ICPolarity_Rising -/// @arg TIM_ICPolarity_Falling -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_SetIC3Plority(TIM_TypeDef* tim, TIMICP_Typedef pol) -{ - (pol) ? SET_BIT(tim->CCER, TIM_CCER_CC3P) : CLEAR_BIT(tim->CCER, TIM_CCER_CC3P); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the tim channel 4 polarity. -/// @param tim: select the TIM peripheral. -/// @param polarity: specifies the IC4 Polarity -/// This parameter can be one of the following values: -/// @arg TIM_ICPolarity_Rising -/// @arg TIM_ICPolarity_Falling -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_SetIC4Plority(TIM_TypeDef* tim, TIMICP_Typedef pol) -{ - (pol) ? SET_BIT(tim->CCER, TIM_CCER_CC4P) : CLEAR_BIT(tim->CCER, TIM_CCER_CC4P); -} - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Sets the tim Capture Compare 5 Register value -/// @param tim: select the TIM peripheral. -/// @param compare: specifies the Capture Compare5 register new value. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_SetCompare5(TIM_TypeDef* tim, u32 compare) -{ - WRITE_REG(tim->CCR5, (u16)compare); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Gets the tim Input Capture 5 value. -/// @param tim: select the TIM peripheral. -/// @retval Value: Capture Compare 5 Register value. -//////////////////////////////////////////////////////////////////////////////// -u32 TIM_GetCapture5(TIM_TypeDef* tim) -{ - return tim->CCR5; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Initializes the tim Channel5 according to the specified -/// parameters in the init_struct. -/// @param tim: select the TIM peripheral. -/// @param init_struct: pointer to a TIM_OCInitTypeDef structure that -/// contains the configuration information for the specified TIM peripheral. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_OC5Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct) -{ - MODIFY_REG(tim->CCMR3, TIM_CCMR3_OC5M, (init_struct->TIM_OCMode) << 4); - MODIFY_REG(tim->CCER, TIM_CCER_CC5EN | TIM_CCER_CC5P, - (init_struct->TIM_OCPolarity << 16) | (init_struct->TIM_OutputState << 16)); - WRITE_REG(tim->CCR4, init_struct->TIM_Pulse); - - if ((tim == TIM1) || (tim == TIM8)) - MODIFY_REG(tim->CR2, TIM_CR2_OIS5, init_struct->TIM_OCIdleState << 8); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the tim peripheral Preload register on CCR5. -/// @param tim: select the TIM peripheral. -/// @param preload: new state of the tim peripheral Preload register -/// This parameter can be one of the following values: -/// @arg TIM_OCPreload_Enable -/// @arg TIM_OCPreload_Disable -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_OC5PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload) -{ - MODIFY_REG(tim->CCMR3, TIM_CCMR3_OC5PEN, preload); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the tim channel 5 polarity. -/// @param tim: select the TIM peripheral. -/// @param polarity: specifies the OC5 Polarity -/// This parameter can be one of the following values: -/// @arg TIM_OCPolarity_High: Output Compare active high -/// @arg TIM_OCPolarity_Low: Output Compare active low -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_OC5PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity) -{ - MODIFY_REG(tim->CCER, TIM_CCER_CC5P, polarity << 16); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configures the tim Output Compare 5 Fast feature. -/// @param tim: select the TIM peripheral. -/// @param fast: new state of the Output Compare Fast Enable Bit. -/// This parameter can be one of the following values: -/// @arg TIM_OCFast_Enable: TIM output compare fast enable -/// @arg TIM_OCFast_Disable: TIM output compare fast disable -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_OC5FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast) -{ - MODIFY_REG(tim->CCMR3, TIM_CCMR3_OC5FEN, fast); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Clears or safeguards the OCREF4 signal on an external event -/// @param tim: select the TIM peripheral. -/// @param clear: new state of the Output Compare Clear Enable Bit. -/// This parameter can be one of the following values: -/// @arg TIM_OCClear_Enable: TIM Output clear enable -/// @arg TIM_OCClear_Disable: TIM Output clear disable -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_ClearOC5Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear) -{ - MODIFY_REG(tim->CCMR3, TIM_CCMR3_OC5CEN, clear); -} - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the tim complementary PWM output Status after Break. -/// @param tim: select the TIM peripheral. -/// @param state: new state of the tim complementary PWM output. -/// This parameter can be: ENABLE or DISABLE. -/// @arg ENABLE: Direct output enable, no longer waiting for output after dead time. -/// @arg DISABLE: Direct output disable, output waiting for dead time. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_DirectOutput(TIM_TypeDef* tim, FunctionalState state) -{ - (state) ? SET_BIT(tim->BDTR, TIM_BDTR_DOEN) : CLEAR_BIT(tim->BDTR, TIM_BDTR_DOEN); -} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup TIM_Private_Functions -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configure the TI1 as Input. -/// @param tim: select the TIM peripheral. -/// @param polarity : The Input Polarity. -/// This parameter can be one of the following values: -/// @arg TIM_ICPolarity_Rising -/// @arg TIM_ICPolarity_Falling -/// @param selection: specifies the input to be used. -/// This parameter can be one of the following values: -/// @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. -/// @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. -/// @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. -/// @param filter: Specifies the Input Capture Filter. -/// This parameter must be a value between 0x00 and 0x0F. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -static void TI1_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter) -{ - MODIFY_REG(tim->CCMR1, TIM_CCMR1_CC1S | TIM_CCMR1_IC1F, (filter << 4) | selection); - MODIFY_REG(tim->CCER, TIM_CCER_CC1EN | TIM_CCER_CC1P, polarity | TIM_CCER_CC1EN); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configure the TI2 as Input. -/// @param tim: select the TIM peripheral. -/// @param polarity : The Input Polarity. -/// This parameter can be one of the following values: -/// @arg TIM_ICPolarity_Rising -/// @arg TIM_ICPolarity_Falling -/// @param selection: specifies the input to be used. -/// This parameter can be one of the following values: -/// @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. -/// @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. -/// @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. -/// @param filter: Specifies the Input Capture Filter. -/// This parameter must be a value between 0x00 and 0x0F. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -static void TI2_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter) -{ - MODIFY_REG(tim->CCMR1, TIM_CCMR1_CC2S | TIM_CCMR1_IC2F, (filter << 12) | (selection << 8)); - MODIFY_REG(tim->CCER, TIM_CCER_CC2EN | TIM_CCER_CC2P, (polarity << 4) | TIM_CCER_CC2EN); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configure the TI3 as Input. -/// @param tim: select the TIM peripheral. -/// @param polarity : The Input Polarity. -/// This parameter can be one of the following values: -/// @arg TIM_ICPolarity_Rising -/// @arg TIM_ICPolarity_Falling -/// @param selection: specifies the input to be used. -/// This parameter can be one of the following values: -/// @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. -/// @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. -/// @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. -/// @param filter: Specifies the Input Capture Filter. -/// This parameter must be a value between 0x00 and 0x0F. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -static void TI3_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter) -{ - MODIFY_REG(tim->CCMR2, TIM_CCMR2_CC3S | TIM_CCMR2_IC3F, (filter << 4) | selection); - MODIFY_REG(tim->CCER, TIM_CCER_CC3EN | TIM_CCER_CC3P, (polarity << 8) | TIM_CCER_CC3EN); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Configure the TI4 as Input. -/// @param tim: select the TIM peripheral. -/// @param polarity : The Input Polarity. -/// This parameter can be one of the following values: -/// @arg TIM_ICPolarity_Rising -/// @arg TIM_ICPolarity_Falling -/// @param selection: specifies the input to be used. -/// This parameter can be one of the following values: -/// @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. -/// @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. -/// @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. -/// @param filter: Specifies the Input Capture Filter. -/// This parameter must be a value between 0x00 and 0x0F. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -static void TI4_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter) -{ - MODIFY_REG(tim->CCMR2, TIM_CCMR2_CC4S | TIM_CCMR2_IC4F, (filter << 12) | (selection << 8)); - MODIFY_REG(tim->CCER, TIM_CCER_CC4EN | TIM_CCER_CC4P, (polarity << 12) | TIM_CCER_CC4EN); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the specified TIM PWM shift /DMA reqeat. -/// @param tim: select the tim peripheral. -/// @param it: Specifies the TIM PWM shift channel to enable or disable. -/// This parameter can be any combination of the following values: -/// @arg TIM_PDER_CCDREPE: TIM DMA reqeat enable bit -/// @arg TIM_PDER_CCR1SHIFTEN: TIM Channel 1 output PWM phase shift enable bit -/// @arg TIM_PDER_CCR2SHIFTEN: TIM Channel 2 output PWM phase shift enable bit -/// @arg TIM_PDER_CCR3SHIFTEN: TIM Channel 3 output PWM phase shift enable bit -/// @arg TIM_PDER_CCR4SHIFTEN: TIM Channel 4 output PWM phase shift enable bit -/// @arg TIM_PDER_CCR5SHIFTEN: TIM Channel 5 output PWM phase shift enable bit -/// @param state: new state of the TIM interrupts. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_PWMShiftConfig(TIM_TypeDef* tim, u32 it, FunctionalState state)//TIMIT_TypeDef -{ - (state) ? SET_BIT(tim->PDER, it) : CLEAR_BIT(tim->PDER, it); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Sets the tim CCR1 shift Register value -/// @param tim: select the TIM peripheral. -/// @param compare: specifies the Capture Compare1 register new value. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_SetCCR1FALL(TIM_TypeDef* tim, u32 shift) -{ - if (tim == TIM1) - WRITE_REG(tim->CCR1FALL, (u32)shift); - -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Sets the tim CCR2 shift Register value -/// @param tim: select the TIM peripheral. -/// @param compare: specifies the Capture Compare1 register new value. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_SetCCR2FALL(TIM_TypeDef* tim, u32 shift) -{ - if (tim == TIM1) - WRITE_REG(tim->CCR2FALL, (u32)shift); - -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Sets the tim CCR3 shift Register value -/// @param tim: select the TIM peripheral. -/// @param compare: specifies the Capture Compare1 register new value. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_SetCCR3FALL(TIM_TypeDef* tim, u32 shift) -{ - if (tim == TIM1) - WRITE_REG(tim->CCR3FALL, (u32)shift); - -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Sets the tim CCR4 shift Register value -/// @param tim: select the TIM peripheral. -/// @param compare: specifies the Capture Compare1 register new value. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_SetCCR4FALL(TIM_TypeDef* tim, u32 shift) -{ - if (tim == TIM1) - WRITE_REG(tim->CCR4FALL, (u32)shift); - -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Sets the tim CCR5 shift Register value -/// @param tim: select the TIM peripheral. -/// @param compare: specifies the Capture Compare1 register new value. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void TIM_SetCCR5FALL(TIM_TypeDef* tim, u32 shift) -{ - if (tim == TIM1) - WRITE_REG(tim->CCR5FALL, (u32)shift); - -} -/// @} - -/// @} - -/// @} diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uart.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uart.c deleted file mode 100644 index 2a0578f91..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uart.c +++ /dev/null @@ -1,502 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_uart.c -/// @file hal_uart.c -/// @author AE TEAM -/// @brief THIS FILE PROVIDES ALL THE UART FIRMWARE FUNCTIONS. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#define _HAL_UART_C_ - -// Files includes -#include "hal_rcc.h" -#include "hal_uart.h" -#include "hal_gpio.h" -#include "hal_dma.h" -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -///@addtogroup UART_HAL -///@{ - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup UART_Exported_Functions -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Deinitializes the uart peripheral registers to their -/// default reset values. -/// @param uart: Select the UART or the UART peripheral. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void UART_DeInit(UART_TypeDef* uart) -{ - - - if(UART2 == uart) { - exRCC_APB1PeriphReset(RCC_APB1ENR_UART2); - } - if(UART1 == uart) { - exRCC_APB2PeriphReset(RCC_APB2ENR_UART1); - } - if(UART3 == uart) { - exRCC_APB1PeriphReset(RCC_APB1ENR_UART3); - } - if(UART4 == uart) { - exRCC_APB1PeriphReset(RCC_APB1ENR_UART4); - } - if(UART5 == uart) { - exRCC_APB1PeriphReset(RCC_APB1ENR_UART5); - } - if(UART6 == uart) { - exRCC_APB2PeriphReset(RCC_APB2ENR_UART6); - } - if(UART7 == uart) { - exRCC_APB1PeriphReset(RCC_APB1ENR_UART7); - } - if(UART8 == uart) { - exRCC_APB1PeriphReset(RCC_APB1ENR_UART8); - } -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Initializes the uart peripheral according to the specified -/// parameters in the UART_InitStruct . -/// @param uart: Select the UART or the UART peripheral. -/// @param init_struct: pointer to a UART_InitTypeDef structure -/// that contains the configuration information for the -/// specified UART peripheral. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void UART_Init(UART_TypeDef* uart, UART_InitTypeDef* init_struct) -{ - u32 apbclock = 0x00; - // UART CCR Configuration - MODIFY_REG(uart->CCR, UART_CCR_CHAR, init_struct->WordLength); - - - MODIFY_REG(uart->CCR, (UART_CCR_SPB0 | UART_CCR_SPB1), init_struct->StopBits); - - MODIFY_REG(uart->CCR, (UART_CCR_PEN | UART_CCR_PSEL), init_struct->Parity); - - // UART GCR Configuration - MODIFY_REG(uart->GCR, (UART_GCR_TX | UART_GCR_RX), init_struct->Mode); - MODIFY_REG(uart->GCR, UART_GCR_AUTOFLOW, init_struct->HWFlowControl); - - //UART BRR Configuration - //Configure the UART Baud Rate - if (uart == UART1) { - - apbclock = RCC_GetPCLK2Freq(); - } - else { - apbclock = RCC_GetPCLK1Freq(); - } - // Determine the UART_baud - uart->BRR = (apbclock / init_struct->BaudRate) / 16; - uart->FRA = (apbclock / init_struct->BaudRate) % 16; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Fills each UART_InitStruct member with its default value. -/// @param init_struct: pointer to a UART_InitTypeDef structure -/// which will be initialized. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void UART_StructInit(UART_InitTypeDef* init_struct) -{ - // UART_InitStruct members default value - init_struct->BaudRate = 9600; - init_struct->WordLength = UART_WordLength_8b; - init_struct->StopBits = UART_StopBits_1; - init_struct->Parity = UART_Parity_No; - init_struct->Mode = UART_GCR_RX | UART_GCR_TX; - init_struct->HWFlowControl = UART_HWFlowControl_None; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the specified UART peripheral. -/// @param uart: Select the UART or the UART peripheral. -/// @param state: new state of the uart peripheral. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void UART_Cmd(UART_TypeDef* uart, FunctionalState state) -{ - MODIFY_REG(uart->GCR, UART_GCR_UART, state << UART_GCR_UART_Pos); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the specified UART interrupts. -/// @param uart: Select the UART or the UART peripheral. -/// @param it: specifies the UART interrupt sources to be -/// enabled or disabled. -/// This parameter can be one of the following values: -/// @arg UART_IT_ERR: Error interrupt(Frame error,) -/// @arg UART_IT_PE: Parity Error interrupt -/// @arg UART_OVER_ERR: overrun Error interrupt -/// @arg UART_IT_RXIEN: Receive Data register interrupt -/// @arg UART_IT_TXIEN: Tansmit Data Register empty interrupt -/// -/// @param state: new state of the specified uart interrupts. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void UART_ITConfig(UART_TypeDef* uart, u16 it, FunctionalState state) -{ - (state) ? (uart->IER |= it) : (uart->IER &= ~it); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the UART DMA interface. -/// @param uart: Select the UART or the UART peripheral. -/// @param dma_request: specifies the DMA request. -/// This parameter can be any combination of the following values: -/// @arg UART_DMAReq_EN: UART DMA transmit request -/// -/// @param state: new state of the DMA Request sources. -/// This parameter can be: ENABLE or DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void UART_DMACmd(UART_TypeDef* uart, u16 dma_request, FunctionalState state) -{ - MODIFY_REG(uart->GCR, UART_GCR_DMA, state << UART_GCR_DMA_Pos); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Transmits single data through the uart peripheral. -/// @param uart: Select the UART or the UART peripheral. -/// @param Data: the data to transmit. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void UART_SendData(UART_TypeDef* uart, u16 value) -{ - // Transmit Data - WRITE_REG(uart->TDR, (value & 0xFFU)); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Returns the most recent received data by the uart peripheral. -/// @param uart: Select the UART or the UART peripheral. -/// @retval The received data. -//////////////////////////////////////////////////////////////////////////////// -u16 UART_ReceiveData(UART_TypeDef* uart) -{ - // Receive Data - return (u16)(uart->RDR & 0xFFU); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Checks whether the specified UART flag is set or not. -/// @param uart: Select the UART or the UART peripheral. -/// @param flag: specifies the flag to check. -/// This parameter can be one of the following values: -/// @arg UART_FLAG_TXEMPTY: Transmit data register empty flag -/// @arg UART_FLAG_TXFULL: Transmit data buffer full -/// @arg UART_FLAG_RXAVL: RX Buffer has a byte flag -/// @arg UART_FLAG_TXEPT: tx and shifter are emptys flag -/// @retval The new state of UART_FLAG (SET or RESET). -//////////////////////////////////////////////////////////////////////////////// -FlagStatus UART_GetFlagStatus(UART_TypeDef* uart, u16 flag) -{ - return (uart->CSR & flag) ? SET : RESET; -} - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Checks whether the specified UART interrupt has occurred or not. -/// @param uart: Select the UART or the UART peripheral. -/// @param it: specifies the UART interrupt source to check. -/// This parameter can be one of the following values: -/// @arg UART_IT_ERR: Error interrupt(Frame error,) -/// @arg UART_IT_PE: Parity Error interrupt -/// @arg UART_OVER_ERR: overrun Error interrupt -/// @arg UART_IT_RXIEN: Receive Data register interrupt -/// @arg UART_IT_TXIEN: Tansmit Data Register empty interrupt -/// @retval The new state of UART_IT (SET or RESET). -//////////////////////////////////////////////////////////////////////////////// -ITStatus UART_GetITStatus(UART_TypeDef* uart, u16 it) -{ - return (uart->ISR & it) ? SET : RESET; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Clears the uart interrupt pending bits. -/// @param uart: Select the UART or the UART peripheral. -/// @param it: specifies the interrupt pending bit to clear. -/// This parameter can be one of the following values: -/// @arg UART_IT_ERR: Error interrupt(Frame error,) -/// @arg UART_IT_PE: Parity Error interrupt -/// @arg UART_OVER_ERR: overrun Error interrupt -/// @arg UART_IT_RXIEN: Receive Data register interrupt -/// @arg UART_IT_TXIEN: Tansmit Data Register empty interrupt -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void UART_ClearITPendingBit(UART_TypeDef* uart, u16 it) -{ - //clear UART_IT pendings bit - uart->ICR = it; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Selects the UART WakeUp method. -/// @param uart: Select the UART or the UART peripheral. -/// @param mode: specifies the UART wakeup method. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void UART_WakeUpConfig(UART_TypeDef* uart, UART_WakeUp_TypeDef mode) -{ - MODIFY_REG(uart->CCR, UART_CCR_WAKE, mode); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Determines if the UART is in mute mode or not. -/// @param uart: Select the UART or the UART peripheral. -/// @param state: new state of the UART mute mode. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void UART_ReceiverWakeUpCmd(UART_TypeDef* uart, FunctionalState state) -{ - MODIFY_REG(uart->CCR, UART_CCR_RWU, state << UART_CCR_RWU_Pos); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Sets the address of the UART Rx Address. -/// @param uart: Select the UART or the UART peripheral. -/// @param address: Indicates the address of the UART Rx Address. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void UART_SetRXAddress(UART_TypeDef* uart, u8 address) -{ - MODIFY_REG(uart->RXAR, UART_RXAR_ADDR, address); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Sets the address of the UART Rx MASK. -/// @param uart: Select the UART or the UART peripheral. -/// @param address: Indicates the address of the UART Rx MASK. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void UART_SetRXMASK(UART_TypeDef* uart, u8 address) -{ - MODIFY_REG(uart->RXMR, UART_RXMR_MASK, address); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ENBALE or DISABLE the UART's 9bit. -/// @param uart: Select the UART or the UART peripheral. -/// @param state: new state of the UART 9 bit. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void UART_Enable9bit(UART_TypeDef* uart, FunctionalState state) -{ - MODIFY_REG(uart->CCR, UART_CCR_B8EN, state << UART_CCR_B8EN_Pos); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Set the UART's 9bit Level. -/// @param uart: Select the UART or the UART peripheral. -/// @param state: new state of the UART 9 bit. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void UART_Set9bitLevel(UART_TypeDef* uart, FunctionalState state) -{ - MODIFY_REG(uart->CCR, UART_CCR_B8TXD, state << UART_CCR_B8TXD_Pos); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Set the UART's 9bit Polarity. -/// @param uart: Select the UART or the UART peripheral. -/// @param polarity: new state of the UART 9 bit Polarity. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void UART_Set9bitPolarity(UART_TypeDef* uart, UART_9bit_Polarity_TypeDef polarity) -{ - MODIFY_REG(uart->CCR, UART_CCR_B8POL, polarity); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Set the UART's 9bit Automatic Toggle. -/// @param uart: Select the UART or the UART peripheral. -/// @param state: new state of the UART 9 bit Automatic Toggle. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void UART_Set9bitAutomaticToggle(UART_TypeDef* uart, FunctionalState state) -{ - MODIFY_REG(uart->CCR, UART_CCR_B8TOG, state << UART_CCR_B8TOG_Pos); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the UART Half Duplex communication. -/// @param uart: Select the UART or the UART peripheral. -/// @param state: new state of the UART Communication. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void UART_HalfDuplexCmd(UART_TypeDef* uart, FunctionalState state) -{ - MODIFY_REG(uart->SCR, UART_SCR_HDSEL, state << UART_SCR_HDSEL_Pos); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Sets the specified UART guard time. -/// @param uart: Select the UART or the UART peripheral. -/// @param guard_time: specifies the guard time. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void UART_SetGuardTime(UART_TypeDef* uart, u8 guard_time) -{ - MODIFY_REG(uart->SCR, UART_SCR_SCFCNT, guard_time << UART_SCR_SCFCNT_Pos); - // Clear the UART Guard time - // uart->SCR &= SCR_SCFCNT_Mask; - // Set the UART guard time - // uart->SCR |= (u16)((u16)guard_time << 0x04); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables the UART's Smart Card mode. -/// @param uart: Select the UART or the UART peripheral. -/// @param state: new state of the Smart Card mode. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void UART_SmartCardCmd(UART_TypeDef* uart, FunctionalState state) -{ - MODIFY_REG(uart->SCR, UART_SCR_SCEN, state << UART_SCR_SCEN_Pos); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables or disables NACK transmission. -/// @param uart: Select the UART or the UART peripheral. -/// @param state: new state of the NACK transmission. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void UART_SmartCardNACKCmd(UART_TypeDef* uart, FunctionalState state) -{ - MODIFY_REG(uart->SCR, UART_SCR_SCARB, state << UART_SCR_SCARB_Pos); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Transmits break characters. -/// @param uart: Select the UART or the UART peripheral. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void UART_SendBreak(UART_TypeDef* uart) -{ - SET_BIT(uart->CCR, UART_CCR_BRK); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enable or Disable Auto Baud-Rate Detection -/// @param uart: Select the UART or the UART peripheral. -/// @param state: new state of the UART AutoBaudRate Detection. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void UART_AutoBaudRateCmd(UART_TypeDef* uart, FunctionalState state) -{ - state ? SET_BIT(uart->ABRCR, UART_ABRCR_ABREN) : CLEAR_BIT(uart->ABRCR, UART_ABRCR_ABREN) ; -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief AutoBaudRate. -/// @param uart: Select the UART or the UART peripheral. -/// value: special character. -/// state: ENABLE/DISABLE. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void UART_AutoBaudRateSet(UART_TypeDef* uart, UART_AutoBaud_TypeDef value, FunctionalState state) -{ - CLEAR_BIT(uart->ABRCR, UART_ABRCR_ABREN); - //This bit field can only be written when ABREN = 0 or the UART is disabled (UARTEN=0). - - if ((value == ABRMODE_FALLING_TO_RISINGEDGE1BIT) || (value == ABRMODE_STARTBIT) || (value == ABRMODE_VALUE0XFF)) { - //UART measures the duration of the start bit (falling edge) to first rising edge - //FORMER edge = 0 LATTER edge= 1, from fist falling edge to rising edge = one bit - //___ _ _______ - // |_|1 x x x x x x x| = Bxxxx xxx1 F to U = 1 start bit - // - MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \ - UART_ABRCR_LATTER | UART_ABRCR_BITCNT_MODE0 ); - } - else if((value == ABRMODE_FALLING_TO_RISINGEDGE2BIT) || (value == Data_FE)) { - //UART measures the duration of the start bit (falling edge) to first rising edge - //FORMER edge = 0 LATTER edge= 1, from fist falling edge to rising edge = two bit - //___ _ _______ - // |_ _|1 x x x x x x| = Bxxxx xx10 F to U = 2 - // - MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \ - UART_ABRCR_LATTER | UART_ABRCR_BITCNT_MODE1); - } - else if((value == ABRMODE_FALLING_TO_RISINGEDGE4BIT) || (value == Data_F8)) { - //UART measures the duration of the start bit (falling edge) to first rising edge - //FORMER edge = 0 LATTER edge= 1, from fist falling edge to rising edge = four bit - //___ _ _______ - // |_ _ _ _|1 x x x x| = Bxxxx 1000 F to U = 4 - // - MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \ - UART_ABRCR_LATTER | UART_ABRCR_BITCNT_MODE2); - } - else if((value == ABRMODE_FALLING_TO_RISINGEDGE8BIT) || (value == ABRMODE_VALUE0X80)) { - //UART measures the duration of the start bit (falling edge) to first rising edge - //FORMER edge = 0 LATTER edge= 1, from fist falling edge to rising edge = eight bit - //___ _ ______ - // |_ _ _ _ _ _ _ _|1 = B1000 0000 F to U = 8 - // - MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \ - UART_ABRCR_LATTER | UART_ABRCR_BITCNT_MODE3); - } - else if((value == ABRMODE_FALLING_TO_FALLINGEDGE2BIT) || (value == ABRMODE_VALUE0X55)) { - //UART measures the duration of the start bit (falling edge) to next falling edge - //FORMER edge = 0 LATTER edge= 0, from fist falling edge to next falling edge = two bit - //___ _ ______ - // |_|1|_|x x x x x x| = Bxxxx xx01 F to F = 2 0x55 and Falling to Falling - // - MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \ - UART_ABRCR_BITCNT_MODE1); - } - else if((value == ABRMODE_FALLING_TO_FALLINGEDGE4BIT) || (value == ABRMODE_VALUE0XF7)) { - //UART measures the duration of the start bit (falling edge) to next falling edge - //FORMER edge = 0 LATTER edge= 0, from fist falling edge to next falling edge = four bit - //___ _ _ _ ______ - // |_|1 1 1|_|x x x x| = Bxxxx 0111 F to F = 4 - // - MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \ - UART_ABRCR_BITCNT_MODE2); - } - else if((value == ABRMODE_FALLING_TO_FALLINGEDGE8BIT) || (value == ABRMODE_VALUE0x7F)) { - //UART measures the duration of the start bit (falling edge) to next falling edge - //FORMER edge = 0 LATTER edge= 0, from fist falling edge to next falling edge = eight bit - //___ _ _ _ _ _ _ _ ______ - // |_|1 1 1 1 1 1 1|_| = B0111 1111 F to F = 8 0x7F - // - MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \ - UART_ABRCR_BITCNT_MODE3); - } - - else { - //UART measures the duration of the start bit (falling edge) to next falling edge - //FORMER edge = 0 LATTER edge= 0, from fist falling edge to next falling edge = eight bit - //___ _ _ _ _ _ _ _ ______ - // |_|1 1 1 1 1 1 1|_| = B0111 1111 F to F = 8 0x7F - // - MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \ - UART_ABRCR_BITCNT_MODE3); - } - if(state == ENABLE) { - SET_BIT(uart->ABRCR, UART_ABRCR_ABREN); - } -} -/// @} - -/// @} - -/// @} diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uid.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uid.c deleted file mode 100644 index e51bfcade..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uid.c +++ /dev/null @@ -1,55 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_uid.c -/// @author AE TEAM -/// @brief THIS FILE PROVIDES ALL THE UID FIRMWARE FUNCTIONS. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

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-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#define _HAL_UID_C_ - -// Files includes -#include "hal_uid.h" -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -///@addtogroup UID_HAL -///@{ - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup UID_Exported_Functions -/// @{ - -u8 device_id_data[12] = {0}; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Get device ID. -/// @param None. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void GetChipUID(void) -{ - u8 i; - - for (i = 0; i < 12; i++) { - device_id_data[i] = *((vu8*)(UID_BASE + i)); - } -} - -/// @} - -/// @} - -/// @} diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_ver.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_ver.c deleted file mode 100644 index 9d771396c..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_ver.c +++ /dev/null @@ -1,131 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_ver.c -/// @author AE TEAM -/// @brief THIS FILE PROVIDES ALL THE LIB AND THE CHIPSET INFORMATION. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

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-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#define _HAL_VER_C_ - -// Files includes -#include "hal_ver.h" - - -// MM32 Library version is 0.90 - -#define __MM32_LIB_VERSION_MAIN (0x0U) //!< [31:24] main version -#define __MM32_LIB_VERSION_SUB1 (0x9U) //!< [23:16] sub1 version -#define __MM32_LIB_VERSION_SUB2 (0x0U) //!< [15:8] sub2 version -#define __MM32_LIB_VERSION_RC (0x00U) //!< [7:0] release candidate -#define __MM32_LIB_VERSION ((__MM32_LIB_VERSION_MAIN << 24U)\ - |(__MM32_LIB_VERSION_SUB1 << 16U)\ - |(__MM32_LIB_VERSION_SUB2 << 8U )\ - |(__MM32_LIB_VERSION_RC)) - -// MM32 Library release date is 2021-05-10 (YYYY-MM-DD) -#define __MM32_LIB_RELESE_YEARH (0x20U) //!< [31:24] release year high -#define __MM32_LIB_RELESE_YEARL (0x21U) //!< [23:16] release year low -#define __MM32_LIB_RELESE_MONTH (0x05U) //!< [15:8] release month -#define __MM32_LIB_RELESE_DAY (0x10U) //!< [7:0] release day -#define __MM32_LIB_RELESE_DATE ((__MM32_LIB_RELESE_YEARH << 24U)\ - |(__MM32_LIB_RELESE_YEARL << 16U)\ - |(__MM32_LIB_RELESE_MONTH << 8U )\ - |(__MM32_LIB_RELESE_DAY)) -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -///@addtogroup VER_HAL -///@{ - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup Lib and chipset_Exported_Functions -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @brief This method returns the Lib revision. -/// @param None. -/// @retval return the Lib version. -//////////////////////////////////////////////////////////////////////////////// -u32 Get_MM32LibVersion(void) -{ - return __MM32_LIB_VERSION; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief This method returns the Lib release date. -/// @param None. -/// @retval return the Lib release date. -//////////////////////////////////////////////////////////////////////////////// -u32 Get_MM32LibReleaseDate(void) -{ - return __MM32_LIB_RELESE_DATE; -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Returns the device revision identifier. -/// @param None. -/// @retval return the device revision identifier. -//////////////////////////////////////////////////////////////////////////////// -u32 Get_ChipsetREVID(void) -{ - return((DBGMCU->IDCODE) & 0xF ); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Returns the device identifier.. -/// @param None. -/// @retval return the device Device identifier. -//////////////////////////////////////////////////////////////////////////////// -u32 Get_ChipsetDEVID(void) -{ - return((DBGMCU->IDCODE) ); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Returns first word of the unique device identifier (UID based on 96 bits) -/// @param None. -/// @retval Device identifier -//////////////////////////////////////////////////////////////////////////////// -u32 Get_ChipsetUIDw0(void) -{ - return(READ_REG(*((vu32*)UID_BASE))); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Returns second word of the unique device identifier (UID based on 96 bits) -/// @param None. -/// @retval Device identifier -//////////////////////////////////////////////////////////////////////////////// -u32 Get_ChipsetUIDw1(void) -{ - return(READ_REG(*((vu32*)(UID_BASE + 4U)))); -} -//////////////////////////////////////////////////////////////////////////////// -/// @brief Returns third word of the unique device identifier (UID based on 96 bits) -/// @param None. -/// @retval Device identifier -//////////////////////////////////////////////////////////////////////////////// -u32 Get_ChipsetUIDw2(void) -{ - return(READ_REG(*((vu32*)(UID_BASE + 8U)))); -} - - - - - -/// @} - -/// @} - -/// @} diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_wwdg.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_wwdg.c deleted file mode 100644 index 05d74b596..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_wwdg.c +++ /dev/null @@ -1,147 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_wwdg.c -/// @author AE TEAM -/// @brief THIS FILE PROVIDES ALL THE WWDG FIRMWARE FUNCTIONS. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

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-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#define _HAL_WWDG_C_ - -// Files includes -#include "hal_wwdg.h" -#include "hal_rcc.h" - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup MM32_Hardware_Abstract_Layer -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup WWDG_HAL -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @addtogroup WWDG_Exported_Functions -/// @{ - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Deinitializes the WWDG peripheral registers to their default reset -/// values. -/// @param None. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void WWDG_DeInit() -{ - exRCC_APB1PeriphReset(RCC_APB1RSTR_WWDG); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Sets the WWDG Prescaler. -/// @param WWDG_Prescaler: specifies the WWDG Prescaler. -/// This parameter can be one of the following values: -/// @arg WWDG_Prescaler_1: WWDG counter clock = APB1CLK / 4096 / 1 -/// @arg WWDG_Prescaler_2: WWDG counter clock = APB1CLK / 4096 / 2 -/// @arg WWDG_Prescaler_4: WWDG counter clock = APB1CLK / 4096 / 4 -/// @arg WWDG_Prescaler_8: WWDG counter clock = APB1CLK / 4096 / 8 -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void WWDG_SetPrescaler(u32 prescaler) -{ - WWDG->CFGR = (WWDG->CFGR & ~WWDG_CFGR_WDGTB) | prescaler; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Sets the WWDG window value. -/// @param WindowValue: specifies the window value to be compared to the -/// downcounter. -/// This parameter value must be lower than 0x80. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void WWDG_SetWindowValue(u8 window_value) -{ - WWDG->CFGR = (WWDG->CFGR & ~WWDG_CFGR_WINDOW) | (window_value & WWDG_CFGR_WINDOW); -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables the WWDG Early Wakeup interrupt(EWI). -/// @note Once enabled this interrupt cannot be disabled except by a system -/// reset. -/// @param None. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void WWDG_EnableIT() -{ - WWDG->CFGR |= WWDG_CFGR_EWI; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Sets the WWDG counter value. -/// @param Counter: specifies the watchdog counter value. -/// This parameter must be a number between 0x40 and 0x7F (to prevent -/// generating an immediate reset). -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void WWDG_SetCounter(u8 count) -{ - WWDG->CR = count & WWDG_CFGR_WINDOW; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables WWDG and load the counter value. -/// @param Counter: specifies the watchdog counter value. -/// This parameter must be a number between 0x40 and 0x7F (to prevent -/// generating an immediate reset). -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -u32 WWDG_GetCounter() -{ - return WWDG->CR & WWDG_CR_CNT; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Enables WWDG and load the counter value. -/// @param Counter: specifies the watchdog counter value. -/// This parameter must be a number between 0x40 and 0x7F (to prevent -/// generating an immediate reset). -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void WWDG_Enable(u8 count) -{ - WWDG->CR = WWDG_CR_WDGA | count; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Checks whether the Early Wakeup interrupt flag is set or not. -/// @param None. -/// @retval The new state of the Early Wakeup interrupt flag (SET or RESET). -//////////////////////////////////////////////////////////////////////////////// -FlagStatus WWDG_GetFlagStatus() -{ - return WWDG->SR ? SET : RESET; -} - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Clears Early Wakeup interrupt flag. -/// @param None. -/// @retval None. -//////////////////////////////////////////////////////////////////////////////// -void WWDG_ClearFlag() -{ - WWDG->SR &= ~WWDG_SR_EWIF; -} - -/// @} - -/// @} - -/// @} diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_device.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_device.h deleted file mode 100644 index 1a85c131a..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_device.h +++ /dev/null @@ -1,23 +0,0 @@ -///----------------------------------------------------------------------------- -/// @file mm32_device.h -/// @brief CMSIS Cortex-M Peripheral Access Layer for MindMotion -/// microcontroller devices -/// -/// This is a convenience header file for defining the part number on the -/// build command line, instead of specifying the part specific header file. -/// -/// Example: Add MM32 series to your build options, to define part -/// Add "#include "mm32_device.h" to your source files -/// -/// -/// -/// -///----------------------------------------------------------------------------- - -#ifndef __MM32_DEVICE_H -#define __MM32_DEVICE_H - -#include "mm32_reg.h" - -#endif // __MM32_DEVICE_H - diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_reg.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_reg.h deleted file mode 100644 index dfba84215..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_reg.h +++ /dev/null @@ -1,71 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file mm32_reg.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF -/// MM32 FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -//////////////////////////////////////////////////////////////////////////////// -#ifndef __MM32_REG_H -#define __MM32_REG_H - -#include -#include -#include "types.h" - - - - -#include "reg_common.h" -#include "reg_adc.h" -#include "reg_bkp.h" -#include "reg_can.h" -#include "reg_comp.h" -#include "reg_crc.h" -#include "reg_crs.h" -#include "reg_dac.h" -#include "reg_dbg.h" -#include "reg_dma.h" -#include "reg_exti.h" -#include "reg_eth.h" -#include "reg_flash.h" -#include "reg_gpio.h" -#include "reg_i2c.h" -#include "reg_iwdg.h" -#include "reg_pwm.h" -#include "reg_pwr.h" -#include "reg_rcc.h" -#include "reg_rtc.h" -#include "reg_sdio.h" -#include "reg_spi.h" -#include "reg_syscfg.h" -#include "reg_tim.h" -#include "reg_uart.h" -#include "reg_usb_otg_fs.h" -#include "reg_wwdg.h" - -//////////////////////////////////////////////////////////////////////////////// -#include "mm32_reg_redefine_v1.h" -//////////////////////////////////////////////////////////////////////////////// - -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -#endif // __MM32_REG_H -//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_reg_redefine_v1.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_reg_redefine_v1.h deleted file mode 100644 index 6cdd79ead..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_reg_redefine_v1.h +++ /dev/null @@ -1,1175 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file mm32_reg_define_v1.H -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE define for version compatibility define -/// FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#ifndef __MM32_REG_DEFINE_V1_H -#define __MM32_REG_DEFINE_V1_H - -// Files includes - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Version compatibility definition -//////////////////////////////////////////////////////////////////////////////// - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief redefine for register -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -/// @brief redefine for ADC of MCU register -//////////////////////////////////////////////////////////////////////////////// - -#define ADC_COMP_IRQHandler ADC1_COMP_IRQHandler - -#define ADDATA_DATA ADC_DR_DATA - -#define ADDATA_CHANNELSEL ADC_DR_CH -#define ADDATA_CHANNELSEL_0 ADC_DR_CH0 -#define ADDATA_CHANNELSEL_1 ADC_DR_CH1 -#define ADDATA_CHANNELSEL_2 ADC_DR_CH2 -#define ADDATA_CHANNELSEL_3 ADC_DR_CH3 -#define ADDATA_CHANNELSEL_4 ADC_DR_CH4 -#define ADDATA_CHANNELSEL_5 ADC_DR_CH5 -#define ADDATA_CHANNELSEL_6 ADC_DR_CH6 -#define ADDATA_CHANNELSEL_7 ADC_DR_CH7 - - - - -#define ADDATA_CHANNELSEL_CH8 ADC_DR_CH8 -#define ADDATA_CHANNELSEL_CH9 ADC_DR_CH9 -#define ADDATA_CHANNELSEL_CH10 ADC_DR_CH10 -#define ADDATA_CHANNELSEL_CH11 ADC_DR_CH11 -#define ADDATA_CHANNELSEL_CH12 ADC_DR_CH12 -#define ADDATA_CHANNELSEL_CH13 ADC_DR_CH13 -#define ADDATA_CHANNELSEL_CH14 ADC_DR_CH14 -#define ADDATA_CHANNELSEL_CH15 ADC_DR_CH15 -#define ADDATA_CHANNELSEL_TempSensor ADC_DR_TempSensor -#define ADDATA_CHANNELSEL_VolSensor ADC_DR_VoltRef - - -#define ADDATA_OVERRUN ADC_DR_OVERRUN -#define ADDATA_VALID ADC_DR_VALID - -#define ADCFG_ADEN ADC_CFGR_ADEN -#define ADCFG_ADWEN ADC_CFGR_ADWEN - -#define ADCFG_RSLTCTL ADC_CFGR_RSLTCTL -#define ADCFG_RSLTCTL_12 ADC_CFGR_RSLTCTL_12 -#define ADCFG_RSLTCTL_11 ADC_CFGR_RSLTCTL_11 -#define ADCFG_RSLTCTL_10 ADC_CFGR_RSLTCTL_10 -#define ADCFG_RSLTCTL_9 ADC_CFGR_RSLTCTL_9 -#define ADCFG_RSLTCTL_8 ADC_CFGR_RSLTCTL_8 - - -#define ADCFG_TSEN ADC_CFGR_TEN -#define ADCFG_VSEN ADC_CFGR_VEN - -#define ADCFG_ADCPRE ADC_CFGR_PRE -#define ADCFG_ADCPRE_2 ADC_CFGR_PRE_2 -#define ADCFG_ADCPRE_4 ADC_CFGR_PRE_4 -#define ADCFG_ADCPRE_6 ADC_CFGR_PRE_6 -#define ADCFG_ADCPRE_8 ADC_CFGR_PRE_8 -#define ADCFG_ADCPRE_10 ADC_CFGR_PRE_10 -#define ADCFG_ADCPRE_12 ADC_CFGR_PRE_12 -#define ADCFG_ADCPRE_14 ADC_CFGR_PRE_14 -#define ADCFG_ADCPRE_16 ADC_CFGR_PRE_16 -#define ADCFG_SAMCTL ADC_CFGR_SAMCTL -#define ADCFG_SAMCTL_1_5 ADC_CFGR_SAMCTL_1_5 -#define ADCFG_SAMCTL_7_5 ADC_CFGR_SAMCTL_7_5 -#define ADCFG_SAMCTL_13_5 ADC_CFGR_SAMCTL_13_5 -#define ADCFG_SAMCTL_28_5 ADC_CFGR_SAMCTL_28_5 -#define ADCFG_SAMCTL_41_5 ADC_CFGR_SAMCTL_41_5 -#define ADCFG_SAMCTL_55_5 ADC_CFGR_SAMCTL_55_5 -#define ADCFG_SAMCTL_71_5 ADC_CFGR_SAMCTL_71_5 -#define ADCFG_SAMCTL_239_5 ADC_CFGR_SAMCTL_239_5 - - -#define ADCFG_ADCPRE_3 ADC_CFGR_PRE_3 -#define ADCFG_ADCPRE_5 ADC_CFGR_PRE_5 -#define ADCFG_ADCPRE_7 ADC_CFGR_PRE_7 -#define ADCFG_ADCPRE_9 ADC_CFGR_PRE_9 -#define ADCFG_ADCPRE_11 ADC_CFGR_PRE_11 -#define ADCFG_ADCPRE_13 ADC_CFGR_PRE_13 -#define ADCFG_ADCPRE_15 ADC_CFGR_PRE_15 -#define ADCFG_ADCPRE_17 ADC_CFGR_PRE_17 -#define ADCFG_SAMCTL_2_5 ADC_CFGR_SAMCTL_2_5 -#define ADCFG_SAMCTL_3_5 ADC_CFGR_SAMCTL_3_5 -#define ADCFG_SAMCTL_4_5 ADC_CFGR_SAMCTL_4_5 -#define ADCFG_SAMCTL_5_5 ADC_CFGR_SAMCTL_5_5 -#define ADCFG_SAMCTL_6_5 ADC_CFGR_SAMCTL_6_5 - -#define ADCR_ADIE ADC_CR_ADIE -#define ADCR_ADWIE ADC_CR_ADWIE -#define ADCR_TRGEN ADC_CR_TRGEN -#define ADCR_DMAEN ADC_CR_DMAEN -#define ADCR_ADST ADC_CR_ADST -#define ADCR_ADMD ADC_CR_MODE -#define ADCR_ADMD_SINGLE ADC_CR_IMM -#define ADCR_ADMD_PERIOD ADC_CR_SCAN -#define ADCR_ADMD_CONTINUE ADC_CR_CONTINUE -#define ADC_Mode_Single ADC_CR_IMM -#define ADC_Mode_Single_Period ADC_CR_SCAN -#define ADC_Mode_Continuous_Scan ADC_CR_CONTINUE - - -#define ADCR_ALIGN ADC_CR_ALIGN -#define ADCR_ALIGN_LEFT ADC_CR_LEFT -#define ADCR_ALIGN_RIGHT ADC_CR_RIGHT -#define ADCR_CMPCH_Pos ADC_CR_CMPCH_Pos -#define ADCR_CMPCH ADC_CR_CMPCH -#define ADCR_CMPCH_0 ADC_CR_CMPCH_0 -#define ADCR_CMPCH_1 ADC_CR_CMPCH_1 -#define ADCR_CMPCH_2 ADC_CR_CMPCH_2 -#define ADCR_CMPCH_4 ADC_CR_CMPCH_4 -#define ADCR_CMPCH_5 ADC_CR_CMPCH_5 -#define ADCR_CMPCH_6 ADC_CR_CMPCH_6 -#define ADCR_CMPCH_7 ADC_CR_CMPCH_7 -#define ADCR_CMPCH_8 ADC_CR_CMPCH_8 -#define ADCR_CMPCH_9 ADC_CR_CMPCH_9 -#define ADCR_CMPCH_10 ADC_CR_CMPCH_10 -#define ADCR_CMPCH_11 ADC_CR_CMPCH_11 -#define ADCR_CMPCH_13 ADC_CR_CMPCH_13 -#define ADCR_CMPCH_14 ADC_CR_CMPCH_14 -#define ADCR_CMPCH_ALL ADC_CR_CMPCH_ALL - - -#define ADCR_TRGSEL ADC_CR_TRGSEL -#define ADCR_TRGSEL_T1_CC1 ADC_CR_T1_CC1 -#define ADCR_TRGSEL_T1_CC2 ADC_CR_T1_CC2 -#define ADCR_TRGSEL_T1_CC3 ADC_CR_T1_CC3 -#define ADCR_TRGSEL_T2_CC2 ADC_CR_T2_CC2 -#define ADCR_TRGSEL_T3_TRGO ADC_CR_T3_TRIG -#define ADCR_TRGSEL_EXTI_11 ADC_CR_EXTI_11 - - - -#define ADCR_TRGSEL_T1_CC4_CC5 ADC_CR_T1_CC4_CC5 -#define ADCR_TRGSEL_T3_CC1 ADC_CR_T3_CC1 -#define ADCR_TRGSEL_T1_TRGO ADC_CR_T1_TRIG -#define ADCR_TRGSEL_T8_CC4 ADC_CR_T8_CC4 -#define ADCR_TRGSEL_T8_CC4_CC5 ADC_CR_T8_CC4_CC5 -#define ADCR_TRGSEL_T2_CC1 ADC_CR_T2_CC1 -#define ADCR_TRGSEL_T3_CC4 ADC_CR_T3_CC4 -#define ADCR_TRGSEL_T2_TRGO ADC_CR_T2_TRIG -#define ADCR_TRGSEL_T8_CC5 ADC_CR_T8_CC5 -#define ADCR_TRGSEL_EXTI_15 ADC_CR_EXTI_15 -#define ADCR_TRGSEL_TIM1_CC4 ADC_CR_TIM1_CC4 -#define ADCR_TRGSEL_TIM1_CC5 ADC_CR_TIM1_CC5 -#define ADCR_SCANDIR ADC_CR_SCANDIR -#define ADCR_TRGSHIFT ADC_CR_TRGSHIFT -#define ADCR_TRGSHIFT_0 ADC_CR_TRGSHIFT_0 -#define ADCR_TRGSHIFT_4 ADC_CR_TRGSHIFT_4 -#define ADCR_TRGSHIFT_16 ADC_CR_TRGSHIFT_16 -#define ADCR_TRGSHIFT_32 ADC_CR_TRGSHIFT_32 -#define ADCR_TRGSHIFT_64 ADC_CR_TRGSHIFT_64 -#define ADCR_TRGSHIFT_128 ADC_CR_TRGSHIFT_128 -#define ADCR_TRGSHIFT_256 ADC_CR_TRGSHIFT_256 -#define ADCR_TRGSHIFT_512 ADC_CR_TRGSHIFT_512 -#define ADCR_CALIBEN ADC_CR_CALIBEN -#define ADCR_CALIBSEL ADC_CR_CALIBSEL - -#define ADCHS_CHEN0 ADC_CHSR_CH0 -#define ADCHS_CHEN1 ADC_CHSR_CH1 -#define ADCHS_CHEN2 ADC_CHSR_CH2 -#define ADCHS_CHEN3 ADC_CHSR_CH3 -#define ADCHS_CHEN4 ADC_CHSR_CH4 -#define ADCHS_CHEN5 ADC_CHSR_CH5 -#define ADCHS_CHEN6 ADC_CHSR_CH6 -#define ADCHS_CHEN7 ADC_CHSR_CH7 -#define ADCHS_ALL ADC_CHSR_CHALL - - -#define ADCHS_CHEN8 ADC_CHSR_CH8 -#define ADCHS_CHEN9 ADC_CHSR_CH9 -#define ADCHS_CHENTS ADC_CHSR_CHT -#define ADCHS_CHENVS ADC_CHSR_CHV -#define ADCHS_CHEN8 ADC_CHSR_CH8 -#define ADCHS_CHEN9 ADC_CHSR_CH9 -#define ADCHS_CHEN10 ADC_CHSR_CH10 -#define ADCHS_CHEN11 ADC_CHSR_CH11 -#define ADCHS_CHEN12 ADC_CHSR_CH12 -#define ADCHS_CHEN13 ADC_CHSR_CH13 -#define ADCHS_CHEN14 ADC_CHSR_CH14 -#define ADCHS_CHEN15 ADC_CHSR_CH15 -#define ADCHS_CHENTS ADC_CHSR_CHT -#define ADCHS_CHENVS ADC_CHSR_CHV - - -#define ADCMPR_CMPLDATA ADC_CMPR_CMPLDATA -#define ADCMPR_CMPHDATA ADC_CMPR_CMPHDATA - -#define ADSTA_ADIF ADC_SR_ADIF -#define ADSTA_ADWIF ADC_SR_ADWIF -#define ADSTA_BUSY ADC_SR_BUSY -#define ADSTA_CHANNEL ADC_SR_CH -#define ADSTA_CHANNEL_CH0 ADC_SR_CH0 -#define ADSTA_CHANNEL_CH1 ADC_SR_CH1 -#define ADSTA_CHANNEL_CH2 ADC_SR_CH2 -#define ADSTA_CHANNEL_CH3 ADC_SR_CH3 -#define ADSTA_CHANNEL_CH4 ADC_SR_CH4 -#define ADSTA_CHANNEL_CH5 ADC_SR_CH5 -#define ADSTA_CHANNEL_CH6 ADC_SR_CH6 -#define ADSTA_CHANNEL_CH7 ADC_SR_CH7 -#define ADSTA_CHANNEL_CH8 ADC_SR_CH8 -#define ADSTA_CHANNEL_CH9 ADC_SR_CH9 -#define ADSTA_CHANNEL_CH10 ADC_SR_CH10 -#define ADSTA_CHANNEL_CH11 ADC_SR_CH11 -#define ADSTA_CHANNEL_CH13 ADC_SR_CH13 -#define ADSTA_CHANNEL_CH14 ADC_SR_CH14 -#define ADSTA_CHANNEL_CH15 ADC_SR_CH15 -#define ADSTA_VALID ADC_SR_VALID -#define ADSTA_OVERRUN ADC_SR_OVERRUN - -#define ADDR_OVERRUN ADC_CHDR_OVERRUN -#define ADDR_VALID ADC_CHDR_VALID -#define ADDR_DATA ADC_CHDR_DATA - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief redefine for HAL library -//////////////////////////////////////////////////////////////////////////////// - - -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -/// @brief redefine for ADC of HAL library -//////////////////////////////////////////////////////////////////////////////// - - -#define ADC_ExternalTrigConv_T1_CC1 ADC1_ExternalTrigConv_T1_CC1 -#define ADC_ExternalTrigConv_T1_CC2 ADC1_ExternalTrigConv_T1_CC2 -#define ADC_ExternalTrigConv_T1_CC3 ADC1_ExternalTrigConv_T1_CC3 -#define ADC_ExternalTrigConv_T2_CC2 ADC1_ExternalTrigConv_T2_CC2 -#define ADC_ExternalTrigConv_T3_TRIG ADC1_ExternalTrigConv_T3_TRIG -#define ADC_ExternalTrigConv_T3_CC1 ADC1_ExternalTrigConv_T3_CC1 -#define ADC_ExternalTrigConv_EXTI_11 ADC1_ExternalTrigConv_EXTI_11 -#define ADC_ExternalTrigConv_T1_CC4_CC5 ADC1_ExternalTrigConv_T1_CC4_CC5 -#define ADC_ExternalTrigConv_T1_TRIG ADC1_ExternalTrigConv_T1_TRIG -#define ADC_ExternalTrigConv_T8_CC4 ADC1_ExternalTrigConv_T8_CC4 -#define ADC_ExternalTrigConv_T8_CC4_CC5 ADC1_ExternalTrigConv_T8_CC4_CC5 -#define ADC_ExternalTrigConv_T2_CC1 ADC1_ExternalTrigConv_T2_CC1 -#define ADC_ExternalTrigConv_T3_CC4 ADC1_ExternalTrigConv_T3_CC4 -#define ADC_ExternalTrigConv_T2_TRIG ADC1_ExternalTrigConv_T2_TRIG -#define ADC_ExternalTrigConv_T8_CC5 ADC1_ExternalTrigConv_T8_CC5 -#define ADC_ExternalTrigConv_EXTI_15 ADC1_ExternalTrigConv_EXTI_15 -#define ADC_ExternalTrigConv_T1_CC4 ADC1_ExternalTrigConv_T1_CC4 -#define ADC_ExternalTrigConv_T1_CC5 ADC1_ExternalTrigConv_T1_CC5 - - - -#define ADC_SampleTime_1_5Cycles ADC_Samctl_1_5 -#define ADC_SampleTime_7_5Cycles ADC_Samctl_7_5 -#define ADC_SampleTime_13_5Cycles ADC_Samctl_13_5 -#define ADC_SampleTime_28_5Cycles ADC_Samctl_28_5 -#define ADC_SampleTime_41_5Cycles ADC_Samctl_41_5 -#define ADC_SampleTime_55_5Cycles ADC_Samctl_55_5 -#define ADC_SampleTime_71_5Cycles ADC_Samctl_71_5 -#define ADC_SampleTime_239_5Cycles ADC_Samctl_239_5 - - - - - - - - - - - - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Version compatibility definition -//////////////////////////////////////////////////////////////////////////////// -#define AES_KEYR0 AES_KEYRn ///< AES Key Register 0 -#define AES_KEYR1 AES_KEYRn ///< AES Key Register 1 -#define AES_KEYR2 AES_KEYRn ///< AES Key Register 2 -#define AES_KEYR3 AES_KEYRn ///< AES Key Register 3 -#define AES_KEYR4 AES_KEYRn ///< AES Key Register 4 -#define AES_KEYR5 AES_KEYRn ///< AES Key Register 5 -#define AES_KEYR6 AES_KEYRn ///< AES Key Register 6 -#define AES_KEYR7 AES_KEYRn ///< AES Key Register 7 - -#define AES_IVR0 AES_IVRn ///< AES Initialization Vector Register 0 -#define AES_IVR1 AES_IVRn ///< AES Initialization Vector Register 1 -#define AES_IVR2 AES_IVRn ///< AES Initialization Vector Register 2 -#define AES_IVR3 AES_IVRn ///< AES Initialization Vector Register 3 - - -#define CRC_DR_DR CRC_DR_DATA -#define CRC_IDR_IDR CRC_IDR_DATA -//////////////////////////////////////////////////////////////////////////////// -/// @brief Version compatibility definition -//////////////////////////////////////////////////////////////////////////////// -#define CRS_CR_SYNCOKIE CRS_CR_OKIE -#define CRS_CR_SYNCWARNIE CRS_CR_WARNIE -#define CRS_CR_ESYNCIE CRS_CR_EXPTIE -#define CRS_CR_CEN CRS_CR_CNTEN -#define CRS_CFGR_SYNCDIV CRS_CFGR_DIV -#define CRS_CFGR_SYNCSRC CRS_CFGR_SRC -#define CRS_CFGR_SYNCPOL CRS_CFGR_POL -#define CRS_ISR_SYNCOKF CRS_ISR_OKIF -#define CRS_ISR_SYNCWARNF CRS_ISR_WARNIF -#define CRS_ISR_ERRF CRS_ISR_ERRIF -#define CRS_ISR_ESYNCF CRS_ISR_EXPTIF -#define CRS_ISR_SYNCERR CRS_ISR_ERR -#define CRS_ISR_SYNCMISS CRS_ISR_MISS -#define CRS_ISR_TRIMOVF CRS_ISR_OVERFLOW -#define CRS_ICR_SYNCOKC CRS_ICR_OK -#define CRS_ICR_SYNCWARNC CRS_ICR_WARN -#define CRS_ICR_ERRC CRS_ICR_ERR -#define CRS_ICR_ESYNCC CRS_ICR_EXPT - -#define CRS_IT_SYNCOK CRS_ISR_SYNCOKF ///< SYNC event OK -#define CRS_IT_SYNCWARN CRS_ISR_SYNCWARNF ///< SYNC warning -#define CRS_IT_ERR CRS_CR_ERRIE ///< error -#define CRS_IT_ESYNC CRS_ISR_ESYNCF ///< Expected SYNC -#define CRS_IT_TRIMOVF CRS_ISR_TRIMOVF ///< Trimming overflow or underflow -#define CRS_IT_SYNCERR CRS_ISR_SYNCERR ///< SYNC error -#define CRS_IT_SYNCMISS CRS_ISR_SYNCMISS ///< SYNC missed - -#define CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF ///< SYNC event OK -#define CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF ///< SYNC warning -#define CRS_FLAG_ERR CRS_ISR_ERRF ///< error -#define CRS_FLAG_ESYNC CRS_ISR_ESYNCF ///< Expected SYNC -#define CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF ///< Trimming overflow or underflow -#define CRS_FLAG_SYNCERR CRS_ISR_SYNCERR ///< SYNC error -#define CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS ///< SYNC missed -//////////////////////////////////////////////////////////////////////////////// -/// @brief Version compatibility definition -//////////////////////////////////////////////////////////////////////////////// -#define DIV_UNSIGN DIV_CR_USIGN ///< Unsigned enable -//////////////////////////////////////////////////////////////////////////////// -/// @brief DMA type pointer Definition -//////////////////////////////////////////////////////////////////////////////// - - -#define DMA_CCR_MEM2MEM DMA_CCR_M2M - -#define DMA_CCR1_EN DMA_CCR_EN -#define DMA_CCR1_DIR DMA_CCR_DIR -#define DMA_CCR1_CIRC DMA_CCR_CIRC -#define DMA_CCR1_PINC DMA_CCR_PINC -#define DMA_CCR1_MINC DMA_CCR_MINC -#define DMA_CCR1_PSIZE_0 DMA_CCR_PSIZE_0 -#define DMA_CCR1_MSIZE_0 DMA_CCR_MSIZE_0 -#define DMA_CCR1_PL_0 DMA_CCR_PL_0 -#define DMA_CCR1_PSIZE_1 DMA_CCR_PSIZE_1 -#define DMA_CCR1_MSIZE_1 DMA_CCR_MSIZE_1 -#define DMA_CCR1_PL_1 DMA_CCR_PL_1 -#define DMA_CCR1_MEM2MEM DMA_CCR_M2M -#define DMA_CCR1_TCIE DMA_CCR_TCIE - - - - -//////////////////////////////////////////////////////////////////////////////// -#define EXTI_IMR_MR0 EXTI_IMR_0 -#define EXTI_IMR_MR1 EXTI_IMR_1 -#define EXTI_IMR_MR2 EXTI_IMR_2 -#define EXTI_IMR_MR3 EXTI_IMR_3 -#define EXTI_IMR_MR4 EXTI_IMR_4 -#define EXTI_IMR_MR5 EXTI_IMR_5 -#define EXTI_IMR_MR6 EXTI_IMR_6 -#define EXTI_IMR_MR7 EXTI_IMR_7 -#define EXTI_IMR_MR8 EXTI_IMR_8 -#define EXTI_IMR_MR9 EXTI_IMR_9 -#define EXTI_IMR_MR10 EXTI_IMR_10 -#define EXTI_IMR_MR11 EXTI_IMR_11 -#define EXTI_IMR_MR12 EXTI_IMR_12 -#define EXTI_IMR_MR13 EXTI_IMR_13 -#define EXTI_IMR_MR14 EXTI_IMR_14 -#define EXTI_IMR_MR15 EXTI_IMR_15 -#define EXTI_IMR_MR16 EXTI_IMR_16 - -#define EXTI_EMR_MR0 EXTI_EMR_0 -#define EXTI_EMR_MR1 EXTI_EMR_1 -#define EXTI_EMR_MR2 EXTI_EMR_2 -#define EXTI_EMR_MR3 EXTI_EMR_3 -#define EXTI_EMR_MR4 EXTI_EMR_4 -#define EXTI_EMR_MR5 EXTI_EMR_5 -#define EXTI_EMR_MR6 EXTI_EMR_6 -#define EXTI_EMR_MR7 EXTI_EMR_7 -#define EXTI_EMR_MR8 EXTI_EMR_8 -#define EXTI_EMR_MR9 EXTI_EMR_9 -#define EXTI_EMR_MR10 EXTI_EMR_10 -#define EXTI_EMR_MR11 EXTI_EMR_11 -#define EXTI_EMR_MR12 EXTI_EMR_12 -#define EXTI_EMR_MR13 EXTI_EMR_13 -#define EXTI_EMR_MR14 EXTI_EMR_14 -#define EXTI_EMR_MR15 EXTI_EMR_15 -#define EXTI_EMR_MR16 EXTI_EMR_16 - -#define EXTI_RTSR_TR0 EXTI_RTSR_0 -#define EXTI_RTSR_TR1 EXTI_RTSR_1 -#define EXTI_RTSR_TR2 EXTI_RTSR_2 -#define EXTI_RTSR_TR3 EXTI_RTSR_3 -#define EXTI_RTSR_TR4 EXTI_RTSR_4 -#define EXTI_RTSR_TR5 EXTI_RTSR_5 -#define EXTI_RTSR_TR6 EXTI_RTSR_6 -#define EXTI_RTSR_TR7 EXTI_RTSR_7 -#define EXTI_RTSR_TR8 EXTI_RTSR_8 -#define EXTI_RTSR_TR9 EXTI_RTSR_9 -#define EXTI_RTSR_TR10 EXTI_RTSR_10 -#define EXTI_RTSR_TR11 EXTI_RTSR_11 -#define EXTI_RTSR_TR12 EXTI_RTSR_12 -#define EXTI_RTSR_TR13 EXTI_RTSR_13 -#define EXTI_RTSR_TR14 EXTI_RTSR_14 -#define EXTI_RTSR_TR15 EXTI_RTSR_15 -#define EXTI_RTSR_TR16 EXTI_RTSR_16 - -#define EXTI_FTSR_TR0 EXTI_FTSR_0 -#define EXTI_FTSR_TR1 EXTI_FTSR_1 -#define EXTI_FTSR_TR2 EXTI_FTSR_2 -#define EXTI_FTSR_TR3 EXTI_FTSR_3 -#define EXTI_FTSR_TR4 EXTI_FTSR_4 -#define EXTI_FTSR_TR5 EXTI_FTSR_5 -#define EXTI_FTSR_TR6 EXTI_FTSR_6 -#define EXTI_FTSR_TR7 EXTI_FTSR_7 -#define EXTI_FTSR_TR8 EXTI_FTSR_8 -#define EXTI_FTSR_TR9 EXTI_FTSR_9 -#define EXTI_FTSR_TR10 EXTI_FTSR_10 -#define EXTI_FTSR_TR11 EXTI_FTSR_11 -#define EXTI_FTSR_TR12 EXTI_FTSR_12 -#define EXTI_FTSR_TR13 EXTI_FTSR_13 -#define EXTI_FTSR_TR14 EXTI_FTSR_14 -#define EXTI_FTSR_TR15 EXTI_FTSR_15 -#define EXTI_FTSR_TR16 EXTI_FTSR_16 - -#define EXTI_SWIER_SWIER0 EXTI_SWIER_0 -#define EXTI_SWIER_SWIER1 EXTI_SWIER_1 -#define EXTI_SWIER_SWIER2 EXTI_SWIER_2 -#define EXTI_SWIER_SWIER3 EXTI_SWIER_3 -#define EXTI_SWIER_SWIER4 EXTI_SWIER_4 -#define EXTI_SWIER_SWIER5 EXTI_SWIER_5 -#define EXTI_SWIER_SWIER6 EXTI_SWIER_6 -#define EXTI_SWIER_SWIER7 EXTI_SWIER_7 -#define EXTI_SWIER_SWIER8 EXTI_SWIER_8 -#define EXTI_SWIER_SWIER9 EXTI_SWIER_9 -#define EXTI_SWIER_SWIER10 EXTI_SWIER_10 -#define EXTI_SWIER_SWIER11 EXTI_SWIER_11 -#define EXTI_SWIER_SWIER12 EXTI_SWIER_12 -#define EXTI_SWIER_SWIER13 EXTI_SWIER_13 -#define EXTI_SWIER_SWIER14 EXTI_SWIER_14 -#define EXTI_SWIER_SWIER15 EXTI_SWIER_15 -#define EXTI_SWIER_SWIER16 EXTI_SWIER_16 - -#define EXTI_PR_PR0 EXTI_PR_0 -#define EXTI_PR_PR1 EXTI_PR_1 -#define EXTI_PR_PR2 EXTI_PR_2 -#define EXTI_PR_PR3 EXTI_PR_3 -#define EXTI_PR_PR4 EXTI_PR_4 -#define EXTI_PR_PR5 EXTI_PR_5 -#define EXTI_PR_PR6 EXTI_PR_6 -#define EXTI_PR_PR7 EXTI_PR_7 -#define EXTI_PR_PR8 EXTI_PR_8 -#define EXTI_PR_PR9 EXTI_PR_9 -#define EXTI_PR_PR10 EXTI_PR_10 -#define EXTI_PR_PR11 EXTI_PR_11 -#define EXTI_PR_PR12 EXTI_PR_12 -#define EXTI_PR_PR13 EXTI_PR_13 -#define EXTI_PR_PR14 EXTI_PR_14 -#define EXTI_PR_PR15 EXTI_PR_15 -#define EXTI_PR_PR16 EXTI_PR_16 - -#define EXTI_IMR_MR17 EXTI_IMR_17 - -#define EXTI_IMR_MR18 EXTI_IMR_18 - -#define EXTI_IMR_MR19 EXTI_IMR_19 - -#define EXTI_IMR_MR20 EXTI_IMR_20 - -#define EXTI_IMR_MR21 EXTI_IMR_21 - - -#define EXTI_IMR_MR24 EXTI_IMR_24 - -#define EXTI_EMR_MR17 EXTI_EMR_17 - -#define EXTI_EMR_MR18 EXTI_EMR_18 - -#define EXTI_EMR_MR19 EXTI_EMR_19 - -#define EXTI_EMR_MR20 EXTI_EMR_20 - -#define EXTI_EMR_MR21 EXTI_EMR_21 - - -#define EXTI_EMR_MR24 EXTI_EMR_24 - -#define EXTI_RTSR_MR17 EXTI_RTSR_17 - -#define EXTI_RTSR_MR18 EXTI_RTSR_18 - -#define EXTI_RTSR_MR19 EXTI_RTSR_19 - -#define EXTI_RTSR_MR20 EXTI_RTSR_20 - -#define EXTI_RTSR_MR21 EXTI_RTSR_21 - - -#define EXTI_RTSR_MR24 EXTI_RTSR_24 - -#define EXTI_FTSR_MR17 EXTI_FTSR_18 - -#define EXTI_FTSR_MR18 EXTI_FTSR_18 - -#define EXTI_FTSR_MR19 EXTI_FTSR_19 - -#define EXTI_FTSR_MR20 EXTI_FTSR_20 - -#define EXTI_FTSR_MR21 EXTI_FTSR_21 - - -#define EXTI_FTSR_MR24 EXTI_FTSR_24 - -#define EXTI_SWIER_MR17 EXTI_SWIER_17 - -#define EXTI_SWIER_MR18 EXTI_SWIER_18 - -#define EXTI_SWIER_MR19 EXTI_SWIER_19 - -#define EXTI_SWIER_MR20 EXTI_SWIER_20 - -#define EXTI_SWIER_MR21 EXTI_SWIER_21 - - -#define EXTI_SWIER_MR24 EXTI_SWIER_24 - -#define EXTI_PR_MR17 EXTI_PR_17 - -#define EXTI_PR_MR18 EXTI_PR_18 - -#define EXTI_PR_MR19 EXTI_PR_19 - -#define EXTI_PR_MR20 EXTI_PR_20 - -#define EXTI_PR_MR21 EXTI_PR_21 - - -#define EXTI_PR_MR24 EXTI_PR_24 - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Version compatibility definition -//////////////////////////////////////////////////////////////////////////////// - -#define GPIO_Mode_IN_FLOATING GPIO_Mode_FLOATING - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Version compatibility definition -//////////////////////////////////////////////////////////////////////////////// -//Bit -#define I2C_CON_MASTER_MODE I2C_CR_MASTER -#define I2C_CON_SPEED I2C_CR_SPEED -#define I2C_CON_SPEED_STANDARD I2C_CR_STD -#define I2C_CON_SPEED_FAST I2C_CR_FAST -#define I2C_CON_10BITADDR_SLAVE I2C_CR_SLAVE10 -#define I2C_CON_10BITADDR_MASTER I2C_CR_MASTER10 -#define I2C_CON_RESTART_EN I2C_CR_REPEN -#define I2C_CON_SLAVE_DISABLE I2C_CR_SLAVEDIS -#define I2C_CON_STOP_DET_IFADDRESSED I2C_CR_STOPINT -#define I2C_CON_EMPTY_CTRL I2C_CR_EMPINT -#define I2C_CON_STOP I2C_CR_STOP -#define I2C_CON_RESTART I2C_CR_RESTART - -#define I2C_TAR_TAR I2C_TAR_ADDR -#define I2C_TAR_GC_OR_START I2C_TAR_GC -#define I2C_SAR_SAR I2C_SAR_ADDR -#define I2C_DATA_CMD_DAT I2C_DR_DAT -#define I2C_DATA_CMD_CMD I2C_DR_CMD -#define I2C_DATA_CMD_STOP I2C_DR_STOP -#define I2C_DATA_CMD_RESTART I2C_DR_RESTART - -#define I2C_SS_SCL_HCNT I2C_SSHR_CNT -#define I2C_SS_SCL_LCNT I2C_SSLR_CNT -#define I2C_FS_SCL_HCNT I2C_FSHR_CNT -#define I2C_FS_SCL_LCNT I2C_FSLR_CNT - -#define I2C_INTR_STAT_RX_UNDER I2C_ISR_RX_UNDER -#define I2C_INTR_STAT_RX_OVER I2C_ISR_RX_OVER -#define I2C_INTR_STAT_RX_FULL I2C_ISR_RX_FULL -#define I2C_INTR_STAT_TX_OVER I2C_ISR_TX_OVER -#define I2C_INTR_STAT_TX_EMPTY I2C_ISR_TX_EMPTY -#define I2C_INTR_STAT_RX_REQ I2C_ISR_RX_REQ -#define I2C_INTR_STAT_TX_ABRT I2C_ISR_TX_ABRT -#define I2C_INTR_STAT_RX_DONE I2C_ISR_RX_DONE -#define I2C_INTR_STAT_ACTIVITY I2C_ISR_ACTIV -#define I2C_INTR_STAT_STOP_DET I2C_ISR_STOP -#define I2C_INTR_STAT_START_DET I2C_ISR_START -#define I2C_INTR_STAT_GEN_CALL I2C_ISR_GC -#define I2C_INTR_STAT_RESTART_DET I2C_ISR_RESTART -#define I2C_INTR_STAT_MST_ON_HOLD I2C_ISR_HOLD - -#define I2C_INTR_MASK_RX_UNDER I2C_IMR_RX_UNDER -#define I2C_INTR_MASK_RX_OVER I2C_IMR_RX_OVER -#define I2C_INTR_MASK_RX_FULL I2C_IMR_RX_FULL -#define I2C_INTR_MASK_TX_OVER I2C_IMR_TX_OVER -#define I2C_INTR_MASK_TX_EMPTY I2C_IMR_TX_EMPTY -#define I2C_INTR_MASK_RX_REQ I2C_IMR_RX_REQ -#define I2C_INTR_MASK_TX_ABRT I2C_IMR_TX_ABRT -#define I2C_INTR_MASK_RX_DONE I2C_IMR_RX_DONE -#define I2C_INTR_MASK_ACTIVITY I2C_IMR_ACTIV -#define I2C_INTR_MASK_STOP_DET I2C_IMR_STOP -#define I2C_INTR_MASK_START_DET I2C_IMR_START -#define I2C_INTR_MASK_GEN_CALL I2C_IMR_GC -#define I2C_INTR_MASK_RESTART_DET I2C_IMR_RESTART -#define I2C_INTR_MASK_MST_ON_HOLD I2C_IMR_HOLD - -#define I2C_RAW_INTR_MASK_RX_UNDER I2C_RAWISR_RX_UNDER -#define I2C_RAW_INTR_MASK_RX_OVER I2C_RAWISR_RX_OVER -#define I2C_RAW_INTR_MASK_RX_FULL I2C_RAWISR_RX_FULL -#define I2C_RAW_INTR_MASK_TX_OVER I2C_RAWISR_TX_OVER -#define I2C_RAW_INTR_MASK_TX_EMPTY I2C_RAWISR_TX_EMPTY -#define I2C_RAW_INTR_MASK_RX_REQ I2C_RAWISR_RX_REQ -#define I2C_RAW_INTR_MASK_TX_ABRT I2C_RAWISR_TX_ABRT -#define I2C_RAW_INTR_MASK_RX_DONE I2C_RAWISR_RX_DONE -#define I2C_RAW_INTR_MASK_ACTIVITY I2C_RAWISR_ACTIV -#define I2C_RAW_INTR_MASK_STOP_DET I2C_RAWISR_STOP -#define I2C_RAW_INTR_MASK_START_DET I2C_RAWISR_START -#define I2C_RAW_INTR_MASK_GEN_CALL I2C_RAWISR_GC -#define I2C_RAW_INTR_MASK_RESTART_DET I2C_RAWISR_RESTART -#define I2C_RAW_INTR_MASK_MST_ON_HOLD I2C_RAWISR_HOLD - -#define I2C_RX_TL I2C_RXTLR_TL -#define I2C_TX_TL I2C_TXTLR_TL - -#define I2C_CLR_INTR I2C_ICR -#define I2C_CLR_RX_UNDER I2C_RX_UNDER -#define I2C_CLR_RX_OVER I2C_RX_OVER -#define I2C_CLR_TX_OVER I2C_TX_OVER -#define I2C_RX_REQ I2C_RD_REQ -#define I2C_CLR_RX_REQ I2C_RD_REQ -#define I2C_CLR_TX_ABRT I2C_TX_ABRT -#define I2C_CLR_RX_DONE I2C_RX_DONE -#define I2C_CLR_ACTIVITY I2C_ACTIV -#define I2C_CLR_STOP_DET I2C_STOP -#define I2C_CLR_START_DET I2C_START -#define I2C_CLR_GEN_CALL I2C_GC - -#define I2C_ENABLE_ENABLE I2C_ENR_ENABLE -#define I2C_ENABLE_ABORT I2C_ENR_ABORT - -#define I2C_STATUS_ACTIVITY I2C_SR_ACTIV -#define I2C_STATUS_TFNF I2C_SR_TFNF -#define I2C_STATUS_TFE I2C_SR_TFE -#define I2C_STATUS_RFNE I2C_SR_RFNE -#define I2C_STATUS_RFF I2C_SR_RFF -#define I2C_STATUS_MST_ACTIVITY I2C_SR_MST_ACTIV -#define I2C_STATUS_SLV_ACTIVITY I2C_SR_SLV_ACTIV - -#define I2C_TXFLR I2C_TXFLR_CNT -#define I2C_RXFLR I2C_RXFLR_CNT - -#define I2C_SDA_TX_HOLD I2C_HOLD_TXCNT -#define I2C_SDA_RX_HOLD I2C_HOLD_RXCNT -#define I2C_DMA_CR_RDMAE I2C_DMA_RXEN -#define I2C_DMA_CR_TDMAE I2C_DMA_TXEN -#define I2C_SDA_SET_UP I2C_SETUP_CNT -#define I2C_ACK_GENERAL_CALL I2C_GCR_GC - - -#define IWDG_PR_PR IWDG_PR_PRE -#define IWDG_PR_PR_DIV4 IWDG_PR_PRE_DIV4 -#define IWDG_PR_PR_DIV8 IWDG_PR_PRE_DIV8 -#define IWDG_PR_PR_DIV16 IWDG_PR_PRE_DIV16 -#define IWDG_PR_PR_DIV32 IWDG_PR_PRE_DIV32 -#define IWDG_PR_PR_DIV64 IWDG_PR_PRE_DIV64 -#define IWDG_PR_PR_DIV128 IWDG_PR_PRE_DIV128 -#define IWDG_PR_PR_DIV256 IWDG_PR_PRE_DIV256 -//////////////////////////////////////////////////////////////////////////////// -/// @brief Version compatibility definition -//////////////////////////////////////////////////////////////////////////////// -#define RCC_AHBENR_DMAEN RCC_AHBENR_DMA1 -#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1 - - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup AHB_peripheral -/// @{ -#define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1 -#define RCC_AHBPeriph_SRAM RCC_AHBENR_SRAM -#define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITF -#define RCC_AHBPeriph_CRC RCC_AHBENR_CRC -#define RCC_AHBPeriph_AES RCC_AHBENR_AES -#define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOA -#define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOB -#define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOC -#define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIOD - - -#define RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOE -#define RCC_AHBPeriph_HIV RCC_AHBENR_HWDIV -#define RCC_AHBPeriph_HWDIV RCC_AHBENR_HWDIV - - - - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup APB2_peripheral -/// @{ -#define RCC_APB2Periph_ADC1 RCC_APB2ENR_ADC1 -#define RCC_APB2Periph_TIM1 RCC_APB2ENR_TIM1 -#define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1 -#define RCC_APB2Periph_UART1 RCC_APB2ENR_UART1 -#define RCC_APB2Periph_COMP RCC_APB2ENR_COMP -#define RCC_APB2Periph_DBGMCU RCC_APB2ENR_DBGMCU - -#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1 -#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1 -#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1 - -#define RCC_APB2Periph_ADC2 RCC_APB2ENR_ADC2 -#define RCC_APB2Periph_ADC3 RCC_APB2ENR_ADC3 -#define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFG -#define RCC_APB2Periph_EXTI RCC_APB2ENR_EXTI - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -/// @defgroup APB1_peripheral -/// @{ -#define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2 -#define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3 -#define RCC_APB1Periph_TIM4 RCC_APB1ENR_TIM4 -#define RCC_APB1Periph_UART3 RCC_APB1ENR_UART3 -#define RCC_APB1Periph_BKP RCC_APB1ENR_BKP -#define RCC_APB1Periph_DAC RCC_APB1ENR_DAC -#define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2 -#define RCC_APB1Periph_ALL 0x3AE64807 -#define RCC_APB1Periph_CAN1 RCC_APB1ENR_CAN -#define RCC_APB1Periph_CRS RCC_APB1ENR_CRS -#define RCC_APB1Periph_UART2 RCC_APB1ENR_UART2 -#define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1 -#define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2 -#define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDG -#define RCC_APB1Periph_PWR RCC_APB1ENR_PWR - -#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWR -#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2 -#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3 -#define RCC_APB1ENR_SYSCFG RCC_APB1ENR_EXTI - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief RTC_CR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define RTC_CRH_SECIE_Pos RTC_CR_SECIE_Pos -#define RTC_CRH_SECIE RTC_CR_SECIE ///< Second Interrupt Enable -#define RTC_CRH_ALRIE_Pos RTC_CR_ALRIE_Pos -#define RTC_CRH_ALRIE RTC_CR_ALRIE ///< Alarm Interrupt Enable -#define RTC_CRH_OWIE_Pos RTC_CR_OWIE_Pos -#define RTC_CRH_OWIE RTC_CR_OWIE ///< OverfloW Interrupt Enable - -//////////////////////////////////////////////////////////////////////////////// -/// @brief RTC_CSR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define RTC_CRL_SECF_Pos RTC_CSR_SECF_Pos -#define RTC_CRL_SECF RTC_CSR_SECF ///< Second Flag -#define RTC_CRL_ALRF_Pos RTC_CSR_ALRF_Pos -#define RTC_CRL_ALRF RTC_CSR_ALRF ///< Alarm Flag -#define RTC_CRL_OWF_Pos RTC_CSR_OWF_Pos -#define RTC_CRL_OWF RTC_CSR_OWF ///< OverfloW Flag -#define RTC_CRL_RSF_Pos RTC_CSR_RSF_Pos -#define RTC_CRL_RSF RTC_CSR_RSF ///< Registers Synchronized Flag -#define RTC_CRL_CNF_Pos RTC_CSR_CNF_Pos -#define RTC_CRL_CNF RTC_CSR_CNF ///< Configuration Flag -#define RTC_CRL_RTOFF_Pos RTC_CSR_RTOFF_Pos -#define RTC_CRL_RTOFF RTC_CSR_RTOFF ///< RTC operation OFF -#define RTC_CRL_ALPEN_Pos RTC_CSR_ALPEN_Pos -#define RTC_CRL_ALPEN RTC_CSR_ALPEN ///< RTC Alarm Loop Enable - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Version compatibility definition -//////////////////////////////////////////////////////////////////////////////// -#define SPI_TXREG_TXREG SPI_TDR_TXREG -#define SPI_RXREG_RXREG SPI_RDR_RXREG - -#define SPI_CSTAT_TXEPT SPI_SR_TXEPT -#define SPI_CSTAT_RXAVL SPI_SR_RXAVL -#define SPI_CSTAT_TXFULL SPI_SR_TXFULL -#define SPI_CSTAT_RXAVL_4BYTE SPI_SR_RXAVL_4BYTE -#define SPI_CSTAT_TXFADDR SPI_SR_TXFADDR -#define SPI_CSTAT_RXFADDR SPI_SR_RXFADDR - -#define SPI_INTSTAT_TX_INTF SPI_ISR_TX_INTF -#define SPI_INTSTAT_RX_INTF SPI_ISR_RX_INTF -#define SPI_INTSTAT_UNDERRUN_INTF SPI_ISR_UNDERRUN_INTF -#define SPI_INTSTAT_RXOERR_INTF SPI_ISR_RXOERR_INTF -#define SPI_INTSTAT_RXMATCH_INTF SPI_ISR_RXMATCH_INTF -#define SPI_INTSTAT_RXFULL_INTF SPI_ISR_RXFULL_INTF -#define SPI_INTSTAT_TXEPT_INTF SPI_ISR_TXEPT_INTF - -#define SPI_INTEN_TX_IEN SPI_IER_TX_IEN -#define SPI_INTEN_RX_IEN SPI_IER_RX_IEN -#define SPI_INTEN_UNDERRUN_IEN SPI_IER_UNDERRUN_IEN -#define SPI_INTEN_RXOERR_IEN SPI_IER_RXOERR_IEN -#define SPI_INTEN_RXMATCH_IEN SPI_IER_RXMATCH_IEN -#define SPI_INTEN_RXFULL_IEN SPI_IER_RXFULL_IEN -#define SPI_INTEN_TXEPT_IEN SPI_IER_TXEPT_IEN - -#define SPI_INTCLR_TX_ICLR SPI_ICR_TX_ICLR -#define SPI_INTCLR_RX_ICLR SPI_ICR_RX_ICLR -#define SPI_INTCLR_UNDERRUN_ICLR SPI_ICR_UNDERRUN_ICLR -#define SPI_INTCLR_RXOERR_ICLR SPI_ICR_RXOERR_ICLR -#define SPI_INTCLR_RXMATCH_ICLR SPI_ICR_RXMATCH_ICLR -#define SPI_INTCLR_RXFULL_ICLR SPI_ICR_RXFULL_ICLR -#define SPI_INTCLR_TXEPT_ICLR SPI_ICR_TXEPT_ICLR - -#define SPI_GCTL_SPIEN SPI_GCR_SPIEN -#define SPI_GCTL_INT_EN SPI_GCR_IEN -#define SPI_GCTL_MM SPI_GCR_MODE -#define SPI_GCTL_TXEN SPI_GCR_TXEN -#define SPI_GCTL_RXEN SPI_GCR_RXEN - -#define SPI_GCTL_RXTLF SPI_GCR_RXTLF -#define SPI_GCTL_RXTLF_One SPI_GCR_RXTLF_One -#define SPI_GCTL_RXTLF_Half SPI_GCR_RXTLF_Half - -#define SPI_GCTL_TXTLF_Pos SPI_GCR_TXTLF_Pos -#define SPI_GCTL_TXTLF SPI_GCR_TXTLF -#define SPI_GCTL_TXTLF_One SPI_GCR_TXTLF_One -#define SPI_GCTL_TXTLF_Half SPI_GCR_TXTLF_Half -#define SPI_GCTL_DMAEN SPI_GCR_DMAEN -#define SPI_GCTL_NSS_SEL SPI_GCR_NSS -#define SPI_GCTL_DATA_SEL SPI_GCR_DWSEL - -#define SPI_GCTL_NSSTOG SPI_GCR_NSSTOG - -#define SPI_CCTL_CPHA SPI_CCR_CPHA -#define SPI_CCTL_CPOL SPI_CCR_CPOL -#define SPI_CCTL_LSBFE SPI_CCR_LSBFE -#define SPI_CCTL_SPILEN SPI_CCR_SPILEN -#define SPI_CCTL_RXEDGE SPI_CCR_RXEDGE -#define SPI_CCTL_TXEDGE SPI_CCR_TXEDGE - -#define SPI_CCTL_CPHASEL SPI_CCR_CPHASEL - -#define SPI_CCTL_HISPD SPI_CCR_HISPD - -#define SPI_SPBRG_SPBRG SPI_BRR_DIVF - -#define SPI_RXDNR_RXDNR SPI_RDNR_RDN - -#define SPI_EXTCTL_EXTLEN SPI_ECR_EXTLEN -#define TIM_CR1_ARPE TIM_CR1_ARPEN - -#define TIM_SMCR_ECE TIM_SMCR_ECEN - -#define TIM_DIER_UIE TIM_DIER_UI -#define TIM_DIER_CC1IE TIM_DIER_CC1I -#define TIM_DIER_CC2IE TIM_DIER_CC2I -#define TIM_DIER_CC3IE TIM_DIER_CC3I -#define TIM_DIER_CC4IE TIM_DIER_CC4I -#define TIM_DIER_COMIE TIM_DIER_COMI -#define TIM_DIER_TIE TIM_DIER_TI -#define TIM_DIER_BIE TIM_DIER_BI -#define TIM_DIER_UDE TIM_DIER_UD -#define TIM_DIER_CC1DE TIM_DIER_CC1D -#define TIM_DIER_CC2DE TIM_DIER_CC2D -#define TIM_DIER_CC3DE TIM_DIER_CC3D -#define TIM_DIER_CC4DE TIM_DIER_CC4D -#define TIM_DIER_COMDE TIM_DIER_COMD -#define TIM_DIER_TDE TIM_DIER_TD - -#define TIM_DIER_UIEN TIM_DIER_UI -#define TIM_DIER_CC1IEN TIM_DIER_CC1I -#define TIM_DIER_CC2IEN TIM_DIER_CC2I -#define TIM_DIER_CC3IEN TIM_DIER_CC3I -#define TIM_DIER_CC4IEN TIM_DIER_CC4I -#define TIM_DIER_COMIEN TIM_DIER_COMI -#define TIM_DIER_TIEN TIM_DIER_TI -#define TIM_DIER_BIEN TIM_DIER_BI -#define TIM_DIER_UDEN TIM_DIER_UD -#define TIM_DIER_CC1DEN TIM_DIER_CC1D -#define TIM_DIER_CC2DEN TIM_DIER_CC2D -#define TIM_DIER_CC3DEN TIM_DIER_CC3D -#define TIM_DIER_CC4DEN TIM_DIER_CC4D -#define TIM_DIER_COMDEN TIM_DIER_COMD -#define TIM_DIER_TDEN TIM_DIER_TD - -#define TIM_DIER_CC5IE TIM_DIER_CC5I -#define TIM_DIER_CC5DE TIM_DIER_CC5D - -#define TIM_SR_UIF TIM_SR_UI -#define TIM_SR_CC1IF TIM_SR_CC1I -#define TIM_SR_CC2IF TIM_SR_CC2I -#define TIM_SR_CC3IF TIM_SR_CC3I -#define TIM_SR_CC4IF TIM_SR_CC4I -#define TIM_SR_COMIF TIM_SR_COMI -#define TIM_SR_TIF TIM_SR_TI -#define TIM_SR_BIF TIM_SR_BI -#define TIM_SR_CC1OF TIM_SR_CC1O -#define TIM_SR_CC2OF TIM_SR_CC2O -#define TIM_SR_CC3OF TIM_SR_CC3O -#define TIM_SR_CC4OF TIM_SR_CC4O - -#define TIM_SR_CC5IF TIM_SR_CC5I - -#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FEN -#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PEN -#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CEN -#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FEN -#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PEN -#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CEN - -#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FEN -#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PEN -#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CEN -#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FEN -#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PEN -#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CEN - -#define TIM_CCER_CC1E TIM_CCER_CC1EN -#define TIM_CCER_CC1NE TIM_CCER_CC1NEN -#define TIM_CCER_CC2E TIM_CCER_CC2EN -#define TIM_CCER_CC2NE TIM_CCER_CC2NEN -#define TIM_CCER_CC3E TIM_CCER_CC3EN -#define TIM_CCER_CC3NE TIM_CCER_CC3NEN -#define TIM_CCER_CC4E TIM_CCER_CC4EN - -#define TIM_CCER_CC5E TIM_CCER_CC5EN - -#define TIM_BDTR_BKE TIM_BDTR_BKEN -#define TIM_BDTR_AOE TIM_BDTR_AOEN -#define TIM_BDTR_MOE TIM_BDTR_MOEN - -#define TIM_BDTR_DOE TIM_BDTR_DOEN - -#define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FEN -#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PEN -#define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CEN -#define UART_TDR_TXREG UART_TDR_DATA -#define UART_RDR_RXREG UART_RDR_DATA - -#define UART_ISR_TX_INTF UART_ISR_TX -#define UART_ISR_RX_INTF UART_ISR_RX -#define UART_ISR_RXOERR_INTF UART_ISR_RXOERR -#define UART_ISR_RXPERR_INTF UART_ISR_RXPERR -#define UART_ISR_RXFERR_INTF UART_ISR_RXFERR -#define UART_ISR_RXBRK_INTF UART_ISR_RXBRK - -#define UART_IER_TXIEN UART_IER_TX -#define UART_IER_RXIEN UART_IER_RXI -#define UART_IER_RXOERREN UART_IER_RXOERR -#define UART_IER_RXPERREN UART_IER_RXPERR -#define UART_IER_RXFERREN UART_IER_RXFERR -#define UART_IER_RXBRKEN UART_IER_RXBRK - -#define UART_ICR_TXICLR UART_ICR_TX -#define UART_ICR_RXICLR UART_ICR_RX -#define UART_ICR_RXOERRCLR UART_ICR_RXOERR -#define UART_ICR_RXPERRCLR UART_ICR_RXPERR -#define UART_ICR_RXFERRCLR UART_ICR_RXFERR -#define UART_ICR_RXBRKCLR UART_ICR_RXBRK - -#define UART_Mode_Rx UART_GCR_RX -#define UART_Mode_Tx UART_GCR_TX -#define UART_EN UART_GCR_UART -#define UART_IT_RXBRK UART_IER_RXBRK -#define UART_IT_ERR UART_IER_RXFERR -#define UART_IT_PE UART_IER_RXPERR -#define UART_OVER_ERR UART_IER_RXOERR -#define UART_IT_RXIEN UART_IER_RX -#define UART_IT_TXIEN UART_IER_TX - -#define UART_HardwareFlowControl_None UART_HWFlowControl_None - -#define UART_BRR_DIV_MANTISSA UART_BRR_MANTISSA -#define UART_BRR_DIV_FRACTION UART_BRR_FRACTION - -#define UART_ISR_TXC_INTF UART_ISR_TXC -#define UART_ISR_TXBRK_INTF UART_ISR_TXBRK -#define UART_ISR_RXB8_INTF UART_ISR_RXB8 - -#define UART_IT_RXB8 UART_IER_RXB8 -#define UART_IT_TXBRK UART_IER_TXBRK -#define UART_IT_TXCIEN UART_IER_TXC -#define UART_ICR_TXCCLR UART_ICR_TXC -#define UART_ICR_TXBRKCLR UART_ICR_TXBRK -#define UART_ICR_RXB8CLR UART_ICR_RXB8 -#define UART_SCR_SCAEN UART_SCR_SCARB -#define UART_DMAReq_EN UART_GCR_DMA -#define UART_FLAG_TXEMPTY UART_CSR_TXEPT -#define UART_FLAG_TXFULL UART_CSR_TXFULL -#define UART_FLAG_RXAVL UART_CSR_RXAVL -#define UART_FLAG_TXEPT UART_CSR_TXC -#define WWDG_CR_T WWDG_CR_CNT - - -#if defined(ENABLEIP_USB_OTG) -//USB - -///------------------- Bit definition for SETUP0 register -------------------- - -//#define SETUP0 ((u16)0x00FF) - -///------------------- Bit definition for SETUP1 register -------------------- -//#define SETUP1 ((u16)0x00FF) - -///------------------- Bit definition for SETUP2 register -------------------- -//#define SETUP2 ((u16)0x00FF) - -///------------------- Bit definition for SETUP3 register -------------------- -//#define SETUP3 ((u16)0x00FF) - -///------------------- Bit definition for SETUP4 register -------------------- -//#define SETUP4 ((u16)0x00FF) - -///------------------- Bit definition for SETUP5 register -------------------- -//#define SETUP5 ((u16)0x00FF) - -///------------------- Bit definition for SETUP6 register -------------------- -//#define SETUP6 ((u16)0x00FF) - -///------------------- Bit definition for SETUP7 register -------------------- -//#define SETUP7 ((u16)0x00FF) - - - -#define USB_TOP_STATE_0 ((u16)0x0020) -#define USB_TOP_STATE_1 ((u16)0x0040) - -///------------------- Bit definition for EP1_INT_STATE register -------------------- -#define EP1_INT_STATE_END ((u16)0x0002) -#define EP1_INT_STATE_INNACK ((u16)0x0004) -#define EP1_INT_STATE_INACK ((u16)0x0008) -#define EP1_INT_STATE_INSTALL ((u16)0x0010) -#define EP1_INT_STATE_OUTNACK ((u16)0x0020) -#define EP1_INT_STATE_OUTACK ((u16)0x0040) -#define EP1_INT_STATE_OUTSTALL ((u16)0x0080) - -///------------------- Bit definition for EP2_INT_STATE register -------------------- -#define EP2_INT_STATE_END ((u16)0x0002) -#define EP2_INT_STATE_INNACK ((u16)0x0004) -#define EP2_INT_STATE_INACK ((u16)0x0008) -#define EP2_INT_STATE_INSTALL ((u16)0x0010) -#define EP2_INT_STATE_OUTNACK ((u16)0x0020) -#define EP2_INT_STATE_OUTACK ((u16)0x0040) -#define EP2_INT_STATE_OUTSTALL ((u16)0x0080) - -///------------------- Bit definition for EP3_INT_STATE register -------------------- -#define EP3_INT_STATE_END ((u16)0x0002) -#define EP3_INT_STATE_INNACK ((u16)0x0004) -#define EP3_INT_STATE_INACK ((u16)0x0008) -#define EP3_INT_STATE_INSTALL ((u16)0x0010) -#define EP3_INT_STATE_OUTNACK ((u16)0x0020) -#define EP3_INT_STATE_OUTACK ((u16)0x0040) -#define EP3_INT_STATE_OUTSTALL ((u16)0x0080) - -///------------------- Bit definition for EP4_INT_STATE register -------------------- -#define EP4_INT_STATE_END ((u16)0x0002) -#define EP4_INT_STATE_INNACK ((u16)0x0004) -#define EP4_INT_STATE_INACK ((u16)0x0008) -#define EP4_INT_STATE_INSTALL ((u16)0x0010) -#define EP4_INT_STATE_OUTNACK ((u16)0x0020) -#define EP4_INT_STATE_OUTACK ((u16)0x0040) -#define EP4_INT_STATE_OUTSTALL ((u16)0x0080) - - -///------------------- Bit definition for EP0_AVIL register -------------------- -#define EP0_AVIL_EPXAVIL ((u16)0x00FF) - -///------------------- Bit definition for EP1_AVIL register -------------------- -#define EP1_AVIL_EPXAVIL ((u16)0x00FF) - -///------------------- Bit definition for EP2_AVIL register -------------------- -#define EP2_AVIL_EPXAVIL ((u16)0x00FF) - -///------------------- Bit definition for EP3_AVIL register -------------------- -#define EP3_AVIL_EPXAVIL ((u16)0x00FF) - -///------------------- Bit definition for EP4_AVIL register -------------------- -#define EP4_AVIL_EPXAVIL ((u16)0x00FF) - -///------------------- Bit definition for EP0_CTRL register -------------------- -#define EP0_CTRL_TRANEN ((u16)0x0080) - -#define EP0_CTRL_TRANCOUNT ((u16)0x007F) -#define EP0_CTRL_TRANCOUNT_0 ((u16)0x0001) -#define EP0_CTRL_TRANCOUNT_1 ((u16)0x0002) -#define EP0_CTRL_TRANCOUNT_2 ((u16)0x0004) -#define EP0_CTRL_TRANCOUNT_3 ((u16)0x0008) -#define EP0_CTRL_TRANCOUNT_4 ((u16)0x0010) -#define EP0_CTRL_TRANCOUNT_5 ((u16)0x0020) -#define EP0_CTRL_TRANCOUNT_6 ((u16)0x0040) - -///------------------- Bit definition for EP1_CTRL register -------------------- -#define EP1_CTRL_TRANEN ((u16)0x0080) - -#define EP1_CTRL_TRANCOUNT ((u16)0x007F) -#define EP1_CTRL_TRANCOUNT_0 ((u16)0x0001) -#define EP1_CTRL_TRANCOUNT_1 ((u16)0x0002) -#define EP1_CTRL_TRANCOUNT_2 ((u16)0x0004) -#define EP1_CTRL_TRANCOUNT_3 ((u16)0x0008) -#define EP1_CTRL_TRANCOUNT_4 ((u16)0x0010) -#define EP1_CTRL_TRANCOUNT_5 ((u16)0x0020) -#define EP1_CTRL_TRANCOUNT_6 ((u16)0x0040) - -///------------------- Bit definition for EP2_CTRL register -------------------- -#define EP2_CTRL_TRANEN ((u16)0x0080) - -#define EP2_CTRL_TRANCOUNT ((u16)0x007F) -#define EP2_CTRL_TRANCOUNT_0 ((u16)0x0001) -#define EP2_CTRL_TRANCOUNT_1 ((u16)0x0002) -#define EP2_CTRL_TRANCOUNT_2 ((u16)0x0004) -#define EP2_CTRL_TRANCOUNT_3 ((u16)0x0008) -#define EP2_CTRL_TRANCOUNT_4 ((u16)0x0010) -#define EP2_CTRL_TRANCOUNT_5 ((u16)0x0020) -#define EP2_CTRL_TRANCOUNT_6 ((u16)0x0040) - -///------------------- Bit definition for EP3_CTRL register -------------------- -#define EP3_CTRL_TRANEN ((u16)0x0080) - -#define EP3_CTRL_TRANCOUNT ((u16)0x007F) -#define EP3_CTRL_TRANCOUNT_0 ((u16)0x0001) -#define EP3_CTRL_TRANCOUNT_1 ((u16)0x0002) -#define EP3_CTRL_TRANCOUNT_2 ((u16)0x0004) -#define EP3_CTRL_TRANCOUNT_3 ((u16)0x0008) -#define EP3_CTRL_TRANCOUNT_4 ((u16)0x0010) -#define EP3_CTRL_TRANCOUNT_5 ((u16)0x0020) -#define EP3_CTRL_TRANCOUNT_6 ((u16)0x0040) - -///------------------- Bit definition for EP4_CTRL register -------------------- -#define EP4_CTRL_TRANEN ((u16)0x0080) - -#define EP4_CTRL_TRANCOUNT ((u16)0x007F) -#define EP4_CTRL_TRANCOUNT_0 ((u16)0x0001) -#define EP4_CTRL_TRANCOUNT_1 ((u16)0x0002) -#define EP4_CTRL_TRANCOUNT_2 ((u16)0x0004) -#define EP4_CTRL_TRANCOUNT_3 ((u16)0x0008) -#define EP4_CTRL_TRANCOUNT_4 ((u16)0x0010) -#define EP4_CTRL_TRANCOUNT_5 ((u16)0x0020) -#define EP4_CTRL_TRANCOUNT_6 ((u16)0x0040) - - -#endif -#endif //__MM32_REG_DEFINE_V1_H - diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_adc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_adc.h deleted file mode 100644 index 1aab3ef16..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_adc.h +++ /dev/null @@ -1,953 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file reg_adc.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF -/// MM32 FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion - -#ifndef __REG_ADC_H -#define __REG_ADC_H - -// Files includes - -#include -#include -#include "types.h" - - - - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - - - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ADC Base Address Definition -//////////////////////////////////////////////////////////////////////////////// -#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) ///< Base Address: 0x40012400 -#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) ///< Base Address: 0x40012800 -#define ADC3_BASE (APB2PERIPH_BASE + 0x4C00) ///< Base Address: 0x40014C00 - - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Analog-to-Digital Converter register -//////////////////////////////////////////////////////////////////////////////// -#define USENCOMBINEREGISTER -#ifdef USENCOMBINEREGISTER - -typedef struct { - union { - __IO u32 DR; ///< ADC data register, offset: 0x00 - __IO u32 ADDATA; - }; - union { - __IO u32 CFGR; ///< ADC configuration register, offset: 0x04 - __IO u32 ADCFG; - }; - union { - __IO u32 CR; ///< ADC control register, offset: 0x08 - __IO u32 ADCR; - }; - union { - __IO u32 CHSR; ///< ADC channel selection register, offset: 0x0C - __IO u32 ADCHS; - }; - union { - __IO u32 CMPR; ///< ADC window compare register, offset: 0x10 - __IO u32 ADCMPR; - }; - union { - __IO u32 SR; ///< ADC status register, offset: 0x14 - __IO u32 ADSTA; - }; - union { - __IO u32 CH0DR; ///< ADC channel0 data register, offset: 0x18 - __IO u32 ADDR0; - }; - union { - __IO u32 CH1DR; ///< ADC channel1 data register, offset: 0x1C - __IO u32 ADDR1; - }; - union { - __IO u32 CH2DR; ///< ADC channel2 data register, offset: 0x20 - __IO u32 ADDR2; - }; - union { - __IO u32 CH3DR; ///< ADC channel3 data register, offset: 0x24 - __IO u32 ADDR3; - }; - union { - __IO u32 CH4DR; ///< ADC channel4 data register, offset: 0x28 - __IO u32 ADDR4; - }; - union { - __IO u32 CH5DR; ///< ADC channel5 data register, offset: 0x2C - __IO u32 ADDR5; - }; - union { - __IO u32 CH6DR; ///< ADC channel6 data register, offset: 0x30 - __IO u32 ADDR6; - }; - union { - __IO u32 CH7DR; ///< ADC channel7 data register, offset: 0x34 - __IO u32 ADDR7; - }; - union { - __IO u32 CH8DR; ///< ADC channel8 data register, offset: 0x38 - __IO u32 ADDR8; - }; - union { - __IO u32 CH9DR; ///< ADC channel9 data register, offset: 0x3C - __IO u32 ADDR9; - }; - __IO u32 ADDR10; ///< offset: 0x40 - __IO u32 ADDR11; ///< offset: 0x44 - __IO u32 ADDR12; ///< offset: 0x48 - __IO u32 ADDR13; ///< offset: 0x4C - union { - __IO u32 CH14DR; ///< ADC channel14 data register, offset: 0x50 - __IO u32 ADDR14; - }; - union { - __IO u32 CH15DR; ///< ADC channel15 data register, offset: 0x54 - __IO u32 ADDR15; - }; - __IO u32 SREXT; ///< ADC Extended Status Register, offset: 0x58 - __IO u32 CHANY0; ///< ADC any Chan Select Register 0, offset: 0x5C - __IO u32 CHANY1; ///< ADC any Chan Select Register 1, offset: 0x60 - __IO u32 ANYCFG; ///< ADC any Chan config Register, offset: 0x64 - __IO u32 ANYCR; ///< ADC any Chan control Register, offset: 0x68 - __IO u32 RESERVED0; ///< offset 0x6C - __IO u32 SMPR1; ///< Sampling configuration register 1 offset 0x70 - __IO u32 SMPR2; ///< Sampling configuration register 2 offset 0x74 - __IO u32 RESERVED1; ///< offset 0x78 - __IO u32 JOFR0; ///< Injection channel data compensation register 0 offset 0x7C - __IO u32 JOFR1; ///< Injection channel data compensation register 1 offset 0x80 - __IO u32 JOFR2; ///< Injection channel data compensation register 2 offset 0x84 - __IO u32 JOFR3; ///< Injection channel data compensation register 3 offset 0x88 - __IO u32 JSQR; ///< Injection sequence register offset 0x8C - __IO u32 JDATA; ///< Inject data register offset 0x90 - __IO u32 RESERVED2; ///< offset 0x94 - __IO u32 RESERVED3; ///< offset 0x98 - __IO u32 RESERVED4; ///< offset 0x9C - __IO u32 RESERVED5; ///< offset 0xA0 - __IO u32 RESERVED6; ///< offset 0xA4 - __IO u32 RESERVED7; ///< offset 0xA8 - __IO u32 RESERVED8; ///< offset 0xAC - __IO u32 JDR0; ///< Injection channel data register 0 offset 0xB0 - __IO u32 JDR1; ///< Injection channel data register 1 offset 0xB4 - __IO u32 JDR2; ///< Injection channel data register 2 offset 0xB8 - __IO u32 JDR3; ///< Injection channel data register 3 offset 0xBC -} ADC_TypeDef; - -#endif -#ifdef USENNEWREGISTER -//////////////////////////////////////////////////////////////////////////////// -/// @brief Analog-to-Digital Converter register -//////////////////////////////////////////////////////////////////////////////// -typedef struct { - __IO u32 DR; ///< ADC data register, offset: 0x00 - __IO u32 CFGR; ///< ADC configuration register, offset: 0x04 - __IO u32 CR; ///< ADC control register, offset: 0x08 - __IO u32 CHSR; ///< ADC channel selection register, offset: 0x0C - __IO u32 CMPR; ///< ADC window compare register, offset: 0x10 - __IO u32 SR; ///< ADC status register, offset: 0x14 - __IO u32 CH0DR; ///< ADC channel0 data register, offset: 0x18 - __IO u32 CH1DR; ///< ADC channel1 data register, offset: 0x1C - __IO u32 CH2DR; ///< ADC channel2 data register, offset: 0x20 - __IO u32 CH3DR; ///< ADC channel3 data register, offset: 0x24 - __IO u32 CH4DR; ///< ADC channel4 data register, offset: 0x28 - __IO u32 CH5DR; ///< ADC channel5 data register, offset: 0x2C - __IO u32 CH6DR; ///< ADC channel6 data register, offset: 0x30 - __IO u32 CH7DR; ///< ADC channel7 data register, offset: 0x34 - __IO u32 CH8DR; ///< ADC channel8 data register, offset: 0x38 -} ADC_TypeDef; -#endif -#ifdef USENOLDREGISTER -typedef struct { - __IO u32 ADDATA; ///< ADC data register, offset: 0x00 - __IO u32 ADCFG; ///< ADC configuration register, offset: 0x04 - __IO u32 ADCR; ///< ADC control register, offset: 0x08 - __IO u32 ADCHS; ///< ADC channel selection register, offset: 0x0C - __IO u32 ADCMPR; ///< ADC window compare register, offset: 0x10 - __IO u32 ADSTA; ///< ADC status register, offset: 0x14 - __IO u32 ADDR0; ///< ADC channel0 data register, offset: 0x18 - __IO u32 ADDR1; ///< ADC channel1 data register, offset: 0x1C - __IO u32 ADDR2; ///< ADC channel2 data register, offset: 0x20 - __IO u32 ADDR3; ///< ADC channel3 data register, offset: 0x24 - __IO u32 ADDR4; ///< ADC channel4 data register, offset: 0x28 - __IO u32 ADDR5; ///< ADC channel5 data register, offset: 0x2C - __IO u32 ADDR6; ///< ADC channel6 data register, offset: 0x30 - __IO u32 ADDR7; ///< ADC channel7 data register, offset: 0x34 - __IO u32 ADDR8; ///< ADC channel8 data register, offset: 0x38 -} ADC_TypeDef; -#endif - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ADC type pointer Definition -//////////////////////////////////////////////////////////////////////////////// -#define ADC1 ((ADC_TypeDef*) ADC1_BASE) -#define ADC2 ((ADC_TypeDef*) ADC2_BASE) -#define ADC3 ((ADC_TypeDef*) ADC3_BASE) - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ADC_DR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define ADC_DR_DATA_Pos (0) -#define ADC_DR_DATA (0xFFFFU << ADC_DR_DATA_Pos) ///< ADC 12bit convert data - -#define ADC_DR_CH_Pos (16) -#define ADC_DR_CH (0x0FU << ADC_DR_CH_Pos) ///< CHANNELSEL[19:16] (ADC current channel convert data) - -#define ADC_DR_CH0 (0x00U << ADC_DR_CH_Pos) ///< ADC Channel select 0 -#define ADC_DR_CH1 (0x01U << ADC_DR_CH_Pos) ///< ADC Channel select 1 -#define ADC_DR_CH2 (0x02U << ADC_DR_CH_Pos) ///< ADC Channel select 2 -#define ADC_DR_CH3 (0x03U << ADC_DR_CH_Pos) ///< ADC Channel select 3 -#define ADC_DR_CH4 (0x04U << ADC_DR_CH_Pos) ///< ADC Channel select 4 -#define ADC_DR_CH5 (0x05U << ADC_DR_CH_Pos) ///< ADC Channel select 5 -#define ADC_DR_CH6 (0x06U << ADC_DR_CH_Pos) ///< ADC Channel select 6 -#define ADC_DR_CH7 (0x07U << ADC_DR_CH_Pos) ///< ADC Channel select 7 - -#define ADC_DR_CH8 (0x08U << ADC_DR_CH_Pos) ///< ADC Channel select 8 - -#define ADC_DR_CH10 (0x0AU << ADC_DR_CH_Pos) ///< ADC Channel select 10 -#define ADC_DR_CH11 (0x0BU << ADC_DR_CH_Pos) ///< ADC Channel select 11 -#define ADC_DR_CH13 (0x0CU << ADC_DR_CH_Pos) ///< ADC Channel select 13 - -#define ADC_DR_CH9 (0x09U << ADC_DR_CH_Pos) ///< ADC Channel select 9 -#define ADC_DR_CH14 (0x0EU << ADC_DR_CH_Pos) ///< ADC Channel select 14 -#define ADC_DR_CH15 (0x0FU << ADC_DR_CH_Pos) ///< ADC Channel select 15 -#define ADC_DR_OVERRUN_Pos (20) -#define ADC_DR_OVERRUN (0x01U << ADC_DR_OVERRUN_Pos) ///< ADC data will be cover -#define ADC_DR_VALID_Pos (21) -#define ADC_DR_VALID (0x01U << ADC_DR_VALID_Pos) ///< ADC data[11:0] is valid - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ADC_CFGR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define ADC_CFGR_ADEN_Pos (0) -#define ADC_CFGR_ADEN (0x01U << ADC_CFGR_ADEN_Pos) ///< Enable ADC convert -#define ADC_CFGR_ADWEN_Pos (1) -#define ADC_CFGR_ADWEN (0x01U << ADC_CFGR_ADWEN_Pos) ///< Enable ADC window compare - - -#define ADC_CFGR_RSLTCTL_Pos (7) -#define ADC_CFGR_RSLTCTL (0x07U << ADC_CFGR_RSLTCTL_Pos) ///< ADC resolution select -#define ADC_CFGR_RSLTCTL_12 (0x00U << ADC_CFGR_RSLTCTL_Pos) ///< ADC resolution select 12bit -#define ADC_CFGR_RSLTCTL_11 (0x01U << ADC_CFGR_RSLTCTL_Pos) ///< ADC resolution select 11bit -#define ADC_CFGR_RSLTCTL_10 (0x02U << ADC_CFGR_RSLTCTL_Pos) ///< ADC resolution select 10bit -#define ADC_CFGR_RSLTCTL_9 (0x03U << ADC_CFGR_RSLTCTL_Pos) ///< ADC resolution select 9bit -#define ADC_CFGR_RSLTCTL_8 (0x04U << ADC_CFGR_RSLTCTL_Pos) ///< ADC resolution select 8bit - -#define ADC_CFGR_TEN_Pos (2) -#define ADC_CFGR_TEN (0x01U << ADC_CFGR_TEN_Pos) ///< Enable ADC temperature sensor -#define ADC_CFGR_VEN_Pos (3) -#define ADC_CFGR_VEN (0x01U << ADC_CFGR_VEN_Pos) ///< Enable ADC voltage reference - - - - - -#define ADC_CFGR_PRE_Pos (4) -#define ADC_CFGR_PREL_Pos (14) -#define ADC_CFGR_PRE ((0x07U << ADC_CFGR_PRE_Pos) + (0x01U << ADC_CFGR_PREL_Pos)) -#define ADC_CFGR_PRE_2 (0x00U << ADC_CFGR_PRE_Pos) ///< ADC preclk 2 -#define ADC_CFGR_PRE_4 (0x01U << ADC_CFGR_PRE_Pos) ///< ADC preclk 4 -#define ADC_CFGR_PRE_6 (0x02U << ADC_CFGR_PRE_Pos) ///< ADC preclk 6 -#define ADC_CFGR_PRE_8 (0x03U << ADC_CFGR_PRE_Pos) ///< ADC preclk 8 -#define ADC_CFGR_PRE_10 (0x04U << ADC_CFGR_PRE_Pos) ///< ADC preclk 10 -#define ADC_CFGR_PRE_12 (0x05U << ADC_CFGR_PRE_Pos) ///< ADC preclk 12 -#define ADC_CFGR_PRE_14 (0x06U << ADC_CFGR_PRE_Pos) ///< ADC preclk 14 -#define ADC_CFGR_PRE_16 (0x07U << ADC_CFGR_PRE_Pos) ///< ADC preclk 16 -#define ADC_CFGR_PRE_3 ((0x01U << ADC_CFGR_PREL_Pos) + (0x00U << ADC_CFGR_PRE_Pos)) ///< ADC preclk 3 -#define ADC_CFGR_PRE_5 ((0x01U << ADC_CFGR_PREL_Pos) + (0x01U << ADC_CFGR_PRE_Pos)) ///< ADC preclk 5 -#define ADC_CFGR_PRE_7 ((0x01U << ADC_CFGR_PREL_Pos) + (0x02U << ADC_CFGR_PRE_Pos)) ///< ADC preclk 7 -#define ADC_CFGR_PRE_9 ((0x01U << ADC_CFGR_PREL_Pos) + (0x03U << ADC_CFGR_PRE_Pos)) ///< ADC preclk 9 -#define ADC_CFGR_PRE_11 ((0x01U << ADC_CFGR_PREL_Pos) + (0x04U << ADC_CFGR_PRE_Pos)) ///< ADC preclk 11 -#define ADC_CFGR_PRE_13 ((0x01U << ADC_CFGR_PREL_Pos) + (0x05U << ADC_CFGR_PRE_Pos)) ///< ADC preclk 13 -#define ADC_CFGR_PRE_15 ((0x01U << ADC_CFGR_PREL_Pos) + (0x06U << ADC_CFGR_PRE_Pos)) ///< ADC preclk 15 -#define ADC_CFGR_PRE_17 ((0x01U << ADC_CFGR_PREL_Pos) + (0x07U << ADC_CFGR_PRE_Pos)) ///< ADC preclk 17 - -#define ADC_CFGR_JADWEN_Pos (16) -#define ADC_CFGR_JADWEN (0x01U << ADC_CFGR_JADWEN_Pos) ///< Inject ADC conversion window comparison enable - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ADC_CR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define ADC_CR_ADIE_Pos (0) -#define ADC_CR_ADIE (0x01U << ADC_CR_ADIE_Pos) ///< ADC interrupt enable -#define ADC_CR_ADWIE_Pos (1) -#define ADC_CR_ADWIE (0x01U << ADC_CR_ADWIE_Pos) ///< ADC window compare interrupt enable -#define ADC_CR_TRGEN_Pos (2) -#define ADC_CR_TRGEN (0x01U << ADC_CR_TRGEN_Pos) ///< extranal trigger single start AD convert -#define ADC_CR_DMAEN_Pos (3) -#define ADC_CR_DMAEN (0x01U << ADC_CR_DMAEN_Pos) ///< ADC DMA enable - -#define ADC_CR_ADST_Pos (8) -#define ADC_CR_ADST (0x01U << ADC_CR_ADST_Pos) ///< ADC start convert data -#define ADC_CR_MODE_Pos (9) -#define ADC_CR_MODE (0x03U << ADC_CR_MODE_Pos) ///< ADC convert mode -#define ADC_CR_IMM (0x00U << ADC_CR_MODE_Pos) ///< ADC imm convert mode -#define ADC_CR_SCAN (0x01U << ADC_CR_MODE_Pos) ///< ADC scan convert mode -#define ADC_CR_CONTINUE (0x02U << ADC_CR_MODE_Pos) ///< ADC continue scan convert mode -#define ADC_CR_ALIGN_Pos (11) -#define ADC_CR_ALIGN (0x01U << ADC_CR_ALIGN_Pos) ///< ADC data align -#define ADC_CR_LEFT (0x01U << ADC_CR_ALIGN_Pos) ///< ADC data left align -#define ADC_CR_RIGHT (0x00U << ADC_CR_ALIGN_Pos) ///< ADC data right align -#define ADC_CR_CMPCH_Pos (12) -#define ADC_CR_CMPCH (0x0FU << ADC_CR_CMPCH_Pos) ///< CMPCH[15:12] ADC window compare channel0 convert data -#define ADC_CR_CMPCH_0 (0x00U << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 0 Conversion Results -#define ADC_CR_CMPCH_1 (0x01U << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 1 Conversion Results -#define ADC_CR_CMPCH_2 (0x02U << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 2 Conversion Results -#define ADC_CR_CMPCH_4 (0x04U << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 4 Conversion Results -#define ADC_CR_CMPCH_5 (0x05U << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 5 Conversion Results -#define ADC_CR_CMPCH_6 (0x06U << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 6 Conversion Results -#define ADC_CR_CMPCH_7 (0x07U << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 7 Conversion Results -#define ADC_CR_CMPCH_8 (0x08U << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 8 Conversion Results -#define ADC_CR_CMPCH_9 (0x09U << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 9 Conversion Results -#define ADC_CR_CMPCH_10 (0x0AU << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 10 Conversion Results -#define ADC_CR_CMPCH_11 (0x0BU << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 11 Conversion Results -#define ADC_CR_CMPCH_13 (0x0DU << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 13 Conversion Results -#define ADC_CR_CMPCH_14 (0x0EU << ADC_CR_CMPCH_Pos) ///< Select Compare Channel 14 Conversion Results -#define ADC_CR_CMPCH_ALL (0x0FU << ADC_CR_CMPCH_Pos) ///< Select Compare ALL Channel Conversion Results - - - -#define ADC_CR_SCANDIR_Pos (16) -#define ADC_CR_SCANDIR (0x01U << ADC_CR_SCANDIR_Pos) ///< ADC scan direction -#define ADC_CR_TRGSEL_H_Pos (17) -#define ADC_CR_TRGSEL_L_Pos (4) -#define ADC_CR_TRGSEL ((0x03U << ADC_CR_TRGSEL_H_Pos) + (0x07U << ADC_CR_TRGSEL_L_Pos)) ///< TRGSEL[6:4][18:17] ADC external trigger source select -#define ADC_CR_T1_CC1 (0x00U << ADC_CR_TRGSEL_L_Pos) ///< The external trigger source of the ADC is T1_CC1 -#define ADC_CR_T1_CC2 (0x01U << ADC_CR_TRGSEL_L_Pos) ///< The external trigger source of the ADC is T1_CC2 -#define ADC_CR_T1_CC3 (0x02U << ADC_CR_TRGSEL_L_Pos) ///< The external trigger source of the ADC is T1_CC3 -#define ADC_CR_T2_CC2 (0x03U << ADC_CR_TRGSEL_L_Pos) ///< The external trigger source of the ADC is T2_CC2 -#define ADC_CR_T3_TRIG (0x04U << ADC_CR_TRGSEL_L_Pos) ///< The external trigger source of the ADC is T3_TRIG -#define ADC_CR_T1_CC4_CC5 (0x05U << ADC_CR_TRGSEL_L_Pos) ///< The external trigger source of the ADC is T1_CC4_CC5 -#define ADC_CR_T3_CC1 (0x06U << ADC_CR_TRGSEL_L_Pos) ///< The external trigger source of the ADC is T3_CC1 -#define ADC_CR_EXTI_11 (0x07U << ADC_CR_TRGSEL_L_Pos) ///< The external trigger source of the ADC is EXTI_11 -#define ADC_CR_T1_TRIG ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x00U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is T1_TRIG -#define ADC_CR_T8_CC4 ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x01U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is T8_CC4 -#define ADC_CR_T8_CC4_CC5 ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x02U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is T8_CC4_CC5 -#define ADC_CR_T2_CC1 ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x03U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is T2_CC1 -#define ADC_CR_T3_CC4 ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x04U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is T3_CC4 -#define ADC_CR_T2_TRIG ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x05U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is T2_TRIG -#define ADC_CR_T8_CC5 ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x06U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is T8_CC5 -#define ADC_CR_EXTI_15 ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x07U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is EXTI_15 -#define ADC_CR_TIM1_CC4 ((0x02U << ADC_CR_TRGSEL_H_Pos) + (0x00U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is TIM1_CC4 -#define ADC_CR_TIM1_CC5 ((0x02U << ADC_CR_TRGSEL_H_Pos) + (0x01U << ADC_CR_TRGSEL_L_Pos)) ///< The external trigger source of the ADC is TIM1_CC5 - -#define ADC_CR_TRGSHIFT_Pos (19) -#define ADC_CR_TRGSHIFT (0x07U << ADC_CR_TRGSHIFT_Pos) ///< External trigger shift sample -#define ADC_CR_TRGSHIFT_0 (0x00U << ADC_CR_TRGSHIFT_Pos) ///< No shift -#define ADC_CR_TRGSHIFT_4 (0x01U << ADC_CR_TRGSHIFT_Pos) ///< Shift 4 period -#define ADC_CR_TRGSHIFT_16 (0x02U << ADC_CR_TRGSHIFT_Pos) ///< Shift 16 period -#define ADC_CR_TRGSHIFT_32 (0x03U << ADC_CR_TRGSHIFT_Pos) ///< Shift 32 period -#define ADC_CR_TRGSHIFT_64 (0x04U << ADC_CR_TRGSHIFT_Pos) ///< Shift 64 period -#define ADC_CR_TRGSHIFT_128 (0x05U << ADC_CR_TRGSHIFT_Pos) ///< Shift 128 period -#define ADC_CR_TRGSHIFT_256 (0x06U << ADC_CR_TRGSHIFT_Pos) ///< Shift 256 period -#define ADC_CR_TRGSHIFT_512 (0x07U << ADC_CR_TRGSHIFT_Pos) ///< Shift 512 period -#define ADC_CR_CALIBEN_Pos (22) -#define ADC_CR_CALIBEN (0x01U << ADC_CR_CALIBEN_Pos) ///< Self-calibration enable -#define ADC_CR_CALIBSEL_Pos (23) -#define ADC_CR_CALIBSEL (0x01U << ADC_CR_CALIBSEL_Pos) ///< Self-calibration voltage selection -#define ADC_CR_TRG_EDGE_Pos (24) -#define ADC_CR_TRG_EDGE (0x03U << ADC_CR_TRG_EDGE_Pos) ///< ADC trig edge config -#define ADC_CR_TRG_EDGE_DUAL (0x00U << ADC_CR_TRG_EDGE_Pos) ///< ADC dual edge trig mode -#define ADC_CR_TRG_EDGE_DOWN (0x01U << ADC_CR_TRG_EDGE_Pos) ///< ADC down edge trig mode -#define ADC_CR_TRG_EDGE_UP (0x02U << ADC_CR_TRG_EDGE_Pos) ///< ADC up edge trig mode -#define ADC_CR_TRG_EDGE_MASK (0x03U << ADC_CR_TRG_EDGE_Pos) ///< ADC mask edge trig mode - -#define ADC_CR_EOSMPIE_Pos (26) -#define ADC_CR_EOSMPIE (0X01U << ADC_CR_EOSMPIE_Pos) ///< ADC end sampling flag interrupt enable -#define ADC_CR_EOCIE_Pos (27) -#define ADC_CR_EOCIE (0X01U << ADC_CR_EOCIE_Pos) ///< ADC end of conversion interrupt enable -//////////////////////////////////////////////////////////////////////////////// -/// @brief ADC_CHSR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define ADC_CHSR_CH0_Pos (0) -#define ADC_CHSR_CH0 (0x01U << ADC_CHSR_CH0_Pos) ///< Enable ADC channel 0 -#define ADC_CHSR_CH1_Pos (1) -#define ADC_CHSR_CH1 (0x01U << ADC_CHSR_CH1_Pos) ///< Enable ADC channel 1 -#define ADC_CHSR_CH2_Pos (2) -#define ADC_CHSR_CH2 (0x01U << ADC_CHSR_CH2_Pos) ///< Enable ADC channel 2 -#define ADC_CHSR_CH3_Pos (3) -#define ADC_CHSR_CH3 (0x01U << ADC_CHSR_CH3_Pos) ///< Enable ADC channel 3 -#define ADC_CHSR_CH4_Pos (4) -#define ADC_CHSR_CH4 (0x01U << ADC_CHSR_CH4_Pos) ///< Enable ADC channel 4 -#define ADC_CHSR_CH5_Pos (5) -#define ADC_CHSR_CH5 (0x01U << ADC_CHSR_CH5_Pos) ///< Enable ADC channel 5 -#define ADC_CHSR_CH6_Pos (6) -#define ADC_CHSR_CH6 (0x01U << ADC_CHSR_CH6_Pos) ///< Enable ADC channel 6 -#define ADC_CHSR_CH7_Pos (7) -#define ADC_CHSR_CH7 (0x01U << ADC_CHSR_CH7_Pos) ///< Enable ADC channel 7 - -#define ADC_CHSR_CH8_Pos (8) -#define ADC_CHSR_CH8 (0x01U << ADC_CHSR_CH8_Pos) ///< Enable ADC channel 8 -#define ADC_CHSR_CH9_Pos (9) -#define ADC_CHSR_CH9 (0x01U << ADC_CHSR_CH9_Pos) ///< Enable ADC channel 9 -#define ADC_CHSR_CHT_Pos (14) -#define ADC_CHSR_CHT (0x01U << ADC_CHSR_CHT_Pos) ///< Enable Temperature Sensor -#define ADC_CHSR_CHV_Pos (15) -#define ADC_CHSR_CHV (0x01U << ADC_CHSR_CHV_Pos) ///< Enable Voltage Sensor - - -#define ADC_CHSR_CH10_Pos (10) -#define ADC_CHSR_CH10 (0x01U << ADC_CHSR_CH10_Pos) ///< Enable ADC channel 10 -#define ADC_CHSR_CH11_Pos (11) -#define ADC_CHSR_CH11 (0x01U << ADC_CHSR_CH11_Pos) ///< Enable ADC channel 11 -#define ADC_CHSR_CH12_Pos (12) -#define ADC_CHSR_CH12 (0x01U << ADC_CHSR_CH12_Pos) ///< Enable ADC channel 12 -#define ADC_CHSR_CH13_Pos (13) -#define ADC_CHSR_CH13 (0x01U << ADC_CHSR_CH13_Pos) ///< Enable ADC channel 13 -//////////////////////////////////////////////////////////////////////////////// -/// @brief ADC_CMPR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define ADC_CMPR_CMPLDATA_Pos (0) -#define ADC_CMPR_CMPLDATA (0x0FFFU << ADC_CMPR_CMPLDATA_Pos) ///< ADC 12bit window compare DOWN LEVEL DATA -#define ADC_CMPR_CMPHDATA_Pos (16) -#define ADC_CMPR_CMPHDATA (0x0FFFU << ADC_CMPR_CMPHDATA_Pos) ///< ADC 12bit window compare UP LEVEL DATA - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ADC_SR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define ADC_SR_ADIF_Pos (0) -#define ADC_SR_ADIF (0x01U << ADC_SR_ADIF_Pos) ///< ADC convert complete flag -#define ADC_SR_ADWIF_Pos (1) -#define ADC_SR_ADWIF (0x01U << ADC_SR_ADWIF_Pos) ///< ADC compare flag -#define ADC_SR_BUSY_Pos (2) -#define ADC_SR_BUSY (0x01U << ADC_SR_BUSY_Pos) ///< ADC busy flag -#define ADC_SR_CH_Pos (4) -#define ADC_SR_CH (0x0FU << ADC_SR_CH_Pos) ///< CHANNEL[7:4] ADC current channel -#define ADC_SR_CH0 (0x00U << ADC_SR_CH_Pos) ///< Channel 0 is the current conversion channel -#define ADC_SR_CH1 (0x01U << ADC_SR_CH_Pos) ///< Channel 1 is the current conversion channel -#define ADC_SR_CH2 (0x02U << ADC_SR_CH_Pos) ///< Channel 2 is the current conversion channel -#define ADC_SR_CH3 (0x03U << ADC_SR_CH_Pos) ///< Channel 3 is the current conversion channel -#define ADC_SR_CH4 (0x04U << ADC_SR_CH_Pos) ///< Channel 4 is the current conversion channel -#define ADC_SR_CH5 (0x05U << ADC_SR_CH_Pos) ///< Channel 5 is the current conversion channel -#define ADC_SR_CH6 (0x06U << ADC_SR_CH_Pos) ///< Channel 6 is the current conversion channel -#define ADC_SR_CH7 (0x07U << ADC_SR_CH_Pos) ///< Channel 7 is the current conversion channel -#define ADC_SR_CH8 (0x08U << ADC_SR_CH_Pos) ///< Channel 8 is the current conversion channel -#define ADC_SR_CH9 (0x09U << ADC_SR_CH_Pos) ///< Channel 9 is the current conversion channel -#define ADC_SR_CH10 (0x0AU << ADC_SR_CH_Pos) ///< Channel 10 is the current conversion channel -#define ADC_SR_CH11 (0x0BU << ADC_SR_CH_Pos) ///< Channel 11 is the current conversion channel -#define ADC_SR_CH13 (0x0DU << ADC_SR_CH_Pos) ///< Channel 13 is the current conversion channel -#define ADC_SR_CH14 (0x0EU << ADC_SR_CH_Pos) ///< Channel 14 is the current conversion channel -#define ADC_SR_CH15 (0x0FU << ADC_SR_CH_Pos) ///< Channel 15 is the current conversion channel - - -#define ADC_SR_VALID_Pos (8) -#define ADC_SR_VALID (0x0FFFU << ADC_SR_VALID_Pos) ///< VALID[19:8] ADC channel 0..11 valid flag -#define ADC_SR_OVERRUN_Pos (20) -#define ADC_SR_OVERRUN (0x0FFFU << ADC_SR_OVERRUN_Pos) ///< OVERRUN[31:20] ADC channel 0..11 data covered flag - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ADC_CHnDR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define ADC_CHDR_DATA_Pos (0) -#define ADC_CHDR_DATA (0xFFFFU << ADC_CHDR_DATA_Pos) ///< ADC channel convert data -#define ADC_CHDR_OVERRUN_Pos (20) -#define ADC_CHDR_OVERRUN (0x01U << ADC_CHDR_OVERRUN_Pos) ///< ADC data covered flag -#define ADC_CHDR_VALID_Pos (21) -#define ADC_CHDR_VALID (0x01U << ADC_CHDR_VALID_Pos) ///< ADC data valid flag - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ADC_SREXT Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define ADC_SREXT_VALID_Pos (0) -#define ADC_SREXT_VALID (0x0FU << ADC_SREXT_VALID_Pos) ///< VALID[3:0] ADC channel 12,14..15 valid flag -#define ADC_SREXT_OVERRUN_Pos (4) -#define ADC_SREXT_OVERRUN (0x0FU << ADC_SREXT_OVERRUN_Pos) ///< OVERRUN[7:4] ADC channel 12,14..15 data covered flag - - -#define ADC_SREXT_EOSMPIF_Pos (16) -#define ADC_SREXT_EOSMPIF (0x01U << ADC_SREXT_EOSMPIF_Pos) ///< End of sampling interrupt flag -#define ADC_SREXT_EOCIF_Pos (17) -#define ADC_SREXT_EOCIF (0x01U << ADC_SREXT_EOCIF_Pos) ///< End of conversion interrupt flag -#define ADC_SREXT_JEOSMPIF_Pos (18) -#define ADC_SREXT_JEOSMPIF (0x01U << ADC_SREXT_JEOSMPIF_Pos) /// Injected channel end of sampling interrupt flag -#define ADC_SREXT_JEOCIF_Pos (19) -#define ADC_SREXT_JEOCIF (0x03U << ADC_SREXT_JEOCIF_Pos) ///< Injected channel end of conversion interrupt flag -#define ADC_SREXT_JEOSIF_Pos (20) -#define ADC_SREXT_JEOSIF (0x03U << ADC_SREXT_JEOSIF_Pos) ///< Injected channel end of sequential conversion interrupt flag -#define ADC_SREXT_JBUSY_Pos (21) -#define ADC_SREXT_JBUSY (0x01U << ADC_SREXT_JBUSY_Pos) ///< Injection mode busy/idle - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ADC_CHANY0 select Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define ADC1_CHANY0_SEL0_Pos (0) ///< CHANY_SEL0 (Bit 0) -#define ADC1_CHANY0_SEL0 (0x0FU << ADC1_CHANY0_SEL0_Pos) ///< CHANY_SEL0 (Bitfield-Mask: 0x0f) -#define ADC1_CHANY0_SEL1_Pos (4) ///< CHANY_SEL1 (Bit 4) -#define ADC1_CHANY0_SEL1 (0x0FU << ADC1_CHANY0_SEL1_Pos) ///< CHANY_SEL1 (Bitfield-Mask: 0x0f) -#define ADC1_CHANY0_SEL2_Pos (8) ///< CHANY_SEL2 (Bit 8) -#define ADC1_CHANY0_SEL2 (0x0FU << ADC1_CHANY0_SEL2_Pos) ///< CHANY_SEL2 (Bitfield-Mask: 0x0f) -#define ADC1_CHANY0_SEL3_Pos (12) ///< CHANY_SEL3 (Bit 12) -#define ADC1_CHANY0_SEL3 (0x0FU << ADC1_CHANY0_SEL3_Pos) ///< CHANY_SEL3 (Bitfield-Mask: 0x0f) -#define ADC1_CHANY0_SEL4_Pos (16) ///< CHANY_SEL4 (Bit 16) -#define ADC1_CHANY0_SEL4 (0x0FU << ADC1_CHANY0_SEL4_Pos) ///< CHANY_SEL4 (Bitfield-Mask: 0x0f) -#define ADC1_CHANY0_SEL5_Pos (20) ///< CHANY_SEL5 (Bit 20) -#define ADC1_CHANY0_SEL5 (0x0FU << ADC1_CHANY0_SEL5_Pos) ///< CHANY_SEL5 (Bitfield-Mask: 0x0f) -#define ADC1_CHANY0_SEL6_Pos (24) ///< CHANY_SEL6 (Bit 24) -#define ADC1_CHANY0_SEL6 (0x0FU << ADC1_CHANY0_SEL6_Pos) ///< CHANY_SEL6 (Bitfield-Mask: 0x0f) -#define ADC1_CHANY0_SEL7_Pos (28) ///< CHANY_SEL7 (Bit 28) -#define ADC1_CHANY0_SEL7 (0x0FU << ADC1_CHANY0_SEL7_Pos) ///< CHANY_SEL7 (Bitfield-Mask: 0x0f) - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ADC_CHANY1 select Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define ADC1_CHANY1_SEL8_Pos (0) ///< CHANY_SEL8 (Bit 0) -#define ADC1_CHANY1_SEL8 (0x0FU << ADC1_CHANY1_SEL8_Pos) ///< CHANY_SEL8 (Bitfield-Mask: 0x0f) -#define ADC1_CHANY1_SEL9_Pos (4) ///< CHANY_SEL9 (Bit 4) -#define ADC1_CHANY1_SEL9 (0x0FU << ADC1_CHANY1_SEL9_Pos) ///< CHANY_SEL9 (Bitfield-Mask: 0x0f) - -#define ADC1_CHANY1_SEL14_Pos (24) ///< CHANY_SEL14 (Bit 24) -#define ADC1_CHANY1_SEL14 (0x0FU << ADC1_CHANY1_SEL14_Pos) ///< CHANY_SEL14 (Bitfield-Mask: 0x0f) -#define ADC1_CHANY1_SEL15_Pos (28) ///< CHANY_SEL15 (Bit 28) -#define ADC1_CHANY1_SEL15 (0x0FU << ADC1_CHANY1_SEL15_Pos) ///< CHANY_SEL15 (Bitfield-Mask: 0x0f) -#define ADC1_CHANY1_SEL10_Pos (8) ///< CHANY_SEL10 (Bit 8) -#define ADC1_CHANY1_SEL10 (0x0FU << ADC1_CHANY1_SEL10_Pos) ///< CHANY_SEL10 (Bitfield-Mask: 0x0f) -#define ADC1_CHANY1_SEL11_Pos (12) ///< CHANY_SEL11 (Bit 12) -#define ADC1_CHANY1_SEL11 (0x0FU << ADC1_CHANY1_SEL11_Pos) ///< CHANY_SEL11 (Bitfield-Mask: 0x0f) -#define ADC1_CHANY1_SEL12_Pos (16) ///< CHANY_SEL12 (Bit 16) -#define ADC1_CHANY1_SEL12 (0x0FU << ADC1_CHANY1_SEL12_Pos) ///< CHANY_SEL12 (Bitfield-Mask: 0x0f) -#define ADC1_CHANY1_SEL13_Pos (20) ///< CHANY_SEL13 (Bit 20) -#define ADC1_CHANY1_SEL13 (0x0FU << ADC1_CHANY1_SEL13_Pos) ///< CHANY_SEL13 (Bitfield-Mask: 0x0f) -//////////////////////////////////////////////////////////////////////////////// -/// @brief ADC_CHANY config number Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define ADC1_CHANY_CFG_NUM_Max (16) ///< CHANY_CFG_NUM Max Value is 16 - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ADC_CHANY mode enable Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define ADC1_CHANY_CR_MDEN_Pos (0) ///< CHANY_MDEN (Bit 0) -#define ADC1_CHANY_CR_MDEN (0x01U << ADC1_CHANY_CR_MDEN_Pos) ///< CHANY_MDEN (Bitfield-Mask: 0x01) - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ADC_ANY_CR mode enable Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define ADC_ANY_CR_JTRGEDGE_Pos (16) ///< Injection mode triggers edge selection -#define ADC_ANY_CR_JTRGEDGE_R_F (0x00U << ADC_ANY_CR_JTRGEDGE_Pos) ///< Triggered along both rising and falling edges -#define ADC_ANY_CR_JTRGEDGE_F (0x01U << ADC_ANY_CR_JTRGEDGE_Pos) ///< Drop edge trigger -#define ADC_ANY_CR_JTRGEDGE_R (0x02U << ADC_ANY_CR_JTRGEDGE_Pos) ///< Rising edge trigger -#define ADC_ANY_CR_JTRGEDGE_S (0x03U << ADC_ANY_CR_JTRGEDGE_Pos) ///< Shield trigger - -#define ADC_ANY_CR_JTRGSHIFT_Pos (13) ///< Injection mode external trigger delay sampling -#define ADC_ANY_CR_JTRGSHIFT_0 (0x00U << ADC_ANY_CR_JTRGSHIFT_Pos) ///< 0 cycle -#define ADC_ANY_CR_JTRGSHIFT_4 (0x01U << ADC_ANY_CR_JTRGSHIFT_Pos) ///< 4 cycle -#define ADC_ANY_CR_JTRGSHIFT_16 (0x02U << ADC_ANY_CR_JTRGSHIFT_Pos) ///< 16 cycle -#define ADC_ANY_CR_JTRGSHIFT_32 (0x03U << ADC_ANY_CR_JTRGSHIFT_Pos) ///< 32 cycle -#define ADC_ANY_CR_JTRGSHIFT_64 (0x04U << ADC_ANY_CR_JTRGSHIFT_Pos) ///< 64 cycle -#define ADC_ANY_CR_JTRGSHIFT_128 (0x05U << ADC_ANY_CR_JTRGSHIFT_Pos) ///< 128 cycle -#define ADC_ANY_CR_JTRGSHIFT_256 (0x06U << ADC_ANY_CR_JTRGSHIFT_Pos) ///< 256 cycle -#define ADC_ANY_CR_JTRGSHIFT_512 (0x07U << ADC_ANY_CR_JTRGSHIFT_Pos) ///< 512 cycle - -#define ADC_ANY_CR_JTRGSEL_Pos (8) ///< External event select for injected group -#define ADC_ANY_CR_JTRGSEL (0x07U << ADC_ANY_CR_JTRGSEL_Pos) -#define ADC_ANY_CR_JTRGSEL_TIM1_TRGO (0x00U << ADC_ANY_CR_JTRGSEL_Pos) ///< TIM1 TRGO -#define ADC_ANY_CR_JTRGSEL_TIM1_CC4 (0x01U << ADC_ANY_CR_JTRGSEL_Pos) ///< TIM1 CC4 -#define ADC_ANY_CR_JTRGSEL_TIM1_CC4_CC5 (0x02U << ADC_ANY_CR_JTRGSEL_Pos) ///< TIM1 CC4 and CC5 -#define ADC_ANY_CR_JTRGSEL_TIM2_TIM4CC1 (0x03U << ADC_ANY_CR_JTRGSEL_Pos) ///< TIM2 CC1 and TIM4 CC1 -#define ADC_ANY_CR_JTRGSEL_TIM3_TIM5CC4 (0x04U << ADC_ANY_CR_JTRGSEL_Pos) ///< TIM3 CC4 and TIM5 CC4 -#define ADC_ANY_CR_JTRGSEL_TIM8_CC4 (0x05U << ADC_ANY_CR_JTRGSEL_Pos) ///< TIM8 CC4 -#define ADC_ANY_CR_JTRGSEL_TIM8_CC4_CC5 (0x06U << ADC_ANY_CR_JTRGSEL_Pos) ///< TIM8 CC4 and CC5 -#define ADC_ANY_CR_JTRGSEL_EXTI12 (0x07U << ADC_ANY_CR_JTRGSEL_Pos) ///< EXTI12 - -#define ADC_ANY_CR_JTRGEN_Pos (7) -#define ADC_ANY_CR_JTRGEN (0x01U << ADC_ANY_CR_JTRGEN_Pos) ///< External trigger conversion mode for injected channels -#define ADC_ANY_CR_JADST_Pos (6) -#define ADC_ANY_CR_JADST (0x01U << ADC_ANY_CR_JADST_Pos) ///< Start conversion of injected channels -#define ADC_ANY_CR_JAUTO_Pos (5) -#define ADC_ANY_CR_JAUTO (0x01U << ADC_ANY_CR_JAUTO_Pos) ///
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-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion - -#ifndef __REG_BKP_H -#define __REG_BKP_H - -// Files includes - -#include -#include -#include "types.h" - - - - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - - - - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief BKP Base Address Definition -//////////////////////////////////////////////////////////////////////////////// - - -#define BKP_BASE (APB1PERIPH_BASE + 0x2840) ///< Base Address: 0x40002840 - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief BKP Register Structure Definition -//////////////////////////////////////////////////////////////////////////////// - - - -#define BKP_NUMBER 20 - -typedef struct { - __IO u32 RTCCR; ///< RTC clock calibration register, offset: 0x00 - __IO u32 CR; ///< BKP control register, offset: 0x04 - __IO u32 CSR; ///< BKP control/status register, offset: 0x08 - __IO u32 RESERVED0; ///< Reserved, offset: 0x0C - __IO u32 DR1; ///< BKP data register 1, offset: 0x10 - __IO u32 DR2; ///< BKP data register 2, offset: 0x14 - __IO u32 DR3; ///< BKP data register 3, offset: 0x18 - __IO u32 DR4; ///< BKP data register 4, offset: 0x1C - __IO u32 DR5; ///< BKP data register 5, offset: 0x20 - __IO u32 DR6; ///< BKP data register 6, offset: 0x24 - __IO u32 DR7; ///< BKP data register 7, offset: 0x28 - __IO u32 DR8; ///< BKP data register 8, offset: 0x2C - __IO u32 DR9; ///< BKP data register 9, offset: 0x30 - __IO u32 DR10; ///< BKP data register 10 offset: 0x34 - __IO u32 DR11; ///< BKP data register 11, offset: 0x38 - __IO u32 DR12; ///< BKP data register 12, offset: 0x3C - __IO u32 DR13; ///< BKP data register 13, offset: 0x40 - __IO u32 DR14; ///< BKP data register 14, offset: 0x44 - __IO u32 DR15; ///< BKP data register 15, offset: 0x48 - __IO u32 DR16; ///< BKP data register 16, offset: 0x4C - __IO u32 DR17; ///< BKP data register 17, offset: 0x50 - __IO u32 DR18; ///< BKP data register 18, offset: 0x54 - __IO u32 DR19; ///< BKP data register 19, offset: 0x58 - __IO u32 DR20; ///< BKP data register 20, offset: 0x5C -} BKP_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief BKP type pointer Definition -//////////////////////////////////////////////////////////////////////////////// -#define BKP ((BKP_TypeDef*) BKP_BASE) - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief BKP_DRn Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define BKP_DR_DATA_Pos (0) -#define BKP_DR_DATA (0xFFFFU << BKP_DR_DATA) ///< Backup data - -//////////////////////////////////////////////////////////////////////////////// -/// @brief BKP_RTCCR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define BKP_RTCCR_CAL_Pos (0) -#define BKP_RTCCR_CAL (0x7FU << BKP_RTCCR_CAL_Pos) ///< Calibration value -#define BKP_RTCCR_CCO_Pos (7) -#define BKP_RTCCR_CCO (0x01U << BKP_RTCCR_CCO_Pos) ///< Calibration Clock Output -#define BKP_RTCCR_ASOE_Pos (8) -#define BKP_RTCCR_ASOE (0x01U << BKP_RTCCR_ASOE_Pos) ///< Alarm or Second Output Enable -#define BKP_RTCCR_ASOS_Pos (9) -#define BKP_RTCCR_ASOS (0x01U << BKP_RTCCR_ASOS_Pos) ///< Alarm or Second Output Selection - -//////////////////////////////////////////////////////////////////////////////// -/// @brief BKP_CR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define BKP_CR_TPE_Pos (0) -#define BKP_CR_TPE (0x01U << BKP_CR_TPE_Pos) ///< TAMPER pin enable -#define BKP_CR_TPAL_Pos (1) -#define BKP_CR_TPAL (0x01U << BKP_CR_TPAL_Pos) ///< TAMPER pin active level - -//////////////////////////////////////////////////////////////////////////////// -/// @brief BKP_CSR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define BKP_CSR_CTE_Pos (0) -#define BKP_CSR_CTE (0x01U << BKP_CSR_CTE_Pos) ///< Clear Tamper event -#define BKP_CSR_CTI_Pos (1) -#define BKP_CSR_CTI (0x01U << BKP_CSR_CTI_Pos) ///< Clear Tamper Interrupt -#define BKP_CSR_TPIE_Pos (2) -#define BKP_CSR_TPIE (0x01U << BKP_CSR_TPIE_Pos) ///< TAMPER Pin interrupt enable -#define BKP_CSR_TEF_Pos (8) -#define BKP_CSR_TEF (0x01U << BKP_CSR_TEF_Pos) ///< Tamper Event Flag -#define BKP_CSR_TIF_Pos (9) -#define BKP_CSR_TIF (0x01U << BKP_CSR_TIF_Pos) ///< Tamper Interrupt Flag - - - - - -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -#endif -//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_can.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_can.h deleted file mode 100644 index 5f66bb681..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_can.h +++ /dev/null @@ -1,532 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file reg_can.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF -/// MM32 FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

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-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion - -#ifndef __REG_CAN_H -#define __REG_CAN_H - -// Files includes - -#include -#include -#include "types.h" - - - - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - - - - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief CAN Base Address Definition -//////////////////////////////////////////////////////////////////////////////// -#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) ///< Base Address: 0x40006400 - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief CAN Register Structure Definition -//////////////////////////////////////////////////////////////////////////////// - -//////////////////////////////////////////////////////////////////////////////// -/// @brief CAN basic -//////////////////////////////////////////////////////////////////////////////// -typedef struct { - __IO u32 CR; ///< Control register, offset: 0x00 - __IO u32 CMR; ///< Command register, offset: 0x04 - __IO u32 SR; ///<
© COPYRIGHT MINDMOTION
-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion - -#ifndef __REG_COMMON_H -#define __REG_COMMON_H - -// Files includes -#include -#include -#include "types.h" - - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - -#ifndef HSE_STARTUP_TIMEOUT -#define HSE_STARTUP_TIMEOUT (0x0500U) ///< Time out for HSE start up. -#endif -#ifdef CUSTOM_HSE_VAL -#ifndef HSE_VALUE -#define HSE_VALUE (12000000U) ///< Value of the External oscillator in Hz. -#endif -#else -#ifndef HSE_VALUE -#define HSE_VALUE (8000000U) ///< Value of the External oscillator in Hz. -#endif -#endif - - - -#define HSI_VALUE_PLL_ON (8000000U) ///< Value of the Internal oscillator in Hz. -#define HSI_DIV6 (8000000U) ///< Value of the Internal oscillator in Hz. -// Value of the Internal oscillator in Hz. - - -#define LSI_VALUE (40000U) ///< Value of the Internal oscillator in Hz. - - - - - -#ifndef HSI_VALUE - -#define HSI_VALUE (8000000U) ///< Value of the Internal oscillator in Hz. - -#endif - - - - - - - - -#define __MPU_PRESENT (0) ///< Cortex-M3 does not provide a MPU present or not -#ifndef __NVIC_PRIO_BITS -#define __NVIC_PRIO_BITS (4) ///< Cortex-M3 uses 4 Bits for the Priority Levels -//#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" -#endif - -#define __Vendor_SysTickConfig (0) ///< Set to 1 if different SysTick Config is used - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief MM32 MCU Interrupt Handle -//////////////////////////////////////////////////////////////////////////////// -typedef enum IRQn { - NonMaskableInt_IRQn = -14, ///< 2 Non Maskable Interrupt - MemoryManagement_IRQn = -12, ///< 4 Cortex-M3 Memory Management Interrupt - BusFault_IRQn = -11, ///< 5 Cortex-M3 Bus Fault Interrupt - UsageFault_IRQn = -10, ///< 6 Cortex-M3 Usage Fault Interrupt - SVCall_IRQn = -5, ///< 11 Cortex-M3 SV Call Interrupt - DebugMonitor_IRQn = -4, ///< 12 Cortex-M3 Debug Monitor Interrupt - PendSV_IRQn = -2, ///< 14 Cortex-M3 Pend SV Interrupt - SysTick_IRQn = -1, ///< 15 Cortex-M3 System Tick Interrupt - - WWDG_IWDG_IRQn = 0, ///< Watchdog interrupt - WWDG_IRQn = 0, ///< Watchdog interrupt - PVD_IRQn = 1, ///< (PVD) Interrupt - TAMPER_IRQn = 2, ///< Intrusion detection interrupted - RTC_IRQn = 3, ///< Real-time clock (RTC) global interrupt - FLASH_IRQn = 4, ///< Flash global interrupt - RCC_CRS_IRQn = 5, ///< RCC and CRS global interrupt - EXTI0_IRQn = 6, ///< EXTI line 0 interrupt - EXTI1_IRQn = 7, ///< EXTI line 1 interrupt - EXTI2_IRQn = 8, ///< EXTI line 2 interrupt - EXTI3_IRQn = 9, ///< EXTI line 3 interrupted - EXTI4_IRQn = 10, ///< EXTI line 4 interrupt - DMA1_Channel1_IRQn = 11, ///< DMA1 channel 1 global interrupt - DMA1_Channel2_IRQn = 12, ///< DMA1 channel 2 global interrupt - DMA1_Channel3_IRQn = 13, ///< DMA1 channel 3 global interrupt - DMA1_Channel4_IRQn = 14, ///< DMA1 channel 4 global interrupt - DMA1_Channel5_IRQn = 15, ///< DMA1 channel 5 global interrupt - DMA1_Channel6_IRQn = 16, ///< DMA1 channel 6 global interrupt - DMA1_Channel7_IRQn = 17, ///< DMA1 channel 7 global interrupt - ADC1_IRQn = 18, ///< ADC1 global interrupt - ADC1_2_IRQn = 18, ///< ADC1&ADC2 global interrupt - ADC2_IRQn = 18, ///< ADC2 global interrupt - FlashCache_IRQn = 19, ///< FlashCache outage - CAN1_RX_IRQn = 21, ///< CAN1 receive interrupt - CAN_IRQn = 21, ///< CAN interrupt - EXTI9_5_IRQn = 23, ///< EXTI line [9: 5] interrupted - TIM1_BRK_IRQn = 24, ///< TIM1 disconnect interrupt - TIM1_UP_IRQn = 25, ///< TIM1 update interrupt - IM1_TRG_COM_IRQn = 26, ///< TIM1 trigger and communication interrupt - TIM1_CC_IRQn = 27, ///< TIM1 capture compare interrupt - TIM2_IRQn = 28, ///< TIM2 global interrupt - TIM3_IRQn = 29, ///< TIM3 global interrupt - TIM4_IRQn = 30, ///< TIM4 global interrupt - I2C1_IRQn = 31, ///< I2C1 global interrupt - I2C2_IRQn = 33, ///< I2C2 global interrupt - SPI1_IRQn = 35, ///< SPI1 global interrupt - SPI2_IRQn = 36, ///< SPI2 global interrupt - UART1_IRQn = 37, ///< UART1 global interrupt - UART2_IRQn = 38, ///< UART2 global interrupt - UART3_IRQn = 39, ///< UART3 global interrupt - EXTI15_10_IRQn = 40, ///< EXTI line [15: 10] interrupted - RTCAlarm_IRQn = 41, ///< RTC alarm connected to EXTI interrupted - USB_WKUP_IRQn = 42, ///< Wake-up interrupt from USB connected to EXTI - TIM8_BRK_IRQn = 43, ///< TIM8 brake interruption - TIM8_UP_IRQn = 44, ///< TIM8 update interrupt - TIM8_TRG_COM_IRQn = 45, ///< TIM8 trigger, communication interrupt - TIM8_CC_IRQn = 46, ///< TIM8 capture compare interrupt - ADC3_IRQn = 47, ///< ADC3 global interrupt - SDIO_IRQn = 49, ///< SDIO global interrupt - TIM5_IRQn = 50, ///< TIM5 global interrupt - SPI3_IRQn = 51, ///< SPI3 global interrupt - UART4_IRQn = 52, ///< UART4 global interrupt - UART5_IRQn = 53, ///< UART5 global interrupt - TIM6_IRQn = 54, ///< TIM6 global interrupt - TIM7_IRQn = 55, ///< TIM7 global interrupt - DMA2_Channel1_IRQn = 56, ///< DMA2 channel 1 global interrupt - DMA2_Channel2_IRQn = 57, ///< DMA2 channel 2 global interrupt - DMA2_Channel3_IRQn = 58, ///< DMA2 channel 3 global interrupt - DMA2_Channel4_IRQn = 59, ///< DMA2 channel 4 global interrupt - DMA2_Channel5_IRQn = 60, ///< DMA2 channel 5 global interrupt - ETHERNET_MAC_IRQn = 61, ///< ETHERNET global interrupt - COMP1_2_IRQn = 64, ///< Comparator 1/2 interrupt connected to EXTI - USB_FS_IRQn = 67, ///< USB FS global interrupt - UART6_IRQn = 71, ///< UART6 global interrupt - UART7_IRQn = 82, ///< UART7 global interrupt - UART8_IRQn = 83, ///< UART8 global interrupt -} IRQn_Type; - - - - -#include - - - -#define PERIPH_BASE (0x40000000U) ///< Peripheral base address in the alias region - -#define EEPROM_BASE (0x08100000U) ///< EEPROM base address in the alias region - - -#define SRAM_BITBAND_BASE (0x22000000U) ///< Peripheral base address in the bit-band region -#define PERIPH_BITBAND_BASE (0x42000000U) ///< SRAM base address in the bit-band region - -#define APB1PERIPH_BASE (PERIPH_BASE + 0x00000000) -#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) -#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000) -#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000) -#define AHB3PERIPH_BASE (PERIPH_BASE + 0x20000000) - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief UID type pointer Definition -//////////////////////////////////////////////////////////////////////////////// -#define UID_BASE (0x1FFFF7E0U) ///< Unique device ID register base address - - - - - - - - -/////////////////////////////////////////////////////////////////////////////// -/// @brief Nested Vectored Interrupt Controller -/////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -/// @brief NVIC_ISER Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define NVIC_ISER_SETENA (0xFFFFFFFFU) ///< Interrupt set enable bits -#define NVIC_ISER_SETENA_0 (0x00000001U) ///< bit 0 -#define NVIC_ISER_SETENA_1 (0x00000002U) ///< bit 1 -#define NVIC_ISER_SETENA_2 (0x00000004U) ///< bit 2 -#define NVIC_ISER_SETENA_3 (0x00000008U) ///< bit 3 -#define NVIC_ISER_SETENA_4 (0x00000010U) ///< bit 4 -#define NVIC_ISER_SETENA_5 (0x00000020U) ///< bit 5 -#define NVIC_ISER_SETENA_6 (0x00000040U) ///< bit 6 -#define NVIC_ISER_SETENA_7 (0x00000080U) ///< bit 7 -#define NVIC_ISER_SETENA_8 (0x00000100U) ///< bit 8 -#define NVIC_ISER_SETENA_9 (0x00000200U) ///< bit 9 -#define NVIC_ISER_SETENA_10 (0x00000400U) ///< bit 10 -#define NVIC_ISER_SETENA_11 (0x00000800U) ///< bit 11 -#define NVIC_ISER_SETENA_12 (0x00001000U) ///< bit 12 -#define NVIC_ISER_SETENA_13 (0x00002000U) ///< bit 13 -#define NVIC_ISER_SETENA_14 (0x00004000U) ///< bit 14 -#define NVIC_ISER_SETENA_15 (0x00008000U) ///< bit 15 -#define NVIC_ISER_SETENA_16 (0x00010000U) ///< bit 16 -#define NVIC_ISER_SETENA_17 (0x00020000U) ///< bit 17 -#define NVIC_ISER_SETENA_18 (0x00040000U) ///< bit 18 -#define NVIC_ISER_SETENA_19 (0x00080000U) ///< bit 19 -#define NVIC_ISER_SETENA_20 (0x00100000U) ///< bit 20 -#define NVIC_ISER_SETENA_21 (0x00200000U) ///< bit 21 -#define NVIC_ISER_SETENA_22 (0x00400000U) ///< bit 22 -#define NVIC_ISER_SETENA_23 (0x00800000U) ///< bit 23 -#define NVIC_ISER_SETENA_24 (0x01000000U) ///< bit 24 -#define NVIC_ISER_SETENA_25 (0x02000000U) ///< bit 25 -#define NVIC_ISER_SETENA_26 (0x04000000U) ///< bit 26 -#define NVIC_ISER_SETENA_27 (0x08000000U) ///< bit 27 -#define NVIC_ISER_SETENA_28 (0x10000000U) ///< bit 28 -#define NVIC_ISER_SETENA_29 (0x20000000U) ///< bit 29 -#define NVIC_ISER_SETENA_30 (0x40000000U) ///< bit 30 -#define NVIC_ISER_SETENA_31 (0x80000000U) ///< bit 31 - -//////////////////////////////////////////////////////////////////////////////// -/// @brief NVIC_ICER Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define NVIC_ICER_CLRENA (0xFFFFFFFFU) ///< Interrupt clear-enable bits -#define NVIC_ICER_CLRENA_0 (0x00000001U) ///< bit 0 -#define NVIC_ICER_CLRENA_1 (0x00000002U) ///< bit 1 -#define NVIC_ICER_CLRENA_2 (0x00000004U) ///< bit 2 -#define NVIC_ICER_CLRENA_3 (0x00000008U) ///< bit 3 -#define NVIC_ICER_CLRENA_4 (0x00000010U) ///< bit 4 -#define NVIC_ICER_CLRENA_5 (0x00000020U) ///< bit 5 -#define NVIC_ICER_CLRENA_6 (0x00000040U) ///< bit 6 -#define NVIC_ICER_CLRENA_7 (0x00000080U) ///< bit 7 -#define NVIC_ICER_CLRENA_8 (0x00000100U) ///< bit 8 -#define NVIC_ICER_CLRENA_9 (0x00000200U) ///< bit 9 -#define NVIC_ICER_CLRENA_10 (0x00000400U) ///< bit 10 -#define NVIC_ICER_CLRENA_11 (0x00000800U) ///< bit 11 -#define NVIC_ICER_CLRENA_12 (0x00001000U) ///< bit 12 -#define NVIC_ICER_CLRENA_13 (0x00002000U) ///< bit 13 -#define NVIC_ICER_CLRENA_14 (0x00004000U) ///< bit 14 -#define NVIC_ICER_CLRENA_15 (0x00008000U) ///< bit 15 -#define NVIC_ICER_CLRENA_16 (0x00010000U) ///< bit 16 -#define NVIC_ICER_CLRENA_17 (0x00020000U) ///< bit 17 -#define NVIC_ICER_CLRENA_18 (0x00040000U) ///< bit 18 -#define NVIC_ICER_CLRENA_19 (0x00080000U) ///< bit 19 -#define NVIC_ICER_CLRENA_20 (0x00100000U) ///< bit 20 -#define NVIC_ICER_CLRENA_21 (0x00200000U) ///< bit 21 -#define NVIC_ICER_CLRENA_22 (0x00400000U) ///< bit 22 -#define NVIC_ICER_CLRENA_23 (0x00800000U) ///< bit 23 -#define NVIC_ICER_CLRENA_24 (0x01000000U) ///< bit 24 -#define NVIC_ICER_CLRENA_25 (0x02000000U) ///< bit 25 -#define NVIC_ICER_CLRENA_26 (0x04000000U) ///< bit 26 -#define NVIC_ICER_CLRENA_27 (0x08000000U) ///< bit 27 -#define NVIC_ICER_CLRENA_28 (0x10000000U) ///< bit 28 -#define NVIC_ICER_CLRENA_29 (0x20000000U) ///< bit 29 -#define NVIC_ICER_CLRENA_30 (0x40000000U) ///< bit 30 -#define NVIC_ICER_CLRENA_31 (0x80000000U) ///< bit 31 - -//////////////////////////////////////////////////////////////////////////////// -/// @brief NVIC_ISPR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define NVIC_ISPR_SETPEND (0xFFFFFFFFU) ///< Interrupt set-pending bits -#define NVIC_ISPR_SETPEND_0 (0x00000001U) ///< bit 0 -#define NVIC_ISPR_SETPEND_1 (0x00000002U) ///< bit 1 -#define NVIC_ISPR_SETPEND_2 (0x00000004U) ///< bit 2 -#define NVIC_ISPR_SETPEND_3 (0x00000008U) ///< bit 3 -#define NVIC_ISPR_SETPEND_4 (0x00000010U) ///< bit 4 -#define NVIC_ISPR_SETPEND_5 (0x00000020U) ///< bit 5 -#define NVIC_ISPR_SETPEND_6 (0x00000040U) ///< bit 6 -#define NVIC_ISPR_SETPEND_7 (0x00000080U) ///< bit 7 -#define NVIC_ISPR_SETPEND_8 (0x00000100U) ///< bit 8 -#define NVIC_ISPR_SETPEND_9 (0x00000200U) ///< bit 9 -#define NVIC_ISPR_SETPEND_10 (0x00000400U) ///< bit 10 -#define NVIC_ISPR_SETPEND_11 (0x00000800U) ///< bit 11 -#define NVIC_ISPR_SETPEND_12 (0x00001000U) ///< bit 12 -#define NVIC_ISPR_SETPEND_13 (0x00002000U) ///< bit 13 -#define NVIC_ISPR_SETPEND_14 (0x00004000U) ///< bit 14 -#define NVIC_ISPR_SETPEND_15 (0x00008000U) ///< bit 15 -#define NVIC_ISPR_SETPEND_16 (0x00010000U) ///< bit 16 -#define NVIC_ISPR_SETPEND_17 (0x00020000U) ///< bit 17 -#define NVIC_ISPR_SETPEND_18 (0x00040000U) ///< bit 18 -#define NVIC_ISPR_SETPEND_19 (0x00080000U) ///< bit 19 -#define NVIC_ISPR_SETPEND_20 (0x00100000U) ///< bit 20 -#define NVIC_ISPR_SETPEND_21 (0x00200000U) ///< bit 21 -#define NVIC_ISPR_SETPEND_22 (0x00400000U) ///< bit 22 -#define NVIC_ISPR_SETPEND_23 (0x00800000U) ///< bit 23 -#define NVIC_ISPR_SETPEND_24 (0x01000000U) ///< bit 24 -#define NVIC_ISPR_SETPEND_25 (0x02000000U) ///< bit 25 -#define NVIC_ISPR_SETPEND_26 (0x04000000U) ///< bit 26 -#define NVIC_ISPR_SETPEND_27 (0x08000000U) ///< bit 27 -#define NVIC_ISPR_SETPEND_28 (0x10000000U) ///< bit 28 -#define NVIC_ISPR_SETPEND_29 (0x20000000U) ///< bit 29 -#define NVIC_ISPR_SETPEND_30 (0x40000000U) ///< bit 30 -#define NVIC_ISPR_SETPEND_31 (0x80000000U) ///< bit 31 - -//////////////////////////////////////////////////////////////////////////////// -/// @brief NVIC_ICPR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define NVIC_ICPR_CLRPEND (0xFFFFFFFFU) ///< Interrupt clear-pending bits -#define NVIC_ICPR_CLRPEND_0 (0x00000001U) ///< bit 0 -#define NVIC_ICPR_CLRPEND_1 (0x00000002U) ///< bit 1 -#define NVIC_ICPR_CLRPEND_2 (0x00000004U) ///< bit 2 -#define NVIC_ICPR_CLRPEND_3 (0x00000008U) ///< bit 3 -#define NVIC_ICPR_CLRPEND_4 (0x00000010U) ///< bit 4 -#define NVIC_ICPR_CLRPEND_5 (0x00000020U) ///< bit 5 -#define NVIC_ICPR_CLRPEND_6 (0x00000040U) ///< bit 6 -#define NVIC_ICPR_CLRPEND_7 (0x00000080U) ///< bit 7 -#define NVIC_ICPR_CLRPEND_8 (0x00000100U) ///< bit 8 -#define NVIC_ICPR_CLRPEND_9 (0x00000200U) ///< bit 9 -#define NVIC_ICPR_CLRPEND_10 (0x00000400U) ///< bit 10 -#define NVIC_ICPR_CLRPEND_11 (0x00000800U) ///< bit 11 -#define NVIC_ICPR_CLRPEND_12 (0x00001000U) ///< bit 12 -#define NVIC_ICPR_CLRPEND_13 (0x00002000U) ///< bit 13 -#define NVIC_ICPR_CLRPEND_14 (0x00004000U) ///< bit 14 -#define NVIC_ICPR_CLRPEND_15 (0x00008000U) ///< bit 15 -#define NVIC_ICPR_CLRPEND_16 (0x00010000U) ///< bit 16 -#define NVIC_ICPR_CLRPEND_17 (0x00020000U) ///< bit 17 -#define NVIC_ICPR_CLRPEND_18 (0x00040000U) ///< bit 18 -#define NVIC_ICPR_CLRPEND_19 (0x00080000U) ///< bit 19 -#define NVIC_ICPR_CLRPEND_20 (0x00100000U) ///< bit 20 -#define NVIC_ICPR_CLRPEND_21 (0x00200000U) ///< bit 21 -#define NVIC_ICPR_CLRPEND_22 (0x00400000U) ///< bit 22 -#define NVIC_ICPR_CLRPEND_23 (0x00800000U) ///< bit 23 -#define NVIC_ICPR_CLRPEND_24 (0x01000000U) ///< bit 24 -#define NVIC_ICPR_CLRPEND_25 (0x02000000U) ///< bit 25 -#define NVIC_ICPR_CLRPEND_26 (0x04000000U) ///< bit 26 -#define NVIC_ICPR_CLRPEND_27 (0x08000000U) ///< bit 27 -#define NVIC_ICPR_CLRPEND_28 (0x10000000U) ///< bit 28 -#define NVIC_ICPR_CLRPEND_29 (0x20000000U) ///< bit 29 -#define NVIC_ICPR_CLRPEND_30 (0x40000000U) ///< bit 30 -#define NVIC_ICPR_CLRPEND_31 (0x80000000U) ///< bit 31 - -//////////////////////////////////////////////////////////////////////////////// -/// @brief NVIC_IABR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define NVIC_IABR_ACTIVE (0xFFFFFFFFU) ///< Interrupt active flags -#define NVIC_IABR_ACTIVE_0 (0x00000001U) ///< bit 0 -#define NVIC_IABR_ACTIVE_1 (0x00000002U) ///< bit 1 -#define NVIC_IABR_ACTIVE_2 (0x00000004U) ///< bit 2 -#define NVIC_IABR_ACTIVE_3 (0x00000008U) ///< bit 3 -#define NVIC_IABR_ACTIVE_4 (0x00000010U) ///< bit 4 -#define NVIC_IABR_ACTIVE_5 (0x00000020U) ///< bit 5 -#define NVIC_IABR_ACTIVE_6 (0x00000040U) ///< bit 6 -#define NVIC_IABR_ACTIVE_7 (0x00000080U) ///< bit 7 -#define NVIC_IABR_ACTIVE_8 (0x00000100U) ///< bit 8 -#define NVIC_IABR_ACTIVE_9 (0x00000200U) ///< bit 9 -#define NVIC_IABR_ACTIVE_10 (0x00000400U) ///< bit 10 -#define NVIC_IABR_ACTIVE_11 (0x00000800U) ///< bit 11 -#define NVIC_IABR_ACTIVE_12 (0x00001000U) ///< bit 12 -#define NVIC_IABR_ACTIVE_13 (0x00002000U) ///< bit 13 -#define NVIC_IABR_ACTIVE_14 (0x00004000U) ///< bit 14 -#define NVIC_IABR_ACTIVE_15 (0x00008000U) ///< bit 15 -#define NVIC_IABR_ACTIVE_16 (0x00010000U) ///< bit 16 -#define NVIC_IABR_ACTIVE_17 (0x00020000U) ///< bit 17 -#define NVIC_IABR_ACTIVE_18 (0x00040000U) ///< bit 18 -#define NVIC_IABR_ACTIVE_19 (0x00080000U) ///< bit 19 -#define NVIC_IABR_ACTIVE_20 (0x00100000U) ///< bit 20 -#define NVIC_IABR_ACTIVE_21 (0x00200000U) ///< bit 21 -#define NVIC_IABR_ACTIVE_22 (0x00400000U) ///< bit 22 -#define NVIC_IABR_ACTIVE_23 (0x00800000U) ///< bit 23 -#define NVIC_IABR_ACTIVE_24 (0x01000000U) ///< bit 24 -#define NVIC_IABR_ACTIVE_25 (0x02000000U) ///< bit 25 -#define NVIC_IABR_ACTIVE_26 (0x04000000U) ///< bit 26 -#define NVIC_IABR_ACTIVE_27 (0x08000000U) ///< bit 27 -#define NVIC_IABR_ACTIVE_28 (0x10000000U) ///< bit 28 -#define NVIC_IABR_ACTIVE_29 (0x20000000U) ///< bit 29 -#define NVIC_IABR_ACTIVE_30 (0x40000000U) ///< bit 30 -#define NVIC_IABR_ACTIVE_31 (0x80000000U) ///< bit 31 - -//////////////////////////////////////////////////////////////////////////////// -/// @brief NVIC_PRI0 Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define NVIC_IPR0_PRI_0 (0x000000FFU) ///< Priority of interrupt 0 -#define NVIC_IPR0_PRI_1 (0x0000FF00U) ///< Priority of interrupt 1 -#define NVIC_IPR0_PRI_2 (0x00FF0000U) ///< Priority of interrupt 2 -#define NVIC_IPR0_PRI_3 (0xFF000000U) ///< Priority of interrupt 3 - -//////////////////////////////////////////////////////////////////////////////// -/// @brief NVIC_PRI1 Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define NVIC_IPR1_PRI_4 (0x000000FFU) ///< Priority of interrupt 4 -#define NVIC_IPR1_PRI_5 (0x0000FF00U) ///< Priority of interrupt 5 -#define NVIC_IPR1_PRI_6 (0x00FF0000U) ///< Priority of interrupt 6 -#define NVIC_IPR1_PRI_7 (0xFF000000U) ///< Priority of interrupt 7 - -//////////////////////////////////////////////////////////////////////////////// -/// @brief NVIC_PRI2 Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define NVIC_IPR2_PRI_8 (0x000000FFU) ///< Priority of interrupt 8 -#define NVIC_IPR2_PRI_9 (0x0000FF00U) ///< Priority of interrupt 9 -#define NVIC_IPR2_PRI_10 (0x00FF0000U) ///< Priority of interrupt 10 -#define NVIC_IPR2_PRI_11 (0xFF000000U) ///< Priority of interrupt 11 - -//////////////////////////////////////////////////////////////////////////////// -/// @brief NVIC_PRI3 Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define NVIC_IPR3_PRI_12 (0x000000FFU) ///< Priority of interrupt 12 -#define NVIC_IPR3_PRI_13 (0x0000FF00U) ///< Priority of interrupt 13 -#define NVIC_IPR3_PRI_14 (0x00FF0000U) ///< Priority of interrupt 14 -#define NVIC_IPR3_PRI_15 (0xFF000000U) ///< Priority of interrupt 15 - -//////////////////////////////////////////////////////////////////////////////// -/// @brief NVIC_PRI4 Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define NVIC_IPR4_PRI_16 (0x000000FFU) ///< Priority of interrupt 16 -#define NVIC_IPR4_PRI_17 (0x0000FF00U) ///< Priority of interrupt 17 -#define NVIC_IPR4_PRI_18 (0x00FF0000U) ///< Priority of interrupt 18 -#define NVIC_IPR4_PRI_19 (0xFF000000U) ///< Priority of interrupt 19 - -//////////////////////////////////////////////////////////////////////////////// -/// @brief NVIC_PRI5 Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define NVIC_IPR5_PRI_20 (0x000000FFU) ///< Priority of interrupt 20 -#define NVIC_IPR5_PRI_21 (0x0000FF00U) ///< Priority of interrupt 21 -#define NVIC_IPR5_PRI_22 (0x00FF0000U) ///< Priority of interrupt 22 -#define NVIC_IPR5_PRI_23 (0xFF000000U) ///< Priority of interrupt 23 - -//////////////////////////////////////////////////////////////////////////////// -/// @brief NVIC_PRI6 Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define NVIC_IPR6_PRI_24 (0x000000FFU) ///< Priority of interrupt 24 -#define NVIC_IPR6_PRI_25 (0x0000FF00U) ///< Priority of interrupt 25 -#define NVIC_IPR6_PRI_26 (0x00FF0000U) ///< Priority of interrupt 26 -#define NVIC_IPR6_PRI_27 (0xFF000000U) ///< Priority of interrupt 27 - -//////////////////////////////////////////////////////////////////////////////// -/// @brief NVIC_PRI7 Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define NVIC_IPR7_PRI_28 (0x000000FFU) ///< Priority of interrupt 28 -#define NVIC_IPR7_PRI_29 (0x0000FF00U) ///< Priority of interrupt 29 -#define NVIC_IPR7_PRI_30 (0x00FF0000U) ///< Priority of interrupt 30 -#define NVIC_IPR7_PRI_31 (0xFF000000U) ///< Priority of interrupt 31 - -//////////////////////////////////////////////////////////////////////////////// -/// @brief NVIC_PRI8 Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define NVIC_IPR7_PRI_32 (0x000000FFU) ///< Priority of interrupt 32 -#define NVIC_IPR7_PRI_33 (0x0000FF00U) ///< Priority of interrupt 33 -#define NVIC_IPR7_PRI_34 (0x00FF0000U) ///< Priority of interrupt 34 -#define NVIC_IPR7_PRI_35 (0xFF000000U) ///< Priority of interrupt 35 - -//////////////////////////////////////////////////////////////////////////////// -/// @brief NVIC_PRI9 Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define NVIC_IPR7_PRI_36 (0x000000FFU) ///< Priority of interrupt 36 -#define NVIC_IPR7_PRI_37 (0x0000FF00U) ///< Priority of interrupt 37 -#define NVIC_IPR7_PRI_38 (0x00FF0000U) ///< Priority of interrupt 38 -#define NVIC_IPR7_PRI_39 (0xFF000000U) ///< Priority of interrupt 39 - -//////////////////////////////////////////////////////////////////////////////// -/// @brief NVIC_PRI10 Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define NVIC_IPR7_PRI_40 (0x000000FFU) ///< Priority of interrupt 40 -#define NVIC_IPR7_PRI_41 (0x0000FF00U) ///< Priority of interrupt 41 -#define NVIC_IPR7_PRI_42 (0x00FF0000U) ///< Priority of interrupt 42 -#define NVIC_IPR7_PRI_43 (0xFF000000U) ///< Priority of interrupt 43 - -//////////////////////////////////////////////////////////////////////////////// -/// @brief NVIC_PRI11 Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define NVIC_IPR7_PRI_44 (0x000000FFU) ///< Priority of interrupt 44 -#define NVIC_IPR7_PRI_45 (0x0000FF00U) ///< Priority of interrupt 45 -#define NVIC_IPR7_PRI_46 (0x00FF0000U) ///< Priority of interrupt 46 -#define NVIC_IPR7_PRI_47 (0xFF000000U) ///< Priority of interrupt 47 - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SCB_CPUID Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define SCB_CPUID_REVISION (0x0000000FU) ///< Implementation defined revision number -#define SCB_CPUID_PARTNO (0x0000FFF0U) ///< Number of processor within family -#define SCB_CPUID_Constant (0x000F0000U) ///< Reads as 0x0F -#define SCB_CPUID_VARIANT (0x00F00000U) ///< Implementation defined variant number -#define SCB_CPUID_IMPLEMENTER (0xFF000000U) ///< Implementer code. ARM is 0x41 - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SCB_ICSR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define SCB_ICSR_VECTACTIVE (0x000001FFU) ///< Active ISR number field -#define SCB_ICSR_RETTOBASE (0x00000800U) ///< All active exceptions minus the IPSR_current_exception yields the empty set -#define SCB_ICSR_VECTPENDING (0x003FF000U) ///< Pending ISR number field -#define SCB_ICSR_ISRPENDING (0x00400000U) ///< Interrupt pending flag -#define SCB_ICSR_ISRPREEMPT (0x00800000U) ///< It indicates that a pending interrupt becomes active in the next running cycle -#define SCB_ICSR_PENDSTCLR (0x02000000U) ///< Clear pending SysTick bit -#define SCB_ICSR_PENDSTSET (0x04000000U) ///< Set pending SysTick bit -#define SCB_ICSR_PENDSVCLR (0x08000000U) ///< Clear pending pendSV bit -#define SCB_ICSR_PENDSVSET (0x10000000U) ///< Set pending pendSV bit -#define SCB_ICSR_NMIPENDSET (0x80000000U) ///< Set pending NMI bit - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SCB_VTOR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define SCB_VTOR_TBLOFF (0x1FFFFF80U) ///< Vector table base offset field -#define SCB_VTOR_TBLBASE (0x20000000U) ///< Table base in code(0) or RAM(1) - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SCB_AIRCR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define SCB_AIRCR_VECTRESET (0x00000001U) ///< System Reset bit -#define SCB_AIRCR_VECTCLRACTIVE (0x00000002U) ///< Clear active vector bit -#define SCB_AIRCR_SYSRESETREQ (0x00000004U) ///< Requests chip control logic to generate a reset -#define SCB_AIRCR_PRIGROUP (0x00000700U) ///< PRIGROUP[2:0] bits (Priority group) -#define SCB_AIRCR_PRIGROUP_0 (0x00000100U) ///< Bit 0 -#define SCB_AIRCR_PRIGROUP_1 (0x00000200U) ///< Bit 1 -#define SCB_AIRCR_PRIGROUP_2 (0x00000400U) ///< Bit 2 - -#define SCB_AIRCR_PRIGROUP0 (0x00000000U) ///< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) -#define SCB_AIRCR_PRIGROUP1 (0x00000100U) ///< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) -#define SCB_AIRCR_PRIGROUP2 (0x00000200U) ///< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) -#define SCB_AIRCR_PRIGROUP3 (0x00000300U) ///< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) -#define SCB_AIRCR_PRIGROUP4 (0x00000400U) ///< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) -#define SCB_AIRCR_PRIGROUP5 (0x00000500U) ///< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) -#define SCB_AIRCR_PRIGROUP6 (0x00000600U) ///< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) -#define SCB_AIRCR_PRIGROUP7 (0x00000700U) ///< Priority group=7 (no pre-emption priority, 8 bits of subpriority) - -#define SCB_AIRCR_ENDIANESS (0x00008000U) ///< Data endianness bit -#define SCB_AIRCR_VECTKEY (0xFFFF0000U) ///< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SCB_SCR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define SCB_SCR_SLEEPONEXIT (0x02U) ///< Sleep on exit bit -#define SCB_SCR_SLEEPDEEP (0x04U) ///< Sleep deep bit -#define SCB_SCR_SEVONPEND (0x10U) ///< Wake up from WFE - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SCB_CCR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define SCB_CCR_NONBASETHRDENA (0x0001U) ///< Thread mode can be entered from any level in Handler mode by controlled return value -#define SCB_CCR_USERSETMPEND (0x0002U) ///< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception -#define SCB_CCR_UNALIGN_TRP (0x0008U) ///< Trap for unaligned access -#define SCB_CCR_DIV_0_TRP (0x0010U) ///< Trap on Divide by 0 -#define SCB_CCR_BFHFNMIGN (0x0100U) ///< Handlers running at priority -1 and -2 -#define SCB_CCR_STKALIGN (0x0200U) ///< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SCB_SHPR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define SCB_SHPR_PRI_N (0x000000FFU) ///< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor -#define SCB_SHPR_PRI_N1 (0x0000FF00U) ///< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved -#define SCB_SHPR_PRI_N2 (0x00FF0000U) ///< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV -#define SCB_SHPR_PRI_N3 (0xFF000000U) ///< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SCB_SHCSR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define SCB_SHCSR_MEMFAULTACT (0x00000001U) ///< MemManage is active -#define SCB_SHCSR_BUSFAULTACT (0x00000002U) ///< BusFault is active -#define SCB_SHCSR_USGFAULTACT (0x00000008U) ///< UsageFault is active -#define SCB_SHCSR_SVCALLACT (0x00000080U) ///< SVCall is active -#define SCB_SHCSR_MONITORACT (0x00000100U) ///< Monitor is active -#define SCB_SHCSR_PENDSVACT (0x00000400U) ///< PendSV is active -#define SCB_SHCSR_SYSTICKACT (0x00000800U) ///< SysTick is active -#define SCB_SHCSR_USGFAULTPENDED (0x00001000U) ///< Usage Fault is pended -#define SCB_SHCSR_MEMFAULTPENDED (0x00002000U) ///< MemManage is pended -#define SCB_SHCSR_BUSFAULTPENDED (0x00004000U) ///< Bus Fault is pended -#define SCB_SHCSR_SVCALLPENDED (0x00008000U) ///< SVCall is pended -#define SCB_SHCSR_MEMFAULTENA (0x00010000U) ///< MemManage enable -#define SCB_SHCSR_BUSFAULTENA (0x00020000U) ///< Bus Fault enable -#define SCB_SHCSR_USGFAULTENA (0x00040000U) ///< UsageFault enable - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SCB_CFSR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -///< MFSR -#define SCB_CFSR_IACCVIOL (0x00000001U) ///< Instruction access violation -#define SCB_CFSR_DACCVIOL (0x00000002U) ///< Data access violation -#define SCB_CFSR_MUNSTKERR (0x00000008U) ///< Unstacking error -#define SCB_CFSR_MSTKERR (0x00000010U) ///< Stacking error -#define SCB_CFSR_MMARVALID (0x00000080U) ///< Memory Manage Address Register address valid flag -///< BFSR -#define SCB_CFSR_IBUSERR (0x00000100U) ///< Instruction bus error flag -#define SCB_CFSR_PRECISERR (0x00000200U) ///< Precise data bus error -#define SCB_CFSR_IMPRECISERR (0x00000400U) ///< Imprecise data bus error -#define SCB_CFSR_UNSTKERR (0x00000800U) ///< Unstacking error -#define SCB_CFSR_STKERR (0x00001000U) ///< Stacking error -#define SCB_CFSR_BFARVALID (0x00008000U) ///< Bus Fault Address Register address valid flag -///< UFSR -#define SCB_CFSR_UNDEFINSTR (0x00010000U) ///< The processor attempt to excecute an undefined instruction -#define SCB_CFSR_INVSTATE (0x00020000U) ///< Invalid combination of EPSR and instruction -#define SCB_CFSR_INVPC (0x00040000U) ///< Attempt to load EXC_RETURN into pc illegally -#define SCB_CFSR_NOCP (0x00080000U) ///< Attempt to use a coprocessor instruction -#define SCB_CFSR_UNALIGNED (0x01000000U) ///< Fault occurs when there is an attempt to make an unaligned memory access -#define SCB_CFSR_DIVBYZERO (0x02000000U) ///< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SCB_HFSR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define SCB_HFSR_VECTTBL (0x00000002U) ///< Fault occures because of vector table read on exception processing -#define SCB_HFSR_FORCED (0x40000000U) ///< Hard Fault activated when a configurable Fault was received and cannot activate -#define SCB_HFSR_DEBUGEVT (0x80000000U) ///< Fault related to debug - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SCB_DFSR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define SCB_DFSR_HALTED (0x01U) ///< Halt request flag -#define SCB_DFSR_BKPT (0x02U) ///< BKPT flag -#define SCB_DFSR_DWTTRAP (0x04U) ///< Data Watchpoint and Trace (DWT) flag -#define SCB_DFSR_VCATCH (0x08U) ///< Vector catch flag -#define SCB_DFSR_EXTERNAL (0x10U) ///< External debug request flag - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SCB_MMFAR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define SCB_MMFAR_ADDRESS (0xFFFFFFFFU) ///< Mem Manage fault address field - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SCB_BFAR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define SCB_BFAR_ADDRESS (0xFFFFFFFFU) ///< Bus fault address field - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SCB_AFSR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define SCB_AFSR_IMPDEF (0xFFFFFFFFU) ///< Implementation defined - - - -#endif -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// - -//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_comp.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_comp.h deleted file mode 100644 index 71297819c..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_comp.h +++ /dev/null @@ -1,228 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file reg_comp.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF -/// MM32 FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion - -#ifndef __REG_COMP_H -#define __REG_COMP_H - -// Files includes - -#include -#include -#include "types.h" - - - - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - - - - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief COMP Base Address Definition -//////////////////////////////////////////////////////////////////////////////// -#define COMP_BASE (APB2PERIPH_BASE + 0x4000) ///< Base Address: 0x40014000 - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Comparators Register Structure Definition -//////////////////////////////////////////////////////////////////////////////// -typedef struct { - - - - __IO u32 RESERVED1; ///< offset: 0x00 - __IO u32 RESERVED2; ///< offset: 0x04 - __IO u32 RESERVED3; ///< offset: 0x08 - union { - __IO u32 CSR1; ///< COMP1 Control Status Register offset: 0x0C - __IO u32 COMP1_CSR; - }; - union { - __IO u32 CSR2; ///< COMP2 Control Status Register offset: 0x10 - __IO u32 COMP2_CSR; - }; - __IO u32 RESERVED4; ///< offset: 0x14 - union { - __IO u32 CRV; ///< COMP external reference voltage register offset: 0x18 - __IO u32 COMP_CRV; - }; - union { - __IO u32 POLL1; ///< COMP1 polling register offset: 0x1C - __IO u32 COMP1_POLL; - }; - union { - __IO u32 POLL2; ///< COMP2 polling register offset: 0x20 - __IO u32 COMP2_POLL; - }; -} COMP_TypeDef; - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief COMP type pointer Definition -//////////////////////////////////////////////////////////////////////////////// -#define COMP ((COMP_TypeDef*) COMP_BASE) - - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief COMP_CSR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define COMP_CSR_EN_Pos (0) -#define COMP_CSR_EN (0x01U << COMP_CSR_EN_Pos) ///< Comparator enable -#define COMP_CSR_MODE_Pos (2) -#define COMP_CSR_MODE (0x03U << COMP_CSR_MODE_Pos) ///< Comparator mode -#define COMP_CSR_MODE_LOWESTPOWER (0x00U << COMP_CSR_MODE_Pos) ///< Comparator lowest power mode -#define COMP_CSR_MODE_LOWPOWER (0x01U << COMP_CSR_MODE_Pos) ///< Comparator low power mode -#define COMP_CSR_MODE_MEDIUMRATE (0x02U << COMP_CSR_MODE_Pos) ///< Comparator medium rate mode -#define COMP_CSR_MODE_HIGHRATE (0x03U << COMP_CSR_MODE_Pos) ///< Comparator high rate mode - -#define COMP_CSR_INM_Pos (4) -#define COMP_CSR_INM (0x03U << COMP_CSR_INM_Pos) ///< Comparator inverting input selection -#define COMP_CSR_INM_0 (0x00U << COMP_CSR_INM_Pos) ///< INM0 as COMP inverting input -#define COMP_CSR_INM_1 (0x01U << COMP_CSR_INM_Pos) ///< INM1 as COMP inverting input -#define COMP_CSR_INM_2 (0x02U << COMP_CSR_INM_Pos) ///< INM2 as COMP inverting input -#define COMP_CSR_INM_3 (0x03U << COMP_CSR_INM_Pos) ///< INM3 as COMP inverting input - -#define COMP_CSR_INP_Pos (7) -#define COMP_CSR_INP (0x03U << COMP_CSR_INP_Pos) ///< Comparator non-inverting input selection -#define COMP_CSR_INP_INP0 (0x00U << COMP_CSR_INP_Pos) ///< INP0 as COMP non-inverting input -#define COMP_CSR_INP_INP1 (0x01U << COMP_CSR_INP_Pos) ///< INP1 as COMP non-inverting input -#define COMP_CSR_INP_INP2 (0x02U << COMP_CSR_INP_Pos) ///< INP2 as COMP non-inverting input -#define COMP_CSR_INP_INP3 (0x03U << COMP_CSR_INP_Pos) ///< INP3 as COMP non-inverting input - -#define COMP_CSR_OUT_Pos (10) -#define COMP_CSR_OUT (0x0FU << COMP_CSR_OUT_Pos) ///< Comparator output selection -#define COMP_CSR_OUT_TIM1_BRAKE (0x02U << COMP_CSR_OUT_Pos) ///< Timer1 brake input -#define COMP_CSR_OUT_TIM8_BRAKE (0x03U << COMP_CSR_OUT_Pos) ///< Timer8 brake input -#define COMP_CSR_OUT_TIM1_OCREFCLR (0x06U << COMP_CSR_OUT_Pos) ///< Timer1 ocrefclear input -#define COMP_CSR_OUT_TIM1_CAPTURE1 (0x07U << COMP_CSR_OUT_Pos) ///< Timer1 input capture 1 -#define COMP_CSR_OUT_TIM2_CAPTURE4 (0x08U << COMP_CSR_OUT_Pos) ///< Timer2 input capture 4 -#define COMP_CSR_OUT_TIM2_OCREFCLR (0x09U << COMP_CSR_OUT_Pos) ///< Timer2 ocrefclear input -#define COMP_CSR_OUT_TIM3_CAPTURE1 (0x0AU << COMP_CSR_OUT_Pos) ///< Timer3 input capture 1 -#define COMP_CSR_OUT_TIM3_OCREFCLR (0x0BU << COMP_CSR_OUT_Pos) ///< Timer3 ocrefclear input -#define COMP_CSR_OUT_TIM8_OCREFCLR (0x0FU << COMP_CSR_OUT_Pos) ///< Timer8 ocrefclear input - -#define COMP_CSR_POL_Pos (15) -#define COMP_CSR_POL (0x01U << COMP_CSR_POL_Pos) ///< Comparator output polarity -#define COMP_CSR_HYST_Pos (16) -#define COMP_CSR_HYST (0x03U << COMP_CSR_HYST_Pos) ///< Comparator hysteresis -#define COMP_CSR_HYST_0 (0x00U << COMP_CSR_HYST_Pos) ///< Hysteresis Voltage: 0mV -#define COMP_CSR_HYST_15 (0x01U << COMP_CSR_HYST_Pos) ///< Hysteresis Voltage: 15mV -#define COMP_CSR_HYST_30 (0x02U << COMP_CSR_HYST_Pos) ///< Hysteresis Voltage: 30mV -#define COMP_CSR_HYST_90 (0x03U << COMP_CSR_HYST_Pos) ///< Hysteresis Voltage: 90mV - -#define COMP_CSR_OFLT_Pos (18) -#define COMP_CSR_OFLT (0x07U << COMP_CSR_OFLT_Pos) ///< Comparator output filter -#define COMP_CSR_OFLT_0 (0x00U << COMP_CSR_OFLT_Pos) ///< 0 clock cycle -#define COMP_CSR_OFLT_1 (0x01U << COMP_CSR_OFLT_Pos) ///< 2 clock cycle -#define COMP_CSR_OFLT_2 (0x02U << COMP_CSR_OFLT_Pos) ///< 4 clock cycle -#define COMP_CSR_OFLT_3 (0x03U << COMP_CSR_OFLT_Pos) ///< 8 clock cycle -#define COMP_CSR_OFLT_4 (0x04U << COMP_CSR_OFLT_Pos) ///< 16 clock cycle -#define COMP_CSR_OFLT_5 (0x05U << COMP_CSR_OFLT_Pos) ///< 32 clock cycle -#define COMP_CSR_OFLT_6 (0x06U << COMP_CSR_OFLT_Pos) ///< 64 clock cycle -#define COMP_CSR_OFLT_7 (0x07U << COMP_CSR_OFLT_Pos) ///< 128 clock cycle - -#define COMP_CSR_STA_Pos (30) -#define COMP_CSR_STA (0x01U << COMP_CSR_STA_Pos) ///< Comparator output status -#define COMP_CSR_LOCK_Pos (31) -#define COMP_CSR_LOCK (0x01U << COMP_CSR_LOCK_Pos) ///< Comparator lock - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief COMP_CRV Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define COMP_CRV_Pos (0) -#define COMP_CRV_MASK (0x0FU << COMP_CRV_Pos) ///< Comparator external reference voltage select -#define COMP_CRV_1_20 (0x00U << COMP_CRV_Pos) ///< Comparator external reference voltage select -#define COMP_CRV_2_20 (0x01U << COMP_CRV_Pos) ///< Comparator external reference voltage select -#define COMP_CRV_3_20 (0x02U << COMP_CRV_Pos) ///< Comparator external reference voltage select -#define COMP_CRV_4_20 (0x03U << COMP_CRV_Pos) ///< Comparator external reference voltage select -#define COMP_CRV_5_20 (0x04U << COMP_CRV_Pos) ///< Comparator external reference voltage select -#define COMP_CRV_6_20 (0x05U << COMP_CRV_Pos) ///< Comparator external reference voltage select -#define COMP_CRV_7_20 (0x06U << COMP_CRV_Pos) ///< Comparator external reference voltage select -#define COMP_CRV_8_20 (0x07U << COMP_CRV_Pos) ///< Comparator external reference voltage select -#define COMP_CRV_9_20 (0x08U << COMP_CRV_Pos) ///< Comparator external reference voltage select -#define COMP_CRV_10_20 (0x09U << COMP_CRV_Pos) ///< Comparator external reference voltage select -#define COMP_CRV_11_20 (0x0AU << COMP_CRV_Pos) ///< Comparator external reference voltage select -#define COMP_CRV_12_20 (0x0BU << COMP_CRV_Pos) ///< Comparator external reference voltage select -#define COMP_CRV_13_20 (0x0CU << COMP_CRV_Pos) ///< Comparator external reference voltage select -#define COMP_CRV_14_20 (0x0DU << COMP_CRV_Pos) ///< Comparator external reference voltage select -#define COMP_CRV_15_20 (0x0EU << COMP_CRV_Pos) ///< Comparator external reference voltage select -#define COMP_CRV_16_20 (0x0FU << COMP_CRV_Pos) ///< Comparator external reference voltage select - -#define COMP_CRV_EN_Pos (4) -#define COMP_CRV_EN (0x01U << COMP_CRV_EN_Pos) ///< Comparator external reference voltage enable -#define COMP_CRV_EN_DISABLE (0x00U << COMP_CRV_EN_Pos) ///< Disable comparator external reference voltage -#define COMP_CRV_EN_ENABLE (0x01U << COMP_CRV_EN_Pos) ///< Enable comparator external reference voltage -#define COMP_CRV_SRC_Pos (5) -#define COMP_CRV_SRC (0x01U << COMP_CRV_SRC_Pos) ///< Comparator external reference voltage source select -#define COMP_CRV_SRC_VREF (0x00U << COMP_CRV_SRC_Pos) ///< Select VREF -#define COMP_CRV_SRC_AVDD (0x01U << COMP_CRV_SRC_Pos) ///< Select AVDD - -//////////////////////////////////////////////////////////////////////////////// -/// @brief COMP_POL Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define COMP_POLL_EN_Pos (0) -#define COMP_POLL_EN (0x01U << COMP_POLL_EN_Pos) ///< Comparator polling enable -#define COMP_POLL_EN_DISABLE (0x00U << COMP_POLL_EN_Pos) ///< Disable comparator polling mode -#define COMP_POLL_EN_ENABLE (0x01U << COMP_POLL_EN_Pos) ///< Enable comparator polling mode -#define COMP_POLL_CH_Pos (1) -#define COMP_POLL_CH (0x01U << COMP_POLL_CH_Pos) ///< Comparator polling channel -#define COMP_POLL_CH_1_2 (0x00U << COMP_POLL_CH_Pos) ///< Polling channel 1/2 -#define COMP_POLL_CH_1_2_3 (0x01U << COMP_POLL_CH_Pos) ///< Polling channel 1/2/3 -#define COMP_POLL_FIXN_Pos (2) -#define COMP_POLL_FIXN (0x01U << COMP_POLL_FIXN_Pos) ///< Polling inverting input fix -#define COMP_POLL_FIXN_NOTFIXED (0x00U << COMP_POLL_FIXN_Pos) ///< Polling channel inverting input is not fixed -#define COMP_POLL_FIXN_FIXED (0x01U << COMP_POLL_FIXN_Pos) ///< Polling channel inverting input fixed -#define COMP_POLL_PERIOD_Pos (4) -#define COMP_POLL_PERIOD (0x07U << COMP_POLL_PERIOD_Pos) ///< polling wait cycle -#define COMP_POLL_PERIOD_1 (0x00U << COMP_POLL_PERIOD_Pos) ///< 1 clock cycle -#define COMP_POLL_PERIOD_2 (0x01U << COMP_POLL_PERIOD_Pos) ///< 2 clock cycle -#define COMP_POLL_PERIOD_4 (0x02U << COMP_POLL_PERIOD_Pos) ///< 4 clock cycle -#define COMP_POLL_PERIOD_8 (0x03U << COMP_POLL_PERIOD_Pos) ///< 8 clock cycle -#define COMP_POLL_PERIOD_16 (0x04U << COMP_POLL_PERIOD_Pos) ///< 16 clock cycle -#define COMP_POLL_PERIOD_32 (0x05U << COMP_POLL_PERIOD_Pos) ///< 32 clock cycle -#define COMP_POLL_PERIOD_64 (0x06U << COMP_POLL_PERIOD_Pos) ///< 64 clock cycle -#define COMP_POLL_PERIOD_128 (0x07U << COMP_POLL_PERIOD_Pos) ///< 128 clock cycle -#define COMP_POLL_POUT_Pos (8) -#define COMP_POLL_POUT (0x07U << COMP_POLL_POUT_Pos) ///< Polling output -#define COMP_POLL_POUT_Low (0x00U << COMP_POLL_POUT_Pos) ///< Non-inverting input is lower than inverting input -#define COMP_POLL_POUT_High (0x01U << COMP_POLL_POUT_Pos) ///< Non-inverting input is higher than inverting input - - - - - -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -#endif -//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_crc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_crc.h deleted file mode 100644 index 9bb28e56f..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_crc.h +++ /dev/null @@ -1,102 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file reg_crc.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF -/// MM32 FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion - -#ifndef __REG_CRC_H -#define __REG_CRC_H - -// Files includes -#include -#include -#include "types.h" - - - - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - - - - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief CRC Base Address Definition -//////////////////////////////////////////////////////////////////////////////// -#define CRC_BASE (AHBPERIPH_BASE + 0x3000) ///< Base Address: 0x40023000 - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief CRC Register Structure Definition -//////////////////////////////////////////////////////////////////////////////// -typedef struct { - __IO u32 DR; ///< CRC data register, offset: 0x00 - __IO u32 IDR; ///< CRC independent data register, offset: 0x04 - __IO u32 CR; ///< CRC control register, offset: 0x08 - __IO u32 MIR; ///< Middle data register, offset: 0x08 -} CRC_TypeDef; - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief CRC type pointer Definition -//////////////////////////////////////////////////////////////////////////////// -#define CRC ((CRC_TypeDef*) CRC_BASE) - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief CRC_DR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define CRC_DR_DATA_Pos (0) -#define CRC_DR_DATA (0xFFFFFFFFU << CRC_DR_DATA_Pos) ///< Data register bits -//////////////////////////////////////////////////////////////////////////////// -/// @brief CRC_IDR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define CRC_IDR_DATA_Pos (0) -#define CRC_IDR_DATA (0xFFU << CRC_IDR_DATA_Pos) ///< General-purpose 8-bit data register bits - -//////////////////////////////////////////////////////////////////////////////// -/// @brief CRC_CTRL Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define CRC_CR_RESET_Pos (0) -#define CRC_CR_RESET (0x01U << CRC_CR_RESET_Pos) ///< RESET bit -//////////////////////////////////////////////////////////////////////////////// -/// @brief CRC_MIR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define CRC_MIR_Pos (0) -#define CRC_MIR (0xFFFFFFFFU << CRC_MIR_Pos) ///< Middle data register - - - - -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -#endif -//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_crs.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_crs.h deleted file mode 100644 index a8beece98..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_crs.h +++ /dev/null @@ -1,152 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file reg_crs.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF -/// MM32 FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion - -#ifndef __REG_CRS_H -#define __REG_CRS_H - -// Files includes - -#include -#include -#include "types.h" - - - - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - - - - - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief CRS Base Address Definition -//////////////////////////////////////////////////////////////////////////////// -#define CRS_BASE (APB1PERIPH_BASE + 0x6C00) ///< Base Address: 0x40006C00 - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief CRS Register Structure Definition -//////////////////////////////////////////////////////////////////////////////// -typedef struct { - __IO u32 CR; ///< Control Register offset: 0x00 - __IO u32 CFGR; ///< Configuration Register offset: 0x04 - __IO u32 ISR; ///< Interrupt and Status Register offset: 0x08 - __IO u32 ICR; ///< Interrupt Flag Clear Register offset: 0x0C -} CRS_TypeDef; - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief CRS type pointer Definition -//////////////////////////////////////////////////////////////////////////////// -#define CRS ((CRS_TypeDef*) CRS_BASE) - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief CRS_CR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define CRS_CR_OKIE_Pos (0) -#define CRS_CR_OKIE (0x01U << CRS_CR_OKIE_Pos) ///< SYNC event OK interrupt enable -#define CRS_CR_WARNIE_Pos (1) -#define CRS_CR_WARNIE (0x01U << CRS_CR_WARNIE_Pos) ///< SYNC warning interrupt enable -#define CRS_CR_ERRIE_Pos (2) -#define CRS_CR_ERRIE (0x01U << CRS_CR_ERRIE_Pos) ///< Synchronization or trimming error interrupt enable -#define CRS_CR_EXPTIE_Pos (3) -#define CRS_CR_EXPTIE (0x01U << CRS_CR_EXPTIE_Pos) ///< Expected SYNC interrupt enable -#define CRS_CR_CNTEN_Pos (5) -#define CRS_CR_CNTEN (0x01U << CRS_CR_CNTEN_Pos) ///< Frequency error counter enable -#define CRS_CR_AUTOTRIMEN_Pos (6) -#define CRS_CR_AUTOTRIMEN (0x01U << CRS_CR_AUTOTRIMEN_Pos) ///< Automatic trimming enable -#define CRS_CR_SWSYNC_Pos (7) -#define CRS_CR_SWSYNC (0x01U << CRS_CR_SWSYNC_Pos) ///< Generate software SYNC event -#define CRS_CR_TRIM_Pos (8) -#define CRS_CR_TRIM (0x3FFU << CRS_CR_TRIM_Pos) ///< HSI 48 oscillator smooth trimming - -//////////////////////////////////////////////////////////////////////////////// -/// @brief CRS_CFGR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define CRS_CFGR_RELOAD_Pos (0) -#define CRS_CFGR_RELOAD (0xFFFFU << CRS_CFGR_RELOAD_Pos) ///< Counter reload value -#define CRS_CFGR_FELIM_Pos (16) -#define CRS_CFGR_FELIM (0xFFU << CRS_CFGR_FELIM_Pos) ///< Frequency error limit -#define CRS_CFGR_DIV_Pos (24) -#define CRS_CFGR_DIV (0x07U << CRS_CFGR_DIV_Pos) ///< SYNC divider -#define CRS_CFGR_SRC_Pos (28) -#define CRS_CFGR_SRC (0x03U << CRS_CFGR_SRC_Pos) ///< SYNC signal source selection -#define CRS_CFGR_SRC_MCO (0x00U << CRS_CFGR_SRC_Pos) -#define CRS_CFGR_SRC_USBSOF (0x02U << CRS_CFGR_SRC_Pos) -#define CRS_CFGR_POL_Pos (31) -#define CRS_CFGR_POL (0x01U << CRS_CFGR_POL_Pos) ///< SYNC polarity selection - -//////////////////////////////////////////////////////////////////////////////// -/// @brief CRS_ISR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define CRS_ISR_OKIF_Pos (0) -#define CRS_ISR_OKIF (0x01U << CRS_ISR_OKIF_Pos) ///< SYNC event OK flag -#define CRS_ISR_WARNIF_Pos (1) -#define CRS_ISR_WARNIF (0x01U << CRS_ISR_WARNIF_Pos) ///< SYNC warning flag -#define CRS_ISR_ERRIF_Pos (2) -#define CRS_ISR_ERRIF (0x01U << CRS_ISR_ERRIF_Pos) ///< Error flag -#define CRS_ISR_EXPTIF_Pos (3) -#define CRS_ISR_EXPTIF (0x01U << CRS_ISR_EXPTIF_Pos) ///< Expected SYNC flag -#define CRS_ISR_ERR_Pos (8) -#define CRS_ISR_ERR (0x01U << CRS_ISR_ERR_Pos) ///< SYNC error -#define CRS_ISR_MISS_Pos (9) -#define CRS_ISR_MISS (0x01U << CRS_ISR_MISS_Pos) ///< SYNC missed -#define CRS_ISR_OVERFLOW_Pos (10) -#define CRS_ISR_OVERFLOW (0x01U << CRS_ISR_OVERFLOW_Pos) ///< Trimming overflow or underflow -#define CRS_ISR_FEDIR_Pos (15) -#define CRS_ISR_FEDIR (0x01U << CRS_ISR_FEDIR_Pos) ///< Frequency error direction -#define CRS_ISR_FECAP_Pos (16) -#define CRS_ISR_FECAP (0xFFFFU << CRS_ISR_FECAP_Pos) ///< Frequency error capture - -//////////////////////////////////////////////////////////////////////////////// -/// @brief CRS_ICR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define CRS_ICR_OK_Pos (0) -#define CRS_ICR_OK (0x01U << CRS_ICR_OK_Pos) ///< SYNC event OK clear flag -#define CRS_ICR_WARN_Pos (1) -#define CRS_ICR_WARN (0x01U << CRS_ICR_WARN_Pos) ///< SYNC warning clear flag -#define CRS_ICR_ERR_Pos (2) -#define CRS_ICR_ERR (0x01U << CRS_ICR_ERR_Pos) ///< Error clear flag -#define CRS_ICR_EXPT_Pos (3) -#define CRS_ICR_EXPT (0x01U << CRS_ICR_EXPT_Pos) ///< Expected SYNC clear flag - - - - - -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -#endif -//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dac.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dac.h deleted file mode 100644 index 2e8d1883d..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dac.h +++ /dev/null @@ -1,247 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file reg_dac.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF -/// MM32 FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion - -#ifndef __REG_DAC_H -#define __REG_DAC_H - -// Files includes - -#include -#include -#include "types.h" - - - - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - - - - - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief DAC Base Address Definition -//////////////////////////////////////////////////////////////////////////////// -#define DAC_BASE (APB1PERIPH_BASE + 0x7400) ///< Base Address: 0x40007400 - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Digital to analog converter register -//////////////////////////////////////////////////////////////////////////////// -typedef struct { - __IO u32 CR; ///< DAC control register, offset: 0x00 - __IO u32 SWTRIGR; ///< DAC software trigger register, offset: 0x04 - __IO u32 DHR12R1; ///< Channel 1 12-bit right align data register, offset: 0x08 - __IO u32 DHR12L1; ///< Channel 1 12-bit left align data register, offset: 0x0C - __IO u32 DHR8R1; ///< Channel 1 8-bit right align data register, offset: 0x10 - __IO u32 DHR12R2; ///< Channel 2 12-bit right align data register, offset: 0x14 - __IO u32 DHR12L2; ///< Channel 2 12-bit left align data register, offset: 0x18 - __IO u32 DHR8R2; ///< Channel 2 8-bit right align data register, offset: 0x1C - __IO u32 DHR12RD; ///< Dual channel 12-bit right align data register,offset: 0x20 - __IO u32 DHR12LD; ///< Dual channel 12-bit left align data register, offset: 0x24 - __IO u32 DHR8RD; ///< Dual channel 8-bit right align data register, offset: 0x28 - __IO u32 DOR1; ///< Channel 1 output register, offset: 0x2C - __IO u32 DOR2; ///< Channel 2 output register, offset: 0x30 -} DAC_TypeDef; - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief DAC type pointer Definition -//////////////////////////////////////////////////////////////////////////////// -#define DAC ((DAC_TypeDef*) DAC_BASE) - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief DAC_CR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define DAC_CR_EN1_Pos (0) -#define DAC_CR_EN1 (0x01U << DAC_CR_EN1_Pos) ///< DAC channel1 enable -#define DAC_CR_BOFF1_Pos (1) -#define DAC_CR_BOFF1 (0x01U << DAC_CR_BOFF1_Pos) ///< DAC channel1 output buffer disable -#define DAC_CR_TEN1_Pos (2) -#define DAC_CR_TEN1 (0x01U << DAC_CR_TEN1_Pos) ///< DAC channel1 Trigger enable -#define DAC_CR_TSEL1_Pos (3) -#define DAC_CR_TSEL1 (0x07U << DAC_CR_TSEL1_Pos) ///< TSEL1[2:0] (DAC channel1 Trigger selection) -#define DAC_CR_TSEL1_TIM1_TRIG (0x00U << DAC_CR_TSEL1_Pos) ///< TIM1_TRIG trigger -#define DAC_CR_TSEL1_TIM3_TRIG (0x01U << DAC_CR_TSEL1_Pos) ///< TIM3_TRIG trigger -#define DAC_CR_TSEL1_TIM2_TRIG (0x04U << DAC_CR_TSEL1_Pos) ///< TIM2_TRIG trigger -#define DAC_CR_TSEL1_TIM4_TRIG (0x05U << DAC_CR_TSEL1_Pos) ///< TIM4_TRIG trigger -#define DAC_CR_TSEL1_EXTI9 (0x06U << DAC_CR_TSEL1_Pos) ///< External interrupt line 9 trigger -#define DAC_CR_TSEL1_SOFTWARE (0x07U << DAC_CR_TSEL1_Pos) ///< Software trigger -#define DAC_CR_WAVE1_Pos (6) -#define DAC_CR_WAVE1 (0x03U << DAC_CR_WAVE1_Pos) ///< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) -#define DAC_CR_WAVE1_NONE (0x00U << DAC_CR_WAVE1_Pos) ///< Turn off waveform generation -#define DAC_CR_WAVE1_NOISE (0x01U << DAC_CR_WAVE1_Pos) ///< Noise waveform generation -#define DAC_CR_WAVE1_TRIANGLE (0x02U << DAC_CR_WAVE1_Pos) ///< Triangle wave generation -#define DAC_CR_MAMP1_Pos (8) -#define DAC_CR_MAMP1 (0x0FU << DAC_CR_MAMP1_Pos) ///< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) -#define DAC_CR_MAMP1_1 (0x00U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 1 -#define DAC_CR_MAMP1_3 (0x01U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 3 -#define DAC_CR_MAMP1_7 (0x02U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 7 -#define DAC_CR_MAMP1_15 (0x03U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 15 -#define DAC_CR_MAMP1_31 (0x04U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 31 -#define DAC_CR_MAMP1_63 (0x05U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 63 -#define DAC_CR_MAMP1_127 (0x06U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 127 -#define DAC_CR_MAMP1_255 (0x07U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 255 -#define DAC_CR_MAMP1_511 (0x08U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 511 -#define DAC_CR_MAMP1_1023 (0x09U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 1023 -#define DAC_CR_MAMP1_2047 (0x0AU << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 2047 -#define DAC_CR_MAMP1_4095 (0x0BU << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 4095 -#define DAC_CR_DMAEN1_Pos (12) -#define DAC_CR_DMAEN1 (0x01U << DAC_CR_DMAEN1_Pos) ///< DAC channel1 DMA enable -#define DAC_CR_EN2_Pos (16) -#define DAC_CR_EN2 (0x01U << DAC_CR_EN2_Pos) ///< DAC channel2 enable -#define DAC_CR_BOFF2_Pos (17) -#define DAC_CR_BOFF2 (0x01U << DAC_CR_BOFF2_Pos) ///< DAC channel2 output buffer disable -#define DAC_CR_TEN2_Pos (18) -#define DAC_CR_TEN2 (0x01U << DAC_CR_TEN2_Pos) ///< DAC channel2 Trigger enable -#define DAC_CR_TSEL2_Pos (19) -#define DAC_CR_TSEL2 (0x07U << DAC_CR_TSEL2_Pos) ///< TSEL1[2:0] (DAC channel1 Trigger selection) -#define DAC_CR_TSEL2_TIM1_TRIG (0x00U << DAC_CR_TSEL2_Pos) ///< TIM1_TRIG trigger -#define DAC_CR_TSEL2_TIM3_TRIG (0x01U << DAC_CR_TSEL2_Pos) ///< TIM3_TRIG trigger -#define DAC_CR_TSEL2_TIM2_TRIG (0x04U << DAC_CR_TSEL2_Pos) ///< TIM2_TRIG trigger -#define DAC_CR_TSEL2_TIM4_TRIG (0x05U << DAC_CR_TSEL2_Pos) ///< TIM4_TRIG trigger -#define DAC_CR_TSEL2_EXTI9 (0x06U << DAC_CR_TSEL2_Pos) ///< External interrupt line 9 trigger -#define DAC_CR_TSEL2_SOFTWARE (0x07U << DAC_CR_TSEL2_Pos) ///< Software trigger -#define DAC_CR_WAVE2_Pos (22) -#define DAC_CR_WAVE2 (0x03U << DAC_CR_WAVE2_Pos) ///< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) -#define DAC_CR_WAVE2_NONE (0x00U << DAC_CR_WAVE2_Pos) ///< Turn off waveform generation -#define DAC_CR_WAVE2_NOISE (0x01U << DAC_CR_WAVE2_Pos) ///< Noise waveform generation -#define DAC_CR_WAVE2_TRIANGLE (0x02U << DAC_CR_WAVE2_Pos) ///< Triangle wave generation -#define DAC_CR_MAMP2_Pos (24) -#define DAC_CR_MAMP2 (0x0FU << DAC_CR_MAMP2_Pos) ///< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) -#define DAC_CR_MAMP2_1 (0x00U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 1 -#define DAC_CR_MAMP2_3 (0x01U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 3 -#define DAC_CR_MAMP2_7 (0x02U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 7 -#define DAC_CR_MAMP2_15 (0x03U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 15 -#define DAC_CR_MAMP2_31 (0x04U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 31 -#define DAC_CR_MAMP2_63 (0x05U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 63 -#define DAC_CR_MAMP2_127 (0x06U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 127 -#define DAC_CR_MAMP2_255 (0x07U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 255 -#define DAC_CR_MAMP2_511 (0x08U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 511 -#define DAC_CR_MAMP2_1023 (0x09U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 1023 -#define DAC_CR_MAMP2_2047 (0x0AU << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 2047 -#define DAC_CR_MAMP2_4095 (0x0BU << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 4095 -#define DAC_CR_DMAEN2_Pos (28) -#define DAC_CR_DMAEN2 (0x01U << DAC_CR_DMAEN2_Pos) ///< DAC channel2 DMA enabled - -//////////////////////////////////////////////////////////////////////////////// -/// @brief DAC_SWTRIGR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define DAC_SWTRIGR_SWTRIG1_Pos (0) -#define DAC_SWTRIGR_SWTRIG1 (0x01U << DAC_SWTRIGR_SWTRIG1_Pos) ///< DAC channel1 software trigger -#define DAC_SWTRIGR_SWTRIG2_Pos (1) -#define DAC_SWTRIGR_SWTRIG2 (0x01U << DAC_SWTRIGR_SWTRIG2_Pos) ///< DAC channel2 software trigger -#define DAC_SWTRIGR_DACPRE_Pos (8) -#define DAC_SWTRIGR_DACPRE (0x7FU << DAC_SWTRIGR_DACPRE_Pos) ///< DAC prescale - -//////////////////////////////////////////////////////////////////////////////// -/// @brief DAC_DHR12R1 Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define DAC_DHR12R1_DACC1DHR_Pos (0) -#define DAC_DHR12R1_DACC1DHR (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) ///< DAC channel1 12-bit Right align data - -//////////////////////////////////////////////////////////////////////////////// -/// @brief DAC_DHR12L1 Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define DAC_DHR12L1_DACC1DHR_Pos (4) -#define DAC_DHR12L1_DACC1DHR (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) ///< DAC channel1 12-bit Left align data - -//////////////////////////////////////////////////////////////////////////////// -/// @brief DAC_DHR8R1 Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define DAC_DHR8R1_DACC1DHR_Pos (0) -#define DAC_DHR8R1_DACC1DHR (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) ///< DAC channel1 8-bit Right align data - -//////////////////////////////////////////////////////////////////////////////// -/// @brief DAC_DHR12R2 Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define DAC_DHR12R2_DACC2DHR_Pos (0) -#define DAC_DHR12R2_DACC2DHR (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) ///< DAC channel2 12-bit Right align data - -//////////////////////////////////////////////////////////////////////////////// -/// @brief DAC_DHR12L2 Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define DAC_DHR12L2_DACC2DHR_Pos (4) -#define DAC_DHR12L2_DACC2DHR (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) ///< DAC channel2 12-bit Left align data - -//////////////////////////////////////////////////////////////////////////////// -/// @brief DAC_DHR8R2 Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define DAC_DHR8R2_DACC2DHR_Pos (0) -#define DAC_DHR8R2_DACC2DHR (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) ///< DAC channel2 8-bit Right align data - -//////////////////////////////////////////////////////////////////////////////// -/// @brief DAC_DHR12RD Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define DAC_DHR12RD_DACC1DHR_Pos (0) -#define DAC_DHR12RD_DACC1DHR (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) ///< DAC channel1 12-bit Right align data -#define DAC_DHR12RD_DACC2DHR_Pos (16) -#define DAC_DHR12RD_DACC2DHR (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) ///< DAC channel2 12-bit Right align data - -//////////////////////////////////////////////////////////////////////////////// -/// @brief DAC_DHR12LD Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define DAC_DHR12LD_DACC1DHR_Pos (4) -#define DAC_DHR12LD_DACC1DHR (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) ///< DAC channel1 12-bit Right align data -#define DAC_DHR12LD_DACC2DHR_Pos (20) -#define DAC_DHR12LD_DACC2DHR (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) ///< DAC channel2 12-bit Right align data - -//////////////////////////////////////////////////////////////////////////////// -/// @brief DAC_DHR8RD Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define DAC_DHR8RD_DACC1DHR_Pos (0) -#define DAC_DHR8RD_DACC1DHR (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) ///< DAC channel1 8-bit Right align data -#define DAC_DHR8RD_DACC2DHR_Pos (8) -#define DAC_DHR8RD_DACC2DHR (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) ///< DAC channel2 8-bit Right align data - -//////////////////////////////////////////////////////////////////////////////// -/// @brief DAC_DOR1 Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define DAC_DOR1_DACC1DOR_Pos (0) -#define DAC_DOR1_DACC1DOR (0xFFFU << DAC_DOR1_DACC1DOR_Pos) ///< DAC channel1 data output - -//////////////////////////////////////////////////////////////////////////////// -/// @brief DAC_DOR2 Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define DAC_DOR2_DACC2DOR_Pos (0) -#define DAC_DOR2_DACC2DOR (0xFFFU << DAC_DOR2_DACC2DOR_Pos) ///< DAC channel2 data output #endif - - - - - -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -#endif -//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dbg.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dbg.h deleted file mode 100644 index 5e378753e..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dbg.h +++ /dev/null @@ -1,113 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file reg_dbg.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF -/// MM32 FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion - -#ifndef __REG_DBG_H -#define __REG_DBG_H - -// Files includes - -#include -#include -#include "types.h" - - - - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - - - - - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief DBG Base Address Definition -//////////////////////////////////////////////////////////////////////////////// - -#define DBG_BASE (0x40007080UL) ///< Base Address: 0x40007080 -//////////////////////////////////////////////////////////////////////////////// -/// @brief DEBUG Registers Structure Definition -//////////////////////////////////////////////////////////////////////////////// -typedef struct { - __IO u32 IDCODE; ///< Code ID offset: 0x00 - __IO u32 CR; ///< Control Register offset: 0x04 -} DBGMCU_TypeDef; - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief DBGMCU type pointer Definition -//////////////////////////////////////////////////////////////////////////////// -#define DBGMCU ((DBGMCU_TypeDef*) DBG_BASE) - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief DBGMCU_IDCODE Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define DBGMCU_IDCODE_DEV_ID_Pos (0) -#define DBGMCU_IDCODE_DEV_ID (0xFFFFFFFFU << DBGMCU_IDCODE_DEV_ID_Pos) ///< Device identifier - -//////////////////////////////////////////////////////////////////////////////// -/// @brief DBGMCU_CR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define DBGMCU_CR_SLEEP_Pos (0) -#define DBGMCU_CR_SLEEP (0x01U << DBGMCU_CR_SLEEP_Pos) ///< Debug Sleep mode -#define DBGMCU_CR_STOP_Pos (1) -#define DBGMCU_CR_STOP (0x01U << DBGMCU_CR_STOP_Pos) ///< Debug Stop mode -#define DBGMCU_CR_STANDBY_Pos (2) -#define DBGMCU_CR_STANDBY (0x01U << DBGMCU_CR_STANDBY_Pos) ///< Debug Standby mode -#define DBGMCU_CR_TRACE_IOEN_Pos (5) -#define DBGMCU_CR_TRACE_IOEN (0x01U << DBGMCU_CR_TRACE_IOEN_Pos) ///< Trace pin assignment -#define DBGMCU_CR_TRACE_MODE_Pos (6) -#define DBGMCU_CR_TRACE_MODE_Msk (0x03U << DBGMCU_CR_TRACE_MODE_Pos) ///< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) -#define DBGMCU_CR_TRACE_MODE_0 (0x01U << DBGMCU_CR_TRACE_MODE_Pos) ///< Bit 0 -#define DBGMCU_CR_TRACE_MODE_1 (0x02U << DBGMCU_CR_TRACE_MODE_Pos) ///< Bit 1 -#define DBGMCU_CR_TRACE_MODE_ASYNC (0x00U << DBGMCU_CR_TRACE_MODE_Pos) ///< Tracking pin uses asynchronous mode -#define DBGMCU_CR_TRACE_MODE_SYNC1 (0x01U << DBGMCU_CR_TRACE_MODE_Pos) ///< The trace pin uses synchronous mode, and the data length is 1 -#define DBGMCU_CR_TRACE_MODE_SYNC2 (0x02U << DBGMCU_CR_TRACE_MODE_Pos) ///< The trace pin uses synchronous mode, and the data length is 2 - -#define DBGMCU_CR_IWDG_STOP_Pos (8) -#define DBGMCU_CR_IWDG_STOP (0x01U << DBGMCU_CR_IWDG_STOP_Pos) ///< Debug independent watchdog stopped when core is halted -#define DBGMCU_CR_WWDG_STOP_Pos (9) -#define DBGMCU_CR_WWDG_STOP (0x01U << DBGMCU_CR_WWDG_STOP_Pos) ///< Debug window watchdog stopped when core is halted -#define DBGMCU_CR_TIM_STOP_Pos (10) -#define DBGMCU_CR_TIM1_STOP (0x01U << DBGMCU_CR_TIM_STOP_Pos) ///< TIM1 counter stopped when core is halted -#define DBGMCU_CR_TIM2_STOP (0x02U << DBGMCU_CR_TIM_STOP_Pos) ///< TIM2 counter stopped when core is halted -#define DBGMCU_CR_TIM3_STOP (0x04U << DBGMCU_CR_TIM_STOP_Pos) ///< TIM3 counter stopped when core is halted -#define DBGMCU_CR_TIM4_STOP (0x08U << DBGMCU_CR_TIM_STOP_Pos) ///< TIM4 counter stopped when core is halted - - - - - -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -#endif -//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dma.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dma.h deleted file mode 100644 index ffcba5654..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dma.h +++ /dev/null @@ -1,325 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file reg_dma.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF -/// MM32 FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion - -#ifndef __REG_DMA_H -#define __REG_DMA_H - -// Files includes - -#include -#include -#include "types.h" - - - - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - - - - - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief DMA Base Address Definition -//////////////////////////////////////////////////////////////////////////////// -#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) ///< Base Address: 0x40020000 -#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) ///< Base Address: 0x40020008 -#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) ///< Base Address: 0x4002001C -#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) ///< Base Address: 0x40020030 -#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) ///< Base Address: 0x40020044 -#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) ///< Base Address: 0x40020058 - -#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) ///< Base Address: 0x4002006C -#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) ///< Base Address: 0x40020080 -#define DMA2_BASE (AHBPERIPH_BASE + 0x0400) ///< Base Address: 0x40020400 -#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) ///< Base Address: 0x40020408 -#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) ///< Base Address: 0x4002041C -#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) ///< Base Address: 0x40020430 -#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) ///< Base Address: 0x40020444 -#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) ///< Base Address: 0x40020458 - -//////////////////////////////////////////////////////////////////////////////// -/// @brief DMA Register Structure Definition -//////////////////////////////////////////////////////////////////////////////// -typedef struct { - __IO u32 CCR; ///< DMA channel x configuration register offset: 0x00 - __IO u32 CNDTR; ///< DMA channel x number of data register offset: 0x04 - __IO u32 CPAR; ///< DMA channel x peripheral address register offset: 0x08 - __IO u32 CMAR; ///< DMA channel x memory address register offset: 0x0C -} DMA_Channel_TypeDef; - -typedef struct { - __IO u32 ISR; ///< Interrupt Status Register offset: 0x00 - __IO u32 IFCR; ///< Interrupt Flag Clear Register offset: 0x04 - __IO u32 CCRx; ///< Channel X configures registers offset: 0x08 - __IO u32 CNDTRx; ///< Channel X transfer quantity register offset: 0x0C - __IO u32 CPARx; ///< Channel X peripheral address register offset: 0x10 - __IO u32 CMARx; ///< Channel X memory address register offset: 0x14 -} DMA_TypeDef; - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief DMA type pointer Definition -//////////////////////////////////////////////////////////////////////////////// -#define DMA1 ((DMA_TypeDef*) DMA1_BASE) -#define DMA1_ch1 ((DMA_Channel_TypeDef*) DMA1_Channel1_BASE) -#define DMA1_ch2 ((DMA_Channel_TypeDef*) DMA1_Channel2_BASE) -#define DMA1_ch3 ((DMA_Channel_TypeDef*) DMA1_Channel3_BASE) -#define DMA1_ch4 ((DMA_Channel_TypeDef*) DMA1_Channel4_BASE) -#define DMA1_ch5 ((DMA_Channel_TypeDef*) DMA1_Channel5_BASE) - -#define DMA1_Channel1 ((DMA_Channel_TypeDef*) DMA1_Channel1_BASE) -#define DMA1_Channel2 ((DMA_Channel_TypeDef*) DMA1_Channel2_BASE) -#define DMA1_Channel3 ((DMA_Channel_TypeDef*) DMA1_Channel3_BASE) -#define DMA1_Channel4 ((DMA_Channel_TypeDef*) DMA1_Channel4_BASE) -#define DMA1_Channel5 ((DMA_Channel_TypeDef*) DMA1_Channel5_BASE) - - -#define DMA1_ch6 ((DMA_Channel_TypeDef*) DMA1_Channel6_BASE) -#define DMA1_ch7 ((DMA_Channel_TypeDef*) DMA1_Channel7_BASE) - -#define DMA1_Channel6 ((DMA_Channel_TypeDef*) DMA1_Channel6_BASE) -#define DMA1_Channel7 ((DMA_Channel_TypeDef*) DMA1_Channel7_BASE) - -#define DMA2 ((DMA_TypeDef*) DMA2_BASE) -#define DMA2_ch1 ((DMA_Channel_TypeDef*) DMA2_Channel1_BASE) -#define DMA2_ch2 ((DMA_Channel_TypeDef*) DMA2_Channel2_BASE) -#define DMA2_ch3 ((DMA_Channel_TypeDef*) DMA2_Channel3_BASE) -#define DMA2_ch4 ((DMA_Channel_TypeDef*) DMA2_Channel4_BASE) -#define DMA2_ch5 ((DMA_Channel_TypeDef*) DMA2_Channel5_BASE) -#define DMA2_Channel1 ((DMA_Channel_TypeDef*) DMA2_Channel1_BASE) -#define DMA2_Channel2 ((DMA_Channel_TypeDef*) DMA2_Channel2_BASE) -#define DMA2_Channel3 ((DMA_Channel_TypeDef*) DMA2_Channel3_BASE) -#define DMA2_Channel4 ((DMA_Channel_TypeDef*) DMA2_Channel4_BASE) -#define DMA2_Channel5 ((DMA_Channel_TypeDef*) DMA2_Channel5_BASE) - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief DMA_ISR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define DMA_ISR_GIF1_Pos (0) -#define DMA_ISR_GIF1 (0x01U << DMA_ISR_GIF1_Pos) ///< Channel 1 Global interrupt flag -#define DMA_ISR_TCIF1_Pos (1) -#define DMA_ISR_TCIF1 (0x01U << DMA_ISR_TCIF1_Pos) ///< Channel 1 Transfer Complete flag -#define DMA_ISR_HTIF1_Pos (2) -#define DMA_ISR_HTIF1 (0x01U << DMA_ISR_HTIF1_Pos) ///< Channel 1 Half Transfer flag -#define DMA_ISR_TEIF1_Pos (3) -#define DMA_ISR_TEIF1 (0x01U << DMA_ISR_TEIF1_Pos) ///< Channel 1 Transfer Error flag -#define DMA_ISR_GIF2_Pos (4) -#define DMA_ISR_GIF2 (0x01U << DMA_ISR_GIF2_Pos) ///< Channel 2 Global interrupt flag -#define DMA_ISR_TCIF2_Pos (5) -#define DMA_ISR_TCIF2 (0x01U << DMA_ISR_TCIF2_Pos) ///< Channel 2 Transfer Complete flag -#define DMA_ISR_HTIF2_Pos (6) -#define DMA_ISR_HTIF2 (0x01U << DMA_ISR_HTIF2_Pos) ///< Channel 2 Half Transfer flag -#define DMA_ISR_TEIF2_Pos (7) -#define DMA_ISR_TEIF2 (0x01U << DMA_ISR_TEIF2_Pos) ///< Channel 2 Transfer Error flag -#define DMA_ISR_GIF3_Pos (8) -#define DMA_ISR_GIF3 (0x01U << DMA_ISR_GIF3_Pos) ///< Channel 3 Global interrupt flag -#define DMA_ISR_TCIF3_Pos (9) -#define DMA_ISR_TCIF3 (0x01U << DMA_ISR_TCIF3_Pos) ///< Channel 3 Transfer Complete flag -#define DMA_ISR_HTIF3_Pos (10) -#define DMA_ISR_HTIF3 (0x01U << DMA_ISR_HTIF3_Pos) ///< Channel 3 Half Transfer flag -#define DMA_ISR_TEIF3_Pos (11) -#define DMA_ISR_TEIF3 (0x01U << DMA_ISR_TEIF3_Pos) ///< Channel 3 Transfer Error flag -#define DMA_ISR_GIF4_Pos (12) -#define DMA_ISR_GIF4 (0x01U << DMA_ISR_GIF4_Pos) ///< Channel 4 Global interrupt flag -#define DMA_ISR_TCIF4_Pos (13) -#define DMA_ISR_TCIF4 (0x01U << DMA_ISR_TCIF4_Pos) ///< Channel 4 Transfer Complete flag -#define DMA_ISR_HTIF4_Pos (14) -#define DMA_ISR_HTIF4 (0x01U << DMA_ISR_HTIF4_Pos) ///< Channel 4 Half Transfer flag -#define DMA_ISR_TEIF4_Pos (15) -#define DMA_ISR_TEIF4 (0x01U << DMA_ISR_TEIF4_Pos) ///< Channel 4 Transfer Error flag -#define DMA_ISR_GIF5_Pos (16) -#define DMA_ISR_GIF5 (0x01U << DMA_ISR_GIF5_Pos) ///< Channel 5 Global interrupt flag -#define DMA_ISR_TCIF5_Pos (17) -#define DMA_ISR_TCIF5 (0x01U << DMA_ISR_TCIF5_Pos) ///< Channel 5 Transfer Complete flag -#define DMA_ISR_HTIF5_Pos (18) -#define DMA_ISR_HTIF5 (0x01U << DMA_ISR_HTIF5_Pos) ///< Channel 5 Half Transfer flag -#define DMA_ISR_TEIF5_Pos (19) -#define DMA_ISR_TEIF5 (0x01U << DMA_ISR_TEIF5_Pos) ///< Channel 5 Transfer Error flag - -#define DMA_ISR_GIF6_Pos (20) -#define DMA_ISR_GIF6 (0x01U << DMA_ISR_GIF6_Pos) ///< Channel 6 Global interrupt flag -#define DMA_ISR_TCIF6_Pos (21) -#define DMA_ISR_TCIF6 (0x01U << DMA_ISR_TCIF6_Pos) ///< Channel 6 Transfer Complete flag -#define DMA_ISR_HTIF6_Pos (22) -#define DMA_ISR_HTIF6 (0x01U << DMA_ISR_HTIF6_Pos) ///< Channel 6 Half Transfer flag -#define DMA_ISR_TEIF6_Pos (23) -#define DMA_ISR_TEIF6 (0x01U << DMA_ISR_TEIF6_Pos) ///< Channel 6 Transfer Error flag -#define DMA_ISR_GIF7_Pos (24) -#define DMA_ISR_GIF7 (0x01U << DMA_ISR_GIF7_Pos) ///< Channel 7 Global interrupt flag -#define DMA_ISR_TCIF7_Pos (25) -#define DMA_ISR_TCIF7 (0x01U << DMA_ISR_TCIF7_Pos) ///< Channel 7 Transfer Complete flag -#define DMA_ISR_HTIF7_Pos (26) -#define DMA_ISR_HTIF7 (0x01U << DMA_ISR_HTIF7_Pos) ///< Channel 7 Half Transfer flag -#define DMA_ISR_TEIF7_Pos (27) -#define DMA_ISR_TEIF7 (0x01U << DMA_ISR_TEIF7_Pos) ///< Channel 7 Transfer Error flag - -//////////////////////////////////////////////////////////////////////////////// -/// @brief DMA_IFCR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define DMA_IFCR_CGIF1_Pos (0) -#define DMA_IFCR_CGIF1 (0x01U << DMA_IFCR_CGIF1_Pos) ///< Channel 1 Global interrupt clearr -#define DMA_IFCR_CTCIF1_Pos (1) -#define DMA_IFCR_CTCIF1 (0x01U << DMA_IFCR_CTCIF1_Pos) ///< Channel 1 Transfer Complete clear -#define DMA_IFCR_CHTIF1_Pos (2) -#define DMA_IFCR_CHTIF1 (0x01U << DMA_IFCR_CHTIF1_Pos) ///< Channel 1 Half Transfer clear -#define DMA_IFCR_CTEIF1_Pos (3) -#define DMA_IFCR_CTEIF1 (0x01U << DMA_IFCR_CTEIF1_Pos) ///< Channel 1 Transfer Error clear -#define DMA_IFCR_CGIF2_Pos (4) -#define DMA_IFCR_CGIF2 (0x01U << DMA_IFCR_CGIF2_Pos) ///< Channel 2 Global interrupt clear -#define DMA_IFCR_CTCIF2_Pos (5) -#define DMA_IFCR_CTCIF2 (0x01U << DMA_IFCR_CTCIF2_Pos) ///< Channel 2 Transfer Complete clear -#define DMA_IFCR_CHTIF2_Pos (6) -#define DMA_IFCR_CHTIF2 (0x01U << DMA_IFCR_CHTIF2_Pos) ///< Channel 2 Half Transfer clear -#define DMA_IFCR_CTEIF2_Pos (7) -#define DMA_IFCR_CTEIF2 (0x01U << DMA_IFCR_CTEIF2_Pos) ///< Channel 2 Transfer Error clear -#define DMA_IFCR_CGIF3_Pos (8) -#define DMA_IFCR_CGIF3 (0x01U << DMA_IFCR_CGIF3_Pos) ///< Channel 3 Global interrupt clear -#define DMA_IFCR_CTCIF3_Pos (9) -#define DMA_IFCR_CTCIF3 (0x01U << DMA_IFCR_CTCIF3_Pos) ///< Channel 3 Transfer Complete clear -#define DMA_IFCR_CHTIF3_Pos (10) -#define DMA_IFCR_CHTIF3 (0x01U << DMA_IFCR_CHTIF3_Pos) ///< Channel 3 Half Transfer clear -#define DMA_IFCR_CTEIF3_Pos (11) -#define DMA_IFCR_CTEIF3 (0x01U << DMA_IFCR_CTEIF3_Pos) ///< Channel 3 Transfer Error clear -#define DMA_IFCR_CGIF4_Pos (12) -#define DMA_IFCR_CGIF4 (0x01U << DMA_IFCR_CGIF4_Pos) ///< Channel 4 Global interrupt clear -#define DMA_IFCR_CTCIF4_Pos (13) -#define DMA_IFCR_CTCIF4 (0x01U << DMA_IFCR_CTCIF4_Pos) ///< Channel 4 Transfer Complete clear -#define DMA_IFCR_CHTIF4_Pos (14) -#define DMA_IFCR_CHTIF4 (0x01U << DMA_IFCR_CHTIF4_Pos) ///< Channel 4 Half Transfer clear -#define DMA_IFCR_CTEIF4_Pos (15) -#define DMA_IFCR_CTEIF4 (0x01U << DMA_IFCR_CTEIF4_Pos) ///< Channel 4 Transfer Error clear -#define DMA_IFCR_CGIF5_Pos (16) -#define DMA_IFCR_CGIF5 (0x01U << DMA_IFCR_CGIF5_Pos) ///< Channel 5 Global interrupt clear -#define DMA_IFCR_CTCIF5_Pos (17) -#define DMA_IFCR_CTCIF5 (0x01U << DMA_IFCR_CTCIF5_Pos) ///< Channel 5 Transfer Complete clear -#define DMA_IFCR_CHTIF5_Pos (18) -#define DMA_IFCR_CHTIF5 (0x01U << DMA_IFCR_CHTIF5_Pos) ///< Channel 5 Half Transfer clear -#define DMA_IFCR_CTEIF5_Pos (19) -#define DMA_IFCR_CTEIF5 (0x01U << DMA_IFCR_CTEIF5_Pos) ///< Channel 5 Transfer Error clear - -#define DMA_IFCR_CGIF6_Pos (20) -#define DMA_IFCR_CGIF6 (0x01U << DMA_IFCR_CGIF6_Pos) ///< Channel 6 Global interrupt clear -#define DMA_IFCR_CTCIF6_Pos (21) -#define DMA_IFCR_CTCIF6 (0x01U << DMA_IFCR_CTCIF6_Pos) ///< Channel 6 Transfer Complete clear -#define DMA_IFCR_CHTIF6_Pos (22) -#define DMA_IFCR_CHTIF6 (0x01U << DMA_IFCR_CHTIF6_Pos) ///< Channel 6 Half Transfer clear -#define DMA_IFCR_CTEIF6_Pos (23) -#define DMA_IFCR_CTEIF6 (0x01U << DMA_IFCR_CTEIF6_Pos) ///< Channel 6 Transfer Error clear -#define DMA_IFCR_CGIF7_Pos (24) -#define DMA_IFCR_CGIF7 (0x01U << DMA_IFCR_CGIF7_Pos) ///< Channel 7 Global interrupt clear -#define DMA_IFCR_CTCIF7_Pos (25) -#define DMA_IFCR_CTCIF7 (0x01U << DMA_IFCR_CTCIF7_Pos) ///< Channel 7 Transfer Complete clear -#define DMA_IFCR_CHTIF7_Pos (26) -#define DMA_IFCR_CHTIF7 (0x01U << DMA_IFCR_CHTIF7_Pos) ///< Channel 7 Half Transfer clear -#define DMA_IFCR_CTEIF7_Pos (27) -#define DMA_IFCR_CTEIF7 (0x01U << DMA_IFCR_CTEIF7_Pos) ///< Channel 7 Transfer Error clear - -//////////////////////////////////////////////////////////////////////////////// -/// @brief DMA_CCR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define DMA_CCR_EN_Pos (0) -#define DMA_CCR_EN (0x01U << DMA_CCR_EN_Pos) ///< Channel enabl -#define DMA_CCR_TCIE_Pos (1) -#define DMA_CCR_TCIE (0x01U << DMA_CCR_TCIE_Pos) ///< Transfer complete interrupt enable -#define DMA_CCR_HTIE_Pos (2) -#define DMA_CCR_HTIE (0x01U << DMA_CCR_HTIE_Pos) ///< Half Transfer interrupt enable -#define DMA_CCR_TEIE_Pos (3) -#define DMA_CCR_TEIE (0x01U << DMA_CCR_TEIE_Pos) ///< Transfer error interrupt enable -#define DMA_CCR_DIR_Pos (4) -#define DMA_CCR_DIR (0x01U << DMA_CCR_DIR_Pos) ///< Data transfer direction -#define DMA_CCR_CIRC_Pos (5) -#define DMA_CCR_CIRC (0x01U << DMA_CCR_CIRC_Pos) ///< Circular mode -#define DMA_CCR_PINC_Pos (6) -#define DMA_CCR_PINC (0x01U << DMA_CCR_PINC_Pos) ///< Peripheral increment mode -#define DMA_CCR_MINC_Pos (7) -#define DMA_CCR_MINC (0x01U << DMA_CCR_MINC_Pos) ///< Memory increment mode - -#define DMA_CCR_PSIZE_Pos (8) -#define DMA_CCR_PSIZE (0x03U << DMA_CCR_PSIZE_Pos) ///< PSIZE[1:0] bits (Peripheral size) -#define DMA_CCR_PSIZE_0 (0x01U << DMA_CCR_PSIZE_Pos) ///< Bit0 -#define DMA_CCR_PSIZE_1 (0x02U << DMA_CCR_PSIZE_Pos) ///< Bit1 - -#define DMA_CCR_PSIZE_BYTE (0x00U << DMA_CCR_PSIZE_Pos) ///< DMA Peripheral Data Size Byte -#define DMA_CCR_PSIZE_HALFWORD (0x01U << DMA_CCR_PSIZE_Pos) ///< DMA Peripheral Data Size HalfWord -#define DMA_CCR_PSIZE_WORD (0x02U << DMA_CCR_PSIZE_Pos) ///< DMA Peripheral Data Size Word - -#define DMA_CCR_MSIZE_Pos (10) -#define DMA_CCR_MSIZE (0x03U << DMA_CCR_MSIZE_Pos) ///< MSIZE[1:0] bits (Memory size) -#define DMA_CCR_MSIZE_0 (0x01U << DMA_CCR_MSIZE_Pos) ///< Bit0 -#define DMA_CCR_MSIZE_1 (0x02U << DMA_CCR_MSIZE_Pos) ///< Bit1 - -#define DMA_CCR_MSIZE_BYTE (0x00U << DMA_CCR_MSIZE_Pos) ///< DMA Memory Data Size Byte -#define DMA_CCR_MSIZE_HALFWORD (0x01U << DMA_CCR_MSIZE_Pos) ///< DMA Memory Data Size HalfWord -#define DMA_CCR_MSIZE_WORD (0x02U << DMA_CCR_MSIZE_Pos) ///< DMA Memory Data Size Word - -#define DMA_CCR_PL_Pos (12) -#define DMA_CCR_PL (0x03U << DMA_CCR_PL_Pos) ///< PL[1:0] bits(Channel Priority level) -#define DMA_CCR_PL_0 (0x01U << DMA_CCR_PL_Pos) ///< Bit0 -#define DMA_CCR_PL_1 (0x02U << DMA_CCR_PL_Pos) ///< Bit1 - -#define DMA_CCR_PL_Low (0x00U << DMA_CCR_PL_Pos) ///< DMA Priority Low -#define DMA_CCR_PL_Medium (0x01U << DMA_CCR_PL_Pos) ///< DMA Priority Medium -#define DMA_CCR_PL_High (0x02U << DMA_CCR_PL_Pos) ///< DMA Priority High -#define DMA_CCR_PL_VeryHigh (0x03U << DMA_CCR_PL_Pos) ///< DMA Priority VeryHigh -#define DMA_CCR_M2M_Pos (14) -#define DMA_CCR_M2M (0x01U << DMA_CCR_M2M_Pos) ///< Memory to memory mode - -#define DMA_CCR_ARE_Pos (15) -#define DMA_CCR_ARE (0x01U << DMA_CCR_ARE_Pos) ///< Auto-Reload Enable bit - -//////////////////////////////////////////////////////////////////////////////// -/// @brief DMA_CNDTR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define DMA_CNDTR_NDT_Pos (0) -#define DMA_CNDTR_NDT (0xFFFFU << DMA_CNDTR_NDT_Pos) ///< Number of data to Transfer - -//////////////////////////////////////////////////////////////////////////////// -/// @brief DMA_CPAR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define DMA_CPAR_PA_Pos (0) -#define DMA_CPAR_PA (0xFFFFFFFFU << DMA_CPAR_PA_Pos) ///< Peripheral Address - -//////////////////////////////////////////////////////////////////////////////// -/// @brief DMA_CMAR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define DMA_CMAR_MA_Pos (0) -#define DMA_CMAR_MA (0xFFFFFFFFU << DMA_CMAR_MA_Pos) ///< Peripheral Address - - - - - -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -#endif -//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_eth.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_eth.h deleted file mode 100644 index 61a0d25c2..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_eth.h +++ /dev/null @@ -1,730 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file reg_iwdg.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF -/// MM32 FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion - -#ifndef __REG_ETH_H -#define __REG_ETH_H - -// Files includes - -#include -#include -#include "types.h" - -#include "reg_common.h" - - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - -//////////////////////////////////////////////////////////////////////////////// -/// @brief IWDG Base Address Definition -//////////////////////////////////////////////////////////////////////////////// -#define ETH_BASE (AHBPERIPH_BASE + 0x8000) ///< Base Address: 0x40028000 - - -#define ETH ((ETH_TypeDef*) ETH_BASE) -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH Register Structure Definition -//////////////////////////////////////////////////////////////////////////////// -typedef struct { - __IO u32 MACCR; ///< configuration register offset 0x0000 - __IO u32 MACFFR; ///< frame filter register offset 0x0004 - __IO u32 MACHTHR; ///< Hash list high register offset 0x0008 - __IO u32 MACHTLR; ///< Hash list low register offset 0x000C - __IO u32 MACMIIAR; ///< MII address register offset 0x0010 - __IO u32 MACMIIDR; ///< MII data register offset 0x0014 - __IO u32 MACFCR; ///< flow control register offset 0x0018 - __IO u32 MACVLANTR; ///< VLAN label register offset 0x001C - __IO u32 RESERVEDX0020[2]; /// 0x0020 ~ 0x0024 - __IO u32 MACRWUFFR; /// 0x0028 - __IO u32 MACPMTCSR; /// 0x002C - __IO u32 RESERVEDX0030[4]; /// 0x0030 ~ 0x003C - __IO u32 MACA0HR; ///< address 0 high register offset 0x0040 - __IO u32 MACA0LR; ///< address 0 low register offset 0x0044 - __IO u32 MACA1HR; ///< address 1 high register offset 0x0048 - __IO u32 MACA1LR; ///< address 1 low register offset 0x004C - __IO u32 MACA2HR; ///< address 2 high register offset 0x0050 - __IO u32 MACA2LR; ///< address 2 low register offset 0x0054 - __IO u32 MACA3HR; ///< address 3 high register offset 0x0058 - __IO u32 MACA3LR; ///< address 3 low register offset 0x005C - __IO u32 MACA4HR; ///< address 4 high register offset 0x0060 - __IO u32 MACA4LR; ///< address 4 low register offset 0x0064 - __IO u32 MACA5HR; ///< address 5 high register offset 0x0068 - __IO u32 MACA5LR; ///< address 5 low register offset 0x006C - __IO u32 MACA6HR; ///< address 6 high register offset 0x0070 - __IO u32 MACA6LR; ///< address 6 low register offset 0x0074 - __IO u32 MACA7HR; ///< address 7 high register offset 0x0078 - __IO u32 MACA7LR; ///< address 7 low register offset 0x007C - __IO u32 MACA8HR; ///< address 8 high register offset 0x0080 - __IO u32 MACA8LR; ///< address 8 low register offset 0x0084 - __IO u32 MACA9HR; ///< address 9 high register offset 0x0088 - __IO u32 MACA9LR; ///< address 9 low register offset 0x008C - __IO u32 MACA10HR; ///< address 10 high register offset 0x0090 - __IO u32 MACA10LR; ///< address 10 low register offset 0x0094 - __IO u32 MACA11HR; ///< address 11 high register offset 0x0098 - __IO u32 MACA11LR; ///< address 11 low register offset 0x009C - __IO u32 MACA12HR; ///< address 12 high register offset 0x00A0 - __IO u32 MACA12LR; ///< address 12 low register offset 0x00A4 - __IO u32 MACA13HR; ///< address 13 high register offset 0x00A8 - __IO u32 MACA13LR; ///< address 13 low register offset 0x00AC - __IO u32 MACA14HR; ///< address 14 high register offset 0x00B0 - __IO u32 MACA14LR; ///< address 14 low register offset 0x00B4 - __IO u32 MACA15HR; ///< address 15 high register offset 0x00B8 - __IO u32 MACA15LR; ///< address 15 low register offset 0x00BC - __IO u32 MACANCR; ///< Automatic negotiation control register offset 0x00C0 - __IO u32 MACANSR; ///< Automatic negotiation of the status register offset 0x00C4 - __IO u32 MACANAR; ///< Automatic negotiation of broadcast registers offset 0x00C8 - __IO u32 MACANLPAR; ///< Automatic negotiation of link partner capability register offset 0x00CC - __IO u32 MACANER; ///< Automatic negotiation of extension registers offset 0x00D0 - __IO u32 MACTBIER; ///< Ten - place interface extension register offset 0x00D4 - __IO u32 MACMIISR; ///< MII status register offset 0x00D8 - __IO u32 RESERVEDX00DC[9]; ///< offset 0x00DC ~ 0x00FC - __IO u32 MMCCR; ///< MMC controls registers offset 0x0100 - __IO u32 MMCRIR; ///< The MMC receives the interrupt register offset 0x0104 - __IO u32 MMCTIR; ///< The MMC sends the interrupt register offset 0x0108 - __IO u32 MMCRIMR; ///< The MMC receives the interrupt mask register offset 0x010C - __IO u32 MMCTIMR; ///< MMC sends interrupt masking registers offset 0x0110 - __IO u32 RESERVEDX0114[14]; ///< offset 0x0114 ~ 0x0148 - __IO u32 MMCTGFSCCR; ///< A good frame counter register that MMC sends after a single conflict offset 0x014C - __IO u32 MMCTGFMSCCR; ///< A good frame counter register that MMC sends after multiple collisions offset 0x0150 - __IO u32 RESERVEDX0154[5]; ///< offset 0x0154 ~ 0x0164 - __IO u32 MMCTGFCR; ///< Good frame counter register sent by MMC offset 0x0168 - __IO u32 RESERVEDX016C[10]; ///< offset 0x016C ~ 0x0190 - __IO u32 MMCRFCECR; ///< Ethernet MMC with CRC error counter register receives frame register offset 0x0194 - __IO u32 MMCRFAECR; ///< Ethernet MMC receives frames with alignment error counter registers offset 0x0198 - __IO u32 RESERVEDX019C[10]; ///< offset 0x019C ~ 0x01C0 - __IO u32 MMCRGUFCR; ///< Good unicast frame counter register received by MMC offset 0x01C4 - __IO u32 RESERVEDx01C8[910]; ///< offset 0x01C8 ~ 0x0FFC - __IO u32 DMABMR; ///< Bus mode register offset 0x1000 - __IO u32 DMATPDR; ///< DMA sends the polling request register offset 0x1004 - __IO u32 DMARPDR; ///< DMA receives the polling request register offset 0x1008 - __IO u32 DMARDLAR; ///< DMA receives a list of descriptor addresses offset 0x100C - __IO u32 DMATDLAR; ///< DMA sends the descriptor list address offset 0x1010 - __IO u32 DMASR; ///< DMA status register offset 0x1014 - __IO u32 DMAOMR; ///< DMA working mode register offset 0x1018 - __IO u32 DMAIER; ///< DMA interrupt enablement register offset 0x101C - __IO u32 DMAMFBOCR; ///< DMA lost frames and cache overflow counter registers offset 0x1020 - __IO u32 DMARSWTR; /// 0x1024 - __IO u32 RESERVEDX1028[8]; /// 0x1028 ~ 0x1044 - __IO u32 DMACHTDR; /// 0x1048 - __IO u32 DMACHRDR; /// 0x104C - __IO u32 DMACHTBAR; ///< DMA is currently sending the cache address register offset 0x1050 - __IO u32 DMACHRBAR; ///< DMA currently receives the cache address register offset 0x1054 -} ETH_TypeDef; - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH_MACCR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define ETH_MACCR_WD_Pos (23) -#define ETH_MACCR_WD (0x01U << ETH_MACCR_WD_Pos) ///< Watchdog disable -#define ETH_MACCR_JD_Pos (22) -#define ETH_MACCR_JD (0x01U << ETH_MACCR_JD_Pos) ///< Jabber disable -#define ETH_MACCR_FBE_Pos (21) -#define ETH_MACCR_FBE (0x01U << ETH_MACCR_FBE_Pos) ///< Frame Burst Enable -#define ETH_MACCR_JE_Pos (20) -#define ETH_MACCR_JE (0x01U << ETH_MACCR_JE_Pos) ///< Jumbo Frame Enable -#define ETH_MACCR_IFG_Pos (17) ///< Inter-frame gap -#define ETH_MACCR_IFG_96Bit (0x00U << ETH_MACCR_IFG_Pos) ///< Minimum IFG between frames during transmission is 96Bit -#define ETH_MACCR_IFG_88Bit (0x01U << ETH_MACCR_IFG_Pos) ///< Minimum IFG between frames during transmission is 88Bit -#define ETH_MACCR_IFG_80Bit (0x02U << ETH_MACCR_IFG_Pos) ///< Minimum IFG between frames during transmission is 80Bit -#define ETH_MACCR_IFG_72Bit (0x03U << ETH_MACCR_IFG_Pos) ///< Minimum IFG between frames during transmission is 72Bit -#define ETH_MACCR_IFG_64Bit (0x04U << ETH_MACCR_IFG_Pos) ///< Minimum IFG between frames during transmission is 64Bit -#define ETH_MACCR_IFG_56Bit (0x05U << ETH_MACCR_IFG_Pos) ///< Minimum IFG between frames during transmission is 56Bit -#define ETH_MACCR_IFG_48Bit (0x06U << ETH_MACCR_IFG_Pos) ///< Minimum IFG between frames during transmission is 48Bit -#define ETH_MACCR_IFG_40Bit (0x07U << ETH_MACCR_IFG_Pos) ///< Minimum IFG between frames during transmission is 40Bit -#define ETH_MACCR_FES_Pos (14) -#define ETH_MACCR_FES (0x01U << ETH_MACCR_FES_Pos) ///< Fast ethernet speed -#define ETH_MACCR_ROD_Pos (13) -#define ETH_MACCR_ROD (0x01U << ETH_MACCR_ROD_Pos) ///< Receive own disable -#define ETH_MACCR_LM_Pos (12) -#define ETH_MACCR_LM (0x01U << ETH_MACCR_LM_Pos) ///< loopback mode -#define ETH_MACCR_DM_Pos (11) -#define ETH_MACCR_DM (0x01U << ETH_MACCR_DM_Pos) ///< Duplex mode -#define ETH_MACCR_IPCO_Pos (10) -#define ETH_MACCR_IPCO (0x01U << ETH_MACCR_IPCO_Pos) ///< IP Checksum offload -#define ETH_MACCR_RD_Pos (9) -#define ETH_MACCR_RD (0x01U << ETH_MACCR_RD_Pos) ///< Retry disable -#define ETH_MACCR_APCS_Pos (8) -#define ETH_MACCR_APCS (0x01U << ETH_MACCR_APCS_Pos) ///< Automatic Pad/CRC stripping -#define ETH_MACCR_BL_Pos (5) ///< Back-off limit: random integer number (r) of slot time delays before rescheduling a transmission attempt during retries after a collision: 0 =< r <2^k -#define ETH_MACCR_BL_10 (0x00U << ETH_MACCR_BL_Pos) ///< k = min (n, 10) -#define ETH_MACCR_BL_8 (0x01U << ETH_MACCR_BL_Pos) ///< k = min (n, 8) -#define ETH_MACCR_BL_4 (0x02U << ETH_MACCR_BL_Pos) ///< k = min (n, 4) -#define ETH_MACCR_BL_1 (0x03U << ETH_MACCR_BL_Pos) ///< k = min (n, 1) -#define ETH_MACCR_DC_Pos (4) -#define ETH_MACCR_DC (0x01U << ETH_MACCR_DC_Pos) ///< Defferal check -#define ETH_MACCR_TE_Pos (3) -#define ETH_MACCR_TE (0x01U << ETH_MACCR_TE_Pos) ///< Transmitter enable -#define ETH_MACCR_RE_Pos (2) -#define ETH_MACCR_RE (0x01U << ETH_MACCR_RE_Pos) ///< Receiver enable -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH_MACFFR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define ETH_MACFFR_RA_Pos (31) -#define ETH_MACFFR_RA (0x01U << ETH_MACFFR_RA_Pos) ///< Receive all - -#define ETH_MACFFR_SAF_Pos (9) -#define ETH_MACFFR_SAF (0x01U << ETH_MACFFR_SAF_Pos) ///< Source address filter enable -#define ETH_MACFFR_SAIF_Pos (8) -#define ETH_MACFFR_SAIF (0x01U << ETH_MACFFR_SAIF_Pos) ///< SA inverse filtering -#define ETH_MACFFR_PCF_Pos (6) -#define ETH_MACFFR_PCF (0x03U << ETH_MACFFR_PCF_Pos) ///< Pass control frames: 3 cases -#define ETH_MACFFR_PCF_BlockAll (0x01U << ETH_MACFFR_PCF_Pos) ///< MAC filters all control frames from reaching the application -#define ETH_MACFFR_PCF_ForwardAll (0x02U << ETH_MACFFR_PCF_Pos) ///< MAC forwards all control frames to application even if they fail the Address Filter -#define ETH_MACFFR_PCF_ForwardPassedAddrFilter (0x03U << ETH_MACFFR_PCF_Pos) ///< MAC forwards control frames that pass the Address Filter. -#define ETH_MACFFR_BFD_Pos (5) -#define ETH_MACFFR_BFD (0x01U << ETH_MACFFR_BFD_Pos) ///< Broadcast frame disable -#define ETH_MACFFR_PAM_Pos (4) -#define ETH_MACFFR_PAM (0x01U << ETH_MACFFR_PAM_Pos) ///< Pass all mutlicast -#define ETH_MACFFR_DAIF_Pos (3) -#define ETH_MACFFR_DAIF (0x01U << ETH_MACFFR_DAIF_Pos) ///< DA Inverse filtering -#define ETH_MACFFR_HM_Pos (2) -#define ETH_MACFFR_HM (0x01U << ETH_MACFFR_HM_Pos) ///< Hash multicast -#define ETH_MACFFR_HU_Pos (1) -#define ETH_MACFFR_HU (0x01U << ETH_MACFFR_HU_Pos) ///< Hash unicast -#define ETH_MACFFR_PM_Pos (0) -#define ETH_MACFFR_PM (0x01U << ETH_MACFFR_PM_Pos) ///< Promiscuous mode - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH_MACHTHR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define ETH_MACHTHR_HTH (0xFFFFFFFFU) ///< Hash table high - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH_MACHTLR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define ETH_MACHTLR_HTL (0xFFFFFFFFU) ///< Hash table low - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH_MACMIIAR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define ETH_MACMIIAR_PA_Pos (11) -#define ETH_MACMIIAR_PA (0x1FU << ETH_MACMIIAR_PA_Pos) ///< Physical layer address -#define ETH_MACMIIAR_MR_Pos (6) -#define ETH_MACMIIAR_MR (0x1FU << ETH_MACMIIAR_MR_Pos) ///< MII register in the selected PHY -#define ETH_MACMIIAR_CR_Pos (2) -#define ETH_MACMIIAR_CR (0x07U << ETH_MACMIIAR_CR_Pos) ///< CR clock range: 6 cases -#define ETH_MACMIIAR_CR_Div42 (0x00U << ETH_MACMIIAR_CR_Pos) ///< HCLK:60-100 MHz; MDC clock= HCLK/42 -#define ETH_MACMIIAR_CR_Div62 (0x01U << ETH_MACMIIAR_CR_Pos) ///< HCLK:100-150 MHz; MDC clock= HCLK/62 -#define ETH_MACMIIAR_CR_Div16 (0x02U << ETH_MACMIIAR_CR_Pos) ///< HCLK:20-35 MHz; MDC clock= HCLK/16 -#define ETH_MACMIIAR_CR_Div26 (0x03U << ETH_MACMIIAR_CR_Pos) ///< HCLK:35-60 MHz; MDC clock= HCLK/26 -#define ETH_MACMIIAR_CR_Div102 (0x04U << ETH_MACMIIAR_CR_Pos) ///< HCLK:150-168 MHz; MDC clock= HCLK/102 -#define ETH_MACMIIAR_MW_Pos (1) -#define ETH_MACMIIAR_MW (0x01U << ETH_MACMIIAR_MW_Pos) ///< MII write -#define ETH_MACMIIAR_MB_Pos (0) -#define ETH_MACMIIAR_MB (0x01U << ETH_MACMIIAR_MB_Pos) ///< MII busy - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH_MACMIIDR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define ETH_MACMIIDR_MD (0x0000FFFFU) ///< MII data: read/write data from/to PHY - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH_MACFCR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define ETH_MACFCR_PT_Pos (16) -#define ETH_MACFCR_PT ((u32)0xFFFF << ETH_MACFCR_PT_Pos) ///< Pause time -#define ETH_MACFCR_PLT_Pos (4) -#define ETH_MACFCR_PLT (0x03U << ETH_MACFCR_PLT_Pos) ///< Pause low threshold: 4 cases -#define ETH_MACFCR_PLT_Minus4 (0x00U << ETH_MACFCR_PLT_Pos) ///< Pause time minus 4 slot times -#define ETH_MACFCR_PLT_Minus28 (0x01U << ETH_MACFCR_PLT_Pos) ///< Pause time minus 28 slot times -#define ETH_MACFCR_PLT_Minus144 (0x02U << ETH_MACFCR_PLT_Pos) ///< Pause time minus 144 slot times -#define ETH_MACFCR_PLT_Minus256 (0x03U << ETH_MACFCR_PLT_Pos) ///< Pause time minus 256 slot times -#define ETH_MACFCR_UPFD_Pos (3) -#define ETH_MACFCR_UPFD (0x01U << ETH_MACFCR_UPFD_Pos) ///< Unicast pause frame detect -#define ETH_MACFCR_RFCE_Pos (2) -#define ETH_MACFCR_RFCE (0x01U << ETH_MACFCR_RFCE_Pos) ///< Receive flow control enable -#define ETH_MACFCR_TFCE_Pos (1) -#define ETH_MACFCR_TFCE (0x01U << ETH_MACFCR_TFCE_Pos) ///< Transmit flow control enable -#define ETH_MACFCR_FCBBPA_Pos (0) -#define ETH_MACFCR_FCBBPA (0x01U << ETH_MACFCR_FCBBPA_Pos) ///< Flow control busy/backpressure activate - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH_MACVLANTR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define ETH_MACVLANTR_VLANTI (0x0000FFFFU) ///< VLAN tag identifier (for receive frames) - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH_MACRWUFFR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define ETH_MACRWUFFR_D (0xFFFFFFFFU) ///< Wake-up frame filter register data -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH_MACPMTCSR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define ETH_MACPMTCSR_WFFRPR_Pos (31) ///< Wake-Up Frame Filter Register Pointer Reset -#define ETH_MACPMTCSR_WFFRPR (0x01U << ETH_MACPMTCSR_WFFRPR_Pos) ///< Wake-Up Frame Filter Register Pointer Reset -#define ETH_MACPMTCSR_GU_Pos (9) -#define ETH_MACPMTCSR_GU (0x01U << ETH_MACPMTCSR_GU_Pos) ///< Global Unicast -#define ETH_MACPMTCSR_WFR_Pos (6) -#define ETH_MACPMTCSR_WFR (0x01U << ETH_MACPMTCSR_WFR_Pos) ///< Wake-Up Frame Received -#define ETH_MACPMTCSR_MPR_Pos (5) -#define ETH_MACPMTCSR_MPR (0x01U << ETH_MACPMTCSR_MPR_Pos) ///< Magic Packet Received -#define ETH_MACPMTCSR_WFE_Pos (2) -#define ETH_MACPMTCSR_WFE (0x01U << ETH_MACPMTCSR_WFE_Pos) ///< Wake-Up Frame Enable -#define ETH_MACPMTCSR_MPE_Pos (1) -#define ETH_MACPMTCSR_MPE (0x01U << ETH_MACPMTCSR_MPE_Pos) ///< Magic Packet Enable -#define ETH_MACPMTCSR_PD_Pos (0) -#define ETH_MACPMTCSR_PD (0x01U << ETH_MACPMTCSR_PD_Pos) ///< Power Down -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH_MACA0HR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define ETH_MACA0HR_MACA0H ((u32)0x0000FFFF) ///< MAC address0 high - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH_MACA0LR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define ETH_MACA0LR_MACA0L ((u32)0xFFFFFFFF) ///< MAC address0 low - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH_MACA1HR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define ETH_MACA1HR_AE_Pos (31) -#define ETH_MACA1HR_AE (0x01U << ETH_MACA1HR_AE_Pos) ///< Address enable -#define ETH_MACA1HR_SA_Pos (30) -#define ETH_MACA1HR_SA (0x01U << ETH_MACA1HR_SA_Pos) ///< Source address -#define ETH_MACA1HR_MBC_Pos (24) -#define ETH_MACA1HR_MBC (0x3FU << ETH_MACA1HR_MBC_Pos) ///< Mask byte control: bits to mask for comparison of the MAC Address bytes -#define ETH_MACA1HR_MBC_HBits15_8 (0x20U << ETH_MACA1HR_MBC_Pos) ///< Mask MAC Address high reg bits [15:8] -#define ETH_MACA1HR_MBC_HBits7_0 (0x10U << ETH_MACA1HR_MBC_Pos) ///< Mask MAC Address high reg bits [7:0] -#define ETH_MACA1HR_MBC_LBits31_24 (0x08U << ETH_MACA1HR_MBC_Pos) ///< Mask MAC Address low reg bits [31:24] -#define ETH_MACA1HR_MBC_LBits23_16 (0x04U << ETH_MACA1HR_MBC_Pos) ///< Mask MAC Address low reg bits [23:16] -#define ETH_MACA1HR_MBC_LBits15_8 (0x02U << ETH_MACA1HR_MBC_Pos) ///< Mask MAC Address low reg bits [15:8] -#define ETH_MACA1HR_MBC_LBits7_0 (0x00U << ETH_MACA1HR_MBC_Pos) ///< Mask MAC Address low reg bits [7:0] -#define ETH_MACA1HR_MACA1H_Pos (0) -#define ETH_MACA1HR_MACA1H (0x0000FFFFU << ETH_MACA1HR_MACA1H_Pos) ///< MAC address1 high - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH_MACA1LR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define ETH_MACA1LR_MACA1L (0xFFFFFFFFU) ///< MAC address1 low - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH_MACA2HR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define ETH_MACA2HR_AE_Pos (31) -#define ETH_MACA2HR_AE (0x01U << ETH_MACA2HR_AE_Pos) ///< Address enable -#define ETH_MACA2HR_SA_Pos (30) -#define ETH_MACA2HR_SA (0x01U << ETH_MACA2HR_SA_Pos) ///< Source address -#define ETH_MACA2HR_MBC_Pos (24) -#define ETH_MACA2HR_MBC (0x3FU << ETH_MACA2HR_MBC_Pos) ///< Mask byte control: bits to mask for comparison of the MAC Address bytes -#define ETH_MACA2HR_MBC_HBits15_8 (0x20U << ETH_MACA2HR_MBC_Pos) ///< Mask MAC Address high reg bits [15:8] -#define ETH_MACA2HR_MBC_HBits7_0 (0x10U << ETH_MACA2HR_MBC_Pos) ///< Mask MAC Address high reg bits [7:0] -#define ETH_MACA2HR_MBC_LBits31_24 (0x08U << ETH_MACA2HR_MBC_Pos) ///< Mask MAC Address low reg bits [31:24] -#define ETH_MACA2HR_MBC_LBits23_16 (0x04U << ETH_MACA2HR_MBC_Pos) ///< Mask MAC Address low reg bits [23:16] -#define ETH_MACA2HR_MBC_LBits15_8 (0x02U << ETH_MACA2HR_MBC_Pos) ///< Mask MAC Address low reg bits [15:8] -#define ETH_MACA2HR_MBC_LBits7_0 (0x00U << ETH_MACA2HR_MBC_Pos) ///< Mask MAC Address low reg bits [7:0] -#define ETH_MACA2HR_MACA2H_Pos (0) -#define ETH_MACA2HR_MACA2H (0x0000FFFFU << ETH_MACA2HR_MACA2H_Pos) ///< MAC address2 high - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH_MACA2LR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define ETH_MACA2LR_MACA2L (0xFFFFFFFFU) ///< MAC address2 low -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH_MACANCR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define ETH_MACANCR_LR_Pos (17) -#define ETH_MACANCR_LR (0x01U << ETH_MACANCR_LR_Pos) ///< Lock to Reference -#define ETH_MACANCR_ECD_Pos (16) -#define ETH_MACANCR_ECD (0x01U << ETH_MACANCR_ECD_Pos) ///< Enable Comma Detect -#define ETH_MACANCR_ELE_Pos (14) -#define ETH_MACANCR_ELE (0x01U << ETH_MACANCR_ELE_Pos) ///< External Loopback Enable -#define ETH_MACANCR_ANE_Pos (12) -#define ETH_MACANCR_ANE (0x01U << ETH_MACANCR_ANE_Pos) ///< Auto-Negotiation Enable -#define ETH_MACANCR_RAN_Pos (9) -#define ETH_MACANCR_RAN (0x01U << ETH_MACANCR_RAN_Pos) ///< Restart Auto-Negotiation -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH_MACANSR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define ETH_MACANSR_ES_Pos (8) -#define ETH_MACANSR_ES (0x01U << ETH_MACANSR_ES_Pos) ///< Extended Status -#define ETH_MACANSR_ANC_Pos (5) -#define ETH_MACANSR_ANC (0x01U << ETH_MACANSR_ANC_Pos) ///< Auto-Negotiation Complete -#define ETH_MACANSR_ANA_Pos (3) -#define ETH_MACANSR_ANA (0x01U << ETH_MACANSR_ANA_Pos) ///< Auto-Negotiation Ability -#define ETH_MACANSR_LS_Pos (2) -#define ETH_MACANSR_LS (0x01U << ETH_MACANSR_LS_Pos) ///< Link Status -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH_MACANAR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define ETH_MACANAR_NP_Pos (15) -#define ETH_MACANAR_NP (0x01U << ETH_MACANAR_NP_Pos) ///< Next Page Support -#define ETH_MACANAR_RFE_Pos (12) -#define ETH_MACANAR_RFE (0x01U << ETH_MACANAR_RFE_Pos) ///< Remote Fault Encoding -#define ETH_MACANAR_PSE_Pos (7) -#define ETH_MACANAR_PSE (0x01U << ETH_MACANAR_PSE_Pos) ///< Pause Encoding -#define ETH_MACANAR_HD_Pos (6) -#define ETH_MACANAR_HD (0x01U << ETH_MACANAR_HD_Pos) ///< support Half-Duplex -#define ETH_MACANAR_FD_Pos (5) -#define ETH_MACANAR_FD (0x01U << ETH_MACANAR_FD_Pos) ///< support Full-Durplex -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH_MACANLPAR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define ETH_MACANLPAR_NP_Pos (15) -#define ETH_MACANLPAR_NP (0x01U << ETH_MACANLPAR_NP_Pos) ///< Next Page Support -#define ETH_MACANLPAR_ACK_Pos (14) -#define ETH_MACANLPAR_ACK (0x01U << ETH_MACANLPAR_ACK_Pos) ///< Acknowledge -#define ETH_MACANLPAR_RFE_Pos (12) -#define ETH_MACANLPAR_RFE (0x01U << ETH_MACANLPAR_RFE_Pos) ///< Remote Fault Encoding -#define ETH_MACANLPAR_PSE_Pos (7) -#define ETH_MACANLPAR_PSE (0x01U << ETH_MACANLPAR_PSE_Pos) ///< Pause Encoding -#define ETH_MACANLPAR_HD_Pos (6) -#define ETH_MACANLPAR_HD (0x01U << ETH_MACANLPAR_HD_Pos) ///< support Half-Duplex -#define ETH_MACANLPAR_FD_Pos (5) -#define ETH_MACANLPAR_FD (0x01U << ETH_MACANLPAR_FD_Pos) ///< support Full-Durplex -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH_MACANER Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define ETH_MACANER_NPA_Pos (2) -#define ETH_MACANER_NPA (0x01U << ETH_MACANER_NPA_Pos) ///< Next Page Ability -#define ETH_MACANER_NPR_Pos (1) -#define ETH_MACANER_NPR (0x01U << ETH_MACANER_NPR_Pos) ///< New Page Received -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH_MACTBIER Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define ETH_MACTBIER_GFD_Pos (15) -#define ETH_MACTBIER_GFD (0x01U << ETH_MACTBIER_GFD_Pos) ///< 1000BASE-X Full-Duplex Capable -#define ETH_MACTBIER_GHD_Pos (14) -#define ETH_MACTBIER_GHD (0x01U << ETH_MACTBIER_GHD_Pos) ///< 1000BASE-X Half-Duplex Capable -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH_MACMIISR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define ETH_MACMIISR_LS_Pos (3) -#define ETH_MACMIISR_LS (0x01U << ETH_MACMIISR_LS_Pos) ///< Link Status -#define ETH_MACMIISR_LSP_Pos (1) -#define ETH_MACMIISR_LSP_2_5 (0x00U << ETH_MACMIISR_LSP_Pos) ///< Link Speed 2.5 MHz -#define ETH_MACMIISR_LSP_25 (0x01U << ETH_MACMIISR_LSP_Pos) ///< Link Speed 25 MHz -#define ETH_MACMIISR_LSP_125 (0x02U << ETH_MACMIISR_LSP_Pos) ///< Link Speed 125 MHz -#define ETH_MACMIISR_LM_Pos (0) -#define ETH_MACMIISR_LM (0x01U << ETH_MACMIISR_LM_Pos) ///< Link Mode : Full-Duplex Capable - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH_MMCCR Registers bits definition -//////////////////////////////////////////////////////////////////////////////// -#define ETH_MMCCR_MCFHP ((u32)0x00000020) ///< MMC counter Full-Half preset -#define ETH_MMCCR_MCP ((u32)0x00000010) ///< MMC counter preset -#define ETH_MMCCR_MCF ((u32)0x00000008) ///< MMC Counter Freeze -#define ETH_MMCCR_ROR_Pos (2) -#define ETH_MMCCR_ROR (0x01U << ETH_MMCCR_ROR_Pos) ///< Reset on Read -#define ETH_MMCCR_CSR_Pos (1) -#define ETH_MMCCR_CSR (0x01U << ETH_MMCCR_CSR_Pos) ///< Counter Stop Rollover -#define ETH_MMCCR_CR_Pos (0) -#define ETH_MMCCR_CR (0x01U << ETH_MMCCR_CR_Pos) ///< Counters Reset - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH_MMCRIR Registers bits definition -//////////////////////////////////////////////////////////////////////////////// -#define ETH_MMCRIR_RGUF_Pos (17) -#define ETH_MMCRIR_RGUFS (0x01U << ETH_MMCRIR_RGUF_Pos) ///< Set when Rx good unicast frames counter reaches half the maximum value -#define ETH_MMCRIR_RFAES_Pos (6) -#define ETH_MMCRIR_RFAES (0x01U << ETH_MMCRIR_RFAES_Pos) ///< Set when Rx alignment error counter reaches half the maximum value -#define ETH_MMCRIR_RFCES_Pos (5) -#define ETH_MMCRIR_RFCES (0x01U << ETH_MMCRIR_RFCES_Pos) ///< Set when Rx crc error counter reaches half the maximum value - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH_MMCTIR Registers bits definition -//////////////////////////////////////////////////////////////////////////////// -#define ETH_MMCTIR_TGFS_Pos (21) -#define ETH_MMCTIR_TGFS (0x01U << ETH_MMCTIR_TGFS_Pos) ///< Set when Tx good frame count counter reaches half the maximum value -#define ETH_MMCTIR_TGFMSCS_Pos (15) -#define ETH_MMCTIR_TGFMSCS (0x01U << ETH_MMCTIR_TGFMSCS_Pos) ///< Set when Tx good multi col counter reaches half the maximum value -#define ETH_MMCTIR_TGFSCS_Pos (14) -#define ETH_MMCTIR_TGFSCS (0x01U << ETH_MMCTIR_TGFSCS_Pos) ///< Set when Tx good single col counter reaches half the maximum value - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH_MMCRIMR Registers bits definition -//////////////////////////////////////////////////////////////////////////////// -#define ETH_MMCRIMR_RGUFM_Pos (17) -#define ETH_MMCRIMR_RGUFM (0x01U << ETH_MMCRIMR_RGUFM_Pos) ///< Mask the interrupt when Rx good unicast frames counter reaches half the maximum value -#define ETH_MMCRIMR_RFAEM_Pos (6) -#define ETH_MMCRIMR_RFAEM (0x01U << ETH_MMCRIMR_RFAEM_Pos) ///< Mask the interrupt when when Rx alignment error counter reaches half the maximum value -#define ETH_MMCRIMR_RFCEM_Pos (5) -#define ETH_MMCRIMR_RFCEM (0x01U << ETH_MMCRIMR_RFCEM_Pos) ///< Mask the interrupt when Rx crc error counter reaches half the maximum value - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH_MMCTIMR Registers bits definition -//////////////////////////////////////////////////////////////////////////////// -#define ETH_MMCTIMR_TGFM_Pos (21) -#define ETH_MMCTIMR_TGFM (0x01U << ETH_MMCTIMR_TGFM_Pos) ///< Mask the interrupt when Tx good frame count counter reaches half the maximum value -#define ETH_MMCTIMR_TGFMSCM_Pos (15) -#define ETH_MMCTIMR_TGFMSCM (0x01U << ETH_MMCTIMR_TGFMSCM_Pos) ///< Mask the interrupt when Tx good multi col counter reaches half the maximum value -#define ETH_MMCTIMR_TGFSCM_Pos (14) -#define ETH_MMCTIMR_TGFSCM (0x01U << ETH_MMCTIMR_TGFSCM_Pos) ///< Mask the interrupt when Tx good single col counter reaches half the maximum value - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH_MMCTGFSCCR Registers bits definition -//////////////////////////////////////////////////////////////////////////////// -#define ETH_MMCTGFSCCR_TGFSCC (0xFFFFFFFFU) ///< Number of successfully transmitted frames after a single collision in Half-duplex mode. -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH_MMCTGFMSCCR Registers bits definition -//////////////////////////////////////////////////////////////////////////////// -#define ETH_MMCTGFMSCCR_TGFMSCC (0xFFFFFFFFU) ///< Number of successfully transmitted frames after more than a single collision in Half-duplex mode. -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH_MMCTGFCR Registers bits definition -//////////////////////////////////////////////////////////////////////////////// -#define ETH_MMCTGFCR_TGFC (0xFFFFFFFFU) ///< Number of good frames transmitted. -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH_MMCRFCECR Registers bits definition -//////////////////////////////////////////////////////////////////////////////// -#define ETH_MMCRFCECR_RFCEC (0xFFFFFFFFU) ///< Number of frames received with CRC error. -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH_MMCRFAECR Registers bits definition -//////////////////////////////////////////////////////////////////////////////// -#define ETH_MMCRFAECR_RFAEC (0xFFFFFFFFU) ///< Number of frames received with alignment (dribble) error -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH_MMCRGUFCR Registers bits definition -//////////////////////////////////////////////////////////////////////////////// -#define ETH_MMCRGUFCR_RGUFC (0xFFFFFFFFU) ///< Number of good unicast frames received. -/// @brief ETH_DMABMR Registers bits definition -//////////////////////////////////////////////////////////////////////////////// -#define ETH_DMABMR_FB_Pos (16) -#define ETH_DMABMR_FB (0x01U << ETH_DMABMR_FB_Pos) ///< Fixed Burst -#define ETH_DMABMR_RTPR_Pos (14) -#define ETH_DMABMR_RTPR (0x03U << ETH_DMABMR_RTPR_Pos) ///< Rx Tx priority ratio -#define ETH_DMABMR_RTPR_1_1 (0x00U << ETH_DMABMR_RTPR_Pos) ///< Rx Tx priority ratio -#define ETH_DMABMR_RTPR_2_1 (0x01U << ETH_DMABMR_RTPR_Pos) ///< Rx Tx priority ratio -#define ETH_DMABMR_RTPR_3_1 (0x02U << ETH_DMABMR_RTPR_Pos) ///< Rx Tx priority ratio -#define ETH_DMABMR_RTPR_4_1 (0x03U << ETH_DMABMR_RTPR_Pos) ///< Rx Tx priority ratio -#define ETH_DMABMR_PBL_Pos (8) -#define ETH_DMABMR_PBL (0x3FU<< ETH_DMABMR_PBL_Pos) //< Programmable burst length -#define ETH_DMABMR_PBL_1Beat (0x01U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 -#define ETH_DMABMR_PBL_2Beat (0x02U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 -#define ETH_DMABMR_PBL_4Beat (0x04U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 -#define ETH_DMABMR_PBL_8Beat (0x08U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 -#define ETH_DMABMR_PBL_16Beat (0x10U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 -#define ETH_DMABMR_PBL_32Beat (0x20U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 -#define ETH_DMABMR_PBL_4xPBL_4Beat (0x10001U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 -#define ETH_DMABMR_PBL_4xPBL_8Beat (0x10002U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 -#define ETH_DMABMR_PBL_4xPBL_16Beat (0x10004U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 -#define ETH_DMABMR_PBL_4xPBL_32Beat (0x10008U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 -#define ETH_DMABMR_PBL_4xPBL_64Beat (0x10010U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 -#define ETH_DMABMR_PBL_4xPBL_128Beat (0x10020U << ETH_DMABMR_PBL_Pos) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 - -#define ETH_DMABMR_DSL_Pos (2) -#define ETH_DMABMR_DSL (0x01U << ETH_DMABMR_DSL_Pos) ///< Descriptor Skip Length -#define ETH_DMABMR_DA_Pos (1) -#define ETH_DMABMR_DA (0x1FU << ETH_DMABMR_DA_Pos) ///< DMA arbitration scheme -#define ETH_DMABMR_SR_Pos (0) -#define ETH_DMABMR_SR (0x01U << ETH_DMABMR_SR_Pos) ///< Software reset - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH_DMATPDR Registers bits definition -//////////////////////////////////////////////////////////////////////////////// -#define ETH_DMATPDR_TPD (0xFFFFFFFFU) ///< Transmit poll demand -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH_DMARPDR Registers bits definition -//////////////////////////////////////////////////////////////////////////////// -#define ETH_DMARPDR_RPD (0xFFFFFFFFU) ///< Receive poll demand -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH_DMARDLAR Registers bits definition -//////////////////////////////////////////////////////////////////////////////// -#define ETH_DMARDLAR_SRL (0xFFFFFFFFU) ///< Start of receive list -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH_DMATDLAR Registers bits definition -//////////////////////////////////////////////////////////////////////////////// -#define ETH_DMATDLAR_STL (0xFFFFFFFFU) ///< Start of transmit list - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH_DMASR Registers bits definition -//////////////////////////////////////////////////////////////////////////////// -#define ETH_DMASR_PMTS_Pos (28) -#define ETH_DMASR_PMTS (0x01U << ETH_DMASR_PMTS_Pos) ///< PMT status -#define ETH_DMASR_MMCS_Pos (27) -#define ETH_DMASR_MMCS (0x01U << ETH_DMASR_MMCS_Pos) ///< MMC status -#define ETH_DMASR_LIS_Pos (26) -#define ETH_DMASR_LIS (0x01U << ETH_DMASR_LIS_Pos) ///< GMAC Line interface Status - -#define ETH_DMASR_EBS_Pos (23) -#define ETH_DMASR_EBS (0x07U << ETH_DMASR_EBS_Pos) ///< Error bits status -#define ETH_DMASR_EBS_DescAccess (0x04U << ETH_DMASR_EBS_Pos) ///< Error bits 0-data buffer, 1-desc. access -#define ETH_DMASR_EBS_ReadTransf (0x02U << ETH_DMASR_EBS_Pos) ///< Error bits 0-write trnsf, 1-read transfr -#define ETH_DMASR_EBS_DataTransfTx (0x01U << ETH_DMASR_EBS_Pos) ///< Error bits 0-Rx DMA, 1-Tx DMA -#define ETH_DMASR_TPS_Pos (20) -#define ETH_DMASR_TPS (0x007U << ETH_DMASR_TPS_Pos) ///< Transmit process state -#define ETH_DMASR_TPS_Stopped (0x000U << ETH_DMASR_TPS_Pos) ///< Stopped - Reset or Stop Tx Command issued -#define ETH_DMASR_TPS_Fetching (0x001U << ETH_DMASR_TPS_Pos) ///< Running - fetching the Tx descriptor -#define ETH_DMASR_TPS_Waiting (0x002U << ETH_DMASR_TPS_Pos) ///< Running - waiting for status -#define ETH_DMASR_TPS_Reading (0x003U << ETH_DMASR_TPS_Pos) ///< Running - reading the data from host memory -#define ETH_DMASR_TPS_Suspended (0x006U << ETH_DMASR_TPS_Pos) ///< Suspended - Tx Descriptor unavailabe -#define ETH_DMASR_TPS_Closing (0x007U << ETH_DMASR_TPS_Pos) ///< Running - closing Rx descriptor -#define ETH_DMASR_RPS_Pos (17) -#define ETH_DMASR_RPS (0x07U << ETH_DMASR_RPS_Pos) ///< Receive process state -#define ETH_DMASR_RPS_Stopped (0x00U << ETH_DMASR_RPS_Pos) ///< Stopped - Reset or Stop Rx Command issued -#define ETH_DMASR_RPS_Fetching (0x01U << ETH_DMASR_RPS_Pos) ///< Running - fetching the Rx descriptor -#define ETH_DMASR_RPS_Waiting (0x03U << ETH_DMASR_RPS_Pos) ///< Running - waiting for packet -#define ETH_DMASR_RPS_Suspended (0x04U << ETH_DMASR_RPS_Pos) ///< Suspended - Rx Descriptor unavailable -#define ETH_DMASR_RPS_Closing (0x05U << ETH_DMASR_RPS_Pos) ///< Running - closing descriptor -#define ETH_DMASR_RPS_Queuing (0x07U << ETH_DMASR_RPS_Pos) ///< Running - queuing the recieve frame into host memory -#define ETH_DMASR_NIS_Pos (16) -#define ETH_DMASR_NIS (0x01U << ETH_DMASR_NIS_Pos ) ///< Normal interrupt summary -#define ETH_DMASR_AIS_Pos (15) -#define ETH_DMASR_AIS (0x01U << ETH_DMASR_AIS_Pos ) ///< Abnormal interrupt summary -#define ETH_DMASR_ERS_Pos (14) -#define ETH_DMASR_ERS (0x01U << ETH_DMASR_ERS_Pos ) ///< Early receive status -#define ETH_DMASR_FBES_Pos (13) -#define ETH_DMASR_FBES (0x01U << ETH_DMASR_FBES_Pos) ///< Fatal bus error status -#define ETH_DMASR_ETS_Pos (10) -#define ETH_DMASR_ETS (0x01U << ETH_DMASR_ETS_Pos ) ///< Early transmit status -#define ETH_DMASR_RWTS_Pos (9) -#define ETH_DMASR_RWTS (0x01U << ETH_DMASR_RWTS_Pos) ///< Receive watchdog timeout status -#define ETH_DMASR_RPSS_Pos (8) -#define ETH_DMASR_RPSS (0x01U << ETH_DMASR_RPSS_Pos) ///< Receive process stopped status -#define ETH_DMASR_RBUS_Pos (7) -#define ETH_DMASR_RBUS (0x01U << ETH_DMASR_RBUS_Pos) ///< Receive buffer unavailable status -#define ETH_DMASR_RS_Pos (6) -#define ETH_DMASR_RS (0x01U << ETH_DMASR_RS_Pos ) ///< Receive status -#define ETH_DMASR_TUS_Pos (5) -#define ETH_DMASR_TUS (0x01U << ETH_DMASR_TUS_Pos ) ///< Transmit underflow status -#define ETH_DMASR_ROS_Pos (4) -#define ETH_DMASR_ROS (0x01U << ETH_DMASR_ROS_Pos ) ///< Receive overflow status -#define ETH_DMASR_TJTS_Pos (3) -#define ETH_DMASR_TJTS (0x01U << ETH_DMASR_TJTS_Pos) ///< Transmit jabber timeout status -#define ETH_DMASR_TBUS_Pos (2) -#define ETH_DMASR_TBUS (0x01U << ETH_DMASR_TBUS_Pos) ///< Transmit buffer unavailable status -#define ETH_DMASR_TPSS_Pos (1) -#define ETH_DMASR_TPSS (0x01U << ETH_DMASR_TPSS_Pos) ///< Transmit process stopped status -#define ETH_DMASR_TS_Pos (0) -#define ETH_DMASR_TS (0x01U << ETH_DMASR_TS_Pos ) ///< Transmit status - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH_DMAOMR Registers bits definition -//////////////////////////////////////////////////////////////////////////////// - -#define ETH_DMAOMR_TSF_Pos (21) -#define ETH_DMAOMR_TSF (0x01U << ETH_DMAOMR_TSF_Pos) ///< Transmit store and forward -#define ETH_DMAOMR_FTF_Pos (20) -#define ETH_DMAOMR_FTF (0x01U << ETH_DMAOMR_FTF_Pos) ///< Flush transmit FIFO -#define ETH_DMAOMR_TTC_Pos (14) -#define ETH_DMAOMR_TTC (0x07U << ETH_DMAOMR_TTC_Pos) ///< Transmit threshold control -#define ETH_DMAOMR_TTC_64Bytes (0x00U << ETH_DMAOMR_TTC_Pos) ///< threshold level of the MTL Transmit FIFO is 64 Bytes -#define ETH_DMAOMR_TTC_128Bytes (0x01U << ETH_DMAOMR_TTC_Pos) ///< threshold level of the MTL Transmit FIFO is 128 Bytes -#define ETH_DMAOMR_TTC_192Bytes (0x02U << ETH_DMAOMR_TTC_Pos) ///< threshold level of the MTL Transmit FIFO is 192 Bytes -#define ETH_DMAOMR_TTC_256Bytes (0x03U << ETH_DMAOMR_TTC_Pos) ///< threshold level of the MTL Transmit FIFO is 256 Bytes -#define ETH_DMAOMR_TTC_40Bytes (0x04U << ETH_DMAOMR_TTC_Pos) ///< threshold level of the MTL Transmit FIFO is 40 Bytes -#define ETH_DMAOMR_TTC_32Bytes (0x05U << ETH_DMAOMR_TTC_Pos) ///< threshold level of the MTL Transmit FIFO is 32 Bytes -#define ETH_DMAOMR_TTC_24Bytes (0x06U << ETH_DMAOMR_TTC_Pos) ///< threshold level of the MTL Transmit FIFO is 24 Bytes -#define ETH_DMAOMR_TTC_16Bytes (0x07U << ETH_DMAOMR_TTC_Pos) ///< threshold level of the MTL Transmit FIFO is 16 Bytes -#define ETH_DMAOMR_ST_Pos (13) -#define ETH_DMAOMR_ST (0x01U << ETH_DMAOMR_ST_Pos ) ///< Start/stop transmission command -#define ETH_DMAOMR_RFD_Pos (11) -#define ETH_DMAOMR_RFD1 (0x00U << ETH_DMAOMR_RFD_Pos ) ///< Threshold for failure flow control 1 byte -#define ETH_DMAOMR_RFD2 (0x01U << ETH_DMAOMR_RFD_Pos ) ///< Threshold for failure flow control 2 byte -#define ETH_DMAOMR_RFD3 (0x02U << ETH_DMAOMR_RFD_Pos ) ///< Threshold for failure flow control 3 byte -#define ETH_DMAOMR_RFD4 (0x03U << ETH_DMAOMR_RFD_Pos ) ///< Threshold for failure flow control 4 byte -#define ETH_DMAOMR_RFA_Pos (9) -#define ETH_DMAOMR_RFA1 (0x00U << ETH_DMAOMR_RFA_Pos ) ///< Activate the threshold for flow control 1 byte -#define ETH_DMAOMR_RFA2 (0x01U << ETH_DMAOMR_RFA_Pos ) ///< Activate the threshold for flow control 2 byte -#define ETH_DMAOMR_RFA3 (0x02U << ETH_DMAOMR_RFA_Pos ) ///< Activate the threshold for flow control 3 byte -#define ETH_DMAOMR_RFA4 (0x03U << ETH_DMAOMR_RFA_Pos ) ///< Activate the threshold for flow control 4 byte - -#define ETH_DMAOMR_EFC_Pos (8) -#define ETH_DMAOMR_EFC (0x01U << ETH_DMAOMR_EFC_Pos ) ///< Enable HW Flow Control -#define ETH_DMAOMR_FEF_Pos (7) -#define ETH_DMAOMR_FEF (0x01U << ETH_DMAOMR_FEF_Pos ) ///< Forward error frames -#define ETH_DMAOMR_FUGF_Pos (6) -#define ETH_DMAOMR_FUGF (0x01U << ETH_DMAOMR_FUGF_Pos) ///< Forward undersized good frames -#define ETH_DMAOMR_RTC_Pos (3) -#define ETH_DMAOMR_RTC (0x03U << ETH_DMAOMR_RTC_Pos) ///< receive threshold control -#define ETH_DMAOMR_RTC_64Bytes (0x00U << ETH_DMAOMR_RTC_Pos) ///< threshold level of the MTL Receive FIFO is 64 Bytes -#define ETH_DMAOMR_RTC_32Bytes (0x01U << ETH_DMAOMR_RTC_Pos) ///< threshold level of the MTL Receive FIFO is 32 Bytes -#define ETH_DMAOMR_RTC_96Bytes (0x02U << ETH_DMAOMR_RTC_Pos) ///< threshold level of the MTL Receive FIFO is 96 Bytes -#define ETH_DMAOMR_RTC_128Bytes (0x03U << ETH_DMAOMR_RTC_Pos) ///< threshold level of the MTL Receive FIFO is 128 Bytes -#define ETH_DMAOMR_OSF_Pos (2) -#define ETH_DMAOMR_OSF (0x01U << ETH_DMAOMR_OSF_Pos) ///< operate on second frame -#define ETH_DMAOMR_SR_Pos (1) -#define ETH_DMAOMR_SR (0x01U << ETH_DMAOMR_SR_Pos ) ///< Start/stop receive - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH_DMAIER Registers bits definition -//////////////////////////////////////////////////////////////////////////////// -#define ETH_DMAIER_NISE_Pos (16) -#define ETH_DMAIER_NISE (0x01U << ETH_DMAIER_NISE_Pos ) ///< Normal interrupt summary enable -#define ETH_DMAIER_AISE_Pos (15) -#define ETH_DMAIER_AISE (0x01U << ETH_DMAIER_AISE_Pos ) ///< Abnormal interrupt summary enable -#define ETH_DMAIER_ERIE_Pos (14) -#define ETH_DMAIER_ERIE (0x01U << ETH_DMAIER_ERIE_Pos ) ///< Early receive interrupt enable -#define ETH_DMAIER_FBEIE_Pos (13) -#define ETH_DMAIER_FBEIE (0x01U << ETH_DMAIER_FBEIE_Pos) ///< Fatal bus error interrupt enable -#define ETH_DMAIER_ETIE_Pos (10) -#define ETH_DMAIER_ETIE (0x01U << ETH_DMAIER_ETIE_Pos ) ///< Early transmit interrupt enable -#define ETH_DMAIER_RWTIE_Pos (9) -#define ETH_DMAIER_RWTIE (0x01U << ETH_DMAIER_RWTIE_Pos) ///< Receive watchdog timeout interrupt enable -#define ETH_DMAIER_RPSIE_Pos (8) -#define ETH_DMAIER_RPSIE (0x01U << ETH_DMAIER_RPSIE_Pos) ///< Receive process stopped interrupt enable -#define ETH_DMAIER_RBUIE_Pos (7) -#define ETH_DMAIER_RBUIE (0x01U << ETH_DMAIER_RBUIE_Pos) ///< Receive buffer unavailable interrupt enable -#define ETH_DMAIER_RIE_Pos (6) -#define ETH_DMAIER_RIE (0x01U << ETH_DMAIER_RIE_Pos ) ///< Receive interrupt enable -#define ETH_DMAIER_TUIE_Pos (5) -#define ETH_DMAIER_TUIE (0x01U << ETH_DMAIER_TUIE_Pos ) ///< Transmit Underflow interrupt enable -#define ETH_DMAIER_ROIE_Pos (4) -#define ETH_DMAIER_ROIE (0x01U << ETH_DMAIER_ROIE_Pos ) ///< Receive Overflow interrupt enable -#define ETH_DMAIER_TJTIE_Pos (3) -#define ETH_DMAIER_TJTIE (0x01U << ETH_DMAIER_TJTIE_Pos) ///< Transmit jabber timeout interrupt enable -#define ETH_DMAIER_TBUIE_Pos (2) -#define ETH_DMAIER_TBUIE (0x01U << ETH_DMAIER_TBUIE_Pos) ///< Transmit buffer unavailable interrupt enable -#define ETH_DMAIER_TPSIE_Pos (1) -#define ETH_DMAIER_TPSIE (0x01U << ETH_DMAIER_TPSIE_Pos) ///< Transmit process stopped interrupt enable -#define ETH_DMAIER_TIE_Pos (0) -#define ETH_DMAIER_TIE (0x01U << ETH_DMAIER_TIE_Pos ) ///< Transmit interrupt enable -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH_DMAMFBOCR Registers bits definition -//////////////////////////////////////////////////////////////////////////////// -#define ETH_DMAMFBOCR_OFOC_Pos (28) -#define ETH_DMAMFBOCR_OFOC (0x01U << ETH_DMAMFBOCR_OFOC_Pos) ///< Overflow bit for FIFO overflow counter - -#define ETH_DMAMFBOCR_MFA_Pos (17) -#define ETH_DMAMFBOCR_MFA (0x7FFU << ETH_DMAMFBOCR_MFA_Pos ) ///< Number of frames missed by the application - -#define ETH_DMAMFBOCR_OMFC_Pos (16) -#define ETH_DMAMFBOCR_OMFC (0x01U << ETH_DMAMFBOCR_OMFC_Pos) ///< Overflow bit for missed frame counter - -#define ETH_DMAMFBOCR_MFC_Pos (0) -#define ETH_DMAMFBOCR_MFC (0xFFFFU << ETH_DMAMFBOCR_MFC_Pos ) ///< Number of frames missed by the controller - -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH_DMACHTDR Registers bits definition -//////////////////////////////////////////////////////////////////////////////// -#define ETH_DMACHTDR_HTDAP (0xFFFFFFFFU) ///< Host transmit descriptor address pointer -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH_DMACHRDR Registers bits definition -//////////////////////////////////////////////////////////////////////////////// -#define ETH_DMACHRDR_HRDAP (0xFFFFFFFFU) ///< Host receive descriptor address pointer -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH_DMACHTBAR Registers bits definition -//////////////////////////////////////////////////////////////////////////////// -#define ETH_DMACHTBAR_HTBAP (0xFFFFFFFFU) ///< Host transmit buffer address pointer -//////////////////////////////////////////////////////////////////////////////// -/// @brief ETH_DMACHRBAR Registers bits definition -//////////////////////////////////////////////////////////////////////////////// -#define ETH_DMACHRBAR_HRBAP (0xFFFFFFFFU) ///< Host receive buffer address pointer - - -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -#endif -//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_exti.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_exti.h deleted file mode 100644 index 608c12bc2..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_exti.h +++ /dev/null @@ -1,544 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file reg_exti.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF -/// MM32 FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion - -#ifndef __REG_EXTI_H -#define __REG_EXTI_H - -// Files includes - -#include -#include -#include "types.h" - - - - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - - - - - - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief EXTI Base Address Definition -//////////////////////////////////////////////////////////////////////////////// -#define EXTI_BASE (APB2PERIPH_BASE + 0x0000) ///< Base Address: 0x40010000 - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief EXTI Registers Structure Definition -//////////////////////////////////////////////////////////////////////////////// -typedef struct { - __IO u32 CFGR; ///< configuration register, offset: 0x00 - u32 Reserved; ///< Reserved offset: 0x04 - __IO u32 CR[4]; ///< External interrupt configuration register, offset: 0x08 - 0x14 - __IO u32 CFGR2; ///< configuration register offset: 0x18 - __IO u32 PDETCSR; ///< Power detection configuration status register offset: 0x1C - __IO u32 VOSDLY; ///< VOS delay time offset: 0x20 - u32 Reserved1[0x100 - 0x09]; ///< Reserved space - __IO u32 IMR; ///< Interrupt Mask Register offset: 0x00 + 0x400 - __IO u32 EMR; ///< Event Mask Register offset: 0x04 + 0x400 - __IO u32 RTSR; ///< Rising Trigger Status Register offset: 0x08 + 0x400 - __IO u32 FTSR; ///< Falling Trigger Status Register offset: 0x0C + 0x400 - __IO u32 SWIER; ///< Software Interrupt Enable Register offset: 0x10 + 0x400 - __IO u32 PR; ///< Pending Register offset: 0x14 + 0x400 -} EXTI_TypeDef; - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief EXTI type pointer Definition -//////////////////////////////////////////////////////////////////////////////// -#define EXTI ((EXTI_TypeDef*) EXTI_BASE) - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief EXTI_CFGR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define EXTI_CFGR_MEMMODE_Pos (0) -#define EXTI_CFGR_MEMMODE (0x03U << EXTI_CFGR_MEMMODE_Pos) ///< EXTI_Memory Remap Config -#define EXTI_CFGR_MEMMODE_0 (0x01U << EXTI_CFGR_MEMMODE_Pos) ///< EXTI_Memory Remap Config Bit 0 -#define EXTI_CFGR_MEMMODE_1 (0x02U << EXTI_CFGR_MEMMODE_Pos) ///< EXTI_Memory Remap Config Bit 1 -#define EXTI_CFGR_FLASH_MEMORY (0x00U << EXTI_CFGR_MEMMODE_Pos) ///< EXTI_Memory Remap Config Mode 0 -#define EXTI_CFGR_SYSTEM_MEMORY (0x01U << EXTI_CFGR_MEMMODE_Pos) ///< EXTI_Memory Remap Config Mode 1 -#define EXTI_CFGR_SRAM_MEMORY (0x03U << EXTI_CFGR_MEMMODE_Pos) ///< EXTI_Memory Remap Config Mode 3 - - -#define EXTI_CFGR_FC_SYNCEN_Pos (27) -#define EXTI_CFGR_FC_SYNCEN (0x01U << EXTI_CFGR_FC_SYNCEN_Pos) ///< FSMC synchronization enable -#define EXTI_CFGR_FC_ODATAEN_Pos (28) -#define EXTI_CFGR_FC_ODATAEN (0x01U << EXTI_CFGR_FC_ODATAEN_Pos) ///< FSMC Only used as data pin -#define EXTI_CFGR_MODESEL_Pos (29) ///< FSMC mode selection -#define EXTI_CFGR_MODESEL0 (0x00U << EXTI_CFGR_MODESEL0_Pos) ///< Compatible with 8080 protocol interface -#define EXTI_CFGR_MODESEL1 (0x01U << EXTI_CFGR_MODESEL1_Pos) ///< Compatible with NOR FLASH protocol interface - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief EXTI_CR1 Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define EXTI_CR1_EXTI0_Pos (0) -#define EXTI_CR1_EXTI0 (0x0FU << EXTI_CR1_EXTI0_Pos) ///< EXTI 0 configuration -#define EXTI_CR1_EXTI0_PA (0x00U << EXTI_CR1_EXTI0_Pos) ///< PA[0] pin -#define EXTI_CR1_EXTI0_PB (0x01U << EXTI_CR1_EXTI0_Pos) ///< PB[0] pin -#define EXTI_CR1_EXTI0_PC (0x02U << EXTI_CR1_EXTI0_Pos) ///< PC[0] pin -#define EXTI_CR1_EXTI0_PD (0x03U << EXTI_CR1_EXTI0_Pos) ///< PD[0] pin - -#define EXTI_CR1_EXTI1_Pos (4) -#define EXTI_CR1_EXTI1 (0x0FU << EXTI_CR1_EXTI1_Pos) ///< EXTI 1 configuration -#define EXTI_CR1_EXTI1_PA (0x00U << EXTI_CR1_EXTI1_Pos) ///< PA[1] pin -#define EXTI_CR1_EXTI1_PB (0x01U << EXTI_CR1_EXTI1_Pos) ///< PB[1] pin -#define EXTI_CR1_EXTI1_PC (0x02U << EXTI_CR1_EXTI1_Pos) ///< PC[1] pin -#define EXTI_CR1_EXTI1_PD (0x03U << EXTI_CR1_EXTI1_Pos) ///< PD[1] pin - -#define EXTI_CR1_EXTI2_Pos (8) -#define EXTI_CR1_EXTI2 (0x0FU << EXTI_CR1_EXTI2_Pos) ///< EXTI 2 configuration -#define EXTI_CR1_EXTI2_PA (0x00U << EXTI_CR1_EXTI2_Pos) ///< PA[2] pin -#define EXTI_CR1_EXTI2_PB (0x01U << EXTI_CR1_EXTI2_Pos) ///< PB[2] pin -#define EXTI_CR1_EXTI2_PC (0x02U << EXTI_CR1_EXTI2_Pos) ///< PC[2] pin -#define EXTI_CR1_EXTI2_PD (0x03U << EXTI_CR1_EXTI2_Pos) ///< PD[2] pin - -#define EXTI_CR1_EXTI3_Pos (12) -#define EXTI_CR1_EXTI3 (0x0FU << EXTI_CR1_EXTI3_Pos) ///< EXTI 3 configuration -#define EXTI_CR1_EXTI3_PA (0x00U << EXTI_CR1_EXTI3_Pos) ///< PA[3] pin -#define EXTI_CR1_EXTI3_PB (0x01U << EXTI_CR1_EXTI3_Pos) ///< PB[3] pin -#define EXTI_CR1_EXTI3_PC (0x02U << EXTI_CR1_EXTI3_Pos) ///< PC[3] pin -#define EXTI_CR1_EXTI3_PD (0x03U << EXTI_CR1_EXTI3_Pos) ///< PD[3] pin - -//////////////////////////////////////////////////////////////////////////////// -/// @brief EXTI_CR2 Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define EXTI_CR2_EXTI4_Pos (0) -#define EXTI_CR2_EXTI4 (0x0FU << EXTI_CR2_EXTI4_Pos) ///< EXTI 4 configuration -#define EXTI_CR2_EXTI4_PA (0x00U << EXTI_CR2_EXTI4_Pos) ///< PA[4] pin -#define EXTI_CR2_EXTI4_PB (0x01U << EXTI_CR2_EXTI4_Pos) ///< PB[4] pin -#define EXTI_CR2_EXTI4_PC (0x02U << EXTI_CR2_EXTI4_Pos) ///< PC[4] pin -#define EXTI_CR2_EXTI4_PD (0x03U << EXTI_CR2_EXTI4_Pos) ///< PD[4] pin - -#define EXTI_CR2_EXTI5_Pos (4) -#define EXTI_CR2_EXTI5 (0x0FU << EXTI_CR2_EXTI5_Pos) ///< EXTI 5 configuration -#define EXTI_CR2_EXTI5_PA (0x00U << EXTI_CR2_EXTI5_Pos) ///< PA[5] pin -#define EXTI_CR2_EXTI5_PB (0x01U << EXTI_CR2_EXTI5_Pos) ///< PB[5] pin -#define EXTI_CR2_EXTI5_PC (0x02U << EXTI_CR2_EXTI5_Pos) ///< PC[5] pin -#define EXTI_CR2_EXTI5_PD (0x03U << EXTI_CR2_EXTI5_Pos) ///< PD[5] pin - -#define EXTI_CR2_EXTI6_Pos (8) -#define EXTI_CR2_EXTI6 (0x0FU << EXTI_CR2_EXTI6_Pos) ///< EXTI 6 configuration -#define EXTI_CR2_EXTI6_PA (0x00U << EXTI_CR2_EXTI6_Pos) ///< PA[6] pin -#define EXTI_CR2_EXTI6_PB (0x01U << EXTI_CR2_EXTI6_Pos) ///< PB[6] pin -#define EXTI_CR2_EXTI6_PC (0x02U << EXTI_CR2_EXTI6_Pos) ///< PC[6] pin -#define EXTI_CR2_EXTI6_PD (0x03U << EXTI_CR2_EXTI6_Pos) ///< PD[6] pin - -#define EXTI_CR2_EXTI7_Pos (12) -#define EXTI_CR2_EXTI7 (0x0FU << EXTI_CR2_EXTI7_Pos) ///< EXTI 7 configuration -#define EXTI_CR2_EXTI7_PA (0x00U << EXTI_CR2_EXTI7_Pos) ///< PA[7] pin -#define EXTI_CR2_EXTI7_PB (0x01U << EXTI_CR2_EXTI7_Pos) ///< PB[7] pin -#define EXTI_CR2_EXTI7_PC (0x02U << EXTI_CR2_EXTI7_Pos) ///< PC[7] pin -#define EXTI_CR2_EXTI7_PD (0x03U << EXTI_CR2_EXTI7_Pos) ///< PD[7] pin - -//////////////////////////////////////////////////////////////////////////////// -/// @brief EXTI_CR3 Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define EXTI_CR3_EXTI8_Pos (0) -#define EXTI_CR3_EXTI8 (0x0FU << EXTI_CR3_EXTI8_Pos) ///< EXTI 8 configuration -#define EXTI_CR3_EXTI8_PA (0x00U << EXTI_CR3_EXTI8_Pos) ///< PA[8] pin -#define EXTI_CR3_EXTI8_PB (0x01U << EXTI_CR3_EXTI8_Pos) ///< PB[8] pin -#define EXTI_CR3_EXTI8_PC (0x02U << EXTI_CR3_EXTI8_Pos) ///< PC[8] pin -#define EXTI_CR3_EXTI8_PD (0x03U << EXTI_CR3_EXTI8_Pos) ///< PD[8] pin - -#define EXTI_CR3_EXTI9_Pos (4) -#define EXTI_CR3_EXTI9 (0x0FU << EXTI_CR3_EXTI9_Pos) ///< EXTI 9 configuration -#define EXTI_CR3_EXTI9_PA (0x00U << EXTI_CR3_EXTI9_Pos) ///< PA[9] pin -#define EXTI_CR3_EXTI9_PB (0x01U << EXTI_CR3_EXTI9_Pos) ///< PB[9] pin -#define EXTI_CR3_EXTI9_PC (0x02U << EXTI_CR3_EXTI9_Pos) ///< PC[9] pin -#define EXTI_CR3_EXTI9_PD (0x03U << EXTI_CR3_EXTI9_Pos) ///< PD[9] pin - -#define EXTI_CR3_EXTI10_Pos (8) -#define EXTI_CR3_EXTI10 (0x0FU << EXTI_CR3_EXTI10_Pos) ///< EXTI 10 configuration -#define EXTI_CR3_EXTI10_PA (0x00U << EXTI_CR3_EXTI10_Pos) ///< PA[10] pin -#define EXTI_CR3_EXTI10_PB (0x01U << EXTI_CR3_EXTI10_Pos) ///< PB[10] pin -#define EXTI_CR3_EXTI10_PC (0x02U << EXTI_CR3_EXTI10_Pos) ///< PC[10] pin -#define EXTI_CR3_EXTI10_PD (0x03U << EXTI_CR3_EXTI10_Pos) ///< PD[10] pin - -#define EXTI_CR3_EXTI11_Pos (12) -#define EXTI_CR3_EXTI11 (0x0FU << EXTI_CR3_EXTI11_Pos) ///< EXTI 11 configuration -#define EXTI_CR3_EXTI11_PA (0x00U << EXTI_CR3_EXTI11_Pos) ///< PA[11] pin -#define EXTI_CR3_EXTI11_PB (0x01U << EXTI_CR3_EXTI11_Pos) ///< PB[11] pin -#define EXTI_CR3_EXTI11_PC (0x02U << EXTI_CR3_EXTI11_Pos) ///< PC[11] pin -#define EXTI_CR3_EXTI11_PD (0x03U << EXTI_CR3_EXTI11_Pos) ///< PD[11] pin - -//////////////////////////////////////////////////////////////////////////////// -/// @brief EXTI_CR4 Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define EXTI_CR4_EXTI12_Pos (0) -#define EXTI_CR4_EXTI12 (0x0FU << EXTI_CR4_EXTI12_Pos) ///< EXTI 12 configuration -#define EXTI_CR4_EXTI12_PA (0x00U << EXTI_CR4_EXTI12_Pos) ///< PA[12] pin -#define EXTI_CR4_EXTI12_PB (0x01U << EXTI_CR4_EXTI12_Pos) ///< PB[12] pin -#define EXTI_CR4_EXTI12_PC (0x02U << EXTI_CR4_EXTI12_Pos) ///< PC[12] pin -#define EXTI_CR4_EXTI12_PD (0x03U << EXTI_CR4_EXTI12_Pos) ///< PD[12] pin - -#define EXTI_CR4_EXTI13_Pos (4) -#define EXTI_CR4_EXTI13 (0x0FU << EXTI_CR4_EXTI13_Pos) ///< EXTI 13 configuration -#define EXTI_CR4_EXTI13_PA (0x00U << EXTI_CR4_EXTI13_Pos) ///< PA[13] pin -#define EXTI_CR4_EXTI13_PB (0x01U << EXTI_CR4_EXTI13_Pos) ///< PB[13] pin -#define EXTI_CR4_EXTI13_PC (0x02U << EXTI_CR4_EXTI13_Pos) ///< PC[13] pin -#define EXTI_CR4_EXTI13_PD (0x03U << EXTI_CR4_EXTI13_Pos) ///< PD[13] pin - -#define EXTI_CR4_EXTI14_Pos (8) -#define EXTI_CR4_EXTI14 (0x0FU << EXTI_CR4_EXTI14_Pos) ///< EXTI 14 configuration -#define EXTI_CR4_EXTI14_PA (0x00U << EXTI_CR4_EXTI14_Pos) ///< PA[14] pin -#define EXTI_CR4_EXTI14_PB (0x01U << EXTI_CR4_EXTI14_Pos) ///< PB[14] pin -#define EXTI_CR4_EXTI14_PC (0x02U << EXTI_CR4_EXTI14_Pos) ///< PC[14] pin -#define EXTI_CR4_EXTI14_PD (0x03U << EXTI_CR4_EXTI14_Pos) ///< PD[14] pin - -#define EXTI_CR4_EXTI15_Pos (12) -#define EXTI_CR4_EXTI15 (0x0FU << EXTI_CR4_EXTI15_Pos) ///< EXTI 15 configuration -#define EXTI_CR4_EXTI15_PA (0x00U << EXTI_CR4_EXTI15_Pos) ///< PA[15] pin -#define EXTI_CR4_EXTI15_PB (0x01U << EXTI_CR4_EXTI15_Pos) ///< PB[15] pin -#define EXTI_CR4_EXTI15_PC (0x02U << EXTI_CR4_EXTI15_Pos) ///< PC[15] pin -#define EXTI_CR4_EXTI15_PD (0x03U << EXTI_CR4_EXTI15_Pos) ///< PD[15] pin -//////////////////////////////////////////////////////////////////////////////// -/// @brief EXTI_CFGR2 Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define EXTI_CFGR2_I2C1_Pos (16) -#define EXTI_CFGR2_I2C1_OD (0x00U << EXTI_CFGR2_I2C1_Pos) ///< Select open drain mode -#define EXTI_CFGR2_I2C1_PP (0x01U << EXTI_CFGR2_I2C1_Pos) ///< Select Push-pull mode -#define EXTI_CFGR2_I2C2_Pos (17) -#define EXTI_CFGR2_I2C2_OD (0x00U << EXTI_CFGR2_I2C2_Pos) ///< Select open drain mode -#define EXTI_CFGR2_I2C2_PP (0x01U << EXTI_CFGR2_I2C2_Pos) ///< Select Push-pull mode -#define EXTI_CFGR2_ETPHY_Pos (20) -#define EXTI_CFGR2_ETPHY_MII (0x00U << EXTI_CFGR2_ETPHY_Pos) ///< Select MII port -#define EXTI_CFGR2_ETPHY_RMII (0x01U << EXTI_CFGR2_ETPHY_Pos) ///< Select RMII port -#define EXTI_CFGR2_MAC_SPD_Pos (20) -#define EXTI_CFGR2_MAC_SPD_10 (0x00U << EXTI_CFGR2_ETPHY_Pos) ///< Select MAC_SPD 10 Mbps -#define EXTI_CFGR2_MAC_SPD_100 (0x01U << EXTI_CFGR2_ETPHY_Pos) ///< Select MAC_SPD 100 Mbps -//////////////////////////////////////////////////////////////////////////////// -/// @brief EXTI_PDETCSR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define EXTI_PDETCSR_PVDE_Pos (0) -#define EXTI_PDETCSR_PVDE (0x01U << EXTI_PDETCSR_PVDE_Pos) ///< PVD Enable -#define EXTI_PDETCSR_PLS_Pos (1) -#define EXTI_PDETCSR_PLS_1_7 (0x00U << EXTI_PDETCSR_PLS_Pos) ///< PVD 1.7mV -#define EXTI_PDETCSR_PLS_2_0 (0x01U << EXTI_PDETCSR_PLS_Pos) ///< PVD 2.0mV -#define EXTI_PDETCSR_PLS_2_3 (0x02U << EXTI_PDETCSR_PLS_Pos) ///< PVD 2.3mV -#define EXTI_PDETCSR_PLS_2_6 (0x03U << EXTI_PDETCSR_PLS_Pos) ///< PVD 2.6mV -#define EXTI_PDETCSR_PLS_2_9 (0x04U << EXTI_PDETCSR_PLS_Pos) ///< PVD 2.9mV -#define EXTI_PDETCSR_PLS_3_2 (0x05U << EXTI_PDETCSR_PLS_Pos) ///< PVD 3.2mV -#define EXTI_PDETCSR_PLS_3_5 (0x06U << EXTI_PDETCSR_PLS_Pos) ///< PVD 3.5mV -#define EXTI_PDETCSR_PLS_3_8 (0x07U << EXTI_PDETCSR_PLS_Pos) ///< PVD 3.8mV -#define EXTI_PDETCSR_PLS_4_1 (0x08U << EXTI_PDETCSR_PLS_Pos) ///< PVD 4.1mV -#define EXTI_PDETCSR_PLS_4_4 (0x09U << EXTI_PDETCSR_PLS_Pos) ///< PVD 4.4mV -#define EXTI_PDETCSR_PLS_4_7 (0x0AU << EXTI_PDETCSR_PLS_Pos) ///< PVD 4.7mV -#define EXTI_PDETCSR_PVDO_Pos (5) -#define EXTI_PDETCSR_PVDO (0x01U << EXTI_PDETCSR_PVDO_Pos) ///< PVD Output state -#define EXTI_PDETCSR_VDTO_Pos (6) -#define EXTI_PDETCSR_VDTO (0x01U << EXTI_PDETCSR_VDTO_Pos) ///< VDTO Output state -#define EXTI_PDETCSR_VDTE_Pos (8) -#define EXTI_PDETCSR_VDTE (0x01U << EXTI_PDETCSR_VDTE_Pos) ///< VDT Enable -#define EXTI_PDETCSR_VDTLS_Pos (9) -#define EXTI_PDETCSR_VDTLS0 (0x00U << EXTI_PDETCSR_VDTLS_Pos) ///< select VDT 0.9V -#define EXTI_PDETCSR_VDTLS1 (0x01U << EXTI_PDETCSR_VDTLS_Pos) ///< select VDT 1.0V -#define EXTI_PDETCSR_VDTLS2 (0x02U << EXTI_PDETCSR_VDTLS_Pos) ///< select VDT 1.1V -#define EXTI_PDETCSR_VDTLS3 (0x03U << EXTI_PDETCSR_VDTLS_Pos) ///< select VDT 1.2V -#define EXTI_PDETCSR_VBATDIV3_Pos (11) -#define EXTI_PDETCSR_VBATDIV3 (0x01U << EXTI_PDETCSR_VBATDIV3_Pos) ///< PVD Enable -//////////////////////////////////////////////////////////////////////////////// -/// @brief EXTI_VOSDLY Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define EXTI_EXTI_VOSDLY (0x3FFU) ///< VOS delay time - -//////////////////////////////////////////////////////////////////////////////// -/// @brief EXTI_IMR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define EXTI_IMR_0_Pos (0) -#define EXTI_IMR_0 (0x01U << EXTI_IMR_0_Pos) ///< Interrupt Mask on line 0 -#define EXTI_IMR_1_Pos (1) -#define EXTI_IMR_1 (0x01U << EXTI_IMR_1_Pos) ///< Interrupt Mask on line 1 -#define EXTI_IMR_2_Pos (2) -#define EXTI_IMR_2 (0x01U << EXTI_IMR_2_Pos) ///< Interrupt Mask on line 2 -#define EXTI_IMR_3_Pos (3) -#define EXTI_IMR_3 (0x01U << EXTI_IMR_3_Pos) ///< Interrupt Mask on line 3 -#define EXTI_IMR_4_Pos (4) -#define EXTI_IMR_4 (0x01U << EXTI_IMR_4_Pos) ///< Interrupt Mask on line 4 -#define EXTI_IMR_5_Pos (5) -#define EXTI_IMR_5 (0x01U << EXTI_IMR_5_Pos) ///< Interrupt Mask on line 5 -#define EXTI_IMR_6_Pos (6) -#define EXTI_IMR_6 (0x01U << EXTI_IMR_6_Pos) ///< Interrupt Mask on line 6 -#define EXTI_IMR_7_Pos (7) -#define EXTI_IMR_7 (0x01U << EXTI_IMR_7_Pos) ///< Interrupt Mask on line 7 -#define EXTI_IMR_8_Pos (8) -#define EXTI_IMR_8 (0x01U << EXTI_IMR_8_Pos) ///< Interrupt Mask on line 8 -#define EXTI_IMR_9_Pos (9) -#define EXTI_IMR_9 (0x01U << EXTI_IMR_9_Pos) ///< Interrupt Mask on line 9 -#define EXTI_IMR_10_Pos (10) -#define EXTI_IMR_10 (0x01U << EXTI_IMR_10_Pos) ///< Interrupt Mask on line 10 -#define EXTI_IMR_11_Pos (11) -#define EXTI_IMR_11 (0x01U << EXTI_IMR_11_Pos) ///< Interrupt Mask on line 11 -#define EXTI_IMR_12_Pos (12) -#define EXTI_IMR_12 (0x01U << EXTI_IMR_12_Pos) ///< Interrupt Mask on line 12 -#define EXTI_IMR_13_Pos (13) -#define EXTI_IMR_13 (0x01U << EXTI_IMR_13_Pos) ///< Interrupt Mask on line 13 -#define EXTI_IMR_14_Pos (14) -#define EXTI_IMR_14 (0x01U << EXTI_IMR_14_Pos) ///< Interrupt Mask on line 14 -#define EXTI_IMR_15_Pos (15) -#define EXTI_IMR_15 (0x01U << EXTI_IMR_15_Pos) ///< Interrupt Mask on line 15 -#define EXTI_IMR_16_Pos (16) -#define EXTI_IMR_16 (0x01U << EXTI_IMR_16_Pos) ///< Interrupt Mask on line 16 - - - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief EXTI_EMR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define EXTI_EMR_0_Pos (0) -#define EXTI_EMR_0 (0x01U << EXTI_EMR_0_Pos) ///< Event Mask on line 0 -#define EXTI_EMR_1_Pos (1) -#define EXTI_EMR_1 (0x01U << EXTI_EMR_1_Pos) ///< Event Mask on line 1 -#define EXTI_EMR_2_Pos (2) -#define EXTI_EMR_2 (0x01U << EXTI_EMR_2_Pos) ///< Event Mask on line 2 -#define EXTI_EMR_3_Pos (3) -#define EXTI_EMR_3 (0x01U << EXTI_EMR_3_Pos) ///< Event Mask on line 3 -#define EXTI_EMR_4_Pos (4) -#define EXTI_EMR_4 (0x01U << EXTI_EMR_4_Pos) ///< Event Mask on line 4 -#define EXTI_EMR_5_Pos (5) -#define EXTI_EMR_5 (0x01U << EXTI_EMR_5_Pos) ///< Event Mask on line 5 -#define EXTI_EMR_6_Pos (6) -#define EXTI_EMR_6 (0x01U << EXTI_EMR_6_Pos) ///< Event Mask on line 6 -#define EXTI_EMR_7_Pos (7) -#define EXTI_EMR_7 (0x01U << EXTI_EMR_7_Pos) ///< Event Mask on line 7 -#define EXTI_EMR_8_Pos (8) -#define EXTI_EMR_8 (0x01U << EXTI_EMR_8_Pos) ///< Event Mask on line 8 -#define EXTI_EMR_9_Pos (9) -#define EXTI_EMR_9 (0x01U << EXTI_EMR_9_Pos) ///< Event Mask on line 9 -#define EXTI_EMR_10_Pos (10) -#define EXTI_EMR_10 (0x01U << EXTI_EMR_10_Pos) ///< Event Mask on line 10 -#define EXTI_EMR_11_Pos (11) -#define EXTI_EMR_11 (0x01U << EXTI_EMR_11_Pos) ///< Event Mask on line 11 -#define EXTI_EMR_12_Pos (12) -#define EXTI_EMR_12 (0x01U << EXTI_EMR_12_Pos) ///< Event Mask on line 12 -#define EXTI_EMR_13_Pos (13) -#define EXTI_EMR_13 (0x01U << EXTI_EMR_13_Pos) ///< Event Mask on line 13 -#define EXTI_EMR_14_Pos (14) -#define EXTI_EMR_14 (0x01U << EXTI_EMR_14_Pos) ///< Event Mask on line 14 -#define EXTI_EMR_15_Pos (15) -#define EXTI_EMR_15 (0x01U << EXTI_EMR_15_Pos) ///< Event Mask on line 15 -#define EXTI_EMR_16_Pos (16) -#define EXTI_EMR_16 (0x01U << EXTI_EMR_16_Pos) ///< Event Mask on line 16 - - - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief EXTI_RTSR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define EXTI_RTSR_0_Pos (0) -#define EXTI_RTSR_0 (0x01U << EXTI_RTSR_0_Pos) ///< Rising trigger event configuration bit of line 0 -#define EXTI_RTSR_1_Pos (1) -#define EXTI_RTSR_1 (0x01U << EXTI_RTSR_1_Pos) ///< Rising trigger event configuration bit of line 1 -#define EXTI_RTSR_2_Pos (2) -#define EXTI_RTSR_2 (0x01U << EXTI_RTSR_2_Pos) ///< Rising trigger event configuration bit of line 2 -#define EXTI_RTSR_3_Pos (3) -#define EXTI_RTSR_3 (0x01U << EXTI_RTSR_3_Pos) ///< Rising trigger event configuration bit of line 3 -#define EXTI_RTSR_4_Pos (4) -#define EXTI_RTSR_4 (0x01U << EXTI_RTSR_4_Pos) ///< Rising trigger event configuration bit of line 4 -#define EXTI_RTSR_5_Pos (5) -#define EXTI_RTSR_5 (0x01U << EXTI_RTSR_5_Pos) ///< Rising trigger event configuration bit of line 5 -#define EXTI_RTSR_6_Pos (6) -#define EXTI_RTSR_6 (0x01U << EXTI_RTSR_6_Pos) ///< Rising trigger event configuration bit of line 6 -#define EXTI_RTSR_7_Pos (7) -#define EXTI_RTSR_7 (0x01U << EXTI_RTSR_7_Pos) ///< Rising trigger event configuration bit of line 7 -#define EXTI_RTSR_8_Pos (8) -#define EXTI_RTSR_8 (0x01U << EXTI_RTSR_8_Pos) ///< Rising trigger event configuration bit of line 8 -#define EXTI_RTSR_9_Pos (9) -#define EXTI_RTSR_9 (0x01U << EXTI_RTSR_9_Pos) ///< Rising trigger event configuration bit of line 9 -#define EXTI_RTSR_10_Pos (10) -#define EXTI_RTSR_10 (0x01U << EXTI_RTSR_10_Pos) ///< Rising trigger event configuration bit of line 10 -#define EXTI_RTSR_11_Pos (11) -#define EXTI_RTSR_11 (0x01U << EXTI_RTSR_11_Pos) ///< Rising trigger event configuration bit of line 11 -#define EXTI_RTSR_12_Pos (12) -#define EXTI_RTSR_12 (0x01U << EXTI_RTSR_12_Pos) ///< Rising trigger event configuration bit of line 12 -#define EXTI_RTSR_13_Pos (13) -#define EXTI_RTSR_13 (0x01U << EXTI_RTSR_13_Pos) ///< Rising trigger event configuration bit of line 13 -#define EXTI_RTSR_14_Pos (14) -#define EXTI_RTSR_14 (0x01U << EXTI_RTSR_14_Pos) ///< Rising trigger event configuration bit of line 14 -#define EXTI_RTSR_15_Pos (15) -#define EXTI_RTSR_15 (0x01U << EXTI_RTSR_15_Pos) ///< Rising trigger event configuration bit of line 15 -#define EXTI_RTSR_16_Pos (16) -#define EXTI_RTSR_16 (0x01U << EXTI_RTSR_16_Pos) ///< Rising trigger event configuration bit of line 16 - - - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief EXTI_FTSR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define EXTI_FTSR_0_Pos (0) -#define EXTI_FTSR_0 (0x01U << EXTI_FTSR_0_Pos) ///< Falling trigger event configuration bit of line 0 -#define EXTI_FTSR_1_Pos (1) -#define EXTI_FTSR_1 (0x01U << EXTI_FTSR_1_Pos) ///< Falling trigger event configuration bit of line 1 -#define EXTI_FTSR_2_Pos (2) -#define EXTI_FTSR_2 (0x01U << EXTI_FTSR_2_Pos) ///< Falling trigger event configuration bit of line 2 -#define EXTI_FTSR_3_Pos (3) -#define EXTI_FTSR_3 (0x01U << EXTI_FTSR_3_Pos) ///< Falling trigger event configuration bit of line 3 -#define EXTI_FTSR_4_Pos (4) -#define EXTI_FTSR_4 (0x01U << EXTI_FTSR_4_Pos) ///< Falling trigger event configuration bit of line 4 -#define EXTI_FTSR_5_Pos (5) -#define EXTI_FTSR_5 (0x01U << EXTI_FTSR_5_Pos) ///< Falling trigger event configuration bit of line 5 -#define EXTI_FTSR_6_Pos (6) -#define EXTI_FTSR_6 (0x01U << EXTI_FTSR_6_Pos) ///< Falling trigger event configuration bit of line 6 -#define EXTI_FTSR_7_Pos (7) -#define EXTI_FTSR_7 (0x01U << EXTI_FTSR_7_Pos) ///< Falling trigger event configuration bit of line 7 -#define EXTI_FTSR_8_Pos (8) -#define EXTI_FTSR_8 (0x01U << EXTI_FTSR_8_Pos) ///< Falling trigger event configuration bit of line 8 -#define EXTI_FTSR_9_Pos (9) -#define EXTI_FTSR_9 (0x01U << EXTI_FTSR_9_Pos) ///< Falling trigger event configuration bit of line 9 -#define EXTI_FTSR_10_Pos (10) -#define EXTI_FTSR_10 (0x01U << EXTI_FTSR_10_Pos) ///< Falling trigger event configuration bit of line 10 -#define EXTI_FTSR_11_Pos (11) -#define EXTI_FTSR_11 (0x01U << EXTI_FTSR_11_Pos) ///< Falling trigger event configuration bit of line 11 -#define EXTI_FTSR_12_Pos (12) -#define EXTI_FTSR_12 (0x01U << EXTI_FTSR_12_Pos) ///< Falling trigger event configuration bit of line 12 -#define EXTI_FTSR_13_Pos (13) -#define EXTI_FTSR_13 (0x01U << EXTI_FTSR_13_Pos) ///< Falling trigger event configuration bit of line 13 -#define EXTI_FTSR_14_Pos (14) -#define EXTI_FTSR_14 (0x01U << EXTI_FTSR_14_Pos) ///< Falling trigger event configuration bit of line 14 -#define EXTI_FTSR_15_Pos (15) -#define EXTI_FTSR_15 (0x01U << EXTI_FTSR_15_Pos) ///< Falling trigger event configuration bit of line 15 -#define EXTI_FTSR_16_Pos (16) -#define EXTI_FTSR_16 (0x01U << EXTI_FTSR_16_Pos) ///< Falling trigger event configuration bit of line 16 - - - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief EXTI_SWIER Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define EXTI_SWIER_0_Pos (0) -#define EXTI_SWIER_0 (0x01U << EXTI_SWIER_0_Pos) ///< Software Interrupt on line 0 -#define EXTI_SWIER_1_Pos (1) -#define EXTI_SWIER_1 (0x01U << EXTI_SWIER_1_Pos) ///< Software Interrupt on line 1 -#define EXTI_SWIER_2_Pos (2) -#define EXTI_SWIER_2 (0x01U << EXTI_SWIER_2_Pos) ///< Software Interrupt on line 2 -#define EXTI_SWIER_3_Pos (3) -#define EXTI_SWIER_3 (0x01U << EXTI_SWIER_3_Pos) ///< Software Interrupt on line 3 -#define EXTI_SWIER_4_Pos (4) -#define EXTI_SWIER_4 (0x01U << EXTI_SWIER_4_Pos) ///< Software Interrupt on line 4 -#define EXTI_SWIER_5_Pos (5) -#define EXTI_SWIER_5 (0x01U << EXTI_SWIER_5_Pos) ///< Software Interrupt on line 5 -#define EXTI_SWIER_6_Pos (6) -#define EXTI_SWIER_6 (0x01U << EXTI_SWIER_6_Pos) ///< Software Interrupt on line 6 -#define EXTI_SWIER_7_Pos (7) -#define EXTI_SWIER_7 (0x01U << EXTI_SWIER_7_Pos) ///< Software Interrupt on line 7 -#define EXTI_SWIER_8_Pos (8) -#define EXTI_SWIER_8 (0x01U << EXTI_SWIER_8_Pos) ///< Software Interrupt on line 8 -#define EXTI_SWIER_9_Pos (9) -#define EXTI_SWIER_9 (0x01U << EXTI_SWIER_9_Pos) ///< Software Interrupt on line 9 -#define EXTI_SWIER_10_Pos (10) -#define EXTI_SWIER_10 (0x01U << EXTI_SWIER_10_Pos) ///< Software Interrupt on line 10 -#define EXTI_SWIER_11_Pos (11) -#define EXTI_SWIER_11 (0x01U << EXTI_SWIER_11_Pos) ///< Software Interrupt on line 11 -#define EXTI_SWIER_12_Pos (12) -#define EXTI_SWIER_12 (0x01U << EXTI_SWIER_12_Pos) ///< Software Interrupt on line 12 -#define EXTI_SWIER_13_Pos (13) -#define EXTI_SWIER_13 (0x01U << EXTI_SWIER_13_Pos) ///< Software Interrupt on line 13 -#define EXTI_SWIER_14_Pos (14) -#define EXTI_SWIER_14 (0x01U << EXTI_SWIER_14_Pos) ///< Software Interrupt on line 14 -#define EXTI_SWIER_15_Pos (15) -#define EXTI_SWIER_15 (0x01U << EXTI_SWIER_15_Pos) ///< Software Interrupt on line 15 -#define EXTI_SWIER_16_Pos (16) -#define EXTI_SWIER_16 (0x01U << EXTI_SWIER_16_Pos) ///< Software Interrupt on line 16 - - - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief EXTI_PR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define EXTI_PR_0_Pos (0) -#define EXTI_PR_0 (0x01U << EXTI_PR_0_Pos) ///< Pending bit 0 -#define EXTI_PR_1_Pos (1) -#define EXTI_PR_1 (0x01U << EXTI_PR_1_Pos) ///< Pending bit 1 -#define EXTI_PR_2_Pos (2) -#define EXTI_PR_2 (0x01U << EXTI_PR_2_Pos) ///< Pending bit 2 -#define EXTI_PR_3_Pos (3) -#define EXTI_PR_3 (0x01U << EXTI_PR_3_Pos) ///< Pending bit 3 -#define EXTI_PR_4_Pos (4) -#define EXTI_PR_4 (0x01U << EXTI_PR_4_Pos) ///< Pending bit 4 -#define EXTI_PR_5_Pos (5) -#define EXTI_PR_5 (0x01U << EXTI_PR_5_Pos) ///< Pending bit 5 -#define EXTI_PR_6_Pos (6) -#define EXTI_PR_6 (0x01U << EXTI_PR_6_Pos) ///< Pending bit 6 -#define EXTI_PR_7_Pos (7) -#define EXTI_PR_7 (0x01U << EXTI_PR_7_Pos) ///< Pending bit 7 -#define EXTI_PR_8_Pos (8) -#define EXTI_PR_8 (0x01U << EXTI_PR_8_Pos) ///< Pending bit 8 -#define EXTI_PR_9_Pos (9) -#define EXTI_PR_9 (0x01U << EXTI_PR_9_Pos) ///< Pending bit 9 -#define EXTI_PR_10_Pos (10) -#define EXTI_PR_10 (0x01U << EXTI_PR_10_Pos) ///< Pending bit 10 -#define EXTI_PR_11_Pos (11) -#define EXTI_PR_11 (0x01U << EXTI_PR_11_Pos) ///< Pending bit 11 -#define EXTI_PR_12_Pos (12) -#define EXTI_PR_12 (0x01U << EXTI_PR_12_Pos) ///< Pending bit 12 -#define EXTI_PR_13_Pos (13) -#define EXTI_PR_13 (0x01U << EXTI_PR_13_Pos) ///< Pending bit 13 -#define EXTI_PR_14_Pos (14) -#define EXTI_PR_14 (0x01U << EXTI_PR_14_Pos) ///< Pending bit 14 -#define EXTI_PR_15_Pos (15) -#define EXTI_PR_15 (0x01U << EXTI_PR_15_Pos) ///< Pending bit 15 -#define EXTI_PR_16_Pos (16) -#define EXTI_PR_16 (0x01U << EXTI_PR_16_Pos) ///< Pending bit 16 - - - - - - - - - - -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -#endif -//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_flash.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_flash.h deleted file mode 100644 index b95acef60..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_flash.h +++ /dev/null @@ -1,290 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file reg_flash.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF -/// MM32 FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion - -#ifndef __REG_FLASH_H -#define __REG_FLASH_H - -// Files includes - -#include -#include -#include "types.h" - - - - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief MM32 MCU Memory/Peripherals mapping -//////////////////////////////////////////////////////////////////////////////// -#define FLASH_BASE (0x08000000U) ///< FLASH base address in the alias region -#define SRAM_BASE (0x20000000U) ///< SRAM base address in the alias region - -#define CACHE_BASE (APB2PERIPH_BASE + 0x6000) ///< Base Address: 0x40016000 - -//////////////////////////////////////////////////////////////////////////////// -/// @brief FLASH Base Address Definition -//////////////////////////////////////////////////////////////////////////////// -#define FLASH_REG_BASE (AHBPERIPH_BASE + 0x2000) ///< Base Address: 0x40022000 -//////////////////////////////////////////////////////////////////////////////// -/// @brief OPTB Base Address Definition -//////////////////////////////////////////////////////////////////////////////// -#define OB_BASE (0x1FFFF800U) ///< Flash Option Bytes base address -#define PROTECT_BASE (0x1FFE0000U) ///< Flash Protect Bytes base address - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief FLASH Registers Structure Definition -//////////////////////////////////////////////////////////////////////////////// -typedef struct { - __IO u32 ACR; ///< Access control Register offset: 0x00 - __IO u32 KEYR; ///< Key Register offset: 0x04 - __IO u32 OPTKEYR; ///< Option byte key Register offset: 0x08 - __IO u32 SR; ///< State Register offset: 0x0C - __IO u32 CR; ///< Control Register offset: 0x10 - __IO u32 AR; ///< Address Register offset: 0x14 - __IO u32 RESERVED; - __IO u32 OBR; ///< Option bytes Register offset: 0x1C - __IO u32 WRPR; ///< Write protect Register offset: 0x20 -} FLASH_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief OPT Structure Definition -//////////////////////////////////////////////////////////////////////////////// -typedef struct { - __IO u16 RDP; ///< Read Protect, offset: 0x00 - __IO u16 USER; ///< User option byte, offset: 0x02 - __IO u16 Data0; ///< User data 0, offset: 0x04 - __IO u16 Data1; ///< User data 1, offset: 0x06 - __IO u16 WRP0; ///< Flash write protection option byte 0, offset: 0x08 - __IO u16 WRP1; ///< Flash write protection option byte 1, offset: 0x0A - __IO u16 WRP2; ///< Flash write protection option byte 2, offset: 0x0C - __IO u16 WRP3; ///< Flash write protection option byte 3, offset: 0x0E -} OB_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief PROTECT BYTES Structure Definition -//////////////////////////////////////////////////////////////////////////////// -typedef struct { - __IO u16 PROTECT_LEN0; ///< The length of Protect byte 0, offset: 0x00 - __IO u16 PROTECT_ADDR0; ///< Data of Protect byte 0, offset: 0x02 - __IO u16 PROTECT_LEN1; ///< The length of Protect byte 1, offset: 0x04 - __IO u16 PROTECT_ADDR1; ///< Data of Protect byte 1, offset: 0x06 - __IO u16 PROTECT_LEN2; ///< The length of Protect byte 2, offset: 0x08 - __IO u16 PROTECT_ADDR2; ///< Data of Protect byte 2, offset: 0x0A - __IO u16 PROTECT_LEN3; ///< The length of Protect byte 3, offset: 0x0C - __IO u16 PROTECT_ADDR3; ///< Data of Protect byte 3, offset: 0x0E -} PROTECT_TypeDef; -//////////////////////////////////////////////////////////////////////////////// -/// @brief CACHE BYTES Structure Definition -//////////////////////////////////////////////////////////////////////////////// - -typedef struct { - __IO u32 CCR; ///< Configuration and control register offset: 0x00 - __IO u32 SR; ///< Status register offset: 0x04 - __IO u32 IMR; ///< Interrupt mask register offset: 0x08 - __IO u32 ISR; ///< Interrupt status register offset: 0x0C - __IO u32 RESERVED0; ///< offset: 0x10 - __IO u32 CSHR; ///< Hit Statistics Register offset: 0x14 - __IO u32 CSMR; ///< Lost Statistics Register offset: 0x18 -} CACHE_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief FLASH type pointer Definition -//////////////////////////////////////////////////////////////////////////////// -#define FLASH ((FLASH_TypeDef*) FLASH_REG_BASE) -//////////////////////////////////////////////////////////////////////////////// -/// @brief OPTB type pointer Definition -//////////////////////////////////////////////////////////////////////////////// -#define OB ((OB_TypeDef*) OB_BASE) -#define PROTECT ((PROTECT_TypeDef*) PROTECT_BASE) -//////////////////////////////////////////////////////////////////////////////// -/// @brief CACHE pointer Definition -//////////////////////////////////////////////////////////////////////////////// -#define CACHE ((CACHE_TypeDef*) CACHE_BASE) -//////////////////////////////////////////////////////////////////////////////// -/// @brief FLASH_ACR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define FLASH_ACR_LATENCY_Pos (0) -#define FLASH_ACR_LATENCY (0x07U << FLASH_ACR_LATENCY_Pos) ///< LATENCY[2:0] bits (Latency) -#define FLASH_ACR_LATENCY_0 (0x00U << FLASH_ACR_LATENCY_Pos) ///< 0 waiting state -#define FLASH_ACR_LATENCY_1 (0x01U << FLASH_ACR_LATENCY_Pos) ///< 1 waiting state -#define FLASH_ACR_LATENCY_2 (0x02U << FLASH_ACR_LATENCY_Pos) ///< 2 waiting state -#define FLASH_ACR_LATENCY_3 (0x03U << FLASH_ACR_LATENCY_Pos) ///< 3 waiting state -#define FLASH_ACR_HLFCYA_Pos (3) -#define FLASH_ACR_HLFCYA (0x01U << FLASH_ACR_HLFCYA_Pos) ///< Flash Half Cycle Access Enable -#define FLASH_ACR_PRFTBE_Pos (4) -#define FLASH_ACR_PRFTBE (0x01U << FLASH_ACR_PRFTBE_Pos) ///< Prefetch Buffer Enable -#define FLASH_ACR_PRFTBS_Pos (5) -#define FLASH_ACR_PRFTBS (0x01U << FLASH_ACR_PRFTBS_Pos) ///< Prefetch Buffer Status -//////////////////////////////////////////////////////////////////////////////// -/// @brief FLASH_KEYR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define FLASH_KEYR_FKEY_Pos (0) -#define FLASH_KEYR_FKEY (0xFFFFFFFFU << FLASH_KEYR_FKEY_Pos) ///< FLASH Key - -//////////////////////////////////////////////////////////////////////////////// -/// @brief FLASH_OPTKEYR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define FLASH_OPTKEYR_OPTKEY_Pos (0) -#define FLASH_OPTKEYR_OPTKEY (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEY_Pos) ///< Option Byte Key - -//////////////////////////////////////////////////////////////////////////////// -/// @brief FLASH_SR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define FLASH_SR_BUSY_Pos (0) -#define FLASH_SR_BUSY (0x01U << FLASH_SR_BUSY_Pos) ///< Busy -#define FLASH_SR_PGERR_Pos (2) -#define FLASH_SR_PGERR (0x01U << FLASH_SR_PGERR_Pos) ///< Programming Error -#define FLASH_SR_WRPRTERR_Pos (4) -#define FLASH_SR_WRPRTERR (0x01U << FLASH_SR_WRPRTERR_Pos) ///< Write Protection Error -#define FLASH_SR_EOP_Pos (5) -#define FLASH_SR_EOP (0x01U << FLASH_SR_EOP_Pos) ///< End of operation - -//////////////////////////////////////////////////////////////////////////////// -/// @brief FLASH_CR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define FLASH_CR_PG_Pos (0) -#define FLASH_CR_PG (0x01U << FLASH_CR_PG_Pos) ///< Programming -#define FLASH_CR_PER_Pos (1) -#define FLASH_CR_PER (0x01U << FLASH_CR_PER_Pos) ///< Page Erase -#define FLASH_CR_MER_Pos (2) -#define FLASH_CR_MER (0x01U << FLASH_CR_MER_Pos) ///< Mass Erase -#define FLASH_CR_OPTPG_Pos (4) -#define FLASH_CR_OPTPG (0x01U << FLASH_CR_OPTPG_Pos) ///< Option Byte Programming -#define FLASH_CR_OPTER_Pos (5) -#define FLASH_CR_OPTER (0x01U << FLASH_CR_OPTER_Pos) ///< Option Byte Erase -#define FLASH_CR_STRT_Pos (6) -#define FLASH_CR_STRT (0x01U << FLASH_CR_STRT_Pos) ///< Start -#define FLASH_CR_LOCK_Pos (7) -#define FLASH_CR_LOCK (0x01U << FLASH_CR_LOCK_Pos) ///< Lock -#define FLASH_CR_OPTWRE_Pos (9) -#define FLASH_CR_OPTWRE (0x01U << FLASH_CR_OPTWRE_Pos) ///< Option Bytes Write Enable -#define FLASH_CR_ERRIE_Pos (10) -#define FLASH_CR_ERRIE (0x01U << FLASH_CR_ERRIE_Pos) ///< Error Interrupt Enable -#define FLASH_CR_EOPIE_Pos (12) -#define FLASH_CR_EOPIE (0x01U << FLASH_CR_EOPIE_Pos) ///< End of operation interrupt enable - -//////////////////////////////////////////////////////////////////////////////// -/// @brief FLASH_AR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define FLASH_AR_FAR_Pos (0) -#define FLASH_AR_FAR (0xFFFFFFFFU << FLASH_AR_FAR_Pos) ///< Flash Address - -//////////////////////////////////////////////////////////////////////////////// -/// @brief FLASH_OBR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define FLASH_OBR_OPTERR_Pos (0) -#define FLASH_OBR_OPTERR (0x01U << FLASH_OBR_OPTERR_Pos) ///< Option Byte Error -#define FLASH_OBR_RDPRT_Pos (1) -#define FLASH_OBR_RDPRT (0x01U << FLASH_OBR_RDPRT_Pos) ///< Read protection level status -#define FLASH_OBR_USER_Pos (2) -#define FLASH_OBR_USER (0xFFU << FLASH_OBR_USER_Pos) ///< User Option Bytes - -#define FLASH_OBR_WDG_SW (0x01U << FLASH_OBR_USER_Pos) ///< WDG_SW -#define FLASH_OBR_RST_STOP (0x02U << FLASH_OBR_USER_Pos) ///< nRST_STOP -#define FLASH_OBR_RST_STDBY (0x04U << FLASH_OBR_USER_Pos) ///< nRST_STDBY - - -#define FLASH_OBR_Data0_Pos (10) -#define FLASH_OBR_Data0 (0xFFU << FLASH_OBR_Data0_Pos) ///< User data storage option byte -#define FLASH_OBR_Data1_Pos (18) -#define FLASH_OBR_Data1 (0xFFU << FLASH_OBR_Data1_Pos) ///< User data storage option byte - -//////////////////////////////////////////////////////////////////////////////// -/// @brief FLASH_WRPR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define FLASH_WRPR_WRP_Pos (0) -#define FLASH_WRPR_WRP (0xFFFFFFFFU << FLASH_WRPR_WRP_Pos) ///< Write Protect - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief CACHE_CCR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define CACHE_CCR_EN_Pos (0) -#define CACHE_CCR_EN (0x01U << CACHE_CCR_EN_Pos) ///< Cache Enable -#define CACHE_CCR_INV_Pos (1) -#define CACHE_CCR_INV (0x01U << CACHE_CCR_INV_REQ_Pos) ///< Manually invalidate the request -#define CACHE_CCR_POW_Pos (2) -#define CACHE_CCR_POW (0x01U << CACHE_CCR_POW_REQ_Pos) ///< Manual SRAM power request -#define CACHE_CCR_MAN_POW_Pos (3) -#define CACHE_CCR_MAN_POW (0x01U << CACHE_CCR_MAN_POW_Pos) ///< Set manual or automatic SRAM power request -#define CACHE_CCR_MAN_INV_Pos (4) -#define CACHE_CCR_MAN_INV (0x01U << CACHE_CCR_MAN_INV_Pos) ///< Manually or automatically disable it -#define CACHE_CCR_PREFETCH_Pos (5) -#define CACHE_CCR_PREFETCH (0x01U << CACHE_CCR_PREFETCH_Pos) ///< Prefetch function -#define CACHE_CCR_STATISTIC_Pos (6) -#define CACHE_CCR_STATISTIC (0x01U << CACHE_CCR_STATISTIC_Pos) ///< Statistics enable -//////////////////////////////////////////////////////////////////////////////// -/// @brief CACHE_SR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define CACHE_SR_CS_Pos (0) -#define CACHE_SR_CS0 (0x00U << CACHE_CCR_CS_Pos) ///< Cache is disabled -#define CACHE_SR_CS1 (0x01U << CACHE_CCR_CS_Pos) ///< Cache is being enabled -#define CACHE_SR_CS2 (0x02U << CACHE_CCR_CS_Pos) ///< Cache is enabled -#define CACHE_SR_CS3 (0x03U << CACHE_CCR_CS_Pos) ///< Cache is being disabled -#define CACHE_SR_INV_Pos (2) -#define CACHE_SR_INV (0x01U << CACHE_CCR_INV_REQ_Pos) ///< Invalidation status -#define CACHE_SR_POW_Pos (4) -#define CACHE_SR_POW (0x01U << CACHE_CCR_POW_REQ_Pos) ///< SRAM power response -//////////////////////////////////////////////////////////////////////////////// -/// @brief CACHE_IMR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define CACHE_IMR_MAN_INV_Pos (0) -#define CACHE_IMR_MAN_INV (0x01U << CACHE_IMR_MAN_INV_Pos) ///< Mask the interrupt request of manual invalidation error -#define CACHE_IMR_POW_Pos (1) -#define CACHE_IMR_POW (0x01U << CACHE_IMR_POW_Pos) ///< Mask the interrupt request of power supply error -//////////////////////////////////////////////////////////////////////////////// -/// @brief CACHE_ISR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define CACHE_ISR_MAN_INV_Pos (0) -#define CACHE_ISR_MAN_INV (0x01U << CACHE_ISR_MAN_INV_Pos) ///< Manual invalidation of error flags -#define CACHE_ISR_POW_Pos (1) -#define CACHE_ISR_POW (0x01U << CACHE_ISR_POW_Pos) ///< SRAM power error flags -//////////////////////////////////////////////////////////////////////////////// -/// @brief CACHE_CSHR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define CACHE_CSHR (0xFFFFU ) ///< Cache Hits -//////////////////////////////////////////////////////////////////////////////// -/// @brief CACHE_CSHR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define CACHE_CSMR (0xFFFFU ) ///< Cache Lost times - - - - - - - -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -#endif -//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_fsmc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_fsmc.h deleted file mode 100644 index 77870dd1e..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_fsmc.h +++ /dev/null @@ -1,194 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file reg_fsmc.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF -/// MM32 FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion - -#ifndef __REG_FSMC_H -#define __REG_FSMC_H - -// Files includes - -#include -#include -#include "types.h" - - - - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief FLASH Base Address Definition -//////////////////////////////////////////////////////////////////////////////// - -#define FSMC_BANK1_ADDR (0x60000000UL ) -#define FSMC_BANK2_ADDR (0x60000000UL + 0x4000000 ) -#define FSMC_BANK3_ADDR (0x60000000UL + 0x8000000 ) -#define FSMC_BANK4_ADDR (0x60000000UL + 0xc000000 ) -#define FSMC_BASE (0x60000000UL + 0x40000000) ///< Base Address: 0xA0000000 - -//////////////////////////////////////////////////////////////////////////////// -/// @brief FSMC Registers Structure Definition -//////////////////////////////////////////////////////////////////////////////// - -typedef struct { - __IO u32 Reservedoffset0x00; ///< Reserved Register offset: 0x00 - __IO u32 Reservedoffset0x04; ///< Reserved Register offset: 0x04 - __IO u32 Reservedoffset0x08; ///< Reserved Register offset: 0x08 - __IO u32 Reservedoffset0x0c; ///< Reserved Register offset: 0x0c - __IO u32 Reservedoffset0x10; ///< Reserved Register offset: 0x10 - __IO u32 Reservedoffset0x14; ///< Reserved Register offset: 0x14 - __IO u32 Reservedoffset0x18; ///< Reserved Register offset: 0x18 - __IO u32 Reservedoffset0x1c; ///< Reserved Register offset: 0x1c - __IO u32 Reservedoffset0x20; ///< Reserved Register offset: 0x20 - __IO u32 Reservedoffset0x24; ///< Reserved Register offset: 0x24 - __IO u32 Reservedoffset0x28; ///< Reserved Register offset: 0x28 - __IO u32 Reservedoffset0x2c; ///< Reserved Register offset: 0x2c - __IO u32 Reservedoffset0x30; ///< Reserved Register offset: 0x30 - __IO u32 Reservedoffset0x34; ///< Reserved Register offset: 0x34 - __IO u32 Reservedoffset0x38; ///< Reserved Register offset: 0x38 - __IO u32 Reservedoffset0x3c; ///< Reserved Register offset: 0x3c - __IO u32 Reservedoffset0x40; ///< Reserved Register offset: 0x40 - __IO u32 Reservedoffset0x44; ///< Reserved Register offset: 0x44 - __IO u32 Reservedoffset0x48; ///< Reserved Register offset: 0x48 - __IO u32 Reservedoffset0x4c; ///< Reserved Register offset: 0x4c - __IO u32 Reservedoffset0x50; ///< Reserved Register offset: 0x50 - __IO u32 SMSKR; ///< SMSKR control Register offset: 0x54 - __IO u32 Reservedoffset0x58; ///< Reserved Register offset: 0x58 - __IO u32 Reservedoffset0x5c; ///< Reserved Register offset: 0x5c - __IO u32 Reservedoffset0x60; ///< Reserved Register offset: 0x60 - __IO u32 Reservedoffset0x64; ///< Reserved Register offset: 0x64 - __IO u32 Reservedoffset0x68; ///< Reserved Register offset: 0x68 - __IO u32 Reservedoffset0x6c; ///< Reserved Register offset: 0x6c - __IO u32 Reservedoffset0x70; ///< Reserved Register offset: 0x70 - __IO u32 Reservedoffset0x74; ///< Reserved Register offset: 0x74 - __IO u32 Reservedoffset0x78; ///< Reserved Register offset: 0x78 - __IO u32 Reservedoffset0x7c; ///< Reserved Register offset: 0x7c - __IO u32 Reservedoffset0x80; ///< Reserved Register offset: 0x80 - __IO u32 Reservedoffset0x84; ///< Reserved Register offset: 0x84 - __IO u32 Reservedoffset0x88; ///< Reserved Register offset: 0x88 - __IO u32 Reservedoffset0x8c; ///< Reserved Register offset: 0x8c - __IO u32 Reservedoffset0x90; ///< Reserved Register offset: 0x90 - __IO u32 SMTMGR_SET0; ///< SMTMGR_SET Register 0 offset: 0x94 - __IO u32 SMTMGR_SET1; ///< SMTMGR_SET Register 1 offset: 0x98 - __IO u32 SMTMGR_SET2; ///< SMTMGR_SET Register 2 offset: 0x9c - __IO u32 Reservedoffset0xA0; ///< Reserved Register offset: 0xa0 - __IO u32 SMCTLR; ///< Reserved Register offset: 0xa4 - __IO u32 Reservedoffset0xA8; ///< Reserved Register offset: 0xa8 - __IO u32 Reservedoffset0xAC; ///< Reserved Register offset: 0xac -} FSMC_TypeDef; - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief FSMC type pointer Definition -//////////////////////////////////////////////////////////////////////////////// -#define FSMC ((FSMC_TypeDef*) FSMC_BASE) - -//////////////////////////////////////////////////////////////////////////////// -/// @brief FSMC_SMSKR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define FSMC_SMSKR_REG_SELECT_Pos (8) -#define FSMC_SMSKR_REG_SELECT0 (0x00U << FSMC_SMSKR_REG_SELECT_Pos) ///< timing parameter configures the register group 0 -#define FSMC_SMSKR_REG_SELECT1 (0x01U << FSMC_SMSKR_REG_SELECT_Pos) ///< timing parameter configures the register group 1 -#define FSMC_SMSKR_REG_SELECT2 (0x02U << FSMC_SMSKR_REG_SELECT_Pos) ///< timing parameter configures the register group 2 -#define FSMC_SMSKR_MEM_TYPE_Pos (5) -#define FSMC_SMSKR_MEM_TYPE0 (0x00U << FSMC_SMSKR_MEM_TYPE_Pos) ///< SDRAM -#define FSMC_SMSKR_MEM_TYPE1 (0x01U << FSMC_SMSKR_MEM_TYPE_Pos) ///< SRAM -#define FSMC_SMSKR_MEM_TYPE2 (0x02U << FSMC_SMSKR_MEM_TYPE_Pos) ///< FLASH -#define FSMC_SMSKR_MEM_SIZE_Pos (0) -#define FSMC_SMSKR_MEM_SIZE_64K (0x01U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 64KB -#define FSMC_SMSKR_MEM_SIZE_128K (0x02U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 128KB -#define FSMC_SMSKR_MEM_SIZE_256K (0x03U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 256KB -#define FSMC_SMSKR_MEM_SIZE_512K (0x04U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 512KB -#define FSMC_SMSKR_MEM_SIZE_1M (0x05U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 1MB -#define FSMC_SMSKR_MEM_SIZE_2M (0x06U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 2MB -#define FSMC_SMSKR_MEM_SIZE_4M (0x07U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 4MB -#define FSMC_SMSKR_MEM_SIZE_8M (0x08U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 8MB -#define FSMC_SMSKR_MEM_SIZE_16M (0x09U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 16MB -#define FSMC_SMSKR_MEM_SIZE_32M (0x10U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 32MB -#define FSMC_SMSKR_MEM_SIZE_64M (0x11U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 64MB -#define FSMC_SMSKR_MEM_SIZE_128M (0x12U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 128MB -#define FSMC_SMSKR_MEM_SIZE_256M (0x13U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 256MB -#define FSMC_SMSKR_MEM_SIZE_512M (0x14U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 512MB -#define FSMC_SMSKR_MEM_SIZE_1G (0x15U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 1GB -#define FSMC_SMSKR_MEM_SIZE_2G (0x16U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 2GB -#define FSMC_SMSKR_MEM_SIZE_4G (0x17U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 4GB - -//////////////////////////////////////////////////////////////////////////////// -/// @brief FSMC_SMTMGR_SET0/1/2 Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define FSMC_SMTMGR_SET_SM_READ_PIPE_Pos (28) -#define FSMC_SMTMGR_SET_SM_READ_PIPE (0x03U << FSMC_SMTMGR_SET_SM_READ_PIPE_Pos) ///< The period of the latched read data -#define FSMC_SMTMGR_SET_LOW_FREG_SYNC_DEVICE_Pos (27) -#define FSMC_SMTMGR_SET_LOW_FREG_SYNC_DEVICE (0x01U << FSMC_SMTMGR_SET_LOW_FREG_SYNC_DEVICE_Pos) ///< Access low frequency synchronization devices -#define FSMC_SMTMGR_SET_READ_MODE_Pos (26) -#define FSMC_SMTMGR_SET_READ_MODE (0x01U << FSMC_SMTMGR_SET_READ_MODE_Pos) ///< The Hready_RESP signal is from an external DEVICE -#define FSMC_SMTMGR_SET_T_WP_Pos (10) -#define FSMC_SMTMGR_SET_T_WP (0x3FU << FSMC_SMTMGR_SET_T_WP_Pos) ///< Write pulse width 64 clock cycles -#define FSMC_SMTMGR_SET_T_WR_Pos (8) -#define FSMC_SMTMGR_SET_T_WR (0x03U << FSMC_SMTMGR_SET_T_WR_Pos) ///< Address/data retention time for write operations is 3 clock cycles -#define FSMC_SMTMGR_SET_T_AS_Pos (6) -#define FSMC_SMTMGR_SET_T_AS (0x03U << FSMC_SMTMGR_SET_T_AS_Pos) ///< The address establishment time of write operation is 3 clock cycles -#define FSMC_SMTMGR_SET_T_RC_Pos (0) -#define FSMC_SMTMGR_SET_T_RC (0x3FU << FSMC_SMTMGR_SET_T_RC_Pos) ///< Read operation cycle 64 clock cycles - -//////////////////////////////////////////////////////////////////////////////// -/// @brief FSMC_SMCTLR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos (13) -#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2 (0x07U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos) -#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_16 (0x00U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos) ///< Memory data bus bit width 16 bits -#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_32 (0x01U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos) ///< Memory data bus bit width 32 bits -#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_64 (0x02U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos) ///< Memory data bus bit width 64 bits -#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_128 (0x03U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos) ///< Memory data bus bit width 128 bits -#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_8 (0x04U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos) ///< Memory data bus bit width 8 bits -#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos (10) -#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1 (0x07U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos) -#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_16 (0x00U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos) ///< Memory data bus bit width 16 bits -#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_32 (0x01U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos) ///< Memory data bus bit width 32 bits -#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_64 (0x02U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos) ///< Memory data bus bit width 64 bits -#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_128 (0x03U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos) ///< Memory data bus bit width 128 bits -#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_8 (0x04U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos) ///< Memory data bus bit width 8 bits -#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos (7) -#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0 (0x07U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos) -#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_16 (0x00U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos) ///< Memory data bus bit width 16 bits -#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_32 (0x01U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos) ///< Memory data bus bit width 32 bits -#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_64 (0x02U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos) ///< Memory data bus bit width 64 bits -#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_128 (0x03U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos) ///< Memory data bus bit width 128 bits -#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_8 (0x04U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos) ///< Memory data bus bit width 8 bits - - - - - - -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -#endif //__REG_FSMC_H -//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_gpio.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_gpio.h deleted file mode 100644 index 44e043bac..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_gpio.h +++ /dev/null @@ -1,706 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file reg_gpio.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF -/// MM32 FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion - -#ifndef __REG_GPIO_H -#define __REG_GPIO_H - -// Files includes - -#include -#include -#include "types.h" - - - - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - - - - - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief GPIO Base Address Definition -//////////////////////////////////////////////////////////////////////////////// - -#define GPIOA_BASE (AHBPERIPH_BASE + 0x0020000) ///< Base Address: 0x40040000 -#define GPIOB_BASE (AHBPERIPH_BASE + 0x0020400) ///< Base Address: 0x40040400 -#define GPIOC_BASE (AHBPERIPH_BASE + 0x0020800) ///< Base Address: 0x40040800 -#define GPIOD_BASE (AHBPERIPH_BASE + 0x0020C00) ///< Base Address: 0x40040C00 -#define GPIOE_BASE (AHBPERIPH_BASE + 0x0021000) ///< Base Address: 0x40041000 -#define GPIOF_BASE (AHBPERIPH_BASE + 0x0021400) ///< Base Address: 0x40041400 -#define GPIOG_BASE (AHBPERIPH_BASE + 0x0021800) ///< Base Address: 0x40041800 -#define GPIOH_BASE (AHBPERIPH_BASE + 0x0021C00) ///< Base Address: 0x40041C00 - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief GPIO Registers Structure Definition -//////////////////////////////////////////////////////////////////////////////// -typedef struct { - __IO u32 CRL; ///< Control Register Low, offset: 0x00 - __IO u32 CRH; ///< Control Register High, offset: 0x04 - __IO u32 IDR; ///< Input Data Register, offset: 0x08 - __IO u32 ODR; ///< Output Data Register, offset: 0x0C - __IO u32 BSRR; ///< Bit Set or Reset Register, offset: 0x10 - __IO u32 BRR; ///< Bit Reset Register, offset: 0x14 - __IO u32 LCKR; ///< Lock Register, offset: 0x18 - __IO u32 DCR; ///< Pin Output Open Drain Config Register, offset: 0x1C - __IO u32 AFRL; ///< Port Multiplexing Function Low Register, offset: 0x20 - __IO u32 AFRH; ///< Port Multiplexing Function High Register, offset: 0x24 -} GPIO_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief GPIO type pointer Definition -//////////////////////////////////////////////////////////////////////////////// -#define GPIOA ((GPIO_TypeDef*) GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef*) GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef*) GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef*) GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef*) GPIOE_BASE) -#define GPIOF ((GPIO_TypeDef*) GPIOF_BASE) -#define GPIOG ((GPIO_TypeDef*) GPIOG_BASE) -#define GPIOH ((GPIO_TypeDef*) GPIOH_BASE) - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief GPIO Common Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// - - - - -#define GPIO_CNF_MODE_AIN 0x00UL //0b0000, ///< Analog input -#define GPIO_CNF_MODE_FLOATING 0x04UL //0b0100, ///< Floating input -#define GPIO_CNF_MODE_INPUPD 0x08UL //0b1000, ///< Pull up and down input -#define GPIO_CNF_MODE_INRESEVED 0x0CUL //0b1100, ///< Reseved input mode -#define GPIO_CNF_MODE_OUT_PP 0x01UL //0b0001, ///< Universal push-pull output default -#define GPIO_CNF_MODE_OUT_OD 0x05UL //0b0101, ///< Universal open drain output default -#define GPIO_CNF_MODE_AF_PP 0x09UL //0b1001, ///< Multiplex push-pull output default -#define GPIO_CNF_MODE_AF_OD 0x0DUL //0b1101 ///< Multiplex open drain output default -#define GPIO_CNF_MODE_50MHZ_OUT_PP 0x01UL //0b0001, ///< Universal push-pull output 50MHZ -#define GPIO_CNF_MODE_50MHZ_OUT_OD 0x05UL //0b0101, ///< Universal open drain output 50MHZ -#define GPIO_CNF_MODE_50MHZ_AF_PP 0x09UL //0b1001, ///< Multiplex push-pull output 50MHZ -#define GPIO_CNF_MODE_50MHZ_AF_OD 0x0DUL //0b1101 ///< Multiplex open drain output 50MHZ -#define GPIO_CNF_MODE_20MHZ_OUT_PP 0x02UL //0b0010, ///< Universal push-pull output 20MHZ -#define GPIO_CNF_MODE_20MHZ_OUT_OD 0x06UL //0b0110, ///< Universal open drain output 20MHZ -#define GPIO_CNF_MODE_20MHZ_AF_PP 0x0AUL //0b1010, ///< Multiplex push-pull output 20MHZ -#define GPIO_CNF_MODE_20MHZ_AF_OD 0x0EUL //0b1110 ///< Multiplex open drain output 20MHZ -#define GPIO_CNF_MODE_10MHZ_OUT_PP 0x03UL //0b0011, ///< Universal push-pull output 10MHZ -#define GPIO_CNF_MODE_10MHZ_OUT_OD 0x07UL //0b0111, ///< Universal open drain output 10MHZ -#define GPIO_CNF_MODE_10MHZ_AF_PP 0x0BUL //0b1011, ///< Multiplex push-pull output 10MHZ -#define GPIO_CNF_MODE_10MHZ_AF_OD 0x0FUL //0b1111 ///< Multiplex open drain output 10MHZ -#define GPIO_CNF_MODE_MASK 0x0FUL //0b1111 - -#define GPIO_CRL_CNF_MODE_0_Pos (0) // ///< Analog input -#define GPIO_CRL_CNF_MODE_1_Pos (4) // ///< Floating input -#define GPIO_CRL_CNF_MODE_2_Pos (8) // ///< Pull up and down input -#define GPIO_CRL_CNF_MODE_3_Pos (12) // ///< Reseved input mode -#define GPIO_CRL_CNF_MODE_4_Pos (16) // ///< Universal push-pull output default -#define GPIO_CRL_CNF_MODE_5_Pos (20) // ///< Universal open drain output default -#define GPIO_CRL_CNF_MODE_6_Pos (24) // ///< Multiplex push-pull output default -#define GPIO_CRL_CNF_MODE_7_Pos (28) // ///< Multiplex open drain output default -#define GPIO_CRH_CNF_MODE_8_Pos (0) // ///< Universal push-pull output 50MHZ -#define GPIO_CRH_CNF_MODE_9_Pos (4) // ///< Universal open drain output 50MHZ -#define GPIO_CRH_CNF_MODE_10_Pos (8) // ///< Multiplex push-pull output 50MHZ -#define GPIO_CRH_CNF_MODE_11_Pos (12) // ///< Multiplex open drain output 50MHZ -#define GPIO_CRH_CNF_MODE_12_Pos (16) // ///< Universal push-pull output 20MHZ -#define GPIO_CRH_CNF_MODE_13_Pos (20) // ///< Universal open drain output 20MHZ -#define GPIO_CRH_CNF_MODE_14_Pos (24) // ///< Multiplex push-pull output 20MHZ -#define GPIO_CRH_CNF_MODE_15_Pos (28) // ///< Multiplex open drain output 20MHZ - -//////////////////////////////////////////////////////////////////////////////// -/// @brief GPIO_CRL Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define GPIO_CRL_MODE ((u32)0x33333333) ///< Port x mode bits - -#define GPIO_CRL_MODE0_Pos (0) -#define GPIO_CRL_MODE0 (0x03U << GPIO_CRL_MODE0_Pos) ///< MODE0[1:0] bits (portx mode bits, pin 0) -#define GPIO_CRL_MODE0_0 (0x01U << GPIO_CRL_MODE0_Pos) ///< Bit 0 -#define GPIO_CRL_MODE0_1 (0x02U << GPIO_CRL_MODE0_Pos) ///< Bit 1 - -#define GPIO_CRL_CNF0_Pos (2) -#define GPIO_CRL_CNF0 (0x03U << GPIO_CRL_CNF0_Pos) ///< CNF0[1:0] bits (portx configuration bits, pin 0) -#define GPIO_CRL_CNF0_0 (0x01U << GPIO_CRL_CNF0_Pos) ///< Bit 0 -#define GPIO_CRL_CNF0_1 (0x02U << GPIO_CRL_CNF0_Pos) ///< Bit 1 - -#define GPIO_CRL_MODE1_Pos (4) -#define GPIO_CRL_MODE1 (0x03U << GPIO_CRL_MODE1_Pos) ///< MODE1[1:0] bits (portx mode bits, pin 1) -#define GPIO_CRL_MODE1_0 (0x01U << GPIO_CRL_MODE1_Pos) ///< Bit 0 -#define GPIO_CRL_MODE1_1 (0x02U << GPIO_CRL_MODE1_Pos) ///< Bit 1 - -#define GPIO_CRL_CNF1_Pos (6) -#define GPIO_CRL_CNF1 (0x03U << GPIO_CRL_CNF1_Pos) ///< CNF1[1:0] bits (portx configuration bits, pin 1) -#define GPIO_CRL_CNF1_0 (0x01U << GPIO_CRL_CNF1_Pos) ///< Bit 0 -#define GPIO_CRL_CNF1_1 (0x02U << GPIO_CRL_CNF1_Pos) ///< Bit 1 - -#define GPIO_CRL_MODE2_Pos (8) -#define GPIO_CRL_MODE2 (0x03U << GPIO_CRL_MODE2_Pos) ///< MODE2[1:0] bits (portx mode bits, pin 2) -#define GPIO_CRL_MODE2_0 (0x01U << GPIO_CRL_MODE2_Pos) ///< Bit 0 -#define GPIO_CRL_MODE2_1 (0x02U << GPIO_CRL_MODE2_Pos) ///< Bit 1 - -#define GPIO_CRL_CNF2_Pos (10) -#define GPIO_CRL_CNF2 (0x03U << GPIO_CRL_CNF2_Pos) ///< CNF2[1:0] bits (portx configuration bits, pin 2) -#define GPIO_CRL_CNF2_0 (0x01U << GPIO_CRL_CNF2_Pos) ///< Bit 0 -#define GPIO_CRL_CNF2_1 (0x02U << GPIO_CRL_CNF2_Pos) ///< Bit 1 - -#define GPIO_CRL_MODE3_Pos (12) -#define GPIO_CRL_MODE3 (0x03U << GPIO_CRL_MODE3_Pos) ///< MODE3[1:0] bits (portx mode bits, pin 3) -#define GPIO_CRL_MODE3_0 (0x01U << GPIO_CRL_MODE3_Pos) ///< Bit 0 -#define GPIO_CRL_MODE3_1 (0x02U << GPIO_CRL_MODE3_Pos) ///< Bit 1 - -#define GPIO_CRL_CNF3_Pos (14) -#define GPIO_CRL_CNF3 (0x03U << GPIO_CRL_CNF3_Pos) ///< CNF3[1:0] bits (portx configuration bits, pin 3) -#define GPIO_CRL_CNF3_0 (0x01U << GPIO_CRL_CNF3_Pos) ///< Bit 0 -#define GPIO_CRL_CNF3_1 (0x02U << GPIO_CRL_CNF3_Pos) ///< Bit 1 - - -#define GPIO_CRL_MODE4_Pos (16) -#define GPIO_CRL_MODE4 (0x03U << GPIO_CRL_MODE4_Pos) ///< MODE4[1:0] bits (portx mode bits, pin 4) -#define GPIO_CRL_MODE4_0 (0x01U << GPIO_CRL_MODE4_Pos) ///< Bit 0 -#define GPIO_CRL_MODE4_1 (0x02U << GPIO_CRL_MODE4_Pos) ///< Bit 1 - -#define GPIO_CRL_CNF4_Pos (18) -#define GPIO_CRL_CNF4 (0x03U << GPIO_CRL_CNF4_Pos) ///< CNF4[1:0] bits (portx configuration bits, pin 4) -#define GPIO_CRL_CNF4_0 (0x01U << GPIO_CRL_CNF4_Pos) ///< Bit 0 -#define GPIO_CRL_CNF4_1 (0x02U << GPIO_CRL_CNF4_Pos) ///< Bit 1 - -#define GPIO_CRL_MODE5_Pos (20) -#define GPIO_CRL_MODE5 (0x03U << GPIO_CRL_MODE5_Pos) ///< MODE5[1:0] bits (portx mode bits, pin 5) -#define GPIO_CRL_MODE5_0 (0x01U << GPIO_CRL_MODE5_Pos) ///< Bit 0 -#define GPIO_CRL_MODE5_1 (0x02U << GPIO_CRL_MODE5_Pos) ///< Bit 1 - -#define GPIO_CRL_CNF5_Pos (22) -#define GPIO_CRL_CNF5 (0x03U << GPIO_CRL_CNF5_Pos) ///< CNF5[1:0] bits (portx configuration bits, pin 5) -#define GPIO_CRL_CNF5_0 (0x01U << GPIO_CRL_CNF5_Pos) ///< Bit 0 -#define GPIO_CRL_CNF5_1 (0x02U << GPIO_CRL_CNF5_Pos) ///< Bit 1 - -#define GPIO_CRL_MODE6_Pos (24) -#define GPIO_CRL_MODE6 (0x03U << GPIO_CRL_MODE6_Pos) ///< MODE6[1:0] bits (portx mode bits, pin 6) -#define GPIO_CRL_MODE6_0 (0x01U << GPIO_CRL_MODE6_Pos) ///< Bit 0 -#define GPIO_CRL_MODE6_1 (0x02U << GPIO_CRL_MODE6_Pos) ///< Bit 1 - -#define GPIO_CRL_CNF6_Pos (26) -#define GPIO_CRL_CNF6 (0x03U << GPIO_CRL_CNF6_Pos) ///< CNF6[1:0] bits (portx configuration bits, pin 6) -#define GPIO_CRL_CNF6_0 (0x01U << GPIO_CRL_CNF6_Pos) ///< Bit 0 -#define GPIO_CRL_CNF6_1 (0x02U << GPIO_CRL_CNF6_Pos) ///< Bit 1 - -#define GPIO_CRL_MODE7_Pos (28) -#define GPIO_CRL_MODE7 (0x03U << GPIO_CRL_MODE7_Pos) ///< MODE7[1:0] bits (portx mode bits, pin 7) -#define GPIO_CRL_MODE7_0 (0x01U << GPIO_CRL_MODE7_Pos) ///< Bit 0 -#define GPIO_CRL_MODE7_1 (0x02U << GPIO_CRL_MODE7_Pos) ///< Bit 1 - -#define GPIO_CRL_CNF7_Pos (30) -#define GPIO_CRL_CNF7 (0x03U << GPIO_CRL_CNF7_Pos) ///< CNF7[1:0] bits (portx configuration bits, pin 7) -#define GPIO_CRL_CNF7_0 (0x01U << GPIO_CRL_CNF7_Pos) ///< Bit 0 -#define GPIO_CRL_CNF7_1 (0x02U << GPIO_CRL_CNF7_Pos) ///< Bit 1 - -//////////////////////////////////////////////////////////////////////////////// -/// @brief GPIO_CRH Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define GPIO_CRH_MODE ((u32)0x33333333) ///< Port x mode bits - -#define GPIO_CRH_MODE8_Pos (0) -#define GPIO_CRH_MODE8 (0x03U << GPIO_CRH_MODE8_Pos) ///< MODE8[1:0] bits (portx mode bits, pin 0) -#define GPIO_CRH_MODE8_0 (0x01U << GPIO_CRH_MODE8_Pos) ///< Bit 0 -#define GPIO_CRH_MODE8_1 (0x02U << GPIO_CRH_MODE8_Pos) ///< Bit 1 -#define GPIO_CRH_CNF8_Pos (2) -#define GPIO_CRH_CNF8 (0x03U << GPIO_CRH_CNF8_Pos) ///< CNF8[1:0] bits (portx configuration bits, pin 0) -#define GPIO_CRH_CNF8_0 (0x01U << GPIO_CRH_CNF8_Pos) ///< Bit 0 -#define GPIO_CRH_CNF8_1 (0x02U << GPIO_CRH_CNF8_Pos) ///< Bit 1 -#define GPIO_CRH_MODE9_Pos (4) -#define GPIO_CRH_MODE9 (0x03U << GPIO_CRH_MODE9_Pos) ///< MODE9[1:0] bits (portx mode bits, pin 1) -#define GPIO_CRH_MODE9_0 (0x01U << GPIO_CRH_MODE9_Pos) ///< Bit 0 -#define GPIO_CRH_MODE9_1 (0x02U << GPIO_CRH_MODE9_Pos) ///< Bit 1 -#define GPIO_CRH_CNF9_Pos (6) -#define GPIO_CRH_CNF9 (0x03U << GPIO_CRH_CNF9_Pos) ///< CNF9[1:0] bits (portx configuration bits, pin 1) -#define GPIO_CRH_CNF9_0 (0x01U << GPIO_CRH_CNF9_Pos) ///< Bit 0 -#define GPIO_CRH_CNF9_1 (0x02U << GPIO_CRH_CNF9_Pos) ///< Bit 1 -#define GPIO_CRH_MODE10_Pos (8) -#define GPIO_CRH_MODE10 (0x03U << GPIO_CRH_MODE10_Pos) ///< MODE10[1:0] bits (portx mode bits, pin 2) -#define GPIO_CRH_MODE10_0 (0x01U << GPIO_CRH_MODE10_Pos) ///< Bit 0 -#define GPIO_CRH_MODE10_1 (0x02U << GPIO_CRH_MODE10_Pos) ///< Bit 1 -#define GPIO_CRH_CNF10_Pos (10) -#define GPIO_CRH_CNF10 (0x03U << GPIO_CRH_CNF10_Pos) ///< CNF10[1:0] bits (portx configuration bits, pin 2) -#define GPIO_CRH_CNF10_0 (0x01U << GPIO_CRH_CNF10_Pos) ///< Bit 0 -#define GPIO_CRH_CNF10_1 (0x02U << GPIO_CRH_CNF10_Pos) ///< Bit 1 -#define GPIO_CRH_MODE11_Pos (12) -#define GPIO_CRH_MODE11 (0x03U << GPIO_CRH_MODE11_Pos) ///< MODE11[1:0] bits (portx mode bits, pin 3) -#define GPIO_CRH_MODE11_0 (0x01U << GPIO_CRH_MODE11_Pos) ///< Bit 0 -#define GPIO_CRH_MODE11_1 (0x02U << GPIO_CRH_MODE11_Pos) ///< Bit 1 -#define GPIO_CRH_CNF11_Pos (14) -#define GPIO_CRH_CNF11 (0x03U << GPIO_CRH_CNF11_Pos) ///< CNF11[1:0] bits (portx configuration bits, pin 3) -#define GPIO_CRH_CNF11_0 (0x01U << GPIO_CRH_CNF11_Pos) ///< Bit 0 -#define GPIO_CRH_CNF11_1 (0x02U << GPIO_CRH_CNF11_Pos) ///< Bit 1 -#define GPIO_CRH_MODE12_Pos (16) -#define GPIO_CRH_MODE12 (0x03U << GPIO_CRH_MODE12_Pos) ///< MODE12[1:0] bits (portx mode bits, pin 4) -#define GPIO_CRH_MODE12_0 (0x01U << GPIO_CRH_MODE12_Pos) ///< Bit 0 -#define GPIO_CRH_MODE12_1 (0x02U << GPIO_CRH_MODE12_Pos) ///< Bit 1 -#define GPIO_CRH_CNF12_Pos (18) -#define GPIO_CRH_CNF12 (0x03U << GPIO_CRH_CNF12_Pos) ///< CNF12[1:0] bits (portx configuration bits, pin 4) -#define GPIO_CRH_CNF12_0 (0x01U << GPIO_CRH_CNF12_Pos) ///< Bit 0 -#define GPIO_CRH_CNF12_1 (0x02U << GPIO_CRH_CNF12_Pos) ///< Bit 1 -#define GPIO_CRH_MODE13_Pos (20) -#define GPIO_CRH_MODE13 (0x03U << GPIO_CRH_MODE13_Pos) ///< MODE13[1:0] bits (portx mode bits, pin 5) -#define GPIO_CRH_MODE13_0 (0x01U << GPIO_CRH_MODE13_Pos) ///< Bit 0 -#define GPIO_CRH_MODE13_1 (0x02U << GPIO_CRH_MODE13_Pos) ///< Bit 1 -#define GPIO_CRH_CNF13_Pos (22) -#define GPIO_CRH_CNF13 (0x03U << GPIO_CRH_CNF13_Pos) ///< CNF13[1:0] bits (portx configuration bits, pin 5) -#define GPIO_CRH_CNF13_0 (0x01U << GPIO_CRH_CNF13_Pos) ///< Bit 0 -#define GPIO_CRH_CNF13_1 (0x02U << GPIO_CRH_CNF13_Pos) ///< Bit 1 -#define GPIO_CRH_MODE14_Pos (24) -#define GPIO_CRH_MODE14 (0x03U << GPIO_CRH_MODE14_Pos) ///< MODE14[1:0] bits (portx mode bits, pin 6) -#define GPIO_CRH_MODE14_0 (0x01U << GPIO_CRH_MODE14_Pos) ///< Bit 0 -#define GPIO_CRH_MODE14_1 (0x02U << GPIO_CRH_MODE14_Pos) ///< Bit 1 -#define GPIO_CRH_CNF14_Pos (26) -#define GPIO_CRH_CNF14 (0x03U << GPIO_CRH_CNF14_Pos) ///< CNF14[1:0] bits (portx configuration bits, pin 6) -#define GPIO_CRH_CNF14_0 (0x01U << GPIO_CRH_CNF14_Pos) ///< Bit 0 -#define GPIO_CRH_CNF14_1 (0x02U << GPIO_CRH_CNF14_Pos) ///< Bit 1 -#define GPIO_CRH_MODE15_Pos (28) -#define GPIO_CRH_MODE15 (0x03U << GPIO_CRH_MODE15_Pos) ///< MODE15[1:0] bits (portx mode bits, pin 7) -#define GPIO_CRH_MODE15_0 (0x01U << GPIO_CRH_MODE15_Pos) ///< Bit 0 -#define GPIO_CRH_MODE15_1 (0x02U << GPIO_CRH_MODE15_Pos) ///< Bit 1 -#define GPIO_CRH_CNF15_Pos (30) -#define GPIO_CRH_CNF15 (0x03U << GPIO_CRH_CNF15_Pos) ///< CNF15[1:0] bits (portx configuration bits, pin 7) -#define GPIO_CRH_CNF15_0 (0x01U << GPIO_CRH_CNF15_Pos) ///< Bit 0 -#define GPIO_CRH_CNF15_1 (0x02U << GPIO_CRH_CNF15_Pos) ///< Bit 1 - -//////////////////////////////////////////////////////////////////////////////// -/// @brief GPIO_IDR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define GPIO_IDR_DATA_Pos (0) -#define GPIO_IDR_DATA (0xFFFFU << GPIO_IDR_DATA_Pos) ///< Port input data -//////////////////////////////////////////////////////////////////////////////// -/// @brief GPIO_IDR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define GPIO_IDR_IDR0_Pos (0) -#define GPIO_IDR_IDR0 (0x01U << GPIO_IDR_IDR0_Pos) ///< Portx Set bit 0 -#define GPIO_IDR_IDR1_Pos (1) -#define GPIO_IDR_IDR1 (0x01U << GPIO_IDR_IDR1_Pos) ///< Portx Set bit 1 -#define GPIO_IDR_IDR2_Pos (2) -#define GPIO_IDR_IDR2 (0x01U << GPIO_IDR_IDR2_Pos) ///< Portx Set bit 2 -#define GPIO_IDR_IDR3_Pos (3) -#define GPIO_IDR_IDR3 (0x01U << GPIO_IDR_IDR3_Pos) ///< Portx Set bit 3 -#define GPIO_IDR_IDR4_Pos (4) -#define GPIO_IDR_IDR4 (0x01U << GPIO_IDR_IDR4_Pos) ///< Portx Set bit 4 -#define GPIO_IDR_IDR5_Pos (5) -#define GPIO_IDR_IDR5 (0x01U << GPIO_IDR_IDR5_Pos) ///< Portx Set bit 5 -#define GPIO_IDR_IDR6_Pos (6) -#define GPIO_IDR_IDR6 (0x01U << GPIO_IDR_IDR6_Pos) ///< Portx Set bit 6 -#define GPIO_IDR_IDR7_Pos (7) -#define GPIO_IDR_IDR7 (0x01U << GPIO_IDR_IDR7_Pos) ///< Portx Set bit 7 -#define GPIO_IDR_IDR8_Pos (8) -#define GPIO_IDR_IDR8 (0x01U << GPIO_IDR_IDR8_Pos) ///< Portx Set bit 8 -#define GPIO_IDR_IDR9_Pos (9) -#define GPIO_IDR_IDR9 (0x01U << GPIO_IDR_IDR9_Pos) ///< Portx Set bit 9 -#define GPIO_IDR_IDR10_Pos (10) -#define GPIO_IDR_IDR10 (0x01U << GPIO_IDR_IDR10_Pos) ///< Portx Set bit 10 -#define GPIO_IDR_IDR11_Pos (11) -#define GPIO_IDR_IDR11 (0x01U << GPIO_IDR_IDR11_Pos) ///< Portx Set bit 11 -#define GPIO_IDR_IDR12_Pos (12) -#define GPIO_IDR_IDR12 (0x01U << GPIO_IDR_IDR12_Pos) ///< Portx Set bit 12 -#define GPIO_IDR_IDR13_Pos (13) -#define GPIO_IDR_IDR13 (0x01U << GPIO_IDR_IDR13_Pos) ///< Portx Set bit 13 -#define GPIO_IDR_IDR14_Pos (14) -#define GPIO_IDR_IDR14 (0x01U << GPIO_IDR_IDR14_Pos) ///< Portx Set bit 14 -#define GPIO_IDR_IDR15_Pos (15) -#define GPIO_IDR_IDR15 (0x01U << GPIO_IDR_IDR15_Pos) ///< Portx Set bit 15 -//////////////////////////////////////////////////////////////////////////////// -/// @brief GPIO_ODR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define GPIO_ODR_DATA_Pos (0) -#define GPIO_ODR_DATA (0xFFFF << GPIO_ODR_DATA_Pos) ///< Port output data -//////////////////////////////////////////////////////////////////////////////// -/// @brief GPIO_ODR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define GPIO_ODR_ODR0_Pos (0) -#define GPIO_ODR_ODR0 (0x01U << GPIO_ODR_ODR0_Pos) ///< Portx Set bit 0 -#define GPIO_ODR_ODR1_Pos (1) -#define GPIO_ODR_ODR1 (0x01U << GPIO_ODR_ODR1_Pos) ///< Portx Set bit 1 -#define GPIO_ODR_ODR2_Pos (2) -#define GPIO_ODR_ODR2 (0x01U << GPIO_ODR_ODR2_Pos) ///< Portx Set bit 2 -#define GPIO_ODR_ODR3_Pos (3) -#define GPIO_ODR_ODR3 (0x01U << GPIO_ODR_ODR3_Pos) ///< Portx Set bit 3 -#define GPIO_ODR_ODR4_Pos (4) -#define GPIO_ODR_ODR4 (0x01U << GPIO_ODR_ODR4_Pos) ///< Portx Set bit 4 -#define GPIO_ODR_ODR5_Pos (5) -#define GPIO_ODR_ODR5 (0x01U << GPIO_ODR_ODR5_Pos) ///< Portx Set bit 5 -#define GPIO_ODR_ODR6_Pos (6) -#define GPIO_ODR_ODR6 (0x01U << GPIO_ODR_ODR6_Pos) ///< Portx Set bit 6 -#define GPIO_ODR_ODR7_Pos (7) -#define GPIO_ODR_ODR7 (0x01U << GPIO_ODR_ODR7_Pos) ///< Portx Set bit 7 -#define GPIO_ODR_ODR8_Pos (8) -#define GPIO_ODR_ODR8 (0x01U << GPIO_ODR_ODR8_Pos) ///< Portx Set bit 8 -#define GPIO_ODR_ODR9_Pos (9) -#define GPIO_ODR_ODR9 (0x01U << GPIO_ODR_ODR9_Pos) ///< Portx Set bit 9 -#define GPIO_ODR_ODR10_Pos (10) -#define GPIO_ODR_ODR10 (0x01U << GPIO_ODR_ODR10_Pos) ///< Portx Set bit 10 -#define GPIO_ODR_ODR11_Pos (11) -#define GPIO_ODR_ODR11 (0x01U << GPIO_ODR_ODR11_Pos) ///< Portx Set bit 11 -#define GPIO_ODR_ODR12_Pos (12) -#define GPIO_ODR_ODR12 (0x01U << GPIO_ODR_ODR12_Pos) ///< Portx Set bit 12 -#define GPIO_ODR_ODR13_Pos (13) -#define GPIO_ODR_ODR13 (0x01U << GPIO_ODR_ODR13_Pos) ///< Portx Set bit 13 -#define GPIO_ODR_ODR14_Pos (14) -#define GPIO_ODR_ODR14 (0x01U << GPIO_ODR_ODR14_Pos) ///< Portx Set bit 14 -#define GPIO_ODR_ODR15_Pos (15) -#define GPIO_ODR_ODR15 (0x01U << GPIO_ODR_ODR15_Pos) ///< Portx Set bit 15 - -//////////////////////////////////////////////////////////////////////////////// -/// @brief GPIO_BRR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define GPIO_BSRR_BS_Pos (0) -#define GPIO_BSRR_BS (0xFFFFU << GPIO_BSRR_BS_Pos) ///< Portx Reset -//////////////////////////////////////////////////////////////////////////////// -/// @brief GPIO_BSRR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define GPIO_BSRR_BS0_Pos (0) -#define GPIO_BSRR_BS0 (0x01U << GPIO_BSRR_BS0_Pos) ///< Portx Set bit 0 -#define GPIO_BSRR_BS1_Pos (1) -#define GPIO_BSRR_BS1 (0x01U << GPIO_BSRR_BS1_Pos) ///< Portx Set bit 1 -#define GPIO_BSRR_BS2_Pos (2) -#define GPIO_BSRR_BS2 (0x01U << GPIO_BSRR_BS2_Pos) ///< Portx Set bit 2 -#define GPIO_BSRR_BS3_Pos (3) -#define GPIO_BSRR_BS3 (0x01U << GPIO_BSRR_BS3_Pos) ///< Portx Set bit 3 -#define GPIO_BSRR_BS4_Pos (4) -#define GPIO_BSRR_BS4 (0x01U << GPIO_BSRR_BS4_Pos) ///< Portx Set bit 4 -#define GPIO_BSRR_BS5_Pos (5) -#define GPIO_BSRR_BS5 (0x01U << GPIO_BSRR_BS5_Pos) ///< Portx Set bit 5 -#define GPIO_BSRR_BS6_Pos (6) -#define GPIO_BSRR_BS6 (0x01U << GPIO_BSRR_BS6_Pos) ///< Portx Set bit 6 -#define GPIO_BSRR_BS7_Pos (7) -#define GPIO_BSRR_BS7 (0x01U << GPIO_BSRR_BS7_Pos) ///< Portx Set bit 7 -#define GPIO_BSRR_BS8_Pos (8) -#define GPIO_BSRR_BS8 (0x01U << GPIO_BSRR_BS8_Pos) ///< Portx Set bit 8 -#define GPIO_BSRR_BS9_Pos (9) -#define GPIO_BSRR_BS9 (0x01U << GPIO_BSRR_BS9_Pos) ///< Portx Set bit 9 -#define GPIO_BSRR_BS10_Pos (10) -#define GPIO_BSRR_BS10 (0x01U << GPIO_BSRR_BS10_Pos) ///< Portx Set bit 10 -#define GPIO_BSRR_BS11_Pos (11) -#define GPIO_BSRR_BS11 (0x01U << GPIO_BSRR_BS11_Pos) ///< Portx Set bit 11 -#define GPIO_BSRR_BS12_Pos (12) -#define GPIO_BSRR_BS12 (0x01U << GPIO_BSRR_BS12_Pos) ///< Portx Set bit 12 -#define GPIO_BSRR_BS13_Pos (13) -#define GPIO_BSRR_BS13 (0x01U << GPIO_BSRR_BS13_Pos) ///< Portx Set bit 13 -#define GPIO_BSRR_BS14_Pos (14) -#define GPIO_BSRR_BS14 (0x01U << GPIO_BSRR_BS14_Pos) ///< Portx Set bit 14 -#define GPIO_BSRR_BS15_Pos (15) -#define GPIO_BSRR_BS15 (0x01U << GPIO_BSRR_BS15_Pos) ///< Portx Set bit 15 - -#define GPIO_BSRR_BR0_Pos (16) -#define GPIO_BSRR_BR0 (0x01U << GPIO_BSRR_BR0_Pos) ///< Portx Reset bit 0 -#define GPIO_BSRR_BR1_Pos (17) -#define GPIO_BSRR_BR1 (0x01U << GPIO_BSRR_BR1_Pos) ///< Portx Reset bit 1 -#define GPIO_BSRR_BR2_Pos (18) -#define GPIO_BSRR_BR2 (0x01U << GPIO_BSRR_BR2_Pos) ///< Portx Reset bit 2 -#define GPIO_BSRR_BR3_Pos (19) -#define GPIO_BSRR_BR3 (0x01U << GPIO_BSRR_BR3_Pos) ///< Portx Reset bit 3 -#define GPIO_BSRR_BR4_Pos (20) -#define GPIO_BSRR_BR4 (0x01U << GPIO_BSRR_BR4_Pos) ///< Portx Reset bit 4 -#define GPIO_BSRR_BR5_Pos (21) -#define GPIO_BSRR_BR5 (0x01U << GPIO_BSRR_BR5_Pos) ///< Portx Reset bit 5 -#define GPIO_BSRR_BR6_Pos (22) -#define GPIO_BSRR_BR6 (0x01U << GPIO_BSRR_BR6_Pos) ///< Portx Reset bit 6 -#define GPIO_BSRR_BR7_Pos (23) -#define GPIO_BSRR_BR7 (0x01U << GPIO_BSRR_BR7_Pos) ///< Portx Reset bit 7 -#define GPIO_BSRR_BR8_Pos (24) -#define GPIO_BSRR_BR8 (0x01U << GPIO_BSRR_BR8_Pos) ///< Portx Reset bit 8 -#define GPIO_BSRR_BR9_Pos (25) -#define GPIO_BSRR_BR9 (0x01U << GPIO_BSRR_BR9_Pos) ///< Portx Reset bit 9 -#define GPIO_BSRR_BR10_Pos (26) -#define GPIO_BSRR_BR10 (0x01U << GPIO_BSRR_BR10_Pos) ///< Portx Reset bit 10 -#define GPIO_BSRR_BR11_Pos (27) -#define GPIO_BSRR_BR11 (0x01U << GPIO_BSRR_BR11_Pos) ///< Portx Reset bit 11 -#define GPIO_BSRR_BR12_Pos (28) -#define GPIO_BSRR_BR12 (0x01U << GPIO_BSRR_BR12_Pos) ///< Portx Reset bit 12 -#define GPIO_BSRR_BR13_Pos (29) -#define GPIO_BSRR_BR13 (0x01U << GPIO_BSRR_BR13_Pos) ///< Portx Reset bit 13 -#define GPIO_BSRR_BR14_Pos (30) -#define GPIO_BSRR_BR14 (0x01U << GPIO_BSRR_BR14_Pos) ///< Portx Reset bit 14 -#define GPIO_BSRR_BR15_Pos (31) -#define GPIO_BSRR_BR15 (0x01U << GPIO_BSRR_BR15_Pos) ///< Portx Reset bit 15 - -//////////////////////////////////////////////////////////////////////////////// -/// @brief GPIO_BRR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define GPIO_BRR_BR_Pos (0) -#define GPIO_BRR_BR (0xFFFFU << GPIO_BRR_BR_Pos) ///< Portx Reset - -//////////////////////////////////////////////////////////////////////////////// -/// @brief GPIO_BRR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define GPIO_BRR_BR0_Pos (0) -#define GPIO_BRR_BR0 (0x01U << GPIO_BRR_BR0_Pos) ///< Portx Set bit 0 -#define GPIO_BRR_BR1_Pos (1) -#define GPIO_BRR_BR1 (0x01U << GPIO_BRR_BR1_Pos) ///< Portx Set bit 1 -#define GPIO_BRR_BR2_Pos (2) -#define GPIO_BRR_BR2 (0x01U << GPIO_BRR_BR2_Pos) ///< Portx Set bit 2 -#define GPIO_BRR_BR3_Pos (3) -#define GPIO_BRR_BR3 (0x01U << GPIO_BRR_BR3_Pos) ///< Portx Set bit 3 -#define GPIO_BRR_BR4_Pos (4) -#define GPIO_BRR_BR4 (0x01U << GPIO_BRR_BR4_Pos) ///< Portx Set bit 4 -#define GPIO_BRR_BR5_Pos (5) -#define GPIO_BRR_BR5 (0x01U << GPIO_BRR_BR5_Pos) ///< Portx Set bit 5 -#define GPIO_BRR_BR6_Pos (6) -#define GPIO_BRR_BR6 (0x01U << GPIO_BRR_BR6_Pos) ///< Portx Set bit 6 -#define GPIO_BRR_BR7_Pos (7) -#define GPIO_BRR_BR7 (0x01U << GPIO_BRR_BR7_Pos) ///< Portx Set bit 7 -#define GPIO_BRR_BR8_Pos (8) -#define GPIO_BRR_BR8 (0x01U << GPIO_BRR_BR8_Pos) ///< Portx Set bit 8 -#define GPIO_BRR_BR9_Pos (9) -#define GPIO_BRR_BR9 (0x01U << GPIO_BRR_BR9_Pos) ///< Portx Set bit 9 -#define GPIO_BRR_BR10_Pos (10) -#define GPIO_BRR_BR10 (0x01U << GPIO_BRR_BR10_Pos) ///< Portx Set bit 10 -#define GPIO_BRR_BR11_Pos (11) -#define GPIO_BRR_BR11 (0x01U << GPIO_BRR_BR11_Pos) ///< Portx Set bit 11 -#define GPIO_BRR_BR12_Pos (12) -#define GPIO_BRR_BR12 (0x01U << GPIO_BRR_BR12_Pos) ///< Portx Set bit 12 -#define GPIO_BRR_BR13_Pos (13) -#define GPIO_BRR_BR13 (0x01U << GPIO_BRR_BR13_Pos) ///< Portx Set bit 13 -#define GPIO_BRR_BR14_Pos (14) -#define GPIO_BRR_BR14 (0x01U << GPIO_BRR_BR14_Pos) ///< Portx Set bit 14 -#define GPIO_BRR_BR15_Pos (15) -#define GPIO_BRR_BR15 (0x01U << GPIO_BRR_BR15_Pos) ///< Portx Set bit 15 - -//////////////////////////////////////////////////////////////////////////////// -/// @brief GPIO_LCKR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define GPIO_LCKR_LCK_Pos (0) -#define GPIO_LCKR_LCK (0xFFFFU << GPIO_LCKR_LCK_Pos) ///< Portx Lock -#define GPIO_LCKR_LCKK_Pos (16) -#define GPIO_LCKR_LCKK (0x01U << GPIO_LCKR_LCKK_Pos) ///< Lock key - -//////////////////////////////////////////////////////////////////////////////// -/// @brief GPIO_LCKR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define GPIO_LCKR_LCK0_Pos (0) -#define GPIO_LCKR_LCK0 (0x01U << GPIO_LCKR_LCK0_Pos) ///< Portx Set bit 0 -#define GPIO_LCKR_LCK1_Pos (1) -#define GPIO_LCKR_LCK1 (0x01U << GPIO_LCKR_LCK1_Pos) ///< Portx Set bit 1 -#define GPIO_LCKR_LCK2_Pos (2) -#define GPIO_LCKR_LCK2 (0x01U << GPIO_LCKR_LCK2_Pos) ///< Portx Set bit 2 -#define GPIO_LCKR_LCK3_Pos (3) -#define GPIO_LCKR_LCK3 (0x01U << GPIO_LCKR_LCK3_Pos) ///< Portx Set bit 3 -#define GPIO_LCKR_LCK4_Pos (4) -#define GPIO_LCKR_LCK4 (0x01U << GPIO_LCKR_LCK4_Pos) ///< Portx Set bit 4 -#define GPIO_LCKR_LCK5_Pos (5) -#define GPIO_LCKR_LCK5 (0x01U << GPIO_LCKR_LCK5_Pos) ///< Portx Set bit 5 -#define GPIO_LCKR_LCK6_Pos (6) -#define GPIO_LCKR_LCK6 (0x01U << GPIO_LCKR_LCK6_Pos) ///< Portx Set bit 6 -#define GPIO_LCKR_LCK7_Pos (7) -#define GPIO_LCKR_LCK7 (0x01U << GPIO_LCKR_LCK7_Pos) ///< Portx Set bit 7 -#define GPIO_LCKR_LCK8_Pos (8) -#define GPIO_LCKR_LCK8 (0x01U << GPIO_LCKR_LCK8_Pos) ///< Portx Set bit 8 -#define GPIO_LCKR_LCK9_Pos (9) -#define GPIO_LCKR_LCK9 (0x01U << GPIO_LCKR_LCK9_Pos) ///< Portx Set bit 9 -#define GPIO_LCKR_LCK10_Pos (10) -#define GPIO_LCKR_LCK10 (0x01U << GPIO_LCKR_LCK10_Pos) ///< Portx Set bit 10 -#define GPIO_LCKR_LCK11_Pos (11) -#define GPIO_LCKR_LCK11 (0x01U << GPIO_LCKR_LCK11_Pos) ///< Portx Set bit 11 -#define GPIO_LCKR_LCK12_Pos (12) -#define GPIO_LCKR_LCK12 (0x01U << GPIO_LCKR_LCK12_Pos) ///< Portx Set bit 12 -#define GPIO_LCKR_LCK13_Pos (13) -#define GPIO_LCKR_LCK13 (0x01U << GPIO_LCKR_LCK13_Pos) ///< Portx Set bit 13 -#define GPIO_LCKR_LCK14_Pos (14) -#define GPIO_LCKR_LCK14 (0x01U << GPIO_LCKR_LCK14_Pos) ///< Portx Set bit 14 -#define GPIO_LCKR_LCK15_Pos (15) -#define GPIO_LCKR_LCK15 (0x01U << GPIO_LCKR_LCK15_Pos) ///< Portx Set bit 15 - -//////////////////////////////////////////////////////////////////////////////// -/// @brief GPIO_DCR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define GPIO_DCR_PX0_Pos (0) -#define GPIO_DCR_PX0 (0x03U << GPIO_DCR_PX0_Pos) ///< PX0[1:0] bits (pinx configuration bits, pin 0) -#define GPIO_DCR_PX0_MODE0 (0x00U << GPIO_DCR_PX0_Pos) ///< Mode = 0 -#define GPIO_DCR_PX0_MODE1 (0x01U << GPIO_DCR_PX0_Pos) ///< Mode = 1 -#define GPIO_DCR_PX0_MODE2 (0x02U << GPIO_DCR_PX0_Pos) ///< Mode = 2 -#define GPIO_DCR_PX0_MODE3 (0x03U << GPIO_DCR_PX0_Pos) ///< Mode = 3 -#define GPIO_DCR_PX1_Pos (2) -#define GPIO_DCR_PX1 (0x03U << GPIO_DCR_PX1_Pos) ///< PX1[1:0] bits (pinx configuration bits, pin 1) -#define GPIO_DCR_PX1_MODE0 (0x00U << GPIO_DCR_PX1_Pos) ///< Mode = 0 -#define GPIO_DCR_PX1_MODE1 (0x01U << GPIO_DCR_PX1_Pos) ///< Mode = 1 -#define GPIO_DCR_PX1_MODE2 (0x02U << GPIO_DCR_PX1_Pos) ///< Mode = 2 -#define GPIO_DCR_PX1_MODE3 (0x03U << GPIO_DCR_PX1_Pos) ///< Mode = 3 -#define GPIO_DCR_PX2_Pos (4) -#define GPIO_DCR_PX2 (0x03U << GPIO_DCR_PX2_Pos) ///< PX2[1:0] bits (pinx configuration bits, pin 2) -#define GPIO_DCR_PX2_MODE0 (0x00U << GPIO_DCR_PX2_Pos) ///< Mode = 0 -#define GPIO_DCR_PX2_MODE1 (0x01U << GPIO_DCR_PX2_Pos) ///< Mode = 1 -#define GPIO_DCR_PX2_MODE2 (0x02U << GPIO_DCR_PX2_Pos) ///< Mode = 2 -#define GPIO_DCR_PX2_MODE3 (0x03U << GPIO_DCR_PX2_Pos) ///< Mode = 3 -#define GPIO_DCR_PX3_Pos (6) -#define GPIO_DCR_PX3 (0x03U << GPIO_DCR_PX3_Pos) ///< PX3[1:0] bits (pinx configuration bits, pin 3) -#define GPIO_DCR_PX3_MODE0 (0x00U << GPIO_DCR_PX3_Pos) ///< Mode = 0 -#define GPIO_DCR_PX3_MODE1 (0x01U << GPIO_DCR_PX3_Pos) ///< Mode = 1 -#define GPIO_DCR_PX3_MODE2 (0x02U << GPIO_DCR_PX3_Pos) ///< Mode = 2 -#define GPIO_DCR_PX3_MODE3 (0x03U << GPIO_DCR_PX3_Pos) ///< Mode = 3 - -#define GPIO_DCR_PX4_Pos (8) -#define GPIO_DCR_PX4 (0x03U << GPIO_DCR_PX4_Pos) ///< PX4[1:0] bits (pinx configuration bits, pin 4) -#define GPIO_DCR_PX4_MODE0 (0x00U << GPIO_DCR_PX4_Pos) ///< Mode = 0 -#define GPIO_DCR_PX4_MODE1 (0x01U << GPIO_DCR_PX4_Pos) ///< Mode = 1 -#define GPIO_DCR_PX4_MODE2 (0x02U << GPIO_DCR_PX4_Pos) ///< Mode = 2 -#define GPIO_DCR_PX4_MODE3 (0x03U << GPIO_DCR_PX4_Pos) ///< Mode = 3 - -#define GPIO_DCR_PX5_Pos (10) -#define GPIO_DCR_PX5 (0x03U << GPIO_DCR_PX5_Pos) ///< PX5[1:0] bits (pinx configuration bits, pin 5) -#define GPIO_DCR_PX5_MODE0 (0x00U << GPIO_DCR_PX5_Pos) ///< Mode = 0 -#define GPIO_DCR_PX5_MODE1 (0x01U << GPIO_DCR_PX5_Pos) ///< Mode = 1 -#define GPIO_DCR_PX5_MODE2 (0x02U << GPIO_DCR_PX5_Pos) ///< Mode = 2 -#define GPIO_DCR_PX5_MODE3 (0x03U << GPIO_DCR_PX5_Pos) ///< Mode = 3 - -#define GPIO_DCR_PX6_Pos (12) -#define GPIO_DCR_PX6 (0x03U << GPIO_DCR_PX6_Pos) ///< PX6[1:0] bits (pinx configuration bits, pin 6) -#define GPIO_DCR_PX6_MODE0 (0x00U << GPIO_DCR_PX6_Pos) ///< Mode = 0 -#define GPIO_DCR_PX6_MODE1 (0x01U << GPIO_DCR_PX6_Pos) ///< Mode = 1 -#define GPIO_DCR_PX6_MODE2 (0x02U << GPIO_DCR_PX6_Pos) ///< Mode = 2 -#define GPIO_DCR_PX6_MODE3 (0x03U << GPIO_DCR_PX6_Pos) ///< Mode = 3 - -#define GPIO_DCR_PX7_Pos (14) -#define GPIO_DCR_PX7 (0x03U << GPIO_DCR_PX7_Pos) ///< PX7[1:0] bits (pinx configuration bits, pin 7) -#define GPIO_DCR_PX7_MODE0 (0x00U << GPIO_DCR_PX7_Pos) ///< Mode = 0 -#define GPIO_DCR_PX7_MODE1 (0x01U << GPIO_DCR_PX7_Pos) ///< Mode = 1 -#define GPIO_DCR_PX7_MODE2 (0x02U << GPIO_DCR_PX7_Pos) ///< Mode = 2 -#define GPIO_DCR_PX7_MODE3 (0x03U << GPIO_DCR_PX7_Pos) ///< Mode = 3 - -#define GPIO_DCR_PX8_Pos (16) -#define GPIO_DCR_PX8 (0x03U << GPIO_DCR_PX8_Pos) ///< PX8[1:0] bits (pinx configuration bits, pin 8) -#define GPIO_DCR_PX8_MODE0 (0x00U << GPIO_DCR_PX8_Pos) ///< Mode = 0 -#define GPIO_DCR_PX8_MODE1 (0x01U << GPIO_DCR_PX8_Pos) ///< Mode = 1 -#define GPIO_DCR_PX8_MODE2 (0x02U << GPIO_DCR_PX8_Pos) ///< Mode = 2 -#define GPIO_DCR_PX8_MODE3 (0x03U << GPIO_DCR_PX8_Pos) ///< Mode = 3 - -#define GPIO_DCR_PX9_Pos (18) -#define GPIO_DCR_PX9 (0x03U << GPIO_DCR_PX9_Pos) ///< PX9[1:0] bits (pinx configuration bits, pin 9) -#define GPIO_DCR_PX9_MODE0 (0x00U << GPIO_DCR_PX9_Pos) ///< Mode = 0 -#define GPIO_DCR_PX9_MODE1 (0x01U << GPIO_DCR_PX9_Pos) ///< Mode = 1 -#define GPIO_DCR_PX9_MODE2 (0x02U << GPIO_DCR_PX9_Pos) ///< Mode = 2 -#define GPIO_DCR_PX9_MODE3 (0x03U << GPIO_DCR_PX9_Pos) ///< Mode = 3 - -#define GPIO_DCR_PX10_Pos (20) -#define GPIO_DCR_PX10 (0x03U << GPIO_DCR_PX10_Pos) ///< PX10[1:0] bits (pinx configuration bits, pin 10) -#define GPIO_DCR_PX10_MODE0 (0x00U << GPIO_DCR_PX10_Pos) ///< Mode = 0 -#define GPIO_DCR_PX10_MODE1 (0x01U << GPIO_DCR_PX10_Pos) ///< Mode = 1 -#define GPIO_DCR_PX10_MODE2 (0x02U << GPIO_DCR_PX10_Pos) ///< Mode = 2 -#define GPIO_DCR_PX10_MODE3 (0x03U << GPIO_DCR_PX10_Pos) ///< Mode = 3 - -#define GPIO_DCR_PX11_Pos (22) -#define GPIO_DCR_PX11 (0x03U << GPIO_DCR_PX11_Pos) ///< PX11[1:0] bits (pinx configuration bits, pin 11) -#define GPIO_DCR_PX11_MODE0 (0x00U << GPIO_DCR_PX11_Pos) ///< Mode = 0 -#define GPIO_DCR_PX11_MODE1 (0x01U << GPIO_DCR_PX11_Pos) ///< Mode = 1 -#define GPIO_DCR_PX11_MODE2 (0x02U << GPIO_DCR_PX11_Pos) ///< Mode = 2 -#define GPIO_DCR_PX11_MODE3 (0x03U << GPIO_DCR_PX11_Pos) ///< Mode = 3 -#define GPIO_DCR_PX12_Pos (24) -#define GPIO_DCR_PX12 (0x03U << GPIO_DCR_PX12_Pos) ///< PX12[1:0] bits (pinx configuration bits, pin 12) -#define GPIO_DCR_PX12_MODE0 (0x00U << GPIO_DCR_PX12_Pos) ///< Mode = 0 -#define GPIO_DCR_PX12_MODE1 (0x01U << GPIO_DCR_PX12_Pos) ///< Mode = 1 -#define GPIO_DCR_PX12_MODE2 (0x02U << GPIO_DCR_PX12_Pos) ///< Mode = 2 -#define GPIO_DCR_PX12_MODE3 (0x03U << GPIO_DCR_PX12_Pos) ///< Mode = 3 -#define GPIO_DCR_PX13_Pos (26) -#define GPIO_DCR_PX13 (0x03U << GPIO_DCR_PX13_Pos) ///< PX13[1:0] bits (pinx configuration bits, pin 13) -#define GPIO_DCR_PX13_MODE0 (0x00U << GPIO_DCR_PX13_Pos) ///< Mode = 0 -#define GPIO_DCR_PX13_MODE1 (0x01U << GPIO_DCR_PX13_Pos) ///< Mode = 1 -#define GPIO_DCR_PX13_MODE2 (0x02U << GPIO_DCR_PX13_Pos) ///< Mode = 2 -#define GPIO_DCR_PX13_MODE3 (0x03U << GPIO_DCR_PX13_Pos) ///< Mode = 3 - -#define GPIO_DCR_PX14_Pos (28) -#define GPIO_DCR_PX14 (0x03U << GPIO_DCR_PX14_Pos) ///< PX14[1:0] bits (pinx configuration bits, pin 14) -#define GPIO_DCR_PX14_MODE0 (0x00U << GPIO_DCR_PX14_Pos) ///< Mode = 0 -#define GPIO_DCR_PX14_MODE1 (0x01U << GPIO_DCR_PX14_Pos) ///< Mode = 1 -#define GPIO_DCR_PX14_MODE2 (0x02U << GPIO_DCR_PX14_Pos) ///< Mode = 2 -#define GPIO_DCR_PX14_MODE3 (0x03U << GPIO_DCR_PX14_Pos) ///< Mode = 3 -#define GPIO_DCR_PX15_Pos (30) -#define GPIO_DCR_PX15 (0x03U << GPIO_DCR_PX15_Pos) ///< PX15[1:0] bits (pinx configuration bits, pin 15) -#define GPIO_DCR_PX15_MODE0 (0x00U << GPIO_DCR_PX15_Pos) ///< Mode = 0 -#define GPIO_DCR_PX15_MODE1 (0x01U << GPIO_DCR_PX15_Pos) ///< Mode = 1 -#define GPIO_DCR_PX15_MODE2 (0x02U << GPIO_DCR_PX15_Pos) ///< Mode = 2 -#define GPIO_DCR_PX15_MODE3 (0x03U << GPIO_DCR_PX15_Pos) ///< Mode = 3 -//////////////////////////////////////////////////////////////////////////////// -/// @brief GPIO_AFRL Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define GPIO_AFRL_AFR0_Pos (0) -#define GPIO_AFRL_AFR0 (0x0FU << GPIO_AFRL_AFR0_Pos) ///< Multiplexing function selection for bit 0 of portx -#define GPIO_AFRL_AFR1_Pos (4) -#define GPIO_AFRL_AFR1 (0x0FU << GPIO_AFRL_AFR1_Pos) ///< Multiplexing function selection for bit 1 of portx -#define GPIO_AFRL_AFR2_Pos (8) -#define GPIO_AFRL_AFR2 (0x0FU << GPIO_AFRL_AFR2_Pos) ///< Multiplexing function selection for bit 2 of portx -#define GPIO_AFRL_AFR3_Pos (12) -#define GPIO_AFRL_AFR3 (0x0FU << GPIO_AFRL_AFR3_Pos) ///< Multiplexing function selection for bit 3 of portx -#define GPIO_AFRL_AFR4_Pos (16) -#define GPIO_AFRL_AFR4 (0x0FU << GPIO_AFRL_AFR4_Pos) ///< Multiplexing function selection for bit 4 of portx -#define GPIO_AFRL_AFR5_Pos (20) -#define GPIO_AFRL_AFR5 (0x0FU << GPIO_AFRL_AFR5_Pos) ///< Multiplexing function selection for bit 5 of portx -#define GPIO_AFRL_AFR6_Pos (24) -#define GPIO_AFRL_AFR6 (0x0FU << GPIO_AFRL_AFR6_Pos) ///< Multiplexing function selection for bit 6 of portx -#define GPIO_AFRL_AFR7_Pos (28) -#define GPIO_AFRL_AFR7 (0x0FU << GPIO_AFRL_AFR7_Pos) ///< Multiplexing function selection for bit 7 of portx - -//////////////////////////////////////////////////////////////////////////////// -/// @brief GPIO_AFRH Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define GPIO_AFRH_AFR8_Pos (0) -#define GPIO_AFRH_AFR8 (0x0FU << GPIO_AFRH_AFR8_Pos) ///< Multiplexing function selection for bit 8 of portx -#define GPIO_AFRH_AFR9_Pos (4) -#define GPIO_AFRH_AFR9 (0x0FU << GPIO_AFRH_AFR9_Pos) ///< Multiplexing function selection for bit 9 of portx -#define GPIO_AFRH_AFR10_Pos (8) -#define GPIO_AFRH_AFR10 (0x0FU << GPIO_AFRH_AFR10_Pos) ///< Multiplexing function selection for bit 10 of portx -#define GPIO_AFRH_AFR11_Pos (12) -#define GPIO_AFRH_AFR11 (0x0FU << GPIO_AFRH_AFR11_Pos) ///< Multiplexing function selection for bit 11 of portx -#define GPIO_AFRH_AFR12_Pos (16) -#define GPIO_AFRH_AFR12 (0x0FU << GPIO_AFRH_AFR12_Pos) ///< Multiplexing function selection for bit 12 of portx -#define GPIO_AFRH_AFR13_Pos (20) -#define GPIO_AFRH_AFR13 (0x0FU << GPIO_AFRH_AFR13_Pos) ///< Multiplexing function selection for bit 13 of portx -#define GPIO_AFRH_AFR14_Pos (24) -#define GPIO_AFRH_AFR14 (0x0FU << GPIO_AFRH_AFR14_Pos) ///< Multiplexing function selection for bit 14 of portx -#define GPIO_AFRH_AFR15_Pos (28) -#define GPIO_AFRH_AFR15 (0x0FU << GPIO_AFRH_AFR15_Pos) ///< Multiplexing function selection for bit 15 of portx -#define GPIO_AF_MODEMASK (0x0FU) ///< Mode = 0 -#define GPIO_AF_MODE0 (0x00U) ///< Mode = 0 -#define GPIO_AF_MODE1 (0x01U) ///< Mode = 1 -#define GPIO_AF_MODE2 (0x02U) ///< Mode = 2 -#define GPIO_AF_MODE3 (0x03U) ///< Mode = 3 -#define GPIO_AF_MODE4 (0x04U) ///< Mode = 4 -#define GPIO_AF_MODE5 (0x05U) ///< Mode = 5 -#define GPIO_AF_MODE6 (0x06U) ///< Mode = 6 -#define GPIO_AF_MODE7 (0x07U) ///< Mode = 7 -#define GPIO_AF_MODE8 (0x08U) ///< Mode = 8 -#define GPIO_AF_MODE9 (0x09U) ///< Mode = 9 -#define GPIO_AF_MODE10 (0x0AU) ///< Mode = 10 -#define GPIO_AF_MODE11 (0x0BU) ///< Mode = 11 -#define GPIO_AF_MODE12 (0x0CU) ///< Mode = 12 -#define GPIO_AF_MODE13 (0x0DU) ///< Mode = 13 -#define GPIO_AF_MODE14 (0x0EU) ///< Mode = 14 -#define GPIO_AF_MODE15 (0x0FU) ///< Mode = 15 - - - - -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -#endif -//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_i2c.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_i2c.h deleted file mode 100644 index e12f107e3..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_i2c.h +++ /dev/null @@ -1,635 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file reg_i2c.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF -/// MM32 FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion - -#ifndef __REG_I2C_H -#define __REG_I2C_H - -// Files includes - -#include -#include -#include "types.h" - - - - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - - - - - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief I2C Base Address Definition -//////////////////////////////////////////////////////////////////////////////// -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) ///< Base Address: 0x40005400 -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) ///< Base Address: 0x40005800 - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief I2C Register Structure Definition -//////////////////////////////////////////////////////////////////////////////// -#undef USENCOMBINEREGISTER -#undef USENNEWREGISTER -#undef USENOLDREGISTER -#define USENCOMBINEREGISTER -#ifdef USENCOMBINEREGISTER -typedef struct { - union { - __IO u32 CR; ///< Control Register offset: 0x00 - __IO u32 IC_CON; - }; - union { - __IO u32 TAR; ///< Target Address Register offset: 0x04 - __IO u32 IC_TAR; - }; - union { - __IO u32 SAR; ///< Slave Address Register offset: 0x08 - __IO u32 IC_SAR; - }; - __IO u32 IC_HS_MADDR_RESERVED; ///< Reserved Register offset: 0x0C - union { - __IO u32 DR; ///< Data Command Register offset: 0x10 - __IO u32 IC_DATA_CMD; - }; - union { - __IO u32 SSHR; ///< SCL High Period Count for Std. Speed Register offset: 0x14 - __IO u32 IC_SS_SCL_HCNT; - }; - union { - __IO u32 SSLR; ///< SCL Low Period Count for Std. Speed Register offset: 0x18 - __IO u32 IC_SS_SCL_LCNT; - }; - union { - __IO u32 FSHR; ///< SCL High Period Count for Fast Speed Register offset: 0x1C - __IO u32 IC_FS_SCL_HCNT; - }; - union { - __IO u32 FSLR; ///< SCL Low Period Count for Fast Speed Register offset: 0x20 - __IO u32 IC_FS_SCL_LCNT; - }; - __IO u32 IC_HS_SCL_HCNT_RESERVED; ///< Reserved Register offset: 0x24 - __IO u32 IC_HS_SCL_LCNT_RESERVED; ///< Reserved Register offset: 0x28 - union { - __IO u32 ISR; ///< Interrupt Status Register offset: 0x2C - __IO u32 IC_INTR_STAT; - }; - union { - __IO u32 IMR; ///< Interrupt Mask Register offset: 0x30 - __IO u32 IC_INTR_MASK; - }; - union { - __IO u32 RAWISR; ///< RAW Interrupt Status Register offset: 0x34 - __IO u32 IC_RAW_INTR_STAT; - }; - union { - __IO u32 RXTLR; ///< Receive FIFO Threshold Level Register offset: 0x38 - __IO u32 IC_RX_TL; - }; - union { - __IO u32 TXTLR; ///< Transmit FIFO Threshold Level Register offset: 0x3C - __IO u32 IC_TX_TL; - }; - union { - __IO u32 ICR; ///< Clear All Interrupt Register offset: 0x40 - __IO u32 IC_CLR_INTR; - }; - union { - __IO u32 RX_UNDER; ///< Clear RX_UNDER Interrupt Register offset: 0x44 - __IO u32 IC_CLR_RX_UNDER; - }; - union { - __IO u32 RX_OVER; ///< Clear RX_OVER Interrupt Register offset: 0x48 - __IO u32 IC_CLR_RX_OVER; - }; - union { - __IO u32 TX_OVER; ///< Clear TX_OVER Interrupt Register offset: 0x4C - __IO u32 IC_CLR_TX_OVER; - }; - union { - __IO u32 RD_REQ; ///< Clear RD_REQ Interrupt Register offset: 0x50 - __IO u32 IC_CLR_RD_REQ; - }; - union { - __IO u32 TX_ABRT; ///< Clear TX_ABRT Interrupt Register offset: 0x54 - __IO u32 IC_CLR_TX_ABRT; - }; - union { - __IO u32 RX_DONE; ///< Clear RX_DONE Interrupt Register offset: 0x58 - __IO u32 IC_CLR_RX_DONE; - }; - union { - __IO u32 ACTIV; ///< Clear ACTIVITY Interrupt Register offset: 0x5C - __IO u32 IC_CLR_ACTIVITY; - }; - union { - __IO u32 STOP; ///< Clear STOP_DET Interrupt Register offset: 0x60 - __IO u32 IC_CLR_STOP_DET; - }; - union { - __IO u32 START; ///< Clear START_DET Interrupt Register offset: 0x64 - __IO u32 IC_CLR_START_DET; - }; - union { - __IO u32 GC; ///< Clear GEN_CALL Interrupt Register offset: 0x68 - __IO u32 IC_CLR_GEN_CALL; - }; - union { - __IO u32 ENR; ///< Enable Register offset: 0x6C - __IO u32 IC_ENABLE; - }; - union { - __IO u32 SR; ///< Status Register offset: 0x70 - __IO u32 IC_STATUS; - }; - union { - __IO u32 TXFLR; ///< Transmit FIFO Level Register offset: 0x74 - __IO u32 IC_TXFLR; - }; - union { - __IO u32 RXFLR; ///< Receive FIFO Level Register offset: 0x78 - __IO u32 IC_RXFLR; - }; - union { - __IO u32 HOLD; ///< SDA Hold Time Register offset: 0x7C - __IO u32 IC_SDA_HOLD; - }; - __IO u32 RESERVED28; ///IC_TX_ABRT_SOURCE_RESERVED; - __IO u32 RESERVED29; ///IC_SLV_DATA_NACK_ONLY_RESERVED; - - union { - __IO u32 DMA; ///< DMA Control Register offset: 0x88 - __IO u32 IC_DMA_CR; - }; - __IO u32 RESERVED30; ///IC_DMA_TDLR_RESERVED; - __IO u32 RESERVED31; ///IC_DMA_RDLR_RESERVED; - union { - __IO u32 SETUP; ///< SDA Setup Time Register offset: 0x94 - __IO u32 IC_SDA_SETUP; - }; - union { - __IO u32 GCR; ///< ACK General Call Register offset: 0x98 - __IO u32 IC_ACK_GENERAL_CALL; - }; - __IO u32 RESERVED32a; ///_RESERVED; offset: 0x9C - __IO u32 RESERVED33; ///_RESERVED; offset: 0xA0 - __IO u32 RESERVED34; ///_RESERVED; offset: 0xA4 - __IO u32 RESERVED35; ///_RESERVED; offset: 0xA8 - __IO u32 RESERVED36; ///_RESERVED; offset: 0xAC     - __IO u32 SLVMASK; ///
© COPYRIGHT MINDMOTION
-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion - -#ifndef __REG_IWDG_H -#define __REG_IWDG_H - -// Files includes - -#include -#include -#include "types.h" - - - - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief IWDG Base Address Definition -//////////////////////////////////////////////////////////////////////////////// -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) ///< Base Address: 0x40003000 - -//////////////////////////////////////////////////////////////////////////////// -/// @brief IWDG Register Structure Definition -//////////////////////////////////////////////////////////////////////////////// -typedef struct { - __IO u32 KR; ///< Key Register offset: 0x00 - __IO u32 PR; ///< Prescaler Register offset: 0x04 - __IO u32 RLR; ///< Reload Register offset: 0x08 - __IO u32 SR; ///< Status Register offset: 0x0C - __IO u32 CR; ///< Control Register offset: 0x10 - __IO u32 IGEN; ///< Interrupt Generator Register offset: 0x14 - __IO u32 CNT; ///< Interrupt Generator count Register offset: 0x18 - __IO u32 PS; ///< Prescaler count Register offset: 0x1C -} IWDG_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief IWDG type pointer Definition -//////////////////////////////////////////////////////////////////////////////// -#define IWDG ((IWDG_TypeDef*) IWDG_BASE) - -//////////////////////////////////////////////////////////////////////////////// -/// @brief IWDG_KR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define IWDG_KEYR_KEY_Pos (0) -#define IWDG_KEYR_KEY (0xFFFFU << IWDG_KEYR_KEY_Pos) ///< Key Value - -//////////////////////////////////////////////////////////////////////////////// -/// @brief IWDG_PR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define IWDG_PR_PRE_Pos (0) -#define IWDG_PR_PRE (0x07U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 4 -#define IWDG_PR_PRE_DIV4 (0x00U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 4 -#define IWDG_PR_PRE_DIV8 (0x01U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 8 -#define IWDG_PR_PRE_DIV16 (0x02U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 16 -#define IWDG_PR_PRE_DIV32 (0x03U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 32 -#define IWDG_PR_PRE_DIV64 (0x04U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 64 -#define IWDG_PR_PRE_DIV128 (0x05U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 128 -#define IWDG_PR_PRE_DIV256 (0x06U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 256 - -//////////////////////////////////////////////////////////////////////////////// -/// @brief IWDG_RLR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define IWDG_RLR_RL_Pos (0) -#define IWDG_RLR_RL (0x0FFFU << IWDG_RLR_RL_Pos) ///< Watchdog counter reload value - -//////////////////////////////////////////////////////////////////////////////// -/// @brief IWDG_SR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define IWDG_SR_PVU_Pos (0) -#define IWDG_SR_PVU (0x01U << IWDG_SR_PVU_Pos) ///< Watchdog prescaler value update -#define IWDG_SR_RVU_Pos (1) -#define IWDG_SR_RVU (0x01U << IWDG_SR_RVU_Pos) ///< Watchdog counter reload value update - -#define IWDG_SR_IVU_Pos (2) -#define IWDG_SR_IVU (0x01U << IWDG_SR_IVU_Pos) - -#define IWDG_SR_UPDATE_Pos (3) -#define IWDG_SR_UPDATE (0x01U << IWDG_SR_UPDATE_Pos) - -//////////////////////////////////////////////////////////////////////////////// -/// @brief IWDG_CR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define IWDG_CR_IRQSEL_Pos (0) -#define IWDG_CR_IRQSEL (0x01U << IWDG_CR_IRQSEL_Pos) ///< IWDG overflow operation selection -#define IWDG_CR_IRQCLR_Pos (1) -#define IWDG_CR_IRQCLR (0x01U << IWDG_CR_IRQCLR_Pos) ///< IWDG interrupt clear - -//////////////////////////////////////////////////////////////////////////////// -/// @brief IWDG_IGRN Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define IWDG_IGEN_IGEN_Pos (0) -#define IWDG_IGEN_IGEN (0xFFFU << IWDG_CR_IRQSEL_Pos) ///< IWDG Interrupt Generate value - - -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -#endif -//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_pwm.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_pwm.h deleted file mode 100644 index aa3605524..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_pwm.h +++ /dev/null @@ -1,72 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file reg_pwm.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF -/// MM32 FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion - -#ifndef __REG_PWM_H -#define __REG_PWM_H - -// Files includes - -#include -#include -#include "types.h" - - - - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - - - - - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief PWM Base Address Definition -//////////////////////////////////////////////////////////////////////////////// - - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief PWM Register Structure Definition -//////////////////////////////////////////////////////////////////////////////// - - - - - - - - - -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -#endif -//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_pwr.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_pwr.h deleted file mode 100644 index 99f523225..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_pwr.h +++ /dev/null @@ -1,219 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file reg_pwr.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF -/// MM32 FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion - -#ifndef __REG_PWR_H -#define __REG_PWR_H - -// Files includes - -#include -#include -#include "types.h" - - - - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - - - - - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief PWR Base Address Definition -//////////////////////////////////////////////////////////////////////////////// -#define PWR_BASE (APB1PERIPH_BASE + 0x7000) ///< Base Address: 0x40007000 - - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief PWR Register Structure Definition -//////////////////////////////////////////////////////////////////////////////// -typedef struct { - union { - __IO u32 CR; ///< Control register, offset: 0x00 - __IO u32 CR1; - }; - union { - __IO u32 CSR; ///< Control Status register offset: 0x04 - __IO u32 CSR1; - }; - __IO u32 CR2; ///< Control register 2 offset: 0x08 - __IO u32 CR3; ///< Control register 3 offset: 0x0C - __IO u32 CR4; ///< Control register 4 offset: 0x10 - __IO u32 CR5; ///< Control register 5 offset: 0x14 - __IO u32 CR6; ///< Control register 6 offset: 0x18 - __IO u32 SR; ///< Status register offset: 0x1C - __IO u32 SCR; ///< clear status register offset: 0x20 - __IO u32 CFGR; ///< Configuration register offset: 0x24 -} PWR_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief PWR type pointer Definition -//////////////////////////////////////////////////////////////////////////////// -#define PWR ((PWR_TypeDef*) PWR_BASE) - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief PWR_CR register Bit definition -//////////////////////////////////////////////////////////////////////////////// -#define PWR_CR_LDPS_Pos (0) -#define PWR_CR_LDPS (0x01U << PWR_CR_LDPS_Pos) ///< Domain Write Protction - -#define PWR_CR_PDDS_Pos (1) -#define PWR_CR_PDDS (0x01U << PWR_CR_PDDS_Pos) ///< Power Down Deepsleep -#define PWR_CR_CSBF_Pos (3) -#define PWR_CR_CSBF (0x01U << PWR_CR_CSBF_Pos) ///< Clear Standby Flag -#define PWR_CR_LPR_Pos (13) -#define PWR_CR_LPR (0x01U << PWR_CR_LPR_Pos) ///< Low power run -#define PWR_CR_VOS_Pos (14) -#define PWR_CR_VOS0 (0x00U << PWR_CR_VOS_Pos) ///< Modulator Voltage Output Select 1.80V -#define PWR_CR_VOS1 (0x01U << PWR_CR_VOS_Pos) ///< Modulator Voltage Output Select 1.70V -#define PWR_CR_VOS2 (0x02U << PWR_CR_VOS_Pos) ///< Modulator Voltage Output Select 1.60V -#define PWR_CR_VOS3 (0x03U << PWR_CR_VOS_Pos) ///< Modulator Voltage Output Select 1.55V - -//////////////////////////////////////////////////////////////////////////////// -/// @brief PWR_CSR register Bit definition -//////////////////////////////////////////////////////////////////////////////// -#define PWR_CSR_SBF_Pos (1) -#define PWR_CSR_SBF (0x01U << PWR_CSR_SBF_Pos) ///< Standby Flag -#define PWR_CSR_VOSRDY_Pos (14) -#define PWR_CSR_VOSRDY (0x01U << PWR_CR_VOSRDY_Pos) ///< Voltage Modulator Output Selection Ready -//////////////////////////////////////////////////////////////////////////////// -/// @brief PWR_CR2 register Bit definition -//////////////////////////////////////////////////////////////////////////////// -#define PWR_CR2_EWUP1_Pos (0) -#define PWR_CR2_EWUP1 (0x01U << PWR_CR2_EWUP1_Pos) ///< Enable WKUP1 wake-up pin -#define PWR_CR2_EWUP2_Pos (1) -#define PWR_CR2_EWUP2 (0x01U << PWR_CR2_EWUP2_Pos) ///< Enable WKUP2 wake-up pin -#define PWR_CR2_EWUP3_Pos (2) -#define PWR_CR2_EWUP3 (0x01U << PWR_CR2_EWUP3_Pos) ///< Enable WKUP3 wake-up pin -#define PWR_CR2_EWUP4_Pos (3) -#define PWR_CR2_EWUP4 (0x01U << PWR_CR2_EWUP4_Pos) ///< Enable WKUP4 wake-up pin -#define PWR_CR2_EWUP5_Pos (4) -#define PWR_CR2_EWUP5 (0x01U << PWR_CR2_EWUP5_Pos) ///< Enable WKUP5 wake-up pin -#define PWR_CR2_EWUP6_Pos (5) -#define PWR_CR2_EWUP6 (0x01U << PWR_CR2_EWUP6_Pos) ///< Enable WKUP6 wake-up pin -#define PWR_CR2_ENWU_Pos (15) -#define PWR_CR2_ENWU (0x01U << PWR_CR2_ENWU_Pos) ///< Enable wakeup module -//////////////////////////////////////////////////////////////////////////////// -/// @brief PWR_CR3 register Bit definition -//////////////////////////////////////////////////////////////////////////////// -#define PWR_CR3_WP1_Pos (0) -#define PWR_CR3_WP1 (0x01U << PWR_CR3_WP1_Pos) ///< WKUP1 used for event polarity detection -#define PWR_CR3_WP2_Pos (1) -#define PWR_CR3_WP2 (0x01U << PWR_CR3_WP2_Pos) ///< WKUP2 used for event polarity detection -#define PWR_CR3_WP3_Pos (2) -#define PWR_CR3_WP3 (0x01U << PWR_CR3_WP3_Pos) ///< WKUP3 used for event polarity detection -#define PWR_CR3_WP4_Pos (3) -#define PWR_CR3_WP4 (0x01U << PWR_CR3_WP4_Pos) ///< WKUP4 used for event polarity detection -#define PWR_CR3_WP5_Pos (4) -#define PWR_CR3_WP5 (0x01U << PWR_CR3_WP5_Pos) ///< WKUP5 used for event polarity detection -#define PWR_CR3_WP6_Pos (5) -#define PWR_CR3_WP6 (0x01U << PWR_CR3_WP6_Pos) ///< WKUP6 used for event polarity detection -//////////////////////////////////////////////////////////////////////////////// -/// @brief PWR_CR4 register Bit definition -//////////////////////////////////////////////////////////////////////////////// -#define PWR_CR4_FILTSEL0_Pos (0) -#define PWR_CR4_FILTSEL0 (0x01U << PWR_CR4_FILTSEL0_Pos) ///< selection wake-up source -#define PWR_CR4_FILTE0_Pos (2) -#define PWR_CR4_FILTE0 (0x01U << PWR_CR4_FILTE0_Pos) ///< enable Filter 0 -#define PWR_CR4_FILTF0_Pos (4) -#define PWR_CR4_FILTF0 (0x01U << PWR_CR4_FILTF0_Pos) ///< Whether the wake source passes through filter 0 -#define PWR_CR4_FILTCNT0_Pos (8) -#define PWR_CR4_FILTCNT0 (0xFFU << PWR_CR4_FILTCNT0_Pos) ///< Filter 0 counter -//////////////////////////////////////////////////////////////////////////////// -/// @brief PWR_CR5 register Bit definition -//////////////////////////////////////////////////////////////////////////////// -#define PWR_CR5_FILTSEL1_Pos (0) -#define PWR_CR5_FILTSEL1 (0x01U << PWR_CR5_FILTSEL1_Pos) ///< selection wake-up source -#define PWR_CR5_FILTE1_Pos (2) -#define PWR_CR5_FILTE1 (0x01U << PWR_CR5_FILTE1_Pos) ///< enable Filter 1 -#define PWR_CR5_FILTF1_Pos (4) -#define PWR_CR5_FILTF1 (0x01U << PWR_CR5_FILTF1_Pos) ///< Whether the wake source passes through filter 1 -#define PWR_CR5_FILTCNT1_Pos (8) -#define PWR_CR5_FILTCNT1 (0xFFU << PWR_CR5_FILTCNT1_Pos) ///< Filter 1 counter -//////////////////////////////////////////////////////////////////////////////// -/// @brief PWR_CR6 register Bit definition -//////////////////////////////////////////////////////////////////////////////// -#define PWR_CR6_STDBY_FS_W_Pos (0) -#define PWR_CR6_STDBY_FS_W1 (0x00U << PWR_CR6_STDBY_FS_W_Pos) ///< 1 LSI cycle wake -#define PWR_CR6_STDBY_FS_W2 (0x01U << PWR_CR6_STDBY_FS_W_Pos) ///< 2 LSI cycle wake -#define PWR_CR6_STDBY_FS_W3 (0x02U << PWR_CR6_STDBY_FS_W_Pos) ///< 3 LSI cycle wake -#define PWR_CR6_STDBY_FS_W4 (0x03U << PWR_CR6_STDBY_FS_W_Pos) ///< 4 LSI cycle wake -#define PWR_CR6_STDBY_FS_W5 (0x04U << PWR_CR6_STDBY_FS_W_Pos) ///< 5 LSI cycle wake -#define PWR_CR6_STDBY_FS_W6 (0x05U << PWR_CR6_STDBY_FS_W_Pos) ///< 6 LSI cycle wake -#define PWR_CR6_STDBY_FS_W7 (0x06U << PWR_CR6_STDBY_FS_W_Pos) ///< 7 LSI cycle wake -#define PWR_CR6_STDBY_FS_W8 (0x07U << PWR_CR6_STDBY_FS_W_Pos) ///< 8 LSI cycle wake -//////////////////////////////////////////////////////////////////////////////// -/// @brief PWR_SR register Bit definition -//////////////////////////////////////////////////////////////////////////////// -#define PWR_SR_WUF1_Pos (0) -#define PWR_SR_WUF1 (0x01U << PWR_SR_WUF1_Pos) ///< wake-up flag 1 -#define PWR_SR_WUF2_Pos (1) -#define PWR_SR_WUF2 (0x01U << PWR_SR_WUF2_Pos) ///< wake-up flag 2 -#define PWR_SR_WUF3_Pos (2) -#define PWR_SR_WUF3 (0x01U << PWR_SR_WUF3_Pos) ///< wake-up flag 3 -#define PWR_SR_WUF4_Pos (3) -#define PWR_SR_WUF4 (0x01U << PWR_SR_WUF4_Pos) ///< wake-up flag 4 -#define PWR_SR_WUF5_Pos (4) -#define PWR_SR_WUF5 (0x01U << PWR_SR_WUF5_Pos) ///< wake-up flag 5 -#define PWR_SR_WUF6_Pos (5) -#define PWR_SR_WUF6 (0x01U << PWR_SR_WUF6_Pos) ///< wake-up flag 6 -//////////////////////////////////////////////////////////////////////////////// -/// @brief PWR_SCR register Bit definition -//////////////////////////////////////////////////////////////////////////////// -#define PWR_SCR_CWUF1_Pos (0) -#define PWR_SCR_CWUF1 (0x01U << PWR_SCR_CWUF1_Pos) ///< clear wake-up flag 1 -#define PWR_SCR_CWUF2_Pos (1) -#define PWR_SCR_CWUF2 (0x01U << PWR_SCR_CWUF2_Pos) ///< clear wake-up flag 2 -#define PWR_SCR_CWUF3_Pos (2) -#define PWR_SCR_CWUF3 (0x01U << PWR_SCR_CWUF3_Pos) ///< clear wake-up flag 3 -#define PWR_SCR_CWUF4_Pos (3) -#define PWR_SCR_CWUF4 (0x01U << PWR_SCR_CWUF4_Pos) ///< clear wake-up flag 4 -#define PWR_SCR_CWUF5_Pos (4) -#define PWR_SCR_CWUF5 (0x01U << PWR_SCR_CWUF5_Pos) ///< clear wake-up flag 5 -#define PWR_SCR_CWUF6_Pos (5) -#define PWR_SCR_CWUF6 (0x01U << PWR_SCR_CWUF6_Pos) ///< clear wake-up flag 6 -//////////////////////////////////////////////////////////////////////////////// -/// @brief PWR_CFGR register Bit definition -//////////////////////////////////////////////////////////////////////////////// -#define PWR_CFGR_LSICALSEL_Pos (0) -#define PWR_CFGR_LSICALSEL (0x1FU << PWR_CFGR_LSICALSEL_Pos) ///< Enable internal clock calibration -#define PWR_CFGR_LSICAL_Pos (5) -#define PWR_CFGR_LSICAL (0x1FU << PWR_CFGR_LSICAL_Pos) ///< Internal high-speed clock calibration - -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -#endif -//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_rcc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_rcc.h deleted file mode 100644 index d378371fc..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_rcc.h +++ /dev/null @@ -1,654 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file reg_rcc.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF -/// MM32 FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion - -#ifndef __REG_RCC_H -#define __REG_RCC_H - -// Files includes - -#include -#include -#include "types.h" - - - - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - - - - - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief RCC Base Address Definition -//////////////////////////////////////////////////////////////////////////////// -#define RCC_BASE (AHBPERIPH_BASE + 0x1000) ///< Base Address: 0x40021000 - - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief RCC Register Structure Definition -//////////////////////////////////////////////////////////////////////////////// -typedef struct { - __IO u32 CR; ///< Control Register offset: 0x00 - __IO u32 CFGR; ///< Configuration Register offset: 0x04 - __IO u32 CIR; ///< Clock Interrupt Register offset: 0x08 - __IO u32 AHB3RSTR; ///< Advanced High Performance Bus 3 Reset Register offset: 0x0C - __IO u32 AHB2RSTR; ///< Advanced High Performance Bus 2 Reset Register offset: 0x10 - __IO u32 AHBRSTR; ///< Advanced High Performance Bus 1 Reset Register offset: 0x14 - __IO u32 APB2RSTR; ///< Advanced Peripheral Bus 2 Reset Register offset: 0x18 - __IO u32 APB1RSTR; ///< Advanced Peripheral Bus 1 Reset Register offset: 0x1C - __IO u32 AHB3ENR; ///< Advanced High Performance Bus 3 Enable Register offset: 0x20 - __IO u32 AHB2ENR; ///< Advanced High Performance Bus 2 Enable Register offset: 0x24 - union { - __IO u32 AHBENR; ///< Advanced High Performance Bus 1 Enable Register offset: 0x28 - __IO u32 AHB1ENR; - }; - - __IO u32 APB2ENR; ///< Advanced Peripheral Bus 2 Enable Register offset: 0x2C - __IO u32 APB1ENR; ///< Advanced Peripheral Bus 1 Enable Register offset: 0x30 - - - __IO u32 BDCR; ///< Backup Domain Control Register offset: 0x34 - __IO u32 CSR; ///< Control Status Register offset: 0x38 - __IO u32 SYSCFGR; ///< System Configuration Register offset: 0x3C - __IO u32 CFGR2; ///< System Configuration Register offset: 0x40 - __IO u32 ICSCR; ///< Internal clock source calibration register offset: 0x44 - __IO u32 PLLCFGR; ///< PLL configures registers offset: 0x48 - u32 Reserved1[13]; ///< Reserved space - __IO u32 HSIDLY; ///< HSI delay register offset: 0x80 - __IO u32 HSEDLY; ///< HSE delay register offset: 0x84 - __IO u32 PLLDLY; ///< PLL delay register offset: 0x88 -} RCC_TypeDef; - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief RCC type pointer Definition -//////////////////////////////////////////////////////////////////////////////// -#define RCC ((RCC_TypeDef*) RCC_BASE) - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief RCC_CR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define RCC_CR_HSION_Pos (0) -#define RCC_CR_HSION (0x01U << RCC_CR_HSION_Pos) ///< Internal High Speed clock enable - -#define RCC_CR_HSIRDY_Pos (1) -#define RCC_CR_HSIRDY (0x01U << RCC_CR_HSIRDY_Pos) ///< Internal High Speed clock ready flag - - - -#define RCC_CR_HSIDIV_Pos (11) -#define RCC_CR_HSIDIV_0 (0x00U << RCC_CR_HSIDIV_Pos) ///< HSI regardless of frequency -#define RCC_CR_HSIDIV_2 (0x01U << RCC_CR_HSIDIV_Pos) ///< HSI 2 frequency division -#define RCC_CR_HSIDIV_4 (0x02U << RCC_CR_HSIDIV_Pos) ///< HSI 4 frequency division -#define RCC_CR_HSIDIV_8 (0x03U << RCC_CR_HSIDIV_Pos) ///< HSI eight points and frequency -#define RCC_CR_HSIDIV_16 (0x04U << RCC_CR_HSIDIV_Pos) ///< HSI 16 points and frequency -#define RCC_CR_HSIDIV_32 (0x05U << RCC_CR_HSIDIV_Pos) ///< HSI 32 points and frequency -#define RCC_CR_HSIDIV_64 (0x06U << RCC_CR_HSIDIV_Pos) ///< HSI 64 frequency division -#define RCC_CR_HSIDIV_128 (0x07U << RCC_CR_HSIDIV_Pos) ///< HSI 128 frequency division -#define RCC_CR_HSEON_Pos (16) -#define RCC_CR_HSEON (0x01U << RCC_CR_HSEON_Pos) ///< External High Speed clock enable -#define RCC_CR_HSERDY_Pos (17) -#define RCC_CR_HSERDY (0x01U << RCC_CR_HSERDY_Pos) ///< External High Speed clock ready flag -#define RCC_CR_HSEBYP_Pos (18) -#define RCC_CR_HSEBYP (0x01U << RCC_CR_HSEBYP_Pos) ///< External High Speed clock Bypass -#define RCC_CR_CSSON_Pos (19) -#define RCC_CR_CSSON (0x01U << RCC_CR_CSSON_Pos) ///< Clock Security System enable - - -#define RCC_CR_PLLON_Pos (24) -#define RCC_CR_PLLON (0x01U << RCC_CR_PLLON_Pos) ///< PLL enable -#define RCC_CR_PLLRDY_Pos (25) -#define RCC_CR_PLLRDY (0x01U << RCC_CR_PLLRDY_Pos) ///< PLL clock ready flag -//////////////////////////////////////////////////////////////////////////////// -/// @brief RCC_CFGR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define RCC_CFGR_SW_Pos (0) -#define RCC_CFGR_SW (0x03U << RCC_CFGR_SW_Pos) ///< SW[1:0] bits (System clock Switch) -#define RCC_CFGR_SW_HSI_DIV6 (0x00U << RCC_CFGR_SW_Pos) ///< HSI/6 selected as system clock -#define RCC_CFGR_SW_HSE (0x01U << RCC_CFGR_SW_Pos) ///< HSE selected as system clock -#define RCC_CFGR_SW_PLL (0x02U << RCC_CFGR_SW_Pos) ///< PLL selected as system clock -#define RCC_CFGR_SW_LSI (0x03U << RCC_CFGR_SW_Pos) ///< LSI selected as system clock - -#define RCC_CFGR_SWS_Pos (2) -#define RCC_CFGR_SWS (0x03U << RCC_CFGR_SWS_Pos) ///< SWS[1:0] bits (System Clock Switch Status) -#define RCC_CFGR_SWS_HSI_DIV6 (0x00U << RCC_CFGR_SWS_Pos) ///< HSI/6 oscillator used as system clock -#define RCC_CFGR_SWS_HSE (0x01U << RCC_CFGR_SWS_Pos) ///< HSE oscillator used as system clock -#define RCC_CFGR_SWS_PLL (0x02U << RCC_CFGR_SWS_Pos) ///< PLL used as system clock -#define RCC_CFGR_SWS_LSI (0x03U << RCC_CFGR_SWS_Pos) ///< LSI used as system clock - -#define RCC_CFGR_HPRE_Pos (4) -#define RCC_CFGR_HPRE (0x0FU << RCC_CFGR_HPRE_Pos) ///< HPRE[3:0] bits (AHB prescaler) -#define RCC_CFGR_PPRE_0 (0x01U << RCC_CFGR_HPRE_Pos) ///< Bit 0 -#define RCC_CFGR_PPRE_1 (0x02U << RCC_CFGR_HPRE_Pos) ///< Bit 1 -#define RCC_CFGR_PPRE_2 (0x04U << RCC_CFGR_HPRE_Pos) ///< Bit 2 -#define RCC_CFGR_PPRE_3 (0x08U << RCC_CFGR_HPRE_Pos) ///< Bit 3 - -#define RCC_CFGR_HPRE_DIV1 (0x00U << RCC_CFGR_HPRE_Pos) ///< AHB = FCLK = SYSCLK not divided -#define RCC_CFGR_HPRE_DIV2 (0x08U << RCC_CFGR_HPRE_Pos) ///< AHB = FCLK = SYSCLK divided by 2 -#define RCC_CFGR_HPRE_DIV4 (0x09U << RCC_CFGR_HPRE_Pos) ///< AHB = FCLK = SYSCLK divided by 4 -#define RCC_CFGR_HPRE_DIV8 (0x0AU << RCC_CFGR_HPRE_Pos) ///< AHB = FCLK = SYSCLK divided by 8 -#define RCC_CFGR_HPRE_DIV16 (0x0BU << RCC_CFGR_HPRE_Pos) ///< AHB = FCLK = SYSCLK divided by 16 -#define RCC_CFGR_HPRE_DIV64 (0x0CU << RCC_CFGR_HPRE_Pos) ///< AHB = FCLK = SYSCLK divided by 64 -#define RCC_CFGR_HPRE_DIV128 (0x0DU << RCC_CFGR_HPRE_Pos) ///< AHB = FCLK = SYSCLK divided by 128 -#define RCC_CFGR_HPRE_DIV256 (0x0EU << RCC_CFGR_HPRE_Pos) ///< AHB = FCLK = SYSCLK divided by 256 -#define RCC_CFGR_HPRE_DIV512 (0x0FU << RCC_CFGR_HPRE_Pos) ///< AHB = FCLK = SYSCLK divided by 512 - -#define RCC_CFGR_PPRE1_Pos (8) -#define RCC_CFGR_PPRE1 (0x07U << RCC_CFGR_PPRE1_Pos) ///< PRE1[2:0] bits (APB1 prescaler) -#define RCC_CFGR_PPRE1_0 (0x01U << RCC_CFGR_PPRE1_Pos) ///< Bit 0 -#define RCC_CFGR_PPRE1_1 (0x02U << RCC_CFGR_PPRE1_Pos) ///< Bit 1 -#define RCC_CFGR_PPRE1_2 (0x04U << RCC_CFGR_PPRE1_Pos) ///< Bit 2 - -#define RCC_CFGR_PPRE1_DIV1 (0x00U << RCC_CFGR_PPRE1_Pos) ///< APB1 = HCLK not divided -#define RCC_CFGR_PPRE1_DIV2 (0x04U << RCC_CFGR_PPRE1_Pos) ///< APB1 = HCLK divided by 2 -#define RCC_CFGR_PPRE1_DIV4 (0x05U << RCC_CFGR_PPRE1_Pos) ///< APB1 = HCLK divided by 4 -#define RCC_CFGR_PPRE1_DIV8 (0x06U << RCC_CFGR_PPRE1_Pos) ///< APB1 = HCLK divided by 8 -#define RCC_CFGR_PPRE1_DIV16 (0x07U << RCC_CFGR_PPRE1_Pos) ///< APB1 = HCLK divided by 16 - -#define RCC_CFGR_PPRE2_Pos (11) -#define RCC_CFGR_PPRE2 (0x07U << RCC_CFGR_PPRE2_Pos) ///< PRE2[2:0] bits (APB2 prescaler) -#define RCC_CFGR_PPRE2_0 (0x01U << RCC_CFGR_PPRE2_Pos) ///< Bit 0 -#define RCC_CFGR_PPRE2_1 (0x02U << RCC_CFGR_PPRE2_Pos) ///< Bit 1 -#define RCC_CFGR_PPRE2_2 (0x04U << RCC_CFGR_PPRE2_Pos) ///< Bit 2 - -#define RCC_CFGR_PPRE2_DIV1 (0x00U << RCC_CFGR_PPRE2_Pos) ///< APB2 = HCLK not divided -#define RCC_CFGR_PPRE2_DIV2 (0x04U << RCC_CFGR_PPRE2_Pos) ///< APB2 = HCLK divided by 2 -#define RCC_CFGR_PPRE2_DIV4 (0x05U << RCC_CFGR_PPRE2_Pos) ///< APB2 = HCLK divided by 4 -#define RCC_CFGR_PPRE2_DIV8 (0x06U << RCC_CFGR_PPRE2_Pos) ///< APB2 = HCLK divided by 8 -#define RCC_CFGR_PPRE2_DIV16 (0x07U << RCC_CFGR_PPRE2_Pos) ///< APB2 = HCLK divided by 16 - - -#define RCC_CFGR_USBPRE_Pos (22) -#define RCC_CFGR_USBPRE (0x03U << RCC_CFGR_USBPRE_Pos) ///< USB prescaler BIT[1:0] - -#define RCC_CFGR_MCO_Pos (24) -#define RCC_CFGR_MCO (0x07U << RCC_CFGR_MCO_Pos) ///< MCO[2:0] bits (Microcontroller Clock Output) -#define RCC_CFGR_MCO_NOCLOCK (0x00U << RCC_CFGR_MCO_Pos) ///< No clock -#define RCC_CFGR_MCO_LSI (0x02U << RCC_CFGR_MCO_Pos) ///< LSI clock -#define RCC_CFGR_MCO_LSE (0x03U << RCC_CFGR_MCO_Pos) ///< LSE clock -#define RCC_CFGR_MCO_SYSCLK (0x04U << RCC_CFGR_MCO_Pos) ///< System clock selected -#define RCC_CFGR_MCO_HSI (0x05U << RCC_CFGR_MCO_Pos) ///< Internal 48 MHz RC oscillator clock selected -#define RCC_CFGR_MCO_HSE (0x06U << RCC_CFGR_MCO_Pos) ///< External 1-25 MHz oscillator clock selected -#define RCC_CFGR_MCO_PLL (0x07U << RCC_CFGR_MCO_Pos) ///< PLL clock divided by 2 selected - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief RCC_CIR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define RCC_CIR_LSIRDYF_Pos (0) -#define RCC_CIR_LSIRDYF (0x01U << RCC_CIR_LSIRDYF_Pos) ///< LSI Ready Interrupt flag - -#define RCC_CIR_LSERDYF_Pos (1) -#define RCC_CIR_LSERDYF (0x01U << RCC_CIR_LSERDYF_Pos) ///< LSE Ready Interrupt flag - -#define RCC_CIR_HSIRDYF_Pos (2) -#define RCC_CIR_HSIRDYF (0x01U << RCC_CIR_HSIRDYF_Pos) ///< HSI Ready Interrupt flag -#define RCC_CIR_HSERDYF_Pos (3) -#define RCC_CIR_HSERDYF (0x01U << RCC_CIR_HSERDYF_Pos) ///< HSE Ready Interrupt flag - -#define RCC_CIR_PLLRDYF_Pos (4) -#define RCC_CIR_PLLRDYF (0x01U << RCC_CIR_PLLRDYF_Pos) ///< PLL Ready Interrupt flag - -#define RCC_CIR_CSSF_Pos (7) -#define RCC_CIR_CSSF (0x01U << RCC_CIR_CSSF_Pos) ///< Clock Security System Interrupt flag -#define RCC_CIR_LSIRDYIE_Pos (8) -#define RCC_CIR_LSIRDYIE (0x01U << RCC_CIR_LSIRDYIE_Pos) ///< LSI Ready Interrupt Enable - -#define RCC_CIR_LSERDYIE_Pos (9) -#define RCC_CIR_LSERDYIE (0x01U << RCC_CIR_LSERDYIE_Pos) ///< LSE Ready Interrupt Enable - -#define RCC_CIR_HSIRDYIE_Pos (10) -#define RCC_CIR_HSIRDYIE (0x01U << RCC_CIR_HSIRDYIE_Pos) ///< HSI Ready Interrupt Enable -#define RCC_CIR_HSERDYIE_Pos (11) -#define RCC_CIR_HSERDYIE (0x01U << RCC_CIR_HSIRDYIE_Pos) ///< HSE Ready Interrupt Enable - -#define RCC_CIR_PLLRDYIE_Pos (12) -#define RCC_CIR_PLLRDYIE (0x01U << RCC_CIR_PLLRDYIE_Pos) ///< PLL Ready Interrupt Enable - -#define RCC_CIR_LSIRDYC_Pos (16) -#define RCC_CIR_LSIRDYC (0x01U << RCC_CIR_LSIRDYC_Pos) ///< LSI Ready Interrupt Clear - -#define RCC_CIR_LSERDYC_Pos (17) -#define RCC_CIR_LSERDYC (0x01U << RCC_CIR_LSERDYC_Pos) ///< LSE Ready Interrupt Clear - -#define RCC_CIR_HSIRDYC_Pos (18) -#define RCC_CIR_HSIRDYC (0x01U << RCC_CIR_HSIRDYC_Pos) ///< HSI Ready Interrupt Clear -#define RCC_CIR_HSERDYC_Pos (19) -#define RCC_CIR_HSERDYC (0x01U << RCC_CIR_HSERDYC_Pos) ///< HSE Ready Interrupt Clear - -#define RCC_CIR_PLLRDYC_Pos (20) -#define RCC_CIR_PLLRDYC (0x01U << RCC_CIR_PLLRDYC_Pos) ///< PLL Ready Interrupt Clear - -#define RCC_CIR_CSSC_Pos (23) -#define RCC_CIR_CSSC (0x01U << RCC_CIR_CSSC_Pos) ///< Clock Security System Interrupt Clear - -//////////////////////////////////////////////////////////////////////////////// -/// @brief RCC_APB2RSTR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define RCC_APB2RSTR_TIM1_Pos (0) -#define RCC_APB2RSTR_TIM1 (0x01U << RCC_APB2RSTR_TIM1_Pos) ///< TIM1 reset -#define RCC_APB2RSTR_TIM8_Pos (1) -#define RCC_APB2RSTR_TIM8 (0x01U << RCC_APB2RSTR_TIM8_Pos) ///< TIM8 reset -#define RCC_APB2RSTR_UART1_Pos (4) -#define RCC_APB2RSTR_UART1 (0x01U << RCC_APB2RSTR_UART1_Pos) ///< UART1 reset -#define RCC_APB2RSTR_UART6_Pos (5) -#define RCC_APB2RSTR_UART6 (0x01U << RCC_APB2RSTR_UART6_Pos) ///< UART6 reset -#define RCC_APB2RSTR_ADC1_Pos (8) -#define RCC_APB2RSTR_ADC1 (0x01U << RCC_APB2RSTR_ADC1_Pos) ///< ADC1 reset -#define RCC_APB2RSTR_ADC2_Pos (9) -#define RCC_APB2RSTR_ADC2 (0x01U << RCC_APB2RSTR_ADC2_Pos) ///< ADC2 reset -#define RCC_APB2RSTR_ADC3_Pos (10) -#define RCC_APB2RSTR_ADC3 (0x01U << RCC_APB2RSTR_ADC3_Pos) ///< ADC3 reset -#define RCC_APB2RSTR_SPI1_Pos (12) -#define RCC_APB2RSTR_SPI1 (0x01U << RCC_APB2RSTR_SPI1_Pos) ///< SPI1 reset -#define RCC_APB2RSTR_SYSCFG_Pos (14) -#define RCC_APB2RSTR_SYSCFG (0x01U << RCC_APB2RSTR_SYSCFG_Pos) ///< SYSCFG reset -#define RCC_APB2RSTR_COMP_Pos (15) -#define RCC_APB2RSTR_COMP (0x01U << RCC_APB2RSTR_COMP_Pos) ///< COMP reset - - - - - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief RCC_AHB3RSTR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define RCC_AHB3RSTR_FSMC_Pos (0) -#define RCC_AHB3RSTR_FSMC (0x01U << RCC_AHB3RSTR_FSMC_Pos) ///< FSMC reset - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief RCC_APB1RSTR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define RCC_APB1RSTR_TIM2_Pos (0) -#define RCC_APB1RSTR_TIM2 (0x01U << RCC_APB1RSTR_TIM2_Pos) ///< Timer 2 reset -#define RCC_APB1RSTR_TIM3_Pos (1) -#define RCC_APB1RSTR_TIM3 (0x01U << RCC_APB1RSTR_TIM3_Pos) ///< Timer 3 reset - -#define RCC_APB1RSTR_TIM4_Pos (2) -#define RCC_APB1RSTR_TIM4 (0x01U << RCC_APB1RSTR_TIM4_Pos) ///< Timer 4 reset -#define RCC_APB1RSTR_TIM5_Pos (3) -#define RCC_APB1RSTR_TIM5 (0x01U << RCC_APB1RSTR_TIM5_Pos) ///< Timer 5 reset -#define RCC_APB1RSTR_TIM6_Pos (4) -#define RCC_APB1RSTR_TIM6 (0x01U << RCC_APB1RSTR_TIM6_Pos) ///< Timer 6 reset -#define RCC_APB1RSTR_TIM7_Pos (5) -#define RCC_APB1RSTR_TIM7 (0x01U << RCC_APB1RSTR_TIM7_Pos) ///< Timer 7 reset - -#define RCC_APB1RSTR_WWDG_Pos (11) -#define RCC_APB1RSTR_WWDG (0x01U << RCC_APB1RSTR_WWDG_Pos) ///< Window Watchdog reset -#define RCC_APB1RSTR_SPI2_Pos (14) -#define RCC_APB1RSTR_SPI2 (0x01U << RCC_APB1RSTR_SPI2_Pos) ///< SPI 2 reset -#define RCC_APB1RSTR_SPI3_Pos (15) -#define RCC_APB1RSTR_SPI3 (0x01U << RCC_APB1RSTR_SPI3_Pos) ///< SPI 3 reset - -#define RCC_APB1RSTR_UART2_Pos (17) -#define RCC_APB1RSTR_UART2 (0x01U << RCC_APB1RSTR_UART2_Pos) ///< UART 2 reset -#define RCC_APB1RSTR_UART3_Pos (18) -#define RCC_APB1RSTR_UART3 (0x01U << RCC_APB1RSTR_UART3_Pos) ///< UART 3 reset -#define RCC_APB1RSTR_UART4_Pos (19) -#define RCC_APB1RSTR_UART4 (0x01U << RCC_APB1RSTR_UART4_Pos) ///< UART 4 reset -#define RCC_APB1RSTR_UART5_Pos (20) -#define RCC_APB1RSTR_UART5 (0x01U << RCC_APB1RSTR_UART5_Pos) ///< UART 5 reset -#define RCC_APB1RSTR_I2C1_Pos (21) -#define RCC_APB1RSTR_I2C1 (0x01U << RCC_APB1RSTR_I2C1_Pos) ///< I2C 1 reset -#define RCC_APB1RSTR_I2C2_Pos (22) -#define RCC_APB1RSTR_I2C2 (0x01U << RCC_APB1RSTR_I2C2_Pos) ///< I2C 2 reset - -#define RCC_APB1RSTR_CRS_Pos (24) -#define RCC_APB1RSTR_CRS (0x01U << RCC_APB1RSTR_CRS_Pos) ///< CRS reset -#define RCC_APB1RSTR_CAN_Pos (25) -#define RCC_APB1RSTR_CAN (0x01U << RCC_APB1RSTR_CAN_Pos) ///< CAN reset - -#define RCC_APB1RSTR_BKP_Pos (27) -#define RCC_APB1RSTR_BKP (0x01U << RCC_APB1RSTR_BKP_Pos) ///< Backup interface reset - -#define RCC_APB1RSTR_PWR_Pos (28) -#define RCC_APB1RSTR_PWR (0x01U << RCC_APB1RSTR_PWR_Pos) ///< Power interface reset -#define RCC_APB1RSTR_DAC_Pos (29) -#define RCC_APB1RSTR_DAC (0x01U << RCC_APB1RSTR_DAC_Pos) ///< DAC interface reset - - -#define RCC_APB1RSTR_UART7_Pos (30) -#define RCC_APB1RSTR_UART7 (0x01U << RCC_APB1RSTR_UART7_Pos) ///< UART7 reset -#define RCC_APB1RSTR_UART8_Pos (31) -#define RCC_APB1RSTR_UART8 (0x01U << RCC_APB1RSTR_UART8_Pos) ///< UART8 reset - -//////////////////////////////////////////////////////////////////////////////// -/// @brief RCC_AHB2RSTR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define RCC_AHB2RSTR_USBFS_Pos (7) -#define RCC_AHB2RSTR_USBFS (0x01U << RCC_AHB2RSTR_USBFS_Pos) ///< USBFS reset -//////////////////////////////////////////////////////////////////////////////// -/// @brief RCC_AHB3ENR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define RCC_AHB3ENR_FSMC_Pos (0) -#define RCC_AHB3ENR_FSMC (0x01U << RCC_AHB3ENR_FSMC_Pos) ///< FSMC reset - -//////////////////////////////////////////////////////////////////////////////// -/// @brief RCC_AHB2ENR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define RCC_AHB2ENR_USBFS_Pos (7) -#define RCC_AHB2ENR_USBFS (0x01U << RCC_AHB2ENR_USBFS_Pos) ///< USBFS reset - -//////////////////////////////////////////////////////////////////////////////// -/// @brief RCC_AHBENR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// - - - -#define RCC_AHBENR_GPIOA_Pos (0) -#define RCC_AHBENR_GPIOA (0x01U << RCC_AHBENR_GPIOA_Pos) ///< GPIOA clock enable -#define RCC_AHBENR_GPIOB_Pos (1) -#define RCC_AHBENR_GPIOB (0x01U << RCC_AHBENR_GPIOB_Pos) ///< GPIOB clock enable -#define RCC_AHBENR_GPIOC_Pos (2) -#define RCC_AHBENR_GPIOC (0x01U << RCC_AHBENR_GPIOC_Pos) ///< GPIOC clock enable -#define RCC_AHBENR_GPIOD_Pos (3) -#define RCC_AHBENR_GPIOD (0x01U << RCC_AHBENR_GPIOD_Pos) ///< GPIOD clock enable -#define RCC_AHBENR_GPIOE_Pos (4) -#define RCC_AHBENR_GPIOE (0x01U << RCC_AHBENR_GPIOE_Pos) ///< GPIOE clock enable -#define RCC_AHBENR_GPIOF_Pos (5) -#define RCC_AHBENR_GPIOF (0x01U << RCC_AHBENR_GPIOF_Pos) ///< GPIOF clock enable -#define RCC_AHBENR_GPIOG_Pos (6) -#define RCC_AHBENR_GPIOG (0x01U << RCC_AHBENR_GPIOG_Pos) ///< GPIOG clock enable -#define RCC_AHBENR_GPIOH_Pos (7) -#define RCC_AHBENR_GPIOH (0x01U << RCC_AHBENR_GPIOH_Pos) ///< GPIOH clock enable -#define RCC_AHBENR_SDIO_Pos (10) -#define RCC_AHBENR_SDIO (0x01U << RCC_AHBENR_SDIO_Pos) ///< SDIO clock enable -#define RCC_AHBENR_CRC_Pos (12) -#define RCC_AHBENR_CRC (0x01U << RCC_AHBENR_CRC_Pos) ///< CRC clock enable -#define RCC_AHBENR_FLASH_Pos (13) -#define RCC_AHBENR_FLASH (0x01U << RCC_AHBENR_FLASH_Pos) ///< FLASH clock enable -#define RCC_AHBENR_SRAM_Pos (14) -#define RCC_AHBENR_SRAM (0x01U << RCC_AHBENR_SRAM_Pos) ///< SRAM clock enable -#define RCC_AHBENR_DMA1_Pos (21) -#define RCC_AHBENR_DMA1 (0x01U << RCC_AHBENR_DMA1_Pos) ///< DMA1 clock enable -#define RCC_AHBENR_DMA2_Pos (22) -#define RCC_AHBENR_DMA2 (0x01U << RCC_AHBENR_DMA2_Pos) ///< DMA2 clock enable -#define RCC_AHBENR_ETHMAC_Pos (25) -#define RCC_AHBENR_ETHMAC (0x01U << RCC_AHBENR_ETHMAC_Pos) ///< ETHMAC clock enable -//////////////////////////////////////////////////////////////////////////////// -/// @brief RCC_APB2ENR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define RCC_APB2ENR_TIM1_Pos (0) -#define RCC_APB2ENR_TIM1 (0x01U << RCC_APB2ENR_TIM1_Pos) ///< TIM1 enable -#define RCC_APB2ENR_TIM8_Pos (1) -#define RCC_APB2ENR_TIM8 (0x01U << RCC_APB2ENR_TIM8_Pos) ///< TIM8 enable -#define RCC_APB2ENR_UART1_Pos (4) -#define RCC_APB2ENR_UART1 (0x01U << RCC_APB2ENR_UART1_Pos) ///< UART1 enable -#define RCC_APB2ENR_UART6_Pos (5) -#define RCC_APB2ENR_UART6 (0x01U << RCC_APB2ENR_UART6_Pos) ///< UART6 enable -#define RCC_APB2ENR_ADC1_Pos (8) -#define RCC_APB2ENR_ADC1 (0x01U << RCC_APB2ENR_ADC1_Pos) ///< ADC1 enable -#define RCC_APB2ENR_ADC2_Pos (9) -#define RCC_APB2ENR_ADC2 (0x01U << RCC_APB2ENR_ADC2_Pos) ///< ADC2 enable -#define RCC_APB2ENR_ADC3_Pos (10) -#define RCC_APB2ENR_ADC3 (0x01U << RCC_APB2ENR_ADC3_Pos) ///< ADC3 enable -#define RCC_APB2ENR_SPI1_Pos (12) -#define RCC_APB2ENR_SPI1 (0x01U << RCC_APB2ENR_SPI1_Pos) ///< SPI1 enable -#define RCC_APB2ENR_EXTI_Pos (14) -#define RCC_APB2ENR_EXTI (0x01U << RCC_APB2ENR_EXTI_Pos) ///< EXTI Block enable -#define RCC_APB2ENR_SYSCFG_Pos (14) -#define RCC_APB2ENR_SYSCFG (0x01U << RCC_APB2ENR_SYSCFG_Pos) ///< SYSCFG enable -#define RCC_APB2ENR_COMP_Pos (15) -#define RCC_APB2ENR_COMP (0x01U << RCC_APB2ENR_COMP_Pos) ///< COMP enable -//////////////////////////////////////////////////////////////////////////////// -/// @brief RCC_APB1ENR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define RCC_APB1ENR_TIM2_Pos (0) -#define RCC_APB1ENR_TIM2 (0x01U << RCC_APB1ENR_TIM2_Pos) ///< Timer 2 clock enable - -#define RCC_APB1ENR_TIM3_Pos (1) -#define RCC_APB1ENR_TIM3 (0x01U << RCC_APB1ENR_TIM3_Pos) ///< Timer 3 clock enabled - -#define RCC_APB1ENR_TIM4_Pos (2) -#define RCC_APB1ENR_TIM4 (0x01U << RCC_APB1ENR_TIM4_Pos) ///< Timer 4 clock enable - - -#define RCC_APB1ENR_TIM5_Pos (3) -#define RCC_APB1ENR_TIM5 (0x01U << RCC_APB1ENR_TIM5_Pos) ///< TIM5 Timer clock enable -#define RCC_APB1ENR_TIM6_Pos (4) -#define RCC_APB1ENR_TIM6 (0x01U << RCC_APB1ENR_TIM6_Pos) ///< TIM6 Timer clock enable -#define RCC_APB1ENR_TIM7_Pos (5) -#define RCC_APB1ENR_TIM7 (0x01U << RCC_APB1ENR_TIM7_Pos) ///< TIM7 Timer clock enable - -#define RCC_APB1ENR_WWDG_Pos (11) -#define RCC_APB1ENR_WWDG (0x01U << RCC_APB1ENR_WWDG_Pos) ///< Window Watchdog clock enable - - -#define RCC_APB1ENR_SPI2_Pos (14) -#define RCC_APB1ENR_SPI2 (0x01U << RCC_APB1ENR_SPI2_Pos) ///< SPI 2 clock enable -#define RCC_APB1ENR_SPI3_Pos (15) -#define RCC_APB1ENR_SPI3 (0x01U << RCC_APB1ENR_SPI3_Pos) ///< SPI 3 clock enable - -#define RCC_APB1ENR_UART2_Pos (17) -#define RCC_APB1ENR_UART2 (0x01U << RCC_APB1ENR_UART2_Pos) ///< UART 2 clock enable -#define RCC_APB1ENR_UART3_Pos (18) -#define RCC_APB1ENR_UART3 (0x01U << RCC_APB1ENR_UART3_Pos) ///< UART 3 clock enable -#define RCC_APB1ENR_UART4_Pos (19) -#define RCC_APB1ENR_UART4 (0x01U << RCC_APB1ENR_UART4_Pos) ///< UART 4 clock enable -#define RCC_APB1ENR_UART5_Pos (20) -#define RCC_APB1ENR_UART5 (0x01U << RCC_APB1ENR_UART5_Pos) ///< UART 5 clock enable -#define RCC_APB1ENR_I2C1_Pos (21) -#define RCC_APB1ENR_I2C1 (0x01U << RCC_APB1ENR_I2C1_Pos) ///< I2C 1 clock enable -#define RCC_APB1ENR_I2C2_Pos (22) -#define RCC_APB1ENR_I2C2 (0x01U << RCC_APB1ENR_I2C2_Pos) ///< I2C 2 clock enable -#define RCC_APB1ENR_CRS_Pos (24) -#define RCC_APB1ENR_CRS (0x01U << RCC_APB1ENR_CRS_Pos) ///< CRS 4 clock enable -#define RCC_APB1ENR_CAN_Pos (25) -#define RCC_APB1ENR_CAN (0x01U << RCC_APB1ENR_CAN_Pos) ///< CAN 5 clock enable - - - -#define RCC_APB1ENR_BKP_Pos (27) -#define RCC_APB1ENR_BKP (0x01U << RCC_APB1ENR_BKP_Pos) ///< Backup interface clock enable - -#define RCC_APB1ENR_PWR_Pos (28) -#define RCC_APB1ENR_PWR (0x01U << RCC_APB1ENR_PWR_Pos) ///< Power interface clock enable - -#define RCC_APB1ENR_DBGMCU_Pos (28) -#define RCC_APB1ENR_DBGMCU (0x01U << RCC_APB1ENR_DBGMCU_Pos) ///< DBGMCU clock enable - - -#define RCC_APB1ENR_DAC_Pos (29) -#define RCC_APB1ENR_DAC (0x01U << RCC_APB1ENR_DAC_Pos) ///< DAC interface clock enable -#define RCC_APB1ENR_UART7_Pos (30) -#define RCC_APB1ENR_UART7 (0x01U << RCC_APB1ENR_UART7_Pos) ///< UART7 interface clock enable -#define RCC_APB1ENR_UART8_Pos (31) -#define RCC_APB1ENR_UART8 (0x01U << RCC_APB1ENR_UART8_Pos) ///< UART8 interface clock enable -//////////////////////////////////////////////////////////////////////////////// -/// @brief RCC_BDCR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define RCC_BDCR_LSEON_Pos (0) -#define RCC_BDCR_LSEON (0x01U << RCC_BDCR_LSEON_Pos) ///< External Low Speed oscillator enable -#define RCC_BDCR_LSERDY_Pos (1) -#define RCC_BDCR_LSERDY (0x01U << RCC_BDCR_LSERDY_Pos) ///< External Low Speed oscillator Ready -#define RCC_BDCR_LSEBYP_Pos (2) -#define RCC_BDCR_LSEBYP (0x01U << RCC_BDCR_LSEBYP_Pos) ///< External Low Speed oscillator Bypass - -#define RCC_BDCR_RTCSEL_Pos (8) -#define RCC_BDCR_RTCSEL (0x03U << RCC_BDCR_RTCSEL_Pos) ///< RTCSEL[1:0] bits (RTC clock source selection) -#define RCC_BDCR_RTCSEL_LSE (0x01U << RCC_BDCR_RTCSEL_Pos) ///< LSE oscillator clock used as RTC clock -#define RCC_BDCR_RTCSEL_LSI (0x02U << RCC_BDCR_RTCSEL_Pos) ///< LSI oscillator clock used as RTC clock -#define RCC_BDCR_RTCSEL_HSE (0x03U << RCC_BDCR_RTCSEL_Pos) ///< HSE oscillator clock divided by 128 used as RTC clock - -#define RCC_BDCR_RTCEN_Pos (15) -#define RCC_BDCR_RTCEN (0x01U << RCC_BDCR_RTCEN_Pos) ///< RTC clock enable -#define RCC_BDCR_BDRST_Pos (16) -#define RCC_BDCR_BDRST (0x01U << RCC_BDCR_BDRST_Pos) ///< Backup domain software reset -#define RCC_BDCR_DBP_Pos (24) -#define RCC_BDCR_DBP (0x01U << RCC_BDCR_DBP_Pos) ///< DBP clock enable - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief RCC_CSR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define RCC_CSR_LSION_Pos (0) -#define RCC_CSR_LSION (0x01U << RCC_CSR_LSION_Pos) ///< Internal Low Speed oscillator enable -#define RCC_CSR_LSIRDY_Pos (1) -#define RCC_CSR_LSIRDY (0x01U << RCC_CSR_LSIRDY_Pos) ///< Internal Low Speed oscillator Ready -#define RCC_CSR_LSIOENLV_Pos (5) -#define RCC_CSR_LSIOENLV (0x01U << RCC_CSR_LSIOENLV_Pos) ///< LSI output enable lower voltage -#define RCC_CSR_PVDRSTEN_Pos (6) -#define RCC_CSR_PVDRSTEN (0x01U << RCC_CSR_PVDRSTEN_Pos) ///< PVD reset enable -#define RCC_CSR_LOCKUPEN_Pos (7) -#define RCC_CSR_LOCKUPEN (0x01U << RCC_CSR_LOCKUPEN_Pos) ///< CPU lockup reset enable -#define RCC_CSR_VDTRSTNEN_Pos (8) -#define RCC_CSR_VDTRSTNEN (0x01U << RCC_CSR_VDTRSTNEN_Pos) ///< Voltage detect reset enable -#define RCC_CSR_VDTRSTF_Pos (21) -#define RCC_CSR_VDTRSTF (0x01U << RCC_CSR_VDTRSTF_Pos) ///< Voltage detect reset flag -#define RCC_CSR_PVDRSTF_Pos (22) -#define RCC_CSR_PVDRSTF (0x01U << RCC_CSR_PVDRSTF_Pos) ///< PVD reset flag -#define RCC_CSR_LOCKUPF_Pos (23) -#define RCC_CSR_LOCKUPF (0x01U << RCC_CSR_LOCKUPF_Pos) ///< CPU lockup reset flag - -#define RCC_CSR_RMVF_Pos (24) -#define RCC_CSR_RMVF (0x01U << RCC_CSR_RMVF_Pos) ///< Remove reset flag -#define RCC_CSR_PINRSTF_Pos (26) -#define RCC_CSR_PINRSTF (0x01U << RCC_CSR_PINRSTF_Pos) ///< PIN reset flag - -#define RCC_CSR_PORRSTF_Pos (27) -#define RCC_CSR_PORRSTF (0x01U << RCC_CSR_PORRSTF_Pos) ///< POR/PDR reset flag - -#define RCC_CSR_SFTRSTF_Pos (28) -#define RCC_CSR_SFTRSTF (0x01U << RCC_CSR_SFTRSTF_Pos) ///< Software Reset flag - -#define RCC_CSR_IWDGRSTF_Pos (29) -#define RCC_CSR_IWDGRSTF (0x01U << RCC_CSR_IWDGRSTF_Pos) ///< Independent Watchdog reset flag - -#define RCC_CSR_WWDGRSTF_Pos (30) -#define RCC_CSR_WWDGRSTF (0x01U << RCC_CSR_WWDGRSTF_Pos) ///< Window watchdog reset flag - -//////////////////////////////////////////////////////////////////////////////// -/// @brief RCC_AHBRSTR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define RCC_AHBRSTR_GPIOA_Pos (0) -#define RCC_AHBRSTR_GPIOA (0x01U << RCC_AHBRSTR_GPIOA_Pos) ///< GPIOA clock reset -#define RCC_AHBRSTR_GPIOB_Pos (1) -#define RCC_AHBRSTR_GPIOB (0x01U << RCC_AHBRSTR_GPIOB_Pos) ///< GPIOB clock reset -#define RCC_AHBRSTR_GPIOC_Pos (2) -#define RCC_AHBRSTR_GPIOC (0x01U << RCC_AHBRSTR_GPIOC_Pos) ///< GPIOC clock reset -#define RCC_AHBRSTR_GPIOD_Pos (3) -#define RCC_AHBRSTR_GPIOD (0x01U << RCC_AHBRSTR_GPIOD_Pos) ///< GPIOD clock reset -#define RCC_AHBRSTR_GPIOE_Pos (4) -#define RCC_AHBRSTR_GPIOE (0x01U << RCC_AHBRSTR_GPIOE_Pos) ///< GPIOE clock reset -#define RCC_AHBRSTR_GPIOF_Pos (5) -#define RCC_AHBRSTR_GPIOF (0x01U << RCC_AHBRSTR_GPIOF_Pos) ///< GPIOF clock reset -#define RCC_AHBRSTR_GPIOG_Pos (6) -#define RCC_AHBRSTR_GPIOG (0x01U << RCC_AHBRSTR_GPIOG_Pos) ///< GPIOG clock reset -#define RCC_AHBRSTR_GPIOH_Pos (7) -#define RCC_AHBRSTR_GPIOH (0x01U << RCC_AHBRSTR_GPIOH_Pos) ///< GPIOH clock reset -#define RCC_AHBRSTR_SDIO_Pos (10) -#define RCC_AHBRSTR_SDIO (0x01U << RCC_AHBRSTR_SDIO_Pos) ///< SDIO clock reset -#define RCC_AHBRSTR_CRC_Pos (12) -#define RCC_AHBRSTR_CRC (0x01U << RCC_AHBRSTR_CRC_Pos) ///< CRC clock reset -#define RCC_AHBRSTR_DMA1_Pos (21) -#define RCC_AHBRSTR_DMA1 (0x01U << RCC_AHBRSTR_DMA1_Pos) ///< DMA1 clock reset -#define RCC_AHBRSTR_DMA2_Pos (22) -#define RCC_AHBRSTR_DMA2 (0x01U << RCC_AHBRSTR_DMA2_Pos) ///< DMA2 clock reset -#define RCC_AHBRSTR_ETHMAC_Pos (25) -#define RCC_AHBRSTR_ETHMAC (0x01U << RCC_AHBRSTR_ETHMAC_Pos) ///< ETHMAC clock reset -//////////////////////////////////////////////////////////////////////////////// -/// @brief RCC_SYSCFG Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// - -#define RCC_SYSCFG_PROGCHECKEN_Pos (0) -#define RCC_SYSCFG_PROGCHECKEN (0x01U << RCC_SYSCFG_PROGCHECKEN_Pos) ///< Whether to check the number in Flash when writing to Flash -#define RCC_SYSCFG_SECTOR1KCFG_Pos (1) -#define RCC_SYSCFG_SECTOR1KCFG (0x01U << RCC_SYSCFG_SECTOR1KCFG_Pos) ///< The size of the Flash page when erased. -#define RCC_SYSCFG_DATAPREFETCH_Pos (2) -#define RCC_SYSCFG_DATAPREFETCH (0x01U << RCC_SYSCFG_DATAPREFETCH_Pos) ///< DATA prefetch module enable bit -#define RCC_SYSCFG_PAD_OSC_TRIM_Pos (8) -#define RCC_SYSCFG_PAD_OSC_TRIM (0x1FU << RCC_SYSCFG_PAD_OSC_TRIM_Pos) ///< Calibration value of external crystal vibration -#define RCC_SYSCFG_OSC_LPFEN_Pos (14) -#define RCC_SYSCFG_OSC_LPFEN (0x01U << RCC_SYSCFG_OSC_LPFEN_Pos) ///< External crystal oscillator low pass filtering enables -//////////////////////////////////////////////////////////////////////////////// -/// @brief RCC_CFGR2 Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define RCC_CFGR2_TIMADVCKSEL_Pos (1) -#define RCC_CFGR2_TIMADVCKSEL (0x01U << RCC_CFGR2_TIMADVCKSEL_Pos) ///< TIMADV_CKSEL -#define RCC_CFGR2_TIMADV_PRE_Pos (1) ///< -#define RCC_CFGR2_TIMADV_PRE (0x07U << RCC_CFGR2_TIMADV_PRE_Pos) ///< SYSCLK's advance points are controlled by the software Frequency coefficient -#define RCC_CFGR2_FSMC_PRE_Pos (8) -#define RCC_CFGR2_FSMC_PRE (0x1FU << RCC_CFGR2_FSMC_PRE_Pos) ///< FSMC Output clock frequency division factor -#define RCC_CFGR2_APB1_CLK_HV_PRE_Pos (16) -#define RCC_CFGR2_APB1_CLK_HV_PRE (0x0FU << RCC_CFGR2_APB1_CLK_HV_PRE_Pos) ///< APB1 Output clock frequency division factor -//////////////////////////////////////////////////////////////////////////////// -/// @brief RCC_ICSCR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define RCC_ICSCR_TIME_CRS_SEL_Pos (0) -#define RCC_ICSCR_TIME_CRS_SEL (0x01U << RCC_ICSCR_TIME_CRS_SEL_Pos) ///< Whether to use the CRS module as source -#define RCC_ICSCR_HSI_CAL_SEL_Pos (11) ///< -#define RCC_ICSCR_HSI_CAL_SEL (0x1FU << RCC_ICSCR_HSI_CAL_SEL_Pos) ///< Select the internal high speed clock calibration value -#define RCC_ICSCR_HSI_CAL_SFT_Pos (16) -#define RCC_ICSCR_HSI_CAL_SFT (0x3FU << RCC_ICSCR_HSI_CAL_SFT_Pos) ///< Internal high-speed clock calibration -//////////////////////////////////////////////////////////////////////////////// -/// @brief RCC_PLLCFGR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define RCC_PLLCFGR_PLLSRC_Pos (0) -#define RCC_PLLCFGR_PLLSRC (0x01U << RCC_PLLCFGR_PLLSRC_Pos) ///< PLL entry clock source -#define RCC_PLLCFGR_PLLXTPRE_Pos (1) ///< -#define RCC_PLLCFGR_PLLXTPRE (0x01U << RCC_PLLCFGR_PLLXTPRE_Pos) ///< HSE divider for PLL entry -#define RCC_PLLCFGR_PLL_ICTRL_Pos (2) -#define RCC_PLLCFGR_PLL_ICTRL (0x03U << RCC_PLLCFGR_PLL_ICTRL_Pos) ///< PLL CP current control signals -#define RCC_PLLCFGR_PLL_LDS_Pos (4) -#define RCC_PLLCFGR_PLL_LDS (0x03U << RCC_PLLCFGR_PLL_LDS_Pos) ///< PLL lock detector accuracy select -#define RCC_PLLCFGR_PLL_DP_Pos (8) ///< -#define RCC_PLLCFGR_PLL_DP (0x07U << RCC_PLLCFGR_PLL_DP_Pos) ///< PLL divider factor DP -#define RCC_PLLCFGR_PLL_DN_Pos (16) -#define RCC_PLLCFGR_PLL_DN (0x7FU << RCC_PLLCFGR_PLL_DN_Pos) ///< PLL divider factor DN -//////////////////////////////////////////////////////////////////////////////// -/// @brief RCC_HSIDLY Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define RCC_HSIDLY_HSI_EQU_CNT (0xFFU) ///< HSI delay time -//////////////////////////////////////////////////////////////////////////////// -/// @brief RCC_HSEDLY Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define RCC_HSEDLY_HSI_EQU_CNT (0xFFFFU) ///< HSE delay time -//////////////////////////////////////////////////////////////////////////////// -/// @brief RCC_PLLDLY Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define RCC_PLLDLY_HSI_EQU_CNT (0xFFU) ///< PLL delay time - - - -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -#endif -//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_rtc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_rtc.h deleted file mode 100644 index 7f8acab01..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_rtc.h +++ /dev/null @@ -1,203 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file reg_rtc.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF -/// MM32 FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion - -#ifndef __REG_RTC_H -#define __REG_RTC_H - -// Files includes - -#include -#include -#include "types.h" - - - - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - - - - - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief RTC Base Address Definition -//////////////////////////////////////////////////////////////////////////////// -#define RTC_BASE (APB1PERIPH_BASE + 0x2800) ///< Base Address: 0x40002800 - - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief RTC Registers Structure Definition -//////////////////////////////////////////////////////////////////////////////// -typedef struct { - union { - __IO u32 CR; ///< Control Register, offset: 0x00 - __IO u32 CRH; - }; - union { - __IO u32 CSR; ///< Control & Status Register, offset: 0x04 - __IO u32 CRL; - }; - __IO u32 PRLH; ///< Prescaler Reload Value High, offset: 0x08 - __IO u32 PRLL; ///< Prescaler Reload Value Low, offset: 0x0C - __IO u32 DIVH; ///< Clock Divider High, offset: 0x10 - __IO u32 DIVL; ///< Clock Divider Low, offset: 0x14 - __IO u32 CNTH; ///< Counter High, offset: 0x18 - __IO u32 CNTL; ///< Counter Low, offset: 0x1C - __IO u32 ALRH; ///< Alarm High, offset: 0x20 - __IO u32 ALRL; ///< Alarm Low, offset: 0x24 - __IO u32 MSRH; ///< Millisecond alarm high register offset: 0x28 - __IO u32 MSRL; ///< Millisecond alarm low register offset: 0x2C - __IO u32 RESERVED0; ///< Reserved offset: 0x30 - __IO u32 RESERVED1; ///< Reserved offset: 0x34 - __IO u32 RESERVED2; ///< Reserved offset: 0x38 - __IO u32 LSE_CFG; ///< LSE configure register offset: 0x3C -} RTC_TypeDef; - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief RTC type pointer Definition -//////////////////////////////////////////////////////////////////////////////// -#define RTC ((RTC_TypeDef*)RTC_BASE) - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief RTC_CR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define RTC_CR_SECIE_Pos (0) -#define RTC_CR_SECIE (0x01U << RTC_CR_SECIE_Pos) ///< Second Interrupt Enable -#define RTC_CR_ALRIE_Pos (1) -#define RTC_CR_ALRIE (0x01U << RTC_CR_ALRIE_Pos) ///< Alarm Interrupt Enable -#define RTC_CR_OWIE_Pos (2) -#define RTC_CR_OWIE (0x01U << RTC_CR_OWIE_Pos) ///< OverfloW Interrupt Enable - -//////////////////////////////////////////////////////////////////////////////// -/// @brief RTC_CSR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define RTC_CSR_SECF_Pos (0) -#define RTC_CSR_SECF (0x01 << RTC_CSR_SECF_Pos) ///< Second Flag -#define RTC_CSR_ALRF_Pos (1) -#define RTC_CSR_ALRF (0x01 << RTC_CSR_ALRF_Pos) ///< Alarm Flag -#define RTC_CSR_OWF_Pos (2) -#define RTC_CSR_OWF (0x01 << RTC_CSR_OWF_Pos) ///< OverfloW Flag -#define RTC_CSR_RSF_Pos (3) -#define RTC_CSR_RSF (0x01 << RTC_CSR_RSF_Pos) ///< Registers Synchronized Flag -#define RTC_CSR_CNF_Pos (4) -#define RTC_CSR_CNF (0x01 << RTC_CSR_CNF_Pos) ///< Configuration Flag -#define RTC_CSR_RTOFF_Pos (5) -#define RTC_CSR_RTOFF (0x01 << RTC_CSR_RTOFF_Pos) ///< RTC operation OFF -#define RTC_CSR_ALPEN_Pos (6) -#define RTC_CSR_ALPEN (0x01 << RTC_CSR_ALPEN_Pos) ///< RTC Alarm Loop Enable -//////////////////////////////////////////////////////////////////////////////// -/// @brief RTC_PRLH Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define RTC_PRLH_PRL_Pos (0) -#define RTC_PRLH_PRL (0x0F << RTC_PRLH_PRL_Pos) ///< RTC Prescaler Reload Value High - -//////////////////////////////////////////////////////////////////////////////// -/// @brief RTC_PRLL Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define RTC_PRLL_PRL_Pos (0) -#define RTC_PRLL_PRL (0xFFFFU << RTC_PRLL_PRL_Pos) ///< RTC Prescaler Reload Value Low - -//////////////////////////////////////////////////////////////////////////////// -/// @brief RTC_DIVH Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define RTC_DIVH_DIV_Pos (0) -#define RTC_DIVH_DIV (0x0F << RTC_DIVH_DIV_Pos) ///< RTC Clock Divider High - -//////////////////////////////////////////////////////////////////////////////// -/// @brief RTC_DIVL Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define RTC_DIVL_DIV_Pos (0) -#define RTC_DIVL_DIV (0xFFFFU << RTC_DIVL_DIV_Pos) ///< RTC Clock Divider Low - -//////////////////////////////////////////////////////////////////////////////// -/// @brief RTC_CNTH Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define RTC_CNTH_CNT_Pos (0) -#define RTC_CNTH_CNT (0xFFFFU << RTC_CNTH_CNT_Pos) ///< RTC Counter High - -//////////////////////////////////////////////////////////////////////////////// -/// @brief RTC_CNTL Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define RTC_CNTL_CNT_Pos (0) -#define RTC_CNTL_CNT (0xFFFFU << RTC_CNTL_CNT_Pos) ///< RTC Counter Low - -//////////////////////////////////////////////////////////////////////////////// -/// @brief RTC_ALRH Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define RTC_ALRH_ALR_Pos (0) -#define RTC_ALRH_ALR (0xFFFFU << RTC_ALRH_ALR_Pos) ///< RTC Alarm High - -//////////////////////////////////////////////////////////////////////////////// -/// @brief RTC_ALRL Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define RTC_ALRL_ALR_Pos (0) -#define RTC_ALRL_ALR (0xFFFFU << RTC_ALRL_ALR_Pos) ///< RTC Alarm Low - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief RTC_MSRH Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define RTC_MSRH_MSR_Pos (0) -#define RTC_MSRH_MSR (0xFFFFU << RTC_MSRH_MSR_Pos) ///< RTC MS Alarm Register High - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief RTC_MSRL Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define RTC_MSRL_MSR_Pos (0) -#define RTC_MSRL_MSR (0xFFFFU << RTC_MSRL_MSR_Pos) ///< RTC MS Alarm Register Low - -//////////////////////////////////////////////////////////////////////////////// -/// @brief RTC_LSE_CFG Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// - -#define RTC_LSE_CFG_TEST_Pos (0) -#define RTC_LSE_CFG_TEST (0x0FU << RTC_LSE_CFG_TEST_Pos) ///< Test control signal -#define RTC_LSE_CFG_DR_Pos (4) -#define RTC_LSE_CFG_DR (0x03U << RTC_LSE_CFG_DR_Pos) ///< Drive capability selection -#define RTC_LSE_CFG_RFB_SEL_Pos (6) -#define RTC_LSE_CFG_RFB_SEL_3 (0x03U << RTC_LSE_CFG_RFB_SEL_Pos) ///< Feedback resistance selection 3M -#define RTC_LSE_CFG_RFB_SEL_6 (0x02U << RTC_LSE_CFG_RFB_SEL_Pos) ///< Feedback resistance selection 6M -#define RTC_LSE_CFG_RFB_SEL_10 (0x01U << RTC_LSE_CFG_RFB_SEL_Pos) ///< Feedback resistance selection 10M -#define RTC_LSE_CFG_RFB_SEL_12 (0x00U << RTC_LSE_CFG_RFB_SEL_Pos) ///< Feedback resistance selection 12M -#define RTC_LSE_CFG_IB_Pos (8) -#define RTC_LSE_CFG_IB (0x01U << RTC_MSRL_MSR_Pos) ///< Bias current regulation - - -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -#endif -//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_sdio.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_sdio.h deleted file mode 100644 index 9c5d0cb60..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_sdio.h +++ /dev/null @@ -1,391 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file reg_sdio.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF -/// MM32 FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion - -#ifndef __REG_SDIO_H -#define __REG_SDIO_H - -// Files includes - -#include -#include -//#include "types.h" -#include "mm32_reg.h" - -//#if defined ( __CC_ARM ) -//#pragma anon_unions -//#endif - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SDIO Base Address Definition -//////////////////////////////////////////////////////////////////////////////// -#define SDIO_BASE (0x40018000U) ///< Base Address: 0x40018000 - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SDIO Register Structure Definition -//////////////////////////////////////////////////////////////////////////////// - -typedef struct { - __IO u32 MMC_CTRL; ///< SDIO transmit data register, offset: 0x00 - __IO u32 MMC_IO; ///< SDIO receive data register, offset: 0x04 - __IO u32 MMC_BYTECNTL; ///< SDIO current state register, offset: 0x08 - __IO u32 MMC_TR_BLOCKCNT; ///< SDIO interruput state register, offset: 0x0C - __IO u32 MMC_CRCCTL; ///< SDIO interruput enable register, offset: 0x10 - __IO u32 CMD_CRC; ///< SDIO interruput control register, offset: 0x14 - __IO u32 DAT_CRCL; ///< SDIO global control register, offset: 0x18 - __IO u32 DAT_CRCH; ///< SDIO common control register, offset: 0x1C - __IO u32 MMC_PORT; ///< SDIO baud rate control register, offset: 0x20 - __IO u32 MMC_INT_MASK; ///< SDIO receive data number register, offset: 0x24 - __IO u32 CLR_MMC_INT; ///< SDIO chip select register, offset: 0x28 - __IO u32 MMC_CARDSEL; ///< SDIO extand control register, offset: 0x2C - __IO u32 MMC_SIG; ///< 0ffset: 0x30 - __IO u32 MMC_IO_MBCTL; ///< 0ffset: 0x34 - __IO u32 MMC_BLOCKCNT; ///< 0ffset: 0x38 - __IO u32 MMC_TIMEOUTCNT; ///< 0ffset: 0x3C - __IO u32 CMD_BUF0; ///< 0ffset: 0x40 - __IO u32 CMD_BUF1; ///< 0ffset: 0x44 - __IO u32 CMD_BUF2; ///< 0ffset: 0x48 - __IO u32 CMD_BUF3; ///< 0ffset: 0x4C - __IO u32 CMD_BUF4; ///< 0ffset: 0x50 - __IO u32 CMD_BUF5; ///< 0ffset: 0x54 - __IO u32 CMD_BUF6; ///< 0ffset: 0x58 - __IO u32 CMD_BUF7; ///< 0ffset: 0x5C - __IO u32 CMD_BUF8; ///< 0ffset: 0x60 - __IO u32 CMD_BUF9; ///< 0ffset: 0x64 - __IO u32 CMD_BUF10; ///< 0ffset: 0x68 - __IO u32 CMD_BUF11; ///< 0ffset: 0x6C - __IO u32 CMD_BUF12; ///< 0ffset: 0x70 - __IO u32 CMD_BUF13; ///< 0ffset: 0x74 - __IO u32 CMD_BUF14; ///< 0ffset: 0x78 - __IO u32 CMD_BUF15; ///< 0ffset: 0x7C - __IO u32 BUF_CTL; ///< 0ffset: 0x80 - - __IO u32 RESERVED[31]; ///< 0ffset: 0x84 - union { - __IO u32 DATA_BUF0; ///< 0ffset: 0x100 - __IO u32 FIFO; - }; - __IO u32 DATA_BUF1; ///< 0ffset: 0x104 - __IO u32 DATA_BUF2; ///< 0ffset: 0x108 - __IO u32 DATA_BUF3; ///< 0ffset: 0x10C - __IO u32 DATA_BUF4; ///< 0ffset: 0x110 -} SDIO_TypeDef; - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SDIO type pointer Definition -//////////////////////////////////////////////////////////////////////////////// -#define SDIO ((SDIO_TypeDef*) SDIO_BASE) - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SDIO_MMC_CTRL Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define SDIO_MMC_CTRL_OPMSel_Pos (0) -#define SDIO_MMC_CTRL_OPMSel (0x01U << SDIO_MMC_CTRL_OPMSel_Pos) ///< SD/MMC/SDIO port operation mode select -#define SDIO_MMC_CTRL_SelSM_Pos (1) -#define SDIO_MMC_CTRL_SelSM (0x01U << SDIO_MMC_CTRL_SelSM_Pos) ///< Select automatic mode -#define SDIO_MMC_CTRL_OUTM_Pos (2) -#define SDIO_MMC_CTRL_OUTM (0x01U << SDIO_MMC_CTRL_OUTM_Pos) ///< SD/MMC/SDIO port CMD line output driver mode selection Open drain -#define SDIO_MMC_CTRL_CLKSP_Pos (3) -#define SDIO_MMC_CTRL_CLKSP2 (0x00U << SDIO_MMC_CTRL_CLKSP_Pos) ///< SD/MMC/SDIO port CLK linespeedselection 1/2 baseclock -#define SDIO_MMC_CTRL_CLKSP4 (0x01U << SDIO_MMC_CTRL_CLKSP_Pos) ///< SD/MMC/SDIO port CLK linespeedselection 1/4 baseclock -#define SDIO_MMC_CTRL_CLKSP6 (0x02U << SDIO_MMC_CTRL_CLKSP_Pos) ///< SD/MMC/SDIO port CLK linespeedselection 1/6 baseclock -#define SDIO_MMC_CTRL_CLKSP8 (0x03U << SDIO_MMC_CTRL_CLKSP_Pos) ///< SD/MMC/SDIO port CLK linespeedselection 1/8 baseclock -#define SDIO_MMC_CTRL_CLKSP10 (0x04U << SDIO_MMC_CTRL_CLKSP_Pos) ///< SD/MMC/SDIO port CLK linespeedselection 1/10 baseclock -#define SDIO_MMC_CTRL_CLKSP12 (0x05U << SDIO_MMC_CTRL_CLKSP_Pos) ///< SD/MMC/SDIO port CLK linespeedselection 1/12 baseclock -#define SDIO_MMC_CTRL_CLKSP14 (0x06U << SDIO_MMC_CTRL_CLKSP_Pos) ///< SD/MMC/SDIO port CLK linespeedselection 1/14 baseclock -#define SDIO_MMC_CTRL_CLKSP16 (0x07U << SDIO_MMC_CTRL_CLKSP_Pos) ///< SD/MMC/SDIO port CLK linespeedselection 1/16 baseclock -#define SDIO_MMC_CTRL_SelPTSM_Pos (6) -#define SDIO_MMC_CTRL_SelPTSM (0x01U << SDIO_MMC_CTRL_SelPTSM_Pos) ///< SelectSD/MMC/SDIO port transfer high speed mode -#define SDIO_MMC_CTRL_DATWT_Pos (7) -#define SDIO_MMC_CTRL_DATWT (0x01U << SDIO_MMC_CTRL_DATWT_Pos) ///< Definethe bus width of SD/MMC/SDIO port DAT line -#define SDIO_MMC_CTRL_MDEN_Pos (8) -#define SDIO_MMC_CTRL_MDEN (0x01U << SDIO_MMC_CTRL_MDEN_Pos) ///< SDIO mode enable -#define SDIO_MMC_CTRL_INTEN_Pos (9) -#define SDIO_MMC_CTRL_INTEN (0x01U << SDIO_MMC_CTRL_INTEN_Pos) ///< SDIO interrupt enale signal -#define SDIO_MMC_CTRL_RDWTEN_Pos (10) -#define SDIO_MMC_CTRL_RDWTEN (0x01U << SDIO_MMC_CTRL_RDWTEN_Pos) ///< SDIO read wait enable signal -//////////////////////////////////////////////////////////////////////////////// -/// @brief SDIO_MMC_IO Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define SDIO_MMC_IO_AUTODATTR_Pos (0) -#define SDIO_MMC_IO_AUTODATTR (0x01U << SDIO_MMC_IO_AUTODATTR_Pos) ///< Set up automatic data transfer -#define SDIO_MMC_IO_TRANSFDIR_Pos (1) -#define SDIO_MMC_IO_TRANSFDIR (0x01U << SDIO_MMC_IO_TRANSFDIR_Pos) ///< Set the direction of data transfer -#define SDIO_MMC_IO_AUTOTR_Pos (2) -#define SDIO_MMC_IO_AUTOTR (0x01U << SDIO_MMC_IO_AUTOTR_Pos) ///< Set up automatic 8-bit/command/response transmission. -#define SDIO_MMC_IO_RESPCMDSEL_Pos (3) -#define SDIO_MMC_IO_RESPCMDSEL (0x01U << SDIO_MMC_IO_RESPCMDSEL_Pos) ///< Receive response -#define SDIO_MMC_IO_CID_CSDRD_Pos (4) -#define SDIO_MMC_IO_CID_CSDRD (0x01U << SDIO_MMC_IO_CID_CSDRD_Pos) ///< CID and CSD reads -#define SDIO_MMC_IO_PCLKG_Pos (5) -#define SDIO_MMC_IO_PCLKG (0x01U << SDIO_MMC_IO_PCLKG_Pos) ///< SD/MMC/SDIO port CLK line 8 empty clock generated -#define SDIO_MMC_IO_ENRRESP_Pos (6) -#define SDIO_MMC_IO_ENRRESP (0x01U << SDIO_MMC_IO_ENRRESP_Pos) ///< Enable automatic receiving of responses after a command -#define SDIO_MMC_IO_AUTOCLKG_Pos (7) -#define SDIO_MMC_IO_AUTOCLKG (0x01U << SDIO_MMC_IO_AUTOCLKG_Pos) ///< Enable automatic conversion of the 8 empty clock after a response/command or a single block of data -#define SDIO_MMC_IO_CMDCH_Pos (8) -#define SDIO_MMC_IO_CMDCH (0x01U << SDIO_MMC_IO_CMDCH_Pos) ///< SDIO mode enable -#define SDIO_MMC_IO_CMDAF_Pos (9) -#define SDIO_MMC_IO_CMDAF (0x01U << SDIO_MMC_IO_CMDAF_Pos) ///< SDIO CMD12 / IO abort flag -//////////////////////////////////////////////////////////////////////////////// -/// @brief SDIO_MMC_BYTECNTL Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define SDIO_MMC_BYTECNTL_CNT (0xFFFFU) ///< Data transfer byte count register -//////////////////////////////////////////////////////////////////////////////// -/// @brief SDIO_MMC_TR_BLOCKCNT Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define SDIO_MMC_TR_BLOCKCNT_CNT (0xFFFFU) ///< The value of the counter that completes the transfer when multiple blocks are transferred. -//////////////////////////////////////////////////////////////////////////////// -/// @brief SDIO_MMC_CRCCTL Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define SDIO_MMC_CRCCTL_DAT_CRCE_Pos (0) -#define SDIO_MMC_CRCCTL_DAT_CRCE (0x01U << SDIO_MMC_CRCCTL_DAT_CRCE_Pos) ///< DAT CRC error -#define SDIO_MMC_CRCCTL_CMD_CRCE_Pos (1) -#define SDIO_MMC_CRCCTL_CMD_CRCE (0x01U << SDIO_MMC_CRCCTL_CMD_CRCE_Pos) ///< CMD CRC error -#define SDIO_MMC_CRCCTL_DAT_CRCS_Pos (2) -#define SDIO_MMC_CRCCTL_DAT_CRCS (0x03U << SDIO_MMC_CRCCTL_DAT_CRCS_Pos) ///< DAT CRC selection -#define SDIO_MMC_CRCCTL_ENRDMB_Pos (4) -#define SDIO_MMC_CRCCTL_ENRDMB (0x01U << SDIO_MMC_CRCCTL_ENRDMB_Pos) ///< Enable reading multiple blocks of data before responding -#define SDIO_MMC_CRCCTL_ENCHK_Pos (5) -#define SDIO_MMC_CRCCTL_ENCHK (0x01U << SDIO_MMC_CRCCTL_ENCHK_Pos) ///< Enable automatic checking -#define SDIO_MMC_CRCCTL_DAT_CRCEN_Pos (6) -#define SDIO_MMC_CRCCTL_DAT_CRCEN (0x01U << SDIO_MMC_CRCCTL_DAT_CRCEN_Pos) ///< SD/MMC/SDIO PORT DAT line CRC circuit enablement -#define SDIO_MMC_CRCCTL_CMD_CRCEN_Pos (7) -#define SDIO_MMC_CRCCTL_CMD_CRCEN (0x01U << SDIO_MMC_CRCCTL_CMD_CRCEN_Pos) ///< SD/MMC/SDIO port CMD line CRC circuit enablement -//////////////////////////////////////////////////////////////////////////////// -/// @brief SDIO_CMD_CRC Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define SDIO_CMD_CRC_CMD_CRCV (0x7FU) ///< CMD_CRCV register value -//////////////////////////////////////////////////////////////////////////////// -/// @brief SDIO_DAT_CRCL Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define SDIO_DAT_CRCL_DAT_CRCLV (0xFFU) ///< CMD_CRCV low register value -//////////////////////////////////////////////////////////////////////////////// -/// @brief SDIO_DAT_CRCH Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define SDIO_DAT_CRCL_DAT_CRCHV (0xFFU) ///< CMD_CRCV high register value -//////////////////////////////////////////////////////////////////////////////// -/// @brief SDIO_MMC_PORT Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define SDIO_MMC_PORT_NTCR_Pos (0) -#define SDIO_MMC_PORT_NTCR (0x0FU << SDIO_MMC_PORT_NTCR_Pos) ///< Ncr timeout count register -#define SDIO_MMC_PORT_AUTONTEN_Pos (4) -#define SDIO_MMC_PORT_AUTONTEN (0x01U << SDIO_MMC_PORT_AUTONTEN_Pos) ///< Automatic Ncr timer output enablement -#define SDIO_MMC_PORT_PDATS_Pos (5) -#define SDIO_MMC_PORT_PDATS (0x01U << SDIO_MMC_PORT_PDATS_Pos) ///< SD/MMC/SDIO port DAT line signal -#define SDIO_MMC_PORT_PCMDS_Pos (6) -#define SDIO_MMC_PORT_PCMDS (0x01U << SDIO_MMC_PORT_PCMDS_Pos) ///< SD/MMC/SDIO port CMD line signal -#define SDIO_MMC_PORT_PCLKS_Pos (7) -#define SDIO_MMC_PORT_PCLKS (0x01U << SDIO_MMC_PORT_PCLKS_Pos) ///< SD/MMC/SDIO port CLK line signal -//////////////////////////////////////////////////////////////////////////////// -/// @brief SDIO_MMC_INT_MASK Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define SDIO_MMC_INT_MASK_CMDDINT_Pos (0) -#define SDIO_MMC_INT_MASK_CMDDINT (0x01U << SDIO_MMC_INT_MASK_CMDDINT_Pos) ///
© COPYRIGHT MINDMOTION
-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion - -#ifndef __REG_SPI_H -#define __REG_SPI_H - -// Files includes - -#include -#include -#include "types.h" - - - - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - - - - - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SPI Base Address Definition -//////////////////////////////////////////////////////////////////////////////// -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) ///< Base Address: 0x40003800 -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) ///< Base Address: 0x400013000 -#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) ///< Base Address: 0x40003C000 - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SPI Register Structure Definition -//////////////////////////////////////////////////////////////////////////////// -#undef USENCOMBINEREGISTER -#undef USENNEWREGISTER -#undef USENOLDREGISTER -#define USENCOMBINEREGISTER -#ifdef USENCOMBINEREGISTER -typedef struct { - union { - __IO u32 TDR; ///< SPI transmit data register, offset: 0x00 - __IO u32 TXREG; - }; - union { - __IO u32 RDR; ///< SPI receive data register, offset: 0x04 - __IO u32 RXREG; - }; - union { - __IO u32 SR; ///< SPI current state register, offset: 0x08 - __IO u32 CSTAT; - }; - union { - __IO u32 ISR; ///< SPI interruput state register, offset: 0x0C - __IO u32 INTSTAT; - }; - union { - __IO u32 IER; ///< SPI interruput enable register, offset: 0x10 - __IO u32 INTEN; - }; - union { - __IO u32 ICR; ///< SPI interruput control register, offset: 0x14 - __IO u32 INTCLR; - }; - union { - __IO u32 GCR; ///< SPI global control register, offset: 0x18 - __IO u32 GCTL; - }; - union { - __IO u32 CCR; ///< SPI common control register, offset: 0x1C - __IO u32 CCTL; - }; - union { - __IO u32 BRR; ///< SPI baud rate control register, offset: 0x20 - __IO u32 SPBRG; - }; - union { - __IO u32 RDNR; ///< SPI receive data number register, offset: 0x24 - __IO u32 RXDNR; - }; - union { - __IO u32 NSSR; ///< SPI chip select register, offset: 0x28 - __IO u32 SCSR; - }; - union { - __IO u32 ECR; ///< SPI extand control register, offset: 0x2C - __IO u32 EXTCTL; - }; - __IO u32 CFGR; ///< I2S configuration register, offset: 0x30 -} SPI_TypeDef; -#endif -#ifdef USENNEWREGISTER -typedef struct { - __IO u32 TDR; ///< SPI transmit data register, offset: 0x00 - __IO u32 RDR; ///< SPI receive data register, offset: 0x04 - __IO u32 SR; ///< SPI current state register, offset: 0x08 - __IO u32 ISR; ///< SPI interruput state register, offset: 0x0C - __IO u32 IER; ///< SPI interruput enable register, offset: 0x10 - __IO u32 ICR; ///< SPI interruput control register, offset: 0x14 - __IO u32 GCR; ///< SPI global control register, offset: 0x18 - __IO u32 CCR; ///< SPI common control register, offset: 0x1C - __IO u32 BRR; ///< SPI baud rate control register, offset: 0x20 - __IO u32 RDNR; ///< SPI receive data number register, offset: 0x24 - __IO u32 NSSR; ///< SPI chip select register, offset: 0x28 - __IO u32 ECR; ///< SPI extand control register, offset: 0x2C -} SPI_TypeDef; -#endif -#ifdef USENOLDREGISTER -typedef struct { - __IO u32 TXREG; ///< SPI transmit data register, offset: 0x00 - __IO u32 RXREG; ///< SPI receive data register, offset: 0x04 - __IO u32 CSTAT; ///< SPI current state register, offset: 0x08 - __IO u32 INTSTAT; ///< SPI interruput state register, offset: 0x0C - __IO u32 INTEN; ///< SPI interruput enable register, offset: 0x10 - __IO u32 INTCLR; ///< SPI interruput control register, offset: 0x14 - __IO u32 GCTL; ///< SPI global control register, offset: 0x18 - __IO u32 CCTL; ///< SPI common control register, offset: 0x1C - __IO u32 SPBRG; ///< SPI baud rate control register, offset: 0x20 - __IO u32 RXDNR; ///< SPI receive data number register, offset: 0x24 - __IO u32 NSSR; ///< SPI chip select register, offset: 0x28 - __IO u32 EXTCTL; ///< SPI extand control register, offset: 0x2C -} SPI_TypeDef; -#endif - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SPI type pointer Definition -//////////////////////////////////////////////////////////////////////////////// -#define SPI2 ((SPI_TypeDef*) SPI2_BASE) -#define SPI1 ((SPI_TypeDef*) SPI1_BASE) -#define SPI3 ((SPI_TypeDef*) SPI3_BASE) -//////////////////////////////////////////////////////////////////////////////// -/// @brief SPI_TDR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define SPI_TDR_TXREG_Pos (0) -#define SPI_TDR_TXREG (0xFFFFFFFFU << SPI_TDR_TXREG_Pos) ///< Transmit data register - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SPI_RDR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define SPI_RDR_RXREG_Pos (0) -#define SPI_RDR_RXREG (0xFFFFFFFFU << SPI_RDR_RXREG_Pos) ///< Receive data register - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SPI_SR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define SPI_SR_TXEPT_Pos (0) -#define SPI_SR_TXEPT (0x01U << SPI_SR_TXEPT_Pos) ///< Transmitter empty bit -#define SPI_SR_RXAVL_Pos (1) -#define SPI_SR_RXAVL (0x01U << SPI_SR_RXAVL_Pos) ///< Receive available byte data message -#define SPI_SR_TXFULL_Pos (2) -#define SPI_SR_TXFULL (0x01U << SPI_SR_TXFULL_Pos) ///< Transmitter FIFO full status bit -#define SPI_SR_RXAVL_4BYTE_Pos (3) -#define SPI_SR_RXAVL_4BYTE (0x01U << SPI_SR_RXAVL_4BYTE_Pos) ///< Receive available 4 byte data message -#define SPI_SR_TXFADDR_Pos (4) -#define SPI_SR_TXFADDR (0x0FU << SPI_SR_TXFADDR_Pos) ///< Transmit FIFO address -#define SPI_SR_RXFADDR_Pos (8) -#define SPI_SR_RXFADDR (0x0FU << SPI_SR_RXFADDR_Pos) ///< Receive FIFO address -#define SPI_SR_BUSY_Pos (12) -#define SPI_SR_BUSY (0x01U << SPI_SR_BUSY_Pos) ///< Data transfer flag -#define SPI_SR_CHSIDE_Pos (13) -#define SPI_SR_CHSIDE (0x01U << SPI_SR_CHSIDE_Pos) ///< transmission channel -//////////////////////////////////////////////////////////////////////////////// -/// @brief SPI_ISR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define SPI_ISR_TX_INTF_Pos (0) -#define SPI_ISR_TX_INTF (0x01U << SPI_ISR_TX_INTF_Pos) ///< Transmit FIFO available interrupt flag bit -#define SPI_ISR_RX_INTF_Pos (1) -#define SPI_ISR_RX_INTF (0x01U << SPI_ISR_RX_INTF_Pos) ///< Receive data available interrupt flag bit -#define SPI_ISR_UNDERRUN_INTF_Pos (2) -#define SPI_ISR_UNDERRUN_INTF (0x01U << SPI_ISR_UNDERRUN_INTF_Pos) ///< SPI underrun interrupt flag bit -#define SPI_ISR_RXOERR_INTF_Pos (3) -#define SPI_ISR_RXOERR_INTF (0x01U << SPI_ISR_RXOERR_INTF_Pos) ///< Receive overrun error interrupt flag bit -#define SPI_ISR_RXMATCH_INTF_Pos (4) -#define SPI_ISR_RXMATCH_INTF (0x01U << SPI_ISR_RXMATCH_INTF_Pos) ///< Receive data match the RXDNR number, the receive process will be completed and generate the interrupt -#define SPI_ISR_RXFULL_INTF_Pos (5) -#define SPI_ISR_RXFULL_INTF (0x01U << SPI_ISR_RXFULL_INTF_Pos) ///< RX FIFO full interrupt flag bit -#define SPI_ISR_TXEPT_INTF_Pos (6) -#define SPI_ISR_TXEPT_INTF (0x01U << SPI_ISR_TXEPT_INTF_Pos) ///< Transmitter empty interrupt flag bit -#define SPI_ISR_FRE_INTF_Pos (7) -#define SPI_ISR_FRE_INTF (0x01U << SPI_ISR_FRE_INTF_Pos) ///< I2S frame transmission error flag bit -//////////////////////////////////////////////////////////////////////////////// -/// @brief SPI_IER Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define SPI_IER_TX_IEN_Pos (0) -#define SPI_IER_TX_IEN (0x01U << SPI_IER_TX_IEN_Pos) ///< Transmit FIFO empty interrupt enable bit -#define SPI_IER_RX_IEN_Pos (1) -#define SPI_IER_RX_IEN (0x01U << SPI_IER_RX_IEN_Pos) ///< Receive FIFO interrupt enable bit -#define SPI_IER_UNDERRUN_IEN_Pos (2) -#define SPI_IER_UNDERRUN_IEN (0x01U << SPI_IER_UNDERRUN_IEN_Pos) ///< Transmitter underrun interrupt enable bit -#define SPI_IER_RXOERR_IEN_Pos (3) -#define SPI_IER_RXOERR_IEN (0x01U << SPI_IER_RXOERR_IEN_Pos) ///< Overrun error interrupt enable bit -#define SPI_IER_RXMATCH_IEN_Pos (4) -#define SPI_IER_RXMATCH_IEN (0x01U << SPI_IER_RXMATCH_IEN_Pos) ///< Receive data complete interrupt enable bit -#define SPI_IER_RXFULL_IEN_Pos (5) -#define SPI_IER_RXFULL_IEN (0x01U << SPI_IER_RXFULL_IEN_Pos) ///< Receive FIFO full interrupt enable bit -#define SPI_IER_TXEPT_IEN_Pos (6) -#define SPI_IER_TXEPT_IEN (0x01U << SPI_IER_TXEPT_IEN_Pos) ///< Transmit empty interrupt enable bit -#define SPI_IER_FRE_IEN_Pos (7) -#define SPI_IER_FRE_IEN (0x01U << SPI_IER_FRE_IEN_Pos) ///< I2S frame transmission interrupt enable bit -//////////////////////////////////////////////////////////////////////////////// -/// @brief SPI_ICR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define SPI_ICR_TX_ICLR_Pos (0) -#define SPI_ICR_TX_ICLR (0x01U << SPI_ICR_TX_ICLR_Pos) ///< Transmitter FIFO empty interrupt clear bit -#define SPI_ICR_RX_ICLR_Pos (1) -#define SPI_ICR_RX_ICLR (0x01U << SPI_ICR_RX_ICLR_Pos) ///< Receive interrupt clear bit -#define SPI_ICR_UNDERRUN_ICLR_Pos (2) -#define SPI_ICR_UNDERRUN_ICLR (0x01U << SPI_ICR_UNDERRUN_ICLR_Pos) ///< Transmitter underrun interrupt clear bit -#define SPI_ICR_RXOERR_ICLR_Pos (3) -#define SPI_ICR_RXOERR_ICLR (0x01U << SPI_ICR_RXOERR_ICLR_Pos) ///< Overrun error interrupt clear bit -#define SPI_ICR_RXMATCH_ICLR_Pos (4) -#define SPI_ICR_RXMATCH_ICLR (0x01U << SPI_ICR_RXMATCH_ICLR_Pos) ///< Receive completed interrupt clear bit -#define SPI_ICR_RXFULL_ICLR_Pos (5) -#define SPI_ICR_RXFULL_ICLR (0x01U << SPI_ICR_RXFULL_ICLR_Pos) ///< Receiver buffer full interrupt clear bit -#define SPI_ICR_TXEPT_ICLR_Pos (6) -#define SPI_ICR_TXEPT_ICLR (0x01U << SPI_ICR_TXEPT_ICLR_Pos) ///< Transmitter empty interrupt clear bit -#define SPI_ICR_FRE_ICLR_Pos (7) -#define SPI_ICR_FRE_ICLR (0x01U << SPI_ICR_FRE_ICLR_Pos) ///< I2S frame transmission interrupt clear bit -//////////////////////////////////////////////////////////////////////////////// -/// @brief SPI_GCR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define SPI_GCR_SPIEN_Pos (0) -#define SPI_GCR_SPIEN (0x01U << SPI_GCR_SPIEN_Pos) ///< SPI select bit -#define SPI_GCR_IEN_Pos (1) -#define SPI_GCR_IEN (0x01U << SPI_GCR_IEN_Pos) ///< SPI interrupt enable bit -#define SPI_GCR_MODE_Pos (2) -#define SPI_GCR_MODE (0x01U << SPI_GCR_MODE_Pos) ///< Master mode bit -#define SPI_GCR_TXEN_Pos (3) -#define SPI_GCR_TXEN (0x01U << SPI_GCR_TXEN_Pos) ///< Transmit enable bit -#define SPI_GCR_RXEN_Pos (4) -#define SPI_GCR_RXEN (0x01U << SPI_GCR_RXEN_Pos) ///< Receive enable bit - -#define SPI_GCR_RXTLF_Pos (5) -#define SPI_GCR_RXTLF (0x03U << SPI_GCR_RXTLF_Pos) ///< RX FIFO trigger level bit -#define SPI_GCR_RXTLF_One (0x00U << SPI_GCR_RXTLF_Pos) ///< -#define SPI_GCR_RXTLF_Half (0x01U << SPI_GCR_RXTLF_Pos) ///< - -#define SPI_GCR_TXTLF_Pos (7) -#define SPI_GCR_TXTLF (0x03U << SPI_GCR_TXTLF_Pos) ///< TX FIFO trigger level bit -#define SPI_GCR_TXTLF_One (0x00U << SPI_GCR_TXTLF_Pos) ///< -#define SPI_GCR_TXTLF_Half (0x01U << SPI_GCR_TXTLF_Pos) ///< -#define SPI_GCR_DMAEN_Pos (9) -#define SPI_GCR_DMAEN (0x01U << SPI_GCR_DMAEN_Pos) ///< DMA access mode enable -#define SPI_GCR_NSS_Pos (10) -#define SPI_GCR_NSS (0x01U << SPI_GCR_NSS_Pos) ///< NSS select signal that from software or hardware -#define SPI_GCR_DWSEL_Pos (11) -#define SPI_GCR_DWSEL (0x01U << SPI_GCR_DWSEL_Pos) ///< Valid byte or double-word data select signal - -#define SPI_GCR_NSSTOG_Pos (12) -#define SPI_GCR_NSSTOG (0x01U << SPI_GCR_NSSTOG_Pos) ///< Slave select toggle -#define SPI_GCR_PAD_SEL_Pos (13) -#define SPI_GCR_PAD_SEL (0x1FU << SPI_GCR_PAD_SEL_Pos) ///< Bus mapping transformation -//////////////////////////////////////////////////////////////////////////////// -/// @brief SPI_CCR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define SPI_CCR_CPHA_Pos (0) -#define SPI_CCR_CPHA (0x01U << SPI_CCR_CPHA_Pos) ///< Clock phase select bit -#define SPI_CCR_CPOL_Pos (1) -#define SPI_CCR_CPOL (0x01U << SPI_CCR_CPOL_Pos) ///< Clock polarity select bit -#define SPI_CCR_LSBFE_Pos (2) -#define SPI_CCR_LSBFE (0x01U << SPI_CCR_LSBFE_Pos) ///< LSI first enable bit -#define SPI_CCR_SPILEN_Pos (3) -#define SPI_CCR_SPILEN (0x01U << SPI_CCR_SPILEN_Pos) ///< SPI character length bit -#define SPI_CCR_RXEDGE_Pos (4) -#define SPI_CCR_RXEDGE (0x01U << SPI_CCR_RXEDGE_Pos) ///< Receive data edge select -#define SPI_CCR_TXEDGE_Pos (5) -#define SPI_CCR_TXEDGE (0x01U << SPI_CCR_TXEDGE_Pos) ///< Transmit data edge select - -#define SPI_CCR_CPHASEL_Pos (6) -#define SPI_CCR_CPHASEL (0x01U << SPI_CCR_CPHASEL) ///< CPHA polarity select - -#define SPI_CCR_HISPD_Pos (7) -#define SPI_CCR_HISPD (0x01U << SPI_CCR_HISPD) ///< High speed slave mode - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SPI_BRR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define SPI_BRR_DIVF_Pos (0) -#define SPI_BRR_DIVF (0xFFFFU << SPI_BRR_DIVF_Pos) ///< SPI baud rate control register for baud rate - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SPI_RDNR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define SPI_RDNR_RDN_Pos (0) -#define SPI_RDNR_RDN (0xFFFFU << SPI_RDNR_RDN_Pos) ///< The register is used to hold a count of to be received bytes in next receive process - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SPI_NSSR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define SPI_NSSR_NSS_Pos (0) -#define SPI_NSSR_NSS (0xFFU << SPI_NSSR_NSS_Pos) ///< Chip select output signal in Master mode - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SPI_ECR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define SPI_ECR_EXTLEN_Pos (0) -#define SPI_ECR_EXTLEN (0x1FU << SPI_ECR_EXTLEN_Pos) ///< control SPI data length - -//////////////////////////////////////////////////////////////////////////////// -/// @brief I2S_CFGR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// - -#define I2SCFGR_CLEAR_Mask ((u32)0xFE00F388) -#define I2S_CFGR_CHLEN_Pos (0) -#define I2S_CFGR_CHLEN (0x01U << I2S_CFGR_CHLEN_Pos) ///< Vocal tract length -#define I2S_CFGR_DATLEN_Pos (1) -#define I2S_CFGR_DATLEN_16 (0x00U << I2S_CFGR_DATLEN_Pos) ///< Audio data width 16 -#define I2S_CFGR_DATLEN_24 (0x01U << I2S_CFGR_DATLEN_Pos) ///< Audio data width 24 -#define I2S_CFGR_DATLEN_32 (0x02U << I2S_CFGR_DATLEN_Pos) ///< Audio data width 32 - -#define I2S_CFGR_I2SSTD_Pos (4) -#define I2S_CFGR_I2SSTD_PCM (0x00U << I2S_CFGR_I2SSTD_Pos) ///< I2S selection PCM standard -#define I2S_CFGR_I2SSTD_MSB_R (0x01U << I2S_CFGR_I2SSTD_Pos) ///< I2S selection Right alignment (MSB) standard -#define I2S_CFGR_I2SSTD_MSB_L (0x02U << I2S_CFGR_I2SSTD_Pos) ///< I2S selection Left aligned (MSB) standard -#define I2S_CFGR_I2SSTD_Philips (0x03U << I2S_CFGR_I2SSTD_Pos) ///< I2S selection Philips standard - -#define I2S_CFGR_PCMSYNC_Pos (6) -#define I2S_CFGR_PCMSYNC (0x01U << I2S_CFGR_PCMSYNC_Pos) ///< PCM frame synchronization mode -#define I2S_CFGR_SPI_I2S_Pos (10) -#define I2S_CFGR_SPI_I2S (0x01U << I2S_CFGR_SPI_I2S_Pos) ///< SPI/I2S module function selection -#define I2S_CFGR_MCKOE_Pos (11) -#define I2S_CFGR_MCKOE (0x01U << I2S_CFGR_MCKOE_Pos) ///< I2S master clock output enable -#define I2S_CFGR_I2SDIV_Pos (16) -#define I2S_CFGR_I2SDIV (0x1FFU << I2S_CFGR_I2SDIV_Pos) ///< The frequency division - - - -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -#endif -//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_syscfg.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_syscfg.h deleted file mode 100644 index 677250dc8..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_syscfg.h +++ /dev/null @@ -1,299 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file reg_syscfg.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF -/// MM32 FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion - -#ifndef __REG_SYSCFG_H -#define __REG_SYSCFG_H - -// Files includes - -#include -#include -#include "types.h" - - - - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - - - - - - - - - -#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000) ///< Base Address: 0x40010000 - - - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief SysTem Configuration Register Structure Definition -//////////////////////////////////////////////////////////////////////////////// -typedef struct { - union { - __IO u32 CFGR; ///< SYSCFG configuration register offset: 0x00 - __IO u32 CFGR1; - }; - __IO u32 RESERVED0x04; ///< RESERVED register offset: 0x04 - __IO u32 EXTICR[4]; ///< SYSCFG configuration register offset: 0x08-0x14 - __IO u32 CFGR2; ///< SYSCFG configuration2 register offset: 0x18 - __IO u32 PDETCSR; ///< SYSCFG Power Detect configuration stautus reg offset: 0x1C - __IO u32 VOSDLY; ///< SYSCFG VOSDLY Counter register offset: 0x20 -} SYSCFG_TypeDef; - - -#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) - - - -//////////////////////////////////////////////////////////////////////////////// -///@brief System Configuration (SYSCFG) -//////////////////////////////////////////////////////////////////////////////// - -/// @brief SYSCFG_CFGR Register Bit definition -#define SYSCFG_CFGR_MEM_MODE_Pos (0) -#define SYSCFG_CFGR_MEM_MODE ((u32)0x00000003) ///< SYSCFG_Memory Remap Config -#define SYSCFG_CFGR_MEM_MODE_0 ((u32)0x00000001) ///< SYSCFG_Memory Remap Config Bit 0 -#define SYSCFG_CFGR_MEM_MODE_1 ((u32)0x00000002) ///< SYSCFG_Memory Remap Config Bit 1 -/// - -#define SYSCFG_CFGR_FSMC_SYNC_EN_Pos (27) -#define SYSCFG_CFGR_FSMC_SYNC_EN (0x01U << SYSCFG_CFGR_FSMC_SYNC_EN_Pos)///< FSMC SYNC Enable -#define SYSCFG_CFGR_FSMC_AF_ADDR_Pos (28) -#define SYSCFG_CFGR_FSMC_AF_ADDR (0x01U << SYSCFG_CFGR_FSMC_AF_ADDR_Pos)///< FSMC Databus AF Address -#define SYSCFG_CFGR_FSMC_MODE_Pos (29) -#define SYSCFG_CFGR_FSMC_MODE ((u32)0x03<
© COPYRIGHT MINDMOTION
-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion - -#ifndef __REG_TIM_H -#define __REG_TIM_H - -// Files includes - -#include -#include -#include "types.h" - - - - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - - - - - - - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM Base Address Definition -//////////////////////////////////////////////////////////////////////////////// -#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) ///< Base Address: 0x40012C00 -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) ///< Base Address: 0x40000000 -#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) ///< Base Address: 0x40000400 -#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) ///< Base Address: 0x40000800 - -#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) ///< Base Address: 0x40000C00 -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) ///< Base Address: 0x40001000 -#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) ///< Base Address: 0x40001400 -#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) ///< Base Address: 0x40013400 - - - - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief Timer Register Structure Definition -//////////////////////////////////////////////////////////////////////////////// -typedef struct { - __IO u32 CR1; ///< TIM control register 1, offset: 0x00 - __IO u32 CR2; ///< TIM control register 2, offset: 0x04 - __IO u32 SMCR; ///< TIM slave Mode Control register, offset: 0x08 - __IO u32 DIER; ///< TIM DMA/interrupt enable register, offset: 0x0C - __IO u32 SR; ///< TIM status register, offset: 0x10 - __IO u32 EGR; ///< TIM event generation register, offset: 0x14 - __IO u32 CCMR1; ///< TIM capture/compare mode register 1, offset: 0x18 - __IO u32 CCMR2; ///< TIM capture/compare mode register 2, offset: 0x1C - __IO u32 CCER; ///< TIM capture/compare enable register, offset: 0x20 - __IO u32 CNT; ///< TIM counter register, offset: 0x24 - __IO u32 PSC; ///< TIM prescaler register, offset: 0x28 - __IO u32 ARR; ///< TIM auto-reload register, offset: 0x2C - __IO u32 RCR; ///< TIM repetition counter register, offset: 0x30 - __IO u32 CCR1; ///< TIM capture/compare register 1, offset: 0x34 - __IO u32 CCR2; ///< TIM capture/compare register 2, offset: 0x38 - __IO u32 CCR3; ///< TIM capture/compare register 3, offset: 0x3C - __IO u32 CCR4; ///< TIM capture/compare register 4, offset: 0x40 - __IO u32 BDTR; ///< TIM break and dead-time register, offset: 0x44 - __IO u32 DCR; ///< TIM DMA control register, offset: 0x48 - __IO u32 DMAR; ///< TIM DMA address for full transfer register, offset: 0x4C - __IO u32 OR; ///< Option register, offset: 0x50 - __IO u32 CCMR3; ///< TIM capture/compare mode register 3, offset: 0x54 - __IO u32 CCR5; ///< TIM capture/compare register 5, offset: 0x58 - __IO u32 PDER; ///< PWM Shift repeat enable register, offset: 0x5C - __IO u32 CCR1FALL; ///< PWM shift count CCR1 register, offset: 0x60 - __IO u32 CCR2FALL; ///< PWM shift count CCR2 register, offset: 0x64 - __IO u32 CCR3FALL; ///< PWM shift count CCR3 register, offset: 0x68 - __IO u32 CCR4FALL; ///< PWM shift count CCR4 register, offset: 0x6c - __IO u32 CCR5FALL; ///< PWM shift count CCR5 register, offset: 0x70 -} TIM_TypeDef; - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM type pointer Definition -//////////////////////////////////////////////////////////////////////////////// -#define TIM1 ((TIM_TypeDef*) TIM1_BASE) -#define TIM2 ((TIM_TypeDef*) TIM2_BASE) -#define TIM3 ((TIM_TypeDef*) TIM3_BASE) -#define TIM4 ((TIM_TypeDef*) TIM4_BASE) - -#define TIM5 ((TIM_TypeDef*) TIM5_BASE) -#define TIM6 ((TIM_TypeDef*) TIM6_BASE) -#define TIM7 ((TIM_TypeDef*) TIM7_BASE) - -#define TIM8 ((TIM_TypeDef*) TIM8_BASE) - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_CR1 Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define TIM_CR1_CEN_Pos (0) -#define TIM_CR1_CEN (0x01U << TIM_CR1_CEN_Pos) ///< Counter enable -#define TIM_CR1_UDIS_Pos (1) -#define TIM_CR1_UDIS (0x01U << TIM_CR1_UDIS_Pos) ///< Update disable -#define TIM_CR1_URS_Pos (2) -#define TIM_CR1_URS (0x01U << TIM_CR1_URS_Pos) ///< Update request source -#define TIM_CR1_OPM_Pos (3) -#define TIM_CR1_OPM (0x01U << TIM_CR1_OPM_Pos) ///< One pulse mode -#define TIM_CR1_DIR_Pos (4) -#define TIM_CR1_DIR (0x01U << TIM_CR1_DIR_Pos) ///< Direction -#define TIM_CR1_CMS_Pos (5) -#define TIM_CR1_CMS (0x03U << TIM_CR1_CMS_Pos) ///< CMS[1:0] bits (Center-aligned mode selection) -#define TIM_CR1_CMS_EDGEALIGNED (0x00U << TIM_CR1_CMS_Pos) ///< Edge-aligned mode -#define TIM_CR1_CMS_CENTERALIGNED1 (0x01U << TIM_CR1_CMS_Pos) ///< Center-aligned mode 1 -#define TIM_CR1_CMS_CENTERALIGNED2 (0x02U << TIM_CR1_CMS_Pos) ///< Center-aligned mode 2 -#define TIM_CR1_CMS_CENTERALIGNED3 (0x03U << TIM_CR1_CMS_Pos) ///< Center-aligned mode 3 -#define TIM_CR1_ARPEN_Pos (7) -#define TIM_CR1_ARPEN (0x01U << TIM_CR1_ARPEN_Pos) ///< Auto-reload preload enable -#define TIM_CR1_CKD_Pos (8) -#define TIM_CR1_CKD (0x03U << TIM_CR1_CKD_Pos) ///< CKD[1:0] bits (clock division) -#define TIM_CR1_CKD_DIV1 (0x00U << TIM_CR1_CKD_Pos) ///< Divided by 1 -#define TIM_CR1_CKD_DIV2 (0x01U << TIM_CR1_CKD_Pos) ///< Divided by 2 -#define TIM_CR1_CKD_DIV4 (0x02U << TIM_CR1_CKD_Pos) ///< Divided by 4 - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_CR2 Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define TIM_CR2_CCPC_Pos (0) -#define TIM_CR2_CCPC (0x01U << TIM_CR2_CCPC_Pos) ///< Capture/Compare Preloaded Control -#define TIM_CR2_CCUS_Pos (2) -#define TIM_CR2_CCUS (0x01U << TIM_CR2_CCUS_Pos) ///< Capture/Compare Control Update Selection -#define TIM_CR2_CCDS_Pos (3) -#define TIM_CR2_CCDS (0x01U << TIM_CR2_CCDS_Pos) ///< Capture/Compare DMA Selection -#define TIM_CR2_MMS_Pos (4) -#define TIM_CR2_MMS (0x07U << TIM_CR2_MMS_Pos) ///< MMS[2:0] bits (Master Mode Selection) -#define TIM_CR2_MMS_RESET (0x00U << TIM_CR2_MMS_Pos) ///< Master Mode Select: Reset -#define TIM_CR2_MMS_ENABLE (0x01U << TIM_CR2_MMS_Pos) ///< Master Mode Select: Enable -#define TIM_CR2_MMS_UPDATE (0x02U << TIM_CR2_MMS_Pos) ///< Master Mode Select: Update -#define TIM_CR2_MMS_OC1 (0x03U << TIM_CR2_MMS_Pos) ///< Master Mode Select: OC1 -#define TIM_CR2_MMS_OC1REF (0x04U << TIM_CR2_MMS_Pos) ///< Master Mode Select: OC1Ref -#define TIM_CR2_MMS_OC2REF (0x05U << TIM_CR2_MMS_Pos) ///< Master Mode Select: OC2Ref -#define TIM_CR2_MMS_OC3REF (0x06U << TIM_CR2_MMS_Pos) ///< Master Mode Select: OC3Ref -#define TIM_CR2_MMS_OC4REF (0x07U << TIM_CR2_MMS_Pos) ///< Master Mode Select: OC4Ref -#define TIM_CR2_TI1S_Pos (7) -#define TIM_CR2_TI1S (0x01U << TIM_CR2_TI1S_Pos) ///< TI1 Selection -#define TIM_CR2_OIS1_Pos (8) -#define TIM_CR2_OIS1 (0x01U << TIM_CR2_OIS1_Pos) ///< Output Idle state 1 (OC1 output) -#define TIM_CR2_OIS1N_Pos (9) -#define TIM_CR2_OIS1N (0x01U << TIM_CR2_OIS1N_Pos) ///< Output Idle state 1 (OC1N output) -#define TIM_CR2_OIS2_Pos (10) -#define TIM_CR2_OIS2 (0x01U << TIM_CR2_OIS2_Pos) ///< Output Idle state 2 (OC2 output) -#define TIM_CR2_OIS2N_Pos (11) -#define TIM_CR2_OIS2N (0x01U << TIM_CR2_OIS2N_Pos) ///< Output Idle state 2 (OC2N output) -#define TIM_CR2_OIS3_Pos (12) -#define TIM_CR2_OIS3 (0x01U << TIM_CR2_OIS3_Pos) ///< Output Idle state 3 (OC3 output) -#define TIM_CR2_OIS3N_Pos (13) -#define TIM_CR2_OIS3N (0x01U << TIM_CR2_OIS3N_Pos) ///< Output Idle state 3 (OC3N output) -#define TIM_CR2_OIS4_Pos (14) -#define TIM_CR2_OIS4 (0x01U << TIM_CR2_OIS4_Pos) ///< Output Idle state 4 (OC4 output) - - -#define TIM_CR2_OIS5_Pos (16) -#define TIM_CR2_OIS5 (0x01U << TIM_CR2_OIS5_Pos) ///< Output Idle state 5 (OC5 output) - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_SMCR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define TIM_SMCR_SMS_Pos (0) -#define TIM_SMCR_SMS (0x07U << TIM_SMCR_SMS_Pos) ///< SMS[2:0] bits (Slave mode selection) -#define TIM_SMCR_SMS_OFF (0x00U << TIM_SMCR_SMS_Pos) ///< Slave Mode select: OFF -#define TIM_SMCR_SMS_ENCODER1 (0x01U << TIM_SMCR_SMS_Pos) ///< Slave Mode select: Encoder1 -#define TIM_SMCR_SMS_ENCODER2 (0x02U << TIM_SMCR_SMS_Pos) ///< Slave Mode select: Encoder2 -#define TIM_SMCR_SMS_ENCODER3 (0x03U << TIM_SMCR_SMS_Pos) ///< Slave Mode select: Encoder3 -#define TIM_SMCR_SMS_RESET (0x04U << TIM_SMCR_SMS_Pos) ///< Slave Mode select: Reset -#define TIM_SMCR_SMS_GATED (0x05U << TIM_SMCR_SMS_Pos) ///< Slave Mode select: Gated -#define TIM_SMCR_SMS_TRIGGER (0x06U << TIM_SMCR_SMS_Pos) ///< Slave Mode select: Trigger -#define TIM_SMCR_SMS_EXTERNAL1 (0x07U << TIM_SMCR_SMS_Pos) ///< Slave Mode select: External1 - -#define TIM_SMCR_OCCS_Pos (3) -#define TIM_SMCR_OCCS (0x01U << TIM_SMCR_OCCS_Pos) ///< Output compare clear selection - -#define TIM_SMCR_TS_Pos (4) -#define TIM_SMCR_TS (0x07U << TIM_SMCR_TS_Pos) ///< TS[2:0] bits (Trigger selection) -#define TIM_SMCR_TS_ITR0 (0x00U << TIM_SMCR_TS_Pos) ///< Internal Trigger 0 (ITR0) -#define TIM_SMCR_TS_ITR1 (0x01U << TIM_SMCR_TS_Pos) ///< Internal Trigger 1 (ITR1) -#define TIM_SMCR_TS_ITR2 (0x02U << TIM_SMCR_TS_Pos) ///< Internal Trigger 2 (ITR2) -#define TIM_SMCR_TS_ITR3 (0x03U << TIM_SMCR_TS_Pos) ///< Internal Trigger 3 (ITR3) -#define TIM_SMCR_TS_TI1F_ED (0x04U << TIM_SMCR_TS_Pos) ///< TI1 Edge Detector (TI1F_ED) -#define TIM_SMCR_TS_TI1FP1 (0x05U << TIM_SMCR_TS_Pos) ///< Filtered Timer Input 1 (TI1FP1) -#define TIM_SMCR_TS_TI2FP2 (0x06U << TIM_SMCR_TS_Pos) ///< Filtered Timer Input 2 (TI2FP2) -#define TIM_SMCR_TS_ETRF (0x07U << TIM_SMCR_TS_Pos) ///< External Trigger input (ETRF) -#define TIM_SMCR_MSM_Pos (7) -#define TIM_SMCR_MSM (0x01U << TIM_SMCR_MSM_Pos) ///< Master/slave mode -#define TIM_SMCR_ETF_Pos (8) -#define TIM_SMCR_ETF (0x0FU << TIM_SMCR_ETF_Pos) ///< ETF[3:0] bits (External trigger filter) -#define TIM_SMCR_ETF_0 (0x01U << TIM_SMCR_ETF_Pos) ///< Bit 0 -#define TIM_SMCR_ETF_1 (0x02U << TIM_SMCR_ETF_Pos) ///< Bit 1 -#define TIM_SMCR_ETF_2 (0x04U << TIM_SMCR_ETF_Pos) ///< Bit 2 -#define TIM_SMCR_ETF_3 (0x08U << TIM_SMCR_ETF_Pos) ///< Bit 3 -#define TIM_SMCR_ETPS_Pos (12) -#define TIM_SMCR_ETPS (0x03U << TIM_SMCR_ETPS_Pos) ///< ETPS[1:0] bits (External trigger prescaler) -#define TIM_SMCR_ETPS_OFF (0x00U << TIM_SMCR_ETPS_Pos) ///< Prescaler OFF -#define TIM_SMCR_ETPS_DIV2 (0x01U << TIM_SMCR_ETPS_Pos) ///< ETRP frequency divided by 2 -#define TIM_SMCR_ETPS_DIV4 (0x02U << TIM_SMCR_ETPS_Pos) ///< ETRP frequency divided by 4 -#define TIM_SMCR_ETPS_DIV8 (0x03U << TIM_SMCR_ETPS_Pos) ///< ETRP frequency divided by 8 -#define TIM_SMCR_ECEN_Pos (14) -#define TIM_SMCR_ECEN (0x01U << TIM_SMCR_ECEN_Pos) ///< External clock enable -#define TIM_SMCR_ETP_Pos (15) -#define TIM_SMCR_ETP (0x01U << TIM_SMCR_ETP_Pos) ///< External trigger polarity -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_DIER Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define TIM_DIER_UI_Pos (0) -#define TIM_DIER_UI (0x01U << TIM_DIER_UI_Pos) ///< Update interrupt enable -#define TIM_DIER_CC1I_Pos (1) -#define TIM_DIER_CC1I (0x01U << TIM_DIER_CC1I_Pos) ///< Capture/Compare 1 interrupt enable -#define TIM_DIER_CC2I_Pos (2) -#define TIM_DIER_CC2I (0x01U << TIM_DIER_CC2I_Pos) ///< Capture/Compare 2 interrupt enable -#define TIM_DIER_CC3I_Pos (3) -#define TIM_DIER_CC3I (0x01U << TIM_DIER_CC3I_Pos) ///< Capture/Compare 3 interrupt enable -#define TIM_DIER_CC4I_Pos (4) -#define TIM_DIER_CC4I (0x01U << TIM_DIER_CC4I_Pos) ///< Capture/Compare 4 interrupt enable -#define TIM_DIER_COMI_Pos (5) -#define TIM_DIER_COMI (0x01U << TIM_DIER_COMI_Pos) ///< COM interrupt enable -#define TIM_DIER_TI_Pos (6) -#define TIM_DIER_TI (0x01U << TIM_DIER_TI_Pos) ///< Trigger interrupt enable -#define TIM_DIER_BI_Pos (7) -#define TIM_DIER_BI (0x01U << TIM_DIER_BI_Pos) ///< Break interrupt enable -#define TIM_DIER_UD_Pos (8) -#define TIM_DIER_UD (0x01U << TIM_DIER_UD_Pos) ///< Update DMA request enable -#define TIM_DIER_CC1D_Pos (9) -#define TIM_DIER_CC1D (0x01U << TIM_DIER_CC1D_Pos) ///< Capture/Compare 1 DMA request enable -#define TIM_DIER_CC2D_Pos (10) -#define TIM_DIER_CC2D (0x01U << TIM_DIER_CC2D_Pos) ///< Capture/Compare 2 DMA request enable -#define TIM_DIER_CC3D_Pos (11) -#define TIM_DIER_CC3D (0x01U << TIM_DIER_CC3D_Pos) ///< Capture/Compare 3 DMA request enable -#define TIM_DIER_CC4D_Pos (12) -#define TIM_DIER_CC4D (0x01U << TIM_DIER_CC4D_Pos) ///< Capture/Compare 4 DMA request enable -#define TIM_DIER_COMD_Pos (13) -#define TIM_DIER_COMD (0x01U << TIM_DIER_COMD_Pos) ///< COM DMA request enable -#define TIM_DIER_TD_Pos (14) -#define TIM_DIER_TD (0x01U << TIM_DIER_TD_Pos) ///< Trigger DMA request enable -#define TIM_DIER_CC5I_Pos (16) -#define TIM_DIER_CC5I (0x01U << TIM_DIER_CC5I_Pos) ///< Capture/Compare 5 interrupt enable - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_SR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define TIM_SR_UI_Pos (0) -#define TIM_SR_UI (0x01U << TIM_SR_UI_Pos) ///< Update interrupt Flag -#define TIM_SR_CC1I_Pos (1) -#define TIM_SR_CC1I (0x01U << TIM_SR_CC1I_Pos) ///< Capture/Compare 1 interrupt Flag -#define TIM_SR_CC2I_Pos (2) -#define TIM_SR_CC2I (0x01U << TIM_SR_CC2I_Pos) ///< Capture/Compare 2 interrupt Flag -#define TIM_SR_CC3I_Pos (3) -#define TIM_SR_CC3I (0x01U << TIM_SR_CC3I_Pos) ///< Capture/Compare 3 interrupt Flag -#define TIM_SR_CC4I_Pos (4) -#define TIM_SR_CC4I (0x01U << TIM_SR_CC4I_Pos) ///< Capture/Compare 4 interrupt Flag -#define TIM_SR_COMI_Pos (5) -#define TIM_SR_COMI (0x01U << TIM_SR_COMI_Pos) ///< COM interrupt Flag -#define TIM_SR_TI_Pos (6) -#define TIM_SR_TI (0x01U << TIM_SR_TI_Pos) ///< Trigger interrupt Flag -#define TIM_SR_BI_Pos (7) -#define TIM_SR_BI (0x01U << TIM_SR_BI_Pos) ///< Break interrupt Flag -#define TIM_SR_CC1O_Pos (9) -#define TIM_SR_CC1O (0x01U << TIM_SR_CC1O_Pos) ///< Capture/Compare 1 Overcapture Flag -#define TIM_SR_CC2O_Pos (10) -#define TIM_SR_CC2O (0x01U << TIM_SR_CC2O_Pos) ///< Capture/Compare 2 Overcapture Flag -#define TIM_SR_CC3O_Pos (11) -#define TIM_SR_CC3O (0x01U << TIM_SR_CC3O_Pos) ///< Capture/Compare 3 Overcapture Flag -#define TIM_SR_CC4O_Pos (12) -#define TIM_SR_CC4O (0x01U << TIM_SR_CC4O_Pos) ///< Capture/Compare 4 Overcapture Flag - -#define TIM_SR_CC5I_Pos (16) -#define TIM_SR_CC5I (0x01U << TIM_SR_CC5I_Pos) ///< Capture/Compare 5 interrupt Flag - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_EGR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define TIM_EGR_UG_Pos (0) -#define TIM_EGR_UG (0x01U << TIM_EGR_UG_Pos) ///< Update Generation -#define TIM_EGR_CC1G_Pos (1) -#define TIM_EGR_CC1G (0x01U << TIM_EGR_CC1G_Pos) ///< Capture/Compare 1 Generation -#define TIM_EGR_CC2G_Pos (2) -#define TIM_EGR_CC2G (0x01U << TIM_EGR_CC2G_Pos) ///< Capture/Compare 2 Generation -#define TIM_EGR_CC3G_Pos (3) -#define TIM_EGR_CC3G (0x01U << TIM_EGR_CC3G_Pos) ///< Capture/Compare 3 Generation -#define TIM_EGR_CC4G_Pos (4) -#define TIM_EGR_CC4G (0x01U << TIM_EGR_CC4G_Pos) ///< Capture/Compare 4 Generation -#define TIM_EGR_COMG_Pos (5) -#define TIM_EGR_COMG (0x01U << TIM_EGR_COMG_Pos) ///< Capture/Compare Control Update Generation -#define TIM_EGR_TG_Pos (6) -#define TIM_EGR_TG (0x01U << TIM_EGR_TG_Pos) ///< Trigger Generation -#define TIM_EGR_BG_Pos (7) -#define TIM_EGR_BG (0x01U << TIM_EGR_BG_Pos) ///< Break Generation - -#define TIM_EGR_CC5G_Pos (16) -#define TIM_EGR_CC5G (0x01U << TIM_EGR_CC5G_Pos) ///< Capture/Compare 5 Generation - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_CCMR1 Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define TIM_CCMR1_CC1S_Pos (0) -#define TIM_CCMR1_CC1S (0x03U << TIM_CCMR1_CC1S_Pos) ///< CC1S[1:0] bits (Capture/Compare 1 Selection) -#define TIM_CCMR1_CC1S_OC (0x00U << TIM_CCMR1_CC1S_Pos) ///< Channel is configured as output -#define TIM_CCMR1_CC1S_DIRECTTI (0x01U << TIM_CCMR1_CC1S_Pos) ///< Channel is configured as input, IC1 is mapped on TI1 -#define TIM_CCMR1_CC1S_INDIRECTTI (0x02U << TIM_CCMR1_CC1S_Pos) ///< Channel is configured as input, IC1 is mapped on TI2 -#define TIM_CCMR1_CC1S_TRC (0x03U << TIM_CCMR1_CC1S_Pos) ///< Channel is configured as input, IC1 is mapped on TRC -#define TIM_CCMR1_OC1FEN_Pos (2) -#define TIM_CCMR1_OC1FEN (0x01U << TIM_CCMR1_OC1FEN_Pos) ///< Output Compare 1 Fast enable - -#define TIM_CCMR1_OC1PEN_Pos (3) -#define TIM_CCMR1_OC1PEN (0x01U << TIM_CCMR1_OC1PEN_Pos) ///< Output Compare 1 Preload enable -#define TIM_CCMR1_OC1M_Pos (4) -#define TIM_CCMR1_OC1M (0x07U << TIM_CCMR1_OC1M_Pos) ///< OC1M[2:0] bits (Output Compare 1 Mode) -#define TIM_CCMR1_OC1M_TIMING (0x00U << TIM_CCMR1_OC1M_Pos) ///< Timing -#define TIM_CCMR1_OC1M_ACTIVE (0x01U << TIM_CCMR1_OC1M_Pos) ///< Active -#define TIM_CCMR1_OC1M_INACTIVE (0x02U << TIM_CCMR1_OC1M_Pos) ///< Inactive -#define TIM_CCMR1_OC1M_TOGGLE (0x03U << TIM_CCMR1_OC1M_Pos) ///< Toggle -#define TIM_CCMR1_OC1M_FORCEINACTIVE (0x04U << TIM_CCMR1_OC1M_Pos) ///< Forceinactive -#define TIM_CCMR1_OC1M_FORCEACTIVE (0x05U << TIM_CCMR1_OC1M_Pos) ///< Forceactive -#define TIM_CCMR1_OC1M_PWM1 (0x06U << TIM_CCMR1_OC1M_Pos) ///< PWM1 -#define TIM_CCMR1_OC1M_PWM2 (0x07U << TIM_CCMR1_OC1M_Pos) ///< PWM2 - -#define TIM_CCMR1_OC1CEN_Pos (7) -#define TIM_CCMR1_OC1CEN (0x01U << TIM_CCMR1_OC1CEN_Pos) ///< Output Compare 1Clear Enable -#define TIM_CCMR1_CC2S_Pos (8) -#define TIM_CCMR1_CC2S (0x03U << TIM_CCMR1_CC2S_Pos) ///< CC2S[1:0] bits (Capture/Compare 2 Selection) -#define TIM_CCMR1_CC2S_OC (0x00U << TIM_CCMR1_CC2S_Pos) ///< Channel is configured as output -#define TIM_CCMR1_CC2S_DIRECTTI (0x01U << TIM_CCMR1_CC2S_Pos) ///< Channel is configured as input, IC2 is mapped on TI2 -#define TIM_CCMR1_CC2S_INDIRECTTI (0x02U << TIM_CCMR1_CC2S_Pos) ///< Channel is configured as input, IC2 is mapped on TI1 -#define TIM_CCMR1_CC2S_TRC (0x03U << TIM_CCMR1_CC2S_Pos) ///< Channel is configured as input, IC2 is mapped on TRC -#define TIM_CCMR1_OC2FEN_Pos (10) -#define TIM_CCMR1_OC2FEN (0x01U << TIM_CCMR1_OC2FEN_Pos) ///< Output Compare 2 Fast enable -#define TIM_CCMR1_OC2PEN_Pos (11) -#define TIM_CCMR1_OC2PEN (0x01U << TIM_CCMR1_OC2PEN_Pos) ///< Output Compare 2 Preload enable -#define TIM_CCMR1_OC2M_Pos (12) -#define TIM_CCMR1_OC2M (0x07U << TIM_CCMR1_OC2M_Pos) ///< OC2M[2:0] bits (Output Compare 2 Mode) -#define TIM_CCMR1_OC2M_TIMING (0x00U << TIM_CCMR1_OC2M_Pos) ///< Timing -#define TIM_CCMR1_OC2M_ACTIVE (0x01U << TIM_CCMR1_OC2M_Pos) ///< Active -#define TIM_CCMR1_OC2M_INACTIVE (0x02U << TIM_CCMR1_OC2M_Pos) ///< Inactive -#define TIM_CCMR1_OC2M_TOGGLE (0x03U << TIM_CCMR1_OC2M_Pos) ///< Toggle -#define TIM_CCMR1_OC2M_FORCEINACTIVE (0x04U << TIM_CCMR1_OC2M_Pos) ///< Forceinactive -#define TIM_CCMR1_OC2M_FORCEACTIVE (0x05U << TIM_CCMR1_OC2M_Pos) ///< Forceactive -#define TIM_CCMR1_OC2M_PWM1 (0x06U << TIM_CCMR1_OC2M_Pos) ///< PWM1 -#define TIM_CCMR1_OC2M_PWM2 (0x07U << TIM_CCMR1_OC2M_Pos) ///< PWM2 -#define TIM_CCMR1_OC2CEN_Pos (15) -#define TIM_CCMR1_OC2CEN (0x01U << TIM_CCMR1_OC2CEN_Pos) ///< Output Compare 2 Clear Enable - -#define TIM_CCMR1_IC1PSC_Pos (2) -#define TIM_CCMR1_IC1PSC (0x03U << TIM_CCMR1_IC1PSC_Pos) ///< IC1PSC[1:0] bits (Input Capture 1 Prescaler) -#define TIM_CCMR1_IC1PSC_DIV1 (0x00U << TIM_CCMR1_IC1PSC_Pos) ///< No Prescaler -#define TIM_CCMR1_IC1PSC_DIV2 (0x01U << TIM_CCMR1_IC1PSC_Pos) ///< Capture is done once every 2 events -#define TIM_CCMR1_IC1PSC_DIV4 (0x02U << TIM_CCMR1_IC1PSC_Pos) ///< Capture is done once every 4 events -#define TIM_CCMR1_IC1PSC_DIV8 (0x03U << TIM_CCMR1_IC1PSC_Pos) ///< Capture is done once every 8 events -#define TIM_CCMR1_IC1F_Pos (4) -#define TIM_CCMR1_IC1F (0x0FU << TIM_CCMR1_IC1F_Pos) ///< IC1F[3:0] bits (Input Capture 1 Filter) -#define TIM_CCMR1_IC1F_0 (0x01U << TIM_CCMR1_IC1F_Pos) ///< Bit 0 -#define TIM_CCMR1_IC1F_1 (0x02U << TIM_CCMR1_IC1F_Pos) ///< Bit 1 -#define TIM_CCMR1_IC1F_2 (0x04U << TIM_CCMR1_IC1F_Pos) ///< Bit 2 -#define TIM_CCMR1_IC1F_3 (0x08U << TIM_CCMR1_IC1F_Pos) ///< Bit 3 - -#define TIM_CCMR1_IC2PSC_Pos (10) -#define TIM_CCMR1_IC2PSC (0x03U << TIM_CCMR1_IC2PSC_Pos) ///< IC2PSC[1:0] bits (Input Capture 2 Prescaler) -#define TIM_CCMR1_IC2PSC_DIV1 (0x00U << TIM_CCMR1_IC2PSC_Pos) ///< No Prescaler -#define TIM_CCMR1_IC2PSC_DIV2 (0x01U << TIM_CCMR1_IC2PSC_Pos) ///< Capture is done once every 2 events -#define TIM_CCMR1_IC2PSC_DIV4 (0x02U << TIM_CCMR1_IC2PSC_Pos) ///< Capture is done once every 4 events -#define TIM_CCMR1_IC2PSC_DIV8 (0x03U << TIM_CCMR1_IC2PSC_Pos) ///< Capture is done once every 8 events -#define TIM_CCMR1_IC2F_Pos (12) -#define TIM_CCMR1_IC2F (0x0FU << TIM_CCMR1_IC2F_Pos) ///< IC2F[3:0] bits (Input Capture 2 Filter) -#define TIM_CCMR1_IC2F_0 (0x01U << TIM_CCMR1_IC2F_Pos) ///< Bit 0 -#define TIM_CCMR1_IC2F_1 (0x02U << TIM_CCMR1_IC2F_Pos) ///< Bit 1 -#define TIM_CCMR1_IC2F_2 (0x04U << TIM_CCMR1_IC2F_Pos) ///< Bit 2 -#define TIM_CCMR1_IC2F_3 (0x08U << TIM_CCMR1_IC2F_Pos) ///< Bit 3 - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_CCMR2 Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define TIM_CCMR2_CC3S_Pos (0) -#define TIM_CCMR2_CC3S (0x03U << TIM_CCMR2_CC3S_Pos) ///< CC3S[1:0] bits (Capture/Compare 3 Selection) -#define TIM_CCMR2_CC3S_OC (0x00U << TIM_CCMR2_CC3S_Pos) ///< Channel is configured as output -#define TIM_CCMR2_CC3S_DIRECTTI (0x01U << TIM_CCMR2_CC3S_Pos) ///< Channel is configured as input, IC3 is mapped on TI3 -#define TIM_CCMR2_CC3S_INDIRECTTI (0x02U << TIM_CCMR2_CC3S_Pos) ///< Channel is configured as input, IC3 is mapped on TI4 -#define TIM_CCMR2_CC3S_TRC (0x03U << TIM_CCMR2_CC3S_Pos) ///< Channel is configured as input, IC3 is mapped on TRC -#define TIM_CCMR2_OC3FEN_Pos (2) -#define TIM_CCMR2_OC3FEN (0x01U << TIM_CCMR2_OC3FEN_Pos) ///< Output Compare 3 Fast enable -#define TIM_CCMR2_IC3PSC_Pos (2) -#define TIM_CCMR2_IC3PSC (0x03U << TIM_CCMR2_IC3PSC_Pos) ///< IC3PSC[1:0] bits (Input Capture 3 Prescaler) -#define TIM_CCMR2_IC3PSC_DIV1 (0x00U << TIM_CCMR2_IC3PSC_Pos) ///< No Prescaler -#define TIM_CCMR2_IC3PSC_DIV2 (0x01U << TIM_CCMR2_IC3PSC_Pos) ///< Capture is done once every 2 events -#define TIM_CCMR2_IC3PSC_DIV4 (0x02U << TIM_CCMR2_IC3PSC_Pos) ///< Capture is done once every 4 events -#define TIM_CCMR2_IC3PSC_DIV8 (0x03U << TIM_CCMR2_IC3PSC_Pos) ///< Capture is done once every 8 events -#define TIM_CCMR2_OC3PEN_Pos (3) -#define TIM_CCMR2_OC3PEN (0x01U << TIM_CCMR2_OC3PEN_Pos) ///< Output Compare 3 Preload enable -#define TIM_CCMR2_OC3M_Pos (4) -#define TIM_CCMR2_OC3M (0x07U << TIM_CCMR2_OC3M_Pos) ///< OC3M[2:0] bits (Output Compare 3 Mode) -#define TIM_CCMR2_OC3M_TIMING (0x00U << TIM_CCMR2_OC3M_Pos) ///< Timing -#define TIM_CCMR2_OC3M_ACTIVE (0x01U << TIM_CCMR2_OC3M_Pos) ///< Active -#define TIM_CCMR2_OC3M_INACTIVE (0x02U << TIM_CCMR2_OC3M_Pos) ///< Inactive -#define TIM_CCMR2_OC3M_TOGGLE (0x03U << TIM_CCMR2_OC3M_Pos) ///< Toggle -#define TIM_CCMR2_OC3M_FORCEINACTIVE (0x04U << TIM_CCMR2_OC3M_Pos) ///< Forceinactive -#define TIM_CCMR2_OC3M_FORCEACTIVE (0x05U << TIM_CCMR2_OC3M_Pos) ///< Forceactive -#define TIM_CCMR2_OC3M_PWM1 (0x06U << TIM_CCMR2_OC3M_Pos) ///< PWM1 -#define TIM_CCMR2_OC3M_PWM2 (0x07U << TIM_CCMR2_OC3M_Pos) ///< PWM2 -#define TIM_CCMR2_IC3F_Pos (4) -#define TIM_CCMR2_IC3F (0x0FU << TIM_CCMR2_IC3F_Pos) ///< IC3F[3:0] bits (Input Capture 3 Filter) -#define TIM_CCMR2_IC3F_0 (0x01U << TIM_CCMR2_IC3F_Pos) ///< Bit 0 -#define TIM_CCMR2_IC3F_1 (0x02U << TIM_CCMR2_IC3F_Pos) ///< Bit 1 -#define TIM_CCMR2_IC3F_2 (0x04U << TIM_CCMR2_IC3F_Pos) ///< Bit 2 -#define TIM_CCMR2_IC3F_3 (0x08U << TIM_CCMR2_IC3F_Pos) ///< Bit 3 -#define TIM_CCMR2_OC3CEN_Pos (7) -#define TIM_CCMR2_OC3CEN (0x01U << TIM_CCMR2_OC3CEN_Pos) ///< Output Compare 3 Clear Enable -#define TIM_CCMR2_CC4S_Pos (8) -#define TIM_CCMR2_CC4S (0x03U << TIM_CCMR2_CC4S_Pos) ///< CC4S[1:0] bits (Capture/Compare 4 Selection) -#define TIM_CCMR2_CC4S_OC (0x00U << TIM_CCMR2_CC4S_Pos) ///< Channel is configured as output -#define TIM_CCMR2_CC4S_DIRECTTI (0x01U << TIM_CCMR2_CC4S_Pos) ///< Channel is configured as input, IC4 is mapped on TI4 -#define TIM_CCMR2_CC4S_INDIRECTTI (0x02U << TIM_CCMR2_CC4S_Pos) ///< Channel is configured as input, IC4 is mapped on TI3 -#define TIM_CCMR2_CC4S_TRC (0x03U << TIM_CCMR2_CC4S_Pos) ///< Channel is configured as input, IC4 is mapped on TRC -#define TIM_CCMR2_OC4FEN_Pos (10) -#define TIM_CCMR2_OC4FEN (0x01U << TIM_CCMR2_OC4FEN_Pos) ///< Output Compare 4 Fast enable -#define TIM_CCMR2_OC4PEN_Pos (11) -#define TIM_CCMR2_OC4PEN (0x01U << TIM_CCMR2_OC4PEN_Pos) ///< Output Compare 4 Preload enable -#define TIM_CCMR2_OC4M_Pos (12) -#define TIM_CCMR2_OC4M (0x07U << TIM_CCMR2_OC4M_Pos) ///< OC4M[2:0] bits (Output Compare 4 Mode) -#define TIM_CCMR2_OC4M_TIMING (0x00U << TIM_CCMR2_OC4M_Pos) ///< Timing -#define TIM_CCMR2_OC4M_ACTIVE (0x01U << TIM_CCMR2_OC4M_Pos) ///< Active -#define TIM_CCMR2_OC4M_INACTIVE (0x02U << TIM_CCMR2_OC4M_Pos) ///< Inactive -#define TIM_CCMR2_OC4M_TOGGLE (0x03U << TIM_CCMR2_OC4M_Pos) ///< Toggle -#define TIM_CCMR2_OC4M_FORCEINACTIVE (0x04U << TIM_CCMR2_OC4M_Pos) ///< Forceinactive -#define TIM_CCMR2_OC4M_FORCEACTIVE (0x05U << TIM_CCMR2_OC4M_Pos) ///< Forceactive -#define TIM_CCMR2_OC4M_PWM1 (0x06U << TIM_CCMR2_OC4M_Pos) ///< PWM1 -#define TIM_CCMR2_OC4M_PWM2 (0x07U << TIM_CCMR2_OC4M_Pos) ///< PWM2 -#define TIM_CCMR2_OC4CEN_Pos (15) -#define TIM_CCMR2_OC4CEN (0x01U << TIM_CCMR2_OC4CEN_Pos) ///< Output Compare 4 Clear Enable -#define TIM_CCMR2_IC4PSC_Pos (10) -#define TIM_CCMR2_IC4PSC (0x03U << TIM_CCMR2_IC4PSC_Pos) ///< IC4PSC[1:0] bits (Input Capture 4 Prescaler) -#define TIM_CCMR2_IC4PSC_DIV1 (0x00U << TIM_CCMR2_IC4PSC_Pos) ///< No Prescaler -#define TIM_CCMR2_IC4PSC_DIV2 (0x01U << TIM_CCMR2_IC4PSC_Pos) ///< Capture is done once every 2 events -#define TIM_CCMR2_IC4PSC_DIV4 (0x02U << TIM_CCMR2_IC4PSC_Pos) ///< Capture is done once every 4 events -#define TIM_CCMR2_IC4PSC_DIV8 (0x03U << TIM_CCMR2_IC4PSC_Pos) ///< Capture is done once every 8 events -#define TIM_CCMR2_IC4F_Pos (12) -#define TIM_CCMR2_IC4F (0x0FU << TIM_CCMR2_IC4F_Pos) ///< IC4F[3:0] bits (Input Capture 4 Filter) -#define TIM_CCMR2_IC4F_0 (0x01U << TIM_CCMR2_IC4F_Pos) ///< Bit 0 -#define TIM_CCMR2_IC4F_1 (0x02U << TIM_CCMR2_IC4F_Pos) ///< Bit 1 -#define TIM_CCMR2_IC4F_2 (0x04U << TIM_CCMR2_IC4F_Pos) ///< Bit 2 -#define TIM_CCMR2_IC4F_3 (0x08U << TIM_CCMR2_IC4F_Pos) ///< Bit 3 - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_CCER Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define TIM_CCER_CC1EN_Pos (0) -#define TIM_CCER_CC1EN (0x01U << TIM_CCER_CC1EN_Pos) ///< Capture/Compare 1 output enable -#define TIM_CCER_CC1P_Pos (1) -#define TIM_CCER_CC1P (0x01U << TIM_CCER_CC1P_Pos) ///< Capture/Compare 1 output Polarity -#define TIM_CCER_CC1NEN_Pos (2) -#define TIM_CCER_CC1NEN (0x01U << TIM_CCER_CC1NEN_Pos) ///< Capture/Compare 1 Complementary output enable -#define TIM_CCER_CC1NP_Pos (3) -#define TIM_CCER_CC1NP (0x01U << TIM_CCER_CC1NP_Pos) ///< Capture/Compare 1 Complementary output Polarity -#define TIM_CCER_CC2EN_Pos (4) -#define TIM_CCER_CC2EN (0x01U << TIM_CCER_CC2EN_Pos) ///< Capture/Compare 2 output enable -#define TIM_CCER_CC2P_Pos (5) -#define TIM_CCER_CC2P (0x01U << TIM_CCER_CC2P_Pos) ///< Capture/Compare 2 output Polarity -#define TIM_CCER_CC2NEN_Pos (6) -#define TIM_CCER_CC2NEN (0x01U << TIM_CCER_CC2NEN_Pos) ///< Capture/Compare 2 Complementary output enable -#define TIM_CCER_CC2NP_Pos (7) -#define TIM_CCER_CC2NP (0x01U << TIM_CCER_CC2NP_Pos) ///< Capture/Compare 2 Complementary output Polarity -#define TIM_CCER_CC3EN_Pos (8) -#define TIM_CCER_CC3EN (0x01U << TIM_CCER_CC3EN_Pos) ///< Capture/Compare 3 output enable -#define TIM_CCER_CC3P_Pos (9) -#define TIM_CCER_CC3P (0x01U << TIM_CCER_CC3P_Pos) ///< Capture/Compare 3 output Polarity -#define TIM_CCER_CC3NEN_Pos (10) -#define TIM_CCER_CC3NEN (0x01U << TIM_CCER_CC3NEN_Pos) ///< Capture/Compare 3 Complementary output enable -#define TIM_CCER_CC3NP_Pos (11) -#define TIM_CCER_CC3NP (0x01U << TIM_CCER_CC3NP_Pos) ///< Capture/Compare 3 Complementary output Polarity -#define TIM_CCER_CC4EN_Pos (12) -#define TIM_CCER_CC4EN (0x01U << TIM_CCER_CC4EN_Pos) ///< Capture/Compare 4 output enable -#define TIM_CCER_CC4P_Pos (13) -#define TIM_CCER_CC4P (0x01U << TIM_CCER_CC4P_Pos) ///< Capture/Compare 4 output Polarity -#define TIM_CCER_CC4NP_Pos (15) -#define TIM_CCER_CC4NP (0x01U << TIM_CCER_CC4NP_Pos) ///< Capture/Compare 4 complementary output polarity - -#define TIM_CCER_CC5EN_Pos (16) -#define TIM_CCER_CC5EN (0x01U << TIM_CCER_CC5EN_Pos) ///< Capture/Compare 5 output enable -#define TIM_CCER_CC5P_Pos (17) -#define TIM_CCER_CC5P (0x01U << TIM_CCER_CC5P_Pos) ///< Capture/Compare 5 output Polarity - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_CNT Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define TIM_CNT_CNT (0xFFFFU) ///< Counter Value - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_PSC Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define TIM_PSC_PSC (0xFFFFU) ///< Prescaler Value - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_ARR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define TIM_ARR_ARR (0xFFFFU) ///< actual auto-reload Value - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_RCR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define TIM_RCR_REP (0xFFU) ///< Repetition Counter Value - -#define TIM_RCR_REP_CNT_Pos (8) -#define TIM_RCR_REP_CNT (0xFFU << TIM_RCR_REP_CNT_Pos) ///< Repetition counter value of real-time writing - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_CCR1 Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define TIM_CCR1_CCR1 (0xFFFFU) ///< Capture/Compare 1 Value - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_CCR2 Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define TIM_CCR2_CCR2 (0xFFFFU) ///< Capture/Compare 2 Value - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_CCR3 Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define TIM_CCR3_CCR3 (0xFFFFU) ///< Capture/Compare 3 Value - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_CCR4 Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define TIM_CCR4_CCR4 (0xFFFFU) ///< Capture/Compare 4 Value - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_BDTR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define TIM_BDTR_DTG_Pos (0) -#define TIM_BDTR_DTG (0xFFU << TIM_BDTR_DTG_Pos) ///< DTG[0:7] bits (Dead-Time Generator set-up) -#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) ///< Bit 0 -#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) ///< Bit 1 -#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) ///< Bit 2 -#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) ///< Bit 3 -#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) ///< Bit 4 -#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) ///< Bit 5 -#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) ///< Bit 6 -#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) ///< Bit 7 -#define TIM_BDTR_LOCK_Pos (8) -#define TIM_BDTR_LOCK (0x03U << TIM_BDTR_LOCK_Pos) ///< LOCK[1:0] bits (Lock Configuration) -#define TIM_BDTR_LOCK_OFF (0x00U << TIM_BDTR_LOCK_Pos) ///< Lock Off -#define TIM_BDTR_LOCK_1 (0x01U << TIM_BDTR_LOCK_Pos) ///< Lock Level 1 -#define TIM_BDTR_LOCK_2 (0x02U << TIM_BDTR_LOCK_Pos) ///< Lock Level 2 -#define TIM_BDTR_LOCK_3 (0x03U << TIM_BDTR_LOCK_Pos) ///< Lock Level 3 -#define TIM_BDTR_OSSI_Pos (10) -#define TIM_BDTR_OSSI (0x01U << TIM_BDTR_OSSI_Pos) ///< Off-State Selection for Idle mode -#define TIM_BDTR_OSSR_Pos (11) -#define TIM_BDTR_OSSR (0x01U << TIM_BDTR_OSSR_Pos) ///< Off-State Selection for Run mode -#define TIM_BDTR_BKEN_Pos (12) -#define TIM_BDTR_BKEN (0x01U << TIM_BDTR_BKEN_Pos) ///< Break enable -#define TIM_BDTR_BKP_Pos (13) -#define TIM_BDTR_BKP (0x01U << TIM_BDTR_BKP_Pos) ///< Break Polarity -#define TIM_BDTR_AOEN_Pos (14) -#define TIM_BDTR_AOEN (0x01U << TIM_BDTR_AOEN_Pos) ///< Automatic Output enable -#define TIM_BDTR_MOEN_Pos (15) -#define TIM_BDTR_MOEN (0x01U << TIM_BDTR_MOEN_Pos) ///< Main Output enable - -#define TIM_BDTR_DOEN_Pos (16) -#define TIM_BDTR_DOEN (0x01U << TIM_BDTR_DOEN_Pos) ///< Direct Output enable -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_DCR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define TIM_DCR_DBA_Pos (0) -#define TIM_DCR_DBA (0x1FU << TIM_DCR_DBA_Pos) ///< DBA[4:0] bits (DMA Base Address) -#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) ///< Bit 0 -#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) ///< Bit 1 -#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) ///< Bit 2 -#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) ///< Bit 3 -#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) ///< Bit 4 -#define TIM_DCR_DBL_Pos (8) -#define TIM_DCR_DBL (0x1FU << TIM_DCR_DBL_Pos) ///< DBL[4:0] bits (DMA Burst Length) -#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) ///< Bit 0 -#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) ///< Bit 1 -#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) ///< Bit 2 -#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) ///< Bit 3 -#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) ///< Bit 4 - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_DMAR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define TIM_DMAR_DMAB (0xFFFFU) ///< DMA register for burst accesses - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_CCMR3 Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define TIM_CCMR3_OC5FEN_Pos (2) -#define TIM_CCMR3_OC5FEN (0x01U << TIM_CCMR3_OC5FEN_Pos) ///< Output Compare 5 Fast enable -#define TIM_CCMR3_OC5PEN_Pos (3) -#define TIM_CCMR3_OC5PEN (0x01U << TIM_CCMR3_OC5PEN_Pos) ///< Output Compare 5 Preload enable -#define TIM_CCMR3_OC5M_Pos (4) -#define TIM_CCMR3_OC5M (0x07U << TIM_CCMR3_OC5M_Pos) ///< OC5M[2:0] bits (Output Compare 5 Mode) - -#define TIM_CCMR3_OC5CEN_Pos (7) -#define TIM_CCMR3_OC5CEN (0x01U << TIM_CCMR3_OC5CEN_Pos) ///< Output Compare 5 Clear Enable -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_CCR5 Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define TIM_CCR5_CCR5 (0xFFFF) ///< Capture/Compare 5 Value - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_PDER Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define TIM_PDER_CCDREPE_Pos (0) -#define TIM_PDER_CCDREPE (0x01U << TIM_PDER_CCDREPE_Pos) ///< DMA request flow enable -#define TIM_PDER_CCR1SHIFTEN_Pos (1) -#define TIM_PDER_CCR1SHIFTEN (0x01U << TIM_PDER_CCR1SHIFTEN_Pos) ///< CCR1 pwm shift enable -#define TIM_PDER_CCR2SHIFTEN_Pos (2) -#define TIM_PDER_CCR2SHIFTEN (0x01U << TIM_PDER_CCR2SHIFTEN_Pos) ///< CCR2 pwm shift enable -#define TIM_PDER_CCR3SHIFTEN_Pos (3) -#define TIM_PDER_CCR3SHIFTEN (0x01U << TIM_PDER_CCR3SHIFTEN_Pos) ///< CCR3 pwm shift enable -#define TIM_PDER_CCR4SHIFTEN_Pos (4) -#define TIM_PDER_CCR4SHIFTEN (0x01U << TIM_PDER_CCR4SHIFTEN_Pos) ///< CCR4 pwm shift enable -#define TIM_PDER_CCR5SHIFTEN_Pos (5) -#define TIM_PDER_CCR5SHIFTEN (0x01U << TIM_PDER_CCR5SHIFTEN_Pos) ///< CCR5 pwm shift enable - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_CCR1FALL Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define TIM_CCR1FALL_CCR1FALL (0xFFFFU) ///< Capture/compare value for ch1 when counting down in PWM center-aligned mode - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_CCR2FALL Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define TIM_CCR2FALL_CCR2FALL (0xFFFFU) ///< Capture/compare value for ch2 when counting down in PWM center-aligned mode - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_CCR3FALL Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define TIM_CCR3FALL_CCR3FALL (0xFFFFU) ///< Capture/compare value for ch3 when counting down in PWM center-aligned mode - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_CCR4FALL Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define TIM_CCR4FALL_CCR4FALL (0xFFFFU) ///< Capture/compare value for ch4 when counting down in PWM center-aligned mode - -//////////////////////////////////////////////////////////////////////////////// -/// @brief TIM_CCR5FALL Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define TIM_CCR5FALL_CCR5FALL (0xFFFFU) ///< Capture/compare value for ch5 when counting down in PWM center-aligned mode - - - -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -#endif -//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_uart.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_uart.h deleted file mode 100644 index 069ff2cf9..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_uart.h +++ /dev/null @@ -1,362 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file reg_uart.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF -/// MM32 FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion - -#ifndef __REG_UART_H -#define __REG_UART_H - -// Files includes - -#include -#include -#include "types.h" - - - - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - - - - - - - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief UART Base Address Definition -//////////////////////////////////////////////////////////////////////////////// -#define UART1_BASE (APB2PERIPH_BASE + 0x3800) ///< Base Address: 0x40013800 -#define UART2_BASE (APB1PERIPH_BASE + 0x4400) ///< Base Address: 0x40004400 -#define UART3_BASE (APB1PERIPH_BASE + 0x4800) ///< Base Address: 0x40004800 -#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) ///< Base Address: 0x40004C00 -#define UART5_BASE (APB1PERIPH_BASE + 0x5000) ///< Base Address: 0x40005000 -#define UART6_BASE (APB2PERIPH_BASE + 0x3C00) ///< Base Address: 0x40013C00 -#define UART7_BASE (APB1PERIPH_BASE + 0x7800) ///< Base Address: 0x40007800 -#define UART8_BASE (APB1PERIPH_BASE + 0x7C00) ///< Base Address: 0x40007C00 - - - - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief UART Register Structure Definition -//////////////////////////////////////////////////////////////////////////////// -typedef struct { - __IO u32 TDR; ///< Transmit Data Register, offset: 0x00 - __IO u32 RDR; ///< Receive Data Register, offset: 0x04 - __IO u32 CSR; ///< Current Status Register, offset: 0x08 - __IO u32 ISR; ///< Interrupt Status Register, offset: 0x0C - __IO u32 IER; ///< Interrupt Enable Register, offset: 0x10 - __IO u32 ICR; ///< Interrupt Clear Register, offset: 0x14 - __IO u32 GCR; ///< Global Control Register, offset: 0x18 - __IO u32 CCR; ///< Config Control Register, offset: 0x1C - __IO u32 BRR; ///< Baud Rate Register, offset: 0x20 - __IO u32 FRA; ///< Fraction Register, offset: 0x24 - - __IO u32 RXAR; ///< Receive Address Register, offset: 0x28 - __IO u32 RXMR; ///< Receive Address Mask Register, offset: 0x2C - __IO u32 SCR; ///< Smart Card Register, offset: 0x30 - - __IO u32 IDLR; ///< Data length register offset: 0x34 - __IO u32 ABRCR; ///< automatic Baud rate control delivery offset: 0x38 - __IO u32 IRDA; ///< Infrared function control register, offset: 0x3C -} UART_TypeDef; - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief UART type pointer Definition -//////////////////////////////////////////////////////////////////////////////// -#define UART1 ((UART_TypeDef*) UART1_BASE) -#define UART2 ((UART_TypeDef*) UART2_BASE) - -#define UART3 ((UART_TypeDef*) UART3_BASE) -#define UART4 ((UART_TypeDef*) UART4_BASE) -#define UART5 ((UART_TypeDef*) UART5_BASE) -#define UART6 ((UART_TypeDef*) UART6_BASE) -#define UART7 ((UART_TypeDef*) UART7_BASE) -#define UART8 ((UART_TypeDef*) UART8_BASE) - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief UART_TDR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define UART_TDR_DATA_Pos (0) -#define UART_TDR_DATA (0xFFU << UART_TDR_DATA_Pos) ///< Transmit data register - -//////////////////////////////////////////////////////////////////////////////// -/// @brief UART_RDR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define UART_RDR_DATA_Pos (0) -#define UART_RDR_DATA (0xFFU << UART_RDR_DATA_Pos) ///< Receive data register - -//////////////////////////////////////////////////////////////////////////////// -/// @brief UART_CSR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define UART_CSR_TXC_Pos (0) -#define UART_CSR_TXC (0x01U << UART_CSR_TXC_Pos) ///< Transmit complete flag bit -#define UART_CSR_RXAVL_Pos (1) -#define UART_CSR_RXAVL (0x01U << UART_CSR_RXAVL_Pos) ///< Receive valid data flag bit -#define UART_CSR_TXFULL_Pos (2) -#define UART_CSR_TXFULL (0x01U << UART_CSR_TXFULL_Pos) ///< Transmit buffer full flag bit -#define UART_CSR_TXEPT_Pos (3) -#define UART_CSR_TXEPT (0x01U << UART_CSR_TXEPT_Pos) ///< Transmit buffer empty flag bit - -//////////////////////////////////////////////////////////////////////////////// -/// @brief UART_ISR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define UART_ISR_TX_Pos (0) -#define UART_ISR_TX (0x01U << UART_ISR_TX_Pos) ///< Transmit buffer empty interrupt flag bit -#define UART_ISR_RX_Pos (1) -#define UART_ISR_RX (0x01U << UART_ISR_RX_Pos) ///< Receive valid data interrupt flag bit - -#define UART_ISR_TXC_Pos (2) -#define UART_ISR_TXC (0x01U << UART_ISR_TXC_Pos) ///< Transmit complete interrupt flag bit - -#define UART_ISR_RXOERR_Pos (3) -#define UART_ISR_RXOERR (0x01U << UART_ISR_RXOERR_Pos) ///< Receive overflow error interrupt flag bit -#define UART_ISR_RXPERR_Pos (4) -#define UART_ISR_RXPERR (0x01U << UART_ISR_RXPERR_Pos) ///< Parity error interrupt flag bit -#define UART_ISR_RXFERR_Pos (5) -#define UART_ISR_RXFERR (0x01U << UART_ISR_RXFERR_Pos) ///< Frame error interrupt flag bit -#define UART_ISR_RXBRK_Pos (6) -#define UART_ISR_RXBRK (0x01U << UART_ISR_RXBRK_Pos) ///< Receive frame break interrupt flag bit - -#define UART_ISR_TXBRK_Pos (7) -#define UART_ISR_TXBRK (0x01U << UART_ISR_TXBRK_Pos) ///< Transmit Break Frame Interrupt Flag Bit -#define UART_ISR_RXB8_Pos (8) -#define UART_ISR_RXB8 (0x01U << UART_ISR_RXB8_Pos) ///< Receive Bit 8 Interrupt Flag Bit - -#define UART_ISR_RXIDLE_Pos (9) -#define UART_ISR_RXIDLE (0x01U << UART_ISR_RXIDLE_Pos) ///< Receive Bit 8 Interrupt clear Bit -#define UART_ISR_ABREND_INTF_Pos (10) -#define UART_ISR_ABREND_INTF (0x01U << UART_ISR_ABREND_INTF_Pos) ///< Auto baud rate end interrupt flag bit -#define UART_ISR_ABRERR_INTF_Pos (11) -#define UART_ISR_ABRERR_INTF (0x01U << UART_ISR_ABRERR_INTF_Pos) ///< Auto baud rate error interrupt flag bit - -//////////////////////////////////////////////////////////////////////////////// -/// @brief UART_IER Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define UART_IER_TX_Pos (0) -#define UART_IER_TX (0x01U << UART_IER_TX_Pos) ///< Transmit buffer empty interrupt enable bit -#define UART_IER_RX_Pos (1) -#define UART_IER_RX (0x01U << UART_IER_RX_Pos) ///< Receive buffer interrupt enable bit - -#define UART_IER_TXC_Pos (2) -#define UART_IER_TXC (0x01U << UART_IER_TXC_Pos) ///< Transmit complete interrupt enable bit - -#define UART_IER_RXOERR_Pos (3) -#define UART_IER_RXOERR (0x01U << UART_IER_RXOERR_Pos) ///< Receive overflow error interrupt enable bit -#define UART_IER_RXPERR_Pos (4) -#define UART_IER_RXPERR (0x01U << UART_IER_RXPERR_Pos) ///< Parity error interrupt enable bit -#define UART_IER_RXFERR_Pos (5) -#define UART_IER_RXFERR (0x01U << UART_IER_RXFERR_Pos) ///< Frame error interrupt enable bit -#define UART_IER_RXBRK_Pos (6) -#define UART_IER_RXBRK (0x01U << UART_IER_RXBRK_Pos) ///< Receive frame break interrupt enable bit - -#define UART_IER_TXBRK_Pos (7) -#define UART_IER_TXBRK (0x01U << UART_IER_TXBRK_Pos) ///< Transmit Break Frame Interrupt Enable Bit -#define UART_IER_RXB8_Pos (8) -#define UART_IER_RXB8 (0x01U << UART_IER_RXB8_Pos) ///< Receive Bit 8 Interrupt Enable Bit - -#define UART_IER_RXIDLE_Pos (9) -#define UART_IER_RXIDLE (0x01U << UART_IER_RXIDLE_Pos) ///< Receive Bit 8 Interrupt clear Bit -#define UART_IER_ABREND_IEN_Pos (10) -#define UART_IER_ABREND_IEN (0x01U << UART_IER_ABREND_IEN_Pos) ///< Auto baud rate end enable bit -#define UART_IER_ABRERR_IEN_Pos (11) -#define UART_IER_ABRERR_IEN (0x01U << UART_IER_ABRERR_IEN_Pos) ///< Auto baud rate error enable bit - -//////////////////////////////////////////////////////////////////////////////// -/// @brief UART_ICR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// - -#define UART_ICR_TX_Pos (0) -#define UART_ICR_TX (0x01U << UART_ICR_TX_Pos) ///< Transmit buffer empty interrupt clear bit -#define UART_ICR_RX_Pos (1) -#define UART_ICR_RX (0x01U << UART_ICR_RX_Pos) ///< Receive interrupt clear bit - -#define UART_ICR_TXC_Pos (2) -#define UART_ICR_TXC (0x01U << UART_ICR_TXC_Pos) ///< Transmit complete interrupt clear bit - -#define UART_ICR_RXOERR_Pos (3) -#define UART_ICR_RXOERR (0x01U << UART_ICR_RXOERR_Pos) ///< Receive overflow error interrupt clear bit -#define UART_ICR_RXPERR_Pos (4) -#define UART_ICR_RXPERR (0x01U << UART_ICR_RXPERR_Pos) ///< Parity error interrupt clear bit - -#define UART_ICR_RXFERR_Pos (5) -#define UART_ICR_RXFERR (0x01U << UART_ICR_RXFERR_Pos) ///< Frame error interrupt clear bit -#define UART_ICR_RXBRK_Pos (6) -#define UART_ICR_RXBRK (0x01U << UART_ICR_RXBRK_Pos) ///< Receive frame break interrupt clear bit - -#define UART_ICR_TXBRK_Pos (7) -#define UART_ICR_TXBRK (0x01U << UART_ICR_TXBRK_Pos) ///< Transmit Break Frame Interrupt clear Bit -#define UART_ICR_RXB8_Pos (8) -#define UART_ICR_RXB8 (0x01U << UART_ICR_RXB8_Pos) ///< Receive Bit 8 Interrupt clear Bit - -#define UART_ICR_RXIDLE_Pos (9) -#define UART_ICR_RXIDLE (0x01U << UART_ICR_RXIDLE_Pos) ///< Receive Bit 8 Interrupt clear Bit -#define UART_ICR_ABRENDCLR_Pos (10) -#define UART_ICR_ABRENDCLR (0x01U << UART_ICR_ABRENDCLR_Pos) ///< Auto baud rate end clear bit -#define UART_ICR_ABRERRCLR_Pos (11) -#define UART_ICR_ABRERRCLR (0x01U << UART_ICR_ABRERRCLR_Pos) ///< Auto baud rate error clear bit - -//////////////////////////////////////////////////////////////////////////////// -/// @brief UART_GCR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define UART_GCR_UART_Pos (0) -#define UART_GCR_UART (0x01U << UART_GCR_UART_Pos) ///< UART mode selection bit -#define UART_GCR_DMA_Pos (1) -#define UART_GCR_DMA (0x01U << UART_GCR_DMA_Pos) ///< DMA mode selection bit -#define UART_GCR_AUTOFLOW_Pos (2) -#define UART_GCR_AUTOFLOW (0x01U << UART_GCR_AUTOFLOW_Pos) ///< Automatic flow control enable bit -#define UART_GCR_RX_Pos (3) -#define UART_GCR_RX (0x01U << UART_GCR_RX_Pos) ///< Enable receive -#define UART_GCR_TX_Pos (4) -#define UART_GCR_TX (0x01U << UART_GCR_TX_Pos) ///< Enable transmit - -#define UART_GCR_SELB8_Pos (7) -#define UART_GCR_SELB8 (0x01U << UART_GCR_SELB8_Pos) ///< UART mode selection bit -#define UART_GCR_SWAP_Pos (8) -#define UART_GCR_SWAP (0x01U << UART_GCR_SWAP_Pos) ///< DMA mode selection bit -#define UART_GCR_RXTOG_Pos (9) -#define UART_GCR_RXTOG (0x01U << UART_GCR_RXTOG_Pos) ///< Automatic flow control enable bit -#define UART_GCR_TXTOG_Pos (10) -#define UART_GCR_TXTOG (0x01U << UART_GCR_TXTOG_Pos) ///< Enable receive - -//////////////////////////////////////////////////////////////////////////////// -/// @brief UART_CCR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define UART_CCR_PEN_Pos (0) -#define UART_CCR_PEN (0x01U << UART_CCR_PEN_Pos) ///< Parity enable bit -#define UART_CCR_PSEL_Pos (1) -#define UART_CCR_PSEL (0x01U << UART_CCR_PSEL_Pos) ///< Parity selection bit - -#define UART_CCR_SPB_Pos (2) -#define UART_CCR_SPB (0x01U << UART_CCR_SPB_Pos) ///< Stop bit selection - - - -#define UART_CCR_SPB0_Pos UART_CCR_SPB_Pos -#define UART_CCR_SPB0 UART_CCR_SPB ///< Stop bit 0 selection - -#define UART_CCR_BRK_Pos (3) -#define UART_CCR_BRK (0x01U << UART_CCR_BRK_Pos) ///< UART transmit frame break -#define UART_CCR_CHAR_Pos (4) -#define UART_CCR_CHAR (0x03U << UART_CCR_CHAR_Pos) ///< UART width bit -#define UART_CCR_CHAR_5b (0x00U << UART_CCR_CHAR_Pos) ///< UART Word Length 5b -#define UART_CCR_CHAR_6b (0x01U << UART_CCR_CHAR_Pos) ///< UART Word Length 6b -#define UART_CCR_CHAR_7b (0x02U << UART_CCR_CHAR_Pos) ///< UART Word Length 7b -#define UART_CCR_CHAR_8b (0x03U << UART_CCR_CHAR_Pos) ///< UART Word Length 8b - -#define UART_CCR_SPB1_Pos (6) -#define UART_CCR_SPB1 (0x01U << UART_CCR_SPB1_Pos) ///< Stop bit 1 selection -#define UART_CCR_B8RXD_Pos (7) -#define UART_CCR_B8RXD (0x01U << UART_CCR_B8RXD_Pos) ///< Synchronous frame receive -#define UART_CCR_B8TXD_Pos (8) -#define UART_CCR_B8TXD (0x01U << UART_CCR_B8TXD_Pos) ///< Synchronous frame transmit -#define UART_CCR_B8POL_Pos (9) -#define UART_CCR_B8POL (0x01U << UART_CCR_B8POL_Pos) ///< Synchronous frame polarity control bit -#define UART_CCR_B8TOG_Pos (10) -#define UART_CCR_B8TOG (0x01U << UART_CCR_B8TOG_Pos) ///< Synchronous frame auto toggle bit -#define UART_CCR_B8EN_Pos (11) -#define UART_CCR_B8EN (0x01U << UART_CCR_B8EN_Pos) ///< Synchronous frame enable bit -#define UART_CCR_RWU_Pos (12) -#define UART_CCR_RWU (0x01U << UART_CCR_RWU_Pos) ///< Receive wake up method -#define UART_CCR_WAKE_Pos (13) -#define UART_CCR_WAKE (0x01U << UART_CCR_WAKE_Pos) ///< Wake up method - -#define UART_CCR_LIN_Pos (14) -#define UART_CCR_LIN (0x01U << UART_CCR_LIN_Pos) ///< Wake up method - -//////////////////////////////////////////////////////////////////////////////// -/// @brief UART_BRR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define UART_BRR_MANTISSA_Pos (0) -#define UART_BRR_MANTISSA (0xFFFFU << UART_BRR_MANTISSA_Pos) ///< UART DIV MANTISSA - -//////////////////////////////////////////////////////////////////////////////// -/// @brief UART_FRA Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define UART_BRR_FRACTION_Pos (0) -#define UART_BRR_FRACTION (0x0FU << UART_BRR_FRACTION_Pos) ///< UART DIV FRACTION - -//////////////////////////////////////////////////////////////////////////////// -/// @brief UART_RXAR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define UART_RXAR_ADDR_Pos (0) -#define UART_RXAR_ADDR (0xFFU << UART_RXAR_ADDR_Pos) ///< Synchronous frame match address - -//////////////////////////////////////////////////////////////////////////////// -/// @brief UART_RXMR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define UART_RXMR_MASK_Pos (0) -#define UART_RXMR_MASK (0xFFU << UART_RXMR_MASK_Pos) ///< Synchronous frame match address mask - -//////////////////////////////////////////////////////////////////////////////// -/// @brief UART_SCR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define UART_SCR_SCEN_Pos (0) -#define UART_SCR_SCEN (0x01U << UART_SCR_SCEN_Pos) ///< ISO7816 enable bit -#define UART_SCR_SCARB_Pos (1) -#define UART_SCR_SCARB (0x01U << UART_SCR_SCARB_Pos) ///< ISO7816 check auto answer bit -#define UART_SCR_NACK_Pos (2) -#define UART_SCR_NACK (0x01U << UART_SCR_NACK_Pos) ///< Master receive frame answer bit -#define UART_SCR_SCFCNT_Pos (4) -#define UART_SCR_SCFCNT (0xFFU << UART_SCR_SCFCNT_Pos) ///< ISO7816 protection counter bit -#define UART_SCR_HDSEL_Pos (12) -#define UART_SCR_HDSEL (0x01U << UART_SCR_HDSEL_Pos) ///< Single-line half-duplex mode selection bit -//////////////////////////////////////////////////////////////////////////////// -/// @brief UART_ABRCR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define UART_ABRCR_ABREN_Pos (0) -#define UART_ABRCR_ABREN (0x01U<
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-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion - -#ifndef __REG_USB_OTG_FS_H -#define __REG_USB_OTG_FS_H - -// Files includes - -#include -#include -#include "types.h" - - - - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - - - - - - - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief USB Base Address Definition -//////////////////////////////////////////////////////////////////////////////// - -#define USB_OTG_FS_BASE (AHB2PERIPH_BASE + 0x0000) ///< Base Address: 0x50000000 - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief USB Register Structure Definition -//////////////////////////////////////////////////////////////////////////////// - -typedef struct { - __IO u32 PER_ID; ///< Peripheral ID register offset: 0x00 - __IO u32 ID_COMP; ///< Peripheral ID complement register offset: 0x04 - __IO u32 REV; ///< Peripheral revision register offset: 0x08 - __IO u32 ADD_INFO; ///< Peripheral additional info register offset: 0x0C - __IO u32 OTG_ISTAT; ///< OTG Interrupt Status Register offset: 0x10 - __IO u32 OTG_ICTRL; ///< OTG Interrupt Control Register offset: 0x14 - __IO u32 OTG_STAT; ///< OTG Status Register offset: 0x18 - __IO u32 OTG_CTRL; ///< OTG Control register offset: 0x1C - __IO u32 RESERVED0[24]; ///< Reserved offset: 0x20 - __IO u32 INT_STAT; ///< Interrupt status register offset: 0x80 - __IO u32 INT_ENB; ///< Interrupt enable register offset: 0x84 - __IO u32 ERR_STAT; ///< Error interrupt status register offset: 0x88 - __IO u32 ERR_ENB; ///< Error interrupt enable register offset: 0x8C - __IO u32 STAT; ///< Status register offset: 0x90 - __IO u32 CTL; ///< Control register offset: 0x94 - __IO u32 ADDR; ///< Address register offset: 0x98 - __IO u32 BDT_PAGE_01; ///< BDT page register 1 offset: 0x9C - __IO u32 FRM_NUML; ///< Frame number register offset: 0xA0 - __IO u32 FRM_NUMH; ///< Frame number register offset: 0xA4 - __IO u32 TOKEN; ///< Token register offset: 0xA8 - __IO u32 SOF_THLD; ///< SOF threshold register offset: 0xAC - __IO u32 BDT_PAGE_02; ///< BDT page register 2 offset: 0xB0 - __IO u32 BDT_PAGE_03; ///< BDT page register 3 offset: 0xB4 - __IO u32 RESERVED1; ///< Reserved offset: 0xB8 - __IO u32 RESERVED2; ///< Reserved offset: 0xBC - __IO u32 EP_CTL[16]; ///< Endpoint control register offset: 0xC0 -} USB_OTG_FS_TypeDef; -//////////////////////////////////////////////////////////////////////////////// -/// @brief USBD type pointer Definition -//////////////////////////////////////////////////////////////////////////////// -#define USB_OTG_FS ((USB_OTG_FS_TypeDef*) USB_OTG_FS_BASE ) - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief OTG_FS_PER_ID Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define OTG_FS_PER_ID_ID_Pos (0) -#define OTG_FS_PER_ID_ID (0x3FU << OTG_FS_PER_ID_ID_Pos) - -//////////////////////////////////////////////////////////////////////////////// -/// @brief OTG_FS_ID_COMP Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define OTG_FS_ID_COMP_NID_Pos (0) -#define OTG_FS_ID_COMP_NID (0x3FU << OTG_FS_ID_COMP_NID_Pos) - -//////////////////////////////////////////////////////////////////////////////// -/// @brief OTG_FS_REV Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define OTG_FS_REV_REV_Pos (0) -#define OTG_FS_REV_REV (0xFFU << OTG_FS_REV_REV_Pos) - -//////////////////////////////////////////////////////////////////////////////// -/// @brief OTG_FS_ADD_INFO Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define OTG_FS_ADD_INFO_HOST_Pos (0) -#define OTG_FS_ADD_INFO_HOST (0x01U << OTG_FS_ADD_INFO_HOST_Pos) -#define OTG_FS_ADD_INFO_IRQ_NUM_Pos (3) -#define OTG_FS_ADD_INFO_IRQ_NUM (0x1FU << OTG_FS_ADD_INFO_IRQ_NUM_Pos) - -//////////////////////////////////////////////////////////////////////////////// -/// @brief OTG_FS_OTG_ISTAT Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define OTG_FS_OTG_ISTAT_A_VBUS_VLD_CHG_Pos (0) -#define OTG_FS_OTG_ISTAT_A_VBUS_VLD_CHG (0x01U << OTG_FS_OTG_ISTAT_A_VBUS_VLD_CHG_Pos) -#define OTG_FS_OTG_ISTAT_B_SESS_END_CHG_Pos (2) -#define OTG_FS_OTG_ISTAT_B_SESS_END_CHG (0x01U << OTG_FS_OTG_ISTAT_B_SESS_END_CHG_Pos) -#define OTG_FS_OTG_ISTAT_SESS_VLD_CHG_Pos (3) -#define OTG_FS_OTG_ISTAT_SESS_VLD_CHG (0x01U << OTG_FS_OTG_ISTAT_SESS_VLD_CHG_Pos) -#define OTG_FS_OTG_ISTAT_LINE_STATE_CHG_Pos (5) -#define OTG_FS_OTG_ISTAT_LINE_STATE_CHG (0x01U << OTG_FS_OTG_ISTAT_LINE_STATE_CHG_Pos) -#define OTG_FS_OTG_ISTAT_1_MSEC_Pos (6) -#define OTG_FS_OTG_ISTAT_1_MSEC (0x01U << OTG_FS_OTG_ISTAT_1_MSEC_Pos) -#define OTG_FS_OTG_ISTAT_ID_CHG_Pos (7) -#define OTG_FS_OTG_ISTAT_ID_CHG (0x01U << OTG_FS_OTG_ISTAT_ID_CHG_Pos) - -//////////////////////////////////////////////////////////////////////////////// -/// @brief OTG_FS_OTG_ICTRL Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define OTG_FS_OTG_ICTRL_A_VBUS_VLD_EN_Pos (0) -#define OTG_FS_OTG_ICTRL_A_VBUS_VLD_EN (0x01U << OTG_FS_OTG_ICTRL_A_VBUS_VLD_EN_Pos) -#define OTG_FS_OTG_ICTRL_B_SESS_END_EN_Pos (2) -#define OTG_FS_OTG_ICTRL_B_SESS_END_EN (0x01U << OTG_FS_OTG_ICTRL_B_SESS_END_EN_Pos) -#define OTG_FS_OTG_ICTRL_SESS_VLD_EN_Pos (3) -#define OTG_FS_OTG_ICTRL_SESS_VLD_EN (0x01U << OTG_FS_OTG_ICTRL_SESS_VLD_EN_Pos) -#define OTG_FS_OTG_ICTRL_LINE_STATE_EN_Pos (5) -#define OTG_FS_OTG_ICTRL_LINE_STATE_EN (0x01U << OTG_FS_OTG_ICTRL_LINE_STATE_EN_Pos) -#define OTG_FS_OTG_ICTRL_1_MSEC_EN_Pos (6) -#define OTG_FS_OTG_ICTRL_1_MSEC_EN (0x01U << OTG_FS_OTG_ICTRL_1_MSEC_EN_Pos) -#define OTG_FS_OTG_ICTRL_ID_EN_Pos (7) -#define OTG_FS_OTG_ICTRL_ID_EN (0x01U << OTG_FS_OTG_ICTRL_ID_EN_Pos) - -//////////////////////////////////////////////////////////////////////////////// -/// @brief OTG_FS_OTG_STAT Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define OTG_FS_OTG_STAT_A_VBUS_VLD_Pos (0) -#define OTG_FS_OTG_STAT_A_VBUS_VLD (0x01U << OTG_FS_OTG_STAT_A_VBUS_VLD_Pos) -#define OTG_FS_OTG_STAT_B_SESS_END_Pos (2) -#define OTG_FS_OTG_STAT_B_SESS_END (0x01U << OTG_FS_OTG_STAT_B_SESS_END_Pos) -#define OTG_FS_OTG_STAT_SESS_VLD_Pos (3) -#define OTG_FS_OTG_STAT_SESS_VLD (0x01U << OTG_FS_OTG_STAT_SESS_VLD_Pos) -#define OTG_FS_OTG_STAT_LINE_STATE_STABLE_Pos (5) -#define OTG_FS_OTG_STAT_LINE_STATE_STABLE (0x01U << OTG_FS_OTG_STAT_LINE_STATE_STABLE_Pos) -#define OTG_FS_OTG_STAT_1_MSEC_Pos (6) -#define OTG_FS_OTG_STAT_1_MSEC (0x01U << OTG_FS_OTG_STAT_1_MSEC_Pos) -#define OTG_FS_OTG_STAT_ID_Pos (7) -#define OTG_FS_OTG_STAT_ID (0x01U << OTG_FS_OTG_STAT_ID_Pos) - -//////////////////////////////////////////////////////////////////////////////// -/// @brief OTG_FS_OTG_CTRL Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define OTG_FS_OTG_CTRL_VBUS_DSCHG_Pos (0) -#define OTG_FS_OTG_CTRL_VBUS_DSCHG (0x01U << OTG_FS_OTG_CTRL_VBUS_DSCHG_Pos) -#define OTG_FS_OTG_CTRL_VBUS_CHG_Pos (1) -#define OTG_FS_OTG_CTRL_VBUS_CHG (0x01U << OTG_FS_OTG_CTRL_VBUS_CHG_Pos) -#define OTG_FS_OTG_CTRL_OTG_EN_Pos (2) -#define OTG_FS_OTG_CTRL_OTG_EN (0x01U << OTG_FS_OTG_CTRL_OTG_EN_Pos) -#define OTG_FS_OTG_CTRL_VBUS_ON_Pos (3) -#define OTG_FS_OTG_CTRL_VBUS_ON (0x01U << OTG_FS_OTG_CTRL_VBUS_ON_Pos) -#define OTG_FS_OTG_CTRL_DM_LOW_Pos (4) -#define OTG_FS_OTG_CTRL_DM_LOW (0x01U << OTG_FS_OTG_CTRL_DM_LOW_Pos) -#define OTG_FS_OTG_CTRL_DP_LOW_Pos (5) -#define OTG_FS_OTG_CTRL_DP_LOW (0x01U << OTG_FS_OTG_CTRL_DP_LOW_Pos) -#define OTG_FS_OTG_CTRL_DM_HIGH_Pos (6) -#define OTG_FS_OTG_CTRL_DM_HIGH (0x01U << OTG_FS_OTG_CTRL_DM_HIGH_Pos) -#define OTG_FS_OTG_CTRL_DP_HIGH_Pos (7) -#define OTG_FS_OTG_CTRL_DP_HIGH (0x01U << OTG_FS_OTG_CTRL_DP_HIGH_Pos) - -//////////////////////////////////////////////////////////////////////////////// -/// @brief OTG_FS_INT_STAT Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define OTG_FS_INT_STAT_USB_RST_Pos (0) -#define OTG_FS_INT_STAT_USB_RST (0x01U << OTG_FS_INT_STAT_USB_RST_Pos) -#define OTG_FS_INT_STAT_ERROR_Pos (1) -#define OTG_FS_INT_STAT_ERROR (0x01U << OTG_FS_INT_STAT_ERROR_Pos) -#define OTG_FS_INT_STAT_SOF_TOK_Pos (2) -#define OTG_FS_INT_STAT_SOF_TOK (0x01U << OTG_FS_INT_STAT_SOF_TOK_Pos) -#define OTG_FS_INT_STAT_TOK_DNE_Pos (3) -#define OTG_FS_INT_STAT_TOK_DNE (0x01U << OTG_FS_INT_STAT_TOK_DNE_Pos) -#define OTG_FS_INT_STAT_SLEEP_Pos (4) -#define OTG_FS_INT_STAT_SLEEP (0x01U << OTG_FS_INT_STAT_SLEEP_Pos) -#define OTG_FS_INT_STAT_RESUME_Pos (5) -#define OTG_FS_INT_STAT_RESUME (0x01U << OTG_FS_INT_STAT_RESUME_Pos) -#define OTG_FS_INT_STAT_ATTACH_Pos (6) -#define OTG_FS_INT_STAT_ATTACH (0x01U << OTG_FS_INT_STAT_ATTACH_Pos) -#define OTG_FS_INT_STAT_STALL_Pos (7) -#define OTG_FS_INT_STAT_STALL (0x01U << OTG_FS_INT_STAT_STALL_Pos) - -//////////////////////////////////////////////////////////////////////////////// -/// @brief OTG_FS_INT_ENB Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define OTG_FS_INT_ENB_USB_RST_EN_Pos (0) -#define OTG_FS_INT_ENB_USB_RST_EN (0x01U << OTG_FS_INT_ENB_USB_RST_EN_Pos) -#define OTG_FS_INT_ENB_ERROR_EN_Pos (1) -#define OTG_FS_INT_ENB_ERROR_EN (0x01U << OTG_FS_INT_ENB_ERROR_EN_Pos) -#define OTG_FS_INT_ENB_SOF_TOK_EN_Pos (2) -#define OTG_FS_INT_ENB_SOF_TOK_EN (0x01U << OTG_FS_INT_ENB_SOF_TOK_EN_Pos) -#define OTG_FS_INT_ENB_TOK_DNE_EN_Pos (3) -#define OTG_FS_INT_ENB_TOK_DNE_EN (0x01U << OTG_FS_INT_ENB_TOK_DNE_EN_Pos) -#define OTG_FS_INT_ENB_SLEEP_EN_Pos (4) -#define OTG_FS_INT_ENB_SLEEP_EN (0x01U << OTG_FS_INT_ENB_SLEEP_EN_Pos) -#define OTG_FS_INT_ENB_RESUME_EN_Pos (5) -#define OTG_FS_INT_ENB_RESUME_EN (0x01U << OTG_FS_INT_ENB_RESUME_EN_Pos) -#define OTG_FS_INT_ENB_ATTACH_EN_Pos (6) -#define OTG_FS_INT_ENB_ATTACH_EN (0x01U << OTG_FS_INT_ENB_ATTACH_EN_Pos) -#define OTG_FS_INT_ENB_STALL_EN_Pos (7) -#define OTG_FS_INT_ENB_STALL_EN (0x01U << OTG_FS_INT_ENB_STALL_EN_Pos) - -//////////////////////////////////////////////////////////////////////////////// -/// @brief OTG_FS_ERR_STAT Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define OTG_FS_ERR_STAT_PID_ERR_Pos (0) -#define OTG_FS_ERR_STAT_PID_ERR (0x01U << OTG_FS_ERR_STAT_PID_ERR_Pos) -#define OTG_FS_ERR_STAT_CRC5_EOF_Pos (1) -#define OTG_FS_ERR_STAT_CRC5_EOF (0x01U << OTG_FS_ERR_STAT_CRC5_EOF_Pos) -#define OTG_FS_ERR_STAT_CRC16_Pos (2) -#define OTG_FS_ERR_STAT_CRC16 (0x01U << OTG_FS_ERR_STAT_CRC16_Pos) -#define OTG_FS_ERR_STAT_DFN8_Pos (3) -#define OTG_FS_ERR_STAT_DFN8 (0x01U << OTG_FS_ERR_STAT_DFN8_Pos) -#define OTG_FS_ERR_STAT_BTO_ERR_Pos (4) -#define OTG_FS_ERR_STAT_BTO_ERR (0x01U << OTG_FS_ERR_STAT_BTO_ERR_Pos) -#define OTG_FS_ERR_STAT_DMA_ERR_Pos (5) -#define OTG_FS_ERR_STAT_DMA_ERR (0x01U << OTG_FS_ERR_STAT_DMA_ERR_Pos) -#define OTG_FS_ERR_STAT_BTS_ERR_Pos (7) -#define OTG_FS_ERR_STAT_BTS_ERR (0x01U << OTG_FS_ERR_STAT_BTS_ERR_Pos) - -//////////////////////////////////////////////////////////////////////////////// -/// @brief OTG_FS_ERR_ENB Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define OTG_FS_ERR_ENB_PID_ERR_EN_Pos (0) -#define OTG_FS_ERR_ENB_PID_ERR_EN (0x01U << OTG_FS_ERR_ENB_PID_ERR_EN_Pos) -#define OTG_FS_ERR_ENB_CRC5_EOF_EN_Pos (1) -#define OTG_FS_ERR_ENB_CRC5_EOF_EN (0x01U << OTG_FS_ERR_ENB_CRC5_EOF_EN_Pos) -#define OTG_FS_ERR_ENB_CRC16_EN_Pos (2) -#define OTG_FS_ERR_ENB_CRC16_EN (0x01U << OTG_FS_ERR_ENB_CRC16_EN_Pos) -#define OTG_FS_ERR_ENB_DFN8_EN_Pos (3) -#define OTG_FS_ERR_ENB_DFN8_EN (0x01U << OTG_FS_ERR_ENB_DFN8_EN_Pos) -#define OTG_FS_ERR_ENB_BTO_ERR_EN_Pos (4) -#define OTG_FS_ERR_ENB_BTO_ERR_EN (0x01U << OTG_FS_ERR_ENB_BTO_ERR_EN_Pos) -#define OTG_FS_ERR_ENB_DMA_ERR_EN_Pos (5) -#define OTG_FS_ERR_ENB_DMA_ERR_EN (0x01U << OTG_FS_ERR_ENB_DMA_ERR_EN_Pos) -#define OTG_FS_ERR_ENB_BTS_ERR_EN_Pos (7) -#define OTG_FS_ERR_ENB_BTS_ERR_EN (0x01U << OTG_FS_ERR_ENB_BTS_ERR_EN_Pos) - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief OTG_FS_STAT Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define OTG_FS_STAT_ODD_Pos (2) -#define OTG_FS_STAT_ODD (0x01U << OTG_FS_STAT_ODD_Pos) -#define OTG_FS_STAT_TX_Pos (3) -#define OTG_FS_STAT_TX (0x01U << OTG_FS_STAT_TX_Pos) -#define OTG_FS_STAT_ENDP_Pos (4) -#define OTG_FS_STAT_ENDP (0x0FU << OTG_FS_STAT_ENDP_Pos) - -//////////////////////////////////////////////////////////////////////////////// -/// @brief OTG_FS_CTL Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define OTG_FS_CTL_USB_EN_SOF_EN_Pos (0) -#define OTG_FS_CTL_USB_EN_SOF_EN (0x01U << OTG_FS_CTL_USB_EN_SOF_EN_Pos) -#define OTG_FS_CTL_ODD_RST_Pos (1) -#define OTG_FS_CTL_ODD_RST (0x01U << OTG_FS_CTL_ODD_RST_Pos) -#define OTG_FS_CTL_RESUME_Pos (2) -#define OTG_FS_CTL_RESUME (0x01U << OTG_FS_CTL_RESUME_Pos) -#define OTG_FS_CTL_HOST_MODE_EN_Pos (3) -#define OTG_FS_CTL_HOST_MODE_EN (0x01U << OTG_FS_CTL_HOST_MODE_EN_Pos) -#define OTG_FS_CTL_RESET_Pos (4) -#define OTG_FS_CTL_RESET (0x01U << OTG_FS_CTL_RESET_Pos) -#define OTG_FS_CTL_TXDSUSPEND_TOKENBUSY_Pos (5) -#define OTG_FS_CTL_TXDSUSPEND_TOKENBUSY (0x01U << OTG_FS_CTL_TXDSUSPEND_TOKENBUSY_Pos) -#define OTG_FS_CTL_SE0_Pos (6) -#define OTG_FS_CTL_SE0 (0x01U << OTG_FS_CTL_SE0_Pos) -#define OTG_FS_CTL_JSTATE_Pos (7) -#define OTG_FS_CTL_JSTATE (0x01U << OTG_FS_CTL_JSTATE_Pos) - -//////////////////////////////////////////////////////////////////////////////// -/// @brief OTG_FS_ADDR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define OTG_FS_ADDR_ADDR_Pos (0) -#define OTG_FS_ADDR_ADDR (0x7FU << OTG_FS_ADDR_ADDR_Pos) -#define OTG_FS_ADDR_LS_EN_Pos (7) -#define OTG_FS_ADDR_LS_EN (0x01U << OTG_FS_ADDR_LS_EN_Pos) - -//////////////////////////////////////////////////////////////////////////////// -/// @brief OTG_FS_BDT_PAGE_01 Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define OTG_FS_BDT_PAGE_01_BDT_BA_15_9_Pos (1) -#define OTG_FS_BDT_PAGE_01_BDT_BA_15_9 (0x7FU << OTG_FS_BDT_PAGE_01_BDT_BA_15_9_Pos) - -//////////////////////////////////////////////////////////////////////////////// -/// @brief OTG_FS_FRM_NUML Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define OTG_FS_FRM_NUML_FRM_Pos (0) -#define OTG_FS_FRM_NUML_FRM (0xFFU << OTG_FS_FRM_NUML_FRM_Pos) - -//////////////////////////////////////////////////////////////////////////////// -/// @brief OTG_FS_FRM_NUMH Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define OTG_FS_FRM_NUMH_FRM_Pos (0) -#define OTG_FS_FRM_NUMH_FRM (0x07U << OTG_FS_FRM_NUMH_FRM_Pos) - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief OTG_FS_TOKEN Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define OTG_FS_TOKEN_TOKEN_ENDPT_Pos (0) -#define OTG_FS_TOKEN_TOKEN_ENDPT (0x0FU << OTG_FS_TOKEN_TOKEN_ENDPT_Pos) -#define OTG_FS_TOKEN_TOKEN_PID_Pos (4) -#define OTG_FS_TOKEN_TOKEN_PID (0x0FU << OTG_FS_TOKEN_TOKEN_PID_Pos) - -//////////////////////////////////////////////////////////////////////////////// -/// @brief OTG_FS_SOF_THLD Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define OTG_FS_SOF_THLD_CNT_Pos (0) -#define OTG_FS_SOF_THLD_CNT (0xFFU << OTG_FS_SOF_THLD_CNT_Pos) - -//////////////////////////////////////////////////////////////////////////////// -/// @brief OTG_FS_BDT_PAGE_02 Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define OTG_FS_BDT_PAGE_02_BDT_BA_23_16_Pos (0) -#define OTG_FS_BDT_PAGE_02_BDT_BA_23_16 (0xFFU << OTG_FS_BDT_PAGE_02_BDT_BA_23_16_Pos) - -//////////////////////////////////////////////////////////////////////////////// -/// @brief OTG_FS_BDT_PAGE_03 Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define OTG_FS_BDT_PAGE_03_BDT_BA_31_24_Pos (0) -#define OTG_FS_BDT_PAGE_03_BDT_BA_31_24 (0xFFU << OTG_FS_BDT_PAGE_03_BDT_BA_31_24_Pos) - -//////////////////////////////////////////////////////////////////////////////// -/// @brief OTG_FS_EP_CTL Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define OTG_FS_EP_CTL_EP_HSHK_Pos (0) -#define OTG_FS_EP_CTL_EP_HSHK (0x01U << OTG_FS_EP_CTL_EP_HSHK_Pos) -#define OTG_FS_EP_CTL_EP_STALL_Pos (1) -#define OTG_FS_EP_CTL_EP_STALL (0x01U << OTG_FS_EP_CTL_EP_STALL_Pos) -#define OTG_FS_EP_CTL_EP_TX_EN_Pos (2) -#define OTG_FS_EP_CTL_EP_TX_EN (0x01U << OTG_FS_EP_CTL_EP_TX_EN_Pos) -#define OTG_FS_EP_CTL_EP_RX_EN_Pos (3) -#define OTG_FS_EP_CTL_EP_RX_EN (0x01U << OTG_FS_EP_CTL_EP_RX_EN_Pos) -#define OTG_FS_EP_CTL_EP_CTL_DIS_Pos (4) -#define OTG_FS_EP_CTL_EP_CTL_DIS (0x01U << OTG_FS_EP_CTL_EP_CTL_DIS_Pos) -#define OTG_FS_EP_CTL_RETRY_DIS_Pos (6) -#define OTG_FS_EP_CTL_RETRY_DIS (0x01U << OTG_FS_EP_CTL_RETRY_DIS_Pos) -#define OTG_FS_EP_CTL_HOST_WO_HUB_Pos (7) -#define OTG_FS_EP_CTL_HOST_WO_HUB (0x01U << OTG_FS_EP_CTL_HOST_WO_HUB_Pos) - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief OTG_FS Buffer Descriptor Bit Definition -//////////////////////////////////////////////////////////////////////////////// - -#define OTG_FS_BD_TOK_PID_Pos (2) -#define OTG_FS_BD_TOK_PID (0x0FU << OTG_FS_BD_TOK_PID_Pos) -#define OTG_FS_BD_DATA01_Pos (6) -#define OTG_FS_BD_DATA01 (0x01U << OTG_FS_BD_DATA01_Pos) -#define OTG_FS_BD_OWN_Pos (7) -#define OTG_FS_BD_OWN (0x01U << OTG_FS_BD_OWN_Pos) -#define OTG_FS_BD_BC_Pos (16) -#define OTG_FS_BD_BC (0x3FFU << OTG_FS_BD_BC_Pos) -#define OTG_FS_BD_ADDRESS_Pos (0) -#define OTG_FS_BD_ADDRESS (0xFFFFFFFFU << OTG_FS_BD_ADDRESS_Pos) - - - -/** -* @} -*/ -//#define OTG_FS_INT_STAT_RST ((uint32_t)0x01) -//#define OTG_FS_INT_STAT_ERROR ((uint32_t)0x02) -//#define OTG_FS_INT_STAT_SOF ((uint32_t)0x04) -//#define OTG_FS_INT_STAT_DNE ((uint32_t)0x08) -//#define OTG_FS_INT_STAT_SLEEP ((uint32_t)0x10) -//#define OTG_FS_INT_STAT_RESUME ((uint32_t)0x20) -//#define OTG_FS_INT_STAT_ATTACH ((uint32_t)0x40) -//#define OTG_FS_INT_STAT_STALL ((uint32_t)0x80) - -//TEMP -#define USB_INT_STAT_RST 0x01 -#define USB_INT_STAT_ERROR 0x02 -#define USB_INT_STAT_SOF_TOK 0x04 -#define USB_INT_STAT_TOK_DNE 0x08 -#define USB_INT_STAT_SLEEP 0x10 -#define USB_INT_STAT_RESUME 0x20 -#define USB_INT_STAT_ATTACH 0x40 -#define USB_INT_STAT_STALL 0x80 - - - - - - - - - - - - - - - - - - - -/*! @name PERID - Peripheral ID register */ -#define USB_PERID_ID_MASK (0x3FU) -#define USB_PERID_ID_SHIFT (0U) -#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK) - -/*! @name IDCOMP - Peripheral ID Complement register */ -#define USB_IDCOMP_NID_MASK (0x3FU) -#define USB_IDCOMP_NID_SHIFT (0U) -#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK) - -/*! @name REV - Peripheral Revision register */ -#define USB_REV_REV_MASK (0xFFU) -#define USB_REV_REV_SHIFT (0U) -#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK) - -/*! @name ADDINFO - Peripheral Additional Info register */ -#define USB_ADDINFO_IEHOST_MASK (0x1U) -#define USB_ADDINFO_IEHOST_SHIFT (0U) -#define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK) - -/*! @name OTGISTAT - OTG Interrupt Status register */ -#define USB_OTGISTAT_LINE_STATE_CHG_MASK (0x20U) -#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT (5U) -#define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK) -#define USB_OTGISTAT_ONEMSEC_MASK (0x40U) -#define USB_OTGISTAT_ONEMSEC_SHIFT (6U) -#define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK) - -/*! @name OTGICR - OTG Interrupt Control register */ -#define USB_OTGICR_LINESTATEEN_MASK (0x20U) -#define USB_OTGICR_LINESTATEEN_SHIFT (5U) -#define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK) -#define USB_OTGICR_ONEMSECEN_MASK (0x40U) -#define USB_OTGICR_ONEMSECEN_SHIFT (6U) -#define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK) - -/*! @name OTGSTAT - OTG Status register */ -#define USB_OTGSTAT_LINESTATESTABLE_MASK (0x20U) -#define USB_OTGSTAT_LINESTATESTABLE_SHIFT (5U) -#define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK) -#define USB_OTGSTAT_ONEMSECEN_MASK (0x40U) -#define USB_OTGSTAT_ONEMSECEN_SHIFT (6U) -#define USB_OTGSTAT_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSECEN_SHIFT)) & USB_OTGSTAT_ONEMSECEN_MASK) - -/*! @name OTGCTL - OTG Control register */ -#define USB_OTGCTL_OTGEN_MASK (0x4U) -#define USB_OTGCTL_OTGEN_SHIFT (2U) -#define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK) -#define USB_OTGCTL_DMLOW_MASK (0x10U) -#define USB_OTGCTL_DMLOW_SHIFT (4U) -#define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK) -#define USB_OTGCTL_DPLOW_MASK (0x20U) -#define USB_OTGCTL_DPLOW_SHIFT (5U) -#define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK) -#define USB_OTGCTL_DPHIGH_MASK (0x80U) -#define USB_OTGCTL_DPHIGH_SHIFT (7U) -#define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK) - -/*! @name ISTAT - Interrupt Status register */ -#define USB_ISTAT_USBRST_MASK (0x1U) -#define USB_ISTAT_USBRST_SHIFT (0U) -#define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK) -#define USB_ISTAT_ERROR_MASK (0x2U) -#define USB_ISTAT_ERROR_SHIFT (1U) -#define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK) -#define USB_ISTAT_SOFTOK_MASK (0x4U) -#define USB_ISTAT_SOFTOK_SHIFT (2U) -#define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK) -#define USB_ISTAT_TOKDNE_MASK (0x8U) -#define USB_ISTAT_TOKDNE_SHIFT (3U) -#define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK) -#define USB_ISTAT_SLEEP_MASK (0x10U) -#define USB_ISTAT_SLEEP_SHIFT (4U) -#define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK) -#define USB_ISTAT_RESUME_MASK (0x20U) -#define USB_ISTAT_RESUME_SHIFT (5U) -#define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK) -#define USB_ISTAT_ATTACH_MASK (0x40U) -#define USB_ISTAT_ATTACH_SHIFT (6U) -#define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK) -#define USB_ISTAT_STALL_MASK (0x80U) -#define USB_ISTAT_STALL_SHIFT (7U) -#define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK) - -/*! @name INTEN - Interrupt Enable register */ -#define USB_INTEN_USBRSTEN_MASK (0x1U) -#define USB_INTEN_USBRSTEN_SHIFT (0U) -#define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK) -#define USB_INTEN_ERROREN_MASK (0x2U) -#define USB_INTEN_ERROREN_SHIFT (1U) -#define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK) -#define USB_INTEN_SOFTOKEN_MASK (0x4U) -#define USB_INTEN_SOFTOKEN_SHIFT (2U) -#define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK) -#define USB_INTEN_TOKDNEEN_MASK (0x8U) -#define USB_INTEN_TOKDNEEN_SHIFT (3U) -#define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK) -#define USB_INTEN_SLEEPEN_MASK (0x10U) -#define USB_INTEN_SLEEPEN_SHIFT (4U) -#define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK) -#define USB_INTEN_RESUMEEN_MASK (0x20U) -#define USB_INTEN_RESUMEEN_SHIFT (5U) -#define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK) -#define USB_INTEN_ATTACHEN_MASK (0x40U) -#define USB_INTEN_ATTACHEN_SHIFT (6U) -#define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK) -#define USB_INTEN_STALLEN_MASK (0x80U) -#define USB_INTEN_STALLEN_SHIFT (7U) -#define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK) - -/*! @name ERRSTAT - Error Interrupt Status register */ -#define USB_ERRSTAT_PIDERR_MASK (0x1U) -#define USB_ERRSTAT_PIDERR_SHIFT (0U) -#define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK) -#define USB_ERRSTAT_CRC5EOF_MASK (0x2U) -#define USB_ERRSTAT_CRC5EOF_SHIFT (1U) -#define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK) -#define USB_ERRSTAT_CRC16_MASK (0x4U) -#define USB_ERRSTAT_CRC16_SHIFT (2U) -#define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK) -#define USB_ERRSTAT_DFN8_MASK (0x8U) -#define USB_ERRSTAT_DFN8_SHIFT (3U) -#define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK) -#define USB_ERRSTAT_BTOERR_MASK (0x10U) -#define USB_ERRSTAT_BTOERR_SHIFT (4U) -#define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK) -#define USB_ERRSTAT_DMAERR_MASK (0x20U) -#define USB_ERRSTAT_DMAERR_SHIFT (5U) -#define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK) -#define USB_ERRSTAT_OWNERR_MASK (0x40U) -#define USB_ERRSTAT_OWNERR_SHIFT (6U) -#define USB_ERRSTAT_OWNERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_OWNERR_SHIFT)) & USB_ERRSTAT_OWNERR_MASK) -#define USB_ERRSTAT_BTSERR_MASK (0x80U) -#define USB_ERRSTAT_BTSERR_SHIFT (7U) -#define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK) - -/*! @name ERREN - Error Interrupt Enable register */ -#define USB_ERREN_PIDERREN_MASK (0x1U) -#define USB_ERREN_PIDERREN_SHIFT (0U) -#define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK) -#define USB_ERREN_CRC5EOFEN_MASK (0x2U) -#define USB_ERREN_CRC5EOFEN_SHIFT (1U) -#define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK) -#define USB_ERREN_CRC16EN_MASK (0x4U) -#define USB_ERREN_CRC16EN_SHIFT (2U) -#define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK) -#define USB_ERREN_DFN8EN_MASK (0x8U) -#define USB_ERREN_DFN8EN_SHIFT (3U) -#define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK) -#define USB_ERREN_BTOERREN_MASK (0x10U) -#define USB_ERREN_BTOERREN_SHIFT (4U) -#define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK) -#define USB_ERREN_DMAERREN_MASK (0x20U) -#define USB_ERREN_DMAERREN_SHIFT (5U) -#define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK) -#define USB_ERREN_OWNERREN_MASK (0x40U) -#define USB_ERREN_OWNERREN_SHIFT (6U) -#define USB_ERREN_OWNERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_OWNERREN_SHIFT)) & USB_ERREN_OWNERREN_MASK) -#define USB_ERREN_BTSERREN_MASK (0x80U) -#define USB_ERREN_BTSERREN_SHIFT (7U) -#define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK) - -/*! @name STAT - Status register */ -#define USB_STAT_ODD_MASK (0x4U) -#define USB_STAT_ODD_SHIFT (2U) -#define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK) -#define USB_STAT_TX_MASK (0x8U) -#define USB_STAT_TX_SHIFT (3U) -#define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK) -#define USB_STAT_ENDP_MASK (0xF0U) -#define USB_STAT_ENDP_SHIFT (4U) -#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK) - -/*! @name CTL - Control register */ -#define USB_CTL_USBENSOFEN_MASK (0x1U) -#define USB_CTL_USBENSOFEN_SHIFT (0U) -#define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK) -#define USB_CTL_ODDRST_MASK (0x2U) -#define USB_CTL_ODDRST_SHIFT (1U) -#define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK) -#define USB_CTL_RESUME_MASK (0x4U) -#define USB_CTL_RESUME_SHIFT (2U) -#define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK) -#define USB_CTL_HOSTMODEEN_MASK (0x8U) -#define USB_CTL_HOSTMODEEN_SHIFT (3U) -#define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK) -#define USB_CTL_RESET_MASK (0x10U) -#define USB_CTL_RESET_SHIFT (4U) -#define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK) -#define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U) -#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U) -#define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK) -#define USB_CTL_SE0_MASK (0x40U) -#define USB_CTL_SE0_SHIFT (6U) -#define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK) -#define USB_CTL_JSTATE_MASK (0x80U) -#define USB_CTL_JSTATE_SHIFT (7U) -#define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK) - -/*! @name ADDR - Address register */ -#define USB_ADDR_ADDR_MASK (0x7FU) -#define USB_ADDR_ADDR_SHIFT (0U) -#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK) -#define USB_ADDR_LSEN_MASK (0x80U) -#define USB_ADDR_LSEN_SHIFT (7U) -#define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK) - -/*! @name BDTPAGE1 - BDT Page register 1 */ -#define USB_BDTPAGE1_BDTBA_MASK (0xFEU) -#define USB_BDTPAGE1_BDTBA_SHIFT (1U) -#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK) - -/*! @name FRMNUML - Frame Number register Low */ -#define USB_FRMNUML_FRM_MASK (0xFFU) -#define USB_FRMNUML_FRM_SHIFT (0U) -#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK) - -/*! @name FRMNUMH - Frame Number register High */ -#define USB_FRMNUMH_FRM_MASK (0x7U) -#define USB_FRMNUMH_FRM_SHIFT (0U) -#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK) - -/*! @name TOKEN - Token register */ -#define USB_TOKEN_TOKENENDPT_MASK (0xFU) -#define USB_TOKEN_TOKENENDPT_SHIFT (0U) -#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK) -#define USB_TOKEN_TOKENPID_MASK (0xF0U) -#define USB_TOKEN_TOKENPID_SHIFT (4U) -#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK) - -/*! @name SOFTHLD - SOF Threshold register */ -#define USB_SOFTHLD_CNT_MASK (0xFFU) -#define USB_SOFTHLD_CNT_SHIFT (0U) -#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK) - -/*! @name BDTPAGE2 - BDT Page Register 2 */ -#define USB_BDTPAGE2_BDTBA_MASK (0xFFU) -#define USB_BDTPAGE2_BDTBA_SHIFT (0U) -#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK) - -/*! @name BDTPAGE3 - BDT Page Register 3 */ -#define USB_BDTPAGE3_BDTBA_MASK (0xFFU) -#define USB_BDTPAGE3_BDTBA_SHIFT (0U) -#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK) - -/*! @name ENDPT - Endpoint Control register */ -#define USB_ENDPT_EPHSHK_MASK (0x1U) -#define USB_ENDPT_EPHSHK_SHIFT (0U) -#define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK) -#define USB_ENDPT_EPSTALL_MASK (0x2U) -#define USB_ENDPT_EPSTALL_SHIFT (1U) -#define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK) -#define USB_ENDPT_EPTXEN_MASK (0x4U) -#define USB_ENDPT_EPTXEN_SHIFT (2U) -#define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK) -#define USB_ENDPT_EPRXEN_MASK (0x8U) -#define USB_ENDPT_EPRXEN_SHIFT (3U) -#define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK) -#define USB_ENDPT_EPCTLDIS_MASK (0x10U) -#define USB_ENDPT_EPCTLDIS_SHIFT (4U) -#define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK) -#define USB_ENDPT_RETRYDIS_MASK (0x40U) -#define USB_ENDPT_RETRYDIS_SHIFT (6U) -#define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK) -#define USB_ENDPT_HOSTWOHUB_MASK (0x80U) -#define USB_ENDPT_HOSTWOHUB_SHIFT (7U) -#define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK) - -/* The count of USB_ENDPT */ -#define USB_ENDPT_COUNT (16U) - -/*! @name USBCTRL - USB Control register */ -#define USB_USBCTRL_UARTSEL_MASK (0x10U) -#define USB_USBCTRL_UARTSEL_SHIFT (4U) -#define USB_USBCTRL_UARTSEL(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTSEL_SHIFT)) & USB_USBCTRL_UARTSEL_MASK) -#define USB_USBCTRL_UARTCHLS_MASK (0x20U) -#define USB_USBCTRL_UARTCHLS_SHIFT (5U) -#define USB_USBCTRL_UARTCHLS(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTCHLS_SHIFT)) & USB_USBCTRL_UARTCHLS_MASK) -#define USB_USBCTRL_PDE_MASK (0x40U) -#define USB_USBCTRL_PDE_SHIFT (6U) -#define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK) -#define USB_USBCTRL_SUSP_MASK (0x80U) -#define USB_USBCTRL_SUSP_SHIFT (7U) -#define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK) - -/*! @name OBSERVE - USB OTG Observe register */ -#define USB_OBSERVE_DMPD_MASK (0x10U) -#define USB_OBSERVE_DMPD_SHIFT (4U) -#define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK) -#define USB_OBSERVE_DPPD_MASK (0x40U) -#define USB_OBSERVE_DPPD_SHIFT (6U) -#define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK) -#define USB_OBSERVE_DPPU_MASK (0x80U) -#define USB_OBSERVE_DPPU_SHIFT (7U) -#define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK) - -/*! @name CONTROL - USB OTG Control register */ -#define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U) -#define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U) -#define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK) - -/*! @name USBTRC0 - USB Transceiver Control register 0 */ -#define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U) -#define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U) -#define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK) -#define USB_USBTRC0_SYNC_DET_MASK (0x2U) -#define USB_USBTRC0_SYNC_DET_SHIFT (1U) -#define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK) -#define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK (0x4U) -#define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT (2U) -#define USB_USBTRC0_USB_CLK_RECOVERY_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK) -#define USB_USBTRC0_VREDG_DET_MASK (0x8U) -#define USB_USBTRC0_VREDG_DET_SHIFT (3U) -#define USB_USBTRC0_VREDG_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VREDG_DET_SHIFT)) & USB_USBTRC0_VREDG_DET_MASK) -#define USB_USBTRC0_VFEDG_DET_MASK (0x10U) -#define USB_USBTRC0_VFEDG_DET_SHIFT (4U) -#define USB_USBTRC0_VFEDG_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VFEDG_DET_SHIFT)) & USB_USBTRC0_VFEDG_DET_MASK) -#define USB_USBTRC0_USBRESMEN_MASK (0x20U) -#define USB_USBTRC0_USBRESMEN_SHIFT (5U) -#define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK) -#define USB_USBTRC0_USBRESET_MASK (0x80U) -#define USB_USBTRC0_USBRESET_SHIFT (7U) -#define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK) - -/*! @name USBFRMADJUST - Frame Adjust Register */ -#define USB_USBFRMADJUST_ADJ_MASK (0xFFU) -#define USB_USBFRMADJUST_ADJ_SHIFT (0U) -#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK) - -/*! @name MISCCTRL - Miscellaneous Control register */ -#define USB_MISCCTRL_SOFDYNTHLD_MASK (0x1U) -#define USB_MISCCTRL_SOFDYNTHLD_SHIFT (0U) -#define USB_MISCCTRL_SOFDYNTHLD(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_SOFDYNTHLD_SHIFT)) & USB_MISCCTRL_SOFDYNTHLD_MASK) -#define USB_MISCCTRL_SOFBUSSET_MASK (0x2U) -#define USB_MISCCTRL_SOFBUSSET_SHIFT (1U) -#define USB_MISCCTRL_SOFBUSSET(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_SOFBUSSET_SHIFT)) & USB_MISCCTRL_SOFBUSSET_MASK) -#define USB_MISCCTRL_OWNERRISODIS_MASK (0x4U) -#define USB_MISCCTRL_OWNERRISODIS_SHIFT (2U) -#define USB_MISCCTRL_OWNERRISODIS(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_OWNERRISODIS_SHIFT)) & USB_MISCCTRL_OWNERRISODIS_MASK) -#define USB_MISCCTRL_VREDG_EN_MASK (0x8U) -#define USB_MISCCTRL_VREDG_EN_SHIFT (3U) -#define USB_MISCCTRL_VREDG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VREDG_EN_SHIFT)) & USB_MISCCTRL_VREDG_EN_MASK) -#define USB_MISCCTRL_VFEDG_EN_MASK (0x10U) -#define USB_MISCCTRL_VFEDG_EN_SHIFT (4U) -#define USB_MISCCTRL_VFEDG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VFEDG_EN_SHIFT)) & USB_MISCCTRL_VFEDG_EN_MASK) -#define USB_MISCCTRL_STL_ADJ_EN_MASK (0x80U) -#define USB_MISCCTRL_STL_ADJ_EN_SHIFT (7U) -#define USB_MISCCTRL_STL_ADJ_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_STL_ADJ_EN_SHIFT)) & USB_MISCCTRL_STL_ADJ_EN_MASK) - -/*! @name STALL_IL_DIS - Peripheral mode stall disable for endpoints 7 to 0 in IN direction */ -#define USB_STALL_IL_DIS_STALL_I_DIS0_MASK (0x1U) -#define USB_STALL_IL_DIS_STALL_I_DIS0_SHIFT (0U) -#define USB_STALL_IL_DIS_STALL_I_DIS0(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS0_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS0_MASK) -#define USB_STALL_IL_DIS_STALL_I_DIS1_MASK (0x2U) -#define USB_STALL_IL_DIS_STALL_I_DIS1_SHIFT (1U) -#define USB_STALL_IL_DIS_STALL_I_DIS1(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS1_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS1_MASK) -#define USB_STALL_IL_DIS_STALL_I_DIS2_MASK (0x4U) -#define USB_STALL_IL_DIS_STALL_I_DIS2_SHIFT (2U) -#define USB_STALL_IL_DIS_STALL_I_DIS2(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS2_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS2_MASK) -#define USB_STALL_IL_DIS_STALL_I_DIS3_MASK (0x8U) -#define USB_STALL_IL_DIS_STALL_I_DIS3_SHIFT (3U) -#define USB_STALL_IL_DIS_STALL_I_DIS3(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS3_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS3_MASK) -#define USB_STALL_IL_DIS_STALL_I_DIS4_MASK (0x10U) -#define USB_STALL_IL_DIS_STALL_I_DIS4_SHIFT (4U) -#define USB_STALL_IL_DIS_STALL_I_DIS4(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS4_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS4_MASK) -#define USB_STALL_IL_DIS_STALL_I_DIS5_MASK (0x20U) -#define USB_STALL_IL_DIS_STALL_I_DIS5_SHIFT (5U) -#define USB_STALL_IL_DIS_STALL_I_DIS5(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS5_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS5_MASK) -#define USB_STALL_IL_DIS_STALL_I_DIS6_MASK (0x40U) -#define USB_STALL_IL_DIS_STALL_I_DIS6_SHIFT (6U) -#define USB_STALL_IL_DIS_STALL_I_DIS6(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS6_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS6_MASK) -#define USB_STALL_IL_DIS_STALL_I_DIS7_MASK (0x80U) -#define USB_STALL_IL_DIS_STALL_I_DIS7_SHIFT (7U) -#define USB_STALL_IL_DIS_STALL_I_DIS7(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS7_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS7_MASK) - -/*! @name STALL_IH_DIS - Peripheral mode stall disable for endpoints 15 to 8 in IN direction */ -#define USB_STALL_IH_DIS_STALL_I_DIS8_MASK (0x1U) -#define USB_STALL_IH_DIS_STALL_I_DIS8_SHIFT (0U) -#define USB_STALL_IH_DIS_STALL_I_DIS8(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS8_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS8_MASK) -#define USB_STALL_IH_DIS_STALL_I_DIS9_MASK (0x2U) -#define USB_STALL_IH_DIS_STALL_I_DIS9_SHIFT (1U) -#define USB_STALL_IH_DIS_STALL_I_DIS9(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS9_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS9_MASK) -#define USB_STALL_IH_DIS_STALL_I_DIS10_MASK (0x4U) -#define USB_STALL_IH_DIS_STALL_I_DIS10_SHIFT (2U) -#define USB_STALL_IH_DIS_STALL_I_DIS10(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS10_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS10_MASK) -#define USB_STALL_IH_DIS_STALL_I_DIS11_MASK (0x8U) -#define USB_STALL_IH_DIS_STALL_I_DIS11_SHIFT (3U) -#define USB_STALL_IH_DIS_STALL_I_DIS11(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS11_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS11_MASK) -#define USB_STALL_IH_DIS_STALL_I_DIS12_MASK (0x10U) -#define USB_STALL_IH_DIS_STALL_I_DIS12_SHIFT (4U) -#define USB_STALL_IH_DIS_STALL_I_DIS12(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS12_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS12_MASK) -#define USB_STALL_IH_DIS_STALL_I_DIS13_MASK (0x20U) -#define USB_STALL_IH_DIS_STALL_I_DIS13_SHIFT (5U) -#define USB_STALL_IH_DIS_STALL_I_DIS13(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS13_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS13_MASK) -#define USB_STALL_IH_DIS_STALL_I_DIS14_MASK (0x40U) -#define USB_STALL_IH_DIS_STALL_I_DIS14_SHIFT (6U) -#define USB_STALL_IH_DIS_STALL_I_DIS14(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS14_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS14_MASK) -#define USB_STALL_IH_DIS_STALL_I_DIS15_MASK (0x80U) -#define USB_STALL_IH_DIS_STALL_I_DIS15_SHIFT (7U) -#define USB_STALL_IH_DIS_STALL_I_DIS15(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS15_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS15_MASK) - -/*! @name STALL_OL_DIS - Peripheral mode stall disable for endpoints 7 to 0 in OUT direction */ -#define USB_STALL_OL_DIS_STALL_O_DIS0_MASK (0x1U) -#define USB_STALL_OL_DIS_STALL_O_DIS0_SHIFT (0U) -#define USB_STALL_OL_DIS_STALL_O_DIS0(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS0_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS0_MASK) -#define USB_STALL_OL_DIS_STALL_O_DIS1_MASK (0x2U) -#define USB_STALL_OL_DIS_STALL_O_DIS1_SHIFT (1U) -#define USB_STALL_OL_DIS_STALL_O_DIS1(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS1_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS1_MASK) -#define USB_STALL_OL_DIS_STALL_O_DIS2_MASK (0x4U) -#define USB_STALL_OL_DIS_STALL_O_DIS2_SHIFT (2U) -#define USB_STALL_OL_DIS_STALL_O_DIS2(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS2_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS2_MASK) -#define USB_STALL_OL_DIS_STALL_O_DIS3_MASK (0x8U) -#define USB_STALL_OL_DIS_STALL_O_DIS3_SHIFT (3U) -#define USB_STALL_OL_DIS_STALL_O_DIS3(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS3_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS3_MASK) -#define USB_STALL_OL_DIS_STALL_O_DIS4_MASK (0x10U) -#define USB_STALL_OL_DIS_STALL_O_DIS4_SHIFT (4U) -#define USB_STALL_OL_DIS_STALL_O_DIS4(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS4_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS4_MASK) -#define USB_STALL_OL_DIS_STALL_O_DIS5_MASK (0x20U) -#define USB_STALL_OL_DIS_STALL_O_DIS5_SHIFT (5U) -#define USB_STALL_OL_DIS_STALL_O_DIS5(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS5_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS5_MASK) -#define USB_STALL_OL_DIS_STALL_O_DIS6_MASK (0x40U) -#define USB_STALL_OL_DIS_STALL_O_DIS6_SHIFT (6U) -#define USB_STALL_OL_DIS_STALL_O_DIS6(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS6_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS6_MASK) -#define USB_STALL_OL_DIS_STALL_O_DIS7_MASK (0x80U) -#define USB_STALL_OL_DIS_STALL_O_DIS7_SHIFT (7U) -#define USB_STALL_OL_DIS_STALL_O_DIS7(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS7_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS7_MASK) - -/*! @name STALL_OH_DIS - Peripheral mode stall disable for endpoints 15 to 8 in OUT direction */ -#define USB_STALL_OH_DIS_STALL_O_DIS8_MASK (0x1U) -#define USB_STALL_OH_DIS_STALL_O_DIS8_SHIFT (0U) -#define USB_STALL_OH_DIS_STALL_O_DIS8(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS8_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS8_MASK) -#define USB_STALL_OH_DIS_STALL_O_DIS9_MASK (0x2U) -#define USB_STALL_OH_DIS_STALL_O_DIS9_SHIFT (1U) -#define USB_STALL_OH_DIS_STALL_O_DIS9(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS9_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS9_MASK) -#define USB_STALL_OH_DIS_STALL_O_DIS10_MASK (0x4U) -#define USB_STALL_OH_DIS_STALL_O_DIS10_SHIFT (2U) -#define USB_STALL_OH_DIS_STALL_O_DIS10(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS10_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS10_MASK) -#define USB_STALL_OH_DIS_STALL_O_DIS11_MASK (0x8U) -#define USB_STALL_OH_DIS_STALL_O_DIS11_SHIFT (3U) -#define USB_STALL_OH_DIS_STALL_O_DIS11(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS11_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS11_MASK) -#define USB_STALL_OH_DIS_STALL_O_DIS12_MASK (0x10U) -#define USB_STALL_OH_DIS_STALL_O_DIS12_SHIFT (4U) -#define USB_STALL_OH_DIS_STALL_O_DIS12(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS12_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS12_MASK) -#define USB_STALL_OH_DIS_STALL_O_DIS13_MASK (0x20U) -#define USB_STALL_OH_DIS_STALL_O_DIS13_SHIFT (5U) -#define USB_STALL_OH_DIS_STALL_O_DIS13(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS13_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS13_MASK) -#define USB_STALL_OH_DIS_STALL_O_DIS14_MASK (0x40U) -#define USB_STALL_OH_DIS_STALL_O_DIS14_SHIFT (6U) -#define USB_STALL_OH_DIS_STALL_O_DIS14(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS14_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS14_MASK) -#define USB_STALL_OH_DIS_STALL_O_DIS15_MASK (0x80U) -#define USB_STALL_OH_DIS_STALL_O_DIS15_SHIFT (7U) -#define USB_STALL_OH_DIS_STALL_O_DIS15(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS15_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS15_MASK) - -/*! @name CLK_RECOVER_CTRL - USB Clock recovery control */ -#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U) -#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U) -#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK) -#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U) -#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U) -#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK) -#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U) -#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U) -#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK) - -/*! @name CLK_RECOVER_IRC_EN - IRC48M oscillator enable register */ -#define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK (0x1U) -#define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT (0U) -#define USB_CLK_RECOVER_IRC_EN_REG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_REG_EN_MASK) -#define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK (0x2U) -#define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT (1U) -#define USB_CLK_RECOVER_IRC_EN_IRC_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK) - -/*! @name CLK_RECOVER_INT_EN - Clock recovery combined interrupt enable */ -#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK (0x10U) -#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT (4U) -#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT)) & USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK) - -/*! @name CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status */ -#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U) -#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U) -#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK) - -#define USB0_BASE ((0x50000000)) - -#define USB_BASE_ADDRS { USB0_BASE } - - - - - - - -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -#endif //__REG_USB_OTG_FS_H -//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_wwdg.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_wwdg.h deleted file mode 100644 index a802bbab6..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_wwdg.h +++ /dev/null @@ -1,133 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file reg_wwdg.h -/// @author AE TEAM -/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF -/// MM32 FIRMWARE LIBRARY. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion - -#ifndef __REG_WWDG_H -#define __REG_WWDG_H - -// Files includes - -#include -#include -#include "types.h" - - - - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - - - - - - - - - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief WWDG Base Address Definition -//////////////////////////////////////////////////////////////////////////////// -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) ///< Base Address: 0x40002C00 - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief WWDG Register Structure Definition -//////////////////////////////////////////////////////////////////////////////// -#undef USENCOMBINEREGISTER -#undef USENNEWREGISTER -#undef USENOLDREGISTER -#define USENCOMBINEREGISTER -#ifdef USENCOMBINEREGISTER -typedef struct { - __IO u32 CR; ///< Control register offset: 0x00 - union { - __IO u32 CFGR; ///< Configuration register offset: 0x04 - __IO u32 CFR; - }; - __IO u32 SR; ///< Status register offset: 0x08 -} WWDG_TypeDef; -#endif -#ifdef USENNEWREGISTER -typedef struct { - __IO u32 CR; ///< Control register offset: 0x00 - __IO u32 CFGR; ///< Configuration register offset: 0x04 - __IO u32 SR; ///< Status register offset: 0x08 -} WWDG_TypeDef; -#endif -#ifdef USENOLDREGISTER -typedef struct { - __IO u32 CR; - __IO u32 CFR; - __IO u32 SR; -} WWDG_TypeDef; -#endif - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief WWDG type pointer Definition -//////////////////////////////////////////////////////////////////////////////// -#define WWDG ((WWDG_TypeDef*) WWDG_BASE) - - - -//////////////////////////////////////////////////////////////////////////////// -/// @brief WWDG_CR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define WWDG_CR_CNT_Pos (0) -#define WWDG_CR_CNT (0x7FU << WWDG_CR_CNT_Pos) ///< T[6:0] bits (7-Bit counter (MSB to LSB)) -#define WWDG_CR_WDGA_Pos (7) -#define WWDG_CR_WDGA (0x01U << WWDG_CR_WDGA_Pos) ///< Activation bit - -//////////////////////////////////////////////////////////////////////////////// -/// @brief WWDG_CFR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define WWDG_CFGR_WINDOW_Pos (0) -#define WWDG_CFGR_WINDOW (0x7FU << WWDG_CFGR_WINDOW_Pos) ///< W[6:0] bits (7-bit window value) -#define WWDG_CFGR_WDGTB_Pos (7) -#define WWDG_CFGR_WDGTB (0x03U << WWDG_CFGR_WDGTB_Pos) ///< WDGTB[1:0] bits (Timer Base) -#define WWDG_CFGR_WDGTB_1 (0x00U << WWDG_CFGR_WDGTB_Pos) ///< WDGTB[1:0] bits (Timer Base /1) -#define WWDG_CFGR_WDGTB_2 (0x01U << WWDG_CFGR_WDGTB_Pos) ///< WDGTB[1:0] bits (Timer Base /2) -#define WWDG_CFGR_WDGTB_4 (0x02U << WWDG_CFGR_WDGTB_Pos) ///< WDGTB[1:0] bits (Timer Base /4) -#define WWDG_CFGR_WDGTB_8 (0x03U << WWDG_CFGR_WDGTB_Pos) ///< WDGTB[1:0] bits (Timer Base /8) -#define WWDG_CFGR_EWI_Pos (9) -#define WWDG_CFGR_EWI (0x01U << WWDG_CFGR_EWI_Pos) ///< Early Wakeup Interrupt - -//////////////////////////////////////////////////////////////////////////////// -/// @brief WWDG_SR Register Bit Definition -//////////////////////////////////////////////////////////////////////////////// -#define WWDG_SR_EWIF_Pos (0) -#define WWDG_SR_EWIF (0x01U << WWDG_SR_EWIF_Pos) ///< Early Wakeup Interrupt Flag - - - - -/// @} - -/// @} - -/// @} - -//////////////////////////////////////////////////////////////////////////////// -#endif -//////////////////////////////////////////////////////////////////////////////// diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/types.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/types.h deleted file mode 100644 index baceddd05..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/types.h +++ /dev/null @@ -1,105 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file types.h -/// @author AE TEAM -/// @brief THIS FILE PROVIDES ALL THE TYPE FIRMWARE FUNCTIONS. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#ifndef __TYPES_H -#define __TYPES_H - -// Files includes -#include -#include - - - -#ifdef __cplusplus -#define __I volatile ///< Defines 'read only' permissions -#else -#define __I volatile const ///< Defines 'read only' permissions -#endif -#define __O volatile ///< Defines 'write only' permissions -#define __IO volatile ///< Defines 'read / write' permissions - -typedef long long s64; ///< used for signed 64bit - -typedef signed int s32; -typedef signed short s16; -typedef signed char s8; - -typedef signed int const sc32; ///< Read Only -typedef signed short const sc16; ///< Read Only -typedef signed char const sc8; ///< Read Only - -typedef volatile signed int vs32; -typedef volatile signed short vs16; -typedef volatile signed char vs8; - -typedef volatile signed int const vsc32; ///< Read Only -typedef volatile signed short const vsc16; ///< Read Only -typedef volatile signed char const vsc8; ///< Read Only - -typedef unsigned int u32; -typedef unsigned short u16; -typedef unsigned char u8; - -typedef unsigned int const uc32; ///< Read Only -typedef unsigned short const uc16; ///< Read Only -typedef unsigned char const uc8; ///< Read Only - -typedef volatile unsigned int vu32; -typedef volatile unsigned short vu16; -typedef volatile unsigned char vu8; - -typedef volatile unsigned int const vuc32; ///< Read Only -typedef volatile unsigned short const vuc16; ///< Read Only -typedef volatile unsigned char const vuc8; ///< Read Only -typedef bool BOOL; -#ifndef NULL -#define NULL ((void *)0) -#endif -typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; -typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; -typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; - - -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -#define U8_MAX ((u8)255) -#define S8_MAX ((s8)127) -#define S8_MIN ((s8)-128) -#define U16_MAX ((u16)65535u) -#define S16_MAX ((s16)32767) -#define S16_MIN ((s16)-32768) -#define U32_MAX ((u32)4294967295uL) -#define S32_MAX ((s32)2147483647) -#define S32_MIN ((s32)-2147483648uL) - -#define MAX(a,b)((a)>(b)?(a):(b)) -#define MIN(a,b)((a)<(b)?(a):(b)) - -#define SET_BIT(reg, bit) ((reg) |= (bit)) -#define CLEAR_BIT(reg, bit) ((reg) &= ~(bit)) -#define READ_BIT(reg, bit) ((reg) & (bit)) -#define CLEAR_REG(reg) ((reg) = (0x0)) -#define WRITE_REG(reg, value) ((reg) = (value)) -#define READ_REG(reg) ((reg)) -#define MODIFY_REG(reg, CLEARMASK, SETMASK) WRITE_REG((reg), (((READ_REG(reg)) & (~(CLEARMASK))) | (SETMASK))) -#define POSITION_VAL(value) (__CLZ(__RBIT(value))) - -#define LEFT_SHIFT_BIT(x) (1 << x) - - -#endif diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Source/GCC_StartAsm/startup_mm32m3ux_u_gcc.S b/hw/mcu/mm32/mm32f327x/MM32F327x/Source/GCC_StartAsm/startup_mm32m3ux_u_gcc.S deleted file mode 100644 index 920aefcba..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/Source/GCC_StartAsm/startup_mm32m3ux_u_gcc.S +++ /dev/null @@ -1,440 +0,0 @@ -/** - ****************************************************************************** - * @file startup_mm32m3ux_u_gcc.s - * @author AE Team - * @brief MM32 devices vector table for GCC toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m3 - .fpu softvfp - .thumb - - .global g_pfnVectors - .global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ - .word _sidata -/* start address for the .data section. defined in linker script */ - .word _sdata -/* end address for the .data section. defined in linker script */ - .word _edata -/* start address for the .bss section. defined in linker script */ - .word _sbss -/* end address for the .bss section. defined in linker script */ - .word _ebss - -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss - -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call static constructors */ - bl __libc_init_array -/* Call the application's entry point.*/ - bl main - bx lr - .size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack /* Top of Stack */ - .word Reset_Handler /* Reset Handler */ - .word NMI_Handler /*-14 NMI Handler */ - .word HardFault_Handler /*-13 Hard Fault Handler */ - .word MemManage_Handler /*-12 MPU Fault Handler */ - .word BusFault_Handler /*-11 Bus Fault Handler */ - .word UsageFault_Handler /*-10 Usage Fault Handler */ - .word 0 /*-9 Reserved */ - .word 0 /*-8 Reserved */ - .word 0 /*-7 Reserved */ - .word 0 /*-6 Reserved */ - .word SVC_Handler /*-5 SVCall Handler */ - .word DebugMon_Handler /*-4 Debug Monitor Handler */ - .word 0 /*-3 Reserved */ - .word PendSV_Handler /*-2 PendSV Handler */ - .word SysTick_Handler /*-1 SysTick Handler */ - - /* External Interrupts */ - .word WWDG_IRQHandler /*0 Window Watchdog */ - .word PVD_IRQHandler /*1 PVD through EXTI Line detect */ - .word TAMPER_IRQHandler /*2 Tamper */ - .word RTC_IRQHandler /*3 RTC */ - .word FLASH_IRQHandler /*4 Flash */ - .word RCC_CRS_IRQHandler /*5 RCC */ - .word EXTI0_IRQHandler /*6 EXTI Line 0 */ - .word EXTI1_IRQHandler /*7 EXTI Line 1 */ - .word EXTI2_IRQHandler /*8 EXTI Line 2 */ - .word EXTI3_IRQHandler /*9 EXTI Line 3 */ - .word EXTI4_IRQHandler /*10 EXTI Line 4 */ - .word DMA1_Channel1_IRQHandler /*11 DMA1 Channel 1 */ - .word DMA1_Channel2_IRQHandler /*12 DMA1 Channel 2 */ - .word DMA1_Channel3_IRQHandler /*13 DMA1 Channel 3 */ - .word DMA1_Channel4_IRQHandler /*14 DMA1 Channel 4 */ - .word DMA1_Channel5_IRQHandler /*15 DMA1 Channel 5 */ - .word DMA1_Channel6_IRQHandler /*16 DMA1 Channel 6 */ - .word DMA1_Channel7_IRQHandler /*17 DMA1 Channel 7 */ - .word ADC1_2_IRQHandler /*18 ADC1 and ADC2 */ - .word FlashCache_IRQHandler /*19 FlashCache outage */ - .word 0 /*20 Reserved */ - .word CAN1_RX_IRQHandler /*21 CAN1_RX */ - .word 0 /*22 Reserved */ - .word EXTI9_5_IRQHandler /*23 EXTI Line 9..5 */ - .word TIM1_BRK_IRQHandler /*24 TIM1 Break */ - .word TIM1_UP_IRQHandler /*25 TIM1 Update */ - .word TIM1_TRG_COM_IRQHandler /*26 TIM1 Trigger and Commutation */ - .word TIM1_CC_IRQHandler /*27 TIM1 Capture Compare */ - .word TIM2_IRQHandler /*28 TIM2 */ - .word TIM3_IRQHandler /*29 TIM3 */ - .word TIM4_IRQHandler /*30 TIM4 */ - .word I2C1_IRQHandler /*31 I2C1 Event */ - .word 0 /*32 Reserved */ - .word I2C2_IRQHandler /*33 I2C2 Event */ - .word 0 /*34 Reserved */ - .word SPI1_IRQHandler /*35 SPI1 */ - .word SPI2_IRQHandler /*36 SPI2 */ - .word UART1_IRQHandler /*37 UART1 */ - .word UART2_IRQHandler /*38 UART2 */ - .word UART3_IRQHandler /*39 UART3 */ - .word EXTI15_10_IRQHandler /*40 EXTI Line 15..10 */ - .word RTCAlarm_IRQHandler /*41 RTC Alarm through EXTI Line 17 */ - .word OTG_FS_WKUP_IRQHandler /*42 USB OTG FS Wakeup through EXTI line */ - .word TIM8_BRK_IRQHandler /*43 TIM8 Break */ - .word TIM8_UP_IRQHandler /*44 TIM8 Update */ - .word TIM8_TRG_COM_IRQHandler /*45 TIM8 Trigger and Commutation */ - .word TIM8_CC_IRQHandler /*46 TIM8 Capture Compare */ - .word ADC3_IRQHandler /*47 ADC3 */ - .word 0 /*48 Reserved */ - .word SDIO_IRQHandler /*49 SDIO */ - .word TIM5_IRQHandler /*50 TIM5 */ - .word SPI3_IRQHandler /*51 SPI3 */ - .word UART4_IRQHandler /*52 UART4 */ - .word UART5_IRQHandler /*53 UART5 */ - .word TIM6_IRQHandler /*54 TIM6 */ - .word TIM7_IRQHandler /*55 TIM7 */ - .word DMA2_Channel1_IRQHandler /*56 DMA2 Channel 1 */ - .word DMA2_Channel2_IRQHandler /*57 DMA2 Channel 2 */ - .word DMA2_Channel3_IRQHandler /*58 DMA2 Channel 3 */ - .word DMA2_Channel4_IRQHandler /*59 DMA2 Channel 4 */ - .word DMA2_Channel5_IRQHandler /*60 DMA2 Channel 5 */ - .word ETH_IRQHandler /*61 Ethernet */ - .word 0 /*62 Reserved */ - .word 0 /*63 Reserved */ - .word COMP1_2_IRQHandler /*64 COMP1,COMP2 */ - .word 0 /*65 Reserved */ - .word 0 /*66 Reserved */ - .word OTG_FS_IRQHandler /*67 USB OTG_FullSpeed */ - .word 0 /*68 Reserved */ - .word 0 /*69 Reserved */ - .word 0 /*70 Reserved */ - .word UART6_IRQHandler /*71 UART6 */ - .word 0 /*72 Reserved */ - .word 0 /*73 Reserved */ - .word 0 /*74 Reserved */ - .word 0 /*75 Reserved */ - .word 0 /*76 Reserved */ - .word 0 /*77 Reserved */ - .word 0 /*78 Reserved */ - .word 0 /*79 Reserved */ - .word 0 /*80 Reserved */ - .word 0 /*81 Reserved */ - .word UART7_IRQHandler /*82 UART7 */ - .word UART8_IRQHandler /*83 UART8 */ -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - .weak NMI_Handler - .thumb_set NMI_Handler ,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler ,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler ,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler ,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler ,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler ,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler ,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler ,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler ,Default_Handler - - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler ,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler ,Default_Handler - - .weak TAMPER_IRQHandler - .thumb_set TAMPER_IRQHandler ,Default_Handler - - .weak RTC_IRQHandler - .thumb_set RTC_IRQHandler ,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler ,Default_Handler - - .weak RCC_CRS_IRQHandler - .thumb_set RCC_CRS_IRQHandler ,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler ,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler ,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler ,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler ,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler ,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler ,Default_Handler - - .weak DMA1_Channel2_IRQHandler - .thumb_set DMA1_Channel2_IRQHandler ,Default_Handler - - .weak DMA1_Channel3_IRQHandler - .thumb_set DMA1_Channel3_IRQHandler ,Default_Handler - - .weak DMA1_Channel4_IRQHandler - .thumb_set DMA1_Channel4_IRQHandler ,Default_Handler - - .weak DMA1_Channel5_IRQHandler - .thumb_set DMA1_Channel5_IRQHandler ,Default_Handler - - .weak DMA1_Channel6_IRQHandler - .thumb_set DMA1_Channel6_IRQHandler ,Default_Handler - - .weak DMA1_Channel7_IRQHandler - .thumb_set DMA1_Channel7_IRQHandler ,Default_Handler - - .weak ADC1_2_IRQHandler - .thumb_set ADC1_2_IRQHandler ,Default_Handler - - .weak FlashCache_IRQHandler - .thumb_set FlashCache_IRQHandler ,Default_Handler - - .weak CAN1_RX_IRQHandler - .thumb_set CAN1_RX_IRQHandler ,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler ,Default_Handler - - .weak TIM1_BRK_IRQHandler - .thumb_set TIM1_BRK_IRQHandler ,Default_Handler - - .weak TIM1_UP_IRQHandler - .thumb_set TIM1_UP_IRQHandler ,Default_Handler - - .weak TIM1_TRG_COM_IRQHandler - .thumb_set TIM1_TRG_COM_IRQHandler ,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler ,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler ,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler ,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler ,Default_Handler - - .weak I2C1_IRQHandler - .thumb_set I2C1_IRQHandler ,Default_Handler - - .weak I2C2_IRQHandler - .thumb_set I2C2_IRQHandler ,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler ,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler ,Default_Handler - - .weak UART1_IRQHandler - .thumb_set UART1_IRQHandler ,Default_Handler - - .weak UART2_IRQHandler - .thumb_set UART2_IRQHandler ,Default_Handler - - .weak UART3_IRQHandler - .thumb_set UART3_IRQHandler ,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler ,Default_Handler - - .weak RTCAlarm_IRQHandler - .thumb_set RTCAlarm_IRQHandler ,Default_Handler - - .weak OTG_FS_WKUP_IRQHandler - .thumb_set OTG_FS_WKUP_IRQHandler ,Default_Handler - - .weak TIM8_BRK_IRQHandler - .thumb_set TIM8_BRK_IRQHandler ,Default_Handler - - .weak TIM8_UP_IRQHandler - .thumb_set TIM8_UP_IRQHandler ,Default_Handler - - .weak TIM8_TRG_COM_IRQHandler - .thumb_set TIM8_TRG_COM_IRQHandler ,Default_Handler - - .weak TIM8_CC_IRQHandler - .thumb_set TIM8_CC_IRQHandler ,Default_Handler - - .weak ADC3_IRQHandler - .thumb_set ADC3_IRQHandler ,Default_Handler - - .weak SDIO_IRQHandler - .thumb_set SDIO_IRQHandler ,Default_Handler - - .weak TIM5_IRQHandler - .thumb_set TIM5_IRQHandler ,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler ,Default_Handler - - .weak UART4_IRQHandler - .thumb_set UART4_IRQHandler ,Default_Handler - - .weak UART5_IRQHandler - .thumb_set UART5_IRQHandler ,Default_Handler - - .weak TIM6_IRQHandler - .thumb_set TIM6_IRQHandler ,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler ,Default_Handler - - .weak DMA2_Channel1_IRQHandler - .thumb_set DMA2_Channel1_IRQHandler ,Default_Handler - - .weak DMA2_Channel2_IRQHandler - .thumb_set DMA2_Channel2_IRQHandler ,Default_Handler - - .weak DMA2_Channel3_IRQHandler - .thumb_set DMA2_Channel3_IRQHandler ,Default_Handler - - .weak DMA2_Channel4_IRQHandler - .thumb_set DMA2_Channel4_IRQHandler ,Default_Handler - - .weak DMA2_Channel5_IRQHandler - .thumb_set DMA2_Channel5_IRQHandler ,Default_Handler - - .weak ETH_IRQHandler - .thumb_set ETH_IRQHandler ,Default_Handler - - .weak COMP1_2_IRQHandler - .thumb_set COMP1_2_IRQHandler ,Default_Handler - - .weak OTG_FS_IRQHandler - .thumb_set OTG_FS_IRQHandler ,Default_Handler - - .weak UART6_IRQHandler - .thumb_set UART6_IRQHandler ,Default_Handler - - .weak UART7_IRQHandler - .thumb_set UART7_IRQHandler ,Default_Handler - - .weak UART8_IRQHandler - .thumb_set UART8_IRQHandler ,Default_Handler - - - - -/****END OF FILE****/ - diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Source/system_mm32f327x.c b/hw/mcu/mm32/mm32f327x/MM32F327x/Source/system_mm32f327x.c deleted file mode 100644 index cdfa8e801..000000000 --- a/hw/mcu/mm32/mm32f327x/MM32F327x/Source/system_mm32f327x.c +++ /dev/null @@ -1,866 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file SYSTEM_MM32.C -/// @author AE TEAM -/// @brief THIS FILE PROVIDES ALL THE SYSTEM FUNCTIONS. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - -// Define to prevent recursive inclusion -#define _SYSTEM_MM32_C_ - -// Files includes - -/// @addtogroup CMSIS -/// @{ - -#include "mm32_device.h" - - -/// @} - - - -/// @} - - -/// Uncomment the line corresponding to the desired System clock (SYSCLK) -/// frequency (after reset the HSI is used as SYSCLK source) -/// -/// IMPORTANT NOTE: -/// ============== -/// 1. After each device reset the HSI is used as System clock source. -/// -/// 2. Please make sure that the selected System clock doesn't exceed your device's -/// maximum frequency. -/// -/// 3. If none of the define below is enabled, the HSI is used as System clock -/// source. -/// -/// 4. The System clock configuration functions provided within this file assume that: -/// - For Low, Medium and High density Value line devices an external 8MHz -/// crystal is used to drive the System clock. -/// - For Low, Medium and High density devices an external 8MHz crystal is -/// used to drive the System clock. -/// - For Connectivity line devices an external 25MHz crystal is used to drive -/// the System clock. -/// If you are using different crystal you have to adapt those functions accordingly. - -//#define SYSCLK_FREQ_HSE HSE_VALUE //HSE_VALUE is define in reg_common.h -//#define SYSCLK_FREQ_24MHz (HSE_VALUE*3) //24000000 based HSE_VALUE = 8000000 -//#define SYSCLK_FREQ_36MHz (HSE_VALUE*9/2) //36000000 based HSE_VALUE = 8000000 -//#define SYSCLK_FREQ_48MHz (HSE_VALUE*6) //48000000 based HSE_VALUE = 8000000 -//#define SYSCLK_FREQ_XXMHz (HSE_VALUE*6) //48000000 based HSE_VALUE = 8000000 -//#define SYSCLK_FREQ_XXMHz (HSE_VALUE*9) //72000000 based HSE_VALUE = 8000000 -//#define SYSCLK_FREQ_XXMHz (HSE_VALUE*12) //96000000 based HSE_VALUE = 8000000 -#define SYSCLK_FREQ_XXMHz (HSE_VALUE*12) //120000000 based HSE_VALUE = 8000000 - -#if defined(SYSCLK_FREQ_HSE) || defined(SYSCLK_FREQ_24MHz) || defined(SYSCLK_FREQ_36MHz) || defined(SYSCLK_FREQ_48MHz) || defined(SYSCLK_FREQ_XXMHz) - -#if defined(HSE_VALUE) && (!(HSE_VALUE == 8000000)) -#warning redefine HSE_VALUE in reg_common.h Line 48 and ignore this warning -#endif - -#endif - - -//#define SYSCLK_HSI_24MHz 24000000 -//#define SYSCLK_HSI_36MHz 36000000 -//#define SYSCLK_HSI_48MHz 48000000 -//#define SYSCLK_HSI_XXMHz 48000000 -//#define SYSCLK_HSI_XXMHz 72000000 -//#define SYSCLK_HSI_XXMHz 96000000 -#define SYSCLK_HSI_XXMHz 120000000 -/// Uncomment the following line if you need to relocate your vector Table in -/// Internal SRAM. -///#define VECT_TAB_SRAM -#define VECT_TAB_OFFSET 0x0 -/// Vector Table base offset field. -/// This value must be a multiple of 0x200. - - -/// @} - - - - -/////////////////////////////////////////////////////////////// -///Clock Definitions -/////////////////////////////////////////////////////////////// -#if defined SYSCLK_FREQ_HSE -u32 SystemCoreClock = SYSCLK_FREQ_HSE; -#elif defined SYSCLK_FREQ_24MHz -u32 SystemCoreClock = SYSCLK_FREQ_24MHz; -#elif defined SYSCLK_FREQ_36MHz -u32 SystemCoreClock = SYSCLK_FREQ_36MHz; -#elif defined SYSCLK_FREQ_48MHz -u32 SystemCoreClock = SYSCLK_FREQ_48MHz; -#elif defined SYSCLK_FREQ_XXMHz -u32 SystemCoreClock = SYSCLK_FREQ_XXMHz; - - -#elif defined SYSCLK_HSI_24MHz -u32 SystemCoreClock = SYSCLK_HSI_24MHz; -#elif defined SYSCLK_HSI_36MHz -u32 SystemCoreClock = SYSCLK_HSI_36MHz; -#elif defined SYSCLK_HSI_48MHz -u32 SystemCoreClock = SYSCLK_HSI_48MHz; -#elif defined SYSCLK_HSI_XXMHz -u32 SystemCoreClock = SYSCLK_HSI_XXMHz; -#else //HSI Selected as System Clock source -u32 SystemCoreClock = HSI_VALUE; -#endif - -__I u8 AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - -/// @} - - -static void SetSysClock(void); - -#if defined SYSCLK_FREQ_HSE -static void SetSysClockToHSE(void); -#elif defined SYSCLK_FREQ_24MHz -static void SetSysClockTo24(void); -#elif defined SYSCLK_FREQ_36MHz -static void SetSysClockTo36(void); -#elif defined SYSCLK_FREQ_48MHz -static void SetSysClockTo48(void); -#elif defined SYSCLK_FREQ_XXMHz -static void SetSysClockToXX(void); - -#elif defined SYSCLK_HSI_24MHz -static void SetSysClockTo24_HSI(void); -#elif defined SYSCLK_HSI_36MHz -static void SetSysClockTo36_HSI(void); -#elif defined SYSCLK_HSI_48MHz -static void SetSysClockTo48_HSI(void); -#elif defined SYSCLK_HSI_XXMHz -static void SetSysClockToXX_HSI(void); -#endif - -#ifdef DATA_IN_ExtSRAM -static void SystemInit_ExtMemCtl(void); -#endif //DATA_IN_ExtSRAM - - -/// @} - - - -/// @brief Setup the microcontroller system -/// Initialize the Embedded Flash Interface, the PLL and update the -/// SystemCoreClock variable. -/// @note This function should be used only after reset. -/// @param None -/// @retval None - -void SystemInit (void) -{ - //Reset the RCC clock configuration to the default reset state(for debug purpose) - //Set HSION bit - RCC->CR |= (u32)0x00000001; - - //Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits - RCC->CFGR &= (u32)0xF8FFC00C; - - //Reset HSEON, CSSON and PLLON bits - RCC->CR &= (u32)0xFEF6FFFF; - - //Reset HSEBYP bit - RCC->CR &= (u32)0xFFFBFFFF; - - //Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits - RCC->CFGR &= (u32)0xFF3CFFFF; - RCC->CR &= (u32)0x008FFFFF; - - //Disable all interrupts and clear pending bits - RCC->CIR = 0x009F0000; - //Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers - //Configure the Flash Latency cycles and enable prefetch buffer - SetSysClock(); -} - - -/// @brief use to return the pllm&plln. -/// @param pllclkSourceFrq : PLL source clock frquency; -/// pllclkFrq : Target PLL clock frquency; -/// plln : PLL factor PLLN -/// pllm : PLL factor PLLM -/// @retval amount of error -u32 AutoCalPllFactor(u32 pllclkSourceFrq, u32 pllclkFrq, u8* plln, u8* pllm) -{ - u32 n, m; - u32 tempFrq; - u32 minDiff = pllclkFrq; - u8 flag = 0; - for(m = 0; m < 4 ; m++) { - for(n = 0; n < 64 ; n++) { - tempFrq = pllclkSourceFrq * (n + 1) / (m + 1); - tempFrq = (tempFrq > pllclkFrq) ? (tempFrq - pllclkFrq) : (pllclkFrq - tempFrq) ; - - if(minDiff > tempFrq) { - minDiff = tempFrq; - *plln = n; - *pllm = m; - } - if(minDiff == 0) { - flag = 1; - break; - } - } - if(flag != 0) { - break; - } - } - return minDiff; -} -static void DELAY_xUs(u32 count) -{ - u32 temp; - SysTick->CTRL = 0x0; //disable systick function - SysTick->LOAD = count * 8; //time count for 1us with HSI as SYSCLK - SysTick->VAL = 0x00; //clear counter - SysTick->CTRL = 0x5; //start discrease with Polling - do { - temp = SysTick->CTRL; - } while((temp & 0x01) && !(temp & (1 << 16))); //wait time count done - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; //Close Counter - SysTick->VAL = 0X00; //clear counter -} -/// @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. -/// @param None -/// @retval None - -static void SetSysClock(void) -{ - CACHE->CCR &= ~(0x3 << 3); - CACHE->CCR |= 1; - while((CACHE->SR & 0x3) != 2); -#ifdef SYSCLK_FREQ_HSE - SetSysClockToHSE(); -#elif defined SYSCLK_FREQ_24MHz - SetSysClockTo24(); -#elif defined SYSCLK_FREQ_36MHz - SetSysClockTo36(); -#elif defined SYSCLK_FREQ_48MHz - SetSysClockTo48(); -#elif defined SYSCLK_FREQ_XXMHz - SetSysClockToXX(); - -#elif defined SYSCLK_HSI_24MHz - SetSysClockTo24_HSI(); -#elif defined SYSCLK_HSI_36MHz - SetSysClockTo36_HSI(); -#elif defined SYSCLK_HSI_48MHz - SetSysClockTo48_HSI(); -#elif defined SYSCLK_HSI_XXMHz - SetSysClockToXX_HSI(); -#endif - - //If none of the define above is enabled, the HSI is used as System clock - //source (default after reset) -} - -#ifdef SYSCLK_FREQ_HSE - -/// @brief Selects HSE as System clock source and configure HCLK, PCLK2 -/// and PCLK1 prescalers. -/// @note This function should be used only after reset. -/// @param None -/// @retval None - -static void SetSysClockToHSE(void) -{ - __IO u32 StartUpCounter = 0, HSEStatus = 0; - s32 i; - - //SYSCLK, HCLK, PCLK2 and PCLK1 configuration --------------------------- - //Enable HSE - RCC->CR |= ((u32)RCC_CR_HSEON); - - //Wait till HSE is ready and if Time out is reached exit - do { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) { - HSEStatus = (u32)0x01; - i = 2000; - while(i--); - } - else { - HSEStatus = (u32)0x00; - } - - if (HSEStatus == (u32)0x01) { - //Enable Prefetch Buffer - FLASH->ACR |= FLASH_ACR_PRFTBE; - - //Flash 0 wait state ,bit0~2 - FLASH->ACR &= ~0x07; - //HCLK = SYSCLK - RCC->CFGR |= (u32)RCC_CFGR_HPRE_DIV1; - - //PCLK2 = HCLK - RCC->CFGR |= (u32)RCC_CFGR_PPRE2_DIV1; - - //PCLK1 = HCLK - RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV1; - - //Select HSE as system clock source - RCC->CFGR &= (u32)((u32)~(RCC_CFGR_SW)); - RCC->CFGR |= (u32)RCC_CFGR_SW_HSE; - - //Wait till HSE is used as system clock source - while ((RCC->CFGR & (u32)RCC_CFGR_SWS) != (u32)0x04) { - } - } - else { - //If HSE fails to start-up, the application will have wrong clock - //configuration. User can add here some code to deal with this error - } -} -#elif defined SYSCLK_FREQ_24MHz - -/// @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 -/// and PCLK1 prescalers. -/// @note This function should be used only after reset. -/// @param None -/// @retval None - -static void SetSysClockTo24(void) -{ - __IO u32 StartUpCounter = 0, HSEStatus = 0; - s32 i; - - //SYSCLK, HCLK, PCLK2 and PCLK1 configuration --------------------------- - //Enable HSE - RCC->CR |= ((u32)RCC_CR_HSEON); - - //Wait till HSE is ready and if Time out is reached exit - do { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) { - HSEStatus = (u32)0x01; - i = 2000; - while(i--); - } - else { - HSEStatus = (u32)0x00; - } - - if (HSEStatus == (u32)0x01) { - //Enable Prefetch Buffer - FLASH->ACR |= FLASH_ACR_PRFTBE; - //Flash 0 wait state ,bit0~2 - FLASH->ACR &= ~0x07; - FLASH->ACR |= 0x01; - //HCLK = SYSCLK - RCC->CFGR |= (u32)RCC_CFGR_HPRE_DIV1; - - //PCLK2 = HCLK - RCC->CFGR |= (u32)RCC_CFGR_PPRE2_DIV1; - - //PCLK1 = HCLK - RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV1; - - // PLL configuration: = (HSE ) * (2+1) = 24 MHz - RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ; - RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC ; - - RCC->APB1ENR |= RCC_APB1ENR_PWR; - RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP)); - RCC->PLLCFGR |= ((0 << RCC_PLLCFGR_PLL_DN_Pos) | (2 << RCC_PLLCFGR_PLL_DP_Pos)); - //Enable PLL - RCC->CR |= RCC_CR_PLLON; - - //Wait till PLL is ready - while((RCC->CR & RCC_CR_PLLRDY) == 0) { - } - - //Select PLL as system clock source - RCC->CFGR &= (u32)((u32)~(RCC_CFGR_SW)); - RCC->CFGR |= (u32)RCC_CFGR_SW_PLL; - - //Wait till PLL is used as system clock source - while ((RCC->CFGR & (u32)RCC_CFGR_SWS) != (u32)0x08) { - } - } - else { - //If HSE fails to start-up, the application will have wrong clock - //configuration. User can add here some code to deal with this error - } -} -#elif defined SYSCLK_FREQ_36MHz - -/// @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 -/// and PCLK1 prescalers. -/// @note This function should be used only after reset. -/// @param None -/// @retval None - -static void SetSysClockTo36(void) -{ - s32 i; - __IO u32 StartUpCounter = 0, HSEStatus = 0; - - //SYSCLK, HCLK, PCLK2 and PCLK1 configuration --------------------------- - //Enable HSE - RCC->CR |= ((u32)RCC_CR_HSEON); - - //Wait till HSE is ready and if Time out is reached exit - do { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) { - HSEStatus = (u32)0x01; - i = 2000; - while(i--); - } - else { - HSEStatus = (u32)0x00; - } - - if (HSEStatus == (u32)0x01) { - //Enable Prefetch Buffer - FLASH->ACR |= FLASH_ACR_PRFTBE; - - //Flash 0 wait state ,bit0~2 - FLASH->ACR &= ~0x07; - FLASH->ACR |= 0x01; - //HCLK = SYSCLK - RCC->CFGR |= (u32)RCC_CFGR_HPRE_DIV1; - - //PCLK2 = HCLK - RCC->CFGR |= (u32)RCC_CFGR_PPRE2_DIV1; - - //PCLK1 = HCLK - RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV1; - RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ; - RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC ; - - RCC->APB1ENR |= RCC_APB1ENR_PWR; - RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP)); - RCC->PLLCFGR |= ((1 << RCC_PLLCFGR_PLL_DN_Pos) | (8 << RCC_PLLCFGR_PLL_DP_Pos)); - //Enable PLL - RCC->CR |= RCC_CR_PLLON; - - //Wait till PLL is ready - while((RCC->CR & RCC_CR_PLLRDY) == 0) { - } - - //Select PLL as system clock source - RCC->CFGR &= (u32)((u32)~(RCC_CFGR_SW)); - RCC->CFGR |= (u32)RCC_CFGR_SW_PLL; - - //Wait till PLL is used as system clock source - while ((RCC->CFGR & (u32)RCC_CFGR_SWS) != (u32)0x08) { - } - } - else { - //If HSE fails to start-up, the application will have wrong clock - //configuration. User can add here some code to deal with this error - } -} -#elif defined SYSCLK_FREQ_48MHz - -/// @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 -/// and PCLK1 prescalers. -/// @note This function should be used only after reset. -/// @param None -/// @retval None - -static void SetSysClockTo48(void) -{ - __IO u32 StartUpCounter = 0, HSEStatus = 0; - s32 i; - //SYSCLK, HCLK, PCLK2 and PCLK1 configuration --------------------------- - //Enable HSE - RCC->CR |= ((u32)RCC_CR_HSEON); - - //Wait till HSE is ready and if Time out is reached exit - do { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) { - HSEStatus = (u32)0x01; - i = 2000; - while(i--); - } - else { - HSEStatus = (u32)0x00; - } - - if (HSEStatus == (u32)0x01) { - //Enable Prefetch Buffer - FLASH->ACR |= FLASH_ACR_PRFTBE; - //Flash 0 wait state ,bit0~2 - FLASH->ACR &= ~0x07; - FLASH->ACR |= 0x02; - //HCLK = SYSCLK - RCC->CFGR |= (u32)RCC_CFGR_HPRE_DIV1; - - //PCLK2 = HCLK - RCC->CFGR |= (u32)RCC_CFGR_PPRE2_DIV1; - - //PCLK1 = HCLK - RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV2; - - // PLL configuration: = (HSE ) * (5+1) = 48MHz - RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ; - RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC ; - - RCC->APB1ENR |= RCC_APB1ENR_PWR; - RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP)); - RCC->PLLCFGR |= ((0 << RCC_PLLCFGR_PLL_DN_Pos) | (5 << RCC_PLLCFGR_PLL_DP_Pos)); - //Enable PLL - RCC->CR |= RCC_CR_PLLON; - - //Wait till PLL is ready - while((RCC->CR & RCC_CR_PLLRDY) == 0) { - } - - //Select PLL as system clock source - RCC->CFGR &= (u32)((u32)~(RCC_CFGR_SW)); - RCC->CFGR |= (u32)RCC_CFGR_SW_PLL; - - //Wait till PLL is used as system clock source - while ((RCC->CFGR & (u32)RCC_CFGR_SWS) != (u32)0x08) { - } - } - else { - //If HSE fails to start-up, the application will have wrong clock - //configuration. User can add here some code to deal with this error - } -} -#elif defined SYSCLK_FREQ_XXMHz - -/// @brief Sets System clock frequency to XXMHz and configure HCLK, PCLK2 -/// and PCLK1 prescalers. -/// @note This function should be used only after reset. -/// @param None -/// @retval None - -static void SetSysClockToXX(void) -{ - __IO u32 temp, tn, tm;//j, - __IO u32 StartUpCounter = 0, HSEStatus = 0; - - u8 plln, pllm; - - RCC->CR |= RCC_CR_HSION; - while(!(RCC->CR & RCC_CR_HSIRDY)); - //PLL SYSCLK, HCLK, PCLK2 and PCLK1 configuration --------------------------- - //Enable HSE - RCC->CR |= ((u32)RCC_CR_HSEON); - - DELAY_xUs(5); - - if(SystemCoreClock > 96000000) { - RCC->APB1ENR |= RCC_APB1ENR_PWR; - PWR->CR &= ~(3 << 14); - PWR->CR |= 3 << 14; - } - //Wait till HSE is ready and if Time out is reached exit - while(1) { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - if(HSEStatus != 0) - break; - StartUpCounter++; - if(StartUpCounter >= (10 * HSE_STARTUP_TIMEOUT)) - return; - } - - if ((RCC->CR & RCC_CR_HSERDY) == RESET) { - //If HSE fails to start-up, the application will have wrong clock - //configuration. User can add here some code to deal with this error - HSEStatus = (u32)0x00; - return; - } - - HSEStatus = (u32)0x01; - DELAY_xUs(5); - - SystemCoreClock = SYSCLK_FREQ_XXMHz; - //Enable Prefetch Buffer - FLASH->ACR |= FLASH_ACR_PRFTBE; - //Flash 0 wait state ,bit0~2 - FLASH->ACR &= ~FLASH_ACR_LATENCY; - temp = (SystemCoreClock - 1) / 24000000; - FLASH->ACR |= (temp & FLASH_ACR_LATENCY); - RCC->CFGR &= (~RCC_CFGR_HPRE) & ( ~RCC_CFGR_PPRE1) & (~RCC_CFGR_PPRE2); - - //HCLK = AHB = FCLK = SYSCLK divided by 4 - RCC->CFGR |= (u32)RCC_CFGR_HPRE_DIV4; - - //PCLK2 = APB2 = HCLK divided by 1, APB2 is high APB CLK - RCC->CFGR |= (u32)RCC_CFGR_PPRE2_DIV1; - - if(SystemCoreClock > 72000000) { - //PCLK1 = APB1 = HCLK divided by 4, APB1 is low APB CLK - RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV4; - } - else if(SystemCoreClock > 36000000) { - //PCLK1 = APB1 = HCLK divided by 2, APB1 is low APB CLK - RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV2; - } - - AutoCalPllFactor(HSE_VALUE, SystemCoreClock, &plln, &pllm); - - RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ; - RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC ; - - tm = (((u32)pllm) & 0x07); - tn = (((u32)plln) & 0x7F); - - RCC->APB1ENR |= RCC_APB1ENR_PWR; - RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP)); - RCC->PLLCFGR |= ((tn << RCC_PLLCFGR_PLL_DN_Pos) | (tm << RCC_PLLCFGR_PLL_DP_Pos)); - //Enable PLL - RCC->CR |= RCC_CR_PLLON; - //Wait till PLL is ready - while((RCC->CR & RCC_CR_PLLRDY) == 0) { - __ASM ("nop") ;//__NOP(); - } - //Select PLL as system clock source - RCC->CFGR &= (u32)((u32)~(RCC_CFGR_SW)); - RCC->CFGR |= (u32)RCC_CFGR_SW_PLL; - - //Wait till PLL is used as system clock source - while ((RCC->CFGR & (u32)RCC_CFGR_SWS) != (u32)RCC_CFGR_SWS_PLL) { - __ASM ("nop") ;//__NOP(); - } - - DELAY_xUs(1); - // set HCLK = AHB = FCLK = SYSCLK divided by 2 - RCC->CFGR &= (~(RCC_CFGR_PPRE_0)); - DELAY_xUs(1); - - // set HCLK = AHB = FCLK = SYSCLK divided by 1 - RCC->CFGR &= (~(RCC_CFGR_PPRE_3)); - - DELAY_xUs(1); - -} -#elif defined SYSCLK_HSI_24MHz -void SetSysClockTo24_HSI(void) -{ - u8 temp = 0; - - RCC->CR |= RCC_CR_HSION; - - while(!(RCC->CR & RCC_CR_HSIRDY)); - FLASH->ACR = FLASH_ACR_PRFTBE; - - RCC->CFGR = RCC_CFGR_PPRE1_2; - // PLL configuration: = (HSI = 8M ) * (2+1)/(0+1) = 24 MHz - RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ; - RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC ; - - RCC->APB1ENR |= RCC_APB1ENR_PWR; - RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP)); - RCC->PLLCFGR |= ((0 << RCC_PLLCFGR_PLL_DN_Pos) | (2 << RCC_PLLCFGR_PLL_DP_Pos)); - - - RCC->CR |= RCC_CR_PLLON; - - while(!(RCC->CR & RCC_CR_PLLRDY)); - - RCC->CFGR &= ~RCC_CFGR_SW; - - RCC->CFGR |= RCC_CFGR_SW_PLL; - - while(temp != 0x02) { - temp = RCC->CFGR >> 2; - temp &= 0x03; - } -} - -#elif defined SYSCLK_HSI_36MHz -void SetSysClockTo36_HSI(void) -{ - u8 temp = 0; - - RCC->CR |= RCC_CR_HSION; - - while(!(RCC->CR & RCC_CR_HSIRDY)); - FLASH->ACR = FLASH_ACR_LATENCY_1 | FLASH_ACR_PRFTBE; - RCC->CFGR = RCC_CFGR_PPRE1_2; - // PLL configuration: = (HSI = 8M ) * (8+1)/(1+1) = 36 MHz - RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ; - RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC ; - - RCC->APB1ENR |= RCC_APB1ENR_PWR; - RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP)); - RCC->PLLCFGR |= ((1 << RCC_PLLCFGR_PLL_DN_Pos) | (8 << RCC_PLLCFGR_PLL_DP_Pos)); - - RCC->CR |= RCC_CR_PLLON; - - while(!(RCC->CR & RCC_CR_PLLRDY)); - - RCC->CFGR &= ~ RCC_CFGR_SW; - - RCC->CFGR |= RCC_CFGR_SW_PLL; - - while(temp != 0x02) { - temp = RCC->CFGR >> 2; - temp &= 0x03; - } -} - -#elif defined SYSCLK_HSI_48MHz -void SetSysClockTo48_HSI(void) -{ - u8 temp = 0; - - RCC->CR |= RCC_CR_HSION; - - while(!(RCC->CR & RCC_CR_HSIRDY)); - FLASH->ACR = FLASH_ACR_LATENCY_1 | FLASH_ACR_PRFTBE; - RCC->CFGR = RCC_CFGR_PPRE1_2; - - - - - - // PLL configuration: = (HSI = 8M ) * (5+1)/(0+1) = 36 MHz - RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ; - RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC ; - - RCC->APB1ENR |= RCC_APB1ENR_PWR; - RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP)); - RCC->PLLCFGR |= ((0 << RCC_PLLCFGR_PLL_DN_Pos) | (5 << RCC_PLLCFGR_PLL_DP_Pos)); - - RCC->CR |= RCC_CR_PLLON; - - while(!(RCC->CR & RCC_CR_PLLRDY)); - - RCC->CFGR &= ~RCC_CFGR_SW; - - RCC->CFGR |= RCC_CFGR_SW_PLL; - - while(temp != 0x02) { - temp = RCC->CFGR >> 2; - temp &= 0x03; - } -} -#elif defined SYSCLK_HSI_XXMHz - - -static void SetSysClockToXX_HSI(void) -{ - __IO u32 temp, tn, tm; - u8 plln, pllm; - - RCC->CR |= RCC_CR_HSION; - while(!(RCC->CR & RCC_CR_HSIRDY)); - - if(SystemCoreClock > 96000000) { - RCC->APB1ENR |= RCC_APB1ENR_PWR; - PWR->CR &= ~(3 << 14); - PWR->CR |= 3 << 14; - } - - - - SystemCoreClock = SYSCLK_HSI_XXMHz; - //Enable Prefetch Buffer - FLASH->ACR |= FLASH_ACR_PRFTBE; - //Flash 0 wait state ,bit0~2 - FLASH->ACR &= ~FLASH_ACR_LATENCY; - - temp = (SystemCoreClock - 1) / 24000000; - - FLASH->ACR |= (temp & FLASH_ACR_LATENCY); - - - RCC->CFGR &= (~RCC_CFGR_HPRE) & ( ~RCC_CFGR_PPRE1) & (~RCC_CFGR_PPRE2); - //HCLK = AHB = FCLK = SYSCLK divided by 4 - RCC->CFGR |= (u32)RCC_CFGR_HPRE_DIV4; - - //PCLK2 = APB2 = HCLK divided by 1, APB2 is high APB CLK - RCC->CFGR |= (u32)RCC_CFGR_PPRE2_DIV1; - - if(SystemCoreClock > 72000000) { - //PCLK1 = APB1 = HCLK divided by 4, APB1 is low APB CLK - RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV4; - } - else if(SystemCoreClock > 36000000) { - //PCLK1 = APB1 = HCLK divided by 2, APB1 is low APB CLK - RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV2; - } - - - - AutoCalPllFactor(HSI_VALUE_PLL_ON, SystemCoreClock, &plln, &pllm); - - RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ; - RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC); - - tm = (((u32)pllm) & 0x07); - tn = (((u32)plln) & 0x7F); - - RCC->APB1ENR |= RCC_APB1ENR_PWR; - RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP)); - RCC->PLLCFGR |= ((tn << RCC_PLLCFGR_PLL_DN_Pos) | (tm << RCC_PLLCFGR_PLL_DP_Pos)); - //Enable PLL - RCC->CR |= RCC_CR_PLLON; - //Wait till PLL is ready - while((RCC->CR & RCC_CR_PLLRDY) == 0) { - __ASM ("nop") ;//__NOP(); - } - //Select PLL as system clock source - RCC->CFGR &= (u32)((u32)~(RCC_CFGR_SW)); - RCC->CFGR |= (u32)RCC_CFGR_SW_PLL; - - //Wait till PLL is used as system clock source - while ((RCC->CFGR & (u32)RCC_CFGR_SWS) != (u32)RCC_CFGR_SWS_PLL) { - __ASM ("nop") ;//__NOP(); - } - - DELAY_xUs(1); - // set HCLK = AHB = FCLK = SYSCLK divided by 2 - RCC->CFGR &= (~(RCC_CFGR_PPRE_0)); - DELAY_xUs(1); - - // set HCLK = AHB = FCLK = SYSCLK divided by 1 - RCC->CFGR &= (~(RCC_CFGR_PPRE_3)); - - DELAY_xUs(1); - -} - -#endif - - - -/// @} - - - -/// @} - - - -/// @} - - - -- cgit v1.3.1 From 7b27607f1ae68b1348e12e3fb0264474bb825f9e Mon Sep 17 00:00:00 2001 From: zhangslice <1304224508@qq.com> Date: Mon, 7 Jun 2021 16:58:27 +0800 Subject: mit license Signed-off-by: zhangslice <1304224508@qq.com> --- src/portable/mm32/dcd_mm32f327x_otg.c | 41 +++++++++++++++++++++-------------- 1 file changed, 25 insertions(+), 16 deletions(-) diff --git a/src/portable/mm32/dcd_mm32f327x_otg.c b/src/portable/mm32/dcd_mm32f327x_otg.c index 914bbb38c..e7518830e 100644 --- a/src/portable/mm32/dcd_mm32f327x_otg.c +++ b/src/portable/mm32/dcd_mm32f327x_otg.c @@ -1,19 +1,28 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file dcd_mm32f327x_otg.c -/// @author SE TEAM -/// @brief tinyusb driver. -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// +/* + * The MIT License (MIT) + * + * Copyright (c) 2020 SE TEAM + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ #include "tusb_option.h" #include "reg_usb_otg_fs.h" -- cgit v1.3.1 From 85f8047ac4f9bfd08e04d29b5c294c8a4547f94c Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 7 Jun 2021 17:09:22 +0700 Subject: remove the keil zip --- tinyusb_keil.zip | Bin 1001190 -> 0 bytes 1 file changed, 0 insertions(+), 0 deletions(-) delete mode 100644 tinyusb_keil.zip diff --git a/tinyusb_keil.zip b/tinyusb_keil.zip deleted file mode 100644 index 6b178fcfc..000000000 Binary files a/tinyusb_keil.zip and /dev/null differ -- cgit v1.3.1 From 0ae83458d517777c9f37857a182b0553dd647ffe Mon Sep 17 00:00:00 2001 From: zhangslice <1304224508@qq.com> Date: Thu, 17 Jun 2021 17:11:37 +0800 Subject: dsp updata Signed-off-by: zhangslice <1304224508@qq.com> --- hw/bsp/mm32/mm32f327x/flash.ld | 163 +++++++++++++++++++++++++++++++++ hw/bsp/mm32/mm32f327x/mm32f327x_mb39.c | 161 ++++++++++++++++++++++++++++++++ 2 files changed, 324 insertions(+) create mode 100644 hw/bsp/mm32/mm32f327x/flash.ld create mode 100644 hw/bsp/mm32/mm32f327x/mm32f327x_mb39.c diff --git a/hw/bsp/mm32/mm32f327x/flash.ld b/hw/bsp/mm32/mm32f327x/flash.ld new file mode 100644 index 000000000..d96d6e43d --- /dev/null +++ b/hw/bsp/mm32/mm32f327x/flash.ld @@ -0,0 +1,163 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020 MM32 SE TEAM + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x2001FFFF; /* end of RAM */ + +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/hw/bsp/mm32/mm32f327x/mm32f327x_mb39.c b/hw/bsp/mm32/mm32f327x/mm32f327x_mb39.c new file mode 100644 index 000000000..39b264b70 --- /dev/null +++ b/hw/bsp/mm32/mm32f327x/mm32f327x_mb39.c @@ -0,0 +1,161 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020 MM32 SE TEAM + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "mm32_device.h" +#include "hal_conf.h" +#include "tusb.h" +#include "../board.h" + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void OTG_FS_IRQHandler(void) +{ + dcd_int_handler(TUD_OPT_RHPORT); + +} +void USB_DeviceClockInit(void) +{ + /* Select USBCLK source */ + // RCC_USBCLKConfig(RCC_USBCLKSource_PLLCLK_Div1); + RCC->CFGR &= ~(0x3 << 22); + RCC->CFGR |= (0x1 << 22); + + /* Enable USB clock */ + RCC->AHB2ENR |= 0x1 << 7; +} +//--------------------------------------------------------------------+ +// MACRO TYPEDEF CONSTANT ENUM DECLARATION +//--------------------------------------------------------------------+ +// LED + +void board_led_write(bool state); +extern u32 SystemCoreClock; +const int baudrate = 115200; + +void board_init(void) +{ +// usb clock + USB_DeviceClockInit(); + + if (SysTick_Config(SystemCoreClock / 1000)) { + while (1); + } + NVIC_SetPriority(SysTick_IRQn, 0x0); + + // LED + GPIO_InitTypeDef GPIO_InitStruct; + RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOA, ENABLE); + GPIO_StructInit(&GPIO_InitStruct); + GPIO_PinAFConfig(GPIOA, GPIO_PinSource15, GPIO_AF_15); //Disable JTDI AF to AF15 + + GPIO_InitStruct.GPIO_Pin = GPIO_Pin_15; + GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStruct.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_Init(GPIOA, &GPIO_InitStruct); + + board_led_write(true); + + // UART + UART_InitTypeDef UART_InitStruct; + + RCC_APB2PeriphClockCmd(RCC_APB2ENR_UART1, ENABLE); //enableUART1,GPIOAclock + RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOA, ENABLE); // + //UART initialset + + GPIO_PinAFConfig(GPIOA, GPIO_PinSource9, GPIO_AF_7); + GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_7); + + + UART_StructInit(&UART_InitStruct); + UART_InitStruct.UART_BaudRate = baudrate; + UART_InitStruct.UART_WordLength = UART_WordLength_8b; + UART_InitStruct.UART_StopBits = UART_StopBits_1;//one stopbit + UART_InitStruct.UART_Parity = UART_Parity_No;//none odd-even verify bit + UART_InitStruct.UART_HardwareFlowControl = UART_HardwareFlowControl_None;//No hardware flow control + UART_InitStruct.UART_Mode = UART_Mode_Rx | UART_Mode_Tx; // receive and sent mode + + UART_Init(UART1, &UART_InitStruct); //initial uart 1 + UART_Cmd(UART1, ENABLE); //enable uart 1 + + //UART1_TX GPIOA.9 + GPIO_StructInit(&GPIO_InitStruct); + GPIO_InitStruct.GPIO_Pin = GPIO_Pin_9; + GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOA, &GPIO_InitStruct); + + //UART1_RX GPIOA.10 + GPIO_InitStruct.GPIO_Pin = GPIO_Pin_5; + GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOA, &GPIO_InitStruct); + +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +void board_led_write(bool state) +{ + state ? (GPIO_ResetBits(GPIOA,GPIO_Pin_15)):(GPIO_SetBits(GPIOA,GPIO_Pin_15)); +} + +uint32_t board_button_read(void) +{ + return 0; +} + +int board_uart_read(uint8_t* buf, int len) +{ + (void) buf; (void) len; + return 0; +} + +int board_uart_write(void const * buf, int len) +{ + const char *buff = buf; + while(len){ + while((UART1->CSR & UART_IT_TXIEN) == 0); //The loop is sent until it is finished + UART1->TDR = (*buff & 0xFF); + buff++; + len--; + } + return len; +} + +#if CFG_TUSB_OS == OPT_OS_NONE +volatile uint32_t system_ticks = 0; +void SysTick_Handler(void) +{ + system_ticks++; +} + +uint32_t board_millis(void) +{ + return system_ticks; +} +#endif -- cgit v1.3.1 From 5006b1065a21099d3c62bf2ea3ecf6c1e82d2723 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 18 Jun 2021 12:49:41 +0700 Subject: remove duplicate mm32 dcd --- src/portable/mm32/dcd_mm32f327x_otg.c | 471 ---------------------------------- 1 file changed, 471 deletions(-) delete mode 100644 src/portable/mm32/dcd_mm32f327x_otg.c diff --git a/src/portable/mm32/dcd_mm32f327x_otg.c b/src/portable/mm32/dcd_mm32f327x_otg.c deleted file mode 100644 index e7518830e..000000000 --- a/src/portable/mm32/dcd_mm32f327x_otg.c +++ /dev/null @@ -1,471 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2020 SE TEAM - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#include "tusb_option.h" -#include "reg_usb_otg_fs.h" -#include "mm32_device.h" -#include "hal_conf.h" - -#if TUSB_OPT_DEVICE_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_MM32F327X ) - -#include "device/dcd.h" - -//--------------------------------------------------------------------+ -// MACRO TYPEDEF CONSTANT ENUM DECLARATION -//--------------------------------------------------------------------+ - -enum { - TOK_PID_OUT = 0x1u, - TOK_PID_IN = 0x9u, - TOK_PID_SETUP = 0xDu, -}; - -typedef struct TU_ATTR_PACKED -{ - union { - uint32_t head; - struct { - union { - struct { - uint16_t : 2; - uint16_t tok_pid : 4; - uint16_t data : 1; - uint16_t own : 1; - uint16_t : 8; - }; - struct { - uint16_t : 2; - uint16_t bdt_stall: 1; - uint16_t dts : 1; - uint16_t ninc : 1; - uint16_t keep : 1; - uint16_t : 10; - }; - }; - uint16_t bc : 10; - uint16_t : 6; - }; - }; - uint8_t *addr; -}buffer_descriptor_t; - -TU_VERIFY_STATIC( sizeof(buffer_descriptor_t) == 8, "size is not correct" ); - -typedef struct TU_ATTR_PACKED -{ - union { - uint32_t state; - struct { - uint32_t max_packet_size :11; - uint32_t : 5; - uint32_t odd : 1; - uint32_t :15; - }; - }; - uint16_t length; - uint16_t remaining; -}endpoint_state_t; - -TU_VERIFY_STATIC( sizeof(endpoint_state_t) == 8, "size is not correct" ); - -typedef struct -{ - union { - /* [#EP][OUT,IN][EVEN,ODD] */ - buffer_descriptor_t bdt[16][2][2]; - uint16_t bda[512]; - }; - TU_ATTR_ALIGNED(4) union { - endpoint_state_t endpoint[16][2]; - endpoint_state_t endpoint_unified[16 * 2]; - }; - uint8_t setup_packet[8]; - uint8_t addr; -}dcd_data_t; - -//--------------------------------------------------------------------+ -// INTERNAL OBJECT & FUNCTION DECLARATION -//--------------------------------------------------------------------+ -// BDT(Buffer Descriptor Table) must be 256-byte aligned -CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(512) static dcd_data_t _dcd; - -TU_VERIFY_STATIC( sizeof(_dcd.bdt) == 512, "size is not correct" ); - -static void prepare_next_setup_packet(uint8_t rhport) -{ - const unsigned out_odd = _dcd.endpoint[0][0].odd; - const unsigned in_odd = _dcd.endpoint[0][1].odd; - if (_dcd.bdt[0][0][out_odd].own) { - TU_LOG1("DCD fail to prepare the next SETUP %d %d\r\n", out_odd, in_odd); - return; - } - _dcd.bdt[0][0][out_odd].data = 0; - _dcd.bdt[0][0][out_odd ^ 1].data = 1; - _dcd.bdt[0][1][in_odd].data = 1; - _dcd.bdt[0][1][in_odd ^ 1].data = 0; - dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_OUT), - _dcd.setup_packet, sizeof(_dcd.setup_packet)); -} - -static void process_stall(uint8_t rhport) -{ - if (USB_OTG_FS->EP_CTL[0] & USB_ENDPT_EPSTALL_MASK) { - /* clear stall condition of the control pipe */ - prepare_next_setup_packet(rhport); - USB_OTG_FS->EP_CTL[0] &= ~USB_ENDPT_EPSTALL_MASK; - } -} - -static void process_tokdne(uint8_t rhport) -{ - const unsigned s = USB_OTG_FS->STAT; - USB_OTG_FS->INT_STAT = USB_ISTAT_TOKDNE_MASK; /* fetch the next token if received */ - buffer_descriptor_t *bd = (buffer_descriptor_t *)&_dcd.bda[s]; - endpoint_state_t *ep = &_dcd.endpoint_unified[s >> 3]; - unsigned odd = (s & USB_STAT_ODD_MASK) ? 1 : 0; - - /* fetch pid before discarded by the next steps */ - const unsigned pid = bd->tok_pid; - /* reset values for a next transfer */ - bd->bdt_stall = 0; - bd->dts = 1; - bd->ninc = 0; - bd->keep = 0; - /* update the odd variable to prepare for the next transfer */ - ep->odd = odd ^ 1; - if (pid == TOK_PID_SETUP) { - dcd_event_setup_received(rhport, bd->addr, true); - USB_OTG_FS->CTL &= ~USB_CTL_TXSUSPENDTOKENBUSY_MASK; - return; - } - if (s >> 4) { - TU_LOG1("TKDNE %x\r\n", s); - } - - const unsigned bc = bd->bc; - const unsigned remaining = ep->remaining - bc; - if (remaining && bc == ep->max_packet_size) { - /* continue the transferring consecutive data */ - ep->remaining = remaining; - const int next_remaining = remaining - ep->max_packet_size; - if (next_remaining > 0) { - /* prepare to the after next transfer */ - bd->addr += ep->max_packet_size * 2; - bd->bc = next_remaining > ep->max_packet_size ? ep->max_packet_size: next_remaining; - __DSB(); - bd->own = 1; /* the own bit must set after addr */ - } - return; - } - const unsigned length = ep->length; - dcd_event_xfer_complete(rhport, - ((s & USB_STAT_TX_MASK) << 4) | (s >> USB_STAT_ENDP_SHIFT), - length - remaining, XFER_RESULT_SUCCESS, true); - if (0 == (s & USB_STAT_ENDP_MASK) && 0 == length) { - /* After completion a ZLP of control transfer, - * it prepares for the next steup transfer. */ - if (_dcd.addr) { - /* When the transfer was the SetAddress, - * the device address should be updated here. */ - USB_OTG_FS->ADDR = _dcd.addr; - _dcd.addr = 0; - } - prepare_next_setup_packet(rhport); - } -} - -static void process_bus_reset(uint8_t rhport) -{ - USB_OTG_FS->CTL |= USB_CTL_ODDRST_MASK; - USB_OTG_FS->ADDR = 0; - USB_OTG_FS->INT_ENB = (USB_OTG_FS->INT_ENB & ~USB_INTEN_RESUMEEN_MASK) | USB_INTEN_SLEEPEN_MASK; - - USB_OTG_FS->EP_CTL[0] = USB_ENDPT_EPHSHK_MASK | USB_ENDPT_EPRXEN_MASK | USB_ENDPT_EPTXEN_MASK; - for (unsigned i = 1; i < 16; ++i) { - USB_OTG_FS->EP_CTL[i] = 0; - } - buffer_descriptor_t *bd = _dcd.bdt[0][0]; - for (unsigned i = 0; i < sizeof(_dcd.bdt)/sizeof(*bd); ++i, ++bd) { - bd->head = 0; - } - const endpoint_state_t ep0 = { - .max_packet_size = CFG_TUD_ENDPOINT0_SIZE, - .odd = 0, - .length = 0, - .remaining = 0, - }; - _dcd.endpoint[0][0] = ep0; - _dcd.endpoint[0][1] = ep0; - tu_memclr(_dcd.endpoint[1], sizeof(_dcd.endpoint) - sizeof(_dcd.endpoint[0])); - _dcd.addr = 0; - prepare_next_setup_packet(rhport); - USB_OTG_FS->CTL &= ~USB_CTL_ODDRST_MASK; - dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true); -} - -static void process_bus_inactive(uint8_t rhport) -{ - (void) rhport; - const unsigned inten = USB_OTG_FS->INT_ENB; - USB_OTG_FS->INT_ENB = (inten & ~USB_INTEN_SLEEPEN_MASK) | USB_INTEN_RESUMEEN_MASK; - dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); -} - -static void process_bus_active(uint8_t rhport) -{ - (void) rhport; - const unsigned inten = USB_OTG_FS->INT_ENB; - USB_OTG_FS->INT_ENB = (inten & ~USB_INTEN_RESUMEEN_MASK) | USB_INTEN_SLEEPEN_MASK; - dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true); -} - -/*------------------------------------------------------------------*/ -/* Device API - *------------------------------------------------------------------*/ -void dcd_init(uint8_t rhport) -{ - (void) rhport; - - tu_memclr(&_dcd, sizeof(_dcd)); - USB_OTG_FS->BDT_PAGE_01 = (uint8_t)((uintptr_t)_dcd.bdt >> 8); - USB_OTG_FS->BDT_PAGE_02 = (uint8_t)((uintptr_t)_dcd.bdt >> 16); - USB_OTG_FS->BDT_PAGE_03 = (uint8_t)((uintptr_t)_dcd.bdt >> 24); - - dcd_connect(rhport); - NVIC_ClearPendingIRQ(USB_FS_IRQn); -} -#define USB_DEVICE_INTERRUPT_PRIORITY (3U) -void dcd_int_enable(uint8_t rhport) -{ - uint8_t irqNumber; - irqNumber = USB_FS_IRQn; - (void) rhport; - USB_OTG_FS->INT_ENB = USB_INTEN_USBRSTEN_MASK | USB_INTEN_TOKDNEEN_MASK | - USB_INTEN_SLEEPEN_MASK | USB_INTEN_ERROREN_MASK | USB_INTEN_STALLEN_MASK; - NVIC_SetPriority((IRQn_Type)irqNumber, USB_DEVICE_INTERRUPT_PRIORITY); - NVIC_EnableIRQ(USB_FS_IRQn); -} - -void dcd_int_disable(uint8_t rhport) -{ - (void) rhport; - NVIC_DisableIRQ(USB_FS_IRQn); - USB_OTG_FS->INT_ENB = 0; -} - -void dcd_set_address(uint8_t rhport, uint8_t dev_addr) -{ - (void) rhport; - _dcd.addr = dev_addr & 0x7F; - /* Response with status first before changing device address */ - dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0); -} -extern u32 SystemCoreClock ; -void dcd_remote_wakeup(uint8_t rhport) -{ - (void) rhport; - unsigned cnt = SystemCoreClock / 100; - USB_OTG_FS->CTL |= USB_CTL_RESUME_MASK; - while (cnt--) __NOP(); - USB_OTG_FS->CTL &= ~USB_CTL_RESUME_MASK; -} - -void dcd_connect(uint8_t rhport) -{ - (void) rhport; - USB_OTG_FS->CTL |= USB_CTL_USBENSOFEN_MASK; -} - -void dcd_disconnect(uint8_t rhport) -{ - (void) rhport; - USB_OTG_FS->CTL = 0; -} - -//--------------------------------------------------------------------+ -// Endpoint API -//--------------------------------------------------------------------+ -bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) -{ - (void) rhport; - - const unsigned ep_addr = ep_desc->bEndpointAddress; - const unsigned epn = ep_addr & 0xFu; - const unsigned dir = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT; - const unsigned xfer = ep_desc->bmAttributes.xfer; - endpoint_state_t *ep = &_dcd.endpoint[epn][dir]; - const unsigned odd = ep->odd; - buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][0]; - - /* No support for control transfer */ - TU_ASSERT(epn && (xfer != TUSB_XFER_CONTROL)); - - ep->max_packet_size = ep_desc->wMaxPacketSize.size; - unsigned val = USB_ENDPT_EPCTLDIS_MASK; - val |= (xfer != TUSB_XFER_ISOCHRONOUS) ? USB_ENDPT_EPHSHK_MASK: 0; - val |= dir ? USB_ENDPT_EPTXEN_MASK : USB_ENDPT_EPRXEN_MASK; - USB_OTG_FS->EP_CTL[epn] |= val; - - if (xfer != TUSB_XFER_ISOCHRONOUS) { - bd[odd].dts = 1; - bd[odd].data = 0; - bd[odd ^ 1].dts = 1; - bd[odd ^ 1].data = 1; - } - - return true; -} - -void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) -{ - (void) rhport; - - const unsigned epn = ep_addr & 0xFu; - const unsigned dir = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT; - endpoint_state_t *ep = &_dcd.endpoint[epn][dir]; - buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][0]; - const unsigned msk = dir ? USB_ENDPT_EPTXEN_MASK : USB_ENDPT_EPRXEN_MASK; - USB_OTG_FS->EP_CTL[epn] &= ~msk; - ep->max_packet_size = 0; - ep->length = 0; - ep->remaining = 0; - bd->head = 0; -} - -bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) -{ - (void) rhport; - NVIC_DisableIRQ(USB_FS_IRQn); - const unsigned epn = ep_addr & 0xFu; - const unsigned dir = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT; - endpoint_state_t *ep = &_dcd.endpoint[epn][dir]; - buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][ep->odd]; - - if (bd->own) { - TU_LOG1("DCD XFER fail %x %d %lx %lx\r\n", ep_addr, total_bytes, ep->state, bd->head); - return false; /* The last transfer has not completed */ - } - ep->length = total_bytes; - ep->remaining = total_bytes; - - const unsigned mps = ep->max_packet_size; - if (total_bytes > mps) { - buffer_descriptor_t *next = ep->odd ? bd - 1: bd + 1; - /* When total_bytes is greater than the max packet size, - * it prepares to the next transfer to avoid NAK in advance. */ - next->bc = total_bytes >= 2 * mps ? mps: total_bytes - mps; - next->addr = buffer + mps; - next->own = 1; - } - bd->bc = total_bytes >= mps ? mps: total_bytes; - bd->addr = buffer; - __DSB(); - bd->own = 1; /* the own bit must set after addr */ - NVIC_EnableIRQ(USB_FS_IRQn); - return true; -} - -void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) -{ - (void) rhport; - const unsigned epn = ep_addr & 0xFu; - if (0 == epn) { - USB_OTG_FS->EP_CTL[epn] |= USB_ENDPT_EPSTALL_MASK; - } else { - const unsigned dir = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT; - buffer_descriptor_t *bd = _dcd.bdt[epn][dir]; - bd[0].bdt_stall = 1; - bd[1].bdt_stall = 1; - } -} - -void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) -{ - (void) rhport; - const unsigned epn = ep_addr & 0xFu; - const unsigned dir = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT; - const unsigned odd = _dcd.endpoint[epn][dir].odd; - buffer_descriptor_t *bd = _dcd.bdt[epn][dir]; - - bd[odd ^ 1].own = 0; - bd[odd ^ 1].data = 1; - bd[odd ^ 1].bdt_stall = 0; - bd[odd].own = 0; - bd[odd].data = 0; - bd[odd].bdt_stall = 0; -} - -//--------------------------------------------------------------------+ -// ISR -//--------------------------------------------------------------------+ -void dcd_int_handler(uint8_t rhport) -{ - (void) rhport; - - uint32_t is = USB_OTG_FS->INT_STAT; - uint32_t msk = USB_OTG_FS->INT_ENB; - USB_OTG_FS->INT_STAT = is & ~msk; - is &= msk; - if (is & USB_ISTAT_ERROR_MASK) { - /* TODO: */ - uint32_t es = USB_OTG_FS->ERR_STAT; - USB_OTG_FS->ERR_STAT = es; - USB_OTG_FS->INT_STAT = is; /* discard any pending events */ - return; - } - - if (is & USB_ISTAT_USBRST_MASK) { - USB_OTG_FS->INT_STAT = is; /* discard any pending events */ - process_bus_reset(rhport); - return; - } - if (is & USB_ISTAT_SLEEP_MASK) { - USB_OTG_FS->INT_STAT = USB_ISTAT_SLEEP_MASK; - process_bus_inactive(rhport); - return; - } - if (is & USB_ISTAT_RESUME_MASK) { - USB_OTG_FS->INT_STAT = USB_ISTAT_RESUME_MASK; - process_bus_active(rhport); - return; - } - if (is & USB_ISTAT_SOFTOK_MASK) { - USB_OTG_FS->INT_STAT = USB_ISTAT_SOFTOK_MASK; - dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true); - return; - } - if (is & USB_ISTAT_STALL_MASK) { - USB_OTG_FS->INT_STAT = USB_ISTAT_STALL_MASK; - process_stall(rhport); - return; - } - if (is & USB_ISTAT_TOKDNE_MASK) { - process_tokdne(rhport); - return; - } -} - -#endif -- cgit v1.3.1 From 82618d2d5f15d0f8dd9631dec3807964a1281782 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 18 Jun 2021 17:18:11 +0700 Subject: fix build with mm32 board --- .../device/cdc_msc_freertos/src/FreeRTOSConfig.h | 5 + .../hid_composite_freertos/src/FreeRTOSConfig.h | 4 + hw/bsp/board_mcu.h | 2 + hw/bsp/mm32/boards/mm32f327x_mb39/board.mk | 8 + hw/bsp/mm32/boards/mm32f327x_mb39/flash.ld | 163 +++++++++++++++++++ hw/bsp/mm32/boards/mm32f327x_mb39/mm32f327x_mb39.c | 172 +++++++++++++++++++++ hw/bsp/mm32/family.mk | 36 +++++ hw/bsp/mm32/mm32f327x/flash.ld | 163 ------------------- hw/bsp/mm32/mm32f327x/mm32f327x_mb39.c | 161 ------------------- src/class/cdc/cdc_device.h | 6 +- src/class/vendor/vendor_device.h | 8 +- src/common/tusb_common.h | 32 ++-- src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c | 2 +- 13 files changed, 414 insertions(+), 348 deletions(-) create mode 100644 hw/bsp/mm32/boards/mm32f327x_mb39/board.mk create mode 100644 hw/bsp/mm32/boards/mm32f327x_mb39/flash.ld create mode 100644 hw/bsp/mm32/boards/mm32f327x_mb39/mm32f327x_mb39.c create mode 100644 hw/bsp/mm32/family.mk delete mode 100644 hw/bsp/mm32/mm32f327x/flash.ld delete mode 100644 hw/bsp/mm32/mm32f327x/mm32f327x_mb39.c diff --git a/examples/device/cdc_msc_freertos/src/FreeRTOSConfig.h b/examples/device/cdc_msc_freertos/src/FreeRTOSConfig.h index b76d59706..c9f553f64 100644 --- a/examples/device/cdc_msc_freertos/src/FreeRTOSConfig.h +++ b/examples/device/cdc_msc_freertos/src/FreeRTOSConfig.h @@ -45,7 +45,12 @@ // Include MCU header #include "bsp/board_mcu.h" +// TODO fix later +#if CFG_TUSB_MCU == OPT_MCU_MM32F327X +extern u32 SystemCoreClock; +#else extern uint32_t SystemCoreClock; +#endif /* Cortex M23/M33 port configuration. */ #define configENABLE_MPU 0 diff --git a/examples/device/hid_composite_freertos/src/FreeRTOSConfig.h b/examples/device/hid_composite_freertos/src/FreeRTOSConfig.h index b76d59706..99c5bc328 100644 --- a/examples/device/hid_composite_freertos/src/FreeRTOSConfig.h +++ b/examples/device/hid_composite_freertos/src/FreeRTOSConfig.h @@ -45,7 +45,11 @@ // Include MCU header #include "bsp/board_mcu.h" +#if CFG_TUSB_MCU == OPT_MCU_MM32F327X +extern u32 SystemCoreClock; +#else extern uint32_t SystemCoreClock; +#endif /* Cortex M23/M33 port configuration. */ #define configENABLE_MPU 0 diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h index 1a659c410..c9d143bd7 100644 --- a/hw/bsp/board_mcu.h +++ b/hw/bsp/board_mcu.h @@ -130,6 +130,8 @@ #elif CFG_TUSB_MCU == OPT_MCU_RX63X // no header needed +#elif CFG_TUSB_MCU == OPT_MCU_MM32F327X + #include "mm32_device.h" #else #error "Missing MCU header" #endif diff --git a/hw/bsp/mm32/boards/mm32f327x_mb39/board.mk b/hw/bsp/mm32/boards/mm32f327x_mb39/board.mk new file mode 100644 index 000000000..b7663926f --- /dev/null +++ b/hw/bsp/mm32/boards/mm32f327x_mb39/board.mk @@ -0,0 +1,8 @@ +LD_FILE = $(BOARD_PATH)/flash.ld +SRC_S += $(SDK_DIR)/mm32f327x/MM32F327x/Source/GCC_StartAsm/startup_mm32m3ux_u_gcc.S + +# For flash-jlink target +#JLINK_DEVICE = stm32f411ve + +# flash target using on-board stlink +#flash: flash-jlink diff --git a/hw/bsp/mm32/boards/mm32f327x_mb39/flash.ld b/hw/bsp/mm32/boards/mm32f327x_mb39/flash.ld new file mode 100644 index 000000000..d96d6e43d --- /dev/null +++ b/hw/bsp/mm32/boards/mm32f327x_mb39/flash.ld @@ -0,0 +1,163 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020 MM32 SE TEAM + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x2001FFFF; /* end of RAM */ + +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/hw/bsp/mm32/boards/mm32f327x_mb39/mm32f327x_mb39.c b/hw/bsp/mm32/boards/mm32f327x_mb39/mm32f327x_mb39.c new file mode 100644 index 000000000..cff7bc15e --- /dev/null +++ b/hw/bsp/mm32/boards/mm32f327x_mb39/mm32f327x_mb39.c @@ -0,0 +1,172 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020 MM32 SE TEAM + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "mm32_device.h" +#include "hal_conf.h" +#include "tusb.h" +#include "../board.h" + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void OTG_FS_IRQHandler (void) +{ + tud_int_handler(0); + +} +void USB_DeviceClockInit (void) +{ + /* Select USBCLK source */ + // RCC_USBCLKConfig(RCC_USBCLKSource_PLLCLK_Div1); + RCC->CFGR &= ~(0x3 << 22); + RCC->CFGR |= (0x1 << 22); + + /* Enable USB clock */ + RCC->AHB2ENR |= 0x1 << 7; +} +//--------------------------------------------------------------------+ +// MACRO TYPEDEF CONSTANT ENUM DECLARATION +//--------------------------------------------------------------------+ +// LED + +void board_led_write (bool state); +extern u32 SystemCoreClock; +const int baudrate = 115200; + +void board_init (void) +{ +// usb clock + USB_DeviceClockInit(); + + if ( SysTick_Config(SystemCoreClock / 1000) ) + { + while ( 1 ) + ; + } + NVIC_SetPriority(SysTick_IRQn, 0x0); + + // LED + GPIO_InitTypeDef GPIO_InitStruct; + RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOA, ENABLE); + GPIO_StructInit(&GPIO_InitStruct); + GPIO_PinAFConfig(GPIOA, GPIO_PinSource15, GPIO_AF_15); //Disable JTDI AF to AF15 + + GPIO_InitStruct.GPIO_Pin = GPIO_Pin_15; + GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStruct.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_Init(GPIOA, &GPIO_InitStruct); + + board_led_write(true); + + // UART + UART_InitTypeDef UART_InitStruct; + + RCC_APB2PeriphClockCmd(RCC_APB2ENR_UART1, ENABLE); //enableUART1,GPIOAclock + RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOA, ENABLE); // + //UART initialset + + GPIO_PinAFConfig(GPIOA, GPIO_PinSource9, GPIO_AF_7); + GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_7); + + UART_StructInit(&UART_InitStruct); + UART_InitStruct.UART_BaudRate = baudrate; + UART_InitStruct.UART_WordLength = UART_WordLength_8b; + UART_InitStruct.UART_StopBits = UART_StopBits_1; //one stopbit + UART_InitStruct.UART_Parity = UART_Parity_No; //none odd-even verify bit + UART_InitStruct.UART_HardwareFlowControl = UART_HardwareFlowControl_None; //No hardware flow control + UART_InitStruct.UART_Mode = UART_Mode_Rx | UART_Mode_Tx; // receive and sent mode + + UART_Init(UART1, &UART_InitStruct); //initial uart 1 + UART_Cmd(UART1, ENABLE); //enable uart 1 + + //UART1_TX GPIOA.9 + GPIO_StructInit(&GPIO_InitStruct); + GPIO_InitStruct.GPIO_Pin = GPIO_Pin_9; + GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOA, &GPIO_InitStruct); + + //UART1_RX GPIOA.10 + GPIO_InitStruct.GPIO_Pin = GPIO_Pin_5; + GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOA, &GPIO_InitStruct); + +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +void board_led_write (bool state) +{ + state ? (GPIO_ResetBits(GPIOA, GPIO_Pin_15)) : (GPIO_SetBits(GPIOA, GPIO_Pin_15)); +} + +uint32_t board_button_read (void) +{ + return 0; +} + +int board_uart_read (uint8_t *buf, int len) +{ + (void) buf; + (void) len; + return 0; +} + +int board_uart_write (void const *buf, int len) +{ + const char *buff = buf; + while ( len ) + { + while ( (UART1->CSR & UART_IT_TXIEN) == 0 ) + ; //The loop is sent until it is finished + UART1->TDR = (*buff & 0xFF); + buff++; + len--; + } + return len; +} + +#if CFG_TUSB_OS == OPT_OS_NONE +volatile uint32_t system_ticks = 0; +void SysTick_Handler (void) +{ + system_ticks++; +} + +uint32_t board_millis (void) +{ + return system_ticks; +} +#endif + +// Required by __libc_init_array in startup code if we are compiling using +// -nostdlib/-nostartfiles. +void _init(void) +{ + +} diff --git a/hw/bsp/mm32/family.mk b/hw/bsp/mm32/family.mk new file mode 100644 index 000000000..3273ff870 --- /dev/null +++ b/hw/bsp/mm32/family.mk @@ -0,0 +1,36 @@ +UF2_FAMILY_ID = 0x0 +SDK_DIR = hw/mcu/mindmotion/mm32sdk +DEPS_SUBMODULES += lib/CMSIS_5 $(SDK_DIR) + +include $(TOP)/$(BOARD_PATH)/board.mk + +CFLAGS += \ + -flto \ + -mthumb \ + -mabi=aapcs \ + -mcpu=cortex-m3 \ + -mfloat-abi=soft \ + -nostdlib -nostartfiles \ + -DCFG_TUSB_MCU=OPT_MCU_MM32F327X + +# suppress warning caused by vendor mcu driver +CFLAGS += -Wno-error=unused-parameter -Wno-error=maybe-uninitialized + +SRC_C += \ + src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c \ + $(SDK_DIR)/mm32f327x/MM32F327x/Source/system_mm32f327x.c \ + $(SDK_DIR)/mm32f327x/MM32F327x/HAL_Lib/Src/hal_gpio.c \ + $(SDK_DIR)/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rcc.c \ + $(SDK_DIR)/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uart.c \ + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ + $(TOP)/$(SDK_DIR)/mm32f327x/MM32F327x/Include \ + $(TOP)/$(SDK_DIR)/mm32f327x/MM32F327x/HAL_Lib/Inc + +# For freeRTOS port source +FREERTOS_PORT = ARM_CM3 + +# flash target using on-board +flash: flash-jlink diff --git a/hw/bsp/mm32/mm32f327x/flash.ld b/hw/bsp/mm32/mm32f327x/flash.ld deleted file mode 100644 index d96d6e43d..000000000 --- a/hw/bsp/mm32/mm32f327x/flash.ld +++ /dev/null @@ -1,163 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2020 MM32 SE TEAM - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -/* Entry Point */ -ENTRY(Reset_Handler) - -/* Highest address of the user mode stack */ -_estack = 0x2001FFFF; /* end of RAM */ - -/* Generate a link error if heap and stack don't fit into RAM */ -_Min_Heap_Size = 0x200; /* required amount of heap */ -_Min_Stack_Size = 0x400; /* required amount of stack */ - -/* Specify the memory areas */ -MEMORY -{ -FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K -RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K -} - -/* Define output sections */ -SECTIONS -{ - /* The startup code goes first into FLASH */ - .isr_vector : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } >FLASH - - /* The program code and other data goes into FLASH */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - - KEEP (*(.init)) - KEEP (*(.fini)) - - . = ALIGN(4); - _etext = .; /* define a global symbols at end of code */ - } >FLASH - - /* Constant data goes into FLASH */ - .rodata : - { - . = ALIGN(4); - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - . = ALIGN(4); - } >FLASH - - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } >FLASH - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } >FLASH - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } >FLASH - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } >FLASH - - /* used by the startup to initialize data */ - _sidata = LOADADDR(.data); - - /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end */ - } >RAM AT> FLASH - - - /* Uninitialized data section */ - . = ALIGN(4); - .bss : - { - /* This is used by the startup in order to initialize the .bss secion */ - _sbss = .; /* define a global symbol at bss start */ - __bss_start__ = _sbss; - *(.bss) - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end */ - __bss_end__ = _ebss; - } >RAM - - /* User_heap_stack section, used to check that there is enough RAM left */ - ._user_heap_stack : - { - . = ALIGN(8); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - . = . + _Min_Heap_Size; - . = . + _Min_Stack_Size; - . = ALIGN(8); - } >RAM - - - - /* Remove information from the standard libraries */ - /DISCARD/ : - { - libc.a ( * ) - libm.a ( * ) - libgcc.a ( * ) - } - - .ARM.attributes 0 : { *(.ARM.attributes) } -} diff --git a/hw/bsp/mm32/mm32f327x/mm32f327x_mb39.c b/hw/bsp/mm32/mm32f327x/mm32f327x_mb39.c deleted file mode 100644 index 39b264b70..000000000 --- a/hw/bsp/mm32/mm32f327x/mm32f327x_mb39.c +++ /dev/null @@ -1,161 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2020 MM32 SE TEAM - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#include "mm32_device.h" -#include "hal_conf.h" -#include "tusb.h" -#include "../board.h" - -//--------------------------------------------------------------------+ -// Forward USB interrupt events to TinyUSB IRQ Handler -//--------------------------------------------------------------------+ -void OTG_FS_IRQHandler(void) -{ - dcd_int_handler(TUD_OPT_RHPORT); - -} -void USB_DeviceClockInit(void) -{ - /* Select USBCLK source */ - // RCC_USBCLKConfig(RCC_USBCLKSource_PLLCLK_Div1); - RCC->CFGR &= ~(0x3 << 22); - RCC->CFGR |= (0x1 << 22); - - /* Enable USB clock */ - RCC->AHB2ENR |= 0x1 << 7; -} -//--------------------------------------------------------------------+ -// MACRO TYPEDEF CONSTANT ENUM DECLARATION -//--------------------------------------------------------------------+ -// LED - -void board_led_write(bool state); -extern u32 SystemCoreClock; -const int baudrate = 115200; - -void board_init(void) -{ -// usb clock - USB_DeviceClockInit(); - - if (SysTick_Config(SystemCoreClock / 1000)) { - while (1); - } - NVIC_SetPriority(SysTick_IRQn, 0x0); - - // LED - GPIO_InitTypeDef GPIO_InitStruct; - RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOA, ENABLE); - GPIO_StructInit(&GPIO_InitStruct); - GPIO_PinAFConfig(GPIOA, GPIO_PinSource15, GPIO_AF_15); //Disable JTDI AF to AF15 - - GPIO_InitStruct.GPIO_Pin = GPIO_Pin_15; - GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStruct.GPIO_Mode = GPIO_Mode_Out_PP; - GPIO_Init(GPIOA, &GPIO_InitStruct); - - board_led_write(true); - - // UART - UART_InitTypeDef UART_InitStruct; - - RCC_APB2PeriphClockCmd(RCC_APB2ENR_UART1, ENABLE); //enableUART1,GPIOAclock - RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOA, ENABLE); // - //UART initialset - - GPIO_PinAFConfig(GPIOA, GPIO_PinSource9, GPIO_AF_7); - GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_7); - - - UART_StructInit(&UART_InitStruct); - UART_InitStruct.UART_BaudRate = baudrate; - UART_InitStruct.UART_WordLength = UART_WordLength_8b; - UART_InitStruct.UART_StopBits = UART_StopBits_1;//one stopbit - UART_InitStruct.UART_Parity = UART_Parity_No;//none odd-even verify bit - UART_InitStruct.UART_HardwareFlowControl = UART_HardwareFlowControl_None;//No hardware flow control - UART_InitStruct.UART_Mode = UART_Mode_Rx | UART_Mode_Tx; // receive and sent mode - - UART_Init(UART1, &UART_InitStruct); //initial uart 1 - UART_Cmd(UART1, ENABLE); //enable uart 1 - - //UART1_TX GPIOA.9 - GPIO_StructInit(&GPIO_InitStruct); - GPIO_InitStruct.GPIO_Pin = GPIO_Pin_9; - GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(GPIOA, &GPIO_InitStruct); - - //UART1_RX GPIOA.10 - GPIO_InitStruct.GPIO_Pin = GPIO_Pin_5; - GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IPU; - GPIO_Init(GPIOA, &GPIO_InitStruct); - -} - -//--------------------------------------------------------------------+ -// Board porting API -//--------------------------------------------------------------------+ - -void board_led_write(bool state) -{ - state ? (GPIO_ResetBits(GPIOA,GPIO_Pin_15)):(GPIO_SetBits(GPIOA,GPIO_Pin_15)); -} - -uint32_t board_button_read(void) -{ - return 0; -} - -int board_uart_read(uint8_t* buf, int len) -{ - (void) buf; (void) len; - return 0; -} - -int board_uart_write(void const * buf, int len) -{ - const char *buff = buf; - while(len){ - while((UART1->CSR & UART_IT_TXIEN) == 0); //The loop is sent until it is finished - UART1->TDR = (*buff & 0xFF); - buff++; - len--; - } - return len; -} - -#if CFG_TUSB_OS == OPT_OS_NONE -volatile uint32_t system_ticks = 0; -void SysTick_Handler(void) -{ - system_ticks++; -} - -uint32_t board_millis(void) -{ - return system_ticks; -} -#endif diff --git a/src/class/cdc/cdc_device.h b/src/class/cdc/cdc_device.h index 7ff757add..72e29705a 100644 --- a/src/class/cdc/cdc_device.h +++ b/src/class/cdc/cdc_device.h @@ -82,7 +82,7 @@ int32_t tud_cdc_n_read_char (uint8_t itf); void tud_cdc_n_read_flush (uint8_t itf); // Get a byte from FIFO at the specified position without removing it -bool tud_cdc_n_peek (uint8_t itf, uint8_t* u8); +bool tud_cdc_n_peek (uint8_t itf, uint8_t* uv8); // Write bytes to TX FIFO, data may remain in the FIFO for a while uint32_t tud_cdc_n_write (uint8_t itf, void const* buffer, uint32_t bufsize); @@ -206,9 +206,9 @@ static inline void tud_cdc_read_flush (void) tud_cdc_n_read_flush(0); } -static inline bool tud_cdc_peek (uint8_t* u8) +static inline bool tud_cdc_peek (uint8_t* uv8) { - return tud_cdc_n_peek(0, u8); + return tud_cdc_n_peek(0, uv8); } static inline uint32_t tud_cdc_write_char (char ch) diff --git a/src/class/vendor/vendor_device.h b/src/class/vendor/vendor_device.h index 6d9c784c0..b54194271 100644 --- a/src/class/vendor/vendor_device.h +++ b/src/class/vendor/vendor_device.h @@ -44,7 +44,7 @@ bool tud_vendor_n_mounted (uint8_t itf); uint32_t tud_vendor_n_available (uint8_t itf); uint32_t tud_vendor_n_read (uint8_t itf, void* buffer, uint32_t bufsize); -bool tud_vendor_n_peek (uint8_t itf, uint8_t* u8); +bool tud_vendor_n_peek (uint8_t itf, uint8_t* uv8); uint32_t tud_vendor_n_write (uint8_t itf, void const* buffer, uint32_t bufsize); uint32_t tud_vendor_n_write_available (uint8_t itf); @@ -58,7 +58,7 @@ uint32_t tud_vendor_n_write_str (uint8_t itf, char const* str); static inline bool tud_vendor_mounted (void); static inline uint32_t tud_vendor_available (void); static inline uint32_t tud_vendor_read (void* buffer, uint32_t bufsize); -static inline bool tud_vendor_peek (uint8_t* u8); +static inline bool tud_vendor_peek (uint8_t* uv8); static inline uint32_t tud_vendor_write (void const* buffer, uint32_t bufsize); static inline uint32_t tud_vendor_write_str (char const* str); static inline uint32_t tud_vendor_write_available (void); @@ -94,9 +94,9 @@ static inline uint32_t tud_vendor_read (void* buffer, uint32_t bufsize) return tud_vendor_n_read(0, buffer, bufsize); } -static inline bool tud_vendor_peek (uint8_t* u8) +static inline bool tud_vendor_peek (uint8_t* uv8) { - return tud_vendor_n_peek(0, u8); + return tud_vendor_n_peek(0, uv8); } static inline uint32_t tud_vendor_write (void const* buffer, uint32_t bufsize) diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h index 889ad7b25..ece5d800a 100644 --- a/src/common/tusb_common.h +++ b/src/common/tusb_common.h @@ -38,18 +38,18 @@ #define TU_MIN(_x, _y) ( ( (_x) < (_y) ) ? (_x) : (_y) ) #define TU_MAX(_x, _y) ( ( (_x) > (_y) ) ? (_x) : (_y) ) -#define TU_U16_HIGH(u16) ((uint8_t) (((u16) >> 8) & 0x00ff)) -#define TU_U16_LOW(u16) ((uint8_t) ((u16) & 0x00ff)) -#define U16_TO_U8S_BE(u16) TU_U16_HIGH(u16), TU_U16_LOW(u16) -#define U16_TO_U8S_LE(u16) TU_U16_LOW(u16), TU_U16_HIGH(u16) +#define TU_U16_HIGH(_u16) ((uint8_t) (((_u16) >> 8) & 0x00ff)) +#define TU_U16_LOW(_u16) ((uint8_t) ((_u16) & 0x00ff)) +#define U16_TO_U8S_BE(_u16) TU_U16_HIGH(_u16), TU_U16_LOW(_u16) +#define U16_TO_U8S_LE(_u16) TU_U16_LOW(_u16), TU_U16_HIGH(_u16) -#define TU_U32_BYTE3(u32) ((uint8_t) ((((uint32_t) u32) >> 24) & 0x000000ff)) // MSB -#define TU_U32_BYTE2(u32) ((uint8_t) ((((uint32_t) u32) >> 16) & 0x000000ff)) -#define TU_U32_BYTE1(u32) ((uint8_t) ((((uint32_t) u32) >> 8) & 0x000000ff)) -#define TU_U32_BYTE0(u32) ((uint8_t) (((uint32_t) u32) & 0x000000ff)) // LSB +#define TU_U32_BYTE3(_u32) ((uint8_t) ((((uint32_t) _u32) >> 24) & 0x000000ff)) // MSB +#define TU_U32_BYTE2(_u32) ((uint8_t) ((((uint32_t) _u32) >> 16) & 0x000000ff)) +#define TU_U32_BYTE1(_u32) ((uint8_t) ((((uint32_t) _u32) >> 8) & 0x000000ff)) +#define TU_U32_BYTE0(_u32) ((uint8_t) (((uint32_t) _u32) & 0x000000ff)) // LSB -#define U32_TO_U8S_BE(u32) TU_U32_BYTE3(u32), TU_U32_BYTE2(u32), TU_U32_BYTE1(u32), TU_U32_BYTE0(u32) -#define U32_TO_U8S_LE(u32) TU_U32_BYTE0(u32), TU_U32_BYTE1(u32), TU_U32_BYTE2(u32), TU_U32_BYTE3(u32) +#define U32_TO_U8S_BE(_u32) TU_U32_BYTE3(_u32), TU_U32_BYTE2(_u32), TU_U32_BYTE1(_u32), TU_U32_BYTE0(_u32) +#define U32_TO_U8S_LE(_u32) TU_U32_BYTE0(_u32), TU_U32_BYTE1(_u32), TU_U32_BYTE2(_u32), TU_U32_BYTE3(_u32) #define TU_BIT(n) (1UL << (n)) @@ -88,13 +88,13 @@ TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_u16(uint8_t high, uint8_t low) return (uint16_t) ((((uint16_t) high) << 8) | low); } -TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u32_byte3(uint32_t u32) { return TU_U32_BYTE3(u32); } -TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u32_byte2(uint32_t u32) { return TU_U32_BYTE2(u32); } -TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u32_byte1(uint32_t u32) { return TU_U32_BYTE1(u32); } -TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u32_byte0(uint32_t u32) { return TU_U32_BYTE0(u32); } +TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u32_byte3(uint32_t uv32) { return TU_U32_BYTE3(uv32); } +TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u32_byte2(uint32_t uv32) { return TU_U32_BYTE2(uv32); } +TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u32_byte1(uint32_t uv32) { return TU_U32_BYTE1(uv32); } +TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u32_byte0(uint32_t uv32) { return TU_U32_BYTE0(uv32); } -TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u16_high(uint16_t u16) { return TU_U16_HIGH(u16); } -TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u16_low (uint16_t u16) { return TU_U16_LOW(u16); } +TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u16_high(uint16_t uv16) { return TU_U16_HIGH(uv16); } +TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u16_low (uint16_t uv16) { return TU_U16_LOW(uv16); } //------------- Bits -------------// TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_bit_set (uint32_t value, uint8_t pos) { return value | TU_BIT(pos); } diff --git a/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c b/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c index 59a40dc68..31b1f7080 100644 --- a/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c +++ b/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c @@ -283,7 +283,7 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr) /* Response with status first before changing device address */ dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0); } -extern u32 SystemCoreClock ; +extern u32 SystemCoreClock; void dcd_remote_wakeup(uint8_t rhport) { (void) rhport; -- cgit v1.3.1 From 07adc26ce32ee663905a25bd0300d56c265dc2ad Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 26 Aug 2021 13:07:10 +0700 Subject: fix usbcv TD 9.4 Interface Descriptor test --- src/device/usbd.c | 26 +++++++++++++++++--------- 1 file changed, 17 insertions(+), 9 deletions(-) diff --git a/src/device/usbd.c b/src/device/usbd.c index e12dafcfd..2b706e291 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -751,16 +751,24 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const // driver doesn't use alternate settings or implement this TU_VERIFY(TUSB_REQ_TYPE_STANDARD == p_request->bmRequestType_bit.type); - if (TUSB_REQ_GET_INTERFACE == p_request->bRequest) + switch(p_request->bRequest) { - uint8_t alternate = 0; - tud_control_xfer(rhport, p_request, &alternate, 1); - }else if (TUSB_REQ_SET_INTERFACE == p_request->bRequest) - { - tud_control_status(rhport, p_request); - } else - { - return false; + case TUSB_REQ_GET_INTERFACE: + case TUSB_REQ_SET_INTERFACE: + // Clear complete callback if driver set since it can also stall the request. + usbd_control_set_complete_callback(NULL); + + if (TUSB_REQ_GET_INTERFACE == p_request->bRequest) + { + uint8_t alternate = 0; + tud_control_xfer(rhport, p_request, &alternate, 1); + }else + { + tud_control_status(rhport, p_request); + } + break; + + default: return false; } } } -- cgit v1.3.1 From 71e77e47fa6056937bfcd1a883a66e2bc0b622b2 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 26 Aug 2021 17:02:24 +0700 Subject: add dcd_edpt_close_all() for clear existing configured state correctly responded to TD 9.13 Set Configuration Test --- src/device/dcd.h | 5 ++ src/device/usbd.c | 54 ++++++++++++++++------ src/portable/dialog/da146xx/dcd_da146xx.c | 6 +++ src/portable/espressif/esp32sx/dcd_esp32sx.c | 6 +++ src/portable/microchip/samd/dcd_samd.c | 6 +++ src/portable/microchip/samg/dcd_samg.c | 6 +++ src/portable/microchip/samx7x/dcd_samx7x.c | 6 +++ src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c | 6 +++ src/portable/nordic/nrf5x/dcd_nrf5x.c | 6 +++ src/portable/nuvoton/nuc120/dcd_nuc120.c | 6 +++ src/portable/nuvoton/nuc121/dcd_nuc121.c | 6 +++ src/portable/nuvoton/nuc505/dcd_nuc505.c | 6 +++ src/portable/nxp/khci/dcd_khci.c | 6 +++ src/portable/nxp/lpc17_40/dcd_lpc17_40.c | 6 +++ src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c | 6 +++ .../nxp/transdimension/dcd_transdimension.c | 6 +++ src/portable/raspberrypi/rp2040/dcd_rp2040.c | 6 +++ src/portable/renesas/usba/dcd_usba.c | 6 +++ src/portable/silabs/efm32/dcd_efm32.c | 6 +++ src/portable/sony/cxd56/dcd_cxd56.c | 6 +++ src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 6 +++ src/portable/st/synopsys/dcd_synopsys.c | 6 +++ src/portable/template/dcd_template.c | 5 ++ src/portable/ti/msp430x5xx/dcd_msp430x5xx.c | 6 +++ src/portable/valentyusb/eptri/dcd_eptri.c | 6 +++ 25 files changed, 181 insertions(+), 15 deletions(-) diff --git a/src/device/dcd.h b/src/device/dcd.h index 66767c1fe..8d042bbde 100644 --- a/src/device/dcd.h +++ b/src/device/dcd.h @@ -137,6 +137,11 @@ void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * re // Configure endpoint's registers according to descriptor bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_ep); +// Close all non-control endpoints, cancel all pending transfers if any. +// Invoked when switching from a non-zero Configuration by SET_CONFIGURE therefore +// required for multiple configuration support. +void dcd_edpt_close_all (uint8_t rhport); + // Close an endpoint. // Since it is weak, caller must TU_ASSERT this function's existence before calling it. void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr) TU_ATTR_WEAK; diff --git a/src/device/usbd.c b/src/device/usbd.c index 2b706e291..b2babb7a0 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -38,7 +38,7 @@ //--------------------------------------------------------------------+ // Debug level of USBD -#define USBD_DBG_LVL 2 +#define USBD_DBG 2 #ifndef CFG_TUD_TASK_QUEUE_SZ #define CFG_TUD_TASK_QUEUE_SZ 16 @@ -432,19 +432,22 @@ bool tud_init (uint8_t rhport) return true; } -static void usbd_reset(uint8_t rhport) +static void configuration_reset(uint8_t rhport) { - tu_varclr(&_usbd_dev); + for ( uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++ ) + { + get_driver(i)->reset(rhport); + } + tu_varclr(&_usbd_dev); memset(_usbd_dev.itf2drv, DRVID_INVALID, sizeof(_usbd_dev.itf2drv)); // invalid mapping memset(_usbd_dev.ep2drv , DRVID_INVALID, sizeof(_usbd_dev.ep2drv )); // invalid mapping +} +static void usbd_reset(uint8_t rhport) +{ + configuration_reset(rhport); usbd_control_reset(); - - for ( uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++ ) - { - get_driver(i)->reset(rhport); - } } bool tud_task_event_ready(void) @@ -686,9 +689,29 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const { uint8_t const cfg_num = (uint8_t) p_request->wValue; - if ( !_usbd_dev.cfg_num && cfg_num ) TU_ASSERT( process_set_config(rhport, cfg_num) ); - _usbd_dev.cfg_num = cfg_num; + // Only process if new configure is different + if (_usbd_dev.cfg_num != cfg_num) + { + if ( _usbd_dev.cfg_num ) + { + // already configured: need to clear all endpoints and driver first + TU_LOG(USBD_DBG, "Clear current config (%u) before switching\r\n", _usbd_dev.cfg_num); + + // close all non-control endpoints, cancel all pending transfers if any + dcd_edpt_close_all(rhport); + // close all drivers and current configured state except bus speed + uint8_t const speed = _usbd_dev.speed; + configuration_reset(rhport); + + _usbd_dev.speed = speed; // restore speed + } + + // switch to new configuration if not zero + if ( cfg_num ) TU_ASSERT( process_set_config(rhport, cfg_num) ); + } + + _usbd_dev.cfg_num = cfg_num; tud_control_status(rhport, p_request); } break; @@ -701,7 +724,7 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const // Only support remote wakeup for device feature TU_VERIFY(TUSB_REQ_FEATURE_REMOTE_WAKEUP == p_request->wValue); - TU_LOG(USBD_DBG_LVL, " Enable Remote Wakeup\r\n"); + TU_LOG(USBD_DBG, " Enable Remote Wakeup\r\n"); // Host may enable remote wake up before suspending especially HID device _usbd_dev.remote_wakeup_en = true; @@ -712,7 +735,7 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const // Only support remote wakeup for device feature TU_VERIFY(TUSB_REQ_FEATURE_REMOTE_WAKEUP == p_request->wValue); - TU_LOG(USBD_DBG_LVL, " Disable Remote Wakeup\r\n"); + TU_LOG(USBD_DBG, " Disable Remote Wakeup\r\n"); // Host may disable remote wake up after resuming _usbd_dev.remote_wakeup_en = false; @@ -851,7 +874,8 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const // This function parse configuration descriptor & open drivers accordingly static bool process_set_config(uint8_t rhport, uint8_t cfg_num) { - tusb_desc_configuration_t const * desc_cfg = (tusb_desc_configuration_t const *) tud_descriptor_configuration_cb(cfg_num-1); // index is cfg_num-1 + // index is cfg_num-1 + tusb_desc_configuration_t const * desc_cfg = (tusb_desc_configuration_t const *) tud_descriptor_configuration_cb(cfg_num-1); TU_ASSERT(desc_cfg != NULL && desc_cfg->bDescriptorType == TUSB_DESC_CONFIGURATION); // Parse configuration descriptor @@ -1309,7 +1333,7 @@ bool usbd_edpt_busy(uint8_t rhport, uint8_t ep_addr) void usbd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { - TU_LOG(USBD_DBG_LVL, " Stall EP %02X", ep_addr); + TU_LOG(USBD_DBG, " Stall EP %02X", ep_addr); uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); @@ -1321,7 +1345,7 @@ void usbd_edpt_stall(uint8_t rhport, uint8_t ep_addr) void usbd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { - TU_LOG(USBD_DBG_LVL, " Clear Stall EP %02X", ep_addr); + TU_LOG(USBD_DBG, " Clear Stall EP %02X", ep_addr); uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); diff --git a/src/portable/dialog/da146xx/dcd_da146xx.c b/src/portable/dialog/da146xx/dcd_da146xx.c index 5fcf3bc5b..7b0d8f86c 100644 --- a/src/portable/dialog/da146xx/dcd_da146xx.c +++ b/src/portable/dialog/da146xx/dcd_da146xx.c @@ -847,6 +847,12 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) return true; } +void dcd_edpt_close_all (uint8_t rhport) +{ + (void) rhport; + // TODO implement dcd_edpt_close_all() +} + void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) { uint8_t const epnum = tu_edpt_number(ep_addr); diff --git a/src/portable/espressif/esp32sx/dcd_esp32sx.c b/src/portable/espressif/esp32sx/dcd_esp32sx.c index d728487c2..a5ada0da8 100644 --- a/src/portable/espressif/esp32sx/dcd_esp32sx.c +++ b/src/portable/espressif/esp32sx/dcd_esp32sx.c @@ -312,6 +312,12 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_edpt) return true; } +void dcd_edpt_close_all(uint8_t rhport) +{ + (void) rhport; + // TODO implement dcd_edpt_close_all() +} + bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) { (void)rhport; diff --git a/src/portable/microchip/samd/dcd_samd.c b/src/portable/microchip/samd/dcd_samd.c index 577bd0e05..54e8e62d9 100644 --- a/src/portable/microchip/samd/dcd_samd.c +++ b/src/portable/microchip/samd/dcd_samd.c @@ -240,6 +240,12 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) return true; } +void dcd_edpt_close_all (uint8_t rhport) +{ + (void) rhport; + // TODO implement dcd_edpt_close_all() +} + bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) { (void) rhport; diff --git a/src/portable/microchip/samg/dcd_samg.c b/src/portable/microchip/samg/dcd_samg.c index d50621ce4..81779c56b 100644 --- a/src/portable/microchip/samg/dcd_samg.c +++ b/src/portable/microchip/samg/dcd_samg.c @@ -269,6 +269,12 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) return true; } +void dcd_edpt_close_all (uint8_t rhport) +{ + (void) rhport; + // TODO implement dcd_edpt_close_all() +} + // Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) { diff --git a/src/portable/microchip/samx7x/dcd_samx7x.c b/src/portable/microchip/samx7x/dcd_samx7x.c index 0d9e184f6..032547e47 100644 --- a/src/portable/microchip/samx7x/dcd_samx7x.c +++ b/src/portable/microchip/samx7x/dcd_samx7x.c @@ -544,6 +544,12 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) } } +void dcd_edpt_close_all (uint8_t rhport) +{ + (void) rhport; + // TODO implement dcd_edpt_close_all() +} + void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) { (void) rhport; diff --git a/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c b/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c index 59a40dc68..c472f2175 100644 --- a/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c +++ b/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c @@ -339,6 +339,12 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) return true; } +void dcd_edpt_close_all (uint8_t rhport) +{ + (void) rhport; + // TODO implement dcd_edpt_close_all() +} + void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) { (void) rhport; diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c index f6b64c986..efc4d3183 100644 --- a/src/portable/nordic/nrf5x/dcd_nrf5x.c +++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c @@ -364,6 +364,12 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) return true; } +void dcd_edpt_close_all (uint8_t rhport) +{ + (void) rhport; + // TODO implement dcd_edpt_close_all() +} + void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr) { (void) rhport; diff --git a/src/portable/nuvoton/nuc120/dcd_nuc120.c b/src/portable/nuvoton/nuc120/dcd_nuc120.c index 57cc76e81..7618f288d 100644 --- a/src/portable/nuvoton/nuc120/dcd_nuc120.c +++ b/src/portable/nuvoton/nuc120/dcd_nuc120.c @@ -273,6 +273,12 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) return true; } +void dcd_edpt_close_all (uint8_t rhport) +{ + (void) rhport; + // TODO implement dcd_edpt_close_all() +} + bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) { (void) rhport; diff --git a/src/portable/nuvoton/nuc121/dcd_nuc121.c b/src/portable/nuvoton/nuc121/dcd_nuc121.c index a776e46f5..7edafe5d3 100644 --- a/src/portable/nuvoton/nuc121/dcd_nuc121.c +++ b/src/portable/nuvoton/nuc121/dcd_nuc121.c @@ -289,6 +289,12 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) return true; } +void dcd_edpt_close_all (uint8_t rhport) +{ + (void) rhport; + // TODO implement dcd_edpt_close_all() +} + bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) { (void) rhport; diff --git a/src/portable/nuvoton/nuc505/dcd_nuc505.c b/src/portable/nuvoton/nuc505/dcd_nuc505.c index 4e633086d..ea5a8bea5 100644 --- a/src/portable/nuvoton/nuc505/dcd_nuc505.c +++ b/src/portable/nuvoton/nuc505/dcd_nuc505.c @@ -353,6 +353,12 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) return true; } +void dcd_edpt_close_all (uint8_t rhport) +{ + (void) rhport; + // TODO implement dcd_edpt_close_all() +} + bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) { (void) rhport; diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c index dce464fd2..1f5f4e5e1 100644 --- a/src/portable/nxp/khci/dcd_khci.c +++ b/src/portable/nxp/khci/dcd_khci.c @@ -347,6 +347,12 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) return true; } +void dcd_edpt_close_all (uint8_t rhport) +{ + (void) rhport; + // TODO implement dcd_edpt_close_all() +} + void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) { (void) rhport; diff --git a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c index 519d09151..2eae6d0f7 100644 --- a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c +++ b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c @@ -326,6 +326,12 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) return true; } +void dcd_edpt_close_all (uint8_t rhport) +{ + (void) rhport; + // TODO implement dcd_edpt_close_all() +} + void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { (void) rhport; diff --git a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c index 4392d1882..1bdf72d6d 100644 --- a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c +++ b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c @@ -323,6 +323,12 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) return true; } +void dcd_edpt_close_all (uint8_t rhport) +{ + (void) rhport; + // TODO implement dcd_edpt_close_all() +} + static void prepare_setup_packet(uint8_t rhport) { if (_dcd_controller[rhport].max_speed == TUSB_SPEED_FULL ) diff --git a/src/portable/nxp/transdimension/dcd_transdimension.c b/src/portable/nxp/transdimension/dcd_transdimension.c index eeab3f487..42047ef92 100644 --- a/src/portable/nxp/transdimension/dcd_transdimension.c +++ b/src/portable/nxp/transdimension/dcd_transdimension.c @@ -366,6 +366,12 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) return true; } +void dcd_edpt_close_all (uint8_t rhport) +{ + (void) rhport; + // TODO implement dcd_edpt_close_all() +} + bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) { dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c index 49284e92e..e81681d4f 100644 --- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c @@ -428,6 +428,12 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) return true; } +void dcd_edpt_close_all (uint8_t rhport) +{ + (void) rhport; + // TODO implement dcd_edpt_close_all() +} + bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) { assert(rhport == 0); diff --git a/src/portable/renesas/usba/dcd_usba.c b/src/portable/renesas/usba/dcd_usba.c index 095dcc136..a837b5724 100644 --- a/src/portable/renesas/usba/dcd_usba.c +++ b/src/portable/renesas/usba/dcd_usba.c @@ -733,6 +733,12 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) return true; } +void dcd_edpt_close_all (uint8_t rhport) +{ + (void) rhport; + // TODO implement dcd_edpt_close_all() +} + void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) { (void)rhport; diff --git a/src/portable/silabs/efm32/dcd_efm32.c b/src/portable/silabs/efm32/dcd_efm32.c index bd1f32e6b..3bef83408 100644 --- a/src/portable/silabs/efm32/dcd_efm32.c +++ b/src/portable/silabs/efm32/dcd_efm32.c @@ -434,6 +434,12 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) return true; } +void dcd_edpt_close_all (uint8_t rhport) +{ + (void) rhport; + // TODO implement dcd_edpt_close_all() +} + bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) { (void)rhport; diff --git a/src/portable/sony/cxd56/dcd_cxd56.c b/src/portable/sony/cxd56/dcd_cxd56.c index 834976468..cfd74330f 100644 --- a/src/portable/sony/cxd56/dcd_cxd56.c +++ b/src/portable/sony/cxd56/dcd_cxd56.c @@ -312,6 +312,12 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *p_endpoint_desc) return true; } +void dcd_edpt_close_all (uint8_t rhport) +{ + (void) rhport; + // TODO implement dcd_edpt_close_all() +} + bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) { (void) rhport; diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index eeba7204f..ccffa42d7 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -800,6 +800,12 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc return true; } +void dcd_edpt_close_all (uint8_t rhport) +{ + (void) rhport; + // TODO implement dcd_edpt_close_all() +} + /** * Close an endpoint. * diff --git a/src/portable/st/synopsys/dcd_synopsys.c b/src/portable/st/synopsys/dcd_synopsys.c index 8a998aa3a..fe165e830 100644 --- a/src/portable/st/synopsys/dcd_synopsys.c +++ b/src/portable/st/synopsys/dcd_synopsys.c @@ -670,6 +670,12 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) return true; } +void dcd_edpt_close_all (uint8_t rhport) +{ + (void) rhport; + // TODO implement dcd_edpt_close_all() +} + bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) { uint8_t const epnum = tu_edpt_number(ep_addr); diff --git a/src/portable/template/dcd_template.c b/src/portable/template/dcd_template.c index 12b9144bf..977369300 100644 --- a/src/portable/template/dcd_template.c +++ b/src/portable/template/dcd_template.c @@ -94,6 +94,11 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) return false; } +void dcd_edpt_close_all (uint8_t rhport) +{ + (void) rhport; +} + // Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) { diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c index 027ed26c9..ee85f0a77 100644 --- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c +++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c @@ -298,6 +298,12 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) return true; } +void dcd_edpt_close_all (uint8_t rhport) +{ + (void) rhport; + // TODO implement dcd_edpt_close_all() +} + bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) { (void) rhport; diff --git a/src/portable/valentyusb/eptri/dcd_eptri.c b/src/portable/valentyusb/eptri/dcd_eptri.c index b68f04faa..89bc7a1ab 100644 --- a/src/portable/valentyusb/eptri/dcd_eptri.c +++ b/src/portable/valentyusb/eptri/dcd_eptri.c @@ -429,6 +429,12 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) return true; } +void dcd_edpt_close_all (uint8_t rhport) +{ + (void) rhport; + // TODO implement dcd_edpt_close_all() +} + void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { (void) rhport; -- cgit v1.3.1 From ed4602158bb4e19f4dba122383be1c4845914bde Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 26 Aug 2021 17:08:22 +0700 Subject: TD 9.12 remote wakeup test remove TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP attribute from non-hid examples --- examples/device/audio_4_channel_mic/src/usb_descriptors.c | 2 +- examples/device/audio_test/src/usb_descriptors.c | 2 +- examples/device/cdc_dual_ports/src/usb_descriptors.c | 4 ++-- examples/device/cdc_msc/src/usb_descriptors.c | 4 ++-- examples/device/cdc_msc_freertos/src/usb_descriptors.c | 4 ++-- examples/device/dfu/src/usb_descriptors.c | 2 +- examples/device/dfu_runtime/src/usb_descriptors.c | 2 +- examples/device/dynamic_configuration/src/usb_descriptors.c | 4 ++-- examples/device/hid_generic_inout/src/usb_descriptors.c | 2 +- examples/device/midi_test/src/usb_descriptors.c | 4 ++-- examples/device/msc_dual_lun/src/usb_descriptors.c | 4 ++-- examples/device/uac2_headset/src/usb_descriptors.c | 2 +- examples/device/usbtmc/src/usb_descriptors.c | 2 +- examples/device/webusb_serial/src/usb_descriptors.c | 2 +- 14 files changed, 20 insertions(+), 20 deletions(-) diff --git a/examples/device/audio_4_channel_mic/src/usb_descriptors.c b/examples/device/audio_4_channel_mic/src/usb_descriptors.c index 93ec6e9f7..018919bf3 100644 --- a/examples/device/audio_4_channel_mic/src/usb_descriptors.c +++ b/examples/device/audio_4_channel_mic/src/usb_descriptors.c @@ -92,7 +92,7 @@ enum uint8_t const desc_configuration[] = { // Interface count, string index, total length, attribute, power in mA - TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100), + TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100), // Interface number, string index, EP Out & EP In address, EP size TUD_AUDIO_MIC_FOUR_CH_DESCRIPTOR(/*_itfnum*/ ITF_NUM_AUDIO_CONTROL, /*_stridx*/ 0, /*_nBytesPerSample*/ CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX, /*_nBitsUsedPerSample*/ CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX*8, /*_epin*/ 0x80 | EPNUM_AUDIO, /*_epsize*/ CFG_TUD_AUDIO_EP_SZ_IN) diff --git a/examples/device/audio_test/src/usb_descriptors.c b/examples/device/audio_test/src/usb_descriptors.c index 67dd34d2a..a4e9dc8e1 100644 --- a/examples/device/audio_test/src/usb_descriptors.c +++ b/examples/device/audio_test/src/usb_descriptors.c @@ -92,7 +92,7 @@ enum uint8_t const desc_configuration[] = { // Interface count, string index, total length, attribute, power in mA - TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100), + TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100), // Interface number, string index, EP Out & EP In address, EP size TUD_AUDIO_MIC_ONE_CH_DESCRIPTOR(/*_itfnum*/ ITF_NUM_AUDIO_CONTROL, /*_stridx*/ 0, /*_nBytesPerSample*/ CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX, /*_nBitsUsedPerSample*/ CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX*8, /*_epin*/ 0x80 | EPNUM_AUDIO, /*_epsize*/ CFG_TUD_AUDIO_EP_SZ_IN) diff --git a/examples/device/cdc_dual_ports/src/usb_descriptors.c b/examples/device/cdc_dual_ports/src/usb_descriptors.c index b935b672f..02ccbcc9e 100644 --- a/examples/device/cdc_dual_ports/src/usb_descriptors.c +++ b/examples/device/cdc_dual_ports/src/usb_descriptors.c @@ -118,7 +118,7 @@ enum uint8_t const desc_fs_configuration[] = { // Config number, interface count, string index, total length, attribute, power in mA - TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100), + TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100), // 1st CDC: Interface number, string index, EP notification address and size, EP data address (out, in) and size. TUD_CDC_DESCRIPTOR(ITF_NUM_CDC_0, 4, EPNUM_CDC_0_NOTIF, 8, EPNUM_CDC_0_OUT, EPNUM_CDC_0_IN, 64), @@ -131,7 +131,7 @@ uint8_t const desc_fs_configuration[] = uint8_t const desc_hs_configuration[] = { // Config number, interface count, string index, total length, attribute, power in mA - TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100), + TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100), // 1st CDC: Interface number, string index, EP notification address and size, EP data address (out, in) and size. TUD_CDC_DESCRIPTOR(ITF_NUM_CDC_0, 4, EPNUM_CDC_0_NOTIF, 8, EPNUM_CDC_0_OUT, EPNUM_CDC_0_IN, 512), diff --git a/examples/device/cdc_msc/src/usb_descriptors.c b/examples/device/cdc_msc/src/usb_descriptors.c index 1a89ce561..3cf1eaf91 100644 --- a/examples/device/cdc_msc/src/usb_descriptors.c +++ b/examples/device/cdc_msc/src/usb_descriptors.c @@ -129,7 +129,7 @@ enum uint8_t const desc_fs_configuration[] = { // Config number, interface count, string index, total length, attribute, power in mA - TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100), + TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100), // Interface number, string index, EP notification address and size, EP data address (out, in) and size. TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT, EPNUM_CDC_IN, 64), @@ -142,7 +142,7 @@ uint8_t const desc_fs_configuration[] = uint8_t const desc_hs_configuration[] = { // Config number, interface count, string index, total length, attribute, power in mA - TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100), + TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100), // Interface number, string index, EP notification address and size, EP data address (out, in) and size. TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT, EPNUM_CDC_IN, 512), diff --git a/examples/device/cdc_msc_freertos/src/usb_descriptors.c b/examples/device/cdc_msc_freertos/src/usb_descriptors.c index 75b5ce7bb..c8dbcd415 100644 --- a/examples/device/cdc_msc_freertos/src/usb_descriptors.c +++ b/examples/device/cdc_msc_freertos/src/usb_descriptors.c @@ -117,7 +117,7 @@ enum uint8_t const desc_fs_configuration[] = { // Config number, interface count, string index, total length, attribute, power in mA - TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100), + TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100), // Interface number, string index, EP notification address and size, EP data address (out, in) and size. TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT, EPNUM_CDC_IN, 64), @@ -130,7 +130,7 @@ uint8_t const desc_fs_configuration[] = uint8_t const desc_hs_configuration[] = { // Config number, interface count, string index, total length, attribute, power in mA - TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100), + TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100), // Interface number, string index, EP notification address and size, EP data address (out, in) and size. TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT, EPNUM_CDC_IN, 512), diff --git a/examples/device/dfu/src/usb_descriptors.c b/examples/device/dfu/src/usb_descriptors.c index 1cfe29c53..350334aa5 100644 --- a/examples/device/dfu/src/usb_descriptors.c +++ b/examples/device/dfu/src/usb_descriptors.c @@ -97,7 +97,7 @@ enum uint8_t const desc_configuration[] = { // Config number, interface count, string index, total length, attribute, power in mA - TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100), + TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100), // Interface number, Alternate count, starting string index, attributes, detach timeout, transfer size TUD_DFU_DESCRIPTOR(ITF_NUM_DFU_MODE, ALT_COUNT, 4, FUNC_ATTRS, 1000, CFG_TUD_DFU_XFER_BUFSIZE), diff --git a/examples/device/dfu_runtime/src/usb_descriptors.c b/examples/device/dfu_runtime/src/usb_descriptors.c index 8b2bd265d..060943289 100644 --- a/examples/device/dfu_runtime/src/usb_descriptors.c +++ b/examples/device/dfu_runtime/src/usb_descriptors.c @@ -92,7 +92,7 @@ enum uint8_t const desc_configuration[] = { // Config number, interface count, string index, total length, attribute, power in mA - TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100), + TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100), // Interface number, string index, attributes, detach timeout, transfer size */ TUD_DFU_RT_DESCRIPTOR(ITF_NUM_DFU_RT, 4, 0x0d, 1000, 4096), diff --git a/examples/device/dynamic_configuration/src/usb_descriptors.c b/examples/device/dynamic_configuration/src/usb_descriptors.c index 9ccb37654..3352972a5 100644 --- a/examples/device/dynamic_configuration/src/usb_descriptors.c +++ b/examples/device/dynamic_configuration/src/usb_descriptors.c @@ -160,7 +160,7 @@ enum uint8_t const desc_configuration_0[] = { // Config number, interface count, string index, total length, attribute, power in mA - TUD_CONFIG_DESCRIPTOR(1, ITF_0_NUM_TOTAL, 0, CONFIG_0_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100), + TUD_CONFIG_DESCRIPTOR(1, ITF_0_NUM_TOTAL, 0, CONFIG_0_TOTAL_LEN, 0x00, 100), // Interface number, string index, EP notification address and size, EP data address (out, in) and size. TUD_CDC_DESCRIPTOR(ITF_0_NUM_CDC, 0, EPNUM_0_CDC_NOTIF, 8, EPNUM_0_CDC_OUT, EPNUM_0_CDC_IN, 64), @@ -173,7 +173,7 @@ uint8_t const desc_configuration_0[] = uint8_t const desc_configuraiton_1[] = { // Config number, interface count, string index, total length, attribute, power in mA - TUD_CONFIG_DESCRIPTOR(1, ITF_1_NUM_TOTAL, 0, CONFIG_1_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100), + TUD_CONFIG_DESCRIPTOR(1, ITF_1_NUM_TOTAL, 0, CONFIG_1_TOTAL_LEN, 0x00, 100), // Interface number, string index, EP Out & EP In address, EP size TUD_MSC_DESCRIPTOR(ITF_1_NUM_MSC, 0, EPNUM_1_MSC_OUT, EPNUM_1_MSC_IN, TUD_OPT_HIGH_SPEED ? 512 : 64), diff --git a/examples/device/hid_generic_inout/src/usb_descriptors.c b/examples/device/hid_generic_inout/src/usb_descriptors.c index 5a2f5ffdc..5dabf42a3 100644 --- a/examples/device/hid_generic_inout/src/usb_descriptors.c +++ b/examples/device/hid_generic_inout/src/usb_descriptors.c @@ -101,7 +101,7 @@ enum uint8_t const desc_configuration[] = { // Config number, interface count, string index, total length, attribute, power in mA - TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100), + TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100), // Interface number, string index, protocol, report descriptor len, EP In & Out address, size & polling interval TUD_HID_INOUT_DESCRIPTOR(ITF_NUM_HID, 0, HID_ITF_PROTOCOL_NONE, sizeof(desc_hid_report), EPNUM_HID, 0x80 | EPNUM_HID, CFG_TUD_HID_EP_BUFSIZE, 10) diff --git a/examples/device/midi_test/src/usb_descriptors.c b/examples/device/midi_test/src/usb_descriptors.c index 9d92a7753..bd5a0eeab 100644 --- a/examples/device/midi_test/src/usb_descriptors.c +++ b/examples/device/midi_test/src/usb_descriptors.c @@ -91,7 +91,7 @@ enum uint8_t const desc_fs_configuration[] = { // Config number, interface count, string index, total length, attribute, power in mA - TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100), + TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100), // Interface number, string index, EP Out & EP In address, EP size TUD_MIDI_DESCRIPTOR(ITF_NUM_MIDI, 0, EPNUM_MIDI, 0x80 | EPNUM_MIDI, 64) @@ -101,7 +101,7 @@ uint8_t const desc_fs_configuration[] = uint8_t const desc_hs_configuration[] = { // Config number, interface count, string index, total length, attribute, power in mA - TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100), + TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100), // Interface number, string index, EP Out & EP In address, EP size TUD_MIDI_DESCRIPTOR(ITF_NUM_MIDI, 0, EPNUM_MIDI, 0x80 | EPNUM_MIDI, 512) diff --git a/examples/device/msc_dual_lun/src/usb_descriptors.c b/examples/device/msc_dual_lun/src/usb_descriptors.c index 138de62a3..7e194ea7a 100644 --- a/examples/device/msc_dual_lun/src/usb_descriptors.c +++ b/examples/device/msc_dual_lun/src/usb_descriptors.c @@ -99,7 +99,7 @@ enum uint8_t const desc_fs_configuration[] = { // Config number, interface count, string index, total length, attribute, power in mA - TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100), + TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100), // Interface number, string index, EP Out & EP In address, EP size TUD_MSC_DESCRIPTOR(ITF_NUM_MSC, 0, EPNUM_MSC_OUT, EPNUM_MSC_IN, 64), @@ -109,7 +109,7 @@ uint8_t const desc_fs_configuration[] = uint8_t const desc_hs_configuration[] = { // Config number, interface count, string index, total length, attribute, power in mA - TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100), + TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100), // Interface number, string index, EP Out & EP In address, EP size TUD_MSC_DESCRIPTOR(ITF_NUM_MSC, 0, EPNUM_MSC_OUT, EPNUM_MSC_IN, 512), diff --git a/examples/device/uac2_headset/src/usb_descriptors.c b/examples/device/uac2_headset/src/usb_descriptors.c index 4a26b0b1e..64fa3c25b 100644 --- a/examples/device/uac2_headset/src/usb_descriptors.c +++ b/examples/device/uac2_headset/src/usb_descriptors.c @@ -98,7 +98,7 @@ uint8_t const * tud_descriptor_device_cb(void) uint8_t const desc_configuration[] = { // Interface count, string index, total length, attribute, power in mA - TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100), + TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100), // Interface number, string index, EP Out & EP In address, EP size TUD_AUDIO_HEADSET_STEREO_DESCRIPTOR(2, EPNUM_AUDIO_OUT, EPNUM_AUDIO_IN | 0x80) diff --git a/examples/device/usbtmc/src/usb_descriptors.c b/examples/device/usbtmc/src/usb_descriptors.c index 2336266b8..423482634 100644 --- a/examples/device/usbtmc/src/usb_descriptors.c +++ b/examples/device/usbtmc/src/usb_descriptors.c @@ -122,7 +122,7 @@ enum uint8_t const desc_configuration[] = { // Config number, interface count, string index, total length, attribute, power in mA - TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100), + TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100), TUD_USBTMC_DESC(ITF_NUM_USBTMC), }; diff --git a/examples/device/webusb_serial/src/usb_descriptors.c b/examples/device/webusb_serial/src/usb_descriptors.c index d1539488f..93e802a90 100644 --- a/examples/device/webusb_serial/src/usb_descriptors.c +++ b/examples/device/webusb_serial/src/usb_descriptors.c @@ -107,7 +107,7 @@ enum uint8_t const desc_configuration[] = { // Config number, interface count, string index, total length, attribute, power in mA - TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100), + TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100), // Interface number, string index, EP notification address and size, EP data address (out, in) and size. TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, 0x81, 8, EPNUM_CDC_OUT, 0x80 | EPNUM_CDC_IN, TUD_OPT_HIGH_SPEED ? 512 : 64), -- cgit v1.3.1 From 629da937f84854d76cd8da20daa4a80dd02e56e2 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 26 Aug 2021 17:55:31 +0700 Subject: slightly change the keyboard descriptor template to pass usb compliant test --- src/class/hid/hid_device.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/src/class/hid/hid_device.h b/src/class/hid/hid_device.h index e2c950dd1..5cf4b3060 100644 --- a/src/class/hid/hid_device.h +++ b/src/class/hid/hid_device.h @@ -195,16 +195,7 @@ static inline bool tud_hid_gamepad_report(uint8_t report_id, int8_t x, int8_t y HID_REPORT_COUNT ( 1 ) ,\ HID_REPORT_SIZE ( 8 ) ,\ HID_INPUT ( HID_CONSTANT ) ,\ - /* 6-byte Keycodes */ \ - HID_USAGE_PAGE ( HID_USAGE_PAGE_KEYBOARD ) ,\ - HID_USAGE_MIN ( 0 ) ,\ - HID_USAGE_MAX_N ( 255, 2 ) ,\ - HID_LOGICAL_MIN ( 0 ) ,\ - HID_LOGICAL_MAX_N( 255, 2 ) ,\ - HID_REPORT_COUNT ( 6 ) ,\ - HID_REPORT_SIZE ( 8 ) ,\ - HID_INPUT ( HID_DATA | HID_ARRAY | HID_ABSOLUTE ) ,\ - /* 5-bit LED Indicator Kana | Compose | ScrollLock | CapsLock | NumLock */ \ + /* Output 5-bit LED Indicator Kana | Compose | ScrollLock | CapsLock | NumLock */ \ HID_USAGE_PAGE ( HID_USAGE_PAGE_LED ) ,\ HID_USAGE_MIN ( 1 ) ,\ HID_USAGE_MAX ( 5 ) ,\ @@ -215,6 +206,15 @@ static inline bool tud_hid_gamepad_report(uint8_t report_id, int8_t x, int8_t y HID_REPORT_COUNT ( 1 ) ,\ HID_REPORT_SIZE ( 3 ) ,\ HID_OUTPUT ( HID_CONSTANT ) ,\ + /* 6-byte Keycodes */ \ + HID_USAGE_PAGE ( HID_USAGE_PAGE_KEYBOARD ) ,\ + HID_USAGE_MIN ( 0 ) ,\ + HID_USAGE_MAX_N ( 255, 2 ) ,\ + HID_LOGICAL_MIN ( 0 ) ,\ + HID_LOGICAL_MAX_N( 255, 2 ) ,\ + HID_REPORT_COUNT ( 6 ) ,\ + HID_REPORT_SIZE ( 8 ) ,\ + HID_INPUT ( HID_DATA | HID_ARRAY | HID_ABSOLUTE ) ,\ HID_COLLECTION_END \ // Mouse Report Descriptor Template -- cgit v1.3.1 From 9394de6ae74cf01ba8c8f1dab57dbbdfad6d6407 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 27 Aug 2021 12:38:41 +0700 Subject: update msc driver to pass MSC BOT error recovery compliant test --- examples/device/cdc_msc/src/msc_disk.c | 11 ++ examples/device/msc_dual_lun/src/msc_disk_dual.c | 11 ++ src/class/msc/msc_device.c | 137 +++++++++++++++++------ src/class/msc/msc_device.h | 2 +- src/common/tusb_common.h | 7 +- src/device/usbd.c | 7 +- 6 files changed, 136 insertions(+), 39 deletions(-) diff --git a/examples/device/cdc_msc/src/msc_disk.c b/examples/device/cdc_msc/src/msc_disk.c index 503baace9..32f2563cb 100644 --- a/examples/device/cdc_msc/src/msc_disk.c +++ b/examples/device/cdc_msc/src/msc_disk.c @@ -194,6 +194,17 @@ int32_t tud_msc_read10_cb(uint8_t lun, uint32_t lba, uint32_t offset, void* buff return bufsize; } +bool tud_msc_is_writable_cb (uint8_t lun) +{ + (void) lun; + +#ifdef CFG_EXAMPLE_MSC_READONLY + return false; +#else + return true; +#endif +} + // Callback invoked when received WRITE10 command. // Process data in buffer to disk's storage and return number of written bytes int32_t tud_msc_write10_cb(uint8_t lun, uint32_t lba, uint32_t offset, uint8_t* buffer, uint32_t bufsize) diff --git a/examples/device/msc_dual_lun/src/msc_disk_dual.c b/examples/device/msc_dual_lun/src/msc_disk_dual.c index 2ab050da8..cc7dfae0e 100644 --- a/examples/device/msc_dual_lun/src/msc_disk_dual.c +++ b/examples/device/msc_dual_lun/src/msc_disk_dual.c @@ -274,6 +274,17 @@ int32_t tud_msc_read10_cb(uint8_t lun, uint32_t lba, uint32_t offset, void* buff return bufsize; } +bool tud_msc_is_writable_cb (uint8_t lun) +{ + (void) lun; + +#ifdef CFG_EXAMPLE_MSC_READONLY + return false; +#else + return true; +#endif +} + // Callback invoked when received WRITE10 command. // Process data in buffer to disk's storage and return number of written bytes int32_t tud_msc_write10_cb(uint8_t lun, uint32_t lba, uint32_t offset, uint8_t* buffer, uint32_t bufsize) diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c index 014e8b69e..9e3689d84 100644 --- a/src/class/msc/msc_device.c +++ b/src/class/msc/msc_device.c @@ -46,7 +46,8 @@ enum MSC_STAGE_CMD = 0, MSC_STAGE_DATA, MSC_STAGE_STATUS, - MSC_STAGE_STATUS_SENT + MSC_STAGE_STATUS_SENT, + MSC_STAGE_NEED_RESET, }; typedef struct @@ -174,35 +175,91 @@ uint16_t mscd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint1 TU_ASSERT( usbd_open_edpt_pair(rhport, tu_desc_next(itf_desc), 2, TUSB_XFER_BULK, &p_msc->ep_out, &p_msc->ep_in), 0 ); // Prepare for Command Block Wrapper - if ( !usbd_edpt_xfer(rhport, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t)) ) - { - TU_LOG_FAILED(); - TU_BREAKPOINT(); - } + TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t)), drv_len); return drv_len; } +static void process_bot_reset(mscd_interface_t* p_msc) +{ + p_msc->stage = MSC_STAGE_CMD; + p_msc->total_len = 0; + p_msc->xferred_len = 0; + + p_msc->sense_key = 0; + p_msc->add_sense_code = 0; + p_msc->add_sense_qualifier = 0; +} + + // Invoked when a control transfer occurred on an interface of this class // Driver response accordingly to the request and the transfer stage (setup/data/ack) // return false to stall control endpoint (e.g unsupported request) -bool mscd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * p_request) +bool mscd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request) { // nothing to do with DATA & ACK stage if (stage != CONTROL_STAGE_SETUP) return true; - // Handle class request only - TU_VERIFY(p_request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS); + mscd_interface_t* p_msc = &_mscd_itf; + + // Clear Endpoint Feature (stall) for recovery + if ( TUSB_REQ_TYPE_STANDARD == request->bmRequestType_bit.type && + TUSB_REQ_RCPT_ENDPOINT == request->bmRequestType_bit.recipient && + TUSB_REQ_CLEAR_FEATURE == request->bRequest && + TUSB_REQ_FEATURE_EDPT_HALT == request->wValue ) + { + uint8_t const ep_addr = tu_u16_low(request->wIndex); + + if ( p_msc->stage == MSC_STAGE_NEED_RESET ) + { + // reset recovery is required to recover from this stage + // Clear Stall request cannot resolve this -> continue to stall endpoint + usbd_edpt_stall(rhport, ep_addr); + } + else + { + if ( ep_addr == p_msc->ep_in ) + { + if ( p_msc->stage == MSC_STAGE_STATUS ) + { + // resume sending SCSI status if we are in this stage previously before stalled + p_msc->stage = MSC_STAGE_STATUS_SENT; + TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_in , (uint8_t*) &p_msc->csw, sizeof(msc_csw_t)) ); + } + } + else if ( ep_addr == p_msc->ep_out ) + { + if ( p_msc->stage == MSC_STAGE_CMD ) + { + // part of reset recovery (probably due to invalid CBW) -> prepare for new command + TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t)) ); + } + } + } + + return true; + } + + // From this point only handle class request only + TU_VERIFY(request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS); - switch ( p_request->bRequest ) + switch ( request->bRequest ) { case MSC_REQ_RESET: - // TODO: Actually reset interface. - tud_control_status(rhport, p_request); + TU_LOG(MSC_DEBUG, " MSC BOT Reset\r\n"); + TU_VERIFY(request->wValue == 0 && request->wLength == 0); + + // driver state reset + process_bot_reset(p_msc); + + tud_control_status(rhport, request); break; case MSC_REQ_GET_MAX_LUN: { + TU_LOG(MSC_DEBUG, " MSC Get Max Lun\r\n"); + TU_VERIFY(request->wValue == 0 && request->wLength == 1); + uint8_t maxlun = 1; if (tud_msc_get_maxlun_cb) maxlun = tud_msc_get_maxlun_cb(); TU_VERIFY(maxlun); @@ -210,7 +267,7 @@ bool mscd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t // MAX LUN is minus 1 by specs maxlun--; - tud_control_xfer(rhport, p_request, &maxlun, 1); + tud_control_xfer(rhport, request, &maxlun, 1); } break; @@ -222,6 +279,8 @@ bool mscd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes) { + (void) event; + mscd_interface_t* p_msc = &_mscd_itf; msc_cbw_t const * p_cbw = &p_msc->cbw; msc_csw_t * p_csw = &p_msc->csw; @@ -233,11 +292,20 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t // Complete IN while waiting for CMD is usually Status of previous SCSI op, ignore it if(ep_addr != p_msc->ep_out) return true; - TU_ASSERT( event == XFER_RESULT_SUCCESS && - xferred_bytes == sizeof(msc_cbw_t) && p_cbw->signature == MSC_CBW_SIGNATURE ); + if ( !(xferred_bytes == sizeof(msc_cbw_t) && p_cbw->signature == MSC_CBW_SIGNATURE) ) + { + // BOT 6.6.1 If CBW is not valid stall both endpoints until reset recovery + p_msc->stage = MSC_STAGE_NEED_RESET; + + // invalid CBW stall both endpoints + usbd_edpt_stall(rhport, p_msc->ep_in); + usbd_edpt_stall(rhport, p_msc->ep_out); + + return false; + } TU_LOG(MSC_DEBUG, " SCSI Command: %s\r\n", tu_lookup_find(&_msc_scsi_cmd_table, p_cbw->command[0])); - // TU_LOG_MEM(MSC_DEBUG, p_cbw, xferred_bytes, 2); + //TU_LOG_MEM(MSC_DEBUG, p_cbw, xferred_bytes, 2); p_csw->signature = MSC_CSW_SIGNATURE; p_csw->tag = p_cbw->tag; @@ -440,15 +508,8 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t if ( p_msc->stage == MSC_STAGE_STATUS ) { - // Either endpoints is stalled, need to wait until it is cleared by host - if ( usbd_edpt_stalled(rhport, p_msc->ep_in) || usbd_edpt_stalled(rhport, p_msc->ep_out) ) - { - // simulate an transfer complete with adjusted parameters --> this driver callback will fired again - // and response with status phase after halted endpoints are cleared. - // note: use ep_out to prevent confusing with STATUS complete - dcd_event_xfer_complete(rhport, p_msc->ep_out, 0, XFER_RESULT_SUCCESS, false); - } - else + // skip status if epin is currently stalled, will do it when received Clear Stall request + if ( !usbd_edpt_stalled(rhport, p_msc->ep_in) ) { // Move to Status Sent stage p_msc->stage = MSC_STAGE_STATUS_SENT; @@ -600,9 +661,11 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_ }; bool writable = true; - if (tud_msc_is_writable_cb) { - writable = tud_msc_is_writable_cb(lun); + if ( tud_msc_is_writable_cb ) + { + writable = tud_msc_is_writable_cb(lun); } + mode_resp.write_protected = !writable; resplen = sizeof(mode_resp); @@ -660,7 +723,8 @@ static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc) if ( nbytes < 0 ) { - // negative means error -> pipe is stalled & status in CSW set to failed + // negative means error -> endpoint is stalled & status in CSW set to failed + p_msc->stage = MSC_STAGE_STATUS; p_csw->data_residue = p_cbw->total_bytes - p_msc->xferred_len; p_csw->status = MSC_CSW_STATUS_FAILED; @@ -682,15 +746,22 @@ static void proc_write10_cmd(uint8_t rhport, mscd_interface_t* p_msc) { msc_cbw_t const * p_cbw = &p_msc->cbw; bool writable = true; - if (tud_msc_is_writable_cb) { + + if ( tud_msc_is_writable_cb ) + { writable = tud_msc_is_writable_cb(p_cbw->lun); } - if (!writable) { - msc_csw_t* p_csw = &p_msc->csw; + + if ( !writable ) + { + // Not writable, complete this SCSI op with error + msc_csw_t *p_csw = &p_msc->csw; + + p_msc->stage = MSC_STAGE_STATUS; + p_csw->status = MSC_CSW_STATUS_FAILED; p_csw->data_residue = p_cbw->total_bytes; - p_csw->status = MSC_CSW_STATUS_FAILED; - tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_DATA_PROTECT, 0x27, 0x00); // Sense = Write protected + tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_DATA_PROTECT, 0x27, 0x00); // Sense = Write protected usbd_edpt_stall(rhport, p_msc->ep_out); return; } diff --git a/src/class/msc/msc_device.h b/src/class/msc/msc_device.h index 8f90ef4ad..d32694340 100644 --- a/src/class/msc/msc_device.h +++ b/src/class/msc/msc_device.h @@ -140,7 +140,7 @@ TU_ATTR_WEAK void tud_msc_write10_complete_cb(uint8_t lun); // Invoked when command in tud_msc_scsi_cb is complete TU_ATTR_WEAK void tud_msc_scsi_complete_cb(uint8_t lun, uint8_t const scsi_cmd[16]); -// Hook to make a mass storage device read-only. TODO remove +// Invoked to check if device is writable as part of SCSI WRITE10 TU_ATTR_WEAK bool tud_msc_is_writable_cb(uint8_t lun); //--------------------------------------------------------------------+ diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h index c2356ffee..1452e0105 100644 --- a/src/common/tusb_common.h +++ b/src/common/tusb_common.h @@ -369,12 +369,17 @@ typedef struct static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint32_t key) { + static char not_found[10]; + for(uint16_t i=0; icount; i++) { if (p_table->items[i].key == key) return p_table->items[i].data; } - return NULL; + // not found return the key value in hex + sprintf(not_found, "0x%08lX", key); + + return not_found; } #endif // CFG_TUSB_DEBUG diff --git a/src/device/usbd.c b/src/device/usbd.c index b2babb7a0..7cd8fad42 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -695,7 +695,7 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const if ( _usbd_dev.cfg_num ) { // already configured: need to clear all endpoints and driver first - TU_LOG(USBD_DBG, "Clear current config (%u) before switching\r\n", _usbd_dev.cfg_num); + TU_LOG(USBD_DBG, " Clear current Configuration (%u) before switching\r\n", _usbd_dev.cfg_num); // close all non-control endpoints, cancel all pending transfers if any dcd_edpt_close_all(rhport); @@ -1333,7 +1333,7 @@ bool usbd_edpt_busy(uint8_t rhport, uint8_t ep_addr) void usbd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { - TU_LOG(USBD_DBG, " Stall EP %02X", ep_addr); + TU_LOG(USBD_DBG, " Stall EP %02X\r\n", ep_addr); uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); @@ -1345,12 +1345,11 @@ void usbd_edpt_stall(uint8_t rhport, uint8_t ep_addr) void usbd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { - TU_LOG(USBD_DBG, " Clear Stall EP %02X", ep_addr); + TU_LOG(USBD_DBG, " Clear Stall EP %02X\r\n", ep_addr); uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); - dcd_edpt_clear_stall(rhport, ep_addr); _usbd_dev.ep_status[epnum][dir].stalled = false; _usbd_dev.ep_status[epnum][dir].busy = false; -- cgit v1.3.1 From 032770682ee856a32d0087ae9fd9a04c03e2bd0e Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 27 Aug 2021 13:18:51 +0700 Subject: minor clean up --- src/class/msc/msc_device.c | 36 +++++++++++++++++++----------------- 1 file changed, 19 insertions(+), 17 deletions(-) diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c index 9e3689d84..c0ea5ae40 100644 --- a/src/class/msc/msc_device.c +++ b/src/class/msc/msc_device.c @@ -99,6 +99,18 @@ static inline uint16_t rdwr10_get_blockcount(uint8_t const command[]) return tu_ntohs(block_count); } +static inline bool send_csw(uint8_t rhport, mscd_interface_t* p_msc) +{ + p_msc->stage = MSC_STAGE_STATUS_SENT; + return usbd_edpt_xfer(rhport, p_msc->ep_in , (uint8_t*) &p_msc->csw, sizeof(msc_csw_t)); +} + +static inline bool prepare_cbw(uint8_t rhport, mscd_interface_t* p_msc) +{ + p_msc->stage = MSC_STAGE_CMD; + return usbd_edpt_xfer(rhport, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t)); +} + //--------------------------------------------------------------------+ // Debug //--------------------------------------------------------------------+ @@ -175,12 +187,12 @@ uint16_t mscd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint1 TU_ASSERT( usbd_open_edpt_pair(rhport, tu_desc_next(itf_desc), 2, TUSB_XFER_BULK, &p_msc->ep_out, &p_msc->ep_in), 0 ); // Prepare for Command Block Wrapper - TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t)), drv_len); + TU_ASSERT( prepare_cbw(rhport, p_msc), drv_len); return drv_len; } -static void process_bot_reset(mscd_interface_t* p_msc) +static void proc_bot_reset(mscd_interface_t* p_msc) { p_msc->stage = MSC_STAGE_CMD; p_msc->total_len = 0; @@ -191,7 +203,6 @@ static void process_bot_reset(mscd_interface_t* p_msc) p_msc->add_sense_qualifier = 0; } - // Invoked when a control transfer occurred on an interface of this class // Driver response accordingly to the request and the transfer stage (setup/data/ack) // return false to stall control endpoint (e.g unsupported request) @@ -223,8 +234,7 @@ bool mscd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t if ( p_msc->stage == MSC_STAGE_STATUS ) { // resume sending SCSI status if we are in this stage previously before stalled - p_msc->stage = MSC_STAGE_STATUS_SENT; - TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_in , (uint8_t*) &p_msc->csw, sizeof(msc_csw_t)) ); + TU_ASSERT( send_csw(rhport, p_msc) ); } } else if ( ep_addr == p_msc->ep_out ) @@ -232,7 +242,7 @@ bool mscd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t if ( p_msc->stage == MSC_STAGE_CMD ) { // part of reset recovery (probably due to invalid CBW) -> prepare for new command - TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t)) ); + TU_ASSERT( prepare_cbw(rhport, p_msc) ); } } } @@ -250,7 +260,7 @@ bool mscd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t TU_VERIFY(request->wValue == 0 && request->wLength == 0); // driver state reset - process_bot_reset(p_msc); + proc_bot_reset(p_msc); tud_control_status(rhport, request); break; @@ -495,11 +505,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t break; } - // Move to default CMD stage - p_msc->stage = MSC_STAGE_CMD; - - // Queue for the next CBW - TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t)) ); + TU_ASSERT( prepare_cbw(rhport, p_msc) ); } break; @@ -511,11 +517,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t // skip status if epin is currently stalled, will do it when received Clear Stall request if ( !usbd_edpt_stalled(rhport, p_msc->ep_in) ) { - // Move to Status Sent stage - p_msc->stage = MSC_STAGE_STATUS_SENT; - - // Send SCSI Status - TU_ASSERT(usbd_edpt_xfer(rhport, p_msc->ep_in , (uint8_t*) &p_msc->csw, sizeof(msc_csw_t))); + TU_ASSERT( send_csw(rhport, p_msc) ); } } -- cgit v1.3.1 From 893dceb1984d6304918a45ec8be5a63d3e9993ca Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 27 Aug 2021 17:30:02 +0700 Subject: refactor msc device --- src/class/msc/msc_device.c | 271 +++++++++++++++++++++++++++------------------ 1 file changed, 162 insertions(+), 109 deletions(-) diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c index c0ea5ae40..716b7e503 100644 --- a/src/class/msc/msc_device.c +++ b/src/class/msc/msc_device.c @@ -79,25 +79,9 @@ CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t _mscd_buf[CFG_TUD_MSC_EP_ //--------------------------------------------------------------------+ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_t* buffer, uint32_t bufsize); static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc); -static void proc_write10_cmd(uint8_t rhport, mscd_interface_t* p_msc); - -static inline uint32_t rdwr10_get_lba(uint8_t const command[]) -{ - // use offsetof to avoid pointer to the odd/unaligned address - uint32_t const lba = tu_unaligned_read32(command + offsetof(scsi_write10_t, lba)); - - // lba is in Big Endian - return tu_ntohl(lba); -} - -static inline uint16_t rdwr10_get_blockcount(uint8_t const command[]) -{ - // use offsetof to avoid pointer to the odd/misaligned address - uint16_t const block_count = tu_unaligned_read16(command + offsetof(scsi_write10_t, block_count)); - // block count is in Big Endian - return tu_ntohs(block_count); -} +static void proc_write10_cmd(uint8_t rhport, mscd_interface_t* p_msc); +static void proc_write10_new_data(uint8_t rhport, mscd_interface_t* p_msc, uint32_t xferred_bytes); static inline bool send_csw(uint8_t rhport, mscd_interface_t* p_msc) { @@ -111,6 +95,20 @@ static inline bool prepare_cbw(uint8_t rhport, mscd_interface_t* p_msc) return usbd_edpt_xfer(rhport, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t)); } +static void fail_scsi_op(uint8_t rhport, mscd_interface_t* p_msc, uint8_t status) +{ + msc_cbw_t const * p_cbw = &p_msc->cbw; + msc_csw_t * p_csw = &p_msc->csw; + + p_csw->status = status; + p_csw->data_residue = p_cbw->total_bytes - p_msc->xferred_len; + + p_msc->stage = MSC_STAGE_STATUS; + + // failed but sense key is not set: default to Illegal Request + if ( p_msc->sense_key == 0 ) tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00); +} + //--------------------------------------------------------------------+ // Debug //--------------------------------------------------------------------+ @@ -358,12 +356,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t if ( resplen < 0 ) { - p_msc->total_len = 0; - p_csw->status = MSC_CSW_STATUS_FAILED; - p_msc->stage = MSC_STAGE_STATUS; - - // failed but senskey is not set: default to Illegal Request - if ( p_msc->sense_key == 0 ) tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00); + fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED); // Stall bulk In if needed if (p_cbw->total_bytes) usbd_edpt_stall(rhport, p_msc->ep_in); @@ -390,10 +383,27 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t TU_LOG(MSC_DEBUG, " SCSI Data\r\n"); //TU_LOG_MEM(MSC_DEBUG, _mscd_buf, xferred_bytes, 2); - // OUT transfer, invoke callback if needed - if ( !tu_bit_test(p_cbw->dir, 7) ) + if (SCSI_CMD_READ_10 == p_cbw->command[0]) + { + p_msc->xferred_len += xferred_bytes; + + if ( p_msc->xferred_len >= p_msc->total_len ) + { + // Data Stage is complete + p_msc->stage = MSC_STAGE_STATUS; + }else + { + proc_read10_cmd(rhport, p_msc); + } + } + else if (SCSI_CMD_WRITE_10 == p_cbw->command[0]) + { + proc_write10_new_data(rhport, p_msc, xferred_bytes); + } + else { - if ( SCSI_CMD_WRITE_10 != p_cbw->command[0] ) + // OUT transfer, invoke callback if needed + if ( !tu_bit_test(p_cbw->dir, 7) ) { int32_t cb_result = tud_msc_scsi_cb(p_cbw->lun, p_cbw->command, _mscd_buf, p_msc->total_len); @@ -406,74 +416,46 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t p_csw->status = MSC_CSW_STATUS_PASSED; } } - else - { - uint16_t const block_sz = p_cbw->total_bytes / rdwr10_get_blockcount(p_cbw->command); - - // Adjust lba with transferred bytes - uint32_t const lba = rdwr10_get_lba(p_cbw->command) + (p_msc->xferred_len / block_sz); - - // Application can consume smaller bytes - int32_t nbytes = tud_msc_write10_cb(p_cbw->lun, lba, p_msc->xferred_len % block_sz, _mscd_buf, xferred_bytes); - - if ( nbytes < 0 ) - { - // negative means error -> skip to status phase, status in CSW set to failed - p_csw->data_residue = p_cbw->total_bytes - p_msc->xferred_len; - p_csw->status = MSC_CSW_STATUS_FAILED; - p_msc->stage = MSC_STAGE_STATUS; - - tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00); // Sense = Invalid Command Operation - break; - }else - { - // Application consume less than what we got (including zero) - if ( nbytes < (int32_t) xferred_bytes ) - { - if ( nbytes > 0 ) - { - p_msc->xferred_len += nbytes; - memmove(_mscd_buf, _mscd_buf+nbytes, xferred_bytes-nbytes); - } - - // simulate an transfer complete with adjusted parameters --> this driver callback will fired again - dcd_event_xfer_complete(rhport, p_msc->ep_out, xferred_bytes-nbytes, XFER_RESULT_SUCCESS, false); - - return true; // skip the rest - } - else - { - // Application consume all bytes in our buffer. Nothing to do, process with normal flow - } - } - } - } - // Accumulate data so far - p_msc->xferred_len += xferred_bytes; + p_msc->xferred_len += xferred_bytes; - if ( p_msc->xferred_len >= p_msc->total_len ) - { - // Data Stage is complete - p_msc->stage = MSC_STAGE_STATUS; - } - else - { - // READ10 & WRITE10 Can be executed with large bulk of data e.g write 8K bytes (several flash write) - // We break it into multiple smaller command whose data size is up to CFG_TUD_MSC_EP_BUFSIZE - if (SCSI_CMD_READ_10 == p_cbw->command[0]) + if ( p_msc->xferred_len >= p_msc->total_len ) { - proc_read10_cmd(rhport, p_msc); + // Data Stage is complete + p_msc->stage = MSC_STAGE_STATUS; } - else if (SCSI_CMD_WRITE_10 == p_cbw->command[0]) - { - proc_write10_cmd(rhport, p_msc); - }else + else { - // No other command take more than one transfer yet -> unlikely error + // No command take more than one transfer yet -> unlikely error TU_BREAKPOINT(); } } + +// // Accumulate data so far +// p_msc->xferred_len += xferred_bytes; +// +// if ( p_msc->xferred_len >= p_msc->total_len ) +// { +// // Data Stage is complete +// p_msc->stage = MSC_STAGE_STATUS; +// } +// else +// { +// // READ10 & WRITE10 Can be executed with large bulk of data e.g write 8K bytes (several flash write) +// // We break it into multiple smaller command whose data size is up to CFG_TUD_MSC_EP_BUFSIZE +// if (SCSI_CMD_READ_10 == p_cbw->command[0]) +// { +// proc_read10_cmd(rhport, p_msc); +// } +// else if (SCSI_CMD_WRITE_10 == p_cbw->command[0]) +// { +// proc_write10_cmd(rhport, p_msc); +// }else +// { +// // No other command take more than one transfer yet -> unlikely error +// TU_BREAKPOINT(); +// } +// } break; case MSC_STAGE_STATUS: @@ -535,6 +517,8 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_ (void) bufsize; // TODO refractor later int32_t resplen; + mscd_interface_t* p_msc = &_mscd_itf; + switch ( scsi_cmd[0] ) { case SCSI_CMD_TEST_UNIT_READY: @@ -545,7 +529,7 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_ resplen = - 1; // If sense key is not set by callback, default to Logical Unit Not Ready, Cause Not Reportable - if ( _mscd_itf.sense_key == 0 ) tud_msc_set_sense(lun, SCSI_SENSE_NOT_READY, 0x04, 0x00); + if ( p_msc->sense_key == 0 ) tud_msc_set_sense(lun, SCSI_SENSE_NOT_READY, 0x04, 0x00); } break; @@ -561,7 +545,7 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_ resplen = - 1; // If sense key is not set by callback, default to Logical Unit Not Ready, Cause Not Reportable - if ( _mscd_itf.sense_key == 0 ) tud_msc_set_sense(lun, SCSI_SENSE_NOT_READY, 0x04, 0x00); + if ( p_msc->sense_key == 0 ) tud_msc_set_sense(lun, SCSI_SENSE_NOT_READY, 0x04, 0x00); } } break; @@ -582,7 +566,7 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_ resplen = -1; // If sense key is not set by callback, default to Logical Unit Not Ready, Cause Not Reportable - if ( _mscd_itf.sense_key == 0 ) tud_msc_set_sense(lun, SCSI_SENSE_NOT_READY, 0x04, 0x00); + if ( p_msc->sense_key == 0 ) tud_msc_set_sense(lun, SCSI_SENSE_NOT_READY, 0x04, 0x00); }else { scsi_read_capacity10_resp_t read_capa10; @@ -618,7 +602,7 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_ resplen = -1; // If sense key is not set by callback, default to Logical Unit Not Ready, Cause Not Reportable - if ( _mscd_itf.sense_key == 0 ) tud_msc_set_sense(lun, SCSI_SENSE_NOT_READY, 0x04, 0x00); + if ( p_msc->sense_key == 0 ) tud_msc_set_sense(lun, SCSI_SENSE_NOT_READY, 0x04, 0x00); }else { read_fmt_capa.block_num = tu_htonl(block_count); @@ -685,9 +669,9 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_ sense_rsp.add_sense_len = sizeof(scsi_sense_fixed_resp_t) - 8; - sense_rsp.sense_key = _mscd_itf.sense_key; - sense_rsp.add_sense_code = _mscd_itf.add_sense_code; - sense_rsp.add_sense_qualifier = _mscd_itf.add_sense_qualifier; + sense_rsp.sense_key = p_msc->sense_key; + sense_rsp.add_sense_code = p_msc->add_sense_code; + sense_rsp.add_sense_qualifier = p_msc->add_sense_qualifier; resplen = sizeof(sense_rsp); memcpy(buffer, &sense_rsp, resplen); @@ -703,15 +687,33 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_ return resplen; } + +static inline uint32_t rdwr10_get_lba(uint8_t const command[]) +{ + // use offsetof to avoid pointer to the odd/unaligned address + uint32_t const lba = tu_unaligned_read32(command + offsetof(scsi_write10_t, lba)); + + // lba is in Big Endian + return tu_ntohl(lba); +} + +static inline uint16_t rdwr10_get_blocksize(msc_cbw_t const* cbw) +{ + // first extract block count in the command + uint16_t block_count = tu_unaligned_read16(cbw->command + offsetof(scsi_write10_t, block_count)); + block_count = tu_ntohs(block_count); + + // invalid block count + if (block_count == 0) return 0; + + return cbw->total_bytes / block_count; +} + static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc) { msc_cbw_t const * p_cbw = &p_msc->cbw; - msc_csw_t * p_csw = &p_msc->csw; - - uint16_t const block_cnt = rdwr10_get_blockcount(p_cbw->command); - TU_ASSERT(block_cnt, ); // prevent div by zero - uint16_t const block_sz = p_cbw->total_bytes / block_cnt; + uint16_t const block_sz = rdwr10_get_blocksize(p_cbw); TU_ASSERT(block_sz, ); // prevent div by zero // Adjust lba with transferred bytes @@ -726,11 +728,11 @@ static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc) if ( nbytes < 0 ) { // negative means error -> endpoint is stalled & status in CSW set to failed - p_msc->stage = MSC_STAGE_STATUS; - p_csw->data_residue = p_cbw->total_bytes - p_msc->xferred_len; - p_csw->status = MSC_CSW_STATUS_FAILED; - tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00); // Sense = Invalid Command Operation + // Sense = Flash not ready for access + tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_MEDIUM_ERROR, 0x33, 0x00); + + fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED); usbd_edpt_stall(rhport, p_msc->ep_in); } else if ( nbytes == 0 ) @@ -757,13 +759,10 @@ static void proc_write10_cmd(uint8_t rhport, mscd_interface_t* p_msc) if ( !writable ) { // Not writable, complete this SCSI op with error - msc_csw_t *p_csw = &p_msc->csw; - - p_msc->stage = MSC_STAGE_STATUS; - p_csw->status = MSC_CSW_STATUS_FAILED; - p_csw->data_residue = p_cbw->total_bytes; + // Sense = Write protected + tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_DATA_PROTECT, 0x27, 0x00); - tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_DATA_PROTECT, 0x27, 0x00); // Sense = Write protected + fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED); usbd_edpt_stall(rhport, p_msc->ep_out); return; } @@ -775,4 +774,58 @@ static void proc_write10_cmd(uint8_t rhport, mscd_interface_t* p_msc) TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_out, _mscd_buf, nbytes), ); } +// process new data arrived from WRITE10 +static void proc_write10_new_data(uint8_t rhport, mscd_interface_t* p_msc, uint32_t xferred_bytes) +{ + msc_cbw_t const * p_cbw = &p_msc->cbw; + + uint16_t const block_sz = rdwr10_get_blocksize(p_cbw); + TU_ASSERT(block_sz, ); // prevent div by zero + + // Adjust lba with transferred bytes + uint32_t const lba = rdwr10_get_lba(p_cbw->command) + (p_msc->xferred_len / block_sz); + + // Application can consume smaller bytes + int32_t nbytes = tud_msc_write10_cb(p_cbw->lun, lba, p_msc->xferred_len % block_sz, _mscd_buf, xferred_bytes); + + if ( nbytes < 0 ) + { + // negative means error -> failed this scsi op + + // Sense = Flash not ready for access + tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_MEDIUM_ERROR, 0x33, 0x00); + + fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED); + usbd_edpt_stall(rhport, p_msc->ep_out); + }else + { + // Application consume less than what we got (including zero) + if ( nbytes < (int32_t) xferred_bytes ) + { + if ( nbytes > 0 ) + { + p_msc->xferred_len += nbytes; + memmove(_mscd_buf, _mscd_buf+nbytes, xferred_bytes-nbytes); + } + + // simulate an transfer complete with adjusted parameters --> this driver callback will fired again + dcd_event_xfer_complete(rhport, p_msc->ep_out, xferred_bytes-nbytes, XFER_RESULT_SUCCESS, false); + } + else + { + // Application consume all bytes in our buffer, prepare to receive more data from host + p_msc->xferred_len += xferred_bytes; + + if ( p_msc->xferred_len >= p_msc->total_len ) + { + // Data Stage is complete + p_msc->stage = MSC_STAGE_STATUS; + }else + { + proc_write10_cmd(rhport, p_msc); + } + } + } +} + #endif -- cgit v1.3.1 From 2667ce6981b409a0431a00d48a37f58bf3aa5875 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 27 Aug 2021 17:50:02 +0700 Subject: fix BOT case 2 test compliant --- src/class/msc/msc_device.c | 34 +++++++--------------------------- 1 file changed, 7 insertions(+), 27 deletions(-) diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c index 716b7e503..cc495a1c4 100644 --- a/src/class/msc/msc_device.c +++ b/src/class/msc/msc_device.c @@ -430,32 +430,6 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t TU_BREAKPOINT(); } } - -// // Accumulate data so far -// p_msc->xferred_len += xferred_bytes; -// -// if ( p_msc->xferred_len >= p_msc->total_len ) -// { -// // Data Stage is complete -// p_msc->stage = MSC_STAGE_STATUS; -// } -// else -// { -// // READ10 & WRITE10 Can be executed with large bulk of data e.g write 8K bytes (several flash write) -// // We break it into multiple smaller command whose data size is up to CFG_TUD_MSC_EP_BUFSIZE -// if (SCSI_CMD_READ_10 == p_cbw->command[0]) -// { -// proc_read10_cmd(rhport, p_msc); -// } -// else if (SCSI_CMD_WRITE_10 == p_cbw->command[0]) -// { -// proc_write10_cmd(rhport, p_msc); -// }else -// { -// // No other command take more than one transfer yet -> unlikely error -// TU_BREAKPOINT(); -// } -// } break; case MSC_STAGE_STATUS: @@ -714,7 +688,13 @@ static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc) msc_cbw_t const * p_cbw = &p_msc->cbw; uint16_t const block_sz = rdwr10_get_blocksize(p_cbw); - TU_ASSERT(block_sz, ); // prevent div by zero + + if ( block_sz == 0 ) + { + // 6.7.1 BOT The 13 Cases: case 2 and 3 when cbw->total_bytes == 0 + fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED); + return; + } // Adjust lba with transferred bytes uint32_t const lba = rdwr10_get_lba(p_cbw->command) + (p_msc->xferred_len / block_sz); -- cgit v1.3.1 From e01239ccc936d32cb2933dba3a78555d0e47d17c Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 27 Aug 2021 20:05:56 +0700 Subject: more msc refactoring --- src/class/msc/msc_device.c | 35 ++++++++++++++++++++++------------- 1 file changed, 22 insertions(+), 13 deletions(-) diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c index cc495a1c4..a25fa6109 100644 --- a/src/class/msc/msc_device.c +++ b/src/class/msc/msc_device.c @@ -107,6 +107,18 @@ static void fail_scsi_op(uint8_t rhport, mscd_interface_t* p_msc, uint8_t status // failed but sense key is not set: default to Illegal Request if ( p_msc->sense_key == 0 ) tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00); + + // If there is data stage, stall it + if ( p_cbw->total_bytes ) + { + if ( tu_bit_test(p_cbw->dir, 7) ) + { + usbd_edpt_stall(rhport, p_msc->ep_in); + }else + { + usbd_edpt_stall(rhport, p_msc->ep_out); + } + } } //--------------------------------------------------------------------+ @@ -343,12 +355,10 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_out, _mscd_buf, p_msc->total_len) ); }else { - int32_t resplen; - // First process if it is a built-in commands - resplen = proc_builtin_scsi(p_cbw->lun, p_cbw->command, _mscd_buf, sizeof(_mscd_buf)); + int32_t resplen = proc_builtin_scsi(p_cbw->lun, p_cbw->command, _mscd_buf, sizeof(_mscd_buf)); - // Not built-in, invoke user callback + // Invoke user callback if not built-in if ( (resplen < 0) && (p_msc->sense_key == 0) ) { resplen = tud_msc_scsi_cb(p_cbw->lun, p_cbw->command, _mscd_buf, p_msc->total_len); @@ -356,10 +366,8 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t if ( resplen < 0 ) { + // unsupported command fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED); - - // Stall bulk In if needed - if (p_cbw->total_bytes) usbd_edpt_stall(rhport, p_msc->ep_in); } else { @@ -692,7 +700,7 @@ static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc) if ( block_sz == 0 ) { // 6.7.1 BOT The 13 Cases: case 2 and 3 when cbw->total_bytes == 0 - fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED); + fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_PHASE_ERROR); return; } @@ -713,7 +721,6 @@ static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc) tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_MEDIUM_ERROR, 0x33, 0x00); fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED); - usbd_edpt_stall(rhport, p_msc->ep_in); } else if ( nbytes == 0 ) { @@ -741,9 +748,7 @@ static void proc_write10_cmd(uint8_t rhport, mscd_interface_t* p_msc) // Not writable, complete this SCSI op with error // Sense = Write protected tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_DATA_PROTECT, 0x27, 0x00); - fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED); - usbd_edpt_stall(rhport, p_msc->ep_out); return; } @@ -760,7 +765,12 @@ static void proc_write10_new_data(uint8_t rhport, mscd_interface_t* p_msc, uint3 msc_cbw_t const * p_cbw = &p_msc->cbw; uint16_t const block_sz = rdwr10_get_blocksize(p_cbw); - TU_ASSERT(block_sz, ); // prevent div by zero + if ( block_sz == 0 ) + { + // 6.7.1 BOT The 13 Cases: case 2 and 3 when cbw->total_bytes == 0 + fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_PHASE_ERROR); + return; + } // Adjust lba with transferred bytes uint32_t const lba = rdwr10_get_lba(p_cbw->command) + (p_msc->xferred_len / block_sz); @@ -776,7 +786,6 @@ static void proc_write10_new_data(uint8_t rhport, mscd_interface_t* p_msc, uint3 tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_MEDIUM_ERROR, 0x33, 0x00); fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED); - usbd_edpt_stall(rhport, p_msc->ep_out); }else { // Application consume less than what we got (including zero) -- cgit v1.3.1 From 81c73c235f477adf753ffe40c1d0192185d798ba Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 27 Aug 2021 22:30:30 +0700 Subject: implement dcd_edpt_close_all() for nrf52840 --- src/portable/nordic/nrf5x/dcd_nrf5x.c | 34 +++++++++++++++++++++++++++++++--- 1 file changed, 31 insertions(+), 3 deletions(-) diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c index efc4d3183..7dc5731ab 100644 --- a/src/portable/nordic/nrf5x/dcd_nrf5x.c +++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c @@ -366,8 +366,34 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) void dcd_edpt_close_all (uint8_t rhport) { - (void) rhport; - // TODO implement dcd_edpt_close_all() + // disable interrupt to prevent race condition + dcd_int_disable(rhport); + + // disable all non-control (bulk + interrupt) endpoints + for ( uint8_t ep = 1; ep < EP_CBI_COUNT; ep++ ) + { + NRF_USBD->INTENCLR = TU_BIT(USBD_INTEN_ENDEPOUT0_Pos + ep) | TU_BIT(USBD_INTEN_ENDEPIN0_Pos + ep); + + NRF_USBD->TASKS_STARTEPIN[ep] = 0; + NRF_USBD->TASKS_STARTEPOUT[ep] = 0; + + tu_memclr(_dcd.xfer[ep], 2*sizeof(xfer_td_t)); + } + + // disable both ISO + NRF_USBD->INTENCLR = USBD_INTENCLR_SOF_Msk | USBD_INTENCLR_ENDISOOUT_Msk | USBD_INTENCLR_ENDISOIN_Msk; + NRF_USBD->ISOSPLIT = USBD_ISOSPLIT_SPLIT_OneDir; + + NRF_USBD->TASKS_STARTISOIN = 0; + NRF_USBD->TASKS_STARTISOOUT = 0; + + tu_memclr(_dcd.xfer[EP_ISO_NUM], 2*sizeof(xfer_td_t)); + + // de-activate all non-control + NRF_USBD->EPOUTEN = 1UL; + NRF_USBD->EPINEN = 1UL; + + dcd_int_enable(rhport); } void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr) @@ -514,7 +540,9 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) void bus_reset(void) { // 6.35.6 USB controller automatically disabled all endpoints (except control) - // i.e EPOUTEN and EPINEN and reset USBADDR to 0 + NRF_USBD->EPOUTEN = 1UL; + NRF_USBD->EPINEN = 1UL; + for(int i=0; i<8; i++) { NRF_USBD->TASKS_STARTEPIN[i] = 0; -- cgit v1.3.1 From 8bad0af849f79f56940ba2d1ea3442b58c75861d Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 27 Aug 2021 22:31:08 +0700 Subject: explicitly clear stall and data toggle for edpoint upon open() --- src/portable/nordic/nrf5x/dcd_nrf5x.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c index 7dc5731ab..c962d9228 100644 --- a/src/portable/nordic/nrf5x/dcd_nrf5x.c +++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c @@ -306,8 +306,9 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) { (void) rhport; - uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress); - uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress); + uint8_t const ep_addr = desc_edpt->bEndpointAddress; + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); _dcd.xfer[epnum][dir].mps = desc_edpt->wMaxPacketSize.size; @@ -359,6 +360,11 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) NRF_USBD->EPINEN |= USBD_EPINEN_ISOIN_Msk; } } + + // clear stall and reset DataToggle + NRF_USBD->EPSTALL = (USBD_EPSTALL_STALL_UnStall << USBD_EPSTALL_STALL_Pos) | ep_addr; + NRF_USBD->DTOGGLE = (USBD_DTOGGLE_VALUE_Data0 << USBD_DTOGGLE_VALUE_Pos) | ep_addr; + __ISB(); __DSB(); return true; -- cgit v1.3.1 From c6b9f8a530e9dd9a6ec7e4f55016f275ddcdaa67 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 27 Aug 2021 23:33:11 +0700 Subject: fix msc case 3 complaint test --- src/class/msc/msc_device.c | 78 ++++++++++++++++++++++------------------------ 1 file changed, 37 insertions(+), 41 deletions(-) diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c index a25fa6109..11fc4e80f 100644 --- a/src/class/msc/msc_device.c +++ b/src/class/msc/msc_device.c @@ -121,6 +121,27 @@ static void fail_scsi_op(uint8_t rhport, mscd_interface_t* p_msc, uint8_t status } } +static inline uint32_t rdwr10_get_lba(uint8_t const command[]) +{ + // use offsetof to avoid pointer to the odd/unaligned address + uint32_t const lba = tu_unaligned_read32(command + offsetof(scsi_write10_t, lba)); + + // lba is in Big Endian + return tu_ntohl(lba); +} + +static inline uint16_t rdwr10_get_blocksize(msc_cbw_t const* cbw) +{ + // first extract block count in the command + uint16_t block_count = tu_unaligned_read16(cbw->command + offsetof(scsi_write10_t, block_count)); + block_count = tu_ntohs(block_count); + + // invalid block count + if (block_count == 0) return 0; + + return cbw->total_bytes / block_count; +} + //--------------------------------------------------------------------+ // Debug //--------------------------------------------------------------------+ @@ -336,13 +357,21 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t p_msc->total_len = p_cbw->total_bytes; p_msc->xferred_len = 0; - if (SCSI_CMD_READ_10 == p_cbw->command[0]) + if (SCSI_CMD_READ_10 == p_cbw->command[0] || SCSI_CMD_WRITE_10 == p_cbw->command[0]) { - proc_read10_cmd(rhport, p_msc); - } - else if (SCSI_CMD_WRITE_10 == p_cbw->command[0]) - { - proc_write10_cmd(rhport, p_msc); + if ( rdwr10_get_blocksize(p_cbw) == 0 ) + { + // Invalid CBW length == 0 (not match SCSI command block count) + // 6.7.1 BOT The 13 Cases: case 2 and case 3 -> phase error + fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_PHASE_ERROR); + } + else if (SCSI_CMD_READ_10 == p_cbw->command[0]) + { + proc_read10_cmd(rhport, p_msc); + }else + { + proc_write10_cmd(rhport, p_msc); + } } else { @@ -669,41 +698,13 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_ return resplen; } - -static inline uint32_t rdwr10_get_lba(uint8_t const command[]) -{ - // use offsetof to avoid pointer to the odd/unaligned address - uint32_t const lba = tu_unaligned_read32(command + offsetof(scsi_write10_t, lba)); - - // lba is in Big Endian - return tu_ntohl(lba); -} - -static inline uint16_t rdwr10_get_blocksize(msc_cbw_t const* cbw) -{ - // first extract block count in the command - uint16_t block_count = tu_unaligned_read16(cbw->command + offsetof(scsi_write10_t, block_count)); - block_count = tu_ntohs(block_count); - - // invalid block count - if (block_count == 0) return 0; - - return cbw->total_bytes / block_count; -} - static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc) { msc_cbw_t const * p_cbw = &p_msc->cbw; + // block size already verified not zero uint16_t const block_sz = rdwr10_get_blocksize(p_cbw); - if ( block_sz == 0 ) - { - // 6.7.1 BOT The 13 Cases: case 2 and 3 when cbw->total_bytes == 0 - fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_PHASE_ERROR); - return; - } - // Adjust lba with transferred bytes uint32_t const lba = rdwr10_get_lba(p_cbw->command) + (p_msc->xferred_len / block_sz); @@ -764,13 +765,8 @@ static void proc_write10_new_data(uint8_t rhport, mscd_interface_t* p_msc, uint3 { msc_cbw_t const * p_cbw = &p_msc->cbw; + // block size already verified not zero uint16_t const block_sz = rdwr10_get_blocksize(p_cbw); - if ( block_sz == 0 ) - { - // 6.7.1 BOT The 13 Cases: case 2 and 3 when cbw->total_bytes == 0 - fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_PHASE_ERROR); - return; - } // Adjust lba with transferred bytes uint32_t const lba = rdwr10_get_lba(p_cbw->command) + (p_msc->xferred_len / block_sz); -- cgit v1.3.1 From 53ea1e13243eae30455cc008eda0ee5d63ccf361 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 27 Aug 2021 23:52:59 +0700 Subject: fix msc test case 8 and 10 --- src/class/msc/msc_device.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c index 11fc4e80f..e29cd473a 100644 --- a/src/class/msc/msc_device.c +++ b/src/class/msc/msc_device.c @@ -357,17 +357,25 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t p_msc->total_len = p_cbw->total_bytes; p_msc->xferred_len = 0; - if (SCSI_CMD_READ_10 == p_cbw->command[0] || SCSI_CMD_WRITE_10 == p_cbw->command[0]) + if ( SCSI_CMD_READ_10 == p_cbw->command[0] ) { - if ( rdwr10_get_blocksize(p_cbw) == 0 ) + // Invalid CBW length == 0 or Direction bit is incorrect + // 6.7 The 13 Cases: case 2, case 3, case 10 -> phase error + if ( rdwr10_get_blocksize(p_cbw) == 0 || !tu_bit_test(p_cbw->dir, 7) ) { - // Invalid CBW length == 0 (not match SCSI command block count) - // 6.7.1 BOT The 13 Cases: case 2 and case 3 -> phase error fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_PHASE_ERROR); - } - else if (SCSI_CMD_READ_10 == p_cbw->command[0]) + }else { proc_read10_cmd(rhport, p_msc); + } + } + else if (SCSI_CMD_WRITE_10 == p_cbw->command[0]) + { + // Invalid CBW length == 0 or Direction bit is incorrect + // 6.7 The 13 Cases: case 2, case 3, case 8 -> phase error + if ( rdwr10_get_blocksize(p_cbw) == 0 || tu_bit_test(p_cbw->dir, 7) ) + { + fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_PHASE_ERROR); }else { proc_write10_cmd(rhport, p_msc); -- cgit v1.3.1 From a53839ef44345377e863e4635909c2dacc81f059 Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 28 Aug 2021 01:23:20 +0700 Subject: correct msc example return type of tud_msc_scsi_cb() --- examples/device/cdc_msc/src/msc_disk.c | 2 +- examples/device/cdc_msc_freertos/src/msc_disk.c | 2 +- examples/device/dynamic_configuration/src/msc_disk.c | 2 +- examples/device/msc_dual_lun/src/msc_disk_dual.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/examples/device/cdc_msc/src/msc_disk.c b/examples/device/cdc_msc/src/msc_disk.c index 32f2563cb..42b080cce 100644 --- a/examples/device/cdc_msc/src/msc_disk.c +++ b/examples/device/cdc_msc/src/msc_disk.c @@ -229,7 +229,7 @@ int32_t tud_msc_scsi_cb (uint8_t lun, uint8_t const scsi_cmd[16], void* buffer, // read10 & write10 has their own callback and MUST not be handled here void const* response = NULL; - uint16_t resplen = 0; + int32_t resplen = 0; // most scsi handled is input bool in_xfer = true; diff --git a/examples/device/cdc_msc_freertos/src/msc_disk.c b/examples/device/cdc_msc_freertos/src/msc_disk.c index 5aa7befc9..a4826fbe1 100644 --- a/examples/device/cdc_msc_freertos/src/msc_disk.c +++ b/examples/device/cdc_msc_freertos/src/msc_disk.c @@ -208,7 +208,7 @@ int32_t tud_msc_scsi_cb (uint8_t lun, uint8_t const scsi_cmd[16], void* buffer, // read10 & write10 has their own callback and MUST not be handled here void const* response = NULL; - uint16_t resplen = 0; + int32_t resplen = 0; // most scsi handled is input bool in_xfer = true; diff --git a/examples/device/dynamic_configuration/src/msc_disk.c b/examples/device/dynamic_configuration/src/msc_disk.c index 5aa7befc9..a4826fbe1 100644 --- a/examples/device/dynamic_configuration/src/msc_disk.c +++ b/examples/device/dynamic_configuration/src/msc_disk.c @@ -208,7 +208,7 @@ int32_t tud_msc_scsi_cb (uint8_t lun, uint8_t const scsi_cmd[16], void* buffer, // read10 & write10 has their own callback and MUST not be handled here void const* response = NULL; - uint16_t resplen = 0; + int32_t resplen = 0; // most scsi handled is input bool in_xfer = true; diff --git a/examples/device/msc_dual_lun/src/msc_disk_dual.c b/examples/device/msc_dual_lun/src/msc_disk_dual.c index cc7dfae0e..3cc59b46c 100644 --- a/examples/device/msc_dual_lun/src/msc_disk_dual.c +++ b/examples/device/msc_dual_lun/src/msc_disk_dual.c @@ -307,7 +307,7 @@ int32_t tud_msc_scsi_cb (uint8_t lun, uint8_t const scsi_cmd[16], void* buffer, // read10 & write10 has their own callback and MUST not be handled here void const* response = NULL; - uint16_t resplen = 0; + int32_t resplen = 0; // most scsi handled is input bool in_xfer = true; -- cgit v1.3.1 From 54013737d5949152959e470d3df3d0465296e251 Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 28 Aug 2021 20:26:56 +0700 Subject: fix msc example with out of bound lba (due to compliant test) --- examples/device/cdc_msc/src/msc_disk.c | 6 ++++++ examples/device/cdc_msc_freertos/src/msc_disk.c | 6 ++++++ examples/device/dynamic_configuration/src/msc_disk.c | 6 ++++++ examples/device/msc_dual_lun/src/msc_disk_dual.c | 6 ++++++ 4 files changed, 24 insertions(+) diff --git a/examples/device/cdc_msc/src/msc_disk.c b/examples/device/cdc_msc/src/msc_disk.c index 42b080cce..cad2602a2 100644 --- a/examples/device/cdc_msc/src/msc_disk.c +++ b/examples/device/cdc_msc/src/msc_disk.c @@ -188,6 +188,9 @@ int32_t tud_msc_read10_cb(uint8_t lun, uint32_t lba, uint32_t offset, void* buff { (void) lun; + // out of ramdisk + if ( lba >= DISK_BLOCK_NUM ) return -1; + uint8_t const* addr = msc_disk[lba] + offset; memcpy(buffer, addr, bufsize); @@ -211,6 +214,9 @@ int32_t tud_msc_write10_cb(uint8_t lun, uint32_t lba, uint32_t offset, uint8_t* { (void) lun; + // out of ramdisk + if ( lba >= DISK_BLOCK_NUM ) return -1; + #ifndef CFG_EXAMPLE_MSC_READONLY uint8_t* addr = msc_disk[lba] + offset; memcpy(addr, buffer, bufsize); diff --git a/examples/device/cdc_msc_freertos/src/msc_disk.c b/examples/device/cdc_msc_freertos/src/msc_disk.c index a4826fbe1..b9205f0c2 100644 --- a/examples/device/cdc_msc_freertos/src/msc_disk.c +++ b/examples/device/cdc_msc_freertos/src/msc_disk.c @@ -178,6 +178,9 @@ int32_t tud_msc_read10_cb(uint8_t lun, uint32_t lba, uint32_t offset, void* buff { (void) lun; + // out of ramdisk + if ( lba >= DISK_BLOCK_NUM ) return -1; + uint8_t const* addr = msc_disk[lba] + offset; memcpy(buffer, addr, bufsize); @@ -190,6 +193,9 @@ int32_t tud_msc_write10_cb(uint8_t lun, uint32_t lba, uint32_t offset, uint8_t* { (void) lun; + // out of ramdisk + if ( lba >= DISK_BLOCK_NUM ) return -1; + #ifndef CFG_EXAMPLE_MSC_READONLY uint8_t* addr = msc_disk[lba] + offset; memcpy(addr, buffer, bufsize); diff --git a/examples/device/dynamic_configuration/src/msc_disk.c b/examples/device/dynamic_configuration/src/msc_disk.c index a4826fbe1..b9205f0c2 100644 --- a/examples/device/dynamic_configuration/src/msc_disk.c +++ b/examples/device/dynamic_configuration/src/msc_disk.c @@ -178,6 +178,9 @@ int32_t tud_msc_read10_cb(uint8_t lun, uint32_t lba, uint32_t offset, void* buff { (void) lun; + // out of ramdisk + if ( lba >= DISK_BLOCK_NUM ) return -1; + uint8_t const* addr = msc_disk[lba] + offset; memcpy(buffer, addr, bufsize); @@ -190,6 +193,9 @@ int32_t tud_msc_write10_cb(uint8_t lun, uint32_t lba, uint32_t offset, uint8_t* { (void) lun; + // out of ramdisk + if ( lba >= DISK_BLOCK_NUM ) return -1; + #ifndef CFG_EXAMPLE_MSC_READONLY uint8_t* addr = msc_disk[lba] + offset; memcpy(addr, buffer, bufsize); diff --git a/examples/device/msc_dual_lun/src/msc_disk_dual.c b/examples/device/msc_dual_lun/src/msc_disk_dual.c index 3cc59b46c..18d3ca0d7 100644 --- a/examples/device/msc_dual_lun/src/msc_disk_dual.c +++ b/examples/device/msc_dual_lun/src/msc_disk_dual.c @@ -268,6 +268,9 @@ bool tud_msc_start_stop_cb(uint8_t lun, uint8_t power_condition, bool start, boo // Copy disk's data to buffer (up to bufsize) and return number of copied bytes. int32_t tud_msc_read10_cb(uint8_t lun, uint32_t lba, uint32_t offset, void* buffer, uint32_t bufsize) { + // out of ramdisk + if ( lba >= DISK_BLOCK_NUM ) return -1; + uint8_t const* addr = (lun ? msc_disk1[lba] : msc_disk0[lba]) + offset; memcpy(buffer, addr, bufsize); @@ -289,6 +292,9 @@ bool tud_msc_is_writable_cb (uint8_t lun) // Process data in buffer to disk's storage and return number of written bytes int32_t tud_msc_write10_cb(uint8_t lun, uint32_t lba, uint32_t offset, uint8_t* buffer, uint32_t bufsize) { + // out of ramdisk + if ( lba >= DISK_BLOCK_NUM ) return -1; + #ifndef CFG_EXAMPLE_MSC_READONLY uint8_t* addr = (lun ? msc_disk1[lba] : msc_disk0[lba]) + offset; memcpy(addr, buffer, bufsize); -- cgit v1.3.1 From be98cd56c7ac3bbd8b8762e42f752c9cec7c92f0 Mon Sep 17 00:00:00 2001 From: hathach Date: Sun, 29 Aug 2021 00:29:20 +0700 Subject: update msc to be more robuse add more log, pass more complaint test --- src/class/msc/msc_device.c | 87 ++++++++++++++++++++++++++++++++++------------ 1 file changed, 65 insertions(+), 22 deletions(-) diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c index e29cd473a..792d26dea 100644 --- a/src/class/msc/msc_device.c +++ b/src/class/msc/msc_device.c @@ -62,7 +62,7 @@ typedef struct // Bulk Only Transfer (BOT) Protocol uint8_t stage; - uint32_t total_len; + uint32_t total_len; // byte to be transferred, can be smaller than total_bytes in cbw uint32_t xferred_len; // numbered of bytes transferred so far in the Data Stage // Sense Response Data @@ -83,8 +83,16 @@ static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc); static void proc_write10_cmd(uint8_t rhport, mscd_interface_t* p_msc); static void proc_write10_new_data(uint8_t rhport, mscd_interface_t* p_msc, uint32_t xferred_bytes); +TU_ATTR_ALWAYS_INLINE static inline bool is_data_in(uint8_t dir) +{ + return tu_bit_test(dir, 7); +} + static inline bool send_csw(uint8_t rhport, mscd_interface_t* p_msc) { + // Data residue is always = host expect - actual transferred + p_msc->csw.data_residue = p_msc->cbw.total_bytes - p_msc->xferred_len; + p_msc->stage = MSC_STAGE_STATUS_SENT; return usbd_edpt_xfer(rhport, p_msc->ep_in , (uint8_t*) &p_msc->csw, sizeof(msc_csw_t)); } @@ -100,10 +108,9 @@ static void fail_scsi_op(uint8_t rhport, mscd_interface_t* p_msc, uint8_t status msc_cbw_t const * p_cbw = &p_msc->cbw; msc_csw_t * p_csw = &p_msc->csw; - p_csw->status = status; - p_csw->data_residue = p_cbw->total_bytes - p_msc->xferred_len; - - p_msc->stage = MSC_STAGE_STATUS; + // data_residue will be calculated before sending out csw + p_csw->status = status; + p_msc->stage = MSC_STAGE_STATUS; // failed but sense key is not set: default to Illegal Request if ( p_msc->sense_key == 0 ) tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00); @@ -111,7 +118,7 @@ static void fail_scsi_op(uint8_t rhport, mscd_interface_t* p_msc, uint8_t status // If there is data stage, stall it if ( p_cbw->total_bytes ) { - if ( tu_bit_test(p_cbw->dir, 7) ) + if ( is_data_in(p_cbw->dir) ) { usbd_edpt_stall(rhport, p_msc->ep_in); }else @@ -335,6 +342,8 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t if ( !(xferred_bytes == sizeof(msc_cbw_t) && p_cbw->signature == MSC_CBW_SIGNATURE) ) { + TU_LOG(MSC_DEBUG, " SCSI CBW is not valid\r\n"); + // BOT 6.6.1 If CBW is not valid stall both endpoints until reset recovery p_msc->stage = MSC_STAGE_NEED_RESET; @@ -351,6 +360,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t p_csw->signature = MSC_CSW_SIGNATURE; p_csw->tag = p_cbw->tag; p_csw->data_residue = 0; + p_csw->status = MSC_CSW_STATUS_PASSED; /*------------- Parse command and prepare DATA -------------*/ p_msc->stage = MSC_STAGE_DATA; @@ -360,9 +370,10 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t if ( SCSI_CMD_READ_10 == p_cbw->command[0] ) { // Invalid CBW length == 0 or Direction bit is incorrect - // 6.7 The 13 Cases: case 2, case 3, case 10 -> phase error - if ( rdwr10_get_blocksize(p_cbw) == 0 || !tu_bit_test(p_cbw->dir, 7) ) + // 6.7 The 13 Cases: case 2 (Hn < Di), case 3 (Hn < Do), case 10 (Ho <> Di) -> phase error + if ( rdwr10_get_blocksize(p_cbw) == 0 || !is_data_in(p_cbw->dir) ) { + TU_LOG(MSC_DEBUG, " SCSI ase 2 (Hn < Di), case 3 (Hn < Do), case 10 (Ho <> Di)\r\n"); fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_PHASE_ERROR); }else { @@ -372,9 +383,10 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t else if (SCSI_CMD_WRITE_10 == p_cbw->command[0]) { // Invalid CBW length == 0 or Direction bit is incorrect - // 6.7 The 13 Cases: case 2, case 3, case 8 -> phase error - if ( rdwr10_get_blocksize(p_cbw) == 0 || tu_bit_test(p_cbw->dir, 7) ) + // 6.7 The 13 Cases: case 2 (Hn < Do), case 3 (Hn < Do), case 8 (Hi <> Do) -> phase error + if ( rdwr10_get_blocksize(p_cbw) == 0 || is_data_in(p_cbw->dir) ) { + TU_LOG(MSC_DEBUG, " SCSI ase 2 (Hn < Di), case 3 (Hn < Do), case 8 (Hi <> Do)\r\n"); fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_PHASE_ERROR); }else { @@ -386,9 +398,12 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t // For other SCSI commands // 1. OUT : queue transfer (invoke app callback after done) // 2. IN & Zero: Process if is built-in, else Invoke app callback. Skip DATA if zero length - if ( (p_cbw->total_bytes > 0 ) && !tu_bit_test(p_cbw->dir, 7) ) + if ( (p_cbw->total_bytes > 0 ) && !is_data_in(p_cbw->dir) ) { - // queue transfer + // Didn't check for case 9 (Ho > Dn), which requires examining scsi command first + // but it is OK to just receive data then responded with failed status + + // Prepare for Data stage TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_out, _mscd_buf, p_msc->total_len) ); }else { @@ -404,22 +419,36 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t if ( resplen < 0 ) { // unsupported command + TU_LOG(MSC_DEBUG, " SCSI unsupported command\r\n"); fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED); } - else + else if (resplen == 0) { - p_msc->total_len = (uint32_t) resplen; - p_csw->status = MSC_CSW_STATUS_PASSED; - - if (p_msc->total_len) + if (p_cbw->total_bytes) { - TU_ASSERT( p_cbw->total_bytes >= p_msc->total_len ); // cannot return more than host expect - TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_in, _mscd_buf, p_msc->total_len) ); + // 6.7 The 13 Cases: case 4 (Hi > Dn) + TU_LOG(MSC_DEBUG, " SCSI case 4 (Hi > Dn): %lu\r\n", p_cbw->total_bytes); + fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED); }else { + // case 1 Hn = Dn: all good p_msc->stage = MSC_STAGE_STATUS; } } + else + { + if ( p_cbw->total_bytes == 0 ) + { + // 6.7 The 13 Cases: case 2 (Hn < Di) + TU_LOG(MSC_DEBUG, " SCSI case 2 (Hn < Di): %lu\r\n", p_cbw->total_bytes); + fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED); + }else + { + // cannot return more than host expect + p_msc->total_len = tu_min32((uint32_t) resplen, p_cbw->total_bytes); + TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_in, _mscd_buf, p_msc->total_len) ); + } + } } } break; @@ -448,7 +477,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t else { // OUT transfer, invoke callback if needed - if ( !tu_bit_test(p_cbw->dir, 7) ) + if ( !is_data_in(p_cbw->dir) ) { int32_t cb_result = tud_msc_scsi_cb(p_cbw->lun, p_cbw->command, _mscd_buf, p_msc->total_len); @@ -485,7 +514,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t // Wait for the Status phase to complete if( (ep_addr == p_msc->ep_in) && (xferred_bytes == sizeof(msc_csw_t)) ) { - TU_LOG(MSC_DEBUG, " SCSI Status: %u\r\n", p_csw->status); + TU_LOG(MSC_DEBUG, " SCSI Status = %u\r\n", p_csw->status); // TU_LOG_MEM(MSC_DEBUG, p_csw, xferred_bytes, 2); // Invoke complete callback if defined @@ -507,6 +536,10 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t } TU_ASSERT( prepare_cbw(rhport, p_msc) ); + }else + { + // Any xfer ended here is consider unknown error, ignore it + TU_LOG1(" Warning expect SCSI Status but received unknown data\r\n"); } break; @@ -518,7 +551,15 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t // skip status if epin is currently stalled, will do it when received Clear Stall request if ( !usbd_edpt_stalled(rhport, p_msc->ep_in) ) { - TU_ASSERT( send_csw(rhport, p_msc) ); + if ( (p_cbw->total_bytes > p_msc->xferred_len) && is_data_in(p_cbw->dir) ) + { + // 6.7 The 13 Cases: case 5 (Hi > Di): STALL before status + TU_LOG(MSC_DEBUG, " SCSI case 5 (Hi > Di): %lu > %lu\r\n", p_cbw->total_bytes, p_msc->xferred_len); + usbd_edpt_stall(rhport, p_msc->ep_in); + }else + { + TU_ASSERT( send_csw(rhport, p_msc) ); + } } } @@ -725,6 +766,7 @@ static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc) if ( nbytes < 0 ) { // negative means error -> endpoint is stalled & status in CSW set to failed + TU_LOG(MSC_DEBUG, " tud_msc_read10_cb() return -1\r\n"); // Sense = Flash not ready for access tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_MEDIUM_ERROR, 0x33, 0x00); @@ -785,6 +827,7 @@ static void proc_write10_new_data(uint8_t rhport, mscd_interface_t* p_msc, uint3 if ( nbytes < 0 ) { // negative means error -> failed this scsi op + TU_LOG(MSC_DEBUG, " tud_msc_write10_cb() return -1\r\n"); // Sense = Flash not ready for access tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_MEDIUM_ERROR, 0x33, 0x00); -- cgit v1.3.1 From 66c292e2ecb2cbc888074f2801c50e019f0bacf3 Mon Sep 17 00:00:00 2001 From: hathach Date: Sun, 29 Aug 2021 00:34:21 +0700 Subject: fix a couple of nrf dcd issue - limit out xact dma to prevent usbd overflow in certain situation after stalled - drained already acked data when stalling an OUT endpoint --- src/portable/nordic/nrf5x/dcd_nrf5x.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c index c962d9228..2013c5649 100644 --- a/src/portable/nordic/nrf5x/dcd_nrf5x.c +++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c @@ -206,7 +206,8 @@ static void xact_out_dma(uint8_t epnum) } else { - xact_len = (uint8_t)NRF_USBD->SIZE.EPOUT[epnum]; + // limit xact len to remaining length + xact_len = tu_min16((uint16_t) NRF_USBD->SIZE.EPOUT[epnum], xfer->total_len - xfer->actual_len); // Trigger DMA move data from Endpoint -> SRAM NRF_USBD->EPOUT[epnum].PTR = (uint32_t) xfer->buffer; @@ -480,10 +481,9 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t { if ( xfer->data_received ) { - // Data may already be received previously - xfer->data_received = false; - + // Data is already received previously // start DMA to copy to SRAM + xfer->data_received = false; xact_out_dma(epnum); } else @@ -505,7 +505,11 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr) { (void) rhport; + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + xfer_td_t* xfer = get_td(epnum, dir); if ( epnum == 0 ) { @@ -513,6 +517,15 @@ void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr) }else if (epnum != EP_ISO_NUM) { NRF_USBD->EPSTALL = (USBD_EPSTALL_STALL_Stall << USBD_EPSTALL_STALL_Pos) | ep_addr; + + // Note: nRF can auto ACK packet OUT before get stalled. + // There maybe data in endpoint fifo already, we need to pull it out + if ( (dir == TUSB_DIR_OUT) && xfer->data_received ) + { + TU_LOG_LOCATION(); + xfer->data_received = false; + xact_out_dma(epnum); + } } __ISB(); __DSB(); @@ -533,7 +546,6 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) NRF_USBD->DTOGGLE = (USBD_DTOGGLE_VALUE_Data0 << USBD_DTOGGLE_VALUE_Pos) | ep_addr; // Write any value to SIZE register will allow nRF to ACK/accept data - // Drop any pending data if (dir == TUSB_DIR_OUT) NRF_USBD->SIZE.EPOUT[epnum] = 0; __ISB(); __DSB(); -- cgit v1.3.1 From ad21b692775f5c75c09bc550ef77fdca64690a5a Mon Sep 17 00:00:00 2001 From: hathach Date: Sun, 29 Aug 2021 12:05:34 +0700 Subject: fix nrf clear data toggle sequence when clearing stall --- src/portable/nordic/nrf5x/dcd_nrf5x.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c index 2013c5649..f40ba2d4f 100644 --- a/src/portable/nordic/nrf5x/dcd_nrf5x.c +++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c @@ -539,12 +539,15 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) if ( epnum != 0 && epnum != EP_ISO_NUM ) { - // clear stall - NRF_USBD->EPSTALL = (USBD_EPSTALL_STALL_UnStall << USBD_EPSTALL_STALL_Pos) | ep_addr; - // reset data toggle to DATA0 + // First write this register with VALUE=Nop to select the endpoint, then either read it to get the status from + // VALUE, or write it again with VALUE=Data0 or Data1 + NRF_USBD->DTOGGLE = ep_addr; NRF_USBD->DTOGGLE = (USBD_DTOGGLE_VALUE_Data0 << USBD_DTOGGLE_VALUE_Pos) | ep_addr; + // clear stall + NRF_USBD->EPSTALL = (USBD_EPSTALL_STALL_UnStall << USBD_EPSTALL_STALL_Pos) | ep_addr; + // Write any value to SIZE register will allow nRF to ACK/accept data if (dir == TUSB_DIR_OUT) NRF_USBD->SIZE.EPOUT[epnum] = 0; -- cgit v1.3.1 From ee18cc42f2771cb63e7e5529f9be376cd0080f5e Mon Sep 17 00:00:00 2001 From: hathach Date: Sun, 29 Aug 2021 12:06:10 +0700 Subject: msc handle more test, passed Command Self Test compliant --- src/class/msc/msc_device.c | 28 +++++++++++++++++----------- 1 file changed, 17 insertions(+), 11 deletions(-) diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c index 792d26dea..247575ed4 100644 --- a/src/class/msc/msc_device.c +++ b/src/class/msc/msc_device.c @@ -373,7 +373,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t // 6.7 The 13 Cases: case 2 (Hn < Di), case 3 (Hn < Do), case 10 (Ho <> Di) -> phase error if ( rdwr10_get_blocksize(p_cbw) == 0 || !is_data_in(p_cbw->dir) ) { - TU_LOG(MSC_DEBUG, " SCSI ase 2 (Hn < Di), case 3 (Hn < Do), case 10 (Ho <> Di)\r\n"); + TU_LOG(MSC_DEBUG, " SCSI case 2 (Hn < Di), case 3 (Hn < Do), case 10 (Ho <> Di)\r\n"); fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_PHASE_ERROR); }else { @@ -386,7 +386,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t // 6.7 The 13 Cases: case 2 (Hn < Do), case 3 (Hn < Do), case 8 (Hi <> Do) -> phase error if ( rdwr10_get_blocksize(p_cbw) == 0 || is_data_in(p_cbw->dir) ) { - TU_LOG(MSC_DEBUG, " SCSI ase 2 (Hn < Di), case 3 (Hn < Do), case 8 (Hi <> Do)\r\n"); + TU_LOG(MSC_DEBUG, " SCSI case 2 (Hn < Di), case 3 (Hn < Do), case 8 (Hi <> Do)\r\n"); fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_PHASE_ERROR); }else { @@ -400,11 +400,16 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t // 2. IN & Zero: Process if is built-in, else Invoke app callback. Skip DATA if zero length if ( (p_cbw->total_bytes > 0 ) && !is_data_in(p_cbw->dir) ) { - // Didn't check for case 9 (Ho > Dn), which requires examining scsi command first - // but it is OK to just receive data then responded with failed status - - // Prepare for Data stage - TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_out, _mscd_buf, p_msc->total_len) ); + if (p_cbw->total_bytes > sizeof(_mscd_buf)) + { + TU_LOG(MSC_DEBUG, " SCSI reject non READ10/WRITE10 with large data\r\n"); + fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED); + }else + { + // Didn't check for case 9 (Ho > Dn), which requires examining scsi command first + // but it is OK to just receive data then responded with failed status + TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_out, _mscd_buf, p_msc->total_len) ); + } }else { // First process if it is a built-in commands @@ -483,11 +488,12 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t if ( cb_result < 0 ) { - p_csw->status = MSC_CSW_STATUS_FAILED; - tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00); // Sense = Invalid Command Operation + // unsupported command + TU_LOG(MSC_DEBUG, " SCSI unsupported command\r\n"); + fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED); }else { - p_csw->status = MSC_CSW_STATUS_PASSED; + // TODO haven't implement this scenario any further yet } } @@ -500,7 +506,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t } else { - // No command take more than one transfer yet -> unlikely error + // This scenario with command that take more than one transfer is already rejected at Command stage TU_BREAKPOINT(); } } -- cgit v1.3.1 From 4e3ed8159e420b80aa3d558d0ed728460ba4506f Mon Sep 17 00:00:00 2001 From: hathach Date: Sun, 29 Aug 2021 13:34:47 +0700 Subject: passed all USBCV bot complaince test --- src/class/msc/msc_device.c | 35 +++++++++++++++++++++-------------- 1 file changed, 21 insertions(+), 14 deletions(-) diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c index 247575ed4..52dfcb836 100644 --- a/src/class/msc/msc_device.c +++ b/src/class/msc/msc_device.c @@ -108,20 +108,21 @@ static void fail_scsi_op(uint8_t rhport, mscd_interface_t* p_msc, uint8_t status msc_cbw_t const * p_cbw = &p_msc->cbw; msc_csw_t * p_csw = &p_msc->csw; - // data_residue will be calculated before sending out csw - p_csw->status = status; - p_msc->stage = MSC_STAGE_STATUS; + p_csw->status = status; + p_csw->data_residue = p_msc->cbw.total_bytes - p_msc->xferred_len; + p_msc->stage = MSC_STAGE_STATUS; // failed but sense key is not set: default to Illegal Request if ( p_msc->sense_key == 0 ) tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00); - // If there is data stage, stall it - if ( p_cbw->total_bytes ) + // If there is data stage and not yet complete, stall it + if ( p_cbw->total_bytes && p_csw->data_residue ) { if ( is_data_in(p_cbw->dir) ) { usbd_edpt_stall(rhport, p_msc->ep_in); - }else + } + else { usbd_edpt_stall(rhport, p_msc->ep_out); } @@ -481,6 +482,8 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t } else { + p_msc->xferred_len += xferred_bytes; + // OUT transfer, invoke callback if needed if ( !is_data_in(p_cbw->dir) ) { @@ -497,8 +500,6 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t } } - p_msc->xferred_len += xferred_bytes; - if ( p_msc->xferred_len >= p_msc->total_len ) { // Data Stage is complete @@ -767,7 +768,8 @@ static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc) int32_t nbytes = (int32_t) tu_min32(sizeof(_mscd_buf), p_cbw->total_bytes-p_msc->xferred_len); // Application can consume smaller bytes - nbytes = tud_msc_read10_cb(p_cbw->lun, lba, p_msc->xferred_len % block_sz, _mscd_buf, (uint32_t) nbytes); + uint32_t const offset = p_msc->xferred_len % block_sz; + nbytes = tud_msc_read10_cb(p_cbw->lun, lba, offset, _mscd_buf, (uint32_t) nbytes); if ( nbytes < 0 ) { @@ -827,14 +829,18 @@ static void proc_write10_new_data(uint8_t rhport, mscd_interface_t* p_msc, uint3 // Adjust lba with transferred bytes uint32_t const lba = rdwr10_get_lba(p_cbw->command) + (p_msc->xferred_len / block_sz); - // Application can consume smaller bytes - int32_t nbytes = tud_msc_write10_cb(p_cbw->lun, lba, p_msc->xferred_len % block_sz, _mscd_buf, xferred_bytes); + // Invoke callback to consume new data + uint32_t const offset = p_msc->xferred_len % block_sz; + int32_t nbytes = tud_msc_write10_cb(p_cbw->lun, lba, offset, _mscd_buf, xferred_bytes); if ( nbytes < 0 ) { // negative means error -> failed this scsi op TU_LOG(MSC_DEBUG, " tud_msc_write10_cb() return -1\r\n"); + // update actual byte before failed + p_msc->xferred_len += xferred_bytes; + // Sense = Flash not ready for access tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_MEDIUM_ERROR, 0x33, 0x00); @@ -842,7 +848,7 @@ static void proc_write10_new_data(uint8_t rhport, mscd_interface_t* p_msc, uint3 }else { // Application consume less than what we got (including zero) - if ( nbytes < (int32_t) xferred_bytes ) + if ( (uint32_t) nbytes < xferred_bytes ) { if ( nbytes > 0 ) { @@ -850,12 +856,12 @@ static void proc_write10_new_data(uint8_t rhport, mscd_interface_t* p_msc, uint3 memmove(_mscd_buf, _mscd_buf+nbytes, xferred_bytes-nbytes); } - // simulate an transfer complete with adjusted parameters --> this driver callback will fired again + // simulate an transfer complete with adjusted parameters --> callback will be invoked with adjusted parameter dcd_event_xfer_complete(rhport, p_msc->ep_out, xferred_bytes-nbytes, XFER_RESULT_SUCCESS, false); } else { - // Application consume all bytes in our buffer, prepare to receive more data from host + // Application consume all bytes in our buffer p_msc->xferred_len += xferred_bytes; if ( p_msc->xferred_len >= p_msc->total_len ) @@ -864,6 +870,7 @@ static void proc_write10_new_data(uint8_t rhport, mscd_interface_t* p_msc, uint3 p_msc->stage = MSC_STAGE_STATUS; }else { + // prepare to receive more data from host proc_write10_cmd(rhport, p_msc); } } -- cgit v1.3.1 From fdf1ff545f41c23f63e86d6debaa852e731d7644 Mon Sep 17 00:00:00 2001 From: hathach Date: Sun, 29 Aug 2021 15:44:27 +0700 Subject: responding with status per-spec in test case 4 --- src/class/msc/msc_device.c | 81 ++++++++++++++++++++++++++++++++++------------ 1 file changed, 60 insertions(+), 21 deletions(-) diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c index 52dfcb836..7dcd4983e 100644 --- a/src/class/msc/msc_device.c +++ b/src/class/msc/msc_device.c @@ -138,11 +138,16 @@ static inline uint32_t rdwr10_get_lba(uint8_t const command[]) return tu_ntohl(lba); } +static inline uint16_t rdwr10_get_blockcount(msc_cbw_t const* cbw) +{ + uint16_t const block_count = tu_unaligned_read16(cbw->command + offsetof(scsi_write10_t, block_count)); + return tu_ntohs(block_count); +} + static inline uint16_t rdwr10_get_blocksize(msc_cbw_t const* cbw) { // first extract block count in the command - uint16_t block_count = tu_unaligned_read16(cbw->command + offsetof(scsi_write10_t, block_count)); - block_count = tu_ntohs(block_count); + uint16_t const block_count = rdwr10_get_blockcount(cbw); // invalid block count if (block_count == 0) return 0; @@ -150,6 +155,43 @@ static inline uint16_t rdwr10_get_blocksize(msc_cbw_t const* cbw) return cbw->total_bytes / block_count; } +uint8_t rdwr10_validate_cmd(msc_cbw_t const* cbw) +{ + uint8_t status = MSC_CSW_STATUS_PASSED; + uint16_t const block_count = rdwr10_get_blockcount(cbw); + + if ( cbw->total_bytes == 0 ) + { + if ( block_count ) + { + TU_LOG(MSC_DEBUG, " SCSI case 2 (Hn < Di) or case 3 (Hn < Do) \r\n"); + status = MSC_CSW_STATUS_PHASE_ERROR; + }else + { + // no data transfer, only exist in complaint test suite + } + }else + { + if ( SCSI_CMD_READ_10 == cbw->command[0] && !is_data_in(cbw->dir) ) + { + TU_LOG(MSC_DEBUG, " SCSI case 10 (Ho <> Di)\r\n"); + status = MSC_CSW_STATUS_PHASE_ERROR; + } + else if ( SCSI_CMD_WRITE_10 == cbw->command[0] && is_data_in(cbw->dir) ) + { + TU_LOG(MSC_DEBUG, " SCSI case 8 (Hi <> Do)\r\n"); + status = MSC_CSW_STATUS_PHASE_ERROR; + } + else if ( !block_count ) + { + TU_LOG(MSC_DEBUG, " SCSI case 4 Hi > Dn\r\n"); + status = MSC_CSW_STATUS_FAILED; + } + } + + return status; +} + //--------------------------------------------------------------------+ // Debug //--------------------------------------------------------------------+ @@ -368,30 +410,27 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t p_msc->total_len = p_cbw->total_bytes; p_msc->xferred_len = 0; - if ( SCSI_CMD_READ_10 == p_cbw->command[0] ) + // Read10 or Write10 + if ( (SCSI_CMD_READ_10 == p_cbw->command[0]) || (SCSI_CMD_WRITE_10 == p_cbw->command[0]) ) { - // Invalid CBW length == 0 or Direction bit is incorrect - // 6.7 The 13 Cases: case 2 (Hn < Di), case 3 (Hn < Do), case 10 (Ho <> Di) -> phase error - if ( rdwr10_get_blocksize(p_cbw) == 0 || !is_data_in(p_cbw->dir) ) + uint8_t const status = rdwr10_validate_cmd(p_cbw); + + if ( status != MSC_CSW_STATUS_PASSED) { - TU_LOG(MSC_DEBUG, " SCSI case 2 (Hn < Di), case 3 (Hn < Do), case 10 (Ho <> Di)\r\n"); - fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_PHASE_ERROR); - }else + fail_scsi_op(rhport, p_msc, status); + }else if ( p_cbw->total_bytes ) { - proc_read10_cmd(rhport, p_msc); - } - } - else if (SCSI_CMD_WRITE_10 == p_cbw->command[0]) - { - // Invalid CBW length == 0 or Direction bit is incorrect - // 6.7 The 13 Cases: case 2 (Hn < Do), case 3 (Hn < Do), case 8 (Hi <> Do) -> phase error - if ( rdwr10_get_blocksize(p_cbw) == 0 || is_data_in(p_cbw->dir) ) - { - TU_LOG(MSC_DEBUG, " SCSI case 2 (Hn < Di), case 3 (Hn < Do), case 8 (Hi <> Do)\r\n"); - fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_PHASE_ERROR); + if (SCSI_CMD_READ_10 == p_cbw->command[0]) + { + proc_read10_cmd(rhport, p_msc); + }else + { + proc_write10_cmd(rhport, p_msc); + } }else { - proc_write10_cmd(rhport, p_msc); + // no data transfer, only exist in complaint test suite + p_msc->stage = MSC_STAGE_STATUS; } } else -- cgit v1.3.1 From 8305766afe909a6f1b3be6a88cd4e6c4017255a8 Mon Sep 17 00:00:00 2001 From: MasterPhi Date: Tue, 31 Aug 2021 11:27:43 +0200 Subject: fix HID_LOGICAL_MAX overflow. --- src/class/hid/hid_device.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/class/hid/hid_device.h b/src/class/hid/hid_device.h index 5cf4b3060..7f67fa9cf 100644 --- a/src/class/hid/hid_device.h +++ b/src/class/hid/hid_device.h @@ -364,14 +364,14 @@ static inline bool tud_hid_gamepad_report(uint8_t report_id, int8_t x, int8_t y /* Input */ \ HID_USAGE ( 0x02 ),\ HID_LOGICAL_MIN ( 0x00 ),\ - HID_LOGICAL_MAX ( 0xff ),\ + HID_LOGICAL_MAX_N ( 0xff, 2 ),\ HID_REPORT_SIZE ( 8 ),\ HID_REPORT_COUNT( report_size ),\ HID_INPUT ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ),\ /* Output */ \ HID_USAGE ( 0x03 ),\ HID_LOGICAL_MIN ( 0x00 ),\ - HID_LOGICAL_MAX ( 0xff ),\ + HID_LOGICAL_MAX_N ( 0xff, 2 ),\ HID_REPORT_SIZE ( 8 ),\ HID_REPORT_COUNT( report_size ),\ HID_OUTPUT ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ),\ -- cgit v1.3.1 From 76345ea3a1d78924585b8c4e0c5b5cb5e89d74e7 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 31 Aug 2021 16:41:45 +0700 Subject: clear stall and reset data toggle when open edpt required to pass one of msc test. --- hw/bsp/samd21/boards/metro_m0_express/board.h | 2 +- hw/bsp/samd51/boards/metro_m4_express/board.h | 4 ++-- src/portable/microchip/samd/dcd_samd.c | 2 ++ 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/hw/bsp/samd21/boards/metro_m0_express/board.h b/hw/bsp/samd21/boards/metro_m0_express/board.h index b9292b9af..13b7556b0 100644 --- a/hw/bsp/samd21/boards/metro_m0_express/board.h +++ b/hw/bsp/samd21/boards/metro_m0_express/board.h @@ -35,7 +35,7 @@ #define LED_PIN 17 #define LED_STATE_ON 1 -// Button +// Button: D5 #define BUTTON_PIN 15 #define BUTTON_STATE_ACTIVE 0 diff --git a/hw/bsp/samd51/boards/metro_m4_express/board.h b/hw/bsp/samd51/boards/metro_m4_express/board.h index 9bb5f815e..ab10ae4f8 100644 --- a/hw/bsp/samd51/boards/metro_m4_express/board.h +++ b/hw/bsp/samd51/boards/metro_m4_express/board.h @@ -35,8 +35,8 @@ #define LED_PIN 16 #define LED_STATE_ON 1 -// Button -#define BUTTON_PIN (32+14) // D5 +// Button: D5 +#define BUTTON_PIN (32+14) #define BUTTON_STATE_ACTIVE 0 // UART diff --git a/src/portable/microchip/samd/dcd_samd.c b/src/portable/microchip/samd/dcd_samd.c index 54e8e62d9..526a6fb63 100644 --- a/src/portable/microchip/samd/dcd_samd.c +++ b/src/portable/microchip/samd/dcd_samd.c @@ -230,10 +230,12 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) if ( dir == TUSB_DIR_OUT ) { ep->EPCFG.bit.EPTYPE0 = desc_edpt->bmAttributes.xfer + 1; + ep->EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_STALLRQ0 | USB_DEVICE_EPSTATUSCLR_DTGLOUT; // clear stall & dtoggle ep->EPINTENSET.bit.TRCPT0 = true; }else { ep->EPCFG.bit.EPTYPE1 = desc_edpt->bmAttributes.xfer + 1; + ep->EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_STALLRQ1 | USB_DEVICE_EPSTATUSCLR_DTGLIN; // clear stall & dtoggle ep->EPINTENSET.bit.TRCPT1 = true; } -- cgit v1.3.1 From 864d8381a7acbd89053b6d478c064872b4871ed9 Mon Sep 17 00:00:00 2001 From: MasterPhi Date: Sat, 26 Jun 2021 19:53:57 +0200 Subject: dcd_transmission xfer_fifo support. --- .../nxp/transdimension/dcd_transdimension.c | 114 ++++++++++++++++++++- 1 file changed, 112 insertions(+), 2 deletions(-) diff --git a/src/portable/nxp/transdimension/dcd_transdimension.c b/src/portable/nxp/transdimension/dcd_transdimension.c index 42047ef92..156695fc4 100644 --- a/src/portable/nxp/transdimension/dcd_transdimension.c +++ b/src/portable/nxp/transdimension/dcd_transdimension.c @@ -128,7 +128,8 @@ typedef struct /// Due to the fact QHD is 64 bytes aligned but occupies only 48 bytes /// thus there are 16 bytes padding free that we can make use of. //--------------------------------------------------------------------+ - uint8_t reserved[16]; + tu_fifo_t * ff; + uint8_t reserved[12]; } dcd_qhd_t; TU_VERIFY_STATIC( sizeof(dcd_qhd_t) == 64, "size is not correct"); @@ -314,6 +315,39 @@ static void qtd_init(dcd_qtd_t* p_qtd, void * data_ptr, uint16_t total_bytes) } } +static void qtd_init_fifo(dcd_qtd_t* p_qtd, tu_fifo_buffer_info_t *info, uint16_t total_bytes) +{ + tu_memclr(p_qtd, sizeof(dcd_qtd_t)); + + p_qtd->next = QTD_NEXT_INVALID; + p_qtd->active = 1; + p_qtd->total_bytes = p_qtd->expected_bytes = total_bytes; + + // Fifo length has been trimmed to total_bytes + int16_t len_lin = info->len_lin; + + if (len_lin != 0) + { + p_qtd->buffer[0] = (uint32_t) info->ptr_lin; + + len_lin -= 4096 - ((uint32_t) info->ptr_lin - tu_align4k((uint32_t) info->ptr_lin)); + + // Set linear part + uint8_t i = 1; + for(; i<5; i++) + { + if (len_lin <= 0) break; + p_qtd->buffer[i] |= tu_align4k( p_qtd->buffer[i-1] ) + 4096; + len_lin -= 4096; + } + // Set wrapped part + for(uint8_t page = 0; i<5; i++, page++) + { + p_qtd->buffer[i] |= (uint32_t) info->ptr_wrap + 4096 * page; + } + } +} + //--------------------------------------------------------------------+ // DCD Endpoint Port //--------------------------------------------------------------------+ @@ -407,6 +441,67 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t return true; } +// fifo has to be aligned to 4k boundary +bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes) +{ + dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + uint8_t const ep_idx = 2*epnum + dir; + + if ( epnum == 0 ) + { + // follows UM 24.10.8.1.1 Setup packet handling using setup lockout mechanism + // wait until ENDPTSETUPSTAT before priming data/status in response TODO add time out + while(dcd_reg->ENDPTSETUPSTAT & TU_BIT(0)) {} + } + + dcd_qhd_t * p_qhd = &_dcd_data.qhd[ep_idx]; + dcd_qtd_t * p_qtd = &_dcd_data.qtd[ep_idx]; + + tu_fifo_buffer_info_t fifo_info; + + if(dir == TUSB_DIR_IN) + { + tu_fifo_get_read_info(ff, &fifo_info); + } + else + { + tu_fifo_get_write_info(ff, &fifo_info); + } + + if(total_bytes <= fifo_info.len_lin) + { + // Limit transfer length to total_bytes + fifo_info.len_wrap = 0; + fifo_info.len_lin = total_bytes; + } + else + { + // Class driver ensure at least total_bytes elements in fifo + fifo_info.len_wrap = total_bytes - fifo_info.len_lin; + } + // Force the CPU to flush the buffer. We increase the size by 32 because the call aligns the + // address to 32-byte boundaries. + // void* cast to suppress cast-align warning, buffer must be + CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) fifo_info.ptr_lin, 4), fifo_info.len_lin + 31); + if(fifo_info.len_wrap > 0) + CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) fifo_info.ptr_wrap, 4), fifo_info.len_wrap + 31); + + //------------- Prepare qtd -------------// + qtd_init_fifo(p_qtd, &fifo_info, total_bytes); + p_qtd->int_on_complete = true; + p_qhd->qtd_overlay.next = (uint32_t) p_qtd; // link qtd to qhd + p_qhd->ff = ff; + + CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t)); + + // start transfer + dcd_reg->ENDPTPRIME = TU_BIT( ep_idx2bit(ep_idx) ) ; + + return true; +} + //--------------------------------------------------------------------+ // ISR //--------------------------------------------------------------------+ @@ -474,13 +569,28 @@ void dcd_int_handler(uint8_t rhport) if ( tu_bit_test(edpt_complete, ep_idx2bit(ep_idx)) ) { // 23.10.12.3 Failed QTD also get ENDPTCOMPLETE set + dcd_qhd_t * p_qhd = &_dcd_data.qhd[ep_idx]; dcd_qtd_t * p_qtd = &_dcd_data.qtd[ep_idx]; uint8_t result = p_qtd->halted ? XFER_RESULT_STALLED : ( p_qtd->xact_err ||p_qtd->buffer_err ) ? XFER_RESULT_FAILED : XFER_RESULT_SUCCESS; uint8_t const ep_addr = (ep_idx/2) | ( (ep_idx & 0x01) ? TUSB_DIR_IN_MASK : 0 ); - dcd_event_xfer_complete(rhport, ep_addr, p_qtd->expected_bytes - p_qtd->total_bytes, result, true); // only number of bytes in the IOC qtd + + uint16_t xferred_bytes = p_qtd->expected_bytes - p_qtd->total_bytes; + + if (p_qhd->ff) + { + if(tu_edpt_dir(ep_addr) == TUSB_DIR_IN) + { + tu_fifo_advance_read_pointer(p_qhd->ff, xferred_bytes); + } + else + { + tu_fifo_advance_write_pointer(p_qhd->ff, xferred_bytes); + } + } + dcd_event_xfer_complete(rhport, ep_addr, xferred_bytes, result, true); // only number of bytes in the IOC qtd } } } -- cgit v1.3.1 From 16b802d50cff6118952767b8fefa33dd0447ea91 Mon Sep 17 00:00:00 2001 From: MasterPhi Date: Sat, 26 Jun 2021 23:13:01 +0200 Subject: add dcd_edpt_close and iso xfer. --- .../nxp/transdimension/dcd_transdimension.c | 75 ++++++++++++++-------- 1 file changed, 49 insertions(+), 26 deletions(-) diff --git a/src/portable/nxp/transdimension/dcd_transdimension.c b/src/portable/nxp/transdimension/dcd_transdimension.c index 156695fc4..a4d6c5d48 100644 --- a/src/portable/nxp/transdimension/dcd_transdimension.c +++ b/src/portable/nxp/transdimension/dcd_transdimension.c @@ -239,8 +239,9 @@ void dcd_init(uint8_t rhport) dcd_reg->USBMODE = USBMODE_CM_DEVICE; dcd_reg->OTGSC = OTGSC_VBUS_DISCHARGE | OTGSC_OTG_TERMINATION; - // TODO Force fullspeed on non-highspeed port - // dcd_reg->PORTSC1 = PORTSC1_FORCE_FULL_SPEED; +#if !TUD_OPT_HIGH_SPEED + dcd_reg->PORTSC1 = PORTSC1_FORCE_FULL_SPEED; +#endif CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t)); @@ -329,22 +330,22 @@ static void qtd_init_fifo(dcd_qtd_t* p_qtd, tu_fifo_buffer_info_t *info, uint16_ if (len_lin != 0) { p_qtd->buffer[0] = (uint32_t) info->ptr_lin; - + len_lin -= 4096 - ((uint32_t) info->ptr_lin - tu_align4k((uint32_t) info->ptr_lin)); - + // Set linear part uint8_t i = 1; for(; i<5; i++) { if (len_lin <= 0) break; p_qtd->buffer[i] |= tu_align4k( p_qtd->buffer[i-1] ) + 4096; - len_lin -= 4096; + len_lin -= 4096; } // Set wrapped part for(uint8_t page = 0; i<5; i++, page++) { p_qtd->buffer[i] |= (uint32_t) info->ptr_wrap + 4096 * page; - } + } } } @@ -373,9 +374,6 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) { - // TODO not support ISO yet - TU_VERIFY ( p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS); - uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress); uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress); uint8_t const ep_idx = 2*epnum + dir; @@ -387,14 +385,25 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) dcd_qhd_t * p_qhd = &_dcd_data.qhd[ep_idx]; tu_memclr(p_qhd, sizeof(dcd_qhd_t)); - p_qhd->zero_length_termination = 1; p_qhd->max_package_size = p_endpoint_desc->wMaxPacketSize.size; p_qhd->qtd_overlay.next = QTD_NEXT_INVALID; + if (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) + { + p_qhd->iso_mult = 1; + } else + { + p_qhd->zero_length_termination = 1; + } + CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t)); // Enable EP Control dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; + + // Clear EP type + dcd_reg->ENDPTCTRL[epnum] &=~(0x03 << (dir ? 18 : 2)); + dcd_reg->ENDPTCTRL[epnum] |= ((p_endpoint_desc->bmAttributes.xfer << 2) | ENDPTCTRL_ENABLE | ENDPTCTRL_TOGGLE_RESET) << (dir ? 16 : 0); return true; @@ -406,6 +415,22 @@ void dcd_edpt_close_all (uint8_t rhport) // TODO implement dcd_edpt_close_all() } +void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) +{ + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; + + // Flush EP + uint32_t flush_mask = TU_BIT(epnum) << (dir ? 16 : 0); + dcd_reg->ENDPTFLUSH = flush_mask; + while(dcd_reg->ENDPTFLUSH & flush_mask); + + // Clear EP enable + dcd_reg->ENDPTCTRL[epnum] &=~(ENDPTCTRL_ENABLE << (dir ? 16 : 0)); +} + bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) { dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; @@ -442,7 +467,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t } // fifo has to be aligned to 4k boundary -bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes) +bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes) { dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; uint8_t const epnum = tu_edpt_number(ep_addr); @@ -460,34 +485,33 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16 dcd_qtd_t * p_qtd = &_dcd_data.qtd[ep_idx]; tu_fifo_buffer_info_t fifo_info; - - if(dir == TUSB_DIR_IN) + + if (dir) { tu_fifo_get_read_info(ff, &fifo_info); - } - else + } else { tu_fifo_get_write_info(ff, &fifo_info); } - + if(total_bytes <= fifo_info.len_lin) { // Limit transfer length to total_bytes fifo_info.len_wrap = 0; fifo_info.len_lin = total_bytes; - } - else + } else { - // Class driver ensure at least total_bytes elements in fifo + // Class driver need to ensure at least total_bytes elements in fifo fifo_info.len_wrap = total_bytes - fifo_info.len_lin; } // Force the CPU to flush the buffer. We increase the size by 32 because the call aligns the // address to 32-byte boundaries. // void* cast to suppress cast-align warning, buffer must be CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) fifo_info.ptr_lin, 4), fifo_info.len_lin + 31); - if(fifo_info.len_wrap > 0) + if (fifo_info.len_wrap > 0) + { CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) fifo_info.ptr_wrap, 4), fifo_info.len_wrap + 31); - + } //------------- Prepare qtd -------------// qtd_init_fifo(p_qtd, &fifo_info, total_bytes); p_qtd->int_on_complete = true; @@ -576,20 +600,19 @@ void dcd_int_handler(uint8_t rhport) ( p_qtd->xact_err ||p_qtd->buffer_err ) ? XFER_RESULT_FAILED : XFER_RESULT_SUCCESS; uint8_t const ep_addr = (ep_idx/2) | ( (ep_idx & 0x01) ? TUSB_DIR_IN_MASK : 0 ); - + uint16_t xferred_bytes = p_qtd->expected_bytes - p_qtd->total_bytes; if (p_qhd->ff) { - if(tu_edpt_dir(ep_addr) == TUSB_DIR_IN) + if (tu_edpt_dir(ep_addr)) { tu_fifo_advance_read_pointer(p_qhd->ff, xferred_bytes); - } - else + } else { tu_fifo_advance_write_pointer(p_qhd->ff, xferred_bytes); } - } + } dcd_event_xfer_complete(rhport, ep_addr, xferred_bytes, result, true); // only number of bytes in the IOC qtd } } -- cgit v1.3.1 From e3bf4c069b4624807a7eade9f2432c0bebfae4ec Mon Sep 17 00:00:00 2001 From: MasterPhi Date: Tue, 6 Jul 2021 00:37:14 +0200 Subject: UAC2: Add ring buffer support for dcd_transdimension. Add ring buffer ON/OFF switch. --- src/class/audio/audio_device.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c index ff4e312a7..e16771cd3 100644 --- a/src/class/audio/audio_device.c +++ b/src/class/audio/audio_device.c @@ -64,10 +64,19 @@ // MACRO CONSTANT TYPEDEF //--------------------------------------------------------------------+ +// Use ring buffer if it's available, some MCUs need extra RAM requirements +#ifndef TUD_AUDIO_PREFER_RING_BUFFER +#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX +#define TUD_AUDIO_PREFER_RING_BUFFER 0 +#else +#define TUD_AUDIO_PREFER_RING_BUFFER 1 +#endif +#endif + // Linear buffer in case target MCU is not capable of handling a ring buffer FIFO e.g. no hardware buffer // is available or driver is would need to be changed dramatically -// Only STM32 synopsys use non-linear buffer for now +// Only STM32 synopsys and dcd_transdimension use non-linear buffer for now // Synopsys detection copied from dcd_synopsys.c (refactor later on) #if defined (STM32F105x8) || defined (STM32F105xB) || defined (STM32F105xC) || \ defined (STM32F107xB) || defined (STM32F107xC) @@ -90,11 +99,18 @@ CFG_TUSB_MCU == OPT_MCU_RX63X || \ CFG_TUSB_MCU == OPT_MCU_RX65X || \ CFG_TUSB_MCU == OPT_MCU_RX72N || \ - CFG_TUSB_MCU == OPT_MCU_GD32VF103 + CFG_TUSB_MCU == OPT_MCU_GD32VF103 || \ + CFG_TUSB_MCU == OPT_MCU_LPC18XX || \ + CFG_TUSB_MCU == OPT_MCU_LPC43XX || \ + CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX +#if TUD_AUDIO_PREFER_RING_BUFFER #define USE_LINEAR_BUFFER 0 #else #define USE_LINEAR_BUFFER 1 #endif +#else +#define USE_LINEAR_BUFFER 1 +#endif // Declaration of buffers -- cgit v1.3.1 From d047b28aa262f253b758b82bc32fed55eb59d213 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 31 Aug 2021 17:39:54 +0700 Subject: remove set/clear busy flag in set/clear stall since they are different status note: dcd should resume to prio-stalled queued transfer when unstall --- src/device/usbd.c | 6 ++---- src/device/usbd_pvt.h | 3 ++- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/src/device/usbd.c b/src/device/usbd.c index 7cd8fad42..4f5a2f8ed 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -1214,12 +1214,12 @@ bool usbd_edpt_claim(uint8_t rhport, uint8_t ep_addr) #if CFG_TUSB_OS != OPT_OS_NONE // pre-check to help reducing mutex lock - TU_VERIFY((_usbd_dev.ep_status[epnum][dir].busy == 0) && (_usbd_dev.ep_status[epnum][dir].claimed == 0)); + TU_VERIFY( usbd_edpt_ready(rhport, ep_addr) && (_usbd_dev.ep_status[epnum][dir].claimed == 0)); osal_mutex_lock(_usbd_mutex, OSAL_TIMEOUT_WAIT_FOREVER); #endif // can only claim the endpoint if it is not busy and not claimed yet. - bool const ret = (_usbd_dev.ep_status[epnum][dir].busy == 0) && (_usbd_dev.ep_status[epnum][dir].claimed == 0); + bool const ret = usbd_edpt_ready(rhport, ep_addr) && (_usbd_dev.ep_status[epnum][dir].claimed == 0); if (ret) { _usbd_dev.ep_status[epnum][dir].claimed = 1; @@ -1340,7 +1340,6 @@ void usbd_edpt_stall(uint8_t rhport, uint8_t ep_addr) dcd_edpt_stall(rhport, ep_addr); _usbd_dev.ep_status[epnum][dir].stalled = true; - _usbd_dev.ep_status[epnum][dir].busy = true; } void usbd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) @@ -1352,7 +1351,6 @@ void usbd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) dcd_edpt_clear_stall(rhport, ep_addr); _usbd_dev.ep_status[epnum][dir].stalled = false; - _usbd_dev.ep_status[epnum][dir].busy = false; } bool usbd_edpt_stalled(uint8_t rhport, uint8_t ep_addr) diff --git a/src/device/usbd_pvt.h b/src/device/usbd_pvt.h index 6a4b30956..7607b9895 100644 --- a/src/device/usbd_pvt.h +++ b/src/device/usbd_pvt.h @@ -81,7 +81,7 @@ bool usbd_edpt_claim(uint8_t rhport, uint8_t ep_addr); // Release an endpoint without submitting a transfer bool usbd_edpt_release(uint8_t rhport, uint8_t ep_addr); -// Check if endpoint transferring is complete +// Check if endpoint is busy transferring bool usbd_edpt_busy(uint8_t rhport, uint8_t ep_addr); // Stall endpoint @@ -93,6 +93,7 @@ void usbd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr); // Check if endpoint is stalled bool usbd_edpt_stalled(uint8_t rhport, uint8_t ep_addr); +// Check if endpoint is ready (not busy and not stalled) TU_ATTR_ALWAYS_INLINE static inline bool usbd_edpt_ready(uint8_t rhport, uint8_t ep_addr) { -- cgit v1.3.1 From ab0c3e8dd00e8baed6c0a233dd5377ef4497531d Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 31 Aug 2021 17:41:08 +0700 Subject: fix rp2040 chapter 9 TD 9.6 test --- src/class/msc/msc_device.c | 6 +++++- src/portable/raspberrypi/rp2040/dcd_rp2040.c | 10 ++++------ 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c index 7dcd4983e..6b3a392a8 100644 --- a/src/class/msc/msc_device.c +++ b/src/class/msc/msc_device.c @@ -323,7 +323,11 @@ bool mscd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t if ( p_msc->stage == MSC_STAGE_CMD ) { // part of reset recovery (probably due to invalid CBW) -> prepare for new command - TU_ASSERT( prepare_cbw(rhport, p_msc) ); + // Note: skip if already queued previously + if ( usbd_edpt_ready(rhport, p_msc->ep_out) ) + { + TU_ASSERT( prepare_cbw(rhport, p_msc) ); + } } } } diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c index e81681d4f..0cd3e97de 100644 --- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c @@ -389,17 +389,15 @@ void dcd_remote_wakeup(uint8_t rhport) // disconnect by disabling internal pull-up resistor on D+/D- void dcd_disconnect(uint8_t rhport) { - pico_info("dcd_disconnect %d\n", rhport); - assert(rhport == 0); - usb_hw_clear->sie_ctrl = USB_SIE_CTRL_PULLUP_EN_BITS; + (void) rhport; + usb_hw_clear->sie_ctrl = USB_SIE_CTRL_PULLUP_EN_BITS; } // connect by enabling internal pull-up resistor on D+/D- void dcd_connect(uint8_t rhport) { - pico_info("dcd_connect %d\n", rhport); - assert(rhport == 0); - usb_hw_set->sie_ctrl = USB_SIE_CTRL_PULLUP_EN_BITS; + (void) rhport; + usb_hw_set->sie_ctrl = USB_SIE_CTRL_PULLUP_EN_BITS; } /*------------------------------------------------------------------*/ -- cgit v1.3.1 From 90dc9bc289e12950fba9ea5dafe20e1b0777d0ba Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 1 Sep 2021 12:42:45 +0700 Subject: revert previous changes, edpt stall also clear any pending (not complete) transfer --- src/class/msc/msc_device.c | 6 +----- src/device/usbd.c | 6 ++++-- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c index 6b3a392a8..7dcd4983e 100644 --- a/src/class/msc/msc_device.c +++ b/src/class/msc/msc_device.c @@ -323,11 +323,7 @@ bool mscd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t if ( p_msc->stage == MSC_STAGE_CMD ) { // part of reset recovery (probably due to invalid CBW) -> prepare for new command - // Note: skip if already queued previously - if ( usbd_edpt_ready(rhport, p_msc->ep_out) ) - { - TU_ASSERT( prepare_cbw(rhport, p_msc) ); - } + TU_ASSERT( prepare_cbw(rhport, p_msc) ); } } } diff --git a/src/device/usbd.c b/src/device/usbd.c index 4f5a2f8ed..9af9b2a6e 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -1214,12 +1214,12 @@ bool usbd_edpt_claim(uint8_t rhport, uint8_t ep_addr) #if CFG_TUSB_OS != OPT_OS_NONE // pre-check to help reducing mutex lock - TU_VERIFY( usbd_edpt_ready(rhport, ep_addr) && (_usbd_dev.ep_status[epnum][dir].claimed == 0)); + TU_VERIFY( (_usbd_dev.ep_status[epnum][dir].busy == 0) && (_usbd_dev.ep_status[epnum][dir].claimed == 0)); osal_mutex_lock(_usbd_mutex, OSAL_TIMEOUT_WAIT_FOREVER); #endif // can only claim the endpoint if it is not busy and not claimed yet. - bool const ret = usbd_edpt_ready(rhport, ep_addr) && (_usbd_dev.ep_status[epnum][dir].claimed == 0); + bool const ret = (_usbd_dev.ep_status[epnum][dir].busy == 0) && (_usbd_dev.ep_status[epnum][dir].claimed == 0); if (ret) { _usbd_dev.ep_status[epnum][dir].claimed = 1; @@ -1340,6 +1340,7 @@ void usbd_edpt_stall(uint8_t rhport, uint8_t ep_addr) dcd_edpt_stall(rhport, ep_addr); _usbd_dev.ep_status[epnum][dir].stalled = true; + _usbd_dev.ep_status[epnum][dir].busy = true; } void usbd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) @@ -1351,6 +1352,7 @@ void usbd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) dcd_edpt_clear_stall(rhport, ep_addr); _usbd_dev.ep_status[epnum][dir].stalled = false; + _usbd_dev.ep_status[epnum][dir].busy = false; } bool usbd_edpt_stalled(uint8_t rhport, uint8_t ep_addr) -- cgit v1.3.1 From fc889ece74626f49a08898039102f0a9bf2b85a1 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 1 Sep 2021 16:52:27 +0700 Subject: rp2040 correct ep set/clear stall - stall will remove pending (not complete) transfer. Correct reset data toggle when clear stall. - remove buf ctrl debug code --- src/common/tusb_common.h | 3 ++ src/device/dcd.h | 2 +- src/portable/raspberrypi/rp2040/dcd_rp2040.c | 29 +++++++--------- src/portable/raspberrypi/rp2040/hcd_rp2040.c | 3 +- src/portable/raspberrypi/rp2040/rp2040_usb.c | 11 +++--- src/portable/raspberrypi/rp2040/rp2040_usb.h | 51 ---------------------------- 6 files changed, 22 insertions(+), 77 deletions(-) diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h index 1452e0105..687f980be 100644 --- a/src/common/tusb_common.h +++ b/src/common/tusb_common.h @@ -110,6 +110,9 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u32_byte2(uint32_t u32) { return TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u32_byte1(uint32_t u32) { return TU_U32_BYTE1(u32); } TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u32_byte0(uint32_t u32) { return TU_U32_BYTE0(u32); } +TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_u32_high16(uint32_t u32) { return (uint16_t) (u32 >> 16); } +TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_u32_low16 (uint32_t u32) { return (uint16_t) (u32 & 0x0000ffffu); } + TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u16_high(uint16_t u16) { return TU_U16_HIGH(u16); } TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u16_low (uint16_t u16) { return TU_U16_LOW(u16); } diff --git a/src/device/dcd.h b/src/device/dcd.h index 8d042bbde..d43a0dd9a 100644 --- a/src/device/dcd.h +++ b/src/device/dcd.h @@ -153,7 +153,7 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer // This API is optional, may be useful for register-based for transferring data. bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes) TU_ATTR_WEAK; -// Stall endpoint +// Stall endpoint, any queuing transfer should be removed from endpoint void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr); // clear stall, data toggle is also reset to DATA0 diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c index 0cd3e97de..42ffaf883 100644 --- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c @@ -145,8 +145,7 @@ static void hw_endpoint_init(uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t t if ( num == 0 ) { - // EP0 has no endpoint control register because - // the buffer offsets are fixed + // EP0 has no endpoint control register because the buffer offsets are fixed ep->endpoint_control = NULL; // Buffer offset is fixed (also double buffered) @@ -178,7 +177,7 @@ static void hw_endpoint_xfer(uint8_t ep_addr, uint8_t *buffer, uint16_t total_by static void hw_handle_buff_status(void) { uint32_t remaining_buffers = usb_hw->buf_status; - pico_trace("buf_status 0x%08x\n", remaining_buffers); + pico_trace("buf_status = 0x%08x\n", remaining_buffers); uint bit = 1u; for (uint i = 0; remaining_buffers && i < USB_MAX_ENDPOINTS * 2; i++) { @@ -186,8 +185,10 @@ static void hw_handle_buff_status(void) { // clear this in advance usb_hw_clear->buf_status = bit; + // IN transfer for even i, OUT transfer for odd i struct hw_endpoint *ep = hw_endpoint_get_by_num(i >> 1u, !(i & 1u)); + // Continue xfer bool done = hw_endpoint_xfer_continue(ep); if (done) @@ -325,7 +326,6 @@ static void dcd_rp2040_irq(void) void dcd_init (uint8_t rhport) { - pico_trace("dcd_init %d\n", rhport); assert(rhport == 0); // Reset hardware to default state @@ -370,7 +370,6 @@ void dcd_int_disable(uint8_t rhport) void dcd_set_address (uint8_t rhport, uint8_t dev_addr) { - pico_trace("dcd_set_address %d %d\n", rhport, dev_addr); assert(rhport == 0); // Can't set device address in hardware until status xfer has complete @@ -412,7 +411,6 @@ void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * re request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD && request->bRequest == TUSB_REQ_SET_ADDRESS ) { - pico_trace("Set HW address %d\n", request->wValue); usb_hw->dev_addr_ctrl = (uint8_t) request->wValue; } @@ -429,7 +427,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) void dcd_edpt_close_all (uint8_t rhport) { (void) rhport; - // TODO implement dcd_edpt_close_all() + // reset_all_endpoints(); TODO double check endpoint control } bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) @@ -441,8 +439,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { - pico_trace("dcd_edpt_stall %02x\n", ep_addr); - assert(rhport == 0); + (void) rhport; if ( tu_edpt_number(ep_addr) == 0 ) { @@ -452,22 +449,22 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) struct hw_endpoint *ep = hw_endpoint_get_by_addr(ep_addr); - // TODO check with double buffered - _hw_endpoint_buffer_control_set_mask32(ep, USB_BUF_CTRL_STALL); + // stall and clear current pending buffer + // may need to use EP_ABORT + _hw_endpoint_buffer_control_set_value32(ep, USB_BUF_CTRL_STALL); } void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { - pico_trace("dcd_edpt_clear_stall %02x\n", ep_addr); - assert(rhport == 0); + (void) rhport; if (tu_edpt_number(ep_addr)) { struct hw_endpoint *ep = hw_endpoint_get_by_addr(ep_addr); - // clear stall also reset toggle to DATA0 - // TODO check with double buffered - _hw_endpoint_buffer_control_clear_mask32(ep, USB_BUF_CTRL_STALL | USB_BUF_CTRL_DATA1_PID); + // clear stall also reset toggle to DATA0, ready for next transfer + ep->next_pid = 0; + _hw_endpoint_buffer_control_clear_mask32(ep, USB_BUF_CTRL_STALL); } } diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c index e51dfac2b..5e5bb4906 100644 --- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c @@ -201,7 +201,6 @@ static void hcd_rp2040_irq(void) { handled |= USB_INTS_BUFF_STATUS_BITS; TU_LOG(2, "Buffer complete\n"); - // print_bufctrl32(*epx.buffer_control); hw_handle_buff_status(); } @@ -231,7 +230,7 @@ static void hcd_rp2040_irq(void) if (status & USB_INTS_ERROR_DATA_SEQ_BITS) { usb_hw_clear->sie_status = USB_SIE_STATUS_DATA_SEQ_ERROR_BITS; - print_bufctrl32(*epx.buffer_control); + TU_LOG(3, " Seq Error: [0] = 0x%04u [1] = 0x%04x\r\n", tu_u32_low16(*epx.buffer_control), tu_u32_high16(*epx.buffer_control)); panic("Data Seq Error \n"); } diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c index 43554d28b..f9b4d9b17 100644 --- a/src/portable/raspberrypi/rp2040/rp2040_usb.c +++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c @@ -67,7 +67,6 @@ void rp2040_usb_init(void) void hw_endpoint_reset_transfer(struct hw_endpoint *ep) { - ep->stalled = false; ep->active = false; ep->remaining_len = 0; ep->xferred_len = 0; @@ -171,8 +170,7 @@ static void _hw_endpoint_start_next_buffer(struct hw_endpoint *ep) *ep->endpoint_control = ep_ctrl; - TU_LOG(3, "Prepare Buffer Control:\r\n"); - print_bufctrl32(buf_ctrl); + TU_LOG(3, " Prepare BufCtrl: [0] = 0x%04u [1] = 0x%04x\r\n", tu_u32_low16(buf_ctrl), tu_u32_high16(buf_ctrl)); // Finally, write to buffer_control which will trigger the transfer // the next time the controller polls this dpram address @@ -231,7 +229,7 @@ static uint16_t sync_ep_buffer(struct hw_endpoint *ep, uint8_t buf_id) // Short packet if (xferred_bytes < ep->wMaxPacketSize) { - pico_trace("Short rx transfer on buffer %d with %u bytes\n", buf_id, xferred_bytes); + pico_trace(" Short packet on buffer %d with %u bytes\n", buf_id, xferred_bytes); // Reduce total length as this is last packet ep->remaining_len = 0; } @@ -245,8 +243,7 @@ static void _hw_endpoint_xfer_sync (struct hw_endpoint *ep) // after a buff status interrupt uint32_t buf_ctrl = _hw_endpoint_buffer_control_get_value32(ep); - TU_LOG(3, "_hw_endpoint_xfer_sync:\r\n"); - print_bufctrl32(buf_ctrl); + TU_LOG(3, " Sync BufCtrl: [0] = 0x%04u [1] = 0x%04x\r\n", tu_u32_low16(buf_ctrl), tu_u32_high16(buf_ctrl)); // always sync buffer 0 uint16_t buf0_bytes = sync_ep_buffer(ep, 0); @@ -284,7 +281,7 @@ static void _hw_endpoint_xfer_sync (struct hw_endpoint *ep) usb_hw->abort &= ~TU_BIT(ep_id); TU_LOG(3, "----SHORT PACKET buffer0 on EP %02X:\r\n", ep->ep_addr); - print_bufctrl32(buf_ctrl); + TU_LOG(3, " BufCtrl: [0] = 0x%04u [1] = 0x%04x\r\n", tu_u32_low16(buf_ctrl), tu_u32_high16(buf_ctrl)); #endif } } diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.h b/src/portable/raspberrypi/rp2040/rp2040_usb.h index 5570a731a..b7bb51d1e 100644 --- a/src/portable/raspberrypi/rp2040/rp2040_usb.h +++ b/src/portable/raspberrypi/rp2040/rp2040_usb.h @@ -42,9 +42,6 @@ struct hw_endpoint // Buffer pointer in usb dpram uint8_t *hw_data_buf; - // Have we been stalled TODO remove later - bool stalled; - // Current transfer information bool active; uint16_t remaining_len; @@ -96,52 +93,4 @@ static inline uintptr_t hw_data_offset(uint8_t *buf) extern const char *ep_dir_string[]; -typedef union TU_ATTR_PACKED -{ - uint16_t u16; - struct TU_ATTR_PACKED - { - uint16_t xfer_len : 10; - uint16_t available : 1; - uint16_t stall : 1; - uint16_t reset_bufsel : 1; - uint16_t data_toggle : 1; - uint16_t last_buf : 1; - uint16_t full : 1; - }; -} rp2040_buffer_control_t; - -TU_VERIFY_STATIC(sizeof(rp2040_buffer_control_t) == 2, "size is not correct"); - -#if CFG_TUSB_DEBUG >= 3 -static inline void print_bufctrl16(uint32_t u16) -{ - rp2040_buffer_control_t bufctrl = { - .u16 = u16 - }; - - TU_LOG(3, "len = %u, available = %u, full = %u, last = %u, stall = %u, reset = %u, toggle = %u\r\n", - bufctrl.xfer_len, bufctrl.available, bufctrl.full, bufctrl.last_buf, bufctrl.stall, bufctrl.reset_bufsel, bufctrl.data_toggle); -} - -static inline void print_bufctrl32(uint32_t u32) -{ - uint16_t u16; - - u16 = u32 >> 16; - TU_LOG(3, " Buffer Control 1 0x%x: ", u16); - print_bufctrl16(u16); - - u16 = u32 & 0x0000ffff; - TU_LOG(3, " Buffer Control 0 0x%x: ", u16); - print_bufctrl16(u16); -} - -#else - -#define print_bufctrl16(u16) -#define print_bufctrl32(u32) - -#endif - #endif -- cgit v1.3.1 From 15fa2f447b9187f2cef5dd5ba904449bd4c6703e Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 1 Sep 2021 16:53:12 +0700 Subject: add back edpt check before cbw, since bot reset can occurred any time --- src/class/msc/msc_device.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c index 7dcd4983e..6b3a392a8 100644 --- a/src/class/msc/msc_device.c +++ b/src/class/msc/msc_device.c @@ -323,7 +323,11 @@ bool mscd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t if ( p_msc->stage == MSC_STAGE_CMD ) { // part of reset recovery (probably due to invalid CBW) -> prepare for new command - TU_ASSERT( prepare_cbw(rhport, p_msc) ); + // Note: skip if already queued previously + if ( usbd_edpt_ready(rhport, p_msc->ep_out) ) + { + TU_ASSERT( prepare_cbw(rhport, p_msc) ); + } } } } -- cgit v1.3.1 From 1398226bb5c141db43b4dc2dae846c96c743274d Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 1 Sep 2021 16:54:03 +0700 Subject: only attempt to clear if stalled, and stall if cleared --- src/device/usbd.c | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/src/device/usbd.c b/src/device/usbd.c index 9af9b2a6e..912bae9a8 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -1333,26 +1333,33 @@ bool usbd_edpt_busy(uint8_t rhport, uint8_t ep_addr) void usbd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { - TU_LOG(USBD_DBG, " Stall EP %02X\r\n", ep_addr); uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); - dcd_edpt_stall(rhport, ep_addr); - _usbd_dev.ep_status[epnum][dir].stalled = true; - _usbd_dev.ep_status[epnum][dir].busy = true; + // only stalled if currently cleared + if ( !_usbd_dev.ep_status[epnum][dir].stalled ) + { + TU_LOG(USBD_DBG, " Stall EP %02X\r\n", ep_addr); + dcd_edpt_stall(rhport, ep_addr); + _usbd_dev.ep_status[epnum][dir].stalled = true; + _usbd_dev.ep_status[epnum][dir].busy = true; + } } void usbd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { - TU_LOG(USBD_DBG, " Clear Stall EP %02X\r\n", ep_addr); - uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); - dcd_edpt_clear_stall(rhport, ep_addr); - _usbd_dev.ep_status[epnum][dir].stalled = false; - _usbd_dev.ep_status[epnum][dir].busy = false; + // only clear if currently stalled + if ( _usbd_dev.ep_status[epnum][dir].stalled ) + { + TU_LOG(USBD_DBG, " Clear Stall EP %02X\r\n", ep_addr); + dcd_edpt_clear_stall(rhport, ep_addr); + _usbd_dev.ep_status[epnum][dir].stalled = false; + _usbd_dev.ep_status[epnum][dir].busy = false; + } } bool usbd_edpt_stalled(uint8_t rhport, uint8_t ep_addr) -- cgit v1.3.1 From d6e9fe38beefbea787dad151dfeb3c62be96d527 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 1 Sep 2021 19:42:40 +0700 Subject: rp2040 implement dcd_edpt_close_all() aslo rename reset_ep0_pid() and clean up. We only need to reset pid when setup packet received --- src/portable/raspberrypi/rp2040/dcd_rp2040.c | 46 ++++++++++++++++------------ src/portable/raspberrypi/rp2040/rp2040_usb.h | 4 +-- 2 files changed, 29 insertions(+), 21 deletions(-) diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c index 42ffaf883..a710bd557 100644 --- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c @@ -124,9 +124,7 @@ static void hw_endpoint_init(uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t t // For device, IN is a tx transfer and OUT is an rx transfer ep->rx = (dir == TUSB_DIR_OUT); - // Response to a setup packet on EP0 starts with pid of 1 - ep->next_pid = (num == 0 ? 1u : 0u); - + ep->next_pid = 0u; ep->wMaxPacketSize = wMaxPacketSize; ep->transfer_type = transfer_type; @@ -203,7 +201,7 @@ static void hw_handle_buff_status(void) } } -static void reset_ep0(void) +static void reset_ep0_pid(void) { // If we have finished this transfer on EP0 set pid back to 1 for next // setup transfer. Also clear a stall in case @@ -215,14 +213,18 @@ static void reset_ep0(void) } } -static void reset_all_endpoints(void) +static void reset_non_control_endpoints(void) { - memset(hw_endpoints, 0, sizeof(hw_endpoints)); - next_buffer_ptr = &usb_dpram->epx_data[0]; + // Disable all non-control + for ( uint8_t i = 0; i < USB_MAX_ENDPOINTS-1; i++ ) + { + usb_dpram->ep_ctrl[i].in = 0; + usb_dpram->ep_ctrl[i].out = 0; + } - // Init Control endpoint out & in - hw_endpoint_init(0x0, 64, TUSB_XFER_CONTROL); - hw_endpoint_init(0x80, 64, TUSB_XFER_CONTROL); + // clear non-control hw endpoints + tu_memclr(hw_endpoints[1], sizeof(hw_endpoints) - 2*sizeof(hw_endpoint_t)); + next_buffer_ptr = &usb_dpram->epx_data[0]; } static void dcd_rp2040_irq(void) @@ -234,8 +236,10 @@ static void dcd_rp2040_irq(void) { handled |= USB_INTS_SETUP_REQ_BITS; uint8_t const *setup = (uint8_t const *)&usb_dpram->setup_packet; - // Clear stall bits and reset pid - reset_ep0(); + + // reset pid to both 1 (data and ack) + reset_ep0_pid(); + // Pass setup packet to tiny usb dcd_event_setup_received(0, setup, true); usb_hw_clear->sie_status = USB_SIE_STATUS_SETUP_REC_BITS; @@ -275,7 +279,7 @@ static void dcd_rp2040_irq(void) handled |= USB_INTS_BUS_RESET_BITS; usb_hw->dev_addr_ctrl = 0; - reset_all_endpoints(); + reset_non_control_endpoints(); dcd_event_bus_reset(0, TUSB_SPEED_FULL, true); usb_hw_clear->sie_status = USB_SIE_STATUS_BUS_RESET_BITS; @@ -338,8 +342,13 @@ void dcd_init (uint8_t rhport) irq_set_exclusive_handler(USBCTRL_IRQ, dcd_rp2040_irq); - // reset endpoints - reset_all_endpoints(); + // Init control endpoints + tu_memclr(hw_endpoints[0], 2*sizeof(hw_endpoint_t)); + hw_endpoint_init(0x0, 64, TUSB_XFER_CONTROL); + hw_endpoint_init(0x80, 64, TUSB_XFER_CONTROL); + + // Init non-control endpoints + reset_non_control_endpoints(); // Initializes the USB peripheral for device mode and enables it. // Don't need to enable the pull up here. Force VBUS @@ -374,7 +383,6 @@ void dcd_set_address (uint8_t rhport, uint8_t dev_addr) // Can't set device address in hardware until status xfer has complete // Send 0len complete response on EP0 IN - reset_ep0(); hw_endpoint_xfer(0x80, NULL, 0); } @@ -413,8 +421,6 @@ void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * re { usb_hw->dev_addr_ctrl = (uint8_t) request->wValue; } - - reset_ep0(); } bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) @@ -427,7 +433,9 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) void dcd_edpt_close_all (uint8_t rhport) { (void) rhport; - // reset_all_endpoints(); TODO double check endpoint control + + // may need to use EP Abort + reset_non_control_endpoints(); } bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.h b/src/portable/raspberrypi/rp2040/rp2040_usb.h index b7bb51d1e..a9cf1dd07 100644 --- a/src/portable/raspberrypi/rp2040/rp2040_usb.h +++ b/src/portable/raspberrypi/rp2040/rp2040_usb.h @@ -21,7 +21,7 @@ #define pico_trace(...) TU_LOG(3, __VA_ARGS__) // Hardware information per endpoint -struct hw_endpoint +typedef struct hw_endpoint { // Is this a valid struct bool configured; @@ -63,7 +63,7 @@ struct hw_endpoint // If interrupt endpoint uint8_t interrupt_num; #endif -}; +} hw_endpoint_t; void rp2040_usb_init(void); -- cgit v1.3.1 From d4c56c70a80a6df81f403627e897c50b0a94601e Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 1 Sep 2021 20:01:40 +0700 Subject: minor clean up --- src/device/usbd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/device/usbd.c b/src/device/usbd.c index 912bae9a8..a52ea9afe 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -1214,7 +1214,7 @@ bool usbd_edpt_claim(uint8_t rhport, uint8_t ep_addr) #if CFG_TUSB_OS != OPT_OS_NONE // pre-check to help reducing mutex lock - TU_VERIFY( (_usbd_dev.ep_status[epnum][dir].busy == 0) && (_usbd_dev.ep_status[epnum][dir].claimed == 0)); + TU_VERIFY((_usbd_dev.ep_status[epnum][dir].busy == 0) && (_usbd_dev.ep_status[epnum][dir].claimed == 0)); osal_mutex_lock(_usbd_mutex, OSAL_TIMEOUT_WAIT_FOREVER); #endif -- cgit v1.3.1 From 2e23f3dd7287186445aeab39108f81c51644ed77 Mon Sep 17 00:00:00 2001 From: Kamil Tomaszewski Date: Fri, 3 Sep 2021 18:13:45 +0200 Subject: Fix for MSC during stage STATUS --- src/class/msc/msc_device.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c index 6b3a392a8..71875b014 100644 --- a/src/class/msc/msc_device.c +++ b/src/class/msc/msc_device.c @@ -601,10 +601,10 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t // skip status if epin is currently stalled, will do it when received Clear Stall request if ( !usbd_edpt_stalled(rhport, p_msc->ep_in) ) { - if ( (p_cbw->total_bytes > p_msc->xferred_len) && is_data_in(p_cbw->dir) ) + if ( (p_msc->total_len > p_msc->xferred_len) && is_data_in(p_cbw->dir) ) { // 6.7 The 13 Cases: case 5 (Hi > Di): STALL before status - TU_LOG(MSC_DEBUG, " SCSI case 5 (Hi > Di): %lu > %lu\r\n", p_cbw->total_bytes, p_msc->xferred_len); + TU_LOG(MSC_DEBUG, " SCSI case 5 (Hi > Di): %lu > %lu\r\n", p_msc->total_len, p_msc->xferred_len); usbd_edpt_stall(rhport, p_msc->ep_in); }else { -- cgit v1.3.1 From 51dddf63fa617dd8da8471f485b1c28e5c9513ca Mon Sep 17 00:00:00 2001 From: MasterPhi Date: Fri, 3 Sep 2021 18:26:39 +0200 Subject: Add IAR project connections. --- .../iar_audio_4_channel_mic.ipcf | 154 ++++++++++++++++++++ examples/device/audio_test/iar_audio_test.ipcf | 154 ++++++++++++++++++++ examples/device/board_test/iar_board_test.ipcf | 153 ++++++++++++++++++++ .../device/cdc_dual_ports/iar_cdc_dual_ports.ipcf | 154 ++++++++++++++++++++ examples/device/cdc_msc/iar_cdc_msc.ipcf | 155 ++++++++++++++++++++ .../cdc_msc_freertos/iar_cdc_msc_freertos.ipcf | 157 +++++++++++++++++++++ examples/device/dfu/iar_dfu.ipcf | 154 ++++++++++++++++++++ examples/device/dfu_runtime/iar_dfu_runtime.ipcf | 154 ++++++++++++++++++++ .../iar_dynamic_configuration.ipcf | 155 ++++++++++++++++++++ .../hid_boot_interface/iar_hid_boot_interface.ipcf | 155 ++++++++++++++++++++ .../device/hid_composite/iar_hid_composite.ipcf | 155 ++++++++++++++++++++ .../iar_hid_composite_freertos.ipcf | 157 +++++++++++++++++++++ .../hid_generic_inout/iar_hid_generic_inout.ipcf | 154 ++++++++++++++++++++ .../iar_hid_multiple_interface.ipcf | 154 ++++++++++++++++++++ examples/device/midi_test/iar_midi_test.ipcf | 154 ++++++++++++++++++++ examples/device/msc_dual_lun/iar_msc_dual_lun.ipcf | 155 ++++++++++++++++++++ .../net_lwip_webserver/iar_net_lwip_webserver.ipcf | 155 ++++++++++++++++++++ examples/device/uac2_headset/iar_uac2_headset.ipcf | 155 ++++++++++++++++++++ examples/device/usbtmc/iar_usbtmc.ipcf | 157 +++++++++++++++++++++ .../device/webusb_serial/iar_webusb_serial.ipcf | 155 ++++++++++++++++++++ examples/host/cdc_msc_hid/iar_cdc_msc_hid.ipcf | 155 ++++++++++++++++++++ .../host/hid_controller/iar_hid_controller.ipcf | 154 ++++++++++++++++++++ tools/iar.ipcf | 147 +++++++++++++++++++ tools/iar_gen.py | 51 +++++++ 24 files changed, 3603 insertions(+) create mode 100644 examples/device/audio_4_channel_mic/iar_audio_4_channel_mic.ipcf create mode 100644 examples/device/audio_test/iar_audio_test.ipcf create mode 100644 examples/device/board_test/iar_board_test.ipcf create mode 100644 examples/device/cdc_dual_ports/iar_cdc_dual_ports.ipcf create mode 100644 examples/device/cdc_msc/iar_cdc_msc.ipcf create mode 100644 examples/device/cdc_msc_freertos/iar_cdc_msc_freertos.ipcf create mode 100644 examples/device/dfu/iar_dfu.ipcf create mode 100644 examples/device/dfu_runtime/iar_dfu_runtime.ipcf create mode 100644 examples/device/dynamic_configuration/iar_dynamic_configuration.ipcf create mode 100644 examples/device/hid_boot_interface/iar_hid_boot_interface.ipcf create mode 100644 examples/device/hid_composite/iar_hid_composite.ipcf create mode 100644 examples/device/hid_composite_freertos/iar_hid_composite_freertos.ipcf create mode 100644 examples/device/hid_generic_inout/iar_hid_generic_inout.ipcf create mode 100644 examples/device/hid_multiple_interface/iar_hid_multiple_interface.ipcf create mode 100644 examples/device/midi_test/iar_midi_test.ipcf create mode 100644 examples/device/msc_dual_lun/iar_msc_dual_lun.ipcf create mode 100644 examples/device/net_lwip_webserver/iar_net_lwip_webserver.ipcf create mode 100644 examples/device/uac2_headset/iar_uac2_headset.ipcf create mode 100644 examples/device/usbtmc/iar_usbtmc.ipcf create mode 100644 examples/device/webusb_serial/iar_webusb_serial.ipcf create mode 100644 examples/host/cdc_msc_hid/iar_cdc_msc_hid.ipcf create mode 100644 examples/host/hid_controller/iar_hid_controller.ipcf create mode 100644 tools/iar.ipcf create mode 100644 tools/iar_gen.py diff --git a/examples/device/audio_4_channel_mic/iar_audio_4_channel_mic.ipcf b/examples/device/audio_4_channel_mic/iar_audio_4_channel_mic.ipcf new file mode 100644 index 000000000..a862b871f --- /dev/null +++ b/examples/device/audio_4_channel_mic/iar_audio_4_channel_mic.ipcf @@ -0,0 +1,154 @@ + + + + $TUSB_DIR$/src + $TUSB_DIR$/lib/SEGGER_RTT/RTT + $PROJ_DIR$ + $TUSB_DIR$/hw + + + + $TUSB_DIR$/src/device/usbd.c + $TUSB_DIR$/src/device/usbd_control.c + + + $TUSB_DIR$/src/common/tusb_fifo.c + + + $TUSB_DIR$/src/class/audio/audio_device.c + + + $TUSB_DIR$/src/class/bth/bth_device.c + + + $TUSB_DIR$/src/class/cdc/cdc_device.c + $TUSB_DIR$/src/class/cdc/cdc_host.c + $TUSB_DIR$/src/class/cdc/cdc_rndis_host.c + + + $TUSB_DIR$/src/class/dfu/dfu_device.c + $TUSB_DIR$/src/class/dfu/dfu_rt_device.c + + + $TUSB_DIR$/src/class/hid/hid_device.c + $TUSB_DIR$/src/class/hid/hid_host.c + + + $TUSB_DIR$/src/class/midi/midi_device.c + + + $TUSB_DIR$/src/class/msc/msc_device.c + $TUSB_DIR$/src/class/msc/msc_host.c + + + $TUSB_DIR$/src/class/net/net_device.c + + + $TUSB_DIR$/src/class/usbtmc/usbtmc_device.c + + + $TUSB_DIR$/src/class/vendor/vendor_device.c + $TUSB_DIR$/src/class/vendor/vendor_host.c + + + $TUSB_DIR$/src/tusb.c + + + $TUSB_DIR$/src/host/hub.c + $TUSB_DIR$/src/host/usbh.c + $TUSB_DIR$/src/host/usbh_control.c + + + $TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c + + + $TUSB_DIR$/src/portable/ehci/ehci.c + + + $TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c + + + $TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c + + + $TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c + + + $TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c + + + $TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c + + + $TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c + + + $TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c + + + $TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c + $TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c + + + $TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c + + + $TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c + $TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c + + + $TUSB_DIR$/src/portable/ohci/ohci.c + + + $TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c + + + $TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c + + + $TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c + + + $TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c + + + $TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c + + + $TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c + + + $TUSB_DIR$/src/portable/template/dcd_template.c + + + $TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c + + + $TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c + + + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c + $TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c + + + $TUSB_DIR$/hw/bsp/board.c + + + $TUSB_DIR$/examples/device/audio_4_channel_mic/src/main.c + $TUSB_DIR$/examples/device/audio_4_channel_mic/src/tusb_config.h + $TUSB_DIR$/examples/device/audio_4_channel_mic/src/usb_descriptors.c + + + \ No newline at end of file diff --git a/examples/device/audio_test/iar_audio_test.ipcf b/examples/device/audio_test/iar_audio_test.ipcf new file mode 100644 index 000000000..a5fdd5350 --- /dev/null +++ b/examples/device/audio_test/iar_audio_test.ipcf @@ -0,0 +1,154 @@ + + + + $TUSB_DIR$/src + $TUSB_DIR$/lib/SEGGER_RTT/RTT + $PROJ_DIR$ + $TUSB_DIR$/hw + + + + $TUSB_DIR$/src/device/usbd.c + $TUSB_DIR$/src/device/usbd_control.c + + + $TUSB_DIR$/src/common/tusb_fifo.c + + + $TUSB_DIR$/src/class/audio/audio_device.c + + + $TUSB_DIR$/src/class/bth/bth_device.c + + + $TUSB_DIR$/src/class/cdc/cdc_device.c + $TUSB_DIR$/src/class/cdc/cdc_host.c + $TUSB_DIR$/src/class/cdc/cdc_rndis_host.c + + + $TUSB_DIR$/src/class/dfu/dfu_device.c + $TUSB_DIR$/src/class/dfu/dfu_rt_device.c + + + $TUSB_DIR$/src/class/hid/hid_device.c + $TUSB_DIR$/src/class/hid/hid_host.c + + + $TUSB_DIR$/src/class/midi/midi_device.c + + + $TUSB_DIR$/src/class/msc/msc_device.c + $TUSB_DIR$/src/class/msc/msc_host.c + + + $TUSB_DIR$/src/class/net/net_device.c + + + $TUSB_DIR$/src/class/usbtmc/usbtmc_device.c + + + $TUSB_DIR$/src/class/vendor/vendor_device.c + $TUSB_DIR$/src/class/vendor/vendor_host.c + + + $TUSB_DIR$/src/tusb.c + + + $TUSB_DIR$/src/host/hub.c + $TUSB_DIR$/src/host/usbh.c + $TUSB_DIR$/src/host/usbh_control.c + + + $TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c + + + $TUSB_DIR$/src/portable/ehci/ehci.c + + + $TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c + + + $TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c + + + $TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c + + + $TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c + + + $TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c + + + $TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c + + + $TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c + + + $TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c + $TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c + + + $TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c + + + $TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c + $TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c + + + $TUSB_DIR$/src/portable/ohci/ohci.c + + + $TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c + + + $TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c + + + $TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c + + + $TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c + + + $TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c + + + $TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c + + + $TUSB_DIR$/src/portable/template/dcd_template.c + + + $TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c + + + $TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c + + + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c + $TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c + + + $TUSB_DIR$/hw/bsp/board.c + + + $TUSB_DIR$/examples/device/audio_test/src/main.c + $TUSB_DIR$/examples/device/audio_test/src/tusb_config.h + $TUSB_DIR$/examples/device/audio_test/src/usb_descriptors.c + + + \ No newline at end of file diff --git a/examples/device/board_test/iar_board_test.ipcf b/examples/device/board_test/iar_board_test.ipcf new file mode 100644 index 000000000..942911640 --- /dev/null +++ b/examples/device/board_test/iar_board_test.ipcf @@ -0,0 +1,153 @@ + + + + $TUSB_DIR$/src + $TUSB_DIR$/lib/SEGGER_RTT/RTT + $PROJ_DIR$ + $TUSB_DIR$/hw + + + + $TUSB_DIR$/src/device/usbd.c + $TUSB_DIR$/src/device/usbd_control.c + + + $TUSB_DIR$/src/common/tusb_fifo.c + + + $TUSB_DIR$/src/class/audio/audio_device.c + + + $TUSB_DIR$/src/class/bth/bth_device.c + + + $TUSB_DIR$/src/class/cdc/cdc_device.c + $TUSB_DIR$/src/class/cdc/cdc_host.c + $TUSB_DIR$/src/class/cdc/cdc_rndis_host.c + + + $TUSB_DIR$/src/class/dfu/dfu_device.c + $TUSB_DIR$/src/class/dfu/dfu_rt_device.c + + + $TUSB_DIR$/src/class/hid/hid_device.c + $TUSB_DIR$/src/class/hid/hid_host.c + + + $TUSB_DIR$/src/class/midi/midi_device.c + + + $TUSB_DIR$/src/class/msc/msc_device.c + $TUSB_DIR$/src/class/msc/msc_host.c + + + $TUSB_DIR$/src/class/net/net_device.c + + + $TUSB_DIR$/src/class/usbtmc/usbtmc_device.c + + + $TUSB_DIR$/src/class/vendor/vendor_device.c + $TUSB_DIR$/src/class/vendor/vendor_host.c + + + $TUSB_DIR$/src/tusb.c + + + $TUSB_DIR$/src/host/hub.c + $TUSB_DIR$/src/host/usbh.c + $TUSB_DIR$/src/host/usbh_control.c + + + $TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c + + + $TUSB_DIR$/src/portable/ehci/ehci.c + + + $TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c + + + $TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c + + + $TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c + + + $TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c + + + $TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c + + + $TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c + + + $TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c + + + $TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c + $TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c + + + $TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c + + + $TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c + $TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c + + + $TUSB_DIR$/src/portable/ohci/ohci.c + + + $TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c + + + $TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c + + + $TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c + + + $TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c + + + $TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c + + + $TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c + + + $TUSB_DIR$/src/portable/template/dcd_template.c + + + $TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c + + + $TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c + + + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c + $TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c + + + $TUSB_DIR$/hw/bsp/board.c + + + $TUSB_DIR$/examples/device/board_test/src/main.c + $TUSB_DIR$/examples/device/board_test/src/tusb_config.h + + + \ No newline at end of file diff --git a/examples/device/cdc_dual_ports/iar_cdc_dual_ports.ipcf b/examples/device/cdc_dual_ports/iar_cdc_dual_ports.ipcf new file mode 100644 index 000000000..69e321150 --- /dev/null +++ b/examples/device/cdc_dual_ports/iar_cdc_dual_ports.ipcf @@ -0,0 +1,154 @@ + + + + $TUSB_DIR$/src + $TUSB_DIR$/lib/SEGGER_RTT/RTT + $PROJ_DIR$ + $TUSB_DIR$/hw + + + + $TUSB_DIR$/src/device/usbd.c + $TUSB_DIR$/src/device/usbd_control.c + + + $TUSB_DIR$/src/common/tusb_fifo.c + + + $TUSB_DIR$/src/class/audio/audio_device.c + + + $TUSB_DIR$/src/class/bth/bth_device.c + + + $TUSB_DIR$/src/class/cdc/cdc_device.c + $TUSB_DIR$/src/class/cdc/cdc_host.c + $TUSB_DIR$/src/class/cdc/cdc_rndis_host.c + + + $TUSB_DIR$/src/class/dfu/dfu_device.c + $TUSB_DIR$/src/class/dfu/dfu_rt_device.c + + + $TUSB_DIR$/src/class/hid/hid_device.c + $TUSB_DIR$/src/class/hid/hid_host.c + + + $TUSB_DIR$/src/class/midi/midi_device.c + + + $TUSB_DIR$/src/class/msc/msc_device.c + $TUSB_DIR$/src/class/msc/msc_host.c + + + $TUSB_DIR$/src/class/net/net_device.c + + + $TUSB_DIR$/src/class/usbtmc/usbtmc_device.c + + + $TUSB_DIR$/src/class/vendor/vendor_device.c + $TUSB_DIR$/src/class/vendor/vendor_host.c + + + $TUSB_DIR$/src/tusb.c + + + $TUSB_DIR$/src/host/hub.c + $TUSB_DIR$/src/host/usbh.c + $TUSB_DIR$/src/host/usbh_control.c + + + $TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c + + + $TUSB_DIR$/src/portable/ehci/ehci.c + + + $TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c + + + $TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c + + + $TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c + + + $TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c + + + $TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c + + + $TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c + + + $TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c + + + $TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c + $TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c + + + $TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c + + + $TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c + $TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c + + + $TUSB_DIR$/src/portable/ohci/ohci.c + + + $TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c + + + $TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c + + + $TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c + + + $TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c + + + $TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c + + + $TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c + + + $TUSB_DIR$/src/portable/template/dcd_template.c + + + $TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c + + + $TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c + + + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c + $TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c + + + $TUSB_DIR$/hw/bsp/board.c + + + $TUSB_DIR$/examples/device/cdc_dual_ports/src/main.c + $TUSB_DIR$/examples/device/cdc_dual_ports/src/tusb_config.h + $TUSB_DIR$/examples/device/cdc_dual_ports/src/usb_descriptors.c + + + \ No newline at end of file diff --git a/examples/device/cdc_msc/iar_cdc_msc.ipcf b/examples/device/cdc_msc/iar_cdc_msc.ipcf new file mode 100644 index 000000000..7b7576e8c --- /dev/null +++ b/examples/device/cdc_msc/iar_cdc_msc.ipcf @@ -0,0 +1,155 @@ + + + + $TUSB_DIR$/src + $TUSB_DIR$/lib/SEGGER_RTT/RTT + $PROJ_DIR$ + $TUSB_DIR$/hw + + + + $TUSB_DIR$/src/device/usbd.c + $TUSB_DIR$/src/device/usbd_control.c + + + $TUSB_DIR$/src/common/tusb_fifo.c + + + $TUSB_DIR$/src/class/audio/audio_device.c + + + $TUSB_DIR$/src/class/bth/bth_device.c + + + $TUSB_DIR$/src/class/cdc/cdc_device.c + $TUSB_DIR$/src/class/cdc/cdc_host.c + $TUSB_DIR$/src/class/cdc/cdc_rndis_host.c + + + $TUSB_DIR$/src/class/dfu/dfu_device.c + $TUSB_DIR$/src/class/dfu/dfu_rt_device.c + + + $TUSB_DIR$/src/class/hid/hid_device.c + $TUSB_DIR$/src/class/hid/hid_host.c + + + $TUSB_DIR$/src/class/midi/midi_device.c + + + $TUSB_DIR$/src/class/msc/msc_device.c + $TUSB_DIR$/src/class/msc/msc_host.c + + + $TUSB_DIR$/src/class/net/net_device.c + + + $TUSB_DIR$/src/class/usbtmc/usbtmc_device.c + + + $TUSB_DIR$/src/class/vendor/vendor_device.c + $TUSB_DIR$/src/class/vendor/vendor_host.c + + + $TUSB_DIR$/src/tusb.c + + + $TUSB_DIR$/src/host/hub.c + $TUSB_DIR$/src/host/usbh.c + $TUSB_DIR$/src/host/usbh_control.c + + + $TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c + + + $TUSB_DIR$/src/portable/ehci/ehci.c + + + $TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c + + + $TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c + + + $TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c + + + $TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c + + + $TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c + + + $TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c + + + $TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c + + + $TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c + $TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c + + + $TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c + + + $TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c + $TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c + + + $TUSB_DIR$/src/portable/ohci/ohci.c + + + $TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c + + + $TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c + + + $TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c + + + $TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c + + + $TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c + + + $TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c + + + $TUSB_DIR$/src/portable/template/dcd_template.c + + + $TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c + + + $TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c + + + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c + $TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c + + + $TUSB_DIR$/hw/bsp/board.c + + + $TUSB_DIR$/examples/device/cdc_msc/src/main.c + $TUSB_DIR$/examples/device/cdc_msc/src/msc_disk.c + $TUSB_DIR$/examples/device/cdc_msc/src/tusb_config.h + $TUSB_DIR$/examples/device/cdc_msc/src/usb_descriptors.c + + + \ No newline at end of file diff --git a/examples/device/cdc_msc_freertos/iar_cdc_msc_freertos.ipcf b/examples/device/cdc_msc_freertos/iar_cdc_msc_freertos.ipcf new file mode 100644 index 000000000..f1a00c391 --- /dev/null +++ b/examples/device/cdc_msc_freertos/iar_cdc_msc_freertos.ipcf @@ -0,0 +1,157 @@ + + + + $TUSB_DIR$/src + $TUSB_DIR$/lib/SEGGER_RTT/RTT + $PROJ_DIR$ + $TUSB_DIR$/hw + + + + $TUSB_DIR$/src/device/usbd.c + $TUSB_DIR$/src/device/usbd_control.c + + + $TUSB_DIR$/src/common/tusb_fifo.c + + + $TUSB_DIR$/src/class/audio/audio_device.c + + + $TUSB_DIR$/src/class/bth/bth_device.c + + + $TUSB_DIR$/src/class/cdc/cdc_device.c + $TUSB_DIR$/src/class/cdc/cdc_host.c + $TUSB_DIR$/src/class/cdc/cdc_rndis_host.c + + + $TUSB_DIR$/src/class/dfu/dfu_device.c + $TUSB_DIR$/src/class/dfu/dfu_rt_device.c + + + $TUSB_DIR$/src/class/hid/hid_device.c + $TUSB_DIR$/src/class/hid/hid_host.c + + + $TUSB_DIR$/src/class/midi/midi_device.c + + + $TUSB_DIR$/src/class/msc/msc_device.c + $TUSB_DIR$/src/class/msc/msc_host.c + + + $TUSB_DIR$/src/class/net/net_device.c + + + $TUSB_DIR$/src/class/usbtmc/usbtmc_device.c + + + $TUSB_DIR$/src/class/vendor/vendor_device.c + $TUSB_DIR$/src/class/vendor/vendor_host.c + + + $TUSB_DIR$/src/tusb.c + + + $TUSB_DIR$/src/host/hub.c + $TUSB_DIR$/src/host/usbh.c + $TUSB_DIR$/src/host/usbh_control.c + + + $TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c + + + $TUSB_DIR$/src/portable/ehci/ehci.c + + + $TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c + + + $TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c + + + $TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c + + + $TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c + + + $TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c + + + $TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c + + + $TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c + + + $TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c + $TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c + + + $TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c + + + $TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c + $TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c + + + $TUSB_DIR$/src/portable/ohci/ohci.c + + + $TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c + + + $TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c + + + $TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c + + + $TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c + + + $TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c + + + $TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c + + + $TUSB_DIR$/src/portable/template/dcd_template.c + + + $TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c + + + $TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c + + + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c + $TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c + + + $TUSB_DIR$/hw/bsp/board.c + + + $TUSB_DIR$/examples/device/cdc_msc_freertos/src/FreeRTOSConfig.h + $TUSB_DIR$/examples/device/cdc_msc_freertos/src/freertos_hook.c + $TUSB_DIR$/examples/device/cdc_msc_freertos/src/main.c + $TUSB_DIR$/examples/device/cdc_msc_freertos/src/msc_disk.c + $TUSB_DIR$/examples/device/cdc_msc_freertos/src/tusb_config.h + $TUSB_DIR$/examples/device/cdc_msc_freertos/src/usb_descriptors.c + + + \ No newline at end of file diff --git a/examples/device/dfu/iar_dfu.ipcf b/examples/device/dfu/iar_dfu.ipcf new file mode 100644 index 000000000..d2eb2f043 --- /dev/null +++ b/examples/device/dfu/iar_dfu.ipcf @@ -0,0 +1,154 @@ + + + + $TUSB_DIR$/src + $TUSB_DIR$/lib/SEGGER_RTT/RTT + $PROJ_DIR$ + $TUSB_DIR$/hw + + + + $TUSB_DIR$/src/device/usbd.c + $TUSB_DIR$/src/device/usbd_control.c + + + $TUSB_DIR$/src/common/tusb_fifo.c + + + $TUSB_DIR$/src/class/audio/audio_device.c + + + $TUSB_DIR$/src/class/bth/bth_device.c + + + $TUSB_DIR$/src/class/cdc/cdc_device.c + $TUSB_DIR$/src/class/cdc/cdc_host.c + $TUSB_DIR$/src/class/cdc/cdc_rndis_host.c + + + $TUSB_DIR$/src/class/dfu/dfu_device.c + $TUSB_DIR$/src/class/dfu/dfu_rt_device.c + + + $TUSB_DIR$/src/class/hid/hid_device.c + $TUSB_DIR$/src/class/hid/hid_host.c + + + $TUSB_DIR$/src/class/midi/midi_device.c + + + $TUSB_DIR$/src/class/msc/msc_device.c + $TUSB_DIR$/src/class/msc/msc_host.c + + + $TUSB_DIR$/src/class/net/net_device.c + + + $TUSB_DIR$/src/class/usbtmc/usbtmc_device.c + + + $TUSB_DIR$/src/class/vendor/vendor_device.c + $TUSB_DIR$/src/class/vendor/vendor_host.c + + + $TUSB_DIR$/src/tusb.c + + + $TUSB_DIR$/src/host/hub.c + $TUSB_DIR$/src/host/usbh.c + $TUSB_DIR$/src/host/usbh_control.c + + + $TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c + + + $TUSB_DIR$/src/portable/ehci/ehci.c + + + $TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c + + + $TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c + + + $TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c + + + $TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c + + + $TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c + + + $TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c + + + $TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c + + + $TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c + $TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c + + + $TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c + + + $TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c + $TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c + + + $TUSB_DIR$/src/portable/ohci/ohci.c + + + $TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c + + + $TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c + + + $TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c + + + $TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c + + + $TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c + + + $TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c + + + $TUSB_DIR$/src/portable/template/dcd_template.c + + + $TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c + + + $TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c + + + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c + $TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c + + + $TUSB_DIR$/hw/bsp/board.c + + + $TUSB_DIR$/examples/device/dfu/src/main.c + $TUSB_DIR$/examples/device/dfu/src/tusb_config.h + $TUSB_DIR$/examples/device/dfu/src/usb_descriptors.c + + + \ No newline at end of file diff --git a/examples/device/dfu_runtime/iar_dfu_runtime.ipcf b/examples/device/dfu_runtime/iar_dfu_runtime.ipcf new file mode 100644 index 000000000..18ade4125 --- /dev/null +++ b/examples/device/dfu_runtime/iar_dfu_runtime.ipcf @@ -0,0 +1,154 @@ + + + + $TUSB_DIR$/src + $TUSB_DIR$/lib/SEGGER_RTT/RTT + $PROJ_DIR$ + $TUSB_DIR$/hw + + + + $TUSB_DIR$/src/device/usbd.c + $TUSB_DIR$/src/device/usbd_control.c + + + $TUSB_DIR$/src/common/tusb_fifo.c + + + $TUSB_DIR$/src/class/audio/audio_device.c + + + $TUSB_DIR$/src/class/bth/bth_device.c + + + $TUSB_DIR$/src/class/cdc/cdc_device.c + $TUSB_DIR$/src/class/cdc/cdc_host.c + $TUSB_DIR$/src/class/cdc/cdc_rndis_host.c + + + $TUSB_DIR$/src/class/dfu/dfu_device.c + $TUSB_DIR$/src/class/dfu/dfu_rt_device.c + + + $TUSB_DIR$/src/class/hid/hid_device.c + $TUSB_DIR$/src/class/hid/hid_host.c + + + $TUSB_DIR$/src/class/midi/midi_device.c + + + $TUSB_DIR$/src/class/msc/msc_device.c + $TUSB_DIR$/src/class/msc/msc_host.c + + + $TUSB_DIR$/src/class/net/net_device.c + + + $TUSB_DIR$/src/class/usbtmc/usbtmc_device.c + + + $TUSB_DIR$/src/class/vendor/vendor_device.c + $TUSB_DIR$/src/class/vendor/vendor_host.c + + + $TUSB_DIR$/src/tusb.c + + + $TUSB_DIR$/src/host/hub.c + $TUSB_DIR$/src/host/usbh.c + $TUSB_DIR$/src/host/usbh_control.c + + + $TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c + + + $TUSB_DIR$/src/portable/ehci/ehci.c + + + $TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c + + + $TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c + + + $TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c + + + $TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c + + + $TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c + + + $TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c + + + $TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c + + + $TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c + $TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c + + + $TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c + + + $TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c + $TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c + + + $TUSB_DIR$/src/portable/ohci/ohci.c + + + $TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c + + + $TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c + + + $TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c + + + $TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c + + + $TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c + + + $TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c + + + $TUSB_DIR$/src/portable/template/dcd_template.c + + + $TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c + + + $TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c + + + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c + $TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c + + + $TUSB_DIR$/hw/bsp/board.c + + + $TUSB_DIR$/examples/device/dfu_runtime/src/main.c + $TUSB_DIR$/examples/device/dfu_runtime/src/tusb_config.h + $TUSB_DIR$/examples/device/dfu_runtime/src/usb_descriptors.c + + + \ No newline at end of file diff --git a/examples/device/dynamic_configuration/iar_dynamic_configuration.ipcf b/examples/device/dynamic_configuration/iar_dynamic_configuration.ipcf new file mode 100644 index 000000000..1185e774c --- /dev/null +++ b/examples/device/dynamic_configuration/iar_dynamic_configuration.ipcf @@ -0,0 +1,155 @@ + + + + $TUSB_DIR$/src + $TUSB_DIR$/lib/SEGGER_RTT/RTT + $PROJ_DIR$ + $TUSB_DIR$/hw + + + + $TUSB_DIR$/src/device/usbd.c + $TUSB_DIR$/src/device/usbd_control.c + + + $TUSB_DIR$/src/common/tusb_fifo.c + + + $TUSB_DIR$/src/class/audio/audio_device.c + + + $TUSB_DIR$/src/class/bth/bth_device.c + + + $TUSB_DIR$/src/class/cdc/cdc_device.c + $TUSB_DIR$/src/class/cdc/cdc_host.c + $TUSB_DIR$/src/class/cdc/cdc_rndis_host.c + + + $TUSB_DIR$/src/class/dfu/dfu_device.c + $TUSB_DIR$/src/class/dfu/dfu_rt_device.c + + + $TUSB_DIR$/src/class/hid/hid_device.c + $TUSB_DIR$/src/class/hid/hid_host.c + + + $TUSB_DIR$/src/class/midi/midi_device.c + + + $TUSB_DIR$/src/class/msc/msc_device.c + $TUSB_DIR$/src/class/msc/msc_host.c + + + $TUSB_DIR$/src/class/net/net_device.c + + + $TUSB_DIR$/src/class/usbtmc/usbtmc_device.c + + + $TUSB_DIR$/src/class/vendor/vendor_device.c + $TUSB_DIR$/src/class/vendor/vendor_host.c + + + $TUSB_DIR$/src/tusb.c + + + $TUSB_DIR$/src/host/hub.c + $TUSB_DIR$/src/host/usbh.c + $TUSB_DIR$/src/host/usbh_control.c + + + $TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c + + + $TUSB_DIR$/src/portable/ehci/ehci.c + + + $TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c + + + $TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c + + + $TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c + + + $TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c + + + $TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c + + + $TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c + + + $TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c + + + $TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c + $TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c + + + $TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c + + + $TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c + $TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c + + + $TUSB_DIR$/src/portable/ohci/ohci.c + + + $TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c + + + $TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c + + + $TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c + + + $TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c + + + $TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c + + + $TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c + + + $TUSB_DIR$/src/portable/template/dcd_template.c + + + $TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c + + + $TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c + + + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c + $TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c + + + $TUSB_DIR$/hw/bsp/board.c + + + $TUSB_DIR$/examples/device/dynamic_configuration/src/main.c + $TUSB_DIR$/examples/device/dynamic_configuration/src/msc_disk.c + $TUSB_DIR$/examples/device/dynamic_configuration/src/tusb_config.h + $TUSB_DIR$/examples/device/dynamic_configuration/src/usb_descriptors.c + + + \ No newline at end of file diff --git a/examples/device/hid_boot_interface/iar_hid_boot_interface.ipcf b/examples/device/hid_boot_interface/iar_hid_boot_interface.ipcf new file mode 100644 index 000000000..4214121d0 --- /dev/null +++ b/examples/device/hid_boot_interface/iar_hid_boot_interface.ipcf @@ -0,0 +1,155 @@ + + + + $TUSB_DIR$/src + $TUSB_DIR$/lib/SEGGER_RTT/RTT + $PROJ_DIR$ + $TUSB_DIR$/hw + + + + $TUSB_DIR$/src/device/usbd.c + $TUSB_DIR$/src/device/usbd_control.c + + + $TUSB_DIR$/src/common/tusb_fifo.c + + + $TUSB_DIR$/src/class/audio/audio_device.c + + + $TUSB_DIR$/src/class/bth/bth_device.c + + + $TUSB_DIR$/src/class/cdc/cdc_device.c + $TUSB_DIR$/src/class/cdc/cdc_host.c + $TUSB_DIR$/src/class/cdc/cdc_rndis_host.c + + + $TUSB_DIR$/src/class/dfu/dfu_device.c + $TUSB_DIR$/src/class/dfu/dfu_rt_device.c + + + $TUSB_DIR$/src/class/hid/hid_device.c + $TUSB_DIR$/src/class/hid/hid_host.c + + + $TUSB_DIR$/src/class/midi/midi_device.c + + + $TUSB_DIR$/src/class/msc/msc_device.c + $TUSB_DIR$/src/class/msc/msc_host.c + + + $TUSB_DIR$/src/class/net/net_device.c + + + $TUSB_DIR$/src/class/usbtmc/usbtmc_device.c + + + $TUSB_DIR$/src/class/vendor/vendor_device.c + $TUSB_DIR$/src/class/vendor/vendor_host.c + + + $TUSB_DIR$/src/tusb.c + + + $TUSB_DIR$/src/host/hub.c + $TUSB_DIR$/src/host/usbh.c + $TUSB_DIR$/src/host/usbh_control.c + + + $TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c + + + $TUSB_DIR$/src/portable/ehci/ehci.c + + + $TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c + + + $TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c + + + $TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c + + + $TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c + + + $TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c + + + $TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c + + + $TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c + + + $TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c + $TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c + + + $TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c + + + $TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c + $TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c + + + $TUSB_DIR$/src/portable/ohci/ohci.c + + + $TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c + + + $TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c + + + $TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c + + + $TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c + + + $TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c + + + $TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c + + + $TUSB_DIR$/src/portable/template/dcd_template.c + + + $TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c + + + $TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c + + + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c + $TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c + + + $TUSB_DIR$/hw/bsp/board.c + + + $TUSB_DIR$/examples/device/hid_boot_interface/src/main.c + $TUSB_DIR$/examples/device/hid_boot_interface/src/tusb_config.h + $TUSB_DIR$/examples/device/hid_boot_interface/src/usb_descriptors.c + $TUSB_DIR$/examples/device/hid_boot_interface/src/usb_descriptors.h + + + \ No newline at end of file diff --git a/examples/device/hid_composite/iar_hid_composite.ipcf b/examples/device/hid_composite/iar_hid_composite.ipcf new file mode 100644 index 000000000..a2c5c9855 --- /dev/null +++ b/examples/device/hid_composite/iar_hid_composite.ipcf @@ -0,0 +1,155 @@ + + + + $TUSB_DIR$/src + $TUSB_DIR$/lib/SEGGER_RTT/RTT + $PROJ_DIR$ + $TUSB_DIR$/hw + + + + $TUSB_DIR$/src/device/usbd.c + $TUSB_DIR$/src/device/usbd_control.c + + + $TUSB_DIR$/src/common/tusb_fifo.c + + + $TUSB_DIR$/src/class/audio/audio_device.c + + + $TUSB_DIR$/src/class/bth/bth_device.c + + + $TUSB_DIR$/src/class/cdc/cdc_device.c + $TUSB_DIR$/src/class/cdc/cdc_host.c + $TUSB_DIR$/src/class/cdc/cdc_rndis_host.c + + + $TUSB_DIR$/src/class/dfu/dfu_device.c + $TUSB_DIR$/src/class/dfu/dfu_rt_device.c + + + $TUSB_DIR$/src/class/hid/hid_device.c + $TUSB_DIR$/src/class/hid/hid_host.c + + + $TUSB_DIR$/src/class/midi/midi_device.c + + + $TUSB_DIR$/src/class/msc/msc_device.c + $TUSB_DIR$/src/class/msc/msc_host.c + + + $TUSB_DIR$/src/class/net/net_device.c + + + $TUSB_DIR$/src/class/usbtmc/usbtmc_device.c + + + $TUSB_DIR$/src/class/vendor/vendor_device.c + $TUSB_DIR$/src/class/vendor/vendor_host.c + + + $TUSB_DIR$/src/tusb.c + + + $TUSB_DIR$/src/host/hub.c + $TUSB_DIR$/src/host/usbh.c + $TUSB_DIR$/src/host/usbh_control.c + + + $TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c + + + $TUSB_DIR$/src/portable/ehci/ehci.c + + + $TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c + + + $TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c + + + $TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c + + + $TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c + + + $TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c + + + $TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c + + + $TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c + + + $TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c + $TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c + + + $TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c + + + $TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c + $TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c + + + $TUSB_DIR$/src/portable/ohci/ohci.c + + + $TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c + + + $TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c + + + $TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c + + + $TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c + + + $TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c + + + $TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c + + + $TUSB_DIR$/src/portable/template/dcd_template.c + + + $TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c + + + $TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c + + + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c + $TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c + + + $TUSB_DIR$/hw/bsp/board.c + + + $TUSB_DIR$/examples/device/hid_composite/src/main.c + $TUSB_DIR$/examples/device/hid_composite/src/tusb_config.h + $TUSB_DIR$/examples/device/hid_composite/src/usb_descriptors.c + $TUSB_DIR$/examples/device/hid_composite/src/usb_descriptors.h + + + \ No newline at end of file diff --git a/examples/device/hid_composite_freertos/iar_hid_composite_freertos.ipcf b/examples/device/hid_composite_freertos/iar_hid_composite_freertos.ipcf new file mode 100644 index 000000000..eabff34f5 --- /dev/null +++ b/examples/device/hid_composite_freertos/iar_hid_composite_freertos.ipcf @@ -0,0 +1,157 @@ + + + + $TUSB_DIR$/src + $TUSB_DIR$/lib/SEGGER_RTT/RTT + $PROJ_DIR$ + $TUSB_DIR$/hw + + + + $TUSB_DIR$/src/device/usbd.c + $TUSB_DIR$/src/device/usbd_control.c + + + $TUSB_DIR$/src/common/tusb_fifo.c + + + $TUSB_DIR$/src/class/audio/audio_device.c + + + $TUSB_DIR$/src/class/bth/bth_device.c + + + $TUSB_DIR$/src/class/cdc/cdc_device.c + $TUSB_DIR$/src/class/cdc/cdc_host.c + $TUSB_DIR$/src/class/cdc/cdc_rndis_host.c + + + $TUSB_DIR$/src/class/dfu/dfu_device.c + $TUSB_DIR$/src/class/dfu/dfu_rt_device.c + + + $TUSB_DIR$/src/class/hid/hid_device.c + $TUSB_DIR$/src/class/hid/hid_host.c + + + $TUSB_DIR$/src/class/midi/midi_device.c + + + $TUSB_DIR$/src/class/msc/msc_device.c + $TUSB_DIR$/src/class/msc/msc_host.c + + + $TUSB_DIR$/src/class/net/net_device.c + + + $TUSB_DIR$/src/class/usbtmc/usbtmc_device.c + + + $TUSB_DIR$/src/class/vendor/vendor_device.c + $TUSB_DIR$/src/class/vendor/vendor_host.c + + + $TUSB_DIR$/src/tusb.c + + + $TUSB_DIR$/src/host/hub.c + $TUSB_DIR$/src/host/usbh.c + $TUSB_DIR$/src/host/usbh_control.c + + + $TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c + + + $TUSB_DIR$/src/portable/ehci/ehci.c + + + $TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c + + + $TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c + + + $TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c + + + $TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c + + + $TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c + + + $TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c + + + $TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c + + + $TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c + $TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c + + + $TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c + + + $TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c + $TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c + + + $TUSB_DIR$/src/portable/ohci/ohci.c + + + $TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c + + + $TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c + + + $TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c + + + $TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c + + + $TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c + + + $TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c + + + $TUSB_DIR$/src/portable/template/dcd_template.c + + + $TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c + + + $TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c + + + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c + $TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c + + + $TUSB_DIR$/hw/bsp/board.c + + + $TUSB_DIR$/examples/device/hid_composite_freertos/src/FreeRTOSConfig.h + $TUSB_DIR$/examples/device/hid_composite_freertos/src/freertos_hook.c + $TUSB_DIR$/examples/device/hid_composite_freertos/src/main.c + $TUSB_DIR$/examples/device/hid_composite_freertos/src/tusb_config.h + $TUSB_DIR$/examples/device/hid_composite_freertos/src/usb_descriptors.c + $TUSB_DIR$/examples/device/hid_composite_freertos/src/usb_descriptors.h + + + \ No newline at end of file diff --git a/examples/device/hid_generic_inout/iar_hid_generic_inout.ipcf b/examples/device/hid_generic_inout/iar_hid_generic_inout.ipcf new file mode 100644 index 000000000..d917fa956 --- /dev/null +++ b/examples/device/hid_generic_inout/iar_hid_generic_inout.ipcf @@ -0,0 +1,154 @@ + + + + $TUSB_DIR$/src + $TUSB_DIR$/lib/SEGGER_RTT/RTT + $PROJ_DIR$ + $TUSB_DIR$/hw + + + + $TUSB_DIR$/src/device/usbd.c + $TUSB_DIR$/src/device/usbd_control.c + + + $TUSB_DIR$/src/common/tusb_fifo.c + + + $TUSB_DIR$/src/class/audio/audio_device.c + + + $TUSB_DIR$/src/class/bth/bth_device.c + + + $TUSB_DIR$/src/class/cdc/cdc_device.c + $TUSB_DIR$/src/class/cdc/cdc_host.c + $TUSB_DIR$/src/class/cdc/cdc_rndis_host.c + + + $TUSB_DIR$/src/class/dfu/dfu_device.c + $TUSB_DIR$/src/class/dfu/dfu_rt_device.c + + + $TUSB_DIR$/src/class/hid/hid_device.c + $TUSB_DIR$/src/class/hid/hid_host.c + + + $TUSB_DIR$/src/class/midi/midi_device.c + + + $TUSB_DIR$/src/class/msc/msc_device.c + $TUSB_DIR$/src/class/msc/msc_host.c + + + $TUSB_DIR$/src/class/net/net_device.c + + + $TUSB_DIR$/src/class/usbtmc/usbtmc_device.c + + + $TUSB_DIR$/src/class/vendor/vendor_device.c + $TUSB_DIR$/src/class/vendor/vendor_host.c + + + $TUSB_DIR$/src/tusb.c + + + $TUSB_DIR$/src/host/hub.c + $TUSB_DIR$/src/host/usbh.c + $TUSB_DIR$/src/host/usbh_control.c + + + $TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c + + + $TUSB_DIR$/src/portable/ehci/ehci.c + + + $TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c + + + $TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c + + + $TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c + + + $TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c + + + $TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c + + + $TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c + + + $TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c + + + $TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c + $TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c + + + $TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c + + + $TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c + $TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c + + + $TUSB_DIR$/src/portable/ohci/ohci.c + + + $TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c + + + $TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c + + + $TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c + + + $TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c + + + $TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c + + + $TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c + + + $TUSB_DIR$/src/portable/template/dcd_template.c + + + $TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c + + + $TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c + + + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c + $TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c + + + $TUSB_DIR$/hw/bsp/board.c + + + $TUSB_DIR$/examples/device/hid_generic_inout/src/main.c + $TUSB_DIR$/examples/device/hid_generic_inout/src/tusb_config.h + $TUSB_DIR$/examples/device/hid_generic_inout/src/usb_descriptors.c + + + \ No newline at end of file diff --git a/examples/device/hid_multiple_interface/iar_hid_multiple_interface.ipcf b/examples/device/hid_multiple_interface/iar_hid_multiple_interface.ipcf new file mode 100644 index 000000000..f50f39616 --- /dev/null +++ b/examples/device/hid_multiple_interface/iar_hid_multiple_interface.ipcf @@ -0,0 +1,154 @@ + + + + $TUSB_DIR$/src + $TUSB_DIR$/lib/SEGGER_RTT/RTT + $PROJ_DIR$ + $TUSB_DIR$/hw + + + + $TUSB_DIR$/src/device/usbd.c + $TUSB_DIR$/src/device/usbd_control.c + + + $TUSB_DIR$/src/common/tusb_fifo.c + + + $TUSB_DIR$/src/class/audio/audio_device.c + + + $TUSB_DIR$/src/class/bth/bth_device.c + + + $TUSB_DIR$/src/class/cdc/cdc_device.c + $TUSB_DIR$/src/class/cdc/cdc_host.c + $TUSB_DIR$/src/class/cdc/cdc_rndis_host.c + + + $TUSB_DIR$/src/class/dfu/dfu_device.c + $TUSB_DIR$/src/class/dfu/dfu_rt_device.c + + + $TUSB_DIR$/src/class/hid/hid_device.c + $TUSB_DIR$/src/class/hid/hid_host.c + + + $TUSB_DIR$/src/class/midi/midi_device.c + + + $TUSB_DIR$/src/class/msc/msc_device.c + $TUSB_DIR$/src/class/msc/msc_host.c + + + $TUSB_DIR$/src/class/net/net_device.c + + + $TUSB_DIR$/src/class/usbtmc/usbtmc_device.c + + + $TUSB_DIR$/src/class/vendor/vendor_device.c + $TUSB_DIR$/src/class/vendor/vendor_host.c + + + $TUSB_DIR$/src/tusb.c + + + $TUSB_DIR$/src/host/hub.c + $TUSB_DIR$/src/host/usbh.c + $TUSB_DIR$/src/host/usbh_control.c + + + $TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c + + + $TUSB_DIR$/src/portable/ehci/ehci.c + + + $TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c + + + $TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c + + + $TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c + + + $TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c + + + $TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c + + + $TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c + + + $TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c + + + $TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c + $TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c + + + $TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c + + + $TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c + $TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c + + + $TUSB_DIR$/src/portable/ohci/ohci.c + + + $TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c + + + $TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c + + + $TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c + + + $TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c + + + $TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c + + + $TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c + + + $TUSB_DIR$/src/portable/template/dcd_template.c + + + $TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c + + + $TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c + + + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c + $TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c + + + $TUSB_DIR$/hw/bsp/board.c + + + $TUSB_DIR$/examples/device/hid_multiple_interface/src/main.c + $TUSB_DIR$/examples/device/hid_multiple_interface/src/tusb_config.h + $TUSB_DIR$/examples/device/hid_multiple_interface/src/usb_descriptors.c + + + \ No newline at end of file diff --git a/examples/device/midi_test/iar_midi_test.ipcf b/examples/device/midi_test/iar_midi_test.ipcf new file mode 100644 index 000000000..f8ab96a1f --- /dev/null +++ b/examples/device/midi_test/iar_midi_test.ipcf @@ -0,0 +1,154 @@ + + + + $TUSB_DIR$/src + $TUSB_DIR$/lib/SEGGER_RTT/RTT + $PROJ_DIR$ + $TUSB_DIR$/hw + + + + $TUSB_DIR$/src/device/usbd.c + $TUSB_DIR$/src/device/usbd_control.c + + + $TUSB_DIR$/src/common/tusb_fifo.c + + + $TUSB_DIR$/src/class/audio/audio_device.c + + + $TUSB_DIR$/src/class/bth/bth_device.c + + + $TUSB_DIR$/src/class/cdc/cdc_device.c + $TUSB_DIR$/src/class/cdc/cdc_host.c + $TUSB_DIR$/src/class/cdc/cdc_rndis_host.c + + + $TUSB_DIR$/src/class/dfu/dfu_device.c + $TUSB_DIR$/src/class/dfu/dfu_rt_device.c + + + $TUSB_DIR$/src/class/hid/hid_device.c + $TUSB_DIR$/src/class/hid/hid_host.c + + + $TUSB_DIR$/src/class/midi/midi_device.c + + + $TUSB_DIR$/src/class/msc/msc_device.c + $TUSB_DIR$/src/class/msc/msc_host.c + + + $TUSB_DIR$/src/class/net/net_device.c + + + $TUSB_DIR$/src/class/usbtmc/usbtmc_device.c + + + $TUSB_DIR$/src/class/vendor/vendor_device.c + $TUSB_DIR$/src/class/vendor/vendor_host.c + + + $TUSB_DIR$/src/tusb.c + + + $TUSB_DIR$/src/host/hub.c + $TUSB_DIR$/src/host/usbh.c + $TUSB_DIR$/src/host/usbh_control.c + + + $TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c + + + $TUSB_DIR$/src/portable/ehci/ehci.c + + + $TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c + + + $TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c + + + $TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c + + + $TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c + + + $TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c + + + $TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c + + + $TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c + + + $TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c + $TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c + + + $TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c + + + $TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c + $TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c + + + $TUSB_DIR$/src/portable/ohci/ohci.c + + + $TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c + + + $TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c + + + $TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c + + + $TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c + + + $TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c + + + $TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c + + + $TUSB_DIR$/src/portable/template/dcd_template.c + + + $TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c + + + $TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c + + + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c + $TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c + + + $TUSB_DIR$/hw/bsp/board.c + + + $TUSB_DIR$/examples/device/midi_test/src/main.c + $TUSB_DIR$/examples/device/midi_test/src/tusb_config.h + $TUSB_DIR$/examples/device/midi_test/src/usb_descriptors.c + + + \ No newline at end of file diff --git a/examples/device/msc_dual_lun/iar_msc_dual_lun.ipcf b/examples/device/msc_dual_lun/iar_msc_dual_lun.ipcf new file mode 100644 index 000000000..257230891 --- /dev/null +++ b/examples/device/msc_dual_lun/iar_msc_dual_lun.ipcf @@ -0,0 +1,155 @@ + + + + $TUSB_DIR$/src + $TUSB_DIR$/lib/SEGGER_RTT/RTT + $PROJ_DIR$ + $TUSB_DIR$/hw + + + + $TUSB_DIR$/src/device/usbd.c + $TUSB_DIR$/src/device/usbd_control.c + + + $TUSB_DIR$/src/common/tusb_fifo.c + + + $TUSB_DIR$/src/class/audio/audio_device.c + + + $TUSB_DIR$/src/class/bth/bth_device.c + + + $TUSB_DIR$/src/class/cdc/cdc_device.c + $TUSB_DIR$/src/class/cdc/cdc_host.c + $TUSB_DIR$/src/class/cdc/cdc_rndis_host.c + + + $TUSB_DIR$/src/class/dfu/dfu_device.c + $TUSB_DIR$/src/class/dfu/dfu_rt_device.c + + + $TUSB_DIR$/src/class/hid/hid_device.c + $TUSB_DIR$/src/class/hid/hid_host.c + + + $TUSB_DIR$/src/class/midi/midi_device.c + + + $TUSB_DIR$/src/class/msc/msc_device.c + $TUSB_DIR$/src/class/msc/msc_host.c + + + $TUSB_DIR$/src/class/net/net_device.c + + + $TUSB_DIR$/src/class/usbtmc/usbtmc_device.c + + + $TUSB_DIR$/src/class/vendor/vendor_device.c + $TUSB_DIR$/src/class/vendor/vendor_host.c + + + $TUSB_DIR$/src/tusb.c + + + $TUSB_DIR$/src/host/hub.c + $TUSB_DIR$/src/host/usbh.c + $TUSB_DIR$/src/host/usbh_control.c + + + $TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c + + + $TUSB_DIR$/src/portable/ehci/ehci.c + + + $TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c + + + $TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c + + + $TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c + + + $TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c + + + $TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c + + + $TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c + + + $TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c + + + $TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c + $TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c + + + $TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c + + + $TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c + $TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c + + + $TUSB_DIR$/src/portable/ohci/ohci.c + + + $TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c + + + $TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c + + + $TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c + + + $TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c + + + $TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c + + + $TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c + + + $TUSB_DIR$/src/portable/template/dcd_template.c + + + $TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c + + + $TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c + + + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c + $TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c + + + $TUSB_DIR$/hw/bsp/board.c + + + $TUSB_DIR$/examples/device/msc_dual_lun/src/main.c + $TUSB_DIR$/examples/device/msc_dual_lun/src/msc_disk_dual.c + $TUSB_DIR$/examples/device/msc_dual_lun/src/tusb_config.h + $TUSB_DIR$/examples/device/msc_dual_lun/src/usb_descriptors.c + + + \ No newline at end of file diff --git a/examples/device/net_lwip_webserver/iar_net_lwip_webserver.ipcf b/examples/device/net_lwip_webserver/iar_net_lwip_webserver.ipcf new file mode 100644 index 000000000..1fb5b1eac --- /dev/null +++ b/examples/device/net_lwip_webserver/iar_net_lwip_webserver.ipcf @@ -0,0 +1,155 @@ + + + + $TUSB_DIR$/src + $TUSB_DIR$/lib/SEGGER_RTT/RTT + $PROJ_DIR$ + $TUSB_DIR$/hw + + + + $TUSB_DIR$/src/device/usbd.c + $TUSB_DIR$/src/device/usbd_control.c + + + $TUSB_DIR$/src/common/tusb_fifo.c + + + $TUSB_DIR$/src/class/audio/audio_device.c + + + $TUSB_DIR$/src/class/bth/bth_device.c + + + $TUSB_DIR$/src/class/cdc/cdc_device.c + $TUSB_DIR$/src/class/cdc/cdc_host.c + $TUSB_DIR$/src/class/cdc/cdc_rndis_host.c + + + $TUSB_DIR$/src/class/dfu/dfu_device.c + $TUSB_DIR$/src/class/dfu/dfu_rt_device.c + + + $TUSB_DIR$/src/class/hid/hid_device.c + $TUSB_DIR$/src/class/hid/hid_host.c + + + $TUSB_DIR$/src/class/midi/midi_device.c + + + $TUSB_DIR$/src/class/msc/msc_device.c + $TUSB_DIR$/src/class/msc/msc_host.c + + + $TUSB_DIR$/src/class/net/net_device.c + + + $TUSB_DIR$/src/class/usbtmc/usbtmc_device.c + + + $TUSB_DIR$/src/class/vendor/vendor_device.c + $TUSB_DIR$/src/class/vendor/vendor_host.c + + + $TUSB_DIR$/src/tusb.c + + + $TUSB_DIR$/src/host/hub.c + $TUSB_DIR$/src/host/usbh.c + $TUSB_DIR$/src/host/usbh_control.c + + + $TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c + + + $TUSB_DIR$/src/portable/ehci/ehci.c + + + $TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c + + + $TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c + + + $TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c + + + $TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c + + + $TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c + + + $TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c + + + $TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c + + + $TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c + $TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c + + + $TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c + + + $TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c + $TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c + + + $TUSB_DIR$/src/portable/ohci/ohci.c + + + $TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c + + + $TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c + + + $TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c + + + $TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c + + + $TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c + + + $TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c + + + $TUSB_DIR$/src/portable/template/dcd_template.c + + + $TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c + + + $TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c + + + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c + $TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c + + + $TUSB_DIR$/hw/bsp/board.c + + + $TUSB_DIR$/examples/device/net_lwip_webserver/src/lwipopts.h + $TUSB_DIR$/examples/device/net_lwip_webserver/src/main.c + $TUSB_DIR$/examples/device/net_lwip_webserver/src/tusb_config.h + $TUSB_DIR$/examples/device/net_lwip_webserver/src/usb_descriptors.c + + + \ No newline at end of file diff --git a/examples/device/uac2_headset/iar_uac2_headset.ipcf b/examples/device/uac2_headset/iar_uac2_headset.ipcf new file mode 100644 index 000000000..1d1b9b88c --- /dev/null +++ b/examples/device/uac2_headset/iar_uac2_headset.ipcf @@ -0,0 +1,155 @@ + + + + $TUSB_DIR$/src + $TUSB_DIR$/lib/SEGGER_RTT/RTT + $PROJ_DIR$ + $TUSB_DIR$/hw + + + + $TUSB_DIR$/src/device/usbd.c + $TUSB_DIR$/src/device/usbd_control.c + + + $TUSB_DIR$/src/common/tusb_fifo.c + + + $TUSB_DIR$/src/class/audio/audio_device.c + + + $TUSB_DIR$/src/class/bth/bth_device.c + + + $TUSB_DIR$/src/class/cdc/cdc_device.c + $TUSB_DIR$/src/class/cdc/cdc_host.c + $TUSB_DIR$/src/class/cdc/cdc_rndis_host.c + + + $TUSB_DIR$/src/class/dfu/dfu_device.c + $TUSB_DIR$/src/class/dfu/dfu_rt_device.c + + + $TUSB_DIR$/src/class/hid/hid_device.c + $TUSB_DIR$/src/class/hid/hid_host.c + + + $TUSB_DIR$/src/class/midi/midi_device.c + + + $TUSB_DIR$/src/class/msc/msc_device.c + $TUSB_DIR$/src/class/msc/msc_host.c + + + $TUSB_DIR$/src/class/net/net_device.c + + + $TUSB_DIR$/src/class/usbtmc/usbtmc_device.c + + + $TUSB_DIR$/src/class/vendor/vendor_device.c + $TUSB_DIR$/src/class/vendor/vendor_host.c + + + $TUSB_DIR$/src/tusb.c + + + $TUSB_DIR$/src/host/hub.c + $TUSB_DIR$/src/host/usbh.c + $TUSB_DIR$/src/host/usbh_control.c + + + $TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c + + + $TUSB_DIR$/src/portable/ehci/ehci.c + + + $TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c + + + $TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c + + + $TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c + + + $TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c + + + $TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c + + + $TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c + + + $TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c + + + $TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c + $TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c + + + $TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c + + + $TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c + $TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c + + + $TUSB_DIR$/src/portable/ohci/ohci.c + + + $TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c + + + $TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c + + + $TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c + + + $TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c + + + $TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c + + + $TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c + + + $TUSB_DIR$/src/portable/template/dcd_template.c + + + $TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c + + + $TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c + + + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c + $TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c + + + $TUSB_DIR$/hw/bsp/board.c + + + $TUSB_DIR$/examples/device/uac2_headset/src/main.c + $TUSB_DIR$/examples/device/uac2_headset/src/tusb_config.h + $TUSB_DIR$/examples/device/uac2_headset/src/usb_descriptors.c + $TUSB_DIR$/examples/device/uac2_headset/src/usb_descriptors.h + + + \ No newline at end of file diff --git a/examples/device/usbtmc/iar_usbtmc.ipcf b/examples/device/usbtmc/iar_usbtmc.ipcf new file mode 100644 index 000000000..20a6f954a --- /dev/null +++ b/examples/device/usbtmc/iar_usbtmc.ipcf @@ -0,0 +1,157 @@ + + + + $TUSB_DIR$/src + $TUSB_DIR$/lib/SEGGER_RTT/RTT + $PROJ_DIR$ + $TUSB_DIR$/hw + + + + $TUSB_DIR$/src/device/usbd.c + $TUSB_DIR$/src/device/usbd_control.c + + + $TUSB_DIR$/src/common/tusb_fifo.c + + + $TUSB_DIR$/src/class/audio/audio_device.c + + + $TUSB_DIR$/src/class/bth/bth_device.c + + + $TUSB_DIR$/src/class/cdc/cdc_device.c + $TUSB_DIR$/src/class/cdc/cdc_host.c + $TUSB_DIR$/src/class/cdc/cdc_rndis_host.c + + + $TUSB_DIR$/src/class/dfu/dfu_device.c + $TUSB_DIR$/src/class/dfu/dfu_rt_device.c + + + $TUSB_DIR$/src/class/hid/hid_device.c + $TUSB_DIR$/src/class/hid/hid_host.c + + + $TUSB_DIR$/src/class/midi/midi_device.c + + + $TUSB_DIR$/src/class/msc/msc_device.c + $TUSB_DIR$/src/class/msc/msc_host.c + + + $TUSB_DIR$/src/class/net/net_device.c + + + $TUSB_DIR$/src/class/usbtmc/usbtmc_device.c + + + $TUSB_DIR$/src/class/vendor/vendor_device.c + $TUSB_DIR$/src/class/vendor/vendor_host.c + + + $TUSB_DIR$/src/tusb.c + + + $TUSB_DIR$/src/host/hub.c + $TUSB_DIR$/src/host/usbh.c + $TUSB_DIR$/src/host/usbh_control.c + + + $TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c + + + $TUSB_DIR$/src/portable/ehci/ehci.c + + + $TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c + + + $TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c + + + $TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c + + + $TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c + + + $TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c + + + $TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c + + + $TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c + + + $TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c + $TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c + + + $TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c + + + $TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c + $TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c + + + $TUSB_DIR$/src/portable/ohci/ohci.c + + + $TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c + + + $TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c + + + $TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c + + + $TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c + + + $TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c + + + $TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c + + + $TUSB_DIR$/src/portable/template/dcd_template.c + + + $TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c + + + $TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c + + + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c + $TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c + + + $TUSB_DIR$/hw/bsp/board.c + + + $TUSB_DIR$/examples/device/usbtmc/src/main.c + $TUSB_DIR$/examples/device/usbtmc/src/main.h + $TUSB_DIR$/examples/device/usbtmc/src/tusb_config.h + $TUSB_DIR$/examples/device/usbtmc/src/usbtmc_app.c + $TUSB_DIR$/examples/device/usbtmc/src/usbtmc_app.h + $TUSB_DIR$/examples/device/usbtmc/src/usb_descriptors.c + + + \ No newline at end of file diff --git a/examples/device/webusb_serial/iar_webusb_serial.ipcf b/examples/device/webusb_serial/iar_webusb_serial.ipcf new file mode 100644 index 000000000..391b21451 --- /dev/null +++ b/examples/device/webusb_serial/iar_webusb_serial.ipcf @@ -0,0 +1,155 @@ + + + + $TUSB_DIR$/src + $TUSB_DIR$/lib/SEGGER_RTT/RTT + $PROJ_DIR$ + $TUSB_DIR$/hw + + + + $TUSB_DIR$/src/device/usbd.c + $TUSB_DIR$/src/device/usbd_control.c + + + $TUSB_DIR$/src/common/tusb_fifo.c + + + $TUSB_DIR$/src/class/audio/audio_device.c + + + $TUSB_DIR$/src/class/bth/bth_device.c + + + $TUSB_DIR$/src/class/cdc/cdc_device.c + $TUSB_DIR$/src/class/cdc/cdc_host.c + $TUSB_DIR$/src/class/cdc/cdc_rndis_host.c + + + $TUSB_DIR$/src/class/dfu/dfu_device.c + $TUSB_DIR$/src/class/dfu/dfu_rt_device.c + + + $TUSB_DIR$/src/class/hid/hid_device.c + $TUSB_DIR$/src/class/hid/hid_host.c + + + $TUSB_DIR$/src/class/midi/midi_device.c + + + $TUSB_DIR$/src/class/msc/msc_device.c + $TUSB_DIR$/src/class/msc/msc_host.c + + + $TUSB_DIR$/src/class/net/net_device.c + + + $TUSB_DIR$/src/class/usbtmc/usbtmc_device.c + + + $TUSB_DIR$/src/class/vendor/vendor_device.c + $TUSB_DIR$/src/class/vendor/vendor_host.c + + + $TUSB_DIR$/src/tusb.c + + + $TUSB_DIR$/src/host/hub.c + $TUSB_DIR$/src/host/usbh.c + $TUSB_DIR$/src/host/usbh_control.c + + + $TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c + + + $TUSB_DIR$/src/portable/ehci/ehci.c + + + $TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c + + + $TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c + + + $TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c + + + $TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c + + + $TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c + + + $TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c + + + $TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c + + + $TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c + $TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c + + + $TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c + + + $TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c + $TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c + + + $TUSB_DIR$/src/portable/ohci/ohci.c + + + $TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c + + + $TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c + + + $TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c + + + $TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c + + + $TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c + + + $TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c + + + $TUSB_DIR$/src/portable/template/dcd_template.c + + + $TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c + + + $TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c + + + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c + $TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c + + + $TUSB_DIR$/hw/bsp/board.c + + + $TUSB_DIR$/examples/device/webusb_serial/src/main.c + $TUSB_DIR$/examples/device/webusb_serial/src/tusb_config.h + $TUSB_DIR$/examples/device/webusb_serial/src/usb_descriptors.c + $TUSB_DIR$/examples/device/webusb_serial/src/usb_descriptors.h + + + \ No newline at end of file diff --git a/examples/host/cdc_msc_hid/iar_cdc_msc_hid.ipcf b/examples/host/cdc_msc_hid/iar_cdc_msc_hid.ipcf new file mode 100644 index 000000000..c3d48b369 --- /dev/null +++ b/examples/host/cdc_msc_hid/iar_cdc_msc_hid.ipcf @@ -0,0 +1,155 @@ + + + + $TUSB_DIR$/src + $TUSB_DIR$/lib/SEGGER_RTT/RTT + $PROJ_DIR$ + $TUSB_DIR$/hw + + + + $TUSB_DIR$/src/device/usbd.c + $TUSB_DIR$/src/device/usbd_control.c + + + $TUSB_DIR$/src/common/tusb_fifo.c + + + $TUSB_DIR$/src/class/audio/audio_device.c + + + $TUSB_DIR$/src/class/bth/bth_device.c + + + $TUSB_DIR$/src/class/cdc/cdc_device.c + $TUSB_DIR$/src/class/cdc/cdc_host.c + $TUSB_DIR$/src/class/cdc/cdc_rndis_host.c + + + $TUSB_DIR$/src/class/dfu/dfu_device.c + $TUSB_DIR$/src/class/dfu/dfu_rt_device.c + + + $TUSB_DIR$/src/class/hid/hid_device.c + $TUSB_DIR$/src/class/hid/hid_host.c + + + $TUSB_DIR$/src/class/midi/midi_device.c + + + $TUSB_DIR$/src/class/msc/msc_device.c + $TUSB_DIR$/src/class/msc/msc_host.c + + + $TUSB_DIR$/src/class/net/net_device.c + + + $TUSB_DIR$/src/class/usbtmc/usbtmc_device.c + + + $TUSB_DIR$/src/class/vendor/vendor_device.c + $TUSB_DIR$/src/class/vendor/vendor_host.c + + + $TUSB_DIR$/src/tusb.c + + + $TUSB_DIR$/src/host/hub.c + $TUSB_DIR$/src/host/usbh.c + $TUSB_DIR$/src/host/usbh_control.c + + + $TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c + + + $TUSB_DIR$/src/portable/ehci/ehci.c + + + $TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c + + + $TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c + + + $TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c + + + $TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c + + + $TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c + + + $TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c + + + $TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c + + + $TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c + $TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c + + + $TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c + + + $TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c + $TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c + + + $TUSB_DIR$/src/portable/ohci/ohci.c + + + $TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c + + + $TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c + + + $TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c + + + $TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c + + + $TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c + + + $TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c + + + $TUSB_DIR$/src/portable/template/dcd_template.c + + + $TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c + + + $TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c + + + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c + $TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c + + + $TUSB_DIR$/hw/bsp/board.c + + + $TUSB_DIR$/examples/host/cdc_msc_hid/src/hid_app.c + $TUSB_DIR$/examples/host/cdc_msc_hid/src/main.c + $TUSB_DIR$/examples/host/cdc_msc_hid/src/msc_app.c + $TUSB_DIR$/examples/host/cdc_msc_hid/src/tusb_config.h + + + \ No newline at end of file diff --git a/examples/host/hid_controller/iar_hid_controller.ipcf b/examples/host/hid_controller/iar_hid_controller.ipcf new file mode 100644 index 000000000..b3ce73a91 --- /dev/null +++ b/examples/host/hid_controller/iar_hid_controller.ipcf @@ -0,0 +1,154 @@ + + + + $TUSB_DIR$/src + $TUSB_DIR$/lib/SEGGER_RTT/RTT + $PROJ_DIR$ + $TUSB_DIR$/hw + + + + $TUSB_DIR$/src/device/usbd.c + $TUSB_DIR$/src/device/usbd_control.c + + + $TUSB_DIR$/src/common/tusb_fifo.c + + + $TUSB_DIR$/src/class/audio/audio_device.c + + + $TUSB_DIR$/src/class/bth/bth_device.c + + + $TUSB_DIR$/src/class/cdc/cdc_device.c + $TUSB_DIR$/src/class/cdc/cdc_host.c + $TUSB_DIR$/src/class/cdc/cdc_rndis_host.c + + + $TUSB_DIR$/src/class/dfu/dfu_device.c + $TUSB_DIR$/src/class/dfu/dfu_rt_device.c + + + $TUSB_DIR$/src/class/hid/hid_device.c + $TUSB_DIR$/src/class/hid/hid_host.c + + + $TUSB_DIR$/src/class/midi/midi_device.c + + + $TUSB_DIR$/src/class/msc/msc_device.c + $TUSB_DIR$/src/class/msc/msc_host.c + + + $TUSB_DIR$/src/class/net/net_device.c + + + $TUSB_DIR$/src/class/usbtmc/usbtmc_device.c + + + $TUSB_DIR$/src/class/vendor/vendor_device.c + $TUSB_DIR$/src/class/vendor/vendor_host.c + + + $TUSB_DIR$/src/tusb.c + + + $TUSB_DIR$/src/host/hub.c + $TUSB_DIR$/src/host/usbh.c + $TUSB_DIR$/src/host/usbh_control.c + + + $TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c + + + $TUSB_DIR$/src/portable/ehci/ehci.c + + + $TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c + + + $TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c + + + $TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c + + + $TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c + + + $TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c + + + $TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c + + + $TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c + + + $TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c + $TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c + + + $TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c + + + $TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c + $TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c + + + $TUSB_DIR$/src/portable/ohci/ohci.c + + + $TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c + + + $TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c + + + $TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c + + + $TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c + + + $TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c + + + $TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c + + + $TUSB_DIR$/src/portable/template/dcd_template.c + + + $TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c + + + $TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c + + + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c + $TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c + + + $TUSB_DIR$/hw/bsp/board.c + + + $TUSB_DIR$/examples/host/hid_controller/src/hid_app.c + $TUSB_DIR$/examples/host/hid_controller/src/main.c + $TUSB_DIR$/examples/host/hid_controller/src/tusb_config.h + + + \ No newline at end of file diff --git a/tools/iar.ipcf b/tools/iar.ipcf new file mode 100644 index 000000000..b8e50a1d2 --- /dev/null +++ b/tools/iar.ipcf @@ -0,0 +1,147 @@ + + + + + $TUSB_DIR$/src + $TUSB_DIR$/lib/SEGGER_RTT/RTT + $PROJ_DIR$ + + + + $TUSB_DIR$/src/device/usbd.c + $TUSB_DIR$/src/device/usbd_control.c + + + $TUSB_DIR$/src/common/tusb_fifo.c + + + $TUSB_DIR$/src/class/audio/audio_device.c + + + $TUSB_DIR$/src/class/bth/bth_device.c + + + $TUSB_DIR$/src/class/cdc/cdc_device.c + $TUSB_DIR$/src/class/cdc/cdc_host.c + $TUSB_DIR$/src/class/cdc/cdc_rndis_host.c + + + $TUSB_DIR$/src/class/dfu/dfu_device.c + $TUSB_DIR$/src/class/dfu/dfu_rt_device.c + + + $TUSB_DIR$/src/class/hid/hid_device.c + $TUSB_DIR$/src/class/hid/hid_host.c + + + $TUSB_DIR$/src/class/midi/midi_device.c + + + $TUSB_DIR$/src/class/msc/msc_device.c + $TUSB_DIR$/src/class/msc/msc_host.c + + + $TUSB_DIR$/src/class/net/net_device.c + + + $TUSB_DIR$/src/class/usbtmc/usbtmc_device.c + + + $TUSB_DIR$/src/class/vendor/vendor_device.c + $TUSB_DIR$/src/class/vendor/vendor_host.c + + + $TUSB_DIR$/src/tusb.c + + + $TUSB_DIR$/src/host/hub.c + $TUSB_DIR$/src/host/usbh.c + $TUSB_DIR$/src/host/usbh_control.c + + + $TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c + + + $TUSB_DIR$/src/portable/ehci/ehci.c + + + $TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c + + + $TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c + + + $TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c + + + $TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c + + + $TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c + + + $TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c + + + $TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c + + + $TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c + $TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c + + + $TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c + + + $TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c + $TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c + + + $TUSB_DIR$/src/portable/ohci/ohci.c + + + $TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c + + + $TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c + + + $TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c + + + $TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c + + + $TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c + + + $TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c + + + $TUSB_DIR$/src/portable/template/dcd_template.c + + + $TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c + + + $TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c + + + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c + $TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c + + + + diff --git a/tools/iar_gen.py b/tools/iar_gen.py new file mode 100644 index 000000000..b8c270ff7 --- /dev/null +++ b/tools/iar_gen.py @@ -0,0 +1,51 @@ +#!/usr/bin/python3 + +import os +import xml.dom.minidom as XML + +# Read base configuration +base = "" +with open("iar.ipcf") as f: + base = f.read() + +# Enumerate all device/host examples +dir_1 = os.listdir("../examples") +for dir_2 in dir_1: + if os.path.isdir("../examples/{}".format(dir_2)): + print(dir_2) + examples = os.listdir("../examples/{}".format(dir_2)) + for example in examples: + if os.path.isdir("../examples/{}/{}".format(dir_2, example)): + print("../examples/{}/{}".format(dir_2, example)) + conf = XML.parseString(base) + files = conf.getElementsByTagName("files")[0] + inc = conf.getElementsByTagName("includePath")[0] + # Add bsp inc + path = conf.createElement('path') + path_txt = conf.createTextNode("$TUSB_DIR$/hw") + path.appendChild(path_txt) + inc.appendChild(path) + # Add board.c/.h + grp = conf.createElement('group') + grp.setAttribute("name", "bsp") + path = conf.createElement('path') + path_txt = conf.createTextNode("$TUSB_DIR$/hw/bsp/board.c") + path.appendChild(path_txt) + grp.appendChild(path) + files.appendChild(grp) + # Add example's .c/.h + grp = conf.createElement('group') + grp.setAttribute("name", "example") + for file in os.listdir("../examples/{}/{}/src".format(dir_2, example)): + if file.endswith(".c") or file.endswith(".h"): + path = conf.createElement('path') + path.setAttribute("copyTo", "$PROJ_DIR$/{}".format(file)) + path_txt = conf.createTextNode("$TUSB_DIR$/examples/{0}/{1}/src/{2}".format(dir_2, example, file)) + path.appendChild(path_txt) + grp.appendChild(path) + files.appendChild(grp) + cfg_str = conf.toprettyxml() + cfg_str = '\n'.join([s for s in cfg_str.splitlines() if s.strip()]) + #print(cfg_str) + with open("../examples/{0}/{1}/iar_{1}.ipcf".format(dir_2, example), 'w') as f: + f.write(cfg_str) -- cgit v1.3.1 From fa030075c228390741e450664506892d317c0038 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 6 Sep 2021 19:26:28 +0700 Subject: Revert "Fix for MSC during stage STATUS" This reverts commit 2e23f3dd7287186445aeab39108f81c51644ed77. --- src/class/msc/msc_device.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c index 71875b014..6b3a392a8 100644 --- a/src/class/msc/msc_device.c +++ b/src/class/msc/msc_device.c @@ -601,10 +601,10 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t // skip status if epin is currently stalled, will do it when received Clear Stall request if ( !usbd_edpt_stalled(rhport, p_msc->ep_in) ) { - if ( (p_msc->total_len > p_msc->xferred_len) && is_data_in(p_cbw->dir) ) + if ( (p_cbw->total_bytes > p_msc->xferred_len) && is_data_in(p_cbw->dir) ) { // 6.7 The 13 Cases: case 5 (Hi > Di): STALL before status - TU_LOG(MSC_DEBUG, " SCSI case 5 (Hi > Di): %lu > %lu\r\n", p_msc->total_len, p_msc->xferred_len); + TU_LOG(MSC_DEBUG, " SCSI case 5 (Hi > Di): %lu > %lu\r\n", p_cbw->total_bytes, p_msc->xferred_len); usbd_edpt_stall(rhport, p_msc->ep_in); }else { -- cgit v1.3.1 From c53ce53058fc4d2cd7928836cdc2a83615287f3e Mon Sep 17 00:00:00 2001 From: Christian Arlt Date: Mon, 6 Sep 2021 19:38:31 +0200 Subject: Added Sony DualShock4 CUH-ZCT1E pid --- examples/host/hid_controller/src/hid_app.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/examples/host/hid_controller/src/hid_app.c b/examples/host/hid_controller/src/hid_app.c index c61ce70f3..ce084dc85 100644 --- a/examples/host/hid_controller/src/hid_app.c +++ b/examples/host/hid_controller/src/hid_app.c @@ -111,7 +111,7 @@ static inline bool is_sony_ds4(uint8_t dev_addr) uint16_t vid, pid; tuh_vid_pid_get(dev_addr, &vid, &pid); - return (vid == 0x054c && pid == 0x09cc); + return ( (vid == 0x054c && (pid == 0x09cc || pid == 0x05c4)) ); // Sony DualShock4 } //--------------------------------------------------------------------+ -- cgit v1.3.1 From a0646f20ba515185ec12d9da4ff5954f2db8bef2 Mon Sep 17 00:00:00 2001 From: Christian Arlt Date: Mon, 6 Sep 2021 19:40:14 +0200 Subject: Added Hori Fighting Commander 4 VID PID --- examples/host/hid_controller/src/hid_app.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/examples/host/hid_controller/src/hid_app.c b/examples/host/hid_controller/src/hid_app.c index ce084dc85..c9bd6a722 100644 --- a/examples/host/hid_controller/src/hid_app.c +++ b/examples/host/hid_controller/src/hid_app.c @@ -111,7 +111,9 @@ static inline bool is_sony_ds4(uint8_t dev_addr) uint16_t vid, pid; tuh_vid_pid_get(dev_addr, &vid, &pid); - return ( (vid == 0x054c && (pid == 0x09cc || pid == 0x05c4)) ); // Sony DualShock4 + return ( (vid == 0x054c && (pid == 0x09cc || pid == 0x05c4)) // Sony DualShock4 + || (vid == 0x0f0d && pid == 0x005e) // Hori FC4 + ); } //--------------------------------------------------------------------+ -- cgit v1.3.1 From cc08bb6f994f9d5d004d786835809cc1d998205d Mon Sep 17 00:00:00 2001 From: Christian Arlt Date: Mon, 6 Sep 2021 19:41:09 +0200 Subject: Added Arc System Works GG Xrd Limited Edition controller VID PID --- examples/host/hid_controller/src/hid_app.c | 1 + 1 file changed, 1 insertion(+) diff --git a/examples/host/hid_controller/src/hid_app.c b/examples/host/hid_controller/src/hid_app.c index c9bd6a722..d88c74ac4 100644 --- a/examples/host/hid_controller/src/hid_app.c +++ b/examples/host/hid_controller/src/hid_app.c @@ -113,6 +113,7 @@ static inline bool is_sony_ds4(uint8_t dev_addr) return ( (vid == 0x054c && (pid == 0x09cc || pid == 0x05c4)) // Sony DualShock4 || (vid == 0x0f0d && pid == 0x005e) // Hori FC4 + || (vid == 0x1f4f && pid == 0x1002) // ASW GG xrd controller ); } -- cgit v1.3.1 From f47e5402fa928c5a0cd581c894e9e18c3dfcbdfb Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 7 Sep 2021 13:30:51 +0700 Subject: add msc workaround for cxd56 --- examples/make.mk | 1 + hw/bsp/spresense/board.mk | 3 ++- src/class/msc/msc_device.c | 11 +++++++++++ 3 files changed, 14 insertions(+), 1 deletion(-) diff --git a/examples/make.mk b/examples/make.mk index 9daf60e35..24f8c5572 100644 --- a/examples/make.mk +++ b/examples/make.mk @@ -61,6 +61,7 @@ GDB = $(CROSS_COMPILE)gdb OBJCOPY = $(CROSS_COMPILE)objcopy SIZE = $(CROSS_COMPILE)size MKDIR = mkdir +PYTHON = python ifeq ($(CMDEXE),1) CP = copy diff --git a/hw/bsp/spresense/board.mk b/hw/bsp/spresense/board.mk index a46c42bd6..ba291e817 100644 --- a/hw/bsp/spresense/board.mk +++ b/hw/bsp/spresense/board.mk @@ -70,4 +70,5 @@ $(BUILD)/$(PROJECT).spk: $(MKSPK) # flash flash: $(BUILD)/$(PROJECT).spk - @$(TOP)/hw/mcu/sony/cxd56/tools/flash_writer.py -s -c $(SERIAL) -d -b 115200 -n $< + @echo FLASH $< + @$(PYTHON) $(TOP)/hw/mcu/sony/cxd56/tools/flash_writer.py -s -c $(SERIAL) -d -b 115200 -n $< diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c index 6b3a392a8..0fd592129 100644 --- a/src/class/msc/msc_device.c +++ b/src/class/msc/msc_device.c @@ -611,6 +611,17 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t TU_ASSERT( send_csw(rhport, p_msc) ); } } + + #if TU_CHECK_MCU(CXD56) + // WORKAROUND: cxd56 has its own nuttx usb stack which does not forward Set/ClearFeature(Endpoint) to DCD. + // There is no way for us to know when EP is un-stall, therefore we will unconditionally un-stall here and + // hope everything will work + if ( usbd_edpt_stalled(rhport, p_msc->ep_in) ) + { + usbd_edpt_clear_stall(rhport, p_msc->ep_in); + send_csw(rhport, p_msc); + } + #endif } return true; -- cgit v1.3.1 From f735ee4f3618d14511416310f12bd087d8c1f59c Mon Sep 17 00:00:00 2001 From: MasterPhi Date: Tue, 7 Sep 2021 11:25:35 +0200 Subject: Remove ipcf of examples. --- .../iar_audio_4_channel_mic.ipcf | 154 -------------------- examples/device/audio_test/iar_audio_test.ipcf | 154 -------------------- examples/device/board_test/iar_board_test.ipcf | 153 -------------------- .../device/cdc_dual_ports/iar_cdc_dual_ports.ipcf | 154 -------------------- examples/device/cdc_msc/iar_cdc_msc.ipcf | 155 -------------------- .../cdc_msc_freertos/iar_cdc_msc_freertos.ipcf | 157 --------------------- examples/device/dfu/iar_dfu.ipcf | 154 -------------------- examples/device/dfu_runtime/iar_dfu_runtime.ipcf | 154 -------------------- .../iar_dynamic_configuration.ipcf | 155 -------------------- .../hid_boot_interface/iar_hid_boot_interface.ipcf | 155 -------------------- .../device/hid_composite/iar_hid_composite.ipcf | 155 -------------------- .../iar_hid_composite_freertos.ipcf | 157 --------------------- .../hid_generic_inout/iar_hid_generic_inout.ipcf | 154 -------------------- .../iar_hid_multiple_interface.ipcf | 154 -------------------- examples/device/midi_test/iar_midi_test.ipcf | 154 -------------------- examples/device/msc_dual_lun/iar_msc_dual_lun.ipcf | 155 -------------------- .../net_lwip_webserver/iar_net_lwip_webserver.ipcf | 155 -------------------- examples/device/uac2_headset/iar_uac2_headset.ipcf | 155 -------------------- examples/device/usbtmc/iar_usbtmc.ipcf | 157 --------------------- .../device/webusb_serial/iar_webusb_serial.ipcf | 155 -------------------- examples/host/cdc_msc_hid/iar_cdc_msc_hid.ipcf | 155 -------------------- .../host/hid_controller/iar_hid_controller.ipcf | 154 -------------------- 22 files changed, 3405 deletions(-) delete mode 100644 examples/device/audio_4_channel_mic/iar_audio_4_channel_mic.ipcf delete mode 100644 examples/device/audio_test/iar_audio_test.ipcf delete mode 100644 examples/device/board_test/iar_board_test.ipcf delete mode 100644 examples/device/cdc_dual_ports/iar_cdc_dual_ports.ipcf delete mode 100644 examples/device/cdc_msc/iar_cdc_msc.ipcf delete mode 100644 examples/device/cdc_msc_freertos/iar_cdc_msc_freertos.ipcf delete mode 100644 examples/device/dfu/iar_dfu.ipcf delete mode 100644 examples/device/dfu_runtime/iar_dfu_runtime.ipcf delete mode 100644 examples/device/dynamic_configuration/iar_dynamic_configuration.ipcf delete mode 100644 examples/device/hid_boot_interface/iar_hid_boot_interface.ipcf delete mode 100644 examples/device/hid_composite/iar_hid_composite.ipcf delete mode 100644 examples/device/hid_composite_freertos/iar_hid_composite_freertos.ipcf delete mode 100644 examples/device/hid_generic_inout/iar_hid_generic_inout.ipcf delete mode 100644 examples/device/hid_multiple_interface/iar_hid_multiple_interface.ipcf delete mode 100644 examples/device/midi_test/iar_midi_test.ipcf delete mode 100644 examples/device/msc_dual_lun/iar_msc_dual_lun.ipcf delete mode 100644 examples/device/net_lwip_webserver/iar_net_lwip_webserver.ipcf delete mode 100644 examples/device/uac2_headset/iar_uac2_headset.ipcf delete mode 100644 examples/device/usbtmc/iar_usbtmc.ipcf delete mode 100644 examples/device/webusb_serial/iar_webusb_serial.ipcf delete mode 100644 examples/host/cdc_msc_hid/iar_cdc_msc_hid.ipcf delete mode 100644 examples/host/hid_controller/iar_hid_controller.ipcf diff --git a/examples/device/audio_4_channel_mic/iar_audio_4_channel_mic.ipcf b/examples/device/audio_4_channel_mic/iar_audio_4_channel_mic.ipcf deleted file mode 100644 index a862b871f..000000000 --- a/examples/device/audio_4_channel_mic/iar_audio_4_channel_mic.ipcf +++ /dev/null @@ -1,154 +0,0 @@ - - - - $TUSB_DIR$/src - $TUSB_DIR$/lib/SEGGER_RTT/RTT - $PROJ_DIR$ - $TUSB_DIR$/hw - - - - $TUSB_DIR$/src/device/usbd.c - $TUSB_DIR$/src/device/usbd_control.c - - - $TUSB_DIR$/src/common/tusb_fifo.c - - - $TUSB_DIR$/src/class/audio/audio_device.c - - - $TUSB_DIR$/src/class/bth/bth_device.c - - - $TUSB_DIR$/src/class/cdc/cdc_device.c - $TUSB_DIR$/src/class/cdc/cdc_host.c - $TUSB_DIR$/src/class/cdc/cdc_rndis_host.c - - - $TUSB_DIR$/src/class/dfu/dfu_device.c - $TUSB_DIR$/src/class/dfu/dfu_rt_device.c - - - $TUSB_DIR$/src/class/hid/hid_device.c - $TUSB_DIR$/src/class/hid/hid_host.c - - - $TUSB_DIR$/src/class/midi/midi_device.c - - - $TUSB_DIR$/src/class/msc/msc_device.c - $TUSB_DIR$/src/class/msc/msc_host.c - - - $TUSB_DIR$/src/class/net/net_device.c - - - $TUSB_DIR$/src/class/usbtmc/usbtmc_device.c - - - $TUSB_DIR$/src/class/vendor/vendor_device.c - $TUSB_DIR$/src/class/vendor/vendor_host.c - - - $TUSB_DIR$/src/tusb.c - - - $TUSB_DIR$/src/host/hub.c - $TUSB_DIR$/src/host/usbh.c - $TUSB_DIR$/src/host/usbh_control.c - - - $TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c - - - $TUSB_DIR$/src/portable/ehci/ehci.c - - - $TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c - - - $TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c - - - $TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c - - - $TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c - - - $TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c - - - $TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c - - - $TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c - - - $TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c - - - $TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c - - - $TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c - - - 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$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c - $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c - $TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c - - - $TUSB_DIR$/hw/bsp/board.c - - - $TUSB_DIR$/examples/device/audio_4_channel_mic/src/main.c - $TUSB_DIR$/examples/device/audio_4_channel_mic/src/tusb_config.h - $TUSB_DIR$/examples/device/audio_4_channel_mic/src/usb_descriptors.c - - - \ No newline at end of file diff --git a/examples/device/audio_test/iar_audio_test.ipcf b/examples/device/audio_test/iar_audio_test.ipcf deleted file mode 100644 index a5fdd5350..000000000 --- a/examples/device/audio_test/iar_audio_test.ipcf +++ /dev/null @@ -1,154 +0,0 @@ - - - - $TUSB_DIR$/src - $TUSB_DIR$/lib/SEGGER_RTT/RTT - $PROJ_DIR$ - $TUSB_DIR$/hw - - - - $TUSB_DIR$/src/device/usbd.c - $TUSB_DIR$/src/device/usbd_control.c - - - $TUSB_DIR$/src/common/tusb_fifo.c - - - $TUSB_DIR$/src/class/audio/audio_device.c - - - $TUSB_DIR$/src/class/bth/bth_device.c - - - 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$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c - - - $TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c - - - $TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c - - - $TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c - - - $TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c - - - $TUSB_DIR$/src/portable/template/dcd_template.c - - - $TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c - - - $TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c - - - $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c - $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c - $TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c - - - $TUSB_DIR$/hw/bsp/board.c - - - $TUSB_DIR$/examples/device/audio_test/src/main.c - $TUSB_DIR$/examples/device/audio_test/src/tusb_config.h - $TUSB_DIR$/examples/device/audio_test/src/usb_descriptors.c - - - \ No newline at end of file diff --git a/examples/device/board_test/iar_board_test.ipcf b/examples/device/board_test/iar_board_test.ipcf deleted file mode 100644 index 942911640..000000000 --- a/examples/device/board_test/iar_board_test.ipcf +++ /dev/null @@ -1,153 +0,0 @@ - - - - $TUSB_DIR$/src - $TUSB_DIR$/lib/SEGGER_RTT/RTT - $PROJ_DIR$ - $TUSB_DIR$/hw - - - - $TUSB_DIR$/src/device/usbd.c - $TUSB_DIR$/src/device/usbd_control.c - - - $TUSB_DIR$/src/common/tusb_fifo.c - - - $TUSB_DIR$/src/class/audio/audio_device.c - - - $TUSB_DIR$/src/class/bth/bth_device.c - - - $TUSB_DIR$/src/class/cdc/cdc_device.c - $TUSB_DIR$/src/class/cdc/cdc_host.c - $TUSB_DIR$/src/class/cdc/cdc_rndis_host.c - - - $TUSB_DIR$/src/class/dfu/dfu_device.c - $TUSB_DIR$/src/class/dfu/dfu_rt_device.c - - - $TUSB_DIR$/src/class/hid/hid_device.c - $TUSB_DIR$/src/class/hid/hid_host.c - - - $TUSB_DIR$/src/class/midi/midi_device.c - - - $TUSB_DIR$/src/class/msc/msc_device.c - $TUSB_DIR$/src/class/msc/msc_host.c - - - $TUSB_DIR$/src/class/net/net_device.c - - - $TUSB_DIR$/src/class/usbtmc/usbtmc_device.c - - - $TUSB_DIR$/src/class/vendor/vendor_device.c - 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$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c - - - $TUSB_DIR$/hw/bsp/board.c - - - $TUSB_DIR$/examples/device/board_test/src/main.c - $TUSB_DIR$/examples/device/board_test/src/tusb_config.h - - - \ No newline at end of file diff --git a/examples/device/cdc_dual_ports/iar_cdc_dual_ports.ipcf b/examples/device/cdc_dual_ports/iar_cdc_dual_ports.ipcf deleted file mode 100644 index 69e321150..000000000 --- a/examples/device/cdc_dual_ports/iar_cdc_dual_ports.ipcf +++ /dev/null @@ -1,154 +0,0 @@ - - - - $TUSB_DIR$/src - $TUSB_DIR$/lib/SEGGER_RTT/RTT - $PROJ_DIR$ - $TUSB_DIR$/hw - - - - $TUSB_DIR$/src/device/usbd.c - $TUSB_DIR$/src/device/usbd_control.c - - - $TUSB_DIR$/src/common/tusb_fifo.c - - - $TUSB_DIR$/src/class/audio/audio_device.c - - - $TUSB_DIR$/src/class/bth/bth_device.c - - - $TUSB_DIR$/src/class/cdc/cdc_device.c - $TUSB_DIR$/src/class/cdc/cdc_host.c - $TUSB_DIR$/src/class/cdc/cdc_rndis_host.c - - - $TUSB_DIR$/src/class/dfu/dfu_device.c - $TUSB_DIR$/src/class/dfu/dfu_rt_device.c - - - $TUSB_DIR$/src/class/hid/hid_device.c - $TUSB_DIR$/src/class/hid/hid_host.c - - - $TUSB_DIR$/src/class/midi/midi_device.c - - - $TUSB_DIR$/src/class/msc/msc_device.c - $TUSB_DIR$/src/class/msc/msc_host.c - - - $TUSB_DIR$/src/class/net/net_device.c - - - $TUSB_DIR$/src/class/usbtmc/usbtmc_device.c - - - $TUSB_DIR$/src/class/vendor/vendor_device.c - $TUSB_DIR$/src/class/vendor/vendor_host.c - - - $TUSB_DIR$/src/tusb.c - - - $TUSB_DIR$/src/host/hub.c - $TUSB_DIR$/src/host/usbh.c - $TUSB_DIR$/src/host/usbh_control.c - - - $TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c - - - $TUSB_DIR$/src/portable/ehci/ehci.c - - - $TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c - - - $TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c - - - $TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c - - - $TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c - - - $TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c - - - $TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c - - - $TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c - - - $TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c - - - $TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c - - - $TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c - - - $TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c - $TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c - - - $TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c - - - $TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c - $TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c - - - $TUSB_DIR$/src/portable/ohci/ohci.c - - - $TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c - $TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c - $TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c - - - $TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c - - - $TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c - - - $TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c - - - $TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c - - - $TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c - - - $TUSB_DIR$/src/portable/template/dcd_template.c - - - $TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c - - - $TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c - - - $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c - $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c - $TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c - - - $TUSB_DIR$/hw/bsp/board.c - - - $TUSB_DIR$/examples/device/cdc_dual_ports/src/main.c - $TUSB_DIR$/examples/device/cdc_dual_ports/src/tusb_config.h - $TUSB_DIR$/examples/device/cdc_dual_ports/src/usb_descriptors.c - - - \ No newline at end of file diff --git a/examples/device/cdc_msc/iar_cdc_msc.ipcf b/examples/device/cdc_msc/iar_cdc_msc.ipcf deleted file mode 100644 index 7b7576e8c..000000000 --- a/examples/device/cdc_msc/iar_cdc_msc.ipcf +++ /dev/null @@ -1,155 +0,0 @@ - - - - $TUSB_DIR$/src - $TUSB_DIR$/lib/SEGGER_RTT/RTT - $PROJ_DIR$ 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$TUSB_DIR$/src/portable/template/dcd_template.c - - - $TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c - - - $TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c - - - $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c - $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c - $TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c - - - $TUSB_DIR$/hw/bsp/board.c - - - $TUSB_DIR$/examples/device/cdc_msc_freertos/src/FreeRTOSConfig.h - $TUSB_DIR$/examples/device/cdc_msc_freertos/src/freertos_hook.c - $TUSB_DIR$/examples/device/cdc_msc_freertos/src/main.c - $TUSB_DIR$/examples/device/cdc_msc_freertos/src/msc_disk.c - $TUSB_DIR$/examples/device/cdc_msc_freertos/src/tusb_config.h - $TUSB_DIR$/examples/device/cdc_msc_freertos/src/usb_descriptors.c - - - \ No newline at end of file diff --git a/examples/device/dfu/iar_dfu.ipcf b/examples/device/dfu/iar_dfu.ipcf deleted file mode 100644 index d2eb2f043..000000000 --- a/examples/device/dfu/iar_dfu.ipcf +++ /dev/null @@ -1,154 +0,0 @@ - - - - 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$TUSB_DIR$/examples/device/dfu/src/tusb_config.h - $TUSB_DIR$/examples/device/dfu/src/usb_descriptors.c - - - \ No newline at end of file diff --git a/examples/device/dfu_runtime/iar_dfu_runtime.ipcf b/examples/device/dfu_runtime/iar_dfu_runtime.ipcf deleted file mode 100644 index 18ade4125..000000000 --- a/examples/device/dfu_runtime/iar_dfu_runtime.ipcf +++ /dev/null @@ -1,154 +0,0 @@ - - - - $TUSB_DIR$/src - $TUSB_DIR$/lib/SEGGER_RTT/RTT - $PROJ_DIR$ - $TUSB_DIR$/hw - - - - $TUSB_DIR$/src/device/usbd.c - $TUSB_DIR$/src/device/usbd_control.c - - - $TUSB_DIR$/src/common/tusb_fifo.c - - - $TUSB_DIR$/src/class/audio/audio_device.c - - - $TUSB_DIR$/src/class/bth/bth_device.c - - - $TUSB_DIR$/src/class/cdc/cdc_device.c - $TUSB_DIR$/src/class/cdc/cdc_host.c - $TUSB_DIR$/src/class/cdc/cdc_rndis_host.c - - - $TUSB_DIR$/src/class/dfu/dfu_device.c - $TUSB_DIR$/src/class/dfu/dfu_rt_device.c - - - $TUSB_DIR$/src/class/hid/hid_device.c - $TUSB_DIR$/src/class/hid/hid_host.c - - - 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$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c - - - $TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c - - - $TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c - - - $TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c - $TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c - - - $TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c - - - $TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c - $TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c - - - $TUSB_DIR$/src/portable/ohci/ohci.c - - - $TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c - $TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c - $TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c - - - $TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c - - - $TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c - - - $TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c - - - $TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c - - - $TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c - - - $TUSB_DIR$/src/portable/template/dcd_template.c - - - $TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c - - - $TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c - - - $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c - $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c - $TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c - - - $TUSB_DIR$/hw/bsp/board.c - - - $TUSB_DIR$/examples/device/dfu_runtime/src/main.c - $TUSB_DIR$/examples/device/dfu_runtime/src/tusb_config.h - $TUSB_DIR$/examples/device/dfu_runtime/src/usb_descriptors.c - - - \ No newline at end of file diff --git a/examples/device/dynamic_configuration/iar_dynamic_configuration.ipcf b/examples/device/dynamic_configuration/iar_dynamic_configuration.ipcf deleted file mode 100644 index 1185e774c..000000000 --- a/examples/device/dynamic_configuration/iar_dynamic_configuration.ipcf +++ /dev/null @@ -1,155 +0,0 @@ - - - - $TUSB_DIR$/src - $TUSB_DIR$/lib/SEGGER_RTT/RTT - $PROJ_DIR$ - $TUSB_DIR$/hw - - - - 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$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c - - - $TUSB_DIR$/src/portable/template/dcd_template.c - - - $TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c - - - $TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c - - - $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c - $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c - $TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c - - - $TUSB_DIR$/hw/bsp/board.c - - - $TUSB_DIR$/examples/device/hid_boot_interface/src/main.c - $TUSB_DIR$/examples/device/hid_boot_interface/src/tusb_config.h - $TUSB_DIR$/examples/device/hid_boot_interface/src/usb_descriptors.c - $TUSB_DIR$/examples/device/hid_boot_interface/src/usb_descriptors.h - - - \ No newline at end of file diff --git a/examples/device/hid_composite/iar_hid_composite.ipcf b/examples/device/hid_composite/iar_hid_composite.ipcf deleted file mode 100644 index a2c5c9855..000000000 --- a/examples/device/hid_composite/iar_hid_composite.ipcf +++ /dev/null @@ -1,155 +0,0 @@ - - - - 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$TUSB_DIR$/examples/device/hid_composite/src/tusb_config.h - $TUSB_DIR$/examples/device/hid_composite/src/usb_descriptors.c - $TUSB_DIR$/examples/device/hid_composite/src/usb_descriptors.h - - - \ No newline at end of file diff --git a/examples/device/hid_composite_freertos/iar_hid_composite_freertos.ipcf b/examples/device/hid_composite_freertos/iar_hid_composite_freertos.ipcf deleted file mode 100644 index eabff34f5..000000000 --- a/examples/device/hid_composite_freertos/iar_hid_composite_freertos.ipcf +++ /dev/null @@ -1,157 +0,0 @@ - - - - $TUSB_DIR$/src - $TUSB_DIR$/lib/SEGGER_RTT/RTT - $PROJ_DIR$ - $TUSB_DIR$/hw - - - - $TUSB_DIR$/src/device/usbd.c - $TUSB_DIR$/src/device/usbd_control.c - - - $TUSB_DIR$/src/common/tusb_fifo.c - - - $TUSB_DIR$/src/class/audio/audio_device.c - - - $TUSB_DIR$/src/class/bth/bth_device.c - - - $TUSB_DIR$/src/class/cdc/cdc_device.c - $TUSB_DIR$/src/class/cdc/cdc_host.c - $TUSB_DIR$/src/class/cdc/cdc_rndis_host.c - - - $TUSB_DIR$/src/class/dfu/dfu_device.c - $TUSB_DIR$/src/class/dfu/dfu_rt_device.c - - - $TUSB_DIR$/src/class/hid/hid_device.c - $TUSB_DIR$/src/class/hid/hid_host.c - - - $TUSB_DIR$/src/class/midi/midi_device.c - - - $TUSB_DIR$/src/class/msc/msc_device.c - $TUSB_DIR$/src/class/msc/msc_host.c - - - $TUSB_DIR$/src/class/net/net_device.c - - - $TUSB_DIR$/src/class/usbtmc/usbtmc_device.c - - - $TUSB_DIR$/src/class/vendor/vendor_device.c - $TUSB_DIR$/src/class/vendor/vendor_host.c - - - $TUSB_DIR$/src/tusb.c - - - $TUSB_DIR$/src/host/hub.c - $TUSB_DIR$/src/host/usbh.c - $TUSB_DIR$/src/host/usbh_control.c - - - $TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c - - - $TUSB_DIR$/src/portable/ehci/ehci.c - - - $TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c - - - $TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c - - - $TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c - - - $TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c - - - $TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c - - - $TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c - - - $TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c - - - $TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c - - - $TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c - - - $TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c - - - $TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c - $TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c - - - $TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c - - - $TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c - $TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c - - - $TUSB_DIR$/src/portable/ohci/ohci.c - - - $TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c - $TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c - $TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c - - - $TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c - - - $TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c - - - $TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c - - - $TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c - - - $TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c - - - $TUSB_DIR$/src/portable/template/dcd_template.c - - - $TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c - - - $TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c - - - $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c - $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c - $TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c - - - $TUSB_DIR$/hw/bsp/board.c - - - $TUSB_DIR$/examples/device/hid_composite_freertos/src/FreeRTOSConfig.h - $TUSB_DIR$/examples/device/hid_composite_freertos/src/freertos_hook.c - $TUSB_DIR$/examples/device/hid_composite_freertos/src/main.c - $TUSB_DIR$/examples/device/hid_composite_freertos/src/tusb_config.h - $TUSB_DIR$/examples/device/hid_composite_freertos/src/usb_descriptors.c - $TUSB_DIR$/examples/device/hid_composite_freertos/src/usb_descriptors.h - - - \ No newline at end of file diff --git a/examples/device/hid_generic_inout/iar_hid_generic_inout.ipcf b/examples/device/hid_generic_inout/iar_hid_generic_inout.ipcf deleted file mode 100644 index d917fa956..000000000 --- a/examples/device/hid_generic_inout/iar_hid_generic_inout.ipcf +++ /dev/null @@ -1,154 +0,0 @@ - - - - $TUSB_DIR$/src - $TUSB_DIR$/lib/SEGGER_RTT/RTT - $PROJ_DIR$ - $TUSB_DIR$/hw - - - - $TUSB_DIR$/src/device/usbd.c - $TUSB_DIR$/src/device/usbd_control.c - - - $TUSB_DIR$/src/common/tusb_fifo.c - - - $TUSB_DIR$/src/class/audio/audio_device.c - - - $TUSB_DIR$/src/class/bth/bth_device.c - - - $TUSB_DIR$/src/class/cdc/cdc_device.c - $TUSB_DIR$/src/class/cdc/cdc_host.c - $TUSB_DIR$/src/class/cdc/cdc_rndis_host.c - - - $TUSB_DIR$/src/class/dfu/dfu_device.c - $TUSB_DIR$/src/class/dfu/dfu_rt_device.c - - - $TUSB_DIR$/src/class/hid/hid_device.c - $TUSB_DIR$/src/class/hid/hid_host.c - - - $TUSB_DIR$/src/class/midi/midi_device.c - - - $TUSB_DIR$/src/class/msc/msc_device.c - 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$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c - - - $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c - $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c - $TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c - - - $TUSB_DIR$/hw/bsp/board.c - - - $TUSB_DIR$/examples/device/hid_generic_inout/src/main.c - $TUSB_DIR$/examples/device/hid_generic_inout/src/tusb_config.h - $TUSB_DIR$/examples/device/hid_generic_inout/src/usb_descriptors.c - - - \ No newline at end of file diff --git a/examples/device/hid_multiple_interface/iar_hid_multiple_interface.ipcf b/examples/device/hid_multiple_interface/iar_hid_multiple_interface.ipcf deleted file mode 100644 index f50f39616..000000000 --- a/examples/device/hid_multiple_interface/iar_hid_multiple_interface.ipcf +++ /dev/null @@ -1,154 +0,0 @@ - - - - $TUSB_DIR$/src - $TUSB_DIR$/lib/SEGGER_RTT/RTT - $PROJ_DIR$ - $TUSB_DIR$/hw - - - - $TUSB_DIR$/src/device/usbd.c - $TUSB_DIR$/src/device/usbd_control.c - - - $TUSB_DIR$/src/common/tusb_fifo.c - - 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$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c - - - $TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c - - - $TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c - - - $TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c - - - $TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c - - - $TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c - - - $TUSB_DIR$/src/portable/template/dcd_template.c - - - $TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c - - - $TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c - - - $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c - $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c - $TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c - - - $TUSB_DIR$/hw/bsp/board.c - - - $TUSB_DIR$/examples/device/hid_multiple_interface/src/main.c - $TUSB_DIR$/examples/device/hid_multiple_interface/src/tusb_config.h - $TUSB_DIR$/examples/device/hid_multiple_interface/src/usb_descriptors.c - - - \ No newline at end of file diff --git a/examples/device/midi_test/iar_midi_test.ipcf b/examples/device/midi_test/iar_midi_test.ipcf deleted file mode 100644 index f8ab96a1f..000000000 --- a/examples/device/midi_test/iar_midi_test.ipcf +++ /dev/null @@ -1,154 +0,0 @@ - - - - $TUSB_DIR$/src - $TUSB_DIR$/lib/SEGGER_RTT/RTT - $PROJ_DIR$ - $TUSB_DIR$/hw - - - - $TUSB_DIR$/src/device/usbd.c - $TUSB_DIR$/src/device/usbd_control.c - - - $TUSB_DIR$/src/common/tusb_fifo.c - - - $TUSB_DIR$/src/class/audio/audio_device.c - - - $TUSB_DIR$/src/class/bth/bth_device.c - - - $TUSB_DIR$/src/class/cdc/cdc_device.c - $TUSB_DIR$/src/class/cdc/cdc_host.c - $TUSB_DIR$/src/class/cdc/cdc_rndis_host.c - - - $TUSB_DIR$/src/class/dfu/dfu_device.c - $TUSB_DIR$/src/class/dfu/dfu_rt_device.c - - - $TUSB_DIR$/src/class/hid/hid_device.c - $TUSB_DIR$/src/class/hid/hid_host.c - - - $TUSB_DIR$/src/class/midi/midi_device.c - - - $TUSB_DIR$/src/class/msc/msc_device.c - $TUSB_DIR$/src/class/msc/msc_host.c - - - $TUSB_DIR$/src/class/net/net_device.c - - - $TUSB_DIR$/src/class/usbtmc/usbtmc_device.c - - - $TUSB_DIR$/src/class/vendor/vendor_device.c - $TUSB_DIR$/src/class/vendor/vendor_host.c - - - $TUSB_DIR$/src/tusb.c - - - $TUSB_DIR$/src/host/hub.c - $TUSB_DIR$/src/host/usbh.c - $TUSB_DIR$/src/host/usbh_control.c - - - $TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c - - - $TUSB_DIR$/src/portable/ehci/ehci.c - - - $TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c - - - $TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c - - - $TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c - - - $TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c - - - $TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c - - - $TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c - - - $TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c - - - $TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c - - - $TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c - - - $TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c - - - $TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c - $TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c - - - $TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c - - - $TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c - $TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c - - - $TUSB_DIR$/src/portable/ohci/ohci.c - - - $TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c - $TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c - $TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c - - - $TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c - - - $TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c - - - $TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c - - - $TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c - - - $TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c - - - $TUSB_DIR$/src/portable/template/dcd_template.c - - - $TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c - - - $TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c - - - $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c - $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c - $TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c - - - $TUSB_DIR$/hw/bsp/board.c - - - $TUSB_DIR$/examples/device/midi_test/src/main.c - $TUSB_DIR$/examples/device/midi_test/src/tusb_config.h - $TUSB_DIR$/examples/device/midi_test/src/usb_descriptors.c - - - \ No newline at end of file diff --git a/examples/device/msc_dual_lun/iar_msc_dual_lun.ipcf b/examples/device/msc_dual_lun/iar_msc_dual_lun.ipcf deleted file mode 100644 index 257230891..000000000 --- a/examples/device/msc_dual_lun/iar_msc_dual_lun.ipcf +++ /dev/null @@ -1,155 +0,0 @@ - - - - $TUSB_DIR$/src - $TUSB_DIR$/lib/SEGGER_RTT/RTT - $PROJ_DIR$ - $TUSB_DIR$/hw - - - - $TUSB_DIR$/src/device/usbd.c - $TUSB_DIR$/src/device/usbd_control.c - - - $TUSB_DIR$/src/common/tusb_fifo.c - - - $TUSB_DIR$/src/class/audio/audio_device.c - - - $TUSB_DIR$/src/class/bth/bth_device.c - - - $TUSB_DIR$/src/class/cdc/cdc_device.c - $TUSB_DIR$/src/class/cdc/cdc_host.c - $TUSB_DIR$/src/class/cdc/cdc_rndis_host.c - - - $TUSB_DIR$/src/class/dfu/dfu_device.c - $TUSB_DIR$/src/class/dfu/dfu_rt_device.c - - - $TUSB_DIR$/src/class/hid/hid_device.c - $TUSB_DIR$/src/class/hid/hid_host.c - - - $TUSB_DIR$/src/class/midi/midi_device.c - - - $TUSB_DIR$/src/class/msc/msc_device.c - $TUSB_DIR$/src/class/msc/msc_host.c - - - $TUSB_DIR$/src/class/net/net_device.c - - - $TUSB_DIR$/src/class/usbtmc/usbtmc_device.c - - - $TUSB_DIR$/src/class/vendor/vendor_device.c - $TUSB_DIR$/src/class/vendor/vendor_host.c - - - $TUSB_DIR$/src/tusb.c - - - $TUSB_DIR$/src/host/hub.c - $TUSB_DIR$/src/host/usbh.c - $TUSB_DIR$/src/host/usbh_control.c - - - $TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c - - - $TUSB_DIR$/src/portable/ehci/ehci.c - - - $TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c - - - $TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c - - - $TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c - - - $TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c - - - $TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c - - - $TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c - - - $TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c - - - $TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c - - - $TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c - - - $TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c - - - $TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c - $TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c - - - $TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c - - - $TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c - $TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c - - - $TUSB_DIR$/src/portable/ohci/ohci.c - - - $TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c - $TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c - $TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c - - - $TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c - - - $TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c - - - $TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c - - - $TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c - - - $TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c - - - $TUSB_DIR$/src/portable/template/dcd_template.c - - - $TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c - - - $TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c - - - $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c - $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c - $TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c - - - $TUSB_DIR$/hw/bsp/board.c - - - $TUSB_DIR$/examples/device/msc_dual_lun/src/main.c - $TUSB_DIR$/examples/device/msc_dual_lun/src/msc_disk_dual.c - $TUSB_DIR$/examples/device/msc_dual_lun/src/tusb_config.h - $TUSB_DIR$/examples/device/msc_dual_lun/src/usb_descriptors.c - - - \ No newline at end of file diff --git a/examples/device/net_lwip_webserver/iar_net_lwip_webserver.ipcf b/examples/device/net_lwip_webserver/iar_net_lwip_webserver.ipcf deleted file mode 100644 index 1fb5b1eac..000000000 --- a/examples/device/net_lwip_webserver/iar_net_lwip_webserver.ipcf +++ /dev/null @@ -1,155 +0,0 @@ - - - - $TUSB_DIR$/src - $TUSB_DIR$/lib/SEGGER_RTT/RTT - $PROJ_DIR$ - $TUSB_DIR$/hw - - - - $TUSB_DIR$/src/device/usbd.c - $TUSB_DIR$/src/device/usbd_control.c - - - $TUSB_DIR$/src/common/tusb_fifo.c - - - $TUSB_DIR$/src/class/audio/audio_device.c - - - $TUSB_DIR$/src/class/bth/bth_device.c - - - $TUSB_DIR$/src/class/cdc/cdc_device.c - $TUSB_DIR$/src/class/cdc/cdc_host.c - $TUSB_DIR$/src/class/cdc/cdc_rndis_host.c - - - $TUSB_DIR$/src/class/dfu/dfu_device.c - $TUSB_DIR$/src/class/dfu/dfu_rt_device.c - - - $TUSB_DIR$/src/class/hid/hid_device.c - $TUSB_DIR$/src/class/hid/hid_host.c - - - $TUSB_DIR$/src/class/midi/midi_device.c - - - $TUSB_DIR$/src/class/msc/msc_device.c - $TUSB_DIR$/src/class/msc/msc_host.c - - - $TUSB_DIR$/src/class/net/net_device.c - - - $TUSB_DIR$/src/class/usbtmc/usbtmc_device.c - - - $TUSB_DIR$/src/class/vendor/vendor_device.c - $TUSB_DIR$/src/class/vendor/vendor_host.c - - - $TUSB_DIR$/src/tusb.c - - - $TUSB_DIR$/src/host/hub.c - $TUSB_DIR$/src/host/usbh.c - $TUSB_DIR$/src/host/usbh_control.c - - - $TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c - - - $TUSB_DIR$/src/portable/ehci/ehci.c - - - $TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c - - - $TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c - - - $TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c - - - $TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c - - - $TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c - - - $TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c - - - $TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c - - - $TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c - - - $TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c - - - $TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c - - - $TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c - $TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c - - - $TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c - - - $TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c - $TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c - - - $TUSB_DIR$/src/portable/ohci/ohci.c - - - $TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c - $TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c - $TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c - - - $TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c - - - $TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c - - - $TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c - - - $TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c - - - $TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c - - - $TUSB_DIR$/src/portable/template/dcd_template.c - - - $TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c - - - $TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c - - - $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c - $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c - $TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c - - - $TUSB_DIR$/hw/bsp/board.c - - - $TUSB_DIR$/examples/device/net_lwip_webserver/src/lwipopts.h - $TUSB_DIR$/examples/device/net_lwip_webserver/src/main.c - $TUSB_DIR$/examples/device/net_lwip_webserver/src/tusb_config.h - $TUSB_DIR$/examples/device/net_lwip_webserver/src/usb_descriptors.c - - - \ No newline at end of file diff --git a/examples/device/uac2_headset/iar_uac2_headset.ipcf b/examples/device/uac2_headset/iar_uac2_headset.ipcf deleted file mode 100644 index 1d1b9b88c..000000000 --- a/examples/device/uac2_headset/iar_uac2_headset.ipcf +++ /dev/null @@ -1,155 +0,0 @@ - - - - $TUSB_DIR$/src - $TUSB_DIR$/lib/SEGGER_RTT/RTT - $PROJ_DIR$ - $TUSB_DIR$/hw - - - - $TUSB_DIR$/src/device/usbd.c - $TUSB_DIR$/src/device/usbd_control.c - - - $TUSB_DIR$/src/common/tusb_fifo.c - - - $TUSB_DIR$/src/class/audio/audio_device.c - - - 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$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c - - - $TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c - - - $TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c - - - $TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c - - - $TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c - - - $TUSB_DIR$/src/portable/template/dcd_template.c - - - $TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c - - - $TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c - - - $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c - $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c - $TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c - - - $TUSB_DIR$/hw/bsp/board.c - - - $TUSB_DIR$/examples/device/uac2_headset/src/main.c - $TUSB_DIR$/examples/device/uac2_headset/src/tusb_config.h - $TUSB_DIR$/examples/device/uac2_headset/src/usb_descriptors.c - $TUSB_DIR$/examples/device/uac2_headset/src/usb_descriptors.h - - - \ No newline at end of file diff --git a/examples/device/usbtmc/iar_usbtmc.ipcf b/examples/device/usbtmc/iar_usbtmc.ipcf deleted file mode 100644 index 20a6f954a..000000000 --- a/examples/device/usbtmc/iar_usbtmc.ipcf +++ /dev/null @@ -1,157 +0,0 @@ - - - - $TUSB_DIR$/src - $TUSB_DIR$/lib/SEGGER_RTT/RTT - $PROJ_DIR$ - $TUSB_DIR$/hw - - - - $TUSB_DIR$/src/device/usbd.c - $TUSB_DIR$/src/device/usbd_control.c - - - $TUSB_DIR$/src/common/tusb_fifo.c - - - $TUSB_DIR$/src/class/audio/audio_device.c - - - $TUSB_DIR$/src/class/bth/bth_device.c - - - $TUSB_DIR$/src/class/cdc/cdc_device.c - $TUSB_DIR$/src/class/cdc/cdc_host.c - $TUSB_DIR$/src/class/cdc/cdc_rndis_host.c - - - $TUSB_DIR$/src/class/dfu/dfu_device.c - $TUSB_DIR$/src/class/dfu/dfu_rt_device.c - - - $TUSB_DIR$/src/class/hid/hid_device.c - $TUSB_DIR$/src/class/hid/hid_host.c - - - $TUSB_DIR$/src/class/midi/midi_device.c - - - $TUSB_DIR$/src/class/msc/msc_device.c - $TUSB_DIR$/src/class/msc/msc_host.c - - - $TUSB_DIR$/src/class/net/net_device.c - - - $TUSB_DIR$/src/class/usbtmc/usbtmc_device.c - - - $TUSB_DIR$/src/class/vendor/vendor_device.c - $TUSB_DIR$/src/class/vendor/vendor_host.c - - - $TUSB_DIR$/src/tusb.c - - - $TUSB_DIR$/src/host/hub.c - $TUSB_DIR$/src/host/usbh.c - $TUSB_DIR$/src/host/usbh_control.c - - - $TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c - - - $TUSB_DIR$/src/portable/ehci/ehci.c - - - $TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c - - - $TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c - - - $TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c - - - $TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c - - - $TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c - - - $TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c - - - $TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c - - - $TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c - - - $TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c - - - $TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c - - - $TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c - $TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c - - - $TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c - - - $TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c - $TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c - - - $TUSB_DIR$/src/portable/ohci/ohci.c - - - $TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c - $TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c - $TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c - - - $TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c - - - $TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c - - - $TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c - - - $TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c - - - $TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c - - - $TUSB_DIR$/src/portable/template/dcd_template.c - - - $TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c - - - $TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c - - - $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c - $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c - $TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c - - - $TUSB_DIR$/hw/bsp/board.c - - - $TUSB_DIR$/examples/device/usbtmc/src/main.c - $TUSB_DIR$/examples/device/usbtmc/src/main.h - $TUSB_DIR$/examples/device/usbtmc/src/tusb_config.h - $TUSB_DIR$/examples/device/usbtmc/src/usbtmc_app.c - $TUSB_DIR$/examples/device/usbtmc/src/usbtmc_app.h - $TUSB_DIR$/examples/device/usbtmc/src/usb_descriptors.c - - - \ No newline at end of file diff --git a/examples/device/webusb_serial/iar_webusb_serial.ipcf b/examples/device/webusb_serial/iar_webusb_serial.ipcf deleted file mode 100644 index 391b21451..000000000 --- a/examples/device/webusb_serial/iar_webusb_serial.ipcf +++ /dev/null @@ -1,155 +0,0 @@ - - - - $TUSB_DIR$/src - $TUSB_DIR$/lib/SEGGER_RTT/RTT - $PROJ_DIR$ - $TUSB_DIR$/hw - - - - $TUSB_DIR$/src/device/usbd.c - $TUSB_DIR$/src/device/usbd_control.c - - - $TUSB_DIR$/src/common/tusb_fifo.c - - - $TUSB_DIR$/src/class/audio/audio_device.c - - - $TUSB_DIR$/src/class/bth/bth_device.c - - - $TUSB_DIR$/src/class/cdc/cdc_device.c - $TUSB_DIR$/src/class/cdc/cdc_host.c - $TUSB_DIR$/src/class/cdc/cdc_rndis_host.c - - - $TUSB_DIR$/src/class/dfu/dfu_device.c - $TUSB_DIR$/src/class/dfu/dfu_rt_device.c - - - $TUSB_DIR$/src/class/hid/hid_device.c - $TUSB_DIR$/src/class/hid/hid_host.c - - - $TUSB_DIR$/src/class/midi/midi_device.c - - - $TUSB_DIR$/src/class/msc/msc_device.c - $TUSB_DIR$/src/class/msc/msc_host.c - - - $TUSB_DIR$/src/class/net/net_device.c - - - $TUSB_DIR$/src/class/usbtmc/usbtmc_device.c - - - $TUSB_DIR$/src/class/vendor/vendor_device.c - $TUSB_DIR$/src/class/vendor/vendor_host.c - - - $TUSB_DIR$/src/tusb.c - - - $TUSB_DIR$/src/host/hub.c - $TUSB_DIR$/src/host/usbh.c - $TUSB_DIR$/src/host/usbh_control.c - - - $TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c - - - $TUSB_DIR$/src/portable/ehci/ehci.c - - - $TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c - - - $TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c - - - $TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c - - - $TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c - - - $TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c - - - $TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c - - - $TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c - - - $TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c - - - $TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c - - - $TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c - - - $TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c - $TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c - - - $TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c - - - $TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c - $TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c - - - $TUSB_DIR$/src/portable/ohci/ohci.c - - - $TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c - $TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c - $TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c - - - $TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c - - - $TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c - - - $TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c - - - $TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c - - - $TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c - - - $TUSB_DIR$/src/portable/template/dcd_template.c - - - $TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c - - - $TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c - - - $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c - $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c - $TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c - - - $TUSB_DIR$/hw/bsp/board.c - - - $TUSB_DIR$/examples/device/webusb_serial/src/main.c - $TUSB_DIR$/examples/device/webusb_serial/src/tusb_config.h - $TUSB_DIR$/examples/device/webusb_serial/src/usb_descriptors.c - $TUSB_DIR$/examples/device/webusb_serial/src/usb_descriptors.h - - - \ No newline at end of file diff --git a/examples/host/cdc_msc_hid/iar_cdc_msc_hid.ipcf b/examples/host/cdc_msc_hid/iar_cdc_msc_hid.ipcf deleted file mode 100644 index c3d48b369..000000000 --- a/examples/host/cdc_msc_hid/iar_cdc_msc_hid.ipcf +++ /dev/null @@ -1,155 +0,0 @@ - - - - $TUSB_DIR$/src - $TUSB_DIR$/lib/SEGGER_RTT/RTT - $PROJ_DIR$ - $TUSB_DIR$/hw - - - - $TUSB_DIR$/src/device/usbd.c - $TUSB_DIR$/src/device/usbd_control.c - - - $TUSB_DIR$/src/common/tusb_fifo.c - - - $TUSB_DIR$/src/class/audio/audio_device.c - - - $TUSB_DIR$/src/class/bth/bth_device.c - - - $TUSB_DIR$/src/class/cdc/cdc_device.c - $TUSB_DIR$/src/class/cdc/cdc_host.c - $TUSB_DIR$/src/class/cdc/cdc_rndis_host.c - - - $TUSB_DIR$/src/class/dfu/dfu_device.c - $TUSB_DIR$/src/class/dfu/dfu_rt_device.c - - - $TUSB_DIR$/src/class/hid/hid_device.c - $TUSB_DIR$/src/class/hid/hid_host.c - - - $TUSB_DIR$/src/class/midi/midi_device.c - - - $TUSB_DIR$/src/class/msc/msc_device.c - $TUSB_DIR$/src/class/msc/msc_host.c - - - $TUSB_DIR$/src/class/net/net_device.c - - - $TUSB_DIR$/src/class/usbtmc/usbtmc_device.c - - - $TUSB_DIR$/src/class/vendor/vendor_device.c - $TUSB_DIR$/src/class/vendor/vendor_host.c - - - $TUSB_DIR$/src/tusb.c - - - $TUSB_DIR$/src/host/hub.c - $TUSB_DIR$/src/host/usbh.c - $TUSB_DIR$/src/host/usbh_control.c - - - $TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c - - - $TUSB_DIR$/src/portable/ehci/ehci.c - - - $TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c - - - $TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c - - - $TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c - - - $TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c - - - $TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c - - - $TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c - - - $TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c - - - $TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c - - - $TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c - - - $TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c - - - $TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c - $TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c - - - $TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c - - - $TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c - $TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c - - - $TUSB_DIR$/src/portable/ohci/ohci.c - - - $TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c - $TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c - $TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c - - - $TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c - - - $TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c - - - $TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c - - - $TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c - - - $TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c - - - $TUSB_DIR$/src/portable/template/dcd_template.c - - - $TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c - - - $TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c - - - $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c - $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c - $TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c - - - $TUSB_DIR$/hw/bsp/board.c - - - $TUSB_DIR$/examples/host/cdc_msc_hid/src/hid_app.c - $TUSB_DIR$/examples/host/cdc_msc_hid/src/main.c - $TUSB_DIR$/examples/host/cdc_msc_hid/src/msc_app.c - $TUSB_DIR$/examples/host/cdc_msc_hid/src/tusb_config.h - - - \ No newline at end of file diff --git a/examples/host/hid_controller/iar_hid_controller.ipcf b/examples/host/hid_controller/iar_hid_controller.ipcf deleted file mode 100644 index b3ce73a91..000000000 --- a/examples/host/hid_controller/iar_hid_controller.ipcf +++ /dev/null @@ -1,154 +0,0 @@ - - - - $TUSB_DIR$/src - $TUSB_DIR$/lib/SEGGER_RTT/RTT - $PROJ_DIR$ - $TUSB_DIR$/hw - - - - $TUSB_DIR$/src/device/usbd.c - $TUSB_DIR$/src/device/usbd_control.c - - - $TUSB_DIR$/src/common/tusb_fifo.c - - - $TUSB_DIR$/src/class/audio/audio_device.c - - - $TUSB_DIR$/src/class/bth/bth_device.c - - - $TUSB_DIR$/src/class/cdc/cdc_device.c - $TUSB_DIR$/src/class/cdc/cdc_host.c - $TUSB_DIR$/src/class/cdc/cdc_rndis_host.c - - - $TUSB_DIR$/src/class/dfu/dfu_device.c - $TUSB_DIR$/src/class/dfu/dfu_rt_device.c - - - $TUSB_DIR$/src/class/hid/hid_device.c - $TUSB_DIR$/src/class/hid/hid_host.c - - - $TUSB_DIR$/src/class/midi/midi_device.c - - - $TUSB_DIR$/src/class/msc/msc_device.c - $TUSB_DIR$/src/class/msc/msc_host.c - - - $TUSB_DIR$/src/class/net/net_device.c - - - $TUSB_DIR$/src/class/usbtmc/usbtmc_device.c - - - $TUSB_DIR$/src/class/vendor/vendor_device.c - $TUSB_DIR$/src/class/vendor/vendor_host.c - - - $TUSB_DIR$/src/tusb.c - - - $TUSB_DIR$/src/host/hub.c - $TUSB_DIR$/src/host/usbh.c - $TUSB_DIR$/src/host/usbh_control.c - - - $TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c - - - $TUSB_DIR$/src/portable/ehci/ehci.c - - - $TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c - - - $TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c - - - $TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c - - - $TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c - - - $TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c - - - $TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c - - - $TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c - - - $TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c - - - $TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c - - - $TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c - - - $TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c - $TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c - - - $TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c - - - $TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c - $TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c - - - $TUSB_DIR$/src/portable/ohci/ohci.c - - - $TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c - $TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c - $TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c - - - $TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c - - - $TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c - - - $TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c - - - $TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c - - - $TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c - - - $TUSB_DIR$/src/portable/template/dcd_template.c - - - $TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c - - - $TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c - - - $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c - $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c - $TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c - - - $TUSB_DIR$/hw/bsp/board.c - - - $TUSB_DIR$/examples/host/hid_controller/src/hid_app.c - $TUSB_DIR$/examples/host/hid_controller/src/main.c - $TUSB_DIR$/examples/host/hid_controller/src/tusb_config.h - - - \ No newline at end of file -- cgit v1.3.1 From a754205acb391b7605c835657c22c0a6c155c28e Mon Sep 17 00:00:00 2001 From: MasterPhi Date: Tue, 7 Sep 2021 12:32:17 +0200 Subject: Rename iar.ipcf to iar_template.ipcf --- tools/iar.ipcf | 147 ------------------------------------------------ tools/iar_gen.py | 2 +- tools/iar_template.ipcf | 147 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 148 insertions(+), 148 deletions(-) delete mode 100644 tools/iar.ipcf create mode 100644 tools/iar_template.ipcf diff --git a/tools/iar.ipcf b/tools/iar.ipcf deleted file mode 100644 index b8e50a1d2..000000000 --- a/tools/iar.ipcf +++ /dev/null @@ -1,147 +0,0 @@ - - - - - $TUSB_DIR$/src - $TUSB_DIR$/lib/SEGGER_RTT/RTT - $PROJ_DIR$ - - - - $TUSB_DIR$/src/device/usbd.c - $TUSB_DIR$/src/device/usbd_control.c - - - $TUSB_DIR$/src/common/tusb_fifo.c - - - $TUSB_DIR$/src/class/audio/audio_device.c - - - $TUSB_DIR$/src/class/bth/bth_device.c - - - $TUSB_DIR$/src/class/cdc/cdc_device.c - $TUSB_DIR$/src/class/cdc/cdc_host.c - $TUSB_DIR$/src/class/cdc/cdc_rndis_host.c - - - $TUSB_DIR$/src/class/dfu/dfu_device.c - $TUSB_DIR$/src/class/dfu/dfu_rt_device.c - - - $TUSB_DIR$/src/class/hid/hid_device.c - $TUSB_DIR$/src/class/hid/hid_host.c - - - $TUSB_DIR$/src/class/midi/midi_device.c - - - $TUSB_DIR$/src/class/msc/msc_device.c - $TUSB_DIR$/src/class/msc/msc_host.c - - - $TUSB_DIR$/src/class/net/net_device.c - - - $TUSB_DIR$/src/class/usbtmc/usbtmc_device.c - - - $TUSB_DIR$/src/class/vendor/vendor_device.c - $TUSB_DIR$/src/class/vendor/vendor_host.c - - - $TUSB_DIR$/src/tusb.c - - - $TUSB_DIR$/src/host/hub.c - $TUSB_DIR$/src/host/usbh.c - $TUSB_DIR$/src/host/usbh_control.c - - - $TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c - - - $TUSB_DIR$/src/portable/ehci/ehci.c - - - $TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c - - - $TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c - - - $TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c - - - $TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c - - - $TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c - - - $TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c - - - $TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c - - - $TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c - - - $TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c - - - $TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c - - - $TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c - $TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c - - - $TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c - - - $TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c - $TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c - - - $TUSB_DIR$/src/portable/ohci/ohci.c - - - $TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c - $TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c - $TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c - - - $TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c - - - $TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c - - - $TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c - - - $TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c - - - $TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c - - - $TUSB_DIR$/src/portable/template/dcd_template.c - - - $TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c - - - $TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c - - - $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c - $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c - $TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c - - - - diff --git a/tools/iar_gen.py b/tools/iar_gen.py index b8c270ff7..73c8b29fc 100644 --- a/tools/iar_gen.py +++ b/tools/iar_gen.py @@ -5,7 +5,7 @@ import xml.dom.minidom as XML # Read base configuration base = "" -with open("iar.ipcf") as f: +with open("iar_template.ipcf") as f: base = f.read() # Enumerate all device/host examples diff --git a/tools/iar_template.ipcf b/tools/iar_template.ipcf new file mode 100644 index 000000000..b8e50a1d2 --- /dev/null +++ b/tools/iar_template.ipcf @@ -0,0 +1,147 @@ + + + + + $TUSB_DIR$/src + $TUSB_DIR$/lib/SEGGER_RTT/RTT + $PROJ_DIR$ + + + + $TUSB_DIR$/src/device/usbd.c + $TUSB_DIR$/src/device/usbd_control.c + + + $TUSB_DIR$/src/common/tusb_fifo.c + + + $TUSB_DIR$/src/class/audio/audio_device.c + + + $TUSB_DIR$/src/class/bth/bth_device.c + + + $TUSB_DIR$/src/class/cdc/cdc_device.c + $TUSB_DIR$/src/class/cdc/cdc_host.c + $TUSB_DIR$/src/class/cdc/cdc_rndis_host.c + + + $TUSB_DIR$/src/class/dfu/dfu_device.c + $TUSB_DIR$/src/class/dfu/dfu_rt_device.c + + + $TUSB_DIR$/src/class/hid/hid_device.c + $TUSB_DIR$/src/class/hid/hid_host.c + + + $TUSB_DIR$/src/class/midi/midi_device.c + + + $TUSB_DIR$/src/class/msc/msc_device.c + $TUSB_DIR$/src/class/msc/msc_host.c + + + $TUSB_DIR$/src/class/net/net_device.c + + + $TUSB_DIR$/src/class/usbtmc/usbtmc_device.c + + + $TUSB_DIR$/src/class/vendor/vendor_device.c + $TUSB_DIR$/src/class/vendor/vendor_host.c + + + $TUSB_DIR$/src/tusb.c + + + $TUSB_DIR$/src/host/hub.c + $TUSB_DIR$/src/host/usbh.c + $TUSB_DIR$/src/host/usbh_control.c + + + $TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c + + + $TUSB_DIR$/src/portable/ehci/ehci.c + + + $TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c + + + $TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c + + + $TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c + + + $TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c + + + $TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c + + + $TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c + + + $TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c + + + $TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c + + + $TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c + $TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c + + + $TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c + + + $TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c + $TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c + + + $TUSB_DIR$/src/portable/ohci/ohci.c + + + $TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c + $TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c + + + $TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c + + + $TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c + + + $TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c + + + $TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c + + + $TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c + + + $TUSB_DIR$/src/portable/template/dcd_template.c + + + $TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c + + + $TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c + + + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c + $TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c + $TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c + + + + -- cgit v1.3.1 From b6cda41dafe51dd7d7a28c8b9473929bfe36c933 Mon Sep 17 00:00:00 2001 From: MasterPhi Date: Tue, 7 Sep 2021 12:32:27 +0200 Subject: Add doc for IAR. --- docs/reference/getting_started.rst | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/docs/reference/getting_started.rst b/docs/reference/getting_started.rst index 5f3227927..be2e1b5ea 100644 --- a/docs/reference/getting_started.rst +++ b/docs/reference/getting_started.rst @@ -151,3 +151,39 @@ Some board use uf2 bootloader for drag & drop in to mass storage device, uf2 can .. code-block:: $ make BOARD=feather_nrf52840_express all uf2 + +IAR Support +----------- + +IAR Project Connection files are provided to import TinyUSB stack into your project. + +* A buldable project of your MCU need to be created in advance. + + + * Take example of STM32F0: + + - You need `stm32l0xx.h`, `startup_stm32f0xx.s`, `system_stm32f0xx.c`. + + - `STM32L0xx_HAL_Driver` is only needed to run examples, TinyUSB stack itself doesn't rely on MCU's SDKs. + +* Open `Tools -> Configure Custom Argument Variables` (Switch to `Global` tab if you want to do it for all your projects) + Click `New Group ...`, name it to `TUSB`, Click `Add Variable ...`, name it to `TUSB_DIR`, change it's value to the path of your TinyUSB stack, + for example `C:\\tinyusb` + +Import stack only +^^^^^^^^^^^^^^^^^ + +1. Open `Project -> Add project Connection ...`, click `OK`, choose `tinyusb\\tools\\iar_template.ipcf`. + +Run examples +^^^^^^^^^^^^ + +1. (Python3 is needed) Run `iar_gen.py` to generate .ipcf files of examples: + + .. code-block:: + + cd C:\tinyusb\tools + python iar_gen.py + +2. Open `Project -> Add project Connection ...`, click `OK`, choose `tinyusb\\examples\\(.ipcf of example)`. + For example `C:\\tinyusb\\examples\\device\\cdc_msc\\iar_cdc_msc.ipcf` -- cgit v1.3.1 From 785cdf67f0e03a456fd2dfad7b769b094f7e07ce Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 7 Sep 2021 17:43:45 +0700 Subject: default PYTHON to python3 on linux, and python on windows --- examples/make.mk | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/examples/make.mk b/examples/make.mk index 24f8c5572..c894d35f4 100644 --- a/examples/make.mk +++ b/examples/make.mk @@ -61,15 +61,16 @@ GDB = $(CROSS_COMPILE)gdb OBJCOPY = $(CROSS_COMPILE)objcopy SIZE = $(CROSS_COMPILE)size MKDIR = mkdir -PYTHON = python ifeq ($(CMDEXE),1) CP = copy RM = del + PYTHON = python else SED = sed CP = cp RM = rm + PYTHON = python3 endif #-------------- Source files and compiler flags -------------- -- cgit v1.3.1 From e06a632b72aa926473375a2ed97d142196429d7f Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Sat, 28 Aug 2021 23:55:41 +0900 Subject: Update Renesas RX --- docs/reference/supported.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst index 4c7d753c2..d114d8405 100644 --- a/docs/reference/supported.rst +++ b/docs/reference/supported.rst @@ -84,9 +84,9 @@ Supported MCUs +--------------+-------+------------+-------------------+--------------------+-------------------+-------------------+--------------+ | Raspberry Pi | RP2040 | |:green_square:| | |:x:| | |:green_square:| | | | +--------------+--------------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| Renesas | RX63N | | | | | | +| Renesas | RX63N | |:green_square:| | | |:green_square:| | |:x:| | | | +--------------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| | RX65N | | | | | | +| | RX65N | |:green_square:| | | |:green_square:| | |:x:| | | +--------------+--------------------+-------------------+--------------------+-------------------+-------------------+--------------+ | Silabs | EFM32GG12 | |:green_square:| | |:x:| | |:green_square:| | |:x:| | #750 | +--------------+--------------------+-------------------+--------------------+-------------------+-------------------+--------------+ -- cgit v1.3.1 From f3da48d46adac415846985643c1b6d04c3866b94 Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Tue, 31 Aug 2021 00:14:39 +0900 Subject: Implement dcd_edpt_close_all() for Renesas RX family --- src/portable/renesas/usba/dcd_usba.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/src/portable/renesas/usba/dcd_usba.c b/src/portable/renesas/usba/dcd_usba.c index a837b5724..8e2e3dc26 100644 --- a/src/portable/renesas/usba/dcd_usba.c +++ b/src/portable/renesas/usba/dcd_usba.c @@ -733,10 +733,16 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) return true; } -void dcd_edpt_close_all (uint8_t rhport) +void dcd_edpt_close_all(uint8_t rhport) { - (void) rhport; - // TODO implement dcd_edpt_close_all() + unsigned i = TU_ARRAY_SIZE(_dcd.pipe); + dcd_int_disable(rhport); + while (--i) { /* Close all pipes except 0 */ + const unsigned ep_addr = _dcd.pipe[i].ep; + if (!ep_addr) continue; + dcd_edpt_close(rhport, ep_addr); + } + dcd_int_enable(rhport); } void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) -- cgit v1.3.1 From a54a974fa58c3c863ea6855ac911cecffb2afc04 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 7 Sep 2021 23:02:57 +0700 Subject: make synopsys usbcv compliance - implement dcd_edpt_close_all() - reset dtoggle when open endpoint - correct dev interrupt mask on bus reset --- src/portable/st/synopsys/dcd_synopsys.c | 63 ++++++++++++++++++++------------- 1 file changed, 38 insertions(+), 25 deletions(-) diff --git a/src/portable/st/synopsys/dcd_synopsys.c b/src/portable/st/synopsys/dcd_synopsys.c index fe165e830..93bbaf23b 100644 --- a/src/portable/st/synopsys/dcd_synopsys.c +++ b/src/portable/st/synopsys/dcd_synopsys.c @@ -213,17 +213,18 @@ static void bus_reset(uint8_t rhport) tu_memclr(xfer_status, sizeof(xfer_status)); _out_ep_closed = false; + // clear device address + dev->DCFG &= ~USB_OTG_DCFG_DAD_Msk; + + // 1. NAK for all OUT endpoints for(uint8_t n = 0; n < EP_MAX; n++) { out_ep[n].DOEPCTL |= USB_OTG_DOEPCTL_SNAK; } - // clear device address - dev->DCFG &= ~USB_OTG_DCFG_DAD_Msk; - - // TODO should probably assign value when reset rather than OR - dev->DAINTMSK |= (1 << USB_OTG_DAINTMSK_OEPM_Pos) | (1 << USB_OTG_DAINTMSK_IEPM_Pos); - dev->DOEPMSK |= USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM; - dev->DIEPMSK |= USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM; + // 2. Un-mask interrupt bits + dev->DAINTMSK = (1 << USB_OTG_DAINTMSK_OEPM_Pos) | (1 << USB_OTG_DAINTMSK_IEPM_Pos); + dev->DOEPMSK = USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM; + dev->DIEPMSK = USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM; // "USB Data FIFOs" section in reference manual // Peripheral FIFO architecture @@ -307,8 +308,6 @@ static void set_turnaround(USB_OTG_GlobalTypeDef * usb_otg, tusb_speed_t speed) // Turnaround timeout depends on the MCU clock uint32_t turnaround; - TU_LOG_INT(2, SystemCoreClock); - if ( SystemCoreClock >= 32000000U ) turnaround = 0x6U; else if ( SystemCoreClock >= 27500000U ) @@ -618,8 +617,9 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) usb_otg->GRXFSIZ = sz; } - out_ep[epnum].DOEPCTL |= (1 << USB_OTG_DOEPCTL_USBAEP_Pos) | - (desc_edpt->bmAttributes.xfer << USB_OTG_DOEPCTL_EPTYP_Pos) | + out_ep[epnum].DOEPCTL |= (1 << USB_OTG_DOEPCTL_USBAEP_Pos) | + (desc_edpt->bmAttributes.xfer << USB_OTG_DOEPCTL_EPTYP_Pos) | + (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_OTG_DOEPCTL_SD0PID_SEVNFRM : 0) | (desc_edpt->wMaxPacketSize.size << USB_OTG_DOEPCTL_MPSIZ_Pos); dev->DAINTMSK |= (1 << (USB_OTG_DAINTMSK_OEPM_Pos + epnum)); @@ -661,7 +661,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) in_ep[epnum].DIEPCTL |= (1 << USB_OTG_DIEPCTL_USBAEP_Pos) | (epnum << USB_OTG_DIEPCTL_TXFNUM_Pos) | (desc_edpt->bmAttributes.xfer << USB_OTG_DIEPCTL_EPTYP_Pos) | - (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_OTG_DOEPCTL_SD0PID_SEVNFRM : 0) | + (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_OTG_DIEPCTL_SD0PID_SEVNFRM : 0) | (desc_edpt->wMaxPacketSize.size << USB_OTG_DIEPCTL_MPSIZ_Pos); dev->DAINTMSK |= (1 << (USB_OTG_DAINTMSK_IEPM_Pos + epnum)); @@ -670,10 +670,32 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) return true; } +// Close all non-control endpoints, cancel all pending transfers if any. void dcd_edpt_close_all (uint8_t rhport) { (void) rhport; - // TODO implement dcd_edpt_close_all() + +// USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport); + USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport); + USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport); + USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport); + + // Disable non-control interrupt + dev->DAINTMSK = (1 << USB_OTG_DAINTMSK_OEPM_Pos) | (1 << USB_OTG_DAINTMSK_IEPM_Pos); + + for(uint8_t n = 1; n < EP_MAX; n++) + { + // disable OUT endpoint + out_ep[n].DOEPCTL = 0; + xfer_status[n][TUSB_DIR_OUT].max_size = 0; + + // disable IN endpoint + in_ep[n].DIEPCTL = 0; + xfer_status[n][TUSB_DIR_IN].max_size = 0; + } + + // reset allocated fifo IN + _allocated_fifo_words_tx = 16; } bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) @@ -835,22 +857,13 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); + // Clear stall and reset data toggle if(dir == TUSB_DIR_IN) { in_ep[epnum].DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; - - uint8_t eptype = (in_ep[epnum].DIEPCTL & USB_OTG_DIEPCTL_EPTYP_Msk) >> USB_OTG_DIEPCTL_EPTYP_Pos; - // Required by USB spec to reset DATA toggle bit to DATA0 on interrupt and bulk endpoints. - if(eptype == 2 || eptype == 3) { - in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; - } + in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; } else { out_ep[epnum].DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; - - uint8_t eptype = (out_ep[epnum].DOEPCTL & USB_OTG_DOEPCTL_EPTYP_Msk) >> USB_OTG_DOEPCTL_EPTYP_Pos; - // Required by USB spec to reset DATA toggle bit to DATA0 on interrupt and bulk endpoints. - if(eptype == 2 || eptype == 3) { - out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; - } + out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; } } -- cgit v1.3.1 From 4ac136d81d452ea1dcfc1e9e2e8afbf02749044d Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 8 Sep 2021 00:57:07 +0700 Subject: implement remote wakeup for stm synopsys --- src/portable/st/synopsys/dcd_synopsys.c | 38 ++++++++++++++++++++++++++------- 1 file changed, 30 insertions(+), 8 deletions(-) diff --git a/src/portable/st/synopsys/dcd_synopsys.c b/src/portable/st/synopsys/dcd_synopsys.c index 93bbaf23b..b1435a6c8 100644 --- a/src/portable/st/synopsys/dcd_synopsys.c +++ b/src/portable/st/synopsys/dcd_synopsys.c @@ -555,13 +555,31 @@ void dcd_set_address (uint8_t rhport, uint8_t dev_addr) dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0); } +static void remote_wakeup_delay(void) +{ + // try to delay for 1 ms + uint32_t count = SystemCoreClock / 1000; + while(count--) __NOP(); +} + void dcd_remote_wakeup(uint8_t rhport) { (void) rhport; - // TODO must manually clear this bit after 1-15 ms - // USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport); - // dev->DCTL |= USB_OTG_DCTL_RWUSIG; + USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport); + USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport); + + // set remote wakeup + dev->DCTL |= USB_OTG_DCTL_RWUSIG; + + // enable SOF to detect bus resume + usb_otg->GINTSTS = USB_OTG_GINTSTS_SOF; + usb_otg->GINTMSK |= USB_OTG_GINTMSK_SOFM; + + // Per specs: remote wakeup signal bit must be clear within 1-15ms + remote_wakeup_delay(); + + dev->DCTL &= ~USB_OTG_DCTL_RWUSIG; } void dcd_connect(uint8_t rhport) @@ -1100,7 +1118,7 @@ void dcd_int_handler(uint8_t rhport) USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport); USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport); - uint32_t int_status = usb_otg->GINTSTS; + uint32_t const int_status = usb_otg->GINTSTS & usb_otg->GINTMSK; if(int_status & USB_OTG_GINTSTS_USBRST) { @@ -1133,6 +1151,9 @@ void dcd_int_handler(uint8_t rhport) dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true); } + // TODO check USB_OTG_GINTSTS_DISCINT for disconnect detection + // if(int_status & USB_OTG_GINTSTS_DISCINT) + if(int_status & USB_OTG_GINTSTS_OTGINT) { // OTG INT bit is read-only @@ -1146,13 +1167,15 @@ void dcd_int_handler(uint8_t rhport) usb_otg->GOTGINT = otg_int; } -#if USE_SOF if(int_status & USB_OTG_GINTSTS_SOF) { usb_otg->GINTSTS = USB_OTG_GINTSTS_SOF; + + // Disable SOF interrupt since currently only used for remote wakeup detection + usb_otg->GINTMSK &= ~USB_OTG_GINTMSK_SOFM; + dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true); } -#endif // RxFIFO non-empty interrupt handling. if(int_status & USB_OTG_GINTSTS_RXFLVL) @@ -1166,8 +1189,7 @@ void dcd_int_handler(uint8_t rhport) do { handle_rxflvl_ints(rhport, out_ep); - int_status = usb_otg->GINTSTS; - } while(int_status & USB_OTG_GINTSTS_RXFLVL); + } while(usb_otg->GINTSTS & USB_OTG_GINTSTS_RXFLVL); // Manage RX FIFO size if (_out_ep_closed) -- cgit v1.3.1 From 185bb21bdd1177b14415751fd0b626d0f9c79e15 Mon Sep 17 00:00:00 2001 From: David Shadoff Date: Tue, 7 Sep 2021 21:13:34 -0400 Subject: Add PS4-compatible controllers --- examples/host/hid_controller/src/hid_app.c | 1 + examples/host/hid_controller/src/main.c | 1 + 2 files changed, 2 insertions(+) diff --git a/examples/host/hid_controller/src/hid_app.c b/examples/host/hid_controller/src/hid_app.c index d88c74ac4..bbfea8182 100644 --- a/examples/host/hid_controller/src/hid_app.c +++ b/examples/host/hid_controller/src/hid_app.c @@ -113,6 +113,7 @@ static inline bool is_sony_ds4(uint8_t dev_addr) return ( (vid == 0x054c && (pid == 0x09cc || pid == 0x05c4)) // Sony DualShock4 || (vid == 0x0f0d && pid == 0x005e) // Hori FC4 + || (vid == 0x0f0d && pid == 0x00ee) // Hori PS4 Mini (PS4-099U) || (vid == 0x1f4f && pid == 0x1002) // ASW GG xrd controller ); } diff --git a/examples/host/hid_controller/src/main.c b/examples/host/hid_controller/src/main.c index e13fa818a..b9b37a4d2 100644 --- a/examples/host/hid_controller/src/main.c +++ b/examples/host/hid_controller/src/main.c @@ -49,6 +49,7 @@ int main(void) board_init(); printf("TinyUSB Host HID Controller Example\r\n"); + printf("Note: Events only displayed for explictly supported controllers\r\n"); tusb_init(); -- cgit v1.3.1 From 67e80f60e3841497779a319bbd93133c05b013f8 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 8 Sep 2021 13:35:11 +0700 Subject: fix build with gd32vf103 --- src/portable/st/synopsys/dcd_synopsys.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/portable/st/synopsys/dcd_synopsys.c b/src/portable/st/synopsys/dcd_synopsys.c index b1435a6c8..85abf940e 100644 --- a/src/portable/st/synopsys/dcd_synopsys.c +++ b/src/portable/st/synopsys/dcd_synopsys.c @@ -96,6 +96,9 @@ #elif CFG_TUSB_MCU == OPT_MCU_GD32VF103 #include "synopsys_common.h" +// for remote wakeup delay +#define __NOP() __asm volatile ("nop") + // These numbers are the same for the whole GD32VF103 family. #define OTG_FS_IRQn 86 #define EP_MAX_FS 4 @@ -559,7 +562,10 @@ static void remote_wakeup_delay(void) { // try to delay for 1 ms uint32_t count = SystemCoreClock / 1000; - while(count--) __NOP(); + while ( count-- ) + { + __NOP(); + } } void dcd_remote_wakeup(uint8_t rhport) -- cgit v1.3.1 From d077574097e4ab992f8b7c732341250797acef4f Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 8 Sep 2021 17:56:22 +0700 Subject: reset PID to DATA0 when open endpoint --- src/portable/renesas/usba/dcd_usba.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/portable/renesas/usba/dcd_usba.c b/src/portable/renesas/usba/dcd_usba.c index 8e2e3dc26..92e29f9bf 100644 --- a/src/portable/renesas/usba/dcd_usba.c +++ b/src/portable/renesas/usba/dcd_usba.c @@ -711,7 +711,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) USB0.PIPESEL.WORD = num; USB0.PIPEMAXP.WORD = mps; volatile uint16_t *ctr = get_pipectr(num); - *ctr = USB_PIPECTR_ACLRM; + *ctr = USB_PIPECTR_ACLRM | USB_PIPECTR_SQCLR; *ctr = 0; unsigned cfg = (dir << 4) | epn; if (xfer == TUSB_XFER_BULK) { -- cgit v1.3.1 From 22b5b4704591da35c804045b81b63dd5094d5050 Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Wed, 8 Sep 2021 21:52:27 +0900 Subject: Implement dcd_edpt_close_all for NXP khci --- src/portable/nxp/khci/dcd_khci.c | 24 +++++++++++++++++++++--- 1 file changed, 21 insertions(+), 3 deletions(-) diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c index 1f5f4e5e1..625ddcf8c 100644 --- a/src/portable/nxp/khci/dcd_khci.c +++ b/src/portable/nxp/khci/dcd_khci.c @@ -347,10 +347,26 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) return true; } -void dcd_edpt_close_all (uint8_t rhport) +void dcd_edpt_close_all(uint8_t rhport) { (void) rhport; - // TODO implement dcd_edpt_close_all() + const unsigned ie = NVIC_GetEnableIRQ(USB0_IRQn); + NVIC_DisableIRQ(USB0_IRQn); + for (unsigned i = 1; i < 16; ++i) { + KHCI->ENDPOINT[i].ENDPT = 0; + } + if (ie) NVIC_EnableIRQ(USB0_IRQn); + buffer_descriptor_t *bd = _dcd.bdt[1][0]; + for (unsigned i = 2; i < sizeof(_dcd.bdt)/sizeof(*bd); ++i, ++bd) { + bd->head = 0; + } + endpoint_state_t *ep = &_dcd.endpoint[1][0]; + for (unsigned i = 2; i < sizeof(_dcd.endpoint)/sizeof(*ep); ++i, ++ep) { + /* Clear except the odd */ + ep->max_packet_size = 0; + ep->length = 0; + ep->remaining = 0; + } } void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) @@ -372,6 +388,7 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) { (void) rhport; + const unsigned ie = NVIC_GetEnableIRQ(USB0_IRQn); NVIC_DisableIRQ(USB0_IRQn); const unsigned epn = ep_addr & 0xFu; const unsigned dir = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT; @@ -380,6 +397,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to if (bd->own) { TU_LOG1("DCD XFER fail %x %d %lx %lx\r\n", ep_addr, total_bytes, ep->state, bd->head); + if (ie) NVIC_EnableIRQ(USB0_IRQn); return false; /* The last transfer has not completed */ } ep->length = total_bytes; @@ -398,7 +416,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to bd->addr = buffer; __DSB(); bd->own = 1; /* the own bit must set after addr */ - NVIC_EnableIRQ(USB0_IRQn); + if (ie) NVIC_EnableIRQ(USB0_IRQn); return true; } -- cgit v1.3.1 From 780852efb3c1686fef7f47b42eaabfc65356faae Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Thu, 9 Sep 2021 00:55:02 +0900 Subject: Fix stall handling --- src/portable/nxp/khci/dcd_khci.c | 73 ++++++++++++++++++++-------------------- 1 file changed, 37 insertions(+), 36 deletions(-) diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c index 625ddcf8c..0ddd0f75e 100644 --- a/src/portable/nxp/khci/dcd_khci.c +++ b/src/portable/nxp/khci/dcd_khci.c @@ -121,7 +121,7 @@ static void prepare_next_setup_packet(uint8_t rhport) const unsigned out_odd = _dcd.endpoint[0][0].odd; const unsigned in_odd = _dcd.endpoint[0][1].odd; if (_dcd.bdt[0][0][out_odd].own) { - TU_LOG1("DCD fail to prepare the next SETUP %d %d\r\n", out_odd, in_odd); + // TU_LOG1("DCD fail to prepare the next SETUP %d %d\r\n", out_odd, in_odd); return; } _dcd.bdt[0][0][out_odd].data = 0; @@ -163,9 +163,6 @@ static void process_tokdne(uint8_t rhport) KHCI->CTL &= ~USB_CTL_TXSUSPENDTOKENBUSY_MASK; return; } - if (s >> 4) { - TU_LOG1("TKDNE %x\r\n", s); - } const unsigned bc = bd->bc; const unsigned remaining = ep->remaining - bc; @@ -321,8 +318,8 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) (void) rhport; const unsigned ep_addr = ep_desc->bEndpointAddress; - const unsigned epn = ep_addr & 0xFu; - const unsigned dir = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT; + const unsigned epn = tu_edpt_number(ep_addr); + const unsigned dir = tu_edpt_dir(ep_addr); const unsigned xfer = ep_desc->bmAttributes.xfer; endpoint_state_t *ep = &_dcd.endpoint[epn][dir]; const unsigned odd = ep->odd; @@ -373,8 +370,8 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) { (void) rhport; - const unsigned epn = ep_addr & 0xFu; - const unsigned dir = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT; + const unsigned epn = tu_edpt_number(ep_addr); + const unsigned dir = tu_edpt_dir(ep_addr); endpoint_state_t *ep = &_dcd.endpoint[epn][dir]; buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][0]; const unsigned msk = dir ? USB_ENDPT_EPTXEN_MASK : USB_ENDPT_EPRXEN_MASK; @@ -388,18 +385,15 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) { (void) rhport; - const unsigned ie = NVIC_GetEnableIRQ(USB0_IRQn); - NVIC_DisableIRQ(USB0_IRQn); - const unsigned epn = ep_addr & 0xFu; - const unsigned dir = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT; + const unsigned epn = tu_edpt_number(ep_addr); + const unsigned dir = tu_edpt_dir(ep_addr); endpoint_state_t *ep = &_dcd.endpoint[epn][dir]; buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][ep->odd]; + TU_ASSERT(0 == bd->own); + + const unsigned ie = NVIC_GetEnableIRQ(USB0_IRQn); + NVIC_DisableIRQ(USB0_IRQn); - if (bd->own) { - TU_LOG1("DCD XFER fail %x %d %lx %lx\r\n", ep_addr, total_bytes, ep->state, bd->head); - if (ie) NVIC_EnableIRQ(USB0_IRQn); - return false; /* The last transfer has not completed */ - } ep->length = total_bytes; ep->remaining = total_bytes; @@ -412,10 +406,10 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to next->addr = buffer + mps; next->own = 1; } - bd->bc = total_bytes >= mps ? mps: total_bytes; - bd->addr = buffer; + bd->bc = total_bytes >= mps ? mps: total_bytes; + bd->addr = buffer; __DSB(); - bd->own = 1; /* the own bit must set after addr */ + bd->own = 1; /* This bit must be set last */ if (ie) NVIC_EnableIRQ(USB0_IRQn); return true; } @@ -423,31 +417,38 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { (void) rhport; - const unsigned epn = ep_addr & 0xFu; + const unsigned epn = tu_edpt_number(ep_addr); if (0 == epn) { KHCI->ENDPOINT[epn].ENDPT |= USB_ENDPT_EPSTALL_MASK; } else { - const unsigned dir = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT; - buffer_descriptor_t *bd = _dcd.bdt[epn][dir]; - bd[0].bdt_stall = 1; - bd[1].bdt_stall = 1; + const unsigned dir = tu_edpt_dir(ep_addr); + endpoint_state_t *ep = &_dcd.endpoint[epn][dir]; + buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][ep->odd]; + TU_ASSERT(0 == bd->own,); + const unsigned ie = NVIC_GetEnableIRQ(USB0_IRQn); + NVIC_DisableIRQ(USB0_IRQn); + bd->bdt_stall = 1; + __DSB(); + bd->own = 1; /* This bit must be set last */ + if (ie) NVIC_EnableIRQ(USB0_IRQn); } } void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { (void) rhport; - const unsigned epn = ep_addr & 0xFu; - const unsigned dir = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT; - const unsigned odd = _dcd.endpoint[epn][dir].odd; - buffer_descriptor_t *bd = _dcd.bdt[epn][dir]; - - bd[odd ^ 1].own = 0; - bd[odd ^ 1].data = 1; - bd[odd ^ 1].bdt_stall = 0; - bd[odd].own = 0; - bd[odd].data = 0; - bd[odd].bdt_stall = 0; + const unsigned epn = tu_edpt_number(ep_addr); + TU_VERIFY(epn,); + const unsigned dir = tu_edpt_dir(ep_addr); + endpoint_state_t *ep = &_dcd.endpoint[epn][dir]; + buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][ep->odd]; + TU_ASSERT(bd->own,); + const unsigned ie = NVIC_GetEnableIRQ(USB0_IRQn); + NVIC_DisableIRQ(USB0_IRQn); + bd->own = 0; + __DSB(); + bd->bdt_stall = 0; + if (ie) NVIC_EnableIRQ(USB0_IRQn); } //--------------------------------------------------------------------+ -- cgit v1.3.1 From f81368174b613f4168ddb0e2ec1822c8dbc31d59 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 9 Sep 2021 14:34:03 +0700 Subject: add other speed descriptor callback tud_descriptor_other_speed_configuration_cb() example implement tud_descriptor_device_qualifier_cb() and tud_descriptor_other_speed_configuration_cb() on high speed device to fully compliant to usbcv --- .../device/cdc_dual_ports/src/usb_descriptors.c | 48 ++++++++++- examples/device/cdc_msc/src/usb_descriptors.c | 92 +++++++++++++++++----- .../device/cdc_msc_freertos/src/usb_descriptors.c | 63 +++++++++++++-- .../device/hid_composite/src/usb_descriptors.c | 57 +++++++++++++- .../hid_composite_freertos/src/usb_descriptors.c | 55 ++++++++++++- src/common/tusb_types.h | 5 +- src/device/usbd.c | 40 +++++----- src/device/usbd.h | 9 ++- 8 files changed, 315 insertions(+), 54 deletions(-) diff --git a/examples/device/cdc_dual_ports/src/usb_descriptors.c b/examples/device/cdc_dual_ports/src/usb_descriptors.c index 02ccbcc9e..aa400d486 100644 --- a/examples/device/cdc_dual_ports/src/usb_descriptors.c +++ b/examples/device/cdc_dual_ports/src/usb_descriptors.c @@ -35,6 +35,9 @@ #define USB_PID (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \ _PID_MAP(MIDI, 3) | _PID_MAP(VENDOR, 4) ) +#define USB_VID 0xCafe +#define USB_BCD 0x0200 + //--------------------------------------------------------------------+ // Device Descriptors //--------------------------------------------------------------------+ @@ -42,7 +45,7 @@ tusb_desc_device_t const desc_device = { .bLength = sizeof(tusb_desc_device_t), .bDescriptorType = TUSB_DESC_DEVICE, - .bcdUSB = 0x0200, + .bcdUSB = USB_BCD, // Use Interface Association Descriptor (IAD) for CDC // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1) @@ -51,7 +54,7 @@ tusb_desc_device_t const desc_device = .bDeviceProtocol = MISC_PROTOCOL_IAD, .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE, - .idVendor = 0xCafe, + .idVendor = USB_VID, .idProduct = USB_PID, .bcdDevice = 0x0100, @@ -128,6 +131,8 @@ uint8_t const desc_fs_configuration[] = }; #if TUD_OPT_HIGH_SPEED +// Per USB specs: high speed capable device must report device_qualifier and other_speed_configuration + uint8_t const desc_hs_configuration[] = { // Config number, interface count, string index, total length, attribute, power in mA @@ -139,7 +144,44 @@ uint8_t const desc_hs_configuration[] = // 2nd CDC: Interface number, string index, EP notification address and size, EP data address (out, in) and size. TUD_CDC_DESCRIPTOR(ITF_NUM_CDC_1, 4, EPNUM_CDC_1_NOTIF, 8, EPNUM_CDC_1_OUT, EPNUM_CDC_1_IN, 512), }; -#endif + +// device qualifier is mostly similar to device descriptor since we don't change configuration based on speed +tusb_desc_device_qualifier_t const desc_device_qualifier = +{ + .bLength = sizeof(tusb_desc_device_t), + .bDescriptorType = TUSB_DESC_DEVICE, + .bcdUSB = USB_BCD, + + .bDeviceClass = TUSB_CLASS_MISC, + .bDeviceSubClass = MISC_SUBCLASS_COMMON, + .bDeviceProtocol = MISC_PROTOCOL_IAD, + + .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE, + .bNumConfigurations = 0x01, + .bReserved = 0x00 +}; + +// Invoked when received GET DEVICE QUALIFIER DESCRIPTOR request +// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete. +// device_qualifier descriptor describes information about a high-speed capable device that would +// change if the device were operating at the other speed. If not highspeed capable stall this request. +uint8_t const* tud_descriptor_device_qualifier_cb(void) +{ + return (uint8_t const*) &desc_device_qualifier; +} + +// Invoked when received GET OTHER SEED CONFIGURATION DESCRIPTOR request +// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete +// Configuration descriptor in the other speed e.g if high speed then this is for full speed and vice versa +uint8_t const* tud_descriptor_other_speed_configuration_cb(uint8_t index) +{ + (void) index; // for multiple configurations + + // if link speed is high return fullspeed config, and vice versa + return (tud_speed_get() == TUSB_SPEED_HIGH) ? desc_fs_configuration : desc_hs_configuration; +} + +#endif // highspeed // Invoked when received GET CONFIGURATION DESCRIPTOR // Application return pointer to descriptor diff --git a/examples/device/cdc_msc/src/usb_descriptors.c b/examples/device/cdc_msc/src/usb_descriptors.c index 3cf1eaf91..34537b8f0 100644 --- a/examples/device/cdc_msc/src/usb_descriptors.c +++ b/examples/device/cdc_msc/src/usb_descriptors.c @@ -35,32 +35,35 @@ #define USB_PID (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \ _PID_MAP(MIDI, 3) | _PID_MAP(VENDOR, 4) ) +#define USB_VID 0xCafe +#define USB_BCD 0x0200 + //--------------------------------------------------------------------+ // Device Descriptors //--------------------------------------------------------------------+ tusb_desc_device_t const desc_device = { - .bLength = sizeof(tusb_desc_device_t), - .bDescriptorType = TUSB_DESC_DEVICE, - .bcdUSB = 0x0200, + .bLength = sizeof(tusb_desc_device_t), + .bDescriptorType = TUSB_DESC_DEVICE, + .bcdUSB = USB_BCD, - // Use Interface Association Descriptor (IAD) for CDC - // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1) - .bDeviceClass = TUSB_CLASS_MISC, - .bDeviceSubClass = MISC_SUBCLASS_COMMON, - .bDeviceProtocol = MISC_PROTOCOL_IAD, + // Use Interface Association Descriptor (IAD) for CDC + // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1) + .bDeviceClass = TUSB_CLASS_MISC, + .bDeviceSubClass = MISC_SUBCLASS_COMMON, + .bDeviceProtocol = MISC_PROTOCOL_IAD, - .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE, + .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE, - .idVendor = 0xCafe, - .idProduct = USB_PID, - .bcdDevice = 0x0100, + .idVendor = USB_VID, + .idProduct = USB_PID, + .bcdDevice = 0x0100, - .iManufacturer = 0x01, - .iProduct = 0x02, - .iSerialNumber = 0x03, + .iManufacturer = 0x01, + .iProduct = 0x02, + .iSerialNumber = 0x03, - .bNumConfigurations = 0x01 + .bNumConfigurations = 0x01 }; // Invoked when received GET DEVICE DESCRIPTOR @@ -82,8 +85,6 @@ enum ITF_NUM_TOTAL }; -#define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + TUD_CDC_DESC_LEN + TUD_MSC_DESC_LEN) - #if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In, 5 Bulk etc ... @@ -126,6 +127,9 @@ enum #endif +#define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + TUD_CDC_DESC_LEN + TUD_MSC_DESC_LEN) + +// full speed configuration uint8_t const desc_fs_configuration[] = { // Config number, interface count, string index, total length, attribute, power in mA @@ -139,6 +143,9 @@ uint8_t const desc_fs_configuration[] = }; #if TUD_OPT_HIGH_SPEED +// Per USB specs: high speed capable device must report device_qualifier and other_speed_configuration + +// high speed configuration uint8_t const desc_hs_configuration[] = { // Config number, interface count, string index, total length, attribute, power in mA @@ -150,7 +157,54 @@ uint8_t const desc_hs_configuration[] = // Interface number, string index, EP Out & EP In address, EP size TUD_MSC_DESCRIPTOR(ITF_NUM_MSC, 5, EPNUM_MSC_OUT, EPNUM_MSC_IN, 512), }; -#endif + +// other speed configuration +uint8_t desc_other_speed_config[CONFIG_TOTAL_LEN]; + +// device qualifier is mostly similar to device descriptor since we don't change configuration based on speed +tusb_desc_device_qualifier_t const desc_device_qualifier = +{ + .bLength = sizeof(tusb_desc_device_qualifier_t), + .bDescriptorType = TUSB_DESC_DEVICE_QUALIFIER, + .bcdUSB = USB_BCD, + + .bDeviceClass = TUSB_CLASS_MISC, + .bDeviceSubClass = MISC_SUBCLASS_COMMON, + .bDeviceProtocol = MISC_PROTOCOL_IAD, + + .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE, + .bNumConfigurations = 0x01, + .bReserved = 0x00 +}; + +// Invoked when received GET DEVICE QUALIFIER DESCRIPTOR request +// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete. +// device_qualifier descriptor describes information about a high-speed capable device that would +// change if the device were operating at the other speed. If not highspeed capable stall this request. +uint8_t const* tud_descriptor_device_qualifier_cb(void) +{ + return (uint8_t const*) &desc_device_qualifier; +} + +// Invoked when received GET OTHER SEED CONFIGURATION DESCRIPTOR request +// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete +// Configuration descriptor in the other speed e.g if high speed then this is for full speed and vice versa +uint8_t const* tud_descriptor_other_speed_configuration_cb(uint8_t index) +{ + (void) index; // for multiple configurations + + // if link speed is high return fullspeed config, and vice versa + // Note: the descriptor type is OHER_SPEED_CONFIG instead of CONFIG + memcpy(desc_other_speed_config, + (tud_speed_get() == TUSB_SPEED_HIGH) ? desc_fs_configuration : desc_hs_configuration, + CONFIG_TOTAL_LEN); + + desc_other_speed_config[1] = TUSB_DESC_OTHER_SPEED_CONFIG; + + return desc_other_speed_config; +} + +#endif // highspeed // Invoked when received GET CONFIGURATION DESCRIPTOR diff --git a/examples/device/cdc_msc_freertos/src/usb_descriptors.c b/examples/device/cdc_msc_freertos/src/usb_descriptors.c index c8dbcd415..f3ff305f8 100644 --- a/examples/device/cdc_msc_freertos/src/usb_descriptors.c +++ b/examples/device/cdc_msc_freertos/src/usb_descriptors.c @@ -35,6 +35,9 @@ #define USB_PID (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \ _PID_MAP(MIDI, 3) | _PID_MAP(VENDOR, 4) ) +#define USB_VID 0xCafe +#define USB_BCD 0x0200 + //--------------------------------------------------------------------+ // Device Descriptors //--------------------------------------------------------------------+ @@ -42,7 +45,7 @@ tusb_desc_device_t const desc_device = { .bLength = sizeof(tusb_desc_device_t), .bDescriptorType = TUSB_DESC_DEVICE, - .bcdUSB = 0x0200, + .bcdUSB = USB_BCD, // Use Interface Association Descriptor (IAD) for CDC // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1) @@ -52,7 +55,7 @@ tusb_desc_device_t const desc_device = .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE, - .idVendor = 0xCafe, + .idVendor = USB_VID, .idProduct = USB_PID, .bcdDevice = 0x0100, @@ -82,8 +85,6 @@ enum ITF_NUM_TOTAL }; -#define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + TUD_CDC_DESC_LEN + TUD_MSC_DESC_LEN) - #if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In, 5 Bulk etc ... @@ -114,6 +115,8 @@ enum #endif +#define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + TUD_CDC_DESC_LEN + TUD_MSC_DESC_LEN) + uint8_t const desc_fs_configuration[] = { // Config number, interface count, string index, total length, attribute, power in mA @@ -127,6 +130,9 @@ uint8_t const desc_fs_configuration[] = }; #if TUD_OPT_HIGH_SPEED +// Per USB specs: high speed capable device must report device_qualifier and other_speed_configuration + +// high speed configuration uint8_t const desc_hs_configuration[] = { // Config number, interface count, string index, total length, attribute, power in mA @@ -138,7 +144,54 @@ uint8_t const desc_hs_configuration[] = // Interface number, string index, EP Out & EP In address, EP size TUD_MSC_DESCRIPTOR(ITF_NUM_MSC, 5, EPNUM_MSC_OUT, EPNUM_MSC_IN, 512), }; -#endif + +// other speed configuration +uint8_t desc_other_speed_config[CONFIG_TOTAL_LEN]; + +// device qualifier is mostly similar to device descriptor since we don't change configuration based on speed +tusb_desc_device_qualifier_t const desc_device_qualifier = +{ + .bLength = sizeof(tusb_desc_device_qualifier_t), + .bDescriptorType = TUSB_DESC_DEVICE_QUALIFIER, + .bcdUSB = USB_BCD, + + .bDeviceClass = TUSB_CLASS_MISC, + .bDeviceSubClass = MISC_SUBCLASS_COMMON, + .bDeviceProtocol = MISC_PROTOCOL_IAD, + + .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE, + .bNumConfigurations = 0x01, + .bReserved = 0x00 +}; + +// Invoked when received GET DEVICE QUALIFIER DESCRIPTOR request +// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete. +// device_qualifier descriptor describes information about a high-speed capable device that would +// change if the device were operating at the other speed. If not highspeed capable stall this request. +uint8_t const* tud_descriptor_device_qualifier_cb(void) +{ + return (uint8_t const*) &desc_device_qualifier; +} + +// Invoked when received GET OTHER SEED CONFIGURATION DESCRIPTOR request +// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete +// Configuration descriptor in the other speed e.g if high speed then this is for full speed and vice versa +uint8_t const* tud_descriptor_other_speed_configuration_cb(uint8_t index) +{ + (void) index; // for multiple configurations + + // if link speed is high return fullspeed config, and vice versa + // Note: the descriptor type is OHER_SPEED_CONFIG instead of CONFIG + memcpy(desc_other_speed_config, + (tud_speed_get() == TUSB_SPEED_HIGH) ? desc_fs_configuration : desc_hs_configuration, + CONFIG_TOTAL_LEN); + + desc_other_speed_config[1] = TUSB_DESC_OTHER_SPEED_CONFIG; + + return desc_other_speed_config; +} + +#endif // highspeed // Invoked when received GET CONFIGURATION DESCRIPTOR // Application return pointer to descriptor diff --git a/examples/device/hid_composite/src/usb_descriptors.c b/examples/device/hid_composite/src/usb_descriptors.c index b9a6e7292..e760b20ba 100644 --- a/examples/device/hid_composite/src/usb_descriptors.c +++ b/examples/device/hid_composite/src/usb_descriptors.c @@ -36,6 +36,9 @@ #define USB_PID (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \ _PID_MAP(MIDI, 3) | _PID_MAP(VENDOR, 4) ) +#define USB_VID 0xCafe +#define USB_BCD 0x0200 + //--------------------------------------------------------------------+ // Device Descriptors //--------------------------------------------------------------------+ @@ -43,13 +46,13 @@ tusb_desc_device_t const desc_device = { .bLength = sizeof(tusb_desc_device_t), .bDescriptorType = TUSB_DESC_DEVICE, - .bcdUSB = 0x0200, + .bcdUSB = USB_BCD, .bDeviceClass = 0x00, .bDeviceSubClass = 0x00, .bDeviceProtocol = 0x00, .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE, - .idVendor = 0xCafe, + .idVendor = USB_VID, .idProduct = USB_PID, .bcdDevice = 0x0100, @@ -111,12 +114,62 @@ uint8_t const desc_configuration[] = TUD_HID_DESCRIPTOR(ITF_NUM_HID, 0, HID_ITF_PROTOCOL_NONE, sizeof(desc_hid_report), EPNUM_HID, CFG_TUD_HID_EP_BUFSIZE, 5) }; +#if TUD_OPT_HIGH_SPEED +// Per USB specs: high speed capable device must report device_qualifier and other_speed_configuration + +// other speed configuration +uint8_t desc_other_speed_config[CONFIG_TOTAL_LEN]; + +// device qualifier is mostly similar to device descriptor since we don't change configuration based on speed +tusb_desc_device_qualifier_t const desc_device_qualifier = +{ + .bLength = sizeof(tusb_desc_device_qualifier_t), + .bDescriptorType = TUSB_DESC_DEVICE_QUALIFIER, + .bcdUSB = USB_BCD, + + .bDeviceClass = 0x00, + .bDeviceSubClass = 0x00, + .bDeviceProtocol = 0x00, + + .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE, + .bNumConfigurations = 0x01, + .bReserved = 0x00 +}; + +// Invoked when received GET DEVICE QUALIFIER DESCRIPTOR request +// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete. +// device_qualifier descriptor describes information about a high-speed capable device that would +// change if the device were operating at the other speed. If not highspeed capable stall this request. +uint8_t const* tud_descriptor_device_qualifier_cb(void) +{ + return (uint8_t const*) &desc_device_qualifier; +} + +// Invoked when received GET OTHER SEED CONFIGURATION DESCRIPTOR request +// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete +// Configuration descriptor in the other speed e.g if high speed then this is for full speed and vice versa +uint8_t const* tud_descriptor_other_speed_configuration_cb(uint8_t index) +{ + (void) index; // for multiple configurations + + // other speed config is basically configuration with type = OHER_SPEED_CONFIG + memcpy(desc_other_speed_config, desc_configuration, CONFIG_TOTAL_LEN); + desc_other_speed_config[1] = TUSB_DESC_OTHER_SPEED_CONFIG; + + // this example use the same configuration for both high and full speed mode + return desc_other_speed_config; +} + +#endif // highspeed + // Invoked when received GET CONFIGURATION DESCRIPTOR // Application return pointer to descriptor // Descriptor contents must exist long enough for transfer to complete uint8_t const * tud_descriptor_configuration_cb(uint8_t index) { (void) index; // for multiple configurations + + // This example use the same configuration for both high and full speed mode return desc_configuration; } diff --git a/examples/device/hid_composite_freertos/src/usb_descriptors.c b/examples/device/hid_composite_freertos/src/usb_descriptors.c index b9a6e7292..791813fdf 100644 --- a/examples/device/hid_composite_freertos/src/usb_descriptors.c +++ b/examples/device/hid_composite_freertos/src/usb_descriptors.c @@ -36,6 +36,9 @@ #define USB_PID (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \ _PID_MAP(MIDI, 3) | _PID_MAP(VENDOR, 4) ) +#define USB_VID 0xCafe +#define USB_BCD 0x0200 + //--------------------------------------------------------------------+ // Device Descriptors //--------------------------------------------------------------------+ @@ -43,13 +46,13 @@ tusb_desc_device_t const desc_device = { .bLength = sizeof(tusb_desc_device_t), .bDescriptorType = TUSB_DESC_DEVICE, - .bcdUSB = 0x0200, + .bcdUSB = USB_BCD, .bDeviceClass = 0x00, .bDeviceSubClass = 0x00, .bDeviceProtocol = 0x00, .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE, - .idVendor = 0xCafe, + .idVendor = USB_VID, .idProduct = USB_PID, .bcdDevice = 0x0100, @@ -111,6 +114,54 @@ uint8_t const desc_configuration[] = TUD_HID_DESCRIPTOR(ITF_NUM_HID, 0, HID_ITF_PROTOCOL_NONE, sizeof(desc_hid_report), EPNUM_HID, CFG_TUD_HID_EP_BUFSIZE, 5) }; +#if TUD_OPT_HIGH_SPEED +// Per USB specs: high speed capable device must report device_qualifier and other_speed_configuration + +// other speed configuration +uint8_t desc_other_speed_config[CONFIG_TOTAL_LEN]; + +// device qualifier is mostly similar to device descriptor since we don't change configuration based on speed +tusb_desc_device_qualifier_t const desc_device_qualifier = +{ + .bLength = sizeof(tusb_desc_device_qualifier_t), + .bDescriptorType = TUSB_DESC_DEVICE_QUALIFIER, + .bcdUSB = USB_BCD, + + .bDeviceClass = 0x00, + .bDeviceSubClass = 0x00, + .bDeviceProtocol = 0x00, + + .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE, + .bNumConfigurations = 0x01, + .bReserved = 0x00 +}; + +// Invoked when received GET DEVICE QUALIFIER DESCRIPTOR request +// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete. +// device_qualifier descriptor describes information about a high-speed capable device that would +// change if the device were operating at the other speed. If not highspeed capable stall this request. +uint8_t const* tud_descriptor_device_qualifier_cb(void) +{ + return (uint8_t const*) &desc_device_qualifier; +} + +// Invoked when received GET OTHER SEED CONFIGURATION DESCRIPTOR request +// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete +// Configuration descriptor in the other speed e.g if high speed then this is for full speed and vice versa +uint8_t const* tud_descriptor_other_speed_configuration_cb(uint8_t index) +{ + (void) index; // for multiple configurations + + // other speed config is basically configuration with type = OHER_SPEED_CONFIG + memcpy(desc_other_speed_config, desc_configuration, CONFIG_TOTAL_LEN); + desc_other_speed_config[1] = TUSB_DESC_OTHER_SPEED_CONFIG; + + // this example use the same configuration for both high and full speed mode + return desc_other_speed_config; +} + +#endif // highspeed + // Invoked when received GET CONFIGURATION DESCRIPTOR // Application return pointer to descriptor // Descriptor contents must exist long enough for transfer to complete diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h index d23c6b2dd..f26983a74 100644 --- a/src/common/tusb_types.h +++ b/src/common/tusb_types.h @@ -372,7 +372,7 @@ typedef struct TU_ATTR_PACKED uint8_t bNumInterfaces ; ///< Number of interfaces supported by this speed configuration uint8_t bConfigurationValue ; ///< Value to use to select configuration - uint8_t IConfiguration ; ///< Index of string descriptor + uint8_t iConfiguration ; ///< Index of string descriptor uint8_t bmAttributes ; ///< Same as Configuration descriptor uint8_t bMaxPower ; ///< Same as Configuration descriptor } tusb_desc_other_speed_t; @@ -387,11 +387,14 @@ typedef struct TU_ATTR_PACKED uint8_t bDeviceClass ; ///< Class Code uint8_t bDeviceSubClass ; ///< SubClass Code uint8_t bDeviceProtocol ; ///< Protocol Code + uint8_t bMaxPacketSize0 ; ///< Maximum packet size for other speed uint8_t bNumConfigurations ; ///< Number of Other-speed Configurations uint8_t bReserved ; ///< Reserved for future use, must be zero } tusb_desc_device_qualifier_t; +TU_VERIFY_STATIC( sizeof(tusb_desc_device_qualifier_t) == 10, "size is not correct"); + /// USB Interface Association Descriptor (IAD ECN) typedef struct TU_ATTR_PACKED { diff --git a/src/device/usbd.c b/src/device/usbd.c index a52ea9afe..58b3a5701 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -1002,10 +1002,22 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const break; case TUSB_DESC_CONFIGURATION: + case TUSB_DESC_OTHER_SPEED_CONFIG: { - TU_LOG2(" Configuration[%u]\r\n", desc_index); + tusb_desc_configuration_t const* desc_config; + + if ( desc_type == TUSB_DESC_CONFIGURATION ) + { + TU_LOG2(" Configuration[%u]\r\n", desc_index); + desc_config = (tusb_desc_configuration_t const*) tud_descriptor_configuration_cb(desc_index); + }else + { + // Host only request this after getting Device Qualifier descriptor + TU_LOG2(" Other Speed Configuration\r\n"); + TU_VERIFY( tud_descriptor_other_speed_configuration_cb ); + desc_config = (tusb_desc_configuration_t const*) tud_descriptor_other_speed_configuration_cb(desc_index); + } - tusb_desc_configuration_t const* desc_config = (tusb_desc_configuration_t const*) tud_descriptor_configuration_cb(desc_index); TU_ASSERT(desc_config); // Use offsetof to avoid pointer to the odd/misaligned address @@ -1031,27 +1043,13 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const case TUSB_DESC_DEVICE_QUALIFIER: TU_LOG2(" Device Qualifier\r\n"); - // Host sends this request to ask why our device with USB BCD from 2.0 - // but is running at Full/Low Speed. If not highspeed capable stall this request, - // otherwise return the descriptor that could work in highspeed mode - if ( tud_descriptor_device_qualifier_cb ) - { - uint8_t const* desc_qualifier = tud_descriptor_device_qualifier_cb(); - TU_ASSERT(desc_qualifier); + TU_VERIFY( tud_descriptor_device_qualifier_cb ); - // first byte of descriptor is its size - return tud_control_xfer(rhport, p_request, (void*) desc_qualifier, desc_qualifier[0]); - }else - { - return false; - } - break; + uint8_t const* desc_qualifier = tud_descriptor_device_qualifier_cb(); + TU_VERIFY(desc_qualifier); - case TUSB_DESC_OTHER_SPEED_CONFIG: - TU_LOG2(" Other Speed Configuration\r\n"); - - // After Device Qualifier descriptor is received host will ask for this descriptor - return false; // not supported + // first byte of descriptor is its size + return tud_control_xfer(rhport, p_request, (void*) desc_qualifier, desc_qualifier[0]); break; default: return false; diff --git a/src/device/usbd.h b/src/device/usbd.h index 9becf2d0d..638d93094 100644 --- a/src/device/usbd.h +++ b/src/device/usbd.h @@ -113,9 +113,16 @@ uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid); TU_ATTR_WEAK uint8_t const * tud_descriptor_bos_cb(void); // Invoked when received GET DEVICE QUALIFIER DESCRIPTOR request -// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete +// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete. +// device_qualifier descriptor describes information about a high-speed capable device that would +// change if the device were operating at the other speed. If not highspeed capable stall this request. TU_ATTR_WEAK uint8_t const* tud_descriptor_device_qualifier_cb(void); +// Invoked when received GET OTHER SEED CONFIGURATION DESCRIPTOR request +// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete +// Configuration descriptor in the other speed e.g if high speed then this is for full speed and vice versa +TU_ATTR_WEAK uint8_t const* tud_descriptor_other_speed_configuration_cb(uint8_t index); + // Invoked when device is mounted (configured) TU_ATTR_WEAK void tud_mount_cb(void); -- cgit v1.3.1 From 27800f7e4f39c856d2fe82e6320e855d8c283518 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 9 Sep 2021 16:01:05 +0700 Subject: remove connected check for DCD_EVENT_UNPLUGGED since previous bus reset can clear this implement unplugged detection for trans dimension dcd --- src/device/usbd.c | 14 ++++------- .../nxp/transdimension/dcd_transdimension.c | 28 ++++++++++++---------- 2 files changed, 20 insertions(+), 22 deletions(-) diff --git a/src/device/usbd.c b/src/device/usbd.c index 58b3a5701..4ab60569b 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -1064,15 +1064,11 @@ void dcd_event_handler(dcd_event_t const * event, bool in_isr) switch (event->event_id) { case DCD_EVENT_UNPLUGGED: - // UNPLUGGED event can be bouncing, only processing if we are currently connected - if ( _usbd_dev.connected ) - { - _usbd_dev.connected = 0; - _usbd_dev.addressed = 0; - _usbd_dev.cfg_num = 0; - _usbd_dev.suspended = 0; - osal_queue_send(_usbd_q, event, in_isr); - } + _usbd_dev.connected = 0; + _usbd_dev.addressed = 0; + _usbd_dev.cfg_num = 0; + _usbd_dev.suspended = 0; + osal_queue_send(_usbd_q, event, in_isr); break; case DCD_EVENT_SUSPEND: diff --git a/src/portable/nxp/transdimension/dcd_transdimension.c b/src/portable/nxp/transdimension/dcd_transdimension.c index 42047ef92..da766afa1 100644 --- a/src/portable/nxp/transdimension/dcd_transdimension.c +++ b/src/portable/nxp/transdimension/dcd_transdimension.c @@ -245,7 +245,7 @@ void dcd_init(uint8_t rhport) dcd_reg->ENDPTLISTADDR = (uint32_t) _dcd_data.qhd; // Endpoint List Address has to be 2K alignment dcd_reg->USBSTS = dcd_reg->USBSTS; - dcd_reg->USBINTR = INTR_USB | INTR_ERROR | INTR_PORT_CHANGE | INTR_RESET | INTR_SUSPEND /*| INTR_SOF*/; + dcd_reg->USBINTR = INTR_USB | INTR_ERROR | INTR_PORT_CHANGE | INTR_RESET | INTR_SUSPEND; dcd_reg->USBCMD &= ~0x00FF0000; // Interrupt Threshold Interval = 0 dcd_reg->USBCMD |= USBCMD_RUN_STOP; // Connect @@ -272,7 +272,9 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr) void dcd_remote_wakeup(uint8_t rhport) { - (void) rhport; + dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; + (void) dcd_reg; +// dcd_reg->PORTSC1 = } void dcd_connect(uint8_t rhport) @@ -412,7 +414,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t //--------------------------------------------------------------------+ void dcd_int_handler(uint8_t rhport) { - dcd_registers_t* const dcd_reg = _dcd_controller[rhport].regs; + dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; uint32_t const int_enable = dcd_reg->USBINTR; uint32_t const int_status = dcd_reg->USBSTS & int_enable; @@ -433,6 +435,7 @@ void dcd_int_handler(uint8_t rhport) if (dcd_reg->PORTSC1 & PORTSC1_SUSPEND) { // Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration. + // Skip suspend event if we are not addressed if ((dcd_reg->DEVICEADDR >> 25) & 0x0f) { dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); @@ -440,19 +443,18 @@ void dcd_int_handler(uint8_t rhport) } } + // Set if the port controller enters the full or high-speed operational state. + if (int_status & INTR_PORT_CHANGE) + { + if ( !(dcd_reg->PORTSC1 & PORTSC1_CURRENT_CONNECT_STATUS) ) + { + dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true); + } + } + // Make sure we read the latest version of _dcd_data. CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t)); - // TODO disconnection does not generate interrupt !!!!!! -// if (int_status & INTR_PORT_CHANGE) -// { -// if ( !(dcd_reg->PORTSC1 & PORTSC1_CURRENT_CONNECT_STATUS) ) -// { -// dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_UNPLUGGED }; -// dcd_event_handler(&event, true); -// } -// } - if (int_status & INTR_USB) { uint32_t const edpt_complete = dcd_reg->ENDPTCOMPLETE; -- cgit v1.3.1 From f948cbe4710c800cd168de793cc1c4fb80a55dd7 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 9 Sep 2021 17:04:04 +0700 Subject: nxp tdi implement remote wakeup enhance bus reset, unplugged, suspend, resume detection --- .../nxp/transdimension/dcd_transdimension.c | 53 ++++++++++++++-------- 1 file changed, 35 insertions(+), 18 deletions(-) diff --git a/src/portable/nxp/transdimension/dcd_transdimension.c b/src/portable/nxp/transdimension/dcd_transdimension.c index da766afa1..4a8205162 100644 --- a/src/portable/nxp/transdimension/dcd_transdimension.c +++ b/src/portable/nxp/transdimension/dcd_transdimension.c @@ -245,7 +245,7 @@ void dcd_init(uint8_t rhport) dcd_reg->ENDPTLISTADDR = (uint32_t) _dcd_data.qhd; // Endpoint List Address has to be 2K alignment dcd_reg->USBSTS = dcd_reg->USBSTS; - dcd_reg->USBINTR = INTR_USB | INTR_ERROR | INTR_PORT_CHANGE | INTR_RESET | INTR_SUSPEND; + dcd_reg->USBINTR = INTR_USB | INTR_ERROR | INTR_PORT_CHANGE | INTR_SUSPEND; dcd_reg->USBCMD &= ~0x00FF0000; // Interrupt Threshold Interval = 0 dcd_reg->USBCMD |= USBCMD_RUN_STOP; // Connect @@ -273,8 +273,7 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr) void dcd_remote_wakeup(uint8_t rhport) { dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; - (void) dcd_reg; -// dcd_reg->PORTSC1 = + dcd_reg->PORTSC1 |= PORTSC1_FORCE_PORT_RESUME; } void dcd_connect(uint8_t rhport) @@ -423,15 +422,42 @@ void dcd_int_handler(uint8_t rhport) // disabled interrupt sources if (int_status == 0) return; - if (int_status & INTR_RESET) - { - bus_reset(rhport); - uint32_t speed = (dcd_reg->PORTSC1 & PORTSC1_PORT_SPEED) >> PORTSC1_PORT_SPEED_POS; - dcd_event_bus_reset(rhport, (tusb_speed_t) speed, true); - } + // Set if the port controller enters the full or high-speed operational state. + // either from Bus Reset or Suspended state + if (int_status & INTR_PORT_CHANGE) + { + // TU_LOG2("PortChange %08lx\r\n", dcd_reg->PORTSC1); + + // Reset interrupt is not enabled, we manually check if Port Change is due + // to connection / disconnection + if ( dcd_reg->USBSTS & INTR_RESET ) + { + dcd_reg->USBSTS = INTR_RESET; + + if (dcd_reg->PORTSC1 & PORTSC1_CURRENT_CONNECT_STATUS) + { + uint32_t const speed = (dcd_reg->PORTSC1 & PORTSC1_PORT_SPEED) >> PORTSC1_PORT_SPEED_POS; + bus_reset(rhport); + dcd_event_bus_reset(rhport, (tusb_speed_t) speed, true); + }else + { + dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true); + } + } + else + { + // Triggered by resuming from suspended state + if ( !(dcd_reg->PORTSC1 & PORTSC1_SUSPEND) ) + { + dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true); + } + } + } if (int_status & INTR_SUSPEND) { + // TU_LOG2("Suspend %08lx\r\n", dcd_reg->PORTSC1); + if (dcd_reg->PORTSC1 & PORTSC1_SUSPEND) { // Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration. @@ -443,15 +469,6 @@ void dcd_int_handler(uint8_t rhport) } } - // Set if the port controller enters the full or high-speed operational state. - if (int_status & INTR_PORT_CHANGE) - { - if ( !(dcd_reg->PORTSC1 & PORTSC1_CURRENT_CONNECT_STATUS) ) - { - dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true); - } - } - // Make sure we read the latest version of _dcd_data. CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t)); -- cgit v1.3.1 From ad8c0ee8182f6c6120bf8124dbdcd2883f285f8f Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 9 Sep 2021 20:26:03 +0700 Subject: nxp tdi: enhance qhd using DCD_ATTR_ENDPOINT_MAX --- src/common/tusb_common.h | 2 +- .../nxp/transdimension/dcd_transdimension.c | 87 +++++++++++----------- 2 files changed, 44 insertions(+), 45 deletions(-) diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h index 687f980be..d0cc41285 100644 --- a/src/common/tusb_common.h +++ b/src/common/tusb_common.h @@ -372,7 +372,7 @@ typedef struct static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint32_t key) { - static char not_found[10]; + static char not_found[11]; for(uint16_t i=0; icount; i++) { diff --git a/src/portable/nxp/transdimension/dcd_transdimension.c b/src/portable/nxp/transdimension/dcd_transdimension.c index 4a8205162..35f824112 100644 --- a/src/portable/nxp/transdimension/dcd_transdimension.c +++ b/src/portable/nxp/transdimension/dcd_transdimension.c @@ -145,10 +145,6 @@ typedef struct }dcd_controller_t; #if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX - // Each endpoint with direction (IN/OUT) occupies a queue head - // Therefore QHD_MAX is 2 x max endpoint count - #define QHD_MAX (8*2) - static const dcd_controller_t _dcd_controller[] = { // RT1010 and RT1020 only has 1 USB controller @@ -161,8 +157,6 @@ typedef struct }; #else - #define QHD_MAX (6*2) - static const dcd_controller_t _dcd_controller[] = { { .regs = (dcd_registers_t*) LPC_USB0_BASE, .irqnum = USB0_IRQn, .ep_count = 6 }, @@ -174,8 +168,10 @@ typedef struct typedef struct { // Must be at 2K alignment - dcd_qhd_t qhd[QHD_MAX] TU_ATTR_ALIGNED(64); - dcd_qtd_t qtd[QHD_MAX] TU_ATTR_ALIGNED(32); // for portability, TinyUSB only queue 1 TD for each Qhd + // Each endpoint with direction (IN/OUT) occupies a queue head + // for portability, TinyUSB only queue 1 TD for each Qhd + dcd_qhd_t qhd[DCD_ATTR_ENDPOINT_MAX][2] TU_ATTR_ALIGNED(64); + dcd_qtd_t qtd[DCD_ATTR_ENDPOINT_MAX][2] TU_ATTR_ALIGNED(32); }dcd_data_t; CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(2048) @@ -217,11 +213,11 @@ static void bus_reset(uint8_t rhport) tu_memclr(&_dcd_data, sizeof(dcd_data_t)); //------------- Set up Control Endpoints (0 OUT, 1 IN) -------------// - _dcd_data.qhd[0].zero_length_termination = _dcd_data.qhd[1].zero_length_termination = 1; - _dcd_data.qhd[0].max_package_size = _dcd_data.qhd[1].max_package_size = CFG_TUD_ENDPOINT0_SIZE; - _dcd_data.qhd[0].qtd_overlay.next = _dcd_data.qhd[1].qtd_overlay.next = QTD_NEXT_INVALID; + _dcd_data.qhd[0][0].zero_length_termination = _dcd_data.qhd[0][1].zero_length_termination = 1; + _dcd_data.qhd[0][0].max_package_size = _dcd_data.qhd[0][1].max_package_size = CFG_TUD_ENDPOINT0_SIZE; + _dcd_data.qhd[0][0].qtd_overlay.next = _dcd_data.qhd[0][1].qtd_overlay.next = QTD_NEXT_INVALID; - _dcd_data.qhd[0].int_on_setup = 1; // OUT only + _dcd_data.qhd[0][0].int_on_setup = 1; // OUT only } void dcd_init(uint8_t rhport) @@ -291,11 +287,6 @@ void dcd_disconnect(uint8_t rhport) //--------------------------------------------------------------------+ // HELPER //--------------------------------------------------------------------+ -// index to bit position in register -static inline uint8_t ep_idx2bit(uint8_t ep_idx) -{ - return ep_idx/2 + ( (ep_idx%2) ? 16 : 0); -} static void qtd_init(dcd_qtd_t* p_qtd, void * data_ptr, uint16_t total_bytes) { @@ -325,12 +316,15 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; dcd_reg->ENDPTCTRL[epnum] |= ENDPTCTRL_STALL << (dir ? 16 : 0); + + // flush to abort any primed buffer + dcd_reg->ENDPTFLUSH = TU_BIT(epnum + (dir ? 16 : 0)); } void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); // data toggle also need to be reset dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; @@ -343,15 +337,14 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) // TODO not support ISO yet TU_VERIFY ( p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS); - uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress); - uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress); - uint8_t const ep_idx = 2*epnum + dir; + uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress); + uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress); // Must not exceed max endpoint number TU_ASSERT( epnum < _dcd_controller[rhport].ep_count ); //------------- Prepare Queue Head -------------// - dcd_qhd_t * p_qhd = &_dcd_data.qhd[ep_idx]; + dcd_qhd_t * p_qhd = &_dcd_data.qhd[epnum][dir]; tu_memclr(p_qhd, sizeof(dcd_qhd_t)); p_qhd->zero_length_termination = 1; @@ -378,7 +371,6 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); - uint8_t const ep_idx = 2*epnum + dir; if ( epnum == 0 ) { @@ -387,8 +379,8 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t while(dcd_reg->ENDPTSETUPSTAT & TU_BIT(0)) {} } - dcd_qhd_t * p_qhd = &_dcd_data.qhd[ep_idx]; - dcd_qtd_t * p_qtd = &_dcd_data.qtd[ep_idx]; + dcd_qhd_t * p_qhd = &_dcd_data.qhd[epnum][dir]; + dcd_qtd_t * p_qtd = &_dcd_data.qtd[epnum][dir]; // Force the CPU to flush the buffer. We increase the size by 32 because the call aligns the // address to 32-byte boundaries. @@ -403,7 +395,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t)); // start transfer - dcd_reg->ENDPTPRIME = TU_BIT( ep_idx2bit(ep_idx) ) ; + dcd_reg->ENDPTPRIME = TU_BIT(epnum + (dir ? 16 : 0)); return true; } @@ -411,6 +403,18 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t //--------------------------------------------------------------------+ // ISR //--------------------------------------------------------------------+ + +static void process_edpt_complete_isr(uint8_t rhport, uint8_t ep_num, uint8_t dir) +{ + dcd_qtd_t * p_qtd = &_dcd_data.qtd[ep_num][dir]; + + uint8_t result = p_qtd->halted ? XFER_RESULT_STALLED : + ( p_qtd->xact_err || p_qtd->buffer_err ) ? XFER_RESULT_FAILED : XFER_RESULT_SUCCESS; + + // only number of bytes in the IOC qtd + dcd_event_xfer_complete(rhport, tu_edpt_addr(ep_num, dir), p_qtd->expected_bytes - p_qtd->total_bytes, result, true); +} + void dcd_int_handler(uint8_t rhport) { dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; @@ -481,26 +485,24 @@ void dcd_int_handler(uint8_t rhport) { //------------- Set up Received -------------// // 23.10.10.2 Operational model for setup transfers - dcd_reg->ENDPTSETUPSTAT = dcd_reg->ENDPTSETUPSTAT;// acknowledge + dcd_reg->ENDPTSETUPSTAT = dcd_reg->ENDPTSETUPSTAT; - dcd_event_setup_received(rhport, (uint8_t*) &_dcd_data.qhd[0].setup_request, true); + dcd_event_setup_received(rhport, (uint8_t*) &_dcd_data.qhd[0][0].setup_request, true); + } + + // 23.10.12.3 Failed QTD also get ENDPTCOMPLETE set + if (int_status & INTR_ERROR) + { + TU_LOG_HEX(1, int_status); + TU_LOG_HEX(1, edpt_complete); } if ( edpt_complete ) { - for(uint8_t ep_idx = 0; ep_idx < QHD_MAX; ep_idx++) + for(uint8_t ep_num = 0; ep_num < DCD_ATTR_ENDPOINT_MAX; ep_num++) { - if ( tu_bit_test(edpt_complete, ep_idx2bit(ep_idx)) ) - { - // 23.10.12.3 Failed QTD also get ENDPTCOMPLETE set - dcd_qtd_t * p_qtd = &_dcd_data.qtd[ep_idx]; - - uint8_t result = p_qtd->halted ? XFER_RESULT_STALLED : - ( p_qtd->xact_err ||p_qtd->buffer_err ) ? XFER_RESULT_FAILED : XFER_RESULT_SUCCESS; - - uint8_t const ep_addr = (ep_idx/2) | ( (ep_idx & 0x01) ? TUSB_DIR_IN_MASK : 0 ); - dcd_event_xfer_complete(rhport, ep_addr, p_qtd->expected_bytes - p_qtd->total_bytes, result, true); // only number of bytes in the IOC qtd - } + if ( tu_bit_test(edpt_complete, ep_num) ) process_edpt_complete_isr(rhport, ep_num, TUSB_DIR_OUT); + if ( tu_bit_test(edpt_complete, ep_num+16) ) process_edpt_complete_isr(rhport, ep_num, TUSB_DIR_IN); } } } @@ -509,9 +511,6 @@ void dcd_int_handler(uint8_t rhport) { dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true); } - - if (int_status & INTR_NAK) {} - if (int_status & INTR_ERROR) TU_ASSERT(false, ); } #endif -- cgit v1.3.1 From 283783c082d2253984066cb475714217c63454d6 Mon Sep 17 00:00:00 2001 From: Mengsk Date: Thu, 9 Sep 2021 16:45:18 +0200 Subject: dcd_edpt_xfer_fifo: use qtd_init if restriction not met. --- src/portable/nxp/transdimension/dcd_transdimension.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/src/portable/nxp/transdimension/dcd_transdimension.c b/src/portable/nxp/transdimension/dcd_transdimension.c index a4d6c5d48..0a18e711e 100644 --- a/src/portable/nxp/transdimension/dcd_transdimension.c +++ b/src/portable/nxp/transdimension/dcd_transdimension.c @@ -494,7 +494,7 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16 tu_fifo_get_write_info(ff, &fifo_info); } - if(total_bytes <= fifo_info.len_lin) + if (total_bytes <= fifo_info.len_lin) { // Limit transfer length to total_bytes fifo_info.len_wrap = 0; @@ -508,12 +508,20 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16 // address to 32-byte boundaries. // void* cast to suppress cast-align warning, buffer must be CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) fifo_info.ptr_lin, 4), fifo_info.len_lin + 31); - if (fifo_info.len_wrap > 0) + + //------------- Prepare qtd -------------// + + // In case of : wrapped part is present & buffer is aligned to 4k & buffer size is multiple of 4k + if (total_bytes > fifo_info.len_lin && (uint32_t)fifo_info.ptr_wrap == tu_align4k((uint32_t)fifo_info.ptr_wrap) && tu_fifo_depth(ff) == tu_align4k(tu_fifo_depth(ff))) { - CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) fifo_info.ptr_wrap, 4), fifo_info.len_wrap + 31); + CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) fifo_info.ptr_wrap, 4), fifo_info.len_wrap + 31); + qtd_init_fifo(p_qtd, &fifo_info, total_bytes); } - //------------- Prepare qtd -------------// - qtd_init_fifo(p_qtd, &fifo_info, total_bytes); + else + { + qtd_init(p_qtd, fifo_info.ptr_lin, total_bytes); + } + p_qtd->int_on_complete = true; p_qhd->qtd_overlay.next = (uint32_t) p_qtd; // link qtd to qhd p_qhd->ff = ff; -- cgit v1.3.1 From d7238d9a86901f0da77c8a08330eb647e6ea912b Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Fri, 10 Sep 2021 00:13:29 +0900 Subject: Remove heap memory area --- hw/bsp/frdm_kl25z/board.mk | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/bsp/frdm_kl25z/board.mk b/hw/bsp/frdm_kl25z/board.mk index 451bc37c2..bc9240e55 100644 --- a/hw/bsp/frdm_kl25z/board.mk +++ b/hw/bsp/frdm_kl25z/board.mk @@ -8,8 +8,12 @@ CFLAGS += \ -DCPU_MKL25Z128VLK4 \ -DCFG_TUSB_MCU=OPT_MCU_MKL25ZXX +LDFLAGS += \ + -Wl,--defsym,__stack_size__=0x400 \ + -Wl,--defsym,__heap_size__=0 + # mcu driver cause following warnings -CFLAGS += -Wno-error=unused-parameter +CFLAGS += -Wno-error=unused-parameter -Wno-error=format MCU_DIR = $(SDK_DIR)/devices/MKL25Z4 -- cgit v1.3.1 From 2998f67eacfb007806198a7d91cc1623ee966c2c Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Fri, 10 Sep 2021 00:18:43 +0900 Subject: Fix dcd_edpt_clear_stall to reset data toggle --- src/portable/nxp/khci/dcd_khci.c | 30 +++++++++++++++++++----------- 1 file changed, 19 insertions(+), 11 deletions(-) diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c index 0ddd0f75e..2ba063ff2 100644 --- a/src/portable/nxp/khci/dcd_khci.c +++ b/src/portable/nxp/khci/dcd_khci.c @@ -323,7 +323,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) const unsigned xfer = ep_desc->bmAttributes.xfer; endpoint_state_t *ep = &_dcd.endpoint[epn][dir]; const unsigned odd = ep->odd; - buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][0]; + buffer_descriptor_t *bd = _dcd.bdt[epn][dir]; /* No support for control transfer */ TU_ASSERT(epn && (xfer != TUSB_XFER_CONTROL)); @@ -373,13 +373,17 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) const unsigned epn = tu_edpt_number(ep_addr); const unsigned dir = tu_edpt_dir(ep_addr); endpoint_state_t *ep = &_dcd.endpoint[epn][dir]; - buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][0]; + buffer_descriptor_t *bd = _dcd.bdt[epn][dir]; const unsigned msk = dir ? USB_ENDPT_EPTXEN_MASK : USB_ENDPT_EPRXEN_MASK; + const unsigned ie = NVIC_GetEnableIRQ(USB0_IRQn); + NVIC_DisableIRQ(USB0_IRQn); KHCI->ENDPOINT[epn].ENDPT &= ~msk; ep->max_packet_size = 0; ep->length = 0; ep->remaining = 0; - bd->head = 0; + bd[0].head = 0; + bd[1].head = 0; + if (ie) NVIC_EnableIRQ(USB0_IRQn); } bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) @@ -422,9 +426,9 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) KHCI->ENDPOINT[epn].ENDPT |= USB_ENDPT_EPSTALL_MASK; } else { const unsigned dir = tu_edpt_dir(ep_addr); - endpoint_state_t *ep = &_dcd.endpoint[epn][dir]; - buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][ep->odd]; - TU_ASSERT(0 == bd->own,); + const unsigned odd = _dcd.endpoint[epn][dir].odd; + buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][odd]; + TU_VERIFY(0 == bd->own,); const unsigned ie = NVIC_GetEnableIRQ(USB0_IRQn); NVIC_DisableIRQ(USB0_IRQn); bd->bdt_stall = 1; @@ -440,14 +444,18 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) const unsigned epn = tu_edpt_number(ep_addr); TU_VERIFY(epn,); const unsigned dir = tu_edpt_dir(ep_addr); - endpoint_state_t *ep = &_dcd.endpoint[epn][dir]; - buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][ep->odd]; - TU_ASSERT(bd->own,); + const unsigned odd = _dcd.endpoint[epn][dir].odd; + buffer_descriptor_t *bd = _dcd.bdt[epn][dir]; + TU_VERIFY(bd[odd].own,); const unsigned ie = NVIC_GetEnableIRQ(USB0_IRQn); NVIC_DisableIRQ(USB0_IRQn); - bd->own = 0; + bd[odd].own = 0; __DSB(); - bd->bdt_stall = 0; + bd[odd].bdt_stall = 0; + if (bd[odd].data) { + bd[odd ].data = 0; + bd[odd ^ 1].data = 1; + } if (ie) NVIC_EnableIRQ(USB0_IRQn); } -- cgit v1.3.1 From 580893b3fe802d0aaeefa6c851dda828289c806c Mon Sep 17 00:00:00 2001 From: MasterPhi Date: Fri, 10 Sep 2021 11:17:33 +0200 Subject: Shorter expr. --- src/portable/nxp/transdimension/dcd_transdimension.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/portable/nxp/transdimension/dcd_transdimension.c b/src/portable/nxp/transdimension/dcd_transdimension.c index 0a18e711e..d669791dc 100644 --- a/src/portable/nxp/transdimension/dcd_transdimension.c +++ b/src/portable/nxp/transdimension/dcd_transdimension.c @@ -512,7 +512,7 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16 //------------- Prepare qtd -------------// // In case of : wrapped part is present & buffer is aligned to 4k & buffer size is multiple of 4k - if (total_bytes > fifo_info.len_lin && (uint32_t)fifo_info.ptr_wrap == tu_align4k((uint32_t)fifo_info.ptr_wrap) && tu_fifo_depth(ff) == tu_align4k(tu_fifo_depth(ff))) + if (total_bytes > fifo_info.len_lin && !tu_offset4k((uint32_t)fifo_info.ptr_wrap) && !tu_offset4k(tu_fifo_depth(ff))) { CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) fifo_info.ptr_wrap, 4), fifo_info.len_wrap + 31); qtd_init_fifo(p_qtd, &fifo_info, total_bytes); -- cgit v1.3.1 From 8886de0d8a14daa70d1fcf4101e3fdeda12a1b26 Mon Sep 17 00:00:00 2001 From: MasterPhi Date: Fri, 10 Sep 2021 13:05:15 +0200 Subject: Fix remote_wakeup --- src/portable/nuvoton/nuc121/dcd_nuc121.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/src/portable/nuvoton/nuc121/dcd_nuc121.c b/src/portable/nuvoton/nuc121/dcd_nuc121.c index 7edafe5d3..d101550b6 100644 --- a/src/portable/nuvoton/nuc121/dcd_nuc121.c +++ b/src/portable/nuvoton/nuc121/dcd_nuc121.c @@ -252,10 +252,23 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr) // do it at dcd_edpt0_status_complete() } +static void remote_wakeup_delay(void) +{ + // try to delay for 1 ms + uint32_t count = SystemCoreClock / 1000; + while(count--) __NOP(); +} + void dcd_remote_wakeup(uint8_t rhport) { (void) rhport; - USBD->ATTR = USBD_ATTR_RWAKEUP_Msk; + // Enable PHY before sending Resume('K') state + USBD->ATTR |= USBD_ATTR_PHYEN_Msk; + USBD->ATTR |= USBD_ATTR_RWAKEUP_Msk; + + // Per specs: remote wakeup signal bit must be clear within 1-15ms + remote_wakeup_delay(); + USBD->ATTR &=~USBD_ATTR_RWAKEUP_Msk; } bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) @@ -374,7 +387,8 @@ void dcd_int_handler(uint8_t rhport) { (void) rhport; - uint32_t status = USBD->INTSTS; + // Mask non-enabled irqs, ex. SOF + uint32_t status = USBD->INTSTS & (enabled_irqs | 0xffffff00); #ifdef SUPPORT_LPM uint32_t state = USBD->ATTR & 0x300f; #else -- cgit v1.3.1 From 22571ec98ef89a76239b27c86cbdac3db3c42f09 Mon Sep 17 00:00:00 2001 From: MasterPhi Date: Fri, 10 Sep 2021 16:04:47 +0200 Subject: reset PID to DATA0 on clear_stall. --- src/portable/nuvoton/nuc121/dcd_nuc121.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/portable/nuvoton/nuc121/dcd_nuc121.c b/src/portable/nuvoton/nuc121/dcd_nuc121.c index d101550b6..5dfc77bb7 100644 --- a/src/portable/nuvoton/nuc121/dcd_nuc121.c +++ b/src/portable/nuvoton/nuc121/dcd_nuc121.c @@ -381,6 +381,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) (void) rhport; USBD_EP_T *ep = ep_entry(ep_addr, false); ep->CFG |= USBD_CFG_CSTALL_Msk; + ep->CFG &=~USBD_CFG_DSQSYNC_Msk; } void dcd_int_handler(uint8_t rhport) -- cgit v1.3.1 From 1f7ade2b751d899a73e58c2b7f0d17a00dbf6899 Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 11 Sep 2021 19:27:37 +0700 Subject: nxp tdi: fix error td prevent further transfer --- .../nxp/transdimension/dcd_transdimension.c | 54 +++++++++++++--------- 1 file changed, 31 insertions(+), 23 deletions(-) diff --git a/src/portable/nxp/transdimension/dcd_transdimension.c b/src/portable/nxp/transdimension/dcd_transdimension.c index 35f824112..ee1a50db3 100644 --- a/src/portable/nxp/transdimension/dcd_transdimension.c +++ b/src/portable/nxp/transdimension/dcd_transdimension.c @@ -91,12 +91,15 @@ typedef struct uint32_t : 3 ; uint32_t int_on_complete : 1 ; volatile uint32_t total_bytes : 15 ; - uint32_t : 0 ; + uint32_t : 1 ; // Word 2-6: Buffer Page Pointer List, Each element in the list is a 4K page aligned, physical memory address. The lower 12 bits in each pointer are reserved (except for the first one) as each memory pointer must reference the start of a 4K page uint32_t buffer[5]; ///< buffer1 has frame_n for TODO Isochronous - //------------- DCD Area -------------// + //--------------------------------------------------------------------+ + // TD is 32 bytes aligned but occupies only 28 bytes + // Therefore there are 4 bytes padding that we can use. + //--------------------------------------------------------------------+ uint16_t expected_bytes; uint8_t reserved[2]; } dcd_qtd_t; @@ -109,11 +112,10 @@ typedef struct // Word 0: Capabilities and Characteristics uint32_t : 15 ; ///< Number of packets executed per transaction descriptor 00 - Execute N transactions as demonstrated by the USB variable length protocol where N is computed using Max_packet_length and the Total_bytes field in the dTD. 01 - Execute one transaction 10 - Execute two transactions 11 - Execute three transactions Remark: Non-isochronous endpoints must set MULT = 00. Remark: Isochronous endpoints must set MULT = 01, 10, or 11 as needed. uint32_t int_on_setup : 1 ; ///< Interrupt on setup This bit is used on control type endpoints to indicate if USBINT is set in response to a setup being received. - uint32_t max_package_size : 11 ; ///< This directly corresponds to the maximum packet size of the associated endpoint (wMaxPacketSize) + uint32_t max_packet_size : 11 ; ///< Endpoint's wMaxPacketSize uint32_t : 2 ; uint32_t zero_length_termination : 1 ; ///< This bit is used for non-isochronous endpoints to indicate when a zero-length packet is received to terminate transfers in case the total transfer length is “multiple”. 0 - Enable zero-length packet to terminate transfers equal to a multiple of Max_packet_length (default). 1 - Disable zero-length packet on transfers that are equal in length to a multiple Max_packet_length. uint32_t iso_mult : 2 ; ///< - uint32_t : 0 ; // Word 1: Current qTD Pointer volatile uint32_t qtd_addr; @@ -125,8 +127,8 @@ typedef struct volatile tusb_control_request_t setup_request; //--------------------------------------------------------------------+ - /// Due to the fact QHD is 64 bytes aligned but occupies only 48 bytes - /// thus there are 16 bytes padding free that we can make use of. + // QHD is 64 bytes aligned but occupies only 48 bytes + // Therefore there are 16 bytes padding that we can use. //--------------------------------------------------------------------+ uint8_t reserved[16]; } dcd_qhd_t; @@ -214,7 +216,7 @@ static void bus_reset(uint8_t rhport) //------------- Set up Control Endpoints (0 OUT, 1 IN) -------------// _dcd_data.qhd[0][0].zero_length_termination = _dcd_data.qhd[0][1].zero_length_termination = 1; - _dcd_data.qhd[0][0].max_package_size = _dcd_data.qhd[0][1].max_package_size = CFG_TUD_ENDPOINT0_SIZE; + _dcd_data.qhd[0][0].max_packet_size = _dcd_data.qhd[0][1].max_packet_size = CFG_TUD_ENDPOINT0_SIZE; _dcd_data.qhd[0][0].qtd_overlay.next = _dcd_data.qhd[0][1].qtd_overlay.next = QTD_NEXT_INVALID; _dcd_data.qhd[0][0].int_on_setup = 1; // OUT only @@ -348,7 +350,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) tu_memclr(p_qhd, sizeof(dcd_qhd_t)); p_qhd->zero_length_termination = 1; - p_qhd->max_package_size = p_endpoint_desc->wMaxPacketSize.size; + p_qhd->max_packet_size = p_endpoint_desc->wMaxPacketSize.size; p_qhd->qtd_overlay.next = QTD_NEXT_INVALID; CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t)); @@ -390,7 +392,9 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t //------------- Prepare qtd -------------// qtd_init(p_qtd, buffer, total_bytes); p_qtd->int_on_complete = true; - p_qhd->qtd_overlay.next = (uint32_t) p_qtd; // link qtd to qhd + + p_qhd->qtd_overlay.halted = false; // clear any previous error + p_qhd->qtd_overlay.next = (uint32_t) p_qtd; // activate by linking qtd to qhd CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t)); @@ -404,15 +408,22 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t // ISR //--------------------------------------------------------------------+ -static void process_edpt_complete_isr(uint8_t rhport, uint8_t ep_num, uint8_t dir) +static void process_edpt_complete_isr(uint8_t rhport, uint8_t epnum, uint8_t dir) { - dcd_qtd_t * p_qtd = &_dcd_data.qtd[ep_num][dir]; + dcd_qtd_t * p_qtd = &_dcd_data.qtd[epnum][dir]; uint8_t result = p_qtd->halted ? XFER_RESULT_STALLED : ( p_qtd->xact_err || p_qtd->buffer_err ) ? XFER_RESULT_FAILED : XFER_RESULT_SUCCESS; + if ( result != XFER_RESULT_SUCCESS ) + { + dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; + // flush to abort error buffer + dcd_reg->ENDPTFLUSH = TU_BIT(epnum + (dir ? 16 : 0)); + } + // only number of bytes in the IOC qtd - dcd_event_xfer_complete(rhport, tu_edpt_addr(ep_num, dir), p_qtd->expected_bytes - p_qtd->total_bytes, result, true); + dcd_event_xfer_complete(rhport, tu_edpt_addr(epnum, dir), p_qtd->expected_bytes - p_qtd->total_bytes, result, true); } void dcd_int_handler(uint8_t rhport) @@ -473,11 +484,11 @@ void dcd_int_handler(uint8_t rhport) } } - // Make sure we read the latest version of _dcd_data. - CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t)); - if (int_status & INTR_USB) { + // Make sure we read the latest version of _dcd_data. + CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t)); + uint32_t const edpt_complete = dcd_reg->ENDPTCOMPLETE; dcd_reg->ENDPTCOMPLETE = edpt_complete; // acknowledge @@ -491,18 +502,15 @@ void dcd_int_handler(uint8_t rhport) } // 23.10.12.3 Failed QTD also get ENDPTCOMPLETE set - if (int_status & INTR_ERROR) - { - TU_LOG_HEX(1, int_status); - TU_LOG_HEX(1, edpt_complete); - } + // nothing to do, we will submit xfer as error to usbd + // if (int_status & INTR_ERROR) { } if ( edpt_complete ) { - for(uint8_t ep_num = 0; ep_num < DCD_ATTR_ENDPOINT_MAX; ep_num++) + for(uint8_t epnum = 0; epnum < DCD_ATTR_ENDPOINT_MAX; epnum++) { - if ( tu_bit_test(edpt_complete, ep_num) ) process_edpt_complete_isr(rhport, ep_num, TUSB_DIR_OUT); - if ( tu_bit_test(edpt_complete, ep_num+16) ) process_edpt_complete_isr(rhport, ep_num, TUSB_DIR_IN); + if ( tu_bit_test(edpt_complete, epnum) ) process_edpt_complete_isr(rhport, epnum, TUSB_DIR_OUT); + if ( tu_bit_test(edpt_complete, epnum+16) ) process_edpt_complete_isr(rhport, epnum, TUSB_DIR_IN); } } } -- cgit v1.3.1 From dd60ce784c635addf01ae3039d3be55a74f3d506 Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 11 Sep 2021 21:29:04 +0700 Subject: nxp tdi: implement dcd edpt close all --- .../nxp/transdimension/dcd_transdimension.c | 23 +++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/src/portable/nxp/transdimension/dcd_transdimension.c b/src/portable/nxp/transdimension/dcd_transdimension.c index ee1a50db3..07009ff50 100644 --- a/src/portable/nxp/transdimension/dcd_transdimension.c +++ b/src/portable/nxp/transdimension/dcd_transdimension.c @@ -57,11 +57,15 @@ // ENDPTCTRL enum { ENDPTCTRL_STALL = TU_BIT(0), - ENDPTCTRL_TOGGLE_INHIBIT = TU_BIT(5), ///< used for test only + ENDPTCTRL_TOGGLE_INHIBIT = TU_BIT(5), // used for test only ENDPTCTRL_TOGGLE_RESET = TU_BIT(6), ENDPTCTRL_ENABLE = TU_BIT(7) }; +enum { + ENDPTCTRL_TYPE_POS = 2, // Endpoint type is 2-bit field +}; + // USBSTS, USBINTR enum { INTR_USB = TU_BIT(0), @@ -193,9 +197,9 @@ static void bus_reset(uint8_t rhport) // endpoint type of the unused direction must be changed from the control type to any other // type (e.g. bulk). Leaving an un-configured endpoint control will cause undefined behavior // for the data PID tracking on the active endpoint. - for( int i=1; i < _dcd_controller[rhport].ep_count; i++) + for( uint8_t i=1; i < _dcd_controller[rhport].ep_count; i++) { - dcd_reg->ENDPTCTRL[i] = (TUSB_XFER_BULK << 2) | (TUSB_XFER_BULK << 18); + dcd_reg->ENDPTCTRL[i] = (TUSB_XFER_BULK << ENDPTCTRL_TYPE_POS) | (TUSB_XFER_BULK << (16+ENDPTCTRL_TYPE_POS)); } //------------- Clear All Registers -------------// @@ -364,8 +368,17 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) void dcd_edpt_close_all (uint8_t rhport) { - (void) rhport; - // TODO implement dcd_edpt_close_all() + dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; + + // Disable all non-control endpoints + for( uint8_t epnum=1; epnum < _dcd_controller[rhport].ep_count; epnum++) + { + _dcd_data.qhd[epnum][TUSB_DIR_OUT].qtd_overlay.halted = 1; + _dcd_data.qhd[epnum][TUSB_DIR_IN ].qtd_overlay.halted = 1; + + dcd_reg->ENDPTFLUSH = TU_BIT(epnum) | TU_BIT(epnum+16); + dcd_reg->ENDPTCTRL[epnum] = (TUSB_XFER_BULK << ENDPTCTRL_TYPE_POS) | (TUSB_XFER_BULK << (16+ENDPTCTRL_TYPE_POS)); + } } bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) -- cgit v1.3.1 From 9bed4e2e21dda8c6aac89852492bd178916d6be0 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 13 Sep 2021 00:45:15 +0700 Subject: refactor nxp TDI dcd_edpt_xfer_fifo --- .../nxp/transdimension/dcd_transdimension.c | 161 +++++++++------------ 1 file changed, 70 insertions(+), 91 deletions(-) diff --git a/src/portable/nxp/transdimension/dcd_transdimension.c b/src/portable/nxp/transdimension/dcd_transdimension.c index 294f88c56..a61f503f6 100644 --- a/src/portable/nxp/transdimension/dcd_transdimension.c +++ b/src/portable/nxp/transdimension/dcd_transdimension.c @@ -298,51 +298,30 @@ void dcd_disconnect(uint8_t rhport) static void qtd_init(dcd_qtd_t* p_qtd, void * data_ptr, uint16_t total_bytes) { + // Force the CPU to flush the buffer. We increase the size by 31 because the call aligns the + // address to 32-byte boundaries. Buffer must be word aligned + CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) data_ptr, 4), total_bytes + 31); + tu_memclr(p_qtd, sizeof(dcd_qtd_t)); - p_qtd->next = QTD_NEXT_INVALID; - p_qtd->active = 1; - p_qtd->total_bytes = p_qtd->expected_bytes = total_bytes; + p_qtd->next = QTD_NEXT_INVALID; + p_qtd->active = 1; + p_qtd->total_bytes = p_qtd->expected_bytes = total_bytes; + p_qtd->int_on_complete = true; if (data_ptr != NULL) { - p_qtd->buffer[0] = (uint32_t) data_ptr; + p_qtd->buffer[0] = (uint32_t) data_ptr; + + uint32_t const bufend = p_qtd->buffer[0] + total_bytes; for(uint8_t i=1; i<5; i++) { - p_qtd->buffer[i] |= tu_align4k( p_qtd->buffer[i-1] ) + 4096; - } - } -} - -static void qtd_init_fifo(dcd_qtd_t* p_qtd, tu_fifo_buffer_info_t *info, uint16_t total_bytes) -{ - tu_memclr(p_qtd, sizeof(dcd_qtd_t)); + uint32_t const next_page = tu_align4k( p_qtd->buffer[i-1] ) + 4096; + if ( bufend <= next_page ) break; - p_qtd->next = QTD_NEXT_INVALID; - p_qtd->active = 1; - p_qtd->total_bytes = p_qtd->expected_bytes = total_bytes; + p_qtd->buffer[i] = next_page; - // Fifo length has been trimmed to total_bytes - int16_t len_lin = info->len_lin; - - if (len_lin != 0) - { - p_qtd->buffer[0] = (uint32_t) info->ptr_lin; - - len_lin -= 4096 - ((uint32_t) info->ptr_lin - tu_align4k((uint32_t) info->ptr_lin)); - - // Set linear part - uint8_t i = 1; - for(; i<5; i++) - { - if (len_lin <= 0) break; - p_qtd->buffer[i] |= tu_align4k( p_qtd->buffer[i-1] ) + 4096; - len_lin -= 4096; - } - // Set wrapped part - for(uint8_t page = 0; i<5; i++, page++) - { - p_qtd->buffer[i] |= (uint32_t) info->ptr_wrap + 4096 * page; + // TODO page[1] FRAME_N for ISO transfer } } } @@ -445,11 +424,17 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) dcd_reg->ENDPTCTRL[epnum] &=~(ENDPTCTRL_ENABLE << (dir ? 16 : 0)); } -bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) +static void qhd_start_xfer(uint8_t rhport, uint8_t epnum, uint8_t dir) { dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); + dcd_qhd_t* p_qhd = &_dcd_data.qhd[epnum][dir]; + dcd_qtd_t* p_qtd = &_dcd_data.qtd[epnum][dir]; + + p_qhd->qtd_overlay.halted = false; // clear any previous error + p_qhd->qtd_overlay.next = (uint32_t) p_qtd; // link qtd to qhd + + // flush cache + CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t)); if ( epnum == 0 ) { @@ -458,26 +443,24 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t while(dcd_reg->ENDPTSETUPSTAT & TU_BIT(0)) {} } - dcd_qhd_t * p_qhd = &_dcd_data.qhd[epnum][dir]; - dcd_qtd_t * p_qtd = &_dcd_data.qtd[epnum][dir]; + // start transfer + dcd_reg->ENDPTPRIME = TU_BIT(epnum + (dir ? 16 : 0)); +} - // Force the CPU to flush the buffer. We increase the size by 32 because the call aligns the - // address to 32-byte boundaries. - // void* cast to suppress cast-align warning, buffer must be - CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) buffer, 4), total_bytes + 31); +bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) +{ + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); - //------------- Prepare qtd -------------// + dcd_qhd_t* p_qhd = &_dcd_data.qhd[epnum][dir]; + dcd_qtd_t* p_qtd = &_dcd_data.qtd[epnum][dir]; + + // Prepare qtd qtd_init(p_qtd, buffer, total_bytes); - p_qtd->int_on_complete = true; + // Start qhd transfer p_qhd->ff = NULL; - p_qhd->qtd_overlay.halted = false; // clear any previous error - p_qhd->qtd_overlay.next = (uint32_t) p_qtd; // activate by linking qtd to qhd - - CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t)); - - // start transfer - dcd_reg->ENDPTPRIME = TU_BIT(epnum + (dir ? 16 : 0)); + qhd_start_xfer(rhport, epnum, dir); return true; } @@ -485,17 +468,9 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t // fifo has to be aligned to 4k boundary bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes) { - dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); - if ( epnum == 0 ) - { - // follows UM 24.10.8.1.1 Setup packet handling using setup lockout mechanism - // wait until ENDPTSETUPSTAT before priming data/status in response TODO add time out - while(dcd_reg->ENDPTSETUPSTAT & TU_BIT(0)) {} - } - dcd_qhd_t * p_qhd = &_dcd_data.qhd[epnum][dir]; dcd_qtd_t * p_qtd = &_dcd_data.qtd[epnum][dir]; @@ -509,42 +484,45 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16 tu_fifo_get_write_info(ff, &fifo_info); } - if (total_bytes <= fifo_info.len_lin) - { - // Limit transfer length to total_bytes - fifo_info.len_wrap = 0; - fifo_info.len_lin = total_bytes; - } else - { - // Class driver need to ensure at least total_bytes elements in fifo - fifo_info.len_wrap = total_bytes - fifo_info.len_lin; - } - // Force the CPU to flush the buffer. We increase the size by 32 because the call aligns the - // address to 32-byte boundaries. - // void* cast to suppress cast-align warning, buffer must be - CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) fifo_info.ptr_lin, 4), fifo_info.len_lin + 31); - - //------------- Prepare qtd -------------// - - // In case of : wrapped part is present & buffer is aligned to 4k & buffer size is multiple of 4k - if (total_bytes > fifo_info.len_lin && !tu_offset4k((uint32_t)fifo_info.ptr_wrap) && !tu_offset4k(tu_fifo_depth(ff))) + if ( fifo_info.len_lin >= total_bytes ) { - CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) fifo_info.ptr_wrap, 4), fifo_info.len_wrap + 31); - qtd_init_fifo(p_qtd, &fifo_info, total_bytes); + // Linear length is enough for this transfer + qtd_init(p_qtd, fifo_info.ptr_lin, total_bytes); } else { - qtd_init(p_qtd, fifo_info.ptr_lin, total_bytes); - } + // linear part is not enough - p_qtd->int_on_complete = true; - p_qhd->qtd_overlay.next = (uint32_t) p_qtd; // link qtd to qhd - p_qhd->ff = ff; + // prepare TD up to linear length + qtd_init(p_qtd, fifo_info.ptr_lin, fifo_info.len_lin); - CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t)); + if ( !tu_offset4k((uint32_t) fifo_info.ptr_wrap) && !tu_offset4k(tu_fifo_depth(ff)) ) + { + // If buffer is aligned to 4K & buffer size is multiple of 4K + // We can make use of buffer page array to also combine the linear + wrapped length + p_qtd->total_bytes = p_qtd->expected_bytes = total_bytes; - // start transfer - dcd_reg->ENDPTPRIME = TU_BIT(epnum + (dir ? 16 : 0)); + for(uint8_t i = 1, page = 0; i < 5; i++) + { + // pick up buffer array where linear ends + if (p_qtd->buffer[i] == 0) + { + p_qtd->buffer[i] = (uint32_t) fifo_info.ptr_wrap + 4096 * page; + page++; + } + } + + CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) fifo_info.ptr_wrap, 4), total_bytes - fifo_info.len_wrap + 31); + } + else + { + // TODO we need to carry the wrapped length after the linear part complete + } + } + + // Start qhd transfer + p_qhd->ff = ff; + qhd_start_xfer(rhport, epnum, dir); return true; } @@ -582,6 +560,7 @@ static void process_edpt_complete_isr(uint8_t rhport, uint8_t epnum, uint8_t dir } // only number of bytes in the IOC qtd + // TODO there is still a case with xfer_fifo with additional wrapped buffer to fullfil the requested length dcd_event_xfer_complete(rhport, tu_edpt_addr(epnum, dir), xferred_bytes, result, true); } -- cgit v1.3.1 From d5f2c34eaa3e840b32817829031b95c6b7780314 Mon Sep 17 00:00:00 2001 From: szymonh <12231135+szymonh@users.noreply.github.com> Date: Sun, 12 Sep 2021 20:09:58 +0200 Subject: Prevent buffer overflow in bth_device.c --- src/class/bth/bth_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/class/bth/bth_device.c b/src/class/bth/bth_device.c index 1d27ae7c5..09fab953e 100755 --- a/src/class/bth/bth_device.c +++ b/src/class/bth/bth_device.c @@ -214,7 +214,7 @@ bool btd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t c } else return false; - return tud_control_xfer(rhport, request, &_btd_itf.hci_cmd, request->wLength); + return tud_control_xfer(rhport, request, &_btd_itf.hci_cmd, sizeof(_btd_itf.hci_cmd)); } else if ( stage == CONTROL_STAGE_DATA ) { -- cgit v1.3.1 From ce5db06ba03f356b2049edc3b36aea398fa50036 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 13 Sep 2021 12:05:49 +0700 Subject: clear PID along with clear stall --- src/portable/nuvoton/nuc121/dcd_nuc121.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/src/portable/nuvoton/nuc121/dcd_nuc121.c b/src/portable/nuvoton/nuc121/dcd_nuc121.c index 5dfc77bb7..dbc5cd18a 100644 --- a/src/portable/nuvoton/nuc121/dcd_nuc121.c +++ b/src/portable/nuvoton/nuc121/dcd_nuc121.c @@ -200,11 +200,10 @@ static void bus_reset(void) } /* centralized location for USBD interrupt enable bit mask */ -#if USE_SOF -static const uint32_t enabled_irqs = USBD_INTSTS_VBDETIF_Msk | USBD_INTSTS_BUSIF_Msk | USBD_INTSTS_SETUP_Msk | USBD_INTSTS_USBIF_Msk | USBD_INTSTS_SOFIF_Msk; -#else -static const uint32_t enabled_irqs = USBD_INTSTS_VBDETIF_Msk | USBD_INTSTS_BUSIF_Msk | USBD_INTSTS_SETUP_Msk | USBD_INTSTS_USBIF_Msk; -#endif +enum { + ENABLED_IRQS = USBD_INTSTS_VBDETIF_Msk | USBD_INTSTS_BUSIF_Msk | USBD_INTSTS_SETUP_Msk | + USBD_INTSTS_USBIF_Msk | (USE_SOF ? USBD_INTSTS_SOFIF_Msk : 0) +}; /* NUC121/NUC125/NUC126 TinyUSB API driver implementation @@ -226,8 +225,8 @@ void dcd_init(uint8_t rhport) usb_attach(); - USBD->INTSTS = enabled_irqs; - USBD->INTEN = enabled_irqs; + USBD->INTSTS = ENABLED_IRQS; + USBD->INTEN = ENABLED_IRQS; } void dcd_int_enable(uint8_t rhport) @@ -380,8 +379,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { (void) rhport; USBD_EP_T *ep = ep_entry(ep_addr, false); - ep->CFG |= USBD_CFG_CSTALL_Msk; - ep->CFG &=~USBD_CFG_DSQSYNC_Msk; + ep->CFG = (ep->CFG & ~USBD_CFG_DSQSYNC_Msk) | USBD_CFG_CSTALL_Msk; } void dcd_int_handler(uint8_t rhport) @@ -389,7 +387,8 @@ void dcd_int_handler(uint8_t rhport) (void) rhport; // Mask non-enabled irqs, ex. SOF - uint32_t status = USBD->INTSTS & (enabled_irqs | 0xffffff00); + uint32_t status = USBD->INTSTS & (ENABLED_IRQS | 0xffffff00); + #ifdef SUPPORT_LPM uint32_t state = USBD->ATTR & 0x300f; #else @@ -520,7 +519,7 @@ void dcd_int_handler(uint8_t rhport) } /* acknowledge all interrupts */ - USBD->INTSTS = status & enabled_irqs; + USBD->INTSTS = status & ENABLED_IRQS; } // Invoked when a control transfer's status stage is complete. -- cgit v1.3.1 From 43e6555fd03906c4524f2f212199cdf32cb5fb0f Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 13 Sep 2021 13:09:38 +0700 Subject: clean up --- src/portable/nxp/transdimension/dcd_transdimension.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/portable/nxp/transdimension/dcd_transdimension.c b/src/portable/nxp/transdimension/dcd_transdimension.c index a61f503f6..a7c4545c2 100644 --- a/src/portable/nxp/transdimension/dcd_transdimension.c +++ b/src/portable/nxp/transdimension/dcd_transdimension.c @@ -516,7 +516,8 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16 } else { - // TODO we need to carry the wrapped length after the linear part complete + // TODO we may need to carry the wrapped length after the linear part complete + // for now only transfer up to linear part } } @@ -560,7 +561,6 @@ static void process_edpt_complete_isr(uint8_t rhport, uint8_t epnum, uint8_t dir } // only number of bytes in the IOC qtd - // TODO there is still a case with xfer_fifo with additional wrapped buffer to fullfil the requested length dcd_event_xfer_complete(rhport, tu_edpt_addr(epnum, dir), xferred_bytes, result, true); } -- cgit v1.3.1 From 50e3c0054f8d26340863667a50aae5a798f6aefc Mon Sep 17 00:00:00 2001 From: szymonh <12231135+szymonh@users.noreply.github.com> Date: Mon, 13 Sep 2021 10:23:03 +0200 Subject: Add size check to tud_bt_hci_cmd_cb call in bth_device.c --- src/class/bth/bth_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/class/bth/bth_device.c b/src/class/bth/bth_device.c index 09fab953e..b73f829cc 100755 --- a/src/class/bth/bth_device.c +++ b/src/class/bth/bth_device.c @@ -221,7 +221,7 @@ bool btd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t c // Handle class request only TU_VERIFY(request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS); - if (tud_bt_hci_cmd_cb) tud_bt_hci_cmd_cb(&_btd_itf.hci_cmd, request->wLength); + if (tud_bt_hci_cmd_cb) tud_bt_hci_cmd_cb(&_btd_itf.hci_cmd, tu_min16(request->wLength, sizeof(_btd_itf.hci_cmd))); } return true; -- cgit v1.3.1 From e64bfb9ff53647e21ba755c4ae4aa6bb3f2677ac Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 13 Sep 2021 16:16:37 +0700 Subject: implement dcd_edpt_close_all(), pass chapter9 test suite (without remote wakeup) --- src/portable/espressif/esp32sx/dcd_esp32sx.c | 79 ++++++++++------------------ 1 file changed, 28 insertions(+), 51 deletions(-) diff --git a/src/portable/espressif/esp32sx/dcd_esp32sx.c b/src/portable/espressif/esp32sx/dcd_esp32sx.c index a5ada0da8..541f7d586 100644 --- a/src/portable/espressif/esp32sx/dcd_esp32sx.c +++ b/src/portable/espressif/esp32sx/dcd_esp32sx.c @@ -92,11 +92,12 @@ static void bus_reset(void) USB0.out_ep_reg[ep_num].doepctl |= USB_DO_SNAK0_M; // DOEPCTL0_SNAK } - USB0.dcfg &= ~USB_DEVADDR_M; // reset address + // clear device address + USB0.dcfg &= ~USB_DEVADDR_M; - USB0.daintmsk |= USB_OUTEPMSK0_M | USB_INEPMSK0_M; - USB0.doepmsk |= USB_SETUPMSK_M | USB_XFERCOMPLMSK; - USB0.diepmsk |= USB_TIMEOUTMSK_M | USB_DI_XFERCOMPLMSK_M /*| USB_INTKNTXFEMPMSK_M*/; + USB0.daintmsk = USB_OUTEPMSK0_M | USB_INEPMSK0_M; + USB0.doepmsk = USB_SETUPMSK_M | USB_XFERCOMPLMSK; + USB0.diepmsk = USB_TIMEOUTMSK_M | USB_DI_XFERCOMPLMSK_M /*| USB_INTKNTXFEMPMSK_M*/; // "USB Data FIFOs" section in reference manual // Peripheral FIFO architecture @@ -260,9 +261,10 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_edpt) xfer->max_size = desc_edpt->wMaxPacketSize.size; if (dir == TUSB_DIR_OUT) { - out_ep[epnum].doepctl |= USB_USBACTEP0_M | - desc_edpt->bmAttributes.xfer << USB_EPTYPE0_S | - desc_edpt->wMaxPacketSize.size << USB_MPS0_S; + out_ep[epnum].doepctl |= USB_USBACTEP1_M | + desc_edpt->bmAttributes.xfer << USB_EPTYPE1_S | + (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_DO_SETD0PID1_M : 0) | + desc_edpt->wMaxPacketSize.size << USB_MPS1_S; USB0.daintmsk |= (1 << (16 + epnum)); } else { // "USB Data FIFOs" section in reference manual @@ -315,7 +317,25 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_edpt) void dcd_edpt_close_all(uint8_t rhport) { (void) rhport; - // TODO implement dcd_edpt_close_all() + + usb_out_endpoint_t *out_ep = &(USB0.out_ep_reg[0]); + usb_in_endpoint_t *in_ep = &(USB0.in_ep_reg[0]); + + // Disable non-control interrupt + USB0.daintmsk = USB_OUTEPMSK0_M | USB_INEPMSK0_M; + + for(uint8_t n = 1; n < EP_MAX; n++) + { + // disable OUT endpoint + out_ep[n].doepctl = 0; + xfer_status[n][TUSB_DIR_OUT].max_size = 0; + + // disable IN endpoint + in_ep[n].diepctl = 0; + xfer_status[n][TUSB_DIR_IN].max_size = 0; + } + + _allocated_fifos = 1; } bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) @@ -367,49 +387,6 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes) { (void)rhport; - - // USB buffers always work in bytes so to avoid unnecessary divisions we demand item_size = 1 - TU_ASSERT(ff->item_size == 1); - - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); - - xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir); - xfer->buffer = NULL; - xfer->ff = ff; - xfer->total_len = total_bytes; - xfer->queued_len = 0; - xfer->short_packet = false; - - uint16_t num_packets = (total_bytes / xfer->max_size); - uint8_t short_packet_size = total_bytes % xfer->max_size; - - // Zero-size packet is special case. - if (short_packet_size > 0 || (total_bytes == 0)) { - num_packets++; - } - - ESP_LOGV(TAG, "Transfer <-> EP%i, %s, pkgs: %i, bytes: %i", - epnum, ((dir == TUSB_DIR_IN) ? "USB0.HOST (in)" : "HOST->DEV (out)"), - num_packets, total_bytes); - - // IN and OUT endpoint xfers are interrupt-driven, we just schedule them - // here. - if (dir == TUSB_DIR_IN) { - // A full IN transfer (multiple packets, possibly) triggers XFRC. - USB0.in_ep_reg[epnum].dieptsiz = (num_packets << USB_D_PKTCNT0_S) | total_bytes; - USB0.in_ep_reg[epnum].diepctl |= USB_D_EPENA1_M | USB_D_CNAK1_M; // Enable | CNAK - - // Enable fifo empty interrupt only if there are something to put in the fifo. - if(total_bytes != 0) { - USB0.dtknqr4_fifoemptymsk |= (1 << epnum); - } - } else { - // Each complete packet for OUT xfers triggers XFRC. - USB0.out_ep_reg[epnum].doeptsiz |= USB_PKTCNT0_M | ((xfer->max_size & USB_XFERSIZE0_V) << USB_XFERSIZE0_S); - USB0.out_ep_reg[epnum].doepctl |= USB_EPENA0_M | USB_CNAK0_M; - } - return true; } #endif -- cgit v1.3.1 From cdc63459ebf5bd979d1e98253abd3d75693dcdaf Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 13 Sep 2021 16:49:38 +0700 Subject: esp32sx implement dcd_remote_wakeup(), fully compliance to chapter9 test suite --- .../hid_composite_freertos/src/tusb_config.h | 5 ++-- src/common/tusb_common.h | 2 +- src/portable/espressif/esp32sx/dcd_esp32sx.c | 33 +++++++++++++--------- 3 files changed, 23 insertions(+), 17 deletions(-) diff --git a/examples/device/hid_composite_freertos/src/tusb_config.h b/examples/device/hid_composite_freertos/src/tusb_config.h index 4b0458ef0..4fbccc294 100644 --- a/examples/device/hid_composite_freertos/src/tusb_config.h +++ b/examples/device/hid_composite_freertos/src/tusb_config.h @@ -67,8 +67,9 @@ // This examples use FreeRTOS #define CFG_TUSB_OS OPT_OS_FREERTOS -// CFG_TUSB_DEBUG is defined by compiler in DEBUG build -// #define CFG_TUSB_DEBUG 0 +#ifndef CFG_TUSB_DEBUG +#define CFG_TUSB_DEBUG 0 +#endif /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment. * Tinyusb use follows macros to declare transferring memory so that they can be put diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h index d0cc41285..1899b35cc 100644 --- a/src/common/tusb_common.h +++ b/src/common/tusb_common.h @@ -380,7 +380,7 @@ static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint3 } // not found return the key value in hex - sprintf(not_found, "0x%08lX", key); + sprintf(not_found, "0x%08lX", (unsigned long) key); return not_found; } diff --git a/src/portable/espressif/esp32sx/dcd_esp32sx.c b/src/portable/espressif/esp32sx/dcd_esp32sx.c index 541f7d586..cfbbab233 100644 --- a/src/portable/espressif/esp32sx/dcd_esp32sx.c +++ b/src/portable/espressif/esp32sx/dcd_esp32sx.c @@ -42,10 +42,6 @@ #include "device/dcd.h" -// Since TinyUSB doesn't use SOF for now, and this interrupt too often (1ms interval) -// We disable SOF for now until needed later on -#define USE_SOF 0 - // Max number of bi-directional endpoints including EP0 // Note: ESP32S2 specs say there are only up to 5 IN active endpoints include EP0 // We should probably prohibit enabling Endpoint IN > 4 (not done yet) @@ -194,9 +190,6 @@ void dcd_init(uint8_t rhport) USB0.gintsts = ~0U; //clear pending ints USB0.gintmsk = USB_OTGINTMSK_M | USB_MODEMISMSK_M | - #if USE_SOF - USB_SOFMSK_M | - #endif USB_RXFLVIMSK_M | USB_ERLYSUSPMSK_M | USB_USBSUSPMSK_M | @@ -221,8 +214,17 @@ void dcd_remote_wakeup(uint8_t rhport) { (void)rhport; - // TODO must manually clear this bit after 1-15 ms - // USB0.DCTL |= USB_RMTWKUPSIG_M; + // set remote wakeup + USB0.dctl |= USB_RMTWKUPSIG_M; + + // enable SOF to detect bus resume + USB0.gintsts = USB_SOF_M; + USB0.gintmsk |= USB_SOFMSK_M; + + // Per specs: remote wakeup signal bit must be clear within 1-15ms + vTaskDelay(pdMS_TO_TICKS(1)); + + USB0.dctl &= ~USB_RMTWKUPSIG_M; } // connect by enabling internal pull-up resistor on D+/D- @@ -731,8 +733,8 @@ static void _dcd_int_handler(void* arg) (void) arg; uint8_t const rhport = 0; - const uint32_t int_status = USB0.gintsts; - //const uint32_t int_msk = USB0.gintmsk; + const uint32_t int_msk = USB0.gintmsk; + const uint32_t int_status = USB0.gintsts & int_msk; if (int_status & USB_USBRST_M) { // start of reset @@ -785,12 +787,15 @@ static void _dcd_int_handler(void* arg) USB0.gotgint = otg_int; } -#if USE_SOF if (int_status & USB_SOF_M) { USB0.gintsts = USB_SOF_M; - dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true); // do nothing actually + + // Disable SOF interrupt since currently only used for remote wakeup detection + USB0.gintmsk &= ~USB_SOFMSK_M; + + dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true); } -#endif + if (int_status & USB_RXFLVI_M) { // RXFLVL bit is read-only -- cgit v1.3.1 From 1a87b605bd14404cdabd9f938a49e4e08c1adf95 Mon Sep 17 00:00:00 2001 From: szymonh <12231135+szymonh@users.noreply.github.com> Date: Mon, 13 Sep 2021 13:21:25 +0200 Subject: Add support for Nucleo F412ZG --- .../boards/stm32f412nucleo/STM32F412ZGTx_FLASH.ld | 169 +++++++ hw/bsp/stm32f4/boards/stm32f412nucleo/board.h | 119 +++++ hw/bsp/stm32f4/boards/stm32f412nucleo/board.mk | 11 + .../boards/stm32f412nucleo/stm32f4xx_hal_conf.h | 493 +++++++++++++++++++++ 4 files changed, 792 insertions(+) create mode 100644 hw/bsp/stm32f4/boards/stm32f412nucleo/STM32F412ZGTx_FLASH.ld create mode 100644 hw/bsp/stm32f4/boards/stm32f412nucleo/board.h create mode 100644 hw/bsp/stm32f4/boards/stm32f412nucleo/board.mk create mode 100644 hw/bsp/stm32f4/boards/stm32f412nucleo/stm32f4xx_hal_conf.h diff --git a/hw/bsp/stm32f4/boards/stm32f412nucleo/STM32F412ZGTx_FLASH.ld b/hw/bsp/stm32f4/boards/stm32f412nucleo/STM32F412ZGTx_FLASH.ld new file mode 100644 index 000000000..b00b5dbe0 --- /dev/null +++ b/hw/bsp/stm32f4/boards/stm32f412nucleo/STM32F412ZGTx_FLASH.ld @@ -0,0 +1,169 @@ +/* +***************************************************************************** +** + +** File : LinkerScript.ld +** +** Abstract : Linker script for STM32F412ZGTx Device with +** 1024KByte FLASH, 256KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +** (c)Copyright Ac6. +** You may use this file as-is or modify it according to the needs of your +** project. Distribution of this file (unmodified or modified) is not +** permitted. Ac6 permit registered System Workbench for MCU users the +** rights to distribute the assembled, compiled & linked contents of this +** file as part of an application binary file, provided that it is built +** using the System Workbench for MCU toolchain. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20040000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 256K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/hw/bsp/stm32f4/boards/stm32f412nucleo/board.h b/hw/bsp/stm32f4/boards/stm32f412nucleo/board.h new file mode 100644 index 000000000..73c5f83b9 --- /dev/null +++ b/hw/bsp/stm32f4/boards/stm32f412nucleo/board.h @@ -0,0 +1,119 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +// LED +#define LED_PORT GPIOB +#define LED_PIN GPIO_PIN_14 +#define LED_STATE_ON 0 + +// Button +#define BUTTON_PORT GPIOC +#define BUTTON_PIN GPIO_PIN_13 +#define BUTTON_STATE_ACTIVE 1 + +// UART Enable for STLink VCOM +#define UART_DEV USART3 +#define UART_GPIO_PORT GPIOD +#define UART_GPIO_AF GPIO_AF7_USART3 +#define UART_TX_PIN GPIO_PIN_8 +#define UART_RX_PIN GPIO_PIN_9 + +//--------------------------------------------------------------------+ +// RCC Clock +//--------------------------------------------------------------------+ +static inline void board_clock_init(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; + + /* Enable Power Control clock */ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* The voltage scaling allows optimizing the power consumption when the + * device is clocked below the maximum system frequency, to update the + * voltage scaling value regarding system frequency refer to product + * datasheet. */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /* Enable HSE Oscillator and activate PLL with HSE as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/1000000; + RCC_OscInitStruct.PLL.PLLN = 200; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 7; + RCC_OscInitStruct.PLL.PLLR = 2; + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + /* Select PLLSAI output as USB clock source */ + PeriphClkInitStruct.PLLI2S.PLLI2SM = 8; + PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4; + PeriphClkInitStruct.PLLI2S.PLLI2SN = 192; + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CK48; + PeriphClkInitStruct.Clk48ClockSelection = RCC_CK48CLKSOURCE_PLLI2SQ; + PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC; + PeriphClkInitStruct.PLLI2S.PLLI2SR = 7; + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 + * clocks dividers */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | + RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3); + + // Enable clocks for LED, Button, Uart + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_USART3_CLK_ENABLE(); +} + +static inline void board_vbus_sense_init(void) +{ + // Enable VBUS sense (B device) via pin PA9 + USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN; +} + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/stm32f4/boards/stm32f412nucleo/board.mk b/hw/bsp/stm32f4/boards/stm32f412nucleo/board.mk new file mode 100644 index 000000000..50973f737 --- /dev/null +++ b/hw/bsp/stm32f4/boards/stm32f412nucleo/board.mk @@ -0,0 +1,11 @@ +CFLAGS += -DSTM32F412Zx + +LD_FILE = $(BOARD_PATH)/STM32F412ZGTx_FLASH.ld + +SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f412zx.s + +# For flash-jlink target +JLINK_DEVICE = stm32f412zg + +# flash target using on-board stlink +flash: flash-stlink diff --git a/hw/bsp/stm32f4/boards/stm32f412nucleo/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f412nucleo/stm32f4xx_hal_conf.h new file mode 100644 index 000000000..7864f8d5f --- /dev/null +++ b/hw/bsp/stm32f4/boards/stm32f412nucleo/stm32f4xx_hal_conf.h @@ -0,0 +1,493 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_conf_template.h + * @author MCD Application Team + * @brief HAL configuration file + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_CONF_H +#define __STM32F4xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +/* #define HAL_ADC_MODULE_ENABLED */ +/* #define HAL_CAN_MODULE_ENABLED */ +/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_DAC_MODULE_ENABLED */ +/* #define HAL_DCMI_MODULE_ENABLED */ +#define HAL_DMA_MODULE_ENABLED +/* #define HAL_DMA2D_MODULE_ENABLED */ +/* #define HAL_ETH_MODULE_ENABLED */ +#define HAL_FLASH_MODULE_ENABLED +/* #define HAL_NAND_MODULE_ENABLED */ +/* #define HAL_NOR_MODULE_ENABLED */ +/* #define HAL_PCCARD_MODULE_ENABLED */ +/* #define HAL_SRAM_MODULE_ENABLED */ +/* #define HAL_SDRAM_MODULE_ENABLED */ +/* #define HAL_HASH_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +/* #define HAL_EXTI_MODULE_ENABLED */ +/* #define HAL_I2C_MODULE_ENABLED */ +/* #define HAL_SMBUS_MODULE_ENABLED */ +/* #define HAL_I2S_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_LTDC_MODULE_ENABLED */ +/* #define HAL_DSI_MODULE_ENABLED */ +#define HAL_PWR_MODULE_ENABLED +/* #define HAL_QSPI_MODULE_ENABLED */ +#define HAL_RCC_MODULE_ENABLED +/* #define HAL_RNG_MODULE_ENABLED */ +/* #define HAL_RTC_MODULE_ENABLED */ +/* #define HAL_SAI_MODULE_ENABLED */ +/* #define HAL_SD_MODULE_ENABLED */ +// #define HAL_SPI_MODULE_ENABLED +/* #define HAL_TIM_MODULE_ENABLED */ +#define HAL_UART_MODULE_ENABLED +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +#define HAL_CORTEX_MODULE_ENABLED +/* #define HAL_PCD_MODULE_ENABLED */ +/* #define HAL_HCD_MODULE_ENABLED */ +/* #define HAL_FMPI2C_MODULE_ENABLED */ +/* #define HAL_SPDIFRX_MODULE_ENABLED */ +/* #define HAL_DFSDM_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +/* #define HAL_MMC_MODULE_ENABLED */ + +/* ########################## HSE/HSI Values adaptation ##################### */ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE (8000000U) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT (100U) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE (16000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE (32000U) +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE (32768U) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT (5000U) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE (12288000U) /*!< Value of the External oscillator in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE (3300U) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY (0x0FU) /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 1U +#define INSTRUCTION_CACHE_ENABLE 1U +#define DATA_CACHE_ENABLE 1U + +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ +#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ +#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ +#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ +#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ +#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ +#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */ +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ +#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ +#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */ +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ +#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ +#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Ethernet peripheral configuration ##################### */ + +/* Section 1 : Ethernet peripheral configuration */ + +/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ +#define MAC_ADDR0 2U +#define MAC_ADDR1 0U +#define MAC_ADDR2 0U +#define MAC_ADDR3 0U +#define MAC_ADDR4 0U +#define MAC_ADDR5 0U + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* Section 2: PHY configuration section */ + +/* DP83848 PHY Address*/ +#define DP83848_PHY_ADDRESS 0x01U +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define PHY_RESET_DELAY 0x000000FFU +/* PHY Configuration delay */ +#define PHY_CONFIG_DELAY 0x00000FFFU + +#define PHY_READ_TO 0x0000FFFFU +#define PHY_WRITE_TO 0x0000FFFFU + +/* Section 3: Common PHY Registers */ + +#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */ + +#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ + +/* Section 4: Extended PHY Registers */ + +#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */ +#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */ +#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */ + +#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */ +#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */ + +#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */ +#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */ + +#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */ +#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 1U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f4xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32f4xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32f4xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f4xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32f4xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32f4xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32f4xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #include "stm32f4xx_hal_can_legacy.h" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32f4xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32f4xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32f4xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32f4xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32f4xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32f4xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32f4xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32f4xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32f4xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32f4xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_PCCARD_MODULE_ENABLED + #include "stm32f4xx_hal_pccard.h" +#endif /* HAL_PCCARD_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32f4xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32f4xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32f4xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32f4xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32f4xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32f4xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32f4xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32f4xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32f4xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32f4xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32f4xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32f4xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32f4xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32f4xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32f4xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32f4xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32f4xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32f4xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32f4xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32f4xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32f4xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32f4xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32f4xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32f4xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_FMPI2C_MODULE_ENABLED + #include "stm32f4xx_hal_fmpi2c.h" +#endif /* HAL_FMPI2C_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32f4xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32f4xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32f4xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32f4xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_CONF_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ -- cgit v1.3.1 From 43aac7074be0d14e72cb04eaddcddf1a926c6a74 Mon Sep 17 00:00:00 2001 From: Ha Thach Date: Mon, 13 Sep 2021 22:16:34 +0700 Subject: Update supported.rst --- docs/reference/supported.rst | 1 + 1 file changed, 1 insertion(+) diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst index d114d8405..daf5bce75 100644 --- a/docs/reference/supported.rst +++ b/docs/reference/supported.rst @@ -316,6 +316,7 @@ ST STM32 - `STM32 F411ce Black Pill `__ - `STM32 F411ve Discovery `__ - `STM32 F412zg Discovery `__ +- `STM32 F412zg Nucleo `__ - `STM32 F723e Discovery `__ - `STM32 F746zg Nucleo `__ - `STM32 F746g Discovery `__ -- cgit v1.3.1 From 2d6407e7a5e6c99280ce11f1b02ea4b75dda133f Mon Sep 17 00:00:00 2001 From: szymonh <12231135+szymonh@users.noreply.github.com> Date: Mon, 13 Sep 2021 22:56:25 +0200 Subject: Enforced buffer boundaries for hid devices --- src/class/hid/hid_device.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/class/hid/hid_device.c b/src/class/hid/hid_device.c index 2ee80750a..55071a5ce 100644 --- a/src/class/hid/hid_device.c +++ b/src/class/hid/hid_device.c @@ -282,7 +282,7 @@ bool hidd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t uint8_t const report_id = tu_u16_low(request->wValue); uint8_t* report_buf = p_hid->epin_buf; - uint16_t req_len = request->wLength; + uint16_t req_len = tu_min16(request->wLength, CFG_TUD_HID_EP_BUFSIZE); uint16_t xferlen = 0; @@ -314,7 +314,7 @@ bool hidd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t uint8_t const report_id = tu_u16_low(request->wValue); uint8_t const* report_buf = p_hid->epout_buf; - uint16_t report_len = request->wLength; + uint16_t report_len = tu_min16(request->wLength, CFG_TUD_HID_EP_BUFSIZE); // If host request a specific Report ID, extract report ID in buffer before invoking callback if ( (report_id != HID_REPORT_TYPE_INVALID) && (report_len > 1) && (report_id == report_buf[0]) ) -- cgit v1.3.1 From 103a11d44973c587156bbd9db8502f2b99c7b71e Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 14 Sep 2021 12:25:08 +0700 Subject: add host hid_controller to cmake all list fix 1067 --- examples/host/CMakeLists.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/examples/host/CMakeLists.txt b/examples/host/CMakeLists.txt index f185ac4f8..5c63ec0c0 100644 --- a/examples/host/CMakeLists.txt +++ b/examples/host/CMakeLists.txt @@ -7,3 +7,4 @@ family_initialize_project(tinyusb_host_examples ${CMAKE_CURRENT_LIST_DIR}) # family_add_subdirectory will filter what to actually add based on selected FAMILY family_add_subdirectory(cdc_msc_hid) +family_add_subdirectory(hid_controller) -- cgit v1.3.1 From 5404d6d8ae02fac16eb8dbfd4a9d15de8e6c1342 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 14 Sep 2021 12:47:20 +0700 Subject: usbd pre-compute total interface length without replying on driver open --- src/device/usbd.c | 18 ++++++++---------- src/host/usbh.c | 2 +- 2 files changed, 9 insertions(+), 11 deletions(-) diff --git a/src/device/usbd.c b/src/device/usbd.c index 4ab60569b..a5773c625 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -880,7 +880,7 @@ static bool process_set_config(uint8_t rhport, uint8_t cfg_num) // Parse configuration descriptor _usbd_dev.remote_wakeup_support = (desc_cfg->bmAttributes & TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP) ? 1 : 0; - _usbd_dev.self_powered = (desc_cfg->bmAttributes & TUSB_DESC_CONFIG_ATT_SELF_POWERED) ? 1 : 0; + _usbd_dev.self_powered = (desc_cfg->bmAttributes & TUSB_DESC_CONFIG_ATT_SELF_POWERED ) ? 1 : 0; // Parse interface descriptor uint8_t const * p_desc = ((uint8_t const*) desc_cfg) + sizeof(tusb_desc_configuration_t); @@ -900,26 +900,22 @@ static bool process_set_config(uint8_t rhport, uint8_t cfg_num) TU_ASSERT( TUSB_DESC_INTERFACE == tu_desc_type(p_desc) ); tusb_desc_interface_t const * desc_itf = (tusb_desc_interface_t const*) p_desc; - uint16_t const remaining_len = desc_end-p_desc; // Interface number must not be used already TU_ASSERT(DRVID_INVALID == _usbd_dev.itf2drv[desc_itf->bInterfaceNumber]); - // TODO usbd can calculate the total length used for driver --> driver open() does not need to calculate it - // uint16_t const drv_len = tu_desc_get_interface_total_len(desc_itf, desc_iad ? desc_iad->bInterfaceCount : 1, desc_end-p_desc); + uint16_t const drv_len = tu_desc_get_interface_total_len(desc_itf, desc_iad ? desc_iad->bInterfaceCount : 1, desc_end-p_desc); + TU_ASSERT(drv_len); // Find driver for this interface uint8_t drv_id; for (drv_id = 0; drv_id < TOTAL_DRIVER_COUNT; drv_id++) { usbd_class_driver_t const *driver = get_driver(drv_id); - uint16_t const drv_len = driver->open(rhport, desc_itf, remaining_len); - if ( drv_len > 0 ) + if ( driver->open(rhport, desc_itf, drv_len) ) { // Open successfully, check if length is correct - TU_ASSERT( sizeof(tusb_desc_interface_t) <= drv_len && drv_len <= remaining_len); - TU_LOG2(" %s opened\r\n", driver->name); // bind interface to found driver @@ -941,14 +937,16 @@ static bool process_set_config(uint8_t rhport, uint8_t cfg_num) // bind all endpoints to found driver tu_edpt_bind_driver(_usbd_dev.ep2drv, desc_itf, drv_len, drv_id); - p_desc += drv_len; // next interface break; // exit driver find loop } } - // Failed if cannot find supported driver + // Failed if there is no supported drivers TU_ASSERT(drv_id < TOTAL_DRIVER_COUNT); + + // next Interface or IAD descriptor + p_desc += drv_len; } // invoke callback diff --git a/src/host/usbh.c b/src/host/usbh.c index 51b8f85b6..886a120a8 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -989,7 +989,7 @@ static bool parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configura if ( TUSB_DESC_INTERFACE_ASSOCIATION == tu_desc_type(p_desc) ) { desc_iad = (tusb_desc_interface_assoc_t const *) p_desc; - p_desc = tu_desc_next(p_desc); + p_desc = tu_desc_next(p_desc); // next to Interface } TU_ASSERT( TUSB_DESC_INTERFACE == tu_desc_type(p_desc) ); -- cgit v1.3.1 From 36391680660f1ec0960003eece7e7605c29574af Mon Sep 17 00:00:00 2001 From: MasterPhi Date: Tue, 14 Sep 2021 11:58:22 +0200 Subject: Fix warning. --- src/device/usbd.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/device/usbd.c b/src/device/usbd.c index 4ab60569b..1184f8e47 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -1041,6 +1041,7 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const break; case TUSB_DESC_DEVICE_QUALIFIER: + { TU_LOG2(" Device Qualifier\r\n"); TU_VERIFY( tud_descriptor_device_qualifier_cb ); @@ -1050,6 +1051,7 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const // first byte of descriptor is its size return tud_control_xfer(rhport, p_request, (void*) desc_qualifier, desc_qualifier[0]); + } break; default: return false; -- cgit v1.3.1 From 25ea8f9c9e65d1617382a7896df07afd0dc90ce3 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 14 Sep 2021 21:02:38 +0700 Subject: update configuration parser --- .../audio_4_channel_mic/src/usb_descriptors.c | 13 +++--- src/class/msc/msc_device.c | 2 +- src/device/usbd.c | 44 ++++++++++++--------- src/host/usbh.c | 46 ++++++++++++---------- src/tusb.c | 2 +- src/tusb_option.h | 24 +++++++++++ 6 files changed, 85 insertions(+), 46 deletions(-) diff --git a/examples/device/audio_4_channel_mic/src/usb_descriptors.c b/examples/device/audio_4_channel_mic/src/usb_descriptors.c index 018919bf3..2b66bfe34 100644 --- a/examples/device/audio_4_channel_mic/src/usb_descriptors.c +++ b/examples/device/audio_4_channel_mic/src/usb_descriptors.c @@ -81,12 +81,15 @@ enum #define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + CFG_TUD_AUDIO * TUD_AUDIO_MIC_FOUR_CH_DESC_LEN) -#if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX -// LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number -// 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ... -#define EPNUM_AUDIO 0x03 +#if TU_CHECK_MCU(LPC175X_6X) || TU_CHECK_MCU(LPC177X_8X) || TU_CHECK_MCU(LPC40XX) + // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number + // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ... + #define EPNUM_AUDIO 0x03 +#elif TU_CHECK_MCU(NRF5X) + // nRF5x ISO can only be endpoint 8 + #define EPNUM_AUDIO 0x08 #else -#define EPNUM_AUDIO 0x01 + #define EPNUM_AUDIO 0x01 #endif uint8_t const desc_configuration[] = diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c index 0fd592129..765760fd1 100644 --- a/src/class/msc/msc_device.c +++ b/src/class/msc/msc_device.c @@ -258,7 +258,7 @@ uint16_t mscd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint1 // msc driver length is fixed uint16_t const drv_len = sizeof(tusb_desc_interface_t) + 2*sizeof(tusb_desc_endpoint_t); - // Max length mus be at least 1 interface + 2 endpoints + // Max length must be at least 1 interface + 2 endpoints TU_ASSERT(max_len >= drv_len, 0); mscd_interface_t * p_msc = &_mscd_itf; diff --git a/src/device/usbd.c b/src/device/usbd.c index a5773c625..2874dc5eb 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -888,23 +888,40 @@ static bool process_set_config(uint8_t rhport, uint8_t cfg_num) while( p_desc < desc_end ) { - tusb_desc_interface_assoc_t const * desc_iad = NULL; + uint8_t assoc_itf_count = 1; // Class will always starts with Interface Association (if any) and then Interface descriptor if ( TUSB_DESC_INTERFACE_ASSOCIATION == tu_desc_type(p_desc) ) { - desc_iad = (tusb_desc_interface_assoc_t const *) p_desc; + tusb_desc_interface_assoc_t const * desc_iad = (tusb_desc_interface_assoc_t const *) p_desc; + assoc_itf_count = desc_iad->bInterfaceCount; + p_desc = tu_desc_next(p_desc); // next to Interface + + // IAD's first interface number and class should match with opened interface + //TU_ASSERT(desc_iad->bFirstInterface == desc_itf->bInterfaceNumber && + // desc_iad->bFunctionClass == desc_itf->bInterfaceClass); } TU_ASSERT( TUSB_DESC_INTERFACE == tu_desc_type(p_desc) ); - tusb_desc_interface_t const * desc_itf = (tusb_desc_interface_t const*) p_desc; // Interface number must not be used already TU_ASSERT(DRVID_INVALID == _usbd_dev.itf2drv[desc_itf->bInterfaceNumber]); - uint16_t const drv_len = tu_desc_get_interface_total_len(desc_itf, desc_iad ? desc_iad->bInterfaceCount : 1, desc_end-p_desc); +#if CFG_TUD_MIDI + // MIDI has 2 interfaces (Audio Control v1 + MIDIStreaming) but does not have IAD + // manually increase the associated count + if (1 == assoc_itf_count && + TUSB_CLASS_AUDIO == desc_itf->bInterfaceClass && + AUDIO_SUBCLASS_CONTROL == desc_itf->bInterfaceSubClass && + AUDIO_FUNC_PROTOCOL_CODE_UNDEF == desc_itf->bInterfaceProtocol) + { + assoc_itf_count = 2; + } +#endif + + uint16_t const drv_len = tu_desc_get_interface_total_len(desc_itf, assoc_itf_count, desc_end-p_desc); TU_ASSERT(drv_len); // Find driver for this interface @@ -915,29 +932,18 @@ static bool process_set_config(uint8_t rhport, uint8_t cfg_num) if ( driver->open(rhport, desc_itf, drv_len) ) { - // Open successfully, check if length is correct + // Open successfully TU_LOG2(" %s opened\r\n", driver->name); - // bind interface to found driver - _usbd_dev.itf2drv[desc_itf->bInterfaceNumber] = drv_id; - - // If using IAD, bind all interfaces to the same driver - if (desc_iad) + // bind (associated) interfaces to found driver + for(uint8_t i=0; ibFirstInterface == desc_itf->bInterfaceNumber && - desc_iad->bFunctionClass == desc_itf->bInterfaceClass); - - for(uint8_t i=1; ibInterfaceCount; i++) - { - _usbd_dev.itf2drv[desc_itf->bInterfaceNumber+i] = drv_id; - } + _usbd_dev.itf2drv[desc_itf->bInterfaceNumber+i] = drv_id; } // bind all endpoints to found driver tu_edpt_bind_driver(_usbd_dev.ep2drv, desc_itf, drv_len, drv_id); - break; // exit driver find loop } } diff --git a/src/host/usbh.c b/src/host/usbh.c index 886a120a8..14e71379b 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -982,24 +982,40 @@ static bool parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configura // parse each interfaces while( p_desc < desc_end ) { - // TODO Do we need to use IAD - tusb_desc_interface_assoc_t const * desc_iad = NULL; + uint8_t assoc_itf_count = 1; // Class will always starts with Interface Association (if any) and then Interface descriptor if ( TUSB_DESC_INTERFACE_ASSOCIATION == tu_desc_type(p_desc) ) { - desc_iad = (tusb_desc_interface_assoc_t const *) p_desc; + tusb_desc_interface_assoc_t const * desc_iad = (tusb_desc_interface_assoc_t const *) p_desc; + assoc_itf_count = desc_iad->bInterfaceCount; + p_desc = tu_desc_next(p_desc); // next to Interface + + // IAD's first interface number and class should match with opened interface + //TU_ASSERT(desc_iad->bFirstInterface == desc_itf->bInterfaceNumber && + // desc_iad->bFunctionClass == desc_itf->bInterfaceClass); } TU_ASSERT( TUSB_DESC_INTERFACE == tu_desc_type(p_desc) ); - tusb_desc_interface_t const* desc_itf = (tusb_desc_interface_t const*) p_desc; // Interface number must not be used already - TU_ASSERT( dev->itf2drv[desc_itf->bInterfaceNumber] == DRVID_INVALID ); + TU_ASSERT( DRVID_INVALID == dev->itf2drv[desc_itf->bInterfaceNumber] ); + +#if CFG_TUH_MIDI + // MIDI has 2 interfaces (Audio Control v1 + MIDIStreaming) but does not have IAD + // manually increase the associated count + if (1 == assoc_itf_count && + TUSB_CLASS_AUDIO == desc_itf->bInterfaceClass && + AUDIO_SUBCLASS_CONTROL == desc_itf->bInterfaceSubClass && + AUDIO_FUNC_PROTOCOL_CODE_UNDEF == desc_itf->bInterfaceProtocol) + { + assoc_itf_count = 2; + } +#endif - uint16_t const drv_len = tu_desc_get_interface_total_len(desc_itf, desc_iad ? desc_iad->bInterfaceCount : 1, desc_end-p_desc); + uint16_t const drv_len = tu_desc_get_interface_total_len(desc_itf, assoc_itf_count, desc_end-p_desc); TU_ASSERT(drv_len); if (desc_itf->bInterfaceClass == TUSB_CLASS_HUB && dev->hub_addr != 0) @@ -1019,22 +1035,12 @@ static bool parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configura if ( driver->open(dev->rhport, dev_addr, desc_itf, drv_len) ) { // open successfully - TU_LOG2(" Opened successfully\r\n"); - - // bind interface to found driver - dev->itf2drv[desc_itf->bInterfaceNumber] = drv_id; + TU_LOG2(" %s opened\r\n", driver->name); - // If using IAD, bind all interfaces to the same driver - if (desc_iad) + // bind (associated) interfaces to found driver + for(uint8_t i=0; ibFirstInterface == desc_itf->bInterfaceNumber && - desc_iad->bFunctionClass == desc_itf->bInterfaceClass); - - for(uint8_t i=1; ibInterfaceCount; i++) - { - dev->itf2drv[desc_itf->bInterfaceNumber+i] = drv_id; - } + dev->itf2drv[desc_itf->bInterfaceNumber+i] = drv_id; } // bind all endpoints to found driver diff --git a/src/tusb.c b/src/tusb.c index 6494287d2..5c6adad24 100644 --- a/src/tusb.c +++ b/src/tusb.c @@ -121,7 +121,7 @@ void tu_edpt_bind_driver(uint8_t ep2drv[][2], tusb_desc_interface_t const* desc_ ep2drv[tu_edpt_number(ep_addr)][tu_edpt_dir(ep_addr)] = driver_id; } - len = (uint16_t)(len + tu_desc_len(p_desc)); + len += (uint16_t) tu_desc_len(p_desc); p_desc = tu_desc_next(p_desc); } } diff --git a/src/tusb_option.h b/src/tusb_option.h index a00f3489f..4d7e1e9d2 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -278,6 +278,30 @@ //------------- CLASS -------------// #endif // TUSB_OPT_HOST_ENABLED +#ifndef CFG_TUH_HUB +#define CFG_TUH_HUB 0 +#endif + +#ifndef CFG_TUH_CDC +#define CFG_TUH_CDC 0 +#endif + +#ifndef CFG_TUH_HID +#define CFG_TUH_HID 0 +#endif + +#ifndef CFG_TUH_MIDI +#define CFG_TUH_MIDI 0 +#endif + +#ifndef CFG_TUH_MSC +#define CFG_TUH_MSC 0 +#endif + +#ifndef CFG_TUH_VENDOR +#define CFG_TUH_VENDOR 0 +#endif + //--------------------------------------------------------------------+ // Port Specific // TUP stand for TinyUSB Port (can be renamed) -- cgit v1.3.1 From b4745222457d2a2c6c6e6a0747dd6082557c4c8e Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 14 Sep 2021 21:30:38 +0700 Subject: make vendor driver more flexible - skip additional custom descriptor between interface and endpoints - can have up to 2 bulk endpoint ( 1 in & 1 out) --- src/class/vendor/vendor_device.c | 38 +++++++++++++++++++++++--------------- src/device/usbd.c | 2 +- src/host/usbh.c | 2 +- 3 files changed, 25 insertions(+), 17 deletions(-) diff --git a/src/class/vendor/vendor_device.c b/src/class/vendor/vendor_device.c index 8c59b4ea7..c73ca2538 100644 --- a/src/class/vendor/vendor_device.c +++ b/src/class/vendor/vendor_device.c @@ -175,12 +175,12 @@ void vendord_reset(uint8_t rhport) } } -uint16_t vendord_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len) +uint16_t vendord_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, uint16_t max_len) { - TU_VERIFY(TUSB_CLASS_VENDOR_SPECIFIC == itf_desc->bInterfaceClass, 0); + TU_VERIFY(TUSB_CLASS_VENDOR_SPECIFIC == desc_itf->bInterfaceClass, 0); - uint16_t const drv_len = sizeof(tusb_desc_interface_t) + itf_desc->bNumEndpoints*sizeof(tusb_desc_endpoint_t); - TU_VERIFY(max_len >= drv_len, 0); + uint16_t drv_len = tu_desc_len(desc_itf); + uint8_t const * p_desc = tu_desc_next(desc_itf); // Find available interface vendord_interface_t* p_vendor = NULL; @@ -194,21 +194,29 @@ uint16_t vendord_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, ui } TU_VERIFY(p_vendor, 0); - // Open endpoint pair with usbd helper - TU_ASSERT(usbd_open_edpt_pair(rhport, tu_desc_next(itf_desc), 2, TUSB_XFER_BULK, &p_vendor->ep_out, &p_vendor->ep_in), 0); + p_vendor->itf_num = desc_itf->bInterfaceNumber; + if (desc_itf->bNumEndpoints) + { + // skip non-endpoint descriptors + while ( (TUSB_DESC_ENDPOINT != tu_desc_type(p_desc)) && (drv_len <= max_len) ) + { + drv_len += tu_desc_len(p_desc); + p_desc = tu_desc_next(p_desc); + } - p_vendor->itf_num = itf_desc->bInterfaceNumber; + // Open endpoint pair with usbd helper + TU_ASSERT(usbd_open_edpt_pair(rhport, p_desc, desc_itf->bNumEndpoints, TUSB_XFER_BULK, &p_vendor->ep_out, &p_vendor->ep_in), 0); - // Prepare for incoming data - if ( !usbd_edpt_xfer(rhport, p_vendor->ep_out, p_vendor->epout_buf, sizeof(p_vendor->epout_buf)) ) - { - TU_LOG_FAILED(); - TU_BREAKPOINT(); - } + // Prepare for incoming data + if ( p_vendor->ep_out ) + { + TU_ASSERT(usbd_edpt_xfer(rhport, p_vendor->ep_out, p_vendor->epout_buf, sizeof(p_vendor->epout_buf)), 0); + } - maybe_transmit(p_vendor); + if ( p_vendor->ep_in ) maybe_transmit(p_vendor); + } - return drv_len; + return (uint16_t) true; } bool vendord_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) diff --git a/src/device/usbd.c b/src/device/usbd.c index 2874dc5eb..f23d3048d 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -922,7 +922,7 @@ static bool process_set_config(uint8_t rhport, uint8_t cfg_num) #endif uint16_t const drv_len = tu_desc_get_interface_total_len(desc_itf, assoc_itf_count, desc_end-p_desc); - TU_ASSERT(drv_len); + TU_ASSERT(drv_len >= sizeof(tusb_desc_interface_t)); // Find driver for this interface uint8_t drv_id; diff --git a/src/host/usbh.c b/src/host/usbh.c index 14e71379b..100a17aa4 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -1016,7 +1016,7 @@ static bool parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configura #endif uint16_t const drv_len = tu_desc_get_interface_total_len(desc_itf, assoc_itf_count, desc_end-p_desc); - TU_ASSERT(drv_len); + TU_ASSERT(drv_len >= sizeof(tusb_desc_interface_t)); if (desc_itf->bInterfaceClass == TUSB_CLASS_HUB && dev->hub_addr != 0) { -- cgit v1.3.1 From a23944035dab67a206edad9e31e3ee7400b68bbb Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 15 Sep 2021 00:51:01 +0700 Subject: correct assoc_itf_count for bth driver --- src/device/usbd.c | 11 +++++++++++ src/device/usbd.h | 1 + 2 files changed, 12 insertions(+) diff --git a/src/device/usbd.c b/src/device/usbd.c index f23d3048d..f7846cc0a 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -921,6 +921,17 @@ static bool process_set_config(uint8_t rhport, uint8_t cfg_num) } #endif +#if CFG_TUD_BTH && CFG_TUD_BTH_ISO_ALT_COUNT + // BTH implementation currently does not use IAD. TODO should also use IAD for composite device + if (1 == assoc_itf_count && + TUD_BT_APP_CLASS == desc_itf->bInterfaceClass && + TUD_BT_APP_SUBCLASS == desc_itf->bInterfaceSubClass && + TUD_BT_PROTOCOL_PRIMARY_CONTROLLER == desc_itf->bInterfaceProtocol) + { + assoc_itf_count = 2; + } +#endif + uint16_t const drv_len = tu_desc_get_interface_total_len(desc_itf, assoc_itf_count, desc_end-p_desc); TU_ASSERT(drv_len >= sizeof(tusb_desc_interface_t)); diff --git a/src/device/usbd.h b/src/device/usbd.h index 638d93094..c83509234 100644 --- a/src/device/usbd.h +++ b/src/device/usbd.h @@ -777,6 +777,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb // BT Primary controller descriptor // Interface number, string index, attributes, event endpoint, event endpoint size, interval, data in, data out, data endpoint size, iso endpoint sizes +// TODO BTH should also use IAD like CDC for composite device #define TUD_BTH_DESCRIPTOR(_itfnum, _stridx, _ep_evt, _ep_evt_size, _ep_evt_interval, _ep_in, _ep_out, _ep_size,...) \ TUD_BTH_PRI_ITF(_itfnum, _stridx, _ep_evt, _ep_evt_size, _ep_evt_interval, _ep_in, _ep_out, _ep_size) \ TUD_BTH_ISO_ITFS(_itfnum + 1, _ep_in + 1, _ep_out + 1, __VA_ARGS__) -- cgit v1.3.1 From 0ded1c5bacfba180bb5f6fef2f7cb469adbe19f6 Mon Sep 17 00:00:00 2001 From: MasterPhi Date: Tue, 14 Sep 2021 21:08:12 +0200 Subject: Reset EP flags on close. --- src/device/usbd.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/device/usbd.c b/src/device/usbd.c index 1184f8e47..3043fc7bc 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -1379,7 +1379,13 @@ void usbd_edpt_close(uint8_t rhport, uint8_t ep_addr) TU_ASSERT(dcd_edpt_close, /**/); TU_LOG2(" CLOSING Endpoint: 0x%02X\r\n", ep_addr); + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + dcd_edpt_close(rhport, ep_addr); + _usbd_dev.ep_status[epnum][dir].stalled = false; + _usbd_dev.ep_status[epnum][dir].busy = false; + _usbd_dev.ep_status[epnum][dir].claimed = false; return; } -- cgit v1.3.1 From 93ed3034c01d1b7b312acf5e8c79475e0dc516f9 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 15 Sep 2021 18:35:52 +0700 Subject: merge master and minor clean up --- src/portable/nxp/khci/dcd_khci.c | 59 +++++++++++++++++++++++++++------------- 1 file changed, 40 insertions(+), 19 deletions(-) diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c index 2ba063ff2..69bd07eb0 100644 --- a/src/portable/nxp/khci/dcd_khci.c +++ b/src/portable/nxp/khci/dcd_khci.c @@ -52,23 +52,23 @@ typedef struct TU_ATTR_PACKED struct { union { struct { - uint16_t : 2; - uint16_t tok_pid : 4; - uint16_t data : 1; - uint16_t own : 1; - uint16_t : 8; + uint16_t : 2; + __IO uint16_t tok_pid : 4; + uint16_t data : 1; + __IO uint16_t own : 1; + uint16_t : 8; }; struct { - uint16_t : 2; - uint16_t bdt_stall: 1; - uint16_t dts : 1; - uint16_t ninc : 1; - uint16_t keep : 1; - uint16_t : 10; + uint16_t : 2; + uint16_t bdt_stall : 1; + uint16_t dts : 1; + uint16_t ninc : 1; + uint16_t keep : 1; + uint16_t : 10; }; }; - uint16_t bc : 10; - uint16_t : 6; + __IO uint16_t bc : 10; + uint16_t : 6; }; }; uint8_t *addr; @@ -145,12 +145,17 @@ static void process_tokdne(uint8_t rhport) { const unsigned s = KHCI->STAT; KHCI->ISTAT = USB_ISTAT_TOKDNE_MASK; /* fetch the next token if received */ + + uint8_t const epnum = (s >> USB_STAT_ENDP_SHIFT); + uint8_t const dir = (s & USB_STAT_TX_MASK) >> USB_STAT_TX_SHIFT; + buffer_descriptor_t *bd = (buffer_descriptor_t *)&_dcd.bda[s]; endpoint_state_t *ep = &_dcd.endpoint_unified[s >> 3]; unsigned odd = (s & USB_STAT_ODD_MASK) ? 1 : 0; /* fetch pid before discarded by the next steps */ const unsigned pid = bd->tok_pid; + /* reset values for a next transfer */ bd->bdt_stall = 0; bd->dts = 1; @@ -181,7 +186,7 @@ static void process_tokdne(uint8_t rhport) } const unsigned length = ep->length; dcd_event_xfer_complete(rhport, - ((s & USB_STAT_TX_MASK) << 4) | (s >> USB_STAT_ENDP_SHIFT), + tu_edpt_addr(epnum, dir), length - remaining, XFER_RESULT_SUCCESS, true); if (0 == (s & USB_STAT_ENDP_MASK) && 0 == length) { /* After completion a ZLP of control transfer, @@ -414,6 +419,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to bd->addr = buffer; __DSB(); bd->own = 1; /* This bit must be set last */ + if (ie) NVIC_EnableIRQ(USB0_IRQn); return true; } @@ -422,18 +428,22 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { (void) rhport; const unsigned epn = tu_edpt_number(ep_addr); + if (0 == epn) { KHCI->ENDPOINT[epn].ENDPT |= USB_ENDPT_EPSTALL_MASK; } else { const unsigned dir = tu_edpt_dir(ep_addr); const unsigned odd = _dcd.endpoint[epn][dir].odd; buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][odd]; - TU_VERIFY(0 == bd->own,); + TU_ASSERT(0 == bd->own,); + const unsigned ie = NVIC_GetEnableIRQ(USB0_IRQn); NVIC_DisableIRQ(USB0_IRQn); + bd->bdt_stall = 1; __DSB(); bd->own = 1; /* This bit must be set last */ + if (ie) NVIC_EnableIRQ(USB0_IRQn); } } @@ -447,15 +457,20 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) const unsigned odd = _dcd.endpoint[epn][dir].odd; buffer_descriptor_t *bd = _dcd.bdt[epn][dir]; TU_VERIFY(bd[odd].own,); + const unsigned ie = NVIC_GetEnableIRQ(USB0_IRQn); NVIC_DisableIRQ(USB0_IRQn); + bd[odd].own = 0; __DSB(); + + // clear stall bd[odd].bdt_stall = 0; - if (bd[odd].data) { - bd[odd ].data = 0; - bd[odd ^ 1].data = 1; - } + + // Reset data toggle + bd[odd ].data = 0; + bd[odd ^ 1].data = 1; + if (ie) NVIC_EnableIRQ(USB0_IRQn); } @@ -470,6 +485,7 @@ void dcd_int_handler(uint8_t rhport) uint32_t msk = KHCI->INTEN; KHCI->ISTAT = is & ~msk; is &= msk; + if (is & USB_ISTAT_ERROR_MASK) { /* TODO: */ uint32_t es = KHCI->ERRSTAT; @@ -483,26 +499,31 @@ void dcd_int_handler(uint8_t rhport) process_bus_reset(rhport); return; } + if (is & USB_ISTAT_SLEEP_MASK) { KHCI->ISTAT = USB_ISTAT_SLEEP_MASK; process_bus_inactive(rhport); return; } + if (is & USB_ISTAT_RESUME_MASK) { KHCI->ISTAT = USB_ISTAT_RESUME_MASK; process_bus_active(rhport); return; } + if (is & USB_ISTAT_SOFTOK_MASK) { KHCI->ISTAT = USB_ISTAT_SOFTOK_MASK; dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true); return; } + if (is & USB_ISTAT_STALL_MASK) { KHCI->ISTAT = USB_ISTAT_STALL_MASK; process_stall(rhport); return; } + if (is & USB_ISTAT_TOKDNE_MASK) { process_tokdne(rhport); return; -- cgit v1.3.1 From ecbe8c3376038317269c30af6d47a399e4f6b6d5 Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Mon, 13 Sep 2021 23:46:14 +0900 Subject: Change default LED state to off --- hw/bsp/frdm_kl25z/frdm_kl25z.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/bsp/frdm_kl25z/frdm_kl25z.c b/hw/bsp/frdm_kl25z/frdm_kl25z.c index 7d3a173ed..7cfbaab85 100644 --- a/hw/bsp/frdm_kl25z/frdm_kl25z.c +++ b/hw/bsp/frdm_kl25z/frdm_kl25z.c @@ -84,7 +84,7 @@ void board_init(void) PORT_SetPinMux(LED_PIN_PORT, LED_PIN, LED_PIN_FUNCTION); gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 0 }; GPIO_PinInit(LED_PORT, LED_PIN, &led_config); - board_led_write(true); + board_led_write(false); // UART CLOCK_EnableClock(UART_PIN_CLOCK); -- cgit v1.3.1 From 46bb821753e677e5048f31c07fb26e2427f79ac2 Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Wed, 15 Sep 2021 20:21:30 +0900 Subject: Add J1-19 pin setting as a button --- hw/bsp/frdm_kl25z/frdm_kl25z.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/hw/bsp/frdm_kl25z/frdm_kl25z.c b/hw/bsp/frdm_kl25z/frdm_kl25z.c index 7cfbaab85..cdc996bc2 100644 --- a/hw/bsp/frdm_kl25z/frdm_kl25z.c +++ b/hw/bsp/frdm_kl25z/frdm_kl25z.c @@ -54,6 +54,14 @@ void USB0_IRQHandler(void) #define LED_PIN_FUNCTION kPORT_MuxAsGpio #define LED_STATE_ON 0 +// Button +#define BUTTON_PORT GPIOC +#define BUTTON_PIN_CLOCK kCLOCK_PortC +#define BUTTON_PIN_PORT PORTC +#define BUTTON_PIN 9U +#define BUTTON_PIN_FUNCTION kPORT_MuxAsGpio +#define BUTTON_STATE_ACTIVE 0 + // UART #define UART_PORT UART0 #define UART_PIN_CLOCK kCLOCK_PortA @@ -86,6 +94,18 @@ void board_init(void) GPIO_PinInit(LED_PORT, LED_PIN, &led_config); board_led_write(false); +#if defined(BUTTON_PORT) && defined(BUTTON_PIN) + // Button + CLOCK_EnableClock(BUTTON_PIN_CLOCK); + port_pin_config_t button_port = { + .pullSelect = kPORT_PullUp, + .mux = BUTTON_PIN_FUNCTION, + }; + PORT_SetPinConfig(BUTTON_PIN_PORT, BUTTON_PIN, &button_port); + gpio_pin_config_t button_config = { kGPIO_DigitalInput, 0 }; + GPIO_PinInit(BUTTON_PORT, BUTTON_PIN, &button_config); +#endif + // UART CLOCK_EnableClock(UART_PIN_CLOCK); PORT_SetPinMux(UART_PIN_PORT, UART_PIN_RX, UART_PIN_FUNCTION); @@ -119,6 +139,9 @@ void board_led_write(bool state) uint32_t board_button_read(void) { +#if defined(BUTTON_PORT) && defined(BUTTON_PIN) + return BUTTON_STATE_ACTIVE == GPIO_ReadPinInput(BUTTON_PORT, BUTTON_PIN); +#endif return 0; } -- cgit v1.3.1 From fbe1bf375c8240e2d97683346fedd1a557cafdc0 Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Wed, 15 Sep 2021 21:28:36 +0900 Subject: Fix stall interrupt handling --- src/portable/nxp/khci/dcd_khci.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c index 69bd07eb0..1c3af3433 100644 --- a/src/portable/nxp/khci/dcd_khci.c +++ b/src/portable/nxp/khci/dcd_khci.c @@ -134,10 +134,20 @@ static void prepare_next_setup_packet(uint8_t rhport) static void process_stall(uint8_t rhport) { - if (KHCI->ENDPOINT[0].ENDPT & USB_ENDPT_EPSTALL_MASK) { + unsigned endpt; + endpt = KHCI->ENDPOINT[0].ENDPT; + if (endpt & USB_ENDPT_EPSTALL_MASK) { /* clear stall condition of the control pipe */ prepare_next_setup_packet(rhport); - KHCI->ENDPOINT[0].ENDPT &= ~USB_ENDPT_EPSTALL_MASK; + KHCI->ENDPOINT[0].ENDPT = endpt & ~USB_ENDPT_EPSTALL_MASK; + return; + } + for (int i = 1; i < 16; ++i) { + endpt = KHCI->ENDPOINT[i].ENDPT; + if (endpt & USB_ENDPT_EPSTALL_MASK) { + KHCI->ENDPOINT[i].ENDPT = endpt & ~USB_ENDPT_EPSTALL_MASK; + return; + } } } @@ -471,6 +481,9 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) bd[odd ].data = 0; bd[odd ^ 1].data = 1; + const unsigned endpt = KHCI->ENDPOINT[epn].ENDPT; + if (endpt & USB_ENDPT_EPSTALL_MASK) + KHCI->ENDPOINT[epn].ENDPT = endpt & ~USB_ENDPT_EPSTALL_MASK; if (ie) NVIC_EnableIRQ(USB0_IRQn); } -- cgit v1.3.1 From 8dfe0898e7daa551d7d320df5398ef92a4b28ea3 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 17 Sep 2021 00:43:10 +0700 Subject: minor update to dcd khci --- src/portable/nxp/khci/dcd_khci.c | 83 +++++++++++++++++++++------------------- 1 file changed, 43 insertions(+), 40 deletions(-) diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c index 1c3af3433..3a62ff01e 100644 --- a/src/portable/nxp/khci/dcd_khci.c +++ b/src/portable/nxp/khci/dcd_khci.c @@ -120,10 +120,8 @@ static void prepare_next_setup_packet(uint8_t rhport) { const unsigned out_odd = _dcd.endpoint[0][0].odd; const unsigned in_odd = _dcd.endpoint[0][1].odd; - if (_dcd.bdt[0][0][out_odd].own) { - // TU_LOG1("DCD fail to prepare the next SETUP %d %d\r\n", out_odd, in_odd); - return; - } + TU_ASSERT(0 == _dcd.bdt[0][0][out_odd].own, ); + _dcd.bdt[0][0][out_odd].data = 0; _dcd.bdt[0][0][out_odd ^ 1].data = 1; _dcd.bdt[0][1][in_odd].data = 1; @@ -134,19 +132,15 @@ static void prepare_next_setup_packet(uint8_t rhport) static void process_stall(uint8_t rhport) { - unsigned endpt; - endpt = KHCI->ENDPOINT[0].ENDPT; - if (endpt & USB_ENDPT_EPSTALL_MASK) { - /* clear stall condition of the control pipe */ - prepare_next_setup_packet(rhport); - KHCI->ENDPOINT[0].ENDPT = endpt & ~USB_ENDPT_EPSTALL_MASK; - return; - } - for (int i = 1; i < 16; ++i) { - endpt = KHCI->ENDPOINT[i].ENDPT; + for (int i = 0; i < 16; ++i) { + unsigned const endpt = KHCI->ENDPOINT[i].ENDPT; + if (endpt & USB_ENDPT_EPSTALL_MASK) { + // prepare next setup if endpoint0 + if ( i == 0 ) prepare_next_setup_packet(rhport); + + // clear stall bit KHCI->ENDPOINT[i].ENDPT = endpt & ~USB_ENDPT_EPSTALL_MASK; - return; } } } @@ -158,10 +152,10 @@ static void process_tokdne(uint8_t rhport) uint8_t const epnum = (s >> USB_STAT_ENDP_SHIFT); uint8_t const dir = (s & USB_STAT_TX_MASK) >> USB_STAT_TX_SHIFT; + unsigned const odd = (s & USB_STAT_ODD_MASK) ? 1 : 0; buffer_descriptor_t *bd = (buffer_descriptor_t *)&_dcd.bda[s]; endpoint_state_t *ep = &_dcd.endpoint_unified[s >> 3]; - unsigned odd = (s & USB_STAT_ODD_MASK) ? 1 : 0; /* fetch pid before discarded by the next steps */ const unsigned pid = bd->tok_pid; @@ -241,21 +235,27 @@ static void process_bus_reset(uint8_t rhport) dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true); } -static void process_bus_inactive(uint8_t rhport) +static void process_bus_sleep(uint8_t rhport) { - (void) rhport; + // Enable resume & disable suspend interrupt const unsigned inten = KHCI->INTEN; + KHCI->INTEN = (inten & ~USB_INTEN_SLEEPEN_MASK) | USB_INTEN_RESUMEEN_MASK; + //KHCI->USBTRC0 |= USB_USBTRC0_USBRESMEN_MASK; KHCI->USBCTRL |= USB_USBCTRL_SUSP_MASK; + dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); } -static void process_bus_active(uint8_t rhport) +static void process_bus_resume(uint8_t rhport) { - (void) rhport; - KHCI->USBCTRL &= ~USB_USBCTRL_SUSP_MASK; + // Enable suspend & disable resume interrupt const unsigned inten = KHCI->INTEN; + + KHCI->USBCTRL &= ~USB_USBCTRL_SUSP_MASK; + //KHCI->USBTRC0 &= ~USB_USBTRC0_USBRESMEN_MASK; KHCI->INTEN = (inten & ~USB_INTEN_RESUMEEN_MASK) | USB_INTEN_SLEEPEN_MASK; + dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true); } @@ -268,12 +268,16 @@ void dcd_init(uint8_t rhport) KHCI->USBTRC0 |= USB_USBTRC0_USBRESET_MASK; while (KHCI->USBTRC0 & USB_USBTRC0_USBRESET_MASK); + tu_memclr(&_dcd, sizeof(_dcd)); KHCI->USBTRC0 |= TU_BIT(6); /* software must set this bit to 1 */ KHCI->BDTPAGE1 = (uint8_t)((uintptr_t)_dcd.bdt >> 8); KHCI->BDTPAGE2 = (uint8_t)((uintptr_t)_dcd.bdt >> 16); KHCI->BDTPAGE3 = (uint8_t)((uintptr_t)_dcd.bdt >> 24); + KHCI->INTEN = USB_INTEN_USBRSTEN_MASK | USB_INTEN_TOKDNEEN_MASK | + USB_INTEN_SLEEPEN_MASK | USB_INTEN_ERROREN_MASK | USB_INTEN_STALLEN_MASK; + dcd_connect(rhport); NVIC_ClearPendingIRQ(USB0_IRQn); } @@ -281,8 +285,6 @@ void dcd_init(uint8_t rhport) void dcd_int_enable(uint8_t rhport) { (void) rhport; - KHCI->INTEN = USB_INTEN_USBRSTEN_MASK | USB_INTEN_TOKDNEEN_MASK | - USB_INTEN_SLEEPEN_MASK | USB_INTEN_ERROREN_MASK | USB_INTEN_STALLEN_MASK; NVIC_EnableIRQ(USB0_IRQn); } @@ -290,23 +292,24 @@ void dcd_int_disable(uint8_t rhport) { (void) rhport; NVIC_DisableIRQ(USB0_IRQn); - KHCI->INTEN = 0; } void dcd_set_address(uint8_t rhport, uint8_t dev_addr) { - (void) rhport; - _dcd.addr = dev_addr & 0x7F; - /* Response with status first before changing device address */ + _dcd.addr = dev_addr & 0x7F; + /* Response with status first before changing device address */ dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0); } void dcd_remote_wakeup(uint8_t rhport) { (void) rhport; - unsigned cnt = SystemCoreClock / 100; + KHCI->CTL |= USB_CTL_RESUME_MASK; + + unsigned cnt = SystemCoreClock / 1000; while (cnt--) __NOP(); + KHCI->CTL &= ~USB_CTL_RESUME_MASK; } @@ -481,9 +484,12 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) bd[odd ].data = 0; bd[odd ^ 1].data = 1; + // We already cleared this in ISR, but just clear it here to be safe const unsigned endpt = KHCI->ENDPOINT[epn].ENDPT; - if (endpt & USB_ENDPT_EPSTALL_MASK) + if (endpt & USB_ENDPT_EPSTALL_MASK) { KHCI->ENDPOINT[epn].ENDPT = endpt & ~USB_ENDPT_EPSTALL_MASK; + } + if (ie) NVIC_EnableIRQ(USB0_IRQn); } @@ -492,10 +498,10 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) //--------------------------------------------------------------------+ void dcd_int_handler(uint8_t rhport) { - (void) rhport; - uint32_t is = KHCI->ISTAT; uint32_t msk = KHCI->INTEN; + + // clear non-enabled interrupts KHCI->ISTAT = is & ~msk; is &= msk; @@ -504,42 +510,39 @@ void dcd_int_handler(uint8_t rhport) uint32_t es = KHCI->ERRSTAT; KHCI->ERRSTAT = es; KHCI->ISTAT = is; /* discard any pending events */ - return; } if (is & USB_ISTAT_USBRST_MASK) { KHCI->ISTAT = is; /* discard any pending events */ process_bus_reset(rhport); - return; } if (is & USB_ISTAT_SLEEP_MASK) { + TU_LOG_LOCATION(); + TU_LOG2_HEX(is); KHCI->ISTAT = USB_ISTAT_SLEEP_MASK; - process_bus_inactive(rhport); - return; + process_bus_sleep(rhport); } if (is & USB_ISTAT_RESUME_MASK) { + TU_LOG_LOCATION(); + TU_LOG2_HEX(is); KHCI->ISTAT = USB_ISTAT_RESUME_MASK; - process_bus_active(rhport); - return; + process_bus_resume(rhport); } if (is & USB_ISTAT_SOFTOK_MASK) { KHCI->ISTAT = USB_ISTAT_SOFTOK_MASK; dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true); - return; } if (is & USB_ISTAT_STALL_MASK) { KHCI->ISTAT = USB_ISTAT_STALL_MASK; process_stall(rhport); - return; } if (is & USB_ISTAT_TOKDNE_MASK) { process_tokdne(rhport); - return; } } -- cgit v1.3.1 From c65cc75c6b9369a384e3266ce28ea043607230d2 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 17 Sep 2021 00:44:39 +0700 Subject: use correct resume detection for kl25z --- src/portable/nxp/khci/dcd_khci.c | 30 +++++++++++++++++++----------- 1 file changed, 19 insertions(+), 11 deletions(-) diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c index 3a62ff01e..3bb40aeb2 100644 --- a/src/portable/nxp/khci/dcd_khci.c +++ b/src/portable/nxp/khci/dcd_khci.c @@ -210,7 +210,8 @@ static void process_bus_reset(uint8_t rhport) KHCI->USBCTRL &= ~USB_USBCTRL_SUSP_MASK; KHCI->CTL |= USB_CTL_ODDRST_MASK; KHCI->ADDR = 0; - KHCI->INTEN = (KHCI->INTEN & ~USB_INTEN_RESUMEEN_MASK) | USB_INTEN_SLEEPEN_MASK; + KHCI->INTEN = USB_INTEN_USBRSTEN_MASK | USB_INTEN_TOKDNEEN_MASK | USB_INTEN_SLEEPEN_MASK | + USB_INTEN_ERROREN_MASK | USB_INTEN_STALLEN_MASK; KHCI->ENDPOINT[0].ENDPT = USB_ENDPT_EPHSHK_MASK | USB_ENDPT_EPRXEN_MASK | USB_ENDPT_EPTXEN_MASK; for (unsigned i = 1; i < 16; ++i) { @@ -241,7 +242,7 @@ static void process_bus_sleep(uint8_t rhport) const unsigned inten = KHCI->INTEN; KHCI->INTEN = (inten & ~USB_INTEN_SLEEPEN_MASK) | USB_INTEN_RESUMEEN_MASK; - //KHCI->USBTRC0 |= USB_USBTRC0_USBRESMEN_MASK; + KHCI->USBTRC0 |= USB_USBTRC0_USBRESMEN_MASK; KHCI->USBCTRL |= USB_USBCTRL_SUSP_MASK; dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); @@ -252,8 +253,8 @@ static void process_bus_resume(uint8_t rhport) // Enable suspend & disable resume interrupt const unsigned inten = KHCI->INTEN; - KHCI->USBCTRL &= ~USB_USBCTRL_SUSP_MASK; - //KHCI->USBTRC0 &= ~USB_USBTRC0_USBRESMEN_MASK; + KHCI->USBCTRL &= ~USB_USBCTRL_SUSP_MASK; // will also clear USB_USBTRC0_USB_RESUME_INT_MASK + KHCI->USBTRC0 &= ~USB_USBTRC0_USBRESMEN_MASK; KHCI->INTEN = (inten & ~USB_INTEN_RESUMEEN_MASK) | USB_INTEN_SLEEPEN_MASK; dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true); @@ -275,8 +276,7 @@ void dcd_init(uint8_t rhport) KHCI->BDTPAGE2 = (uint8_t)((uintptr_t)_dcd.bdt >> 16); KHCI->BDTPAGE3 = (uint8_t)((uintptr_t)_dcd.bdt >> 24); - KHCI->INTEN = USB_INTEN_USBRSTEN_MASK | USB_INTEN_TOKDNEEN_MASK | - USB_INTEN_SLEEPEN_MASK | USB_INTEN_ERROREN_MASK | USB_INTEN_STALLEN_MASK; + KHCI->INTEN = USB_INTEN_USBRSTEN_MASK; dcd_connect(rhport); NVIC_ClearPendingIRQ(USB0_IRQn); @@ -297,7 +297,7 @@ void dcd_int_disable(uint8_t rhport) void dcd_set_address(uint8_t rhport, uint8_t dev_addr) { _dcd.addr = dev_addr & 0x7F; - /* Response with status first before changing device address */ + /* Response with status first before changing device address */ dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0); } @@ -518,18 +518,26 @@ void dcd_int_handler(uint8_t rhport) } if (is & USB_ISTAT_SLEEP_MASK) { - TU_LOG_LOCATION(); - TU_LOG2_HEX(is); + // TU_LOG2("Suspend: "); TU_LOG2_HEX(is); + + // Note Host usually has extra delay after bus reset (without SOF), which could falsely + // detected as Sleep event. Though usbd has debouncing logic so we are good KHCI->ISTAT = USB_ISTAT_SLEEP_MASK; process_bus_sleep(rhport); } +#if 0 // ISTAT_RESUME never trigger, probably for host mode ? if (is & USB_ISTAT_RESUME_MASK) { - TU_LOG_LOCATION(); - TU_LOG2_HEX(is); + // TU_LOG2("ISTAT Resume: "); TU_LOG2_HEX(is); KHCI->ISTAT = USB_ISTAT_RESUME_MASK; process_bus_resume(rhport); } +#endif + + if (KHCI->USBTRC0 & USB_USBTRC0_USB_RESUME_INT_MASK) { + // TU_LOG2("USBTRC0 Resume: "); TU_LOG2_HEX(is); TU_LOG2_HEX(KHCI->USBTRC0); + process_bus_resume(rhport); + } if (is & USB_ISTAT_SOFTOK_MASK) { KHCI->ISTAT = USB_ISTAT_SOFTOK_MASK; -- cgit v1.3.1 From b363afc091b1cccafd7ebaf6365a6f655037d986 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 17 Sep 2021 00:46:29 +0700 Subject: minor clean up --- src/portable/nxp/khci/dcd_khci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c index 3bb40aeb2..ff1997440 100644 --- a/src/portable/nxp/khci/dcd_khci.c +++ b/src/portable/nxp/khci/dcd_khci.c @@ -192,7 +192,7 @@ static void process_tokdne(uint8_t rhport) dcd_event_xfer_complete(rhport, tu_edpt_addr(epnum, dir), length - remaining, XFER_RESULT_SUCCESS, true); - if (0 == (s & USB_STAT_ENDP_MASK) && 0 == length) { + if (0 == epnum && 0 == length) { /* After completion a ZLP of control transfer, * it prepares for the next steup transfer. */ if (_dcd.addr) { -- cgit v1.3.1 From 6d8677a78ab4973ff498ec2fe8ea40a1cde230a1 Mon Sep 17 00:00:00 2001 From: Jerzy Kasenberg Date: Fri, 17 Sep 2021 11:41:58 +0200 Subject: dcd_da146xx: Add VBUS handling DA146xx are Bluetooth devices that may be battery powered and when not connected to USB host there is no need for USB peripheral to be running. This change allows to enable USB peripheral when VBUS is present otherwise USB is down reducing power consumption. tud_vsub_changed() function must be called whenever VBUS change was detected. For bus-powered devices this function should be called at startup since VBUS must be present while device is working. --- src/portable/dialog/da146xx/dcd_da146xx.c | 67 +++++++++++++++++++++++-------- 1 file changed, 51 insertions(+), 16 deletions(-) diff --git a/src/portable/dialog/da146xx/dcd_da146xx.c b/src/portable/dialog/da146xx/dcd_da146xx.c index 7b0d8f86c..112cdb502 100644 --- a/src/portable/dialog/da146xx/dcd_da146xx.c +++ b/src/portable/dialog/da146xx/dcd_da146xx.c @@ -217,6 +217,7 @@ typedef struct { static struct { bool vbus_present; + bool init_called; bool in_reset; xfer_ctl_t xfer_status[EP_MAX][2]; // Endpoints that use DMA, one for each direction @@ -224,6 +225,7 @@ static struct } _dcd = { .vbus_present = false, + .init_called = false, .xfer_status = { { { .regs = EP_REGS(USB_EPC0_REG) }, { .regs = EP_REGS(USB_EPC0_REG) } }, @@ -735,19 +737,13 @@ static void handle_ep0_nak(void) *------------------------------------------------------------------*/ void dcd_init(uint8_t rhport) { - USB->USB_MCTRL_REG = USB_USB_MCTRL_REG_USBEN_Msk; - USB->USB_NFSR_REG = 0; - USB->USB_FAR_REG = 0x80; - USB->USB_NFSR_REG = NFSR_NODE_RESET; - USB->USB_TXMSK_REG = 0; - USB->USB_RXMSK_REG = 0; - - USB->USB_MAMSK_REG = USB_USB_MAMSK_REG_USB_M_INTR_Msk | - USB_USB_MAMSK_REG_USB_M_ALT_Msk | - USB_USB_MAMSK_REG_USB_M_WARN_Msk; - USB->USB_ALTMSK_REG = USB_USB_ALTMSK_REG_USB_M_RESET_Msk; + (void) rhport; - dcd_connect(rhport); + _dcd.init_called = true; + if (_dcd.vbus_present) + { + dcd_connect(rhport); + } } void dcd_int_enable(uint8_t rhport) @@ -783,10 +779,25 @@ void dcd_connect(uint8_t rhport) { (void)rhport; - REG_SET_BIT(USB_MCTRL_REG, USB_NAT); - - // Select chosen DMA to be triggered by USB. - DMA->DMA_REQ_MUX_REG = (DMA->DMA_REQ_MUX_REG & ~DA146XX_DMA_USB_MUX_MASK) | DA146XX_DMA_USB_MUX; + if (GET_BIT(USB->USB_MCTRL_REG, USB_USB_MCTRL_REG_USB_NAT) == 0) + { + USB->USB_MCTRL_REG = USB_USB_MCTRL_REG_USBEN_Msk; + USB->USB_NFSR_REG = 0; + USB->USB_FAR_REG = 0x80; + USB->USB_NFSR_REG = NFSR_NODE_RESET; + USB->USB_TXMSK_REG = 0; + USB->USB_RXMSK_REG = 0; + + USB->USB_MAMSK_REG = USB_USB_MAMSK_REG_USB_M_INTR_Msk | + USB_USB_MAMSK_REG_USB_M_ALT_Msk | + USB_USB_MAMSK_REG_USB_M_WARN_Msk; + USB->USB_ALTMSK_REG = USB_USB_ALTMSK_REG_USB_M_RESET_Msk; + + REG_SET_BIT(USB_MCTRL_REG, USB_NAT); + + // Select chosen DMA to be triggered by USB. + DMA->DMA_REQ_MUX_REG = (DMA->DMA_REQ_MUX_REG & ~DA146XX_DMA_USB_MUX_MASK) | DA146XX_DMA_USB_MUX; + } } void dcd_disconnect(uint8_t rhport) @@ -796,6 +807,30 @@ void dcd_disconnect(uint8_t rhport) REG_CLR_BIT(USB_MCTRL_REG, USB_NAT); } +TU_ATTR_ALWAYS_INLINE static inline bool is_in_isr(void) +{ + return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) != 0; +} + +void tusb_vbus_changed(bool present) +{ + if (present && !_dcd.vbus_present) + { + _dcd.vbus_present = true; + // If power event happened before USB started, delay dcd_connect + // until dcd_init is called. + if (_dcd.init_called) + { + dcd_connect(0); + } + } + else if (!present && _dcd.vbus_present) + { + _dcd.vbus_present = false; + USB->USB_MCTRL_REG = 0; + dcd_event_bus_signal(0, DCD_EVENT_UNPLUGGED, is_in_isr()); + } +} /*------------------------------------------------------------------*/ /* DCD Endpoint port -- cgit v1.3.1 From a71ac71d7f9fda4f72b02148a194987821864fa4 Mon Sep 17 00:00:00 2001 From: Jerzy Kasenberg Date: Fri, 17 Sep 2021 11:48:38 +0200 Subject: da1469x_dk_xxx: Add VBUS handling Two BSPs with DA146xx MCUs are now adopted to VBUS handling changed introduced to dcd_da146xx driver. da14695_dk_usb as bus-powered devices informs driver that VBUS is present at startup. da1469x-dk-pro has VBUS change interrupt handler that informs driver about VBUS changes. --- hw/bsp/da14695_dk_usb/da14695_dk_usb.c | 9 ++++++++- hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c | 26 +++++++++++++++++++++++++- 2 files changed, 33 insertions(+), 2 deletions(-) diff --git a/hw/bsp/da14695_dk_usb/da14695_dk_usb.c b/hw/bsp/da14695_dk_usb/da14695_dk_usb.c index e7c7ae364..bdb30e0e5 100644 --- a/hw/bsp/da14695_dk_usb/da14695_dk_usb.c +++ b/hw/bsp/da14695_dk_usb/da14695_dk_usb.c @@ -53,6 +53,9 @@ void UnhandledIRQ(void) while(1); } +// DA146xx driver function that must be called whenever VBUS changes. +extern void tusb_vbus_changed(bool present); + void board_init(void) { // LED @@ -70,7 +73,10 @@ void board_init(void) // 1ms tick timer SysTick_Config(SystemCoreClock / 1000); - NVIC_SetPriority(USB_IRQn, 2); +#if TUSB_OPT_DEVICE_ENABLED + // This board is USB powered there is no need to monitor + // VBUS line. Notify driver that VBUS is present. + tusb_vbus_changed(true); /* Setup USB IRQ */ NVIC_SetPriority(USB_IRQn, 2); @@ -81,6 +87,7 @@ void board_init(void) mcu_gpio_set_pin_function(14, MCU_GPIO_MODE_INPUT, MCU_GPIO_FUNC_USB); mcu_gpio_set_pin_function(15, MCU_GPIO_MODE_INPUT, MCU_GPIO_FUNC_USB); +#endif } //--------------------------------------------------------------------+ diff --git a/hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c b/hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c index 85fa17152..2b6931e4e 100644 --- a/hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c +++ b/hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c @@ -36,6 +36,21 @@ void USB_IRQHandler(void) tud_int_handler(0); } +#if TUSB_OPT_DEVICE_ENABLED +// DA146xx driver function that must be called whenever VBUS changes +extern void tusb_vbus_changed(bool present); + +// VBUS change interrupt handler +void VBUS_IRQHandler(void) +{ + bool present = (CRG_TOP->ANA_STATUS_REG & CRG_TOP_ANA_STATUS_REG_VBUS_AVAILABLE_Msk) != 0; + // Clear VBUS interrupt + CRG_TOP->VBUS_IRQ_CLEAR_REG = 1; + + tusb_vbus_changed(present); +} +#endif + //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ @@ -70,7 +85,15 @@ void board_init(void) // 1ms tick timer SysTick_Config(SystemCoreClock / 1000); - NVIC_SetPriority(USB_IRQn, 2); +#if TUSB_OPT_DEVICE_ENABLED + // Setup interrupt for both connect and disconnect + CRG_TOP->VBUS_IRQ_MASK_REG = CRG_TOP_VBUS_IRQ_MASK_REG_VBUS_IRQ_EN_FALL_Msk | + CRG_TOP_VBUS_IRQ_MASK_REG_VBUS_IRQ_EN_RISE_Msk; + NVIC_SetPriority(VBUS_IRQn, 2); + // Trigger interrupt at the start to inform driver about VBUS state at start + // otherwise it could go unnoticed. + NVIC_SetPendingIRQ(VBUS_IRQn); + NVIC_EnableIRQ(VBUS_IRQn); /* Setup USB IRQ */ NVIC_SetPriority(USB_IRQn, 2); @@ -81,6 +104,7 @@ void board_init(void) mcu_gpio_set_pin_function(14, MCU_GPIO_MODE_INPUT, MCU_GPIO_FUNC_USB); mcu_gpio_set_pin_function(15, MCU_GPIO_MODE_INPUT, MCU_GPIO_FUNC_USB); +#endif } //--------------------------------------------------------------------+ -- cgit v1.3.1 From 2499c9382d4ff0d67106f6dc6cd4a9dfbd0be20e Mon Sep 17 00:00:00 2001 From: Scott Shawcroft Date: Fri, 17 Sep 2021 16:51:34 -0700 Subject: rpi start. doesn't work --- hw/bsp/raspberrypi4/boards/raspberrypi_cm4/board.h | 38 + .../raspberrypi4/boards/raspberrypi_cm4/board.mk | 0 hw/bsp/raspberrypi4/family.c | 151 ++ hw/bsp/raspberrypi4/family.mk | 37 + hw/mcu/broadcom/bcm2711/boot.s | 170 +++ hw/mcu/broadcom/bcm2711/interrupts.c | 26 + hw/mcu/broadcom/bcm2711/interrupts.h | 8 + hw/mcu/broadcom/bcm2711/io.c | 168 +++ hw/mcu/broadcom/bcm2711/io.h | 13 + hw/mcu/broadcom/bcm2711/link.ld | 20 + src/class/msc/msc_device.c | 6 +- src/device/dcd_attr.h | 4 + src/portable/broadcom/synopsys/dcd_synopsys.c | 1212 ++++++++++++++++ src/portable/broadcom/synopsys/synopsys_common.h | 1465 ++++++++++++++++++++ src/tusb_option.h | 3 + 15 files changed, 3318 insertions(+), 3 deletions(-) create mode 100644 hw/bsp/raspberrypi4/boards/raspberrypi_cm4/board.h create mode 100644 hw/bsp/raspberrypi4/boards/raspberrypi_cm4/board.mk create mode 100644 hw/bsp/raspberrypi4/family.c create mode 100644 hw/bsp/raspberrypi4/family.mk create mode 100644 hw/mcu/broadcom/bcm2711/boot.s create mode 100644 hw/mcu/broadcom/bcm2711/interrupts.c create mode 100644 hw/mcu/broadcom/bcm2711/interrupts.h create mode 100644 hw/mcu/broadcom/bcm2711/io.c create mode 100644 hw/mcu/broadcom/bcm2711/io.h create mode 100644 hw/mcu/broadcom/bcm2711/link.ld create mode 100644 src/portable/broadcom/synopsys/dcd_synopsys.c create mode 100644 src/portable/broadcom/synopsys/synopsys_common.h diff --git a/hw/bsp/raspberrypi4/boards/raspberrypi_cm4/board.h b/hw/bsp/raspberrypi4/boards/raspberrypi_cm4/board.h new file mode 100644 index 000000000..1d3565d5c --- /dev/null +++ b/hw/bsp/raspberrypi4/boards/raspberrypi_cm4/board.h @@ -0,0 +1,38 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/raspberrypi4/boards/raspberrypi_cm4/board.mk b/hw/bsp/raspberrypi4/boards/raspberrypi_cm4/board.mk new file mode 100644 index 000000000..e69de29bb diff --git a/hw/bsp/raspberrypi4/family.c b/hw/bsp/raspberrypi4/family.c new file mode 100644 index 000000000..b2665f42d --- /dev/null +++ b/hw/bsp/raspberrypi4/family.c @@ -0,0 +1,151 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "bsp/board.h" +#include "board.h" + +#include "io.h" + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void OTG_FS_IRQHandler(void) +{ + tud_int_handler(0); +} + +//--------------------------------------------------------------------+ +// MACRO TYPEDEF CONSTANT ENUM +//--------------------------------------------------------------------+ + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +void print(void) { + const char* greeting2 = "hello from cm100\r\n"; + board_uart_write(greeting2, strlen(greeting2)); +} + +void board_init(void) +{ + gpio_initOutputPinWithPullNone(18); + gpio_setPinOutputBool(18, true); + gpio_initOutputPinWithPullNone(42); + // gpio_initOutputPinWithPullNone(23); + // gpio_initOutputPinWithPullNone(24); + // gpio_initOutputPinWithPullNone(25); + gpio_setPinOutputBool(18, false); + uart_init(); + gpio_setPinOutputBool(18, true); + const char* greeting = "hello to gdb2\r\n"; + gpio_setPinOutputBool(18, false); + for (size_t i = 0; i < 5; i++) { + // while (true) { + for (size_t j = 0; j < 1000000; j++) { + __asm__("nop"); + } + gpio_setPinOutputBool(42, true); + gpio_setPinOutputBool(18, true); + for (size_t j = 0; j < 1000000; j++) { + __asm__("nop"); + } + gpio_setPinOutputBool(42, false); + gpio_setPinOutputBool(18, false); + } + // uart_writeText("hello from io\n"); + // gpio_setPinOutputBool(24, true); + board_uart_write(greeting, strlen(greeting)); + // gpio_setPinOutputBool(24, false); + // gpio_setPinOutputBool(25, true); + print(); + // gpio_setPinOutputBool(25, false); + while (true) { + // for (size_t i = 0; i < 5; i++) { + for (size_t j = 0; j < 10000000000; j++) { + __asm__("nop"); + } + gpio_setPinOutputBool(42, true); + for (size_t j = 0; j < 10000000000; j++) { + __asm__("nop"); + } + gpio_setPinOutputBool(42, false); + } + // while (1) uart_update(); +} + +void board_led_write(bool state) +{ + gpio_setPinOutputBool(42, state); +} + +uint32_t board_button_read(void) +{ + return 0; +} + +int board_uart_read(uint8_t* buf, int len) +{ + (void) buf; (void) len; + return 0; +} + +int board_uart_write(void const * buf, int len) +{ + for (int i = 0; i < len; i++) { + const char* cbuf = buf; + if (cbuf[i] == '\n') { + uart_writeByteBlockingActual('\r'); + } + uart_writeByteBlockingActual(cbuf[i]); + } + return len; +} + +#if CFG_TUSB_OS == OPT_OS_NONE +volatile uint32_t system_ticks = 0; +void SysTick_Handler (void) +{ + system_ticks++; +} + +uint32_t board_millis(void) +{ + return system_ticks; +} +#endif + +void HardFault_Handler (void) +{ + // asm("bkpt"); +} + +// Required by __libc_init_array in startup code if we are compiling using +// -nostdlib/-nostartfiles. +void _init(void) +{ + +} diff --git a/hw/bsp/raspberrypi4/family.mk b/hw/bsp/raspberrypi4/family.mk new file mode 100644 index 000000000..2d5c78d22 --- /dev/null +++ b/hw/bsp/raspberrypi4/family.mk @@ -0,0 +1,37 @@ +UF2_FAMILY_ID = 0x57755a57 + +include $(TOP)/$(BOARD_PATH)/board.mk + +MCU_DIR = hw/mcu/broadcom/bcm2711 + +CC = clang + +CFLAGS += \ + -Wall \ + -O0 \ + -ffreestanding \ + -nostdlib \ + -nostartfiles \ + -std=c17 \ + -mgeneral-regs-only \ + -DCFG_TUSB_MCU=OPT_MCU_BCM2711 + +SRC_C += \ + src/portable/broadcom/synopsys/dcd_synopsys.c \ + $(MCU_DIR)/io.c \ + $(MCU_DIR)/interrupts.c + +CROSS_COMPILE = aarch64-none-elf- + +SKIP_NANOLIB = 1 + +LD_FILE = $(MCU_DIR)/link.ld + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/$(MCU_DIR) + +SRC_S += $(MCU_DIR)/boot.S + +$(BUILD)/kernel8.img: $(BUILD)/$(PROJECT).elf + $(OBJCOPY) -O binary $^ $@ diff --git a/hw/mcu/broadcom/bcm2711/boot.s b/hw/mcu/broadcom/bcm2711/boot.s new file mode 100644 index 000000000..076b3a76a --- /dev/null +++ b/hw/mcu/broadcom/bcm2711/boot.s @@ -0,0 +1,170 @@ +.section ".text.boot" // Make sure the linker puts this at the start of the kernel image + +.global _start // Execution starts here + +_start: + // Check processor ID is zero (executing on main core), else hang + mrs x1, mpidr_el1 + and x1, x1, #3 + cbz x1, 2f + // We're not on the main core, so hang in an infinite wait loop +1: wfe + b 1b +2: // We're on the main core! + + // Set stack to start below our code + ldr x1, =_start + mov sp, x1 + + adr x0, vectors // load VBAR_EL1 with virtual + // msr vbar_el3, x0 // vector table address + msr vbar_el1, x0 // vector table address + // msr vbar_el2, x0 // vector table address + isb + + // Clean the BSS section + ldr x1, =__bss_start // Start address + ldr w2, =__bss_size // Size of the section +3: cbz w2, 4f // Quit loop if zero + str xzr, [x1], #8 + sub w2, w2, #1 + cbnz w2, 3b // Loop if non-zero + + // Jump to our main() routine in C (make sure it doesn't return) +4: bl main + // In case it does return, halt the master core too + b 1b + +.macro ventry label +.align 7 +b \label +.endm + +.macro handle_invalid_entry type +irq_entry +mov x0, #\type +mrs x1, esr_el1 +mrs x2, elr_el1 +b err_hang +.endm + +.macro irq_entry +sub sp, sp, #272 +stp x0, x1, [sp, #16 * 0] +stp x2, x3, [sp, #16 * 1] +stp x4, x5, [sp, #16 * 2] +stp x6, x7, [sp, #16 * 3] +stp x8, x9, [sp, #16 * 4] +stp x10, x11, [sp, #16 * 5] +stp x12, x13, [sp, #16 * 6] +stp x14, x15, [sp, #16 * 7] +stp x16, x17, [sp, #16 * 8] +stp x18, x19, [sp, #16 * 9] +stp x20, x21, [sp, #16 * 10] +stp x22, x23, [sp, #16 * 11] +stp x24, x25, [sp, #16 * 12] +stp x26, x27, [sp, #16 * 13] +stp x28, x29, [sp, #16 * 14] +str x30, [sp, #16 * 15] +.endm + +.macro irq_exit +ldp x0, x1, [sp, #16 * 0] +ldp x2, x3, [sp, #16 * 1] +ldp x4, x5, [sp, #16 * 2] +ldp x6, x7, [sp, #16 * 3] +ldp x8, x9, [sp, #16 * 4] +ldp x10, x11, [sp, #16 * 5] +ldp x12, x13, [sp, #16 * 6] +ldp x14, x15, [sp, #16 * 7] +ldp x16, x17, [sp, #16 * 8] +ldp x18, x19, [sp, #16 * 9] +ldp x20, x21, [sp, #16 * 10] +ldp x22, x23, [sp, #16 * 11] +ldp x24, x25, [sp, #16 * 12] +ldp x26, x27, [sp, #16 * 13] +ldp x28, x29, [sp, #16 * 14] +ldr x30, [sp, #16 * 15] +add sp, sp, #272 +eret +.endm + + +/* + * Exception vectors. + */ +.align 11 +.globl vectors +vectors: + ventry sync_invalid_el1t // Synchronous EL1t + ventry irq_invalid_el1t // IRQ EL1t + ventry fiq_invalid_el1t // FIQ EL1t + ventry error_invalid_el1t // Error EL1t + + ventry sync_invalid_el1h // Synchronous EL1h + ventry el1_irq // IRQ EL1h + ventry fiq_invalid_el1h // FIQ EL1h + ventry error_invalid_el1h // Error EL1h + + ventry sync_invalid_el0_64 // Synchronous 64-bit EL0 + ventry irq_invalid_el0_64 // IRQ 64-bit EL0 + ventry fiq_invalid_el0_64 // FIQ 64-bit EL0 + ventry error_invalid_el0_64 // Error 64-bit EL0 + + ventry sync_invalid_el0_32 // Synchronous 32-bit EL0 + ventry irq_invalid_el0_32 // IRQ 32-bit EL0 + ventry fiq_invalid_el0_32 // FIQ 32-bit EL0 + ventry error_invalid_el0_32 // Error 32-bit EL0 + +sync_invalid_el1t: + handle_invalid_entry 0 + +irq_invalid_el1t: + handle_invalid_entry 1 + +fiq_invalid_el1t: + handle_invalid_entry 2 + +error_invalid_el1t: + handle_invalid_entry 3 + +sync_invalid_el1h: + handle_invalid_entry 4 + +fiq_invalid_el1h: + handle_invalid_entry 5 + +error_invalid_el1h: + handle_invalid_entry 6 + +sync_invalid_el0_64: + handle_invalid_entry 7 + +irq_invalid_el0_64: + handle_invalid_entry 8 + +fiq_invalid_el0_64: + handle_invalid_entry 9 + +error_invalid_el0_64: + handle_invalid_entry 10 + +sync_invalid_el0_32: + handle_invalid_entry 11 + +irq_invalid_el0_32: + handle_invalid_entry 12 + +fiq_invalid_el0_32: + handle_invalid_entry 13 + +error_invalid_el0_32: + handle_invalid_entry 14 + +el1_irq: + irq_entry + bl handle_irq + irq_exit + +.globl err_hang +err_hang: b err_hang diff --git a/hw/mcu/broadcom/bcm2711/interrupts.c b/hw/mcu/broadcom/bcm2711/interrupts.c new file mode 100644 index 000000000..cb5607526 --- /dev/null +++ b/hw/mcu/broadcom/bcm2711/interrupts.c @@ -0,0 +1,26 @@ +#include +#include + +void disable_async_interrupts(void) { + +} + +void enable_async_interrupts(void) { + +} + +void Default_Handler(void) { + while (true) {} +} + +__attribute__((weak)) void handle_irq(void) { + unsigned int irq = *((volatile uint32_t*) 0x3F00B204); + switch (irq) { + // case (SYSTEM_TIMER_IRQ_1): + // handle_timer_irq(); + // break; + default: + // printf("Unknown pending irq: %x\r\n", irq); + Default_Handler(); + } +} \ No newline at end of file diff --git a/hw/mcu/broadcom/bcm2711/interrupts.h b/hw/mcu/broadcom/bcm2711/interrupts.h new file mode 100644 index 000000000..5f36d6daa --- /dev/null +++ b/hw/mcu/broadcom/bcm2711/interrupts.h @@ -0,0 +1,8 @@ +#pragma once + +void disable_async_interrupts(void); +void enable_async_interrupts(void); + +#define GIC_BASE 0x4c0040000 +#define NUM_CPUS 4 +#define NUM_SPIS 192 diff --git a/hw/mcu/broadcom/bcm2711/io.c b/hw/mcu/broadcom/bcm2711/io.c new file mode 100644 index 000000000..213d6f2fb --- /dev/null +++ b/hw/mcu/broadcom/bcm2711/io.c @@ -0,0 +1,168 @@ +// From: https://github.com/isometimes/rpi4-osdev/blob/master/part4-miniuart/io.c +// CC-0 License + +// GPIO + +enum { + PERIPHERAL_BASE = 0xFE000000, + GPFSEL0 = PERIPHERAL_BASE + 0x200000, + GPSET0 = PERIPHERAL_BASE + 0x20001C, + GPCLR0 = PERIPHERAL_BASE + 0x200028, + GPPUPPDN0 = PERIPHERAL_BASE + 0x2000E4 +}; + +enum { + GPIO_MAX_PIN = 53, + GPIO_FUNCTION_OUT = 1, + GPIO_FUNCTION_ALT5 = 2, + GPIO_FUNCTION_ALT3 = 7 +}; + +enum { + Pull_None = 0, + Pull_Down = 1, // Are down and up the right way around? + Pull_Up = 2 +}; + +void mmio_write(long reg, unsigned int val) { *(volatile unsigned int *)reg = val; } +unsigned int mmio_read(long reg) { return *(volatile unsigned int *)reg; } + +unsigned int gpio_call(unsigned int pin_number, unsigned int value, unsigned int base, unsigned int field_size, unsigned int field_max) { + unsigned int field_mask = (1 << field_size) - 1; + + if (pin_number > field_max) return 0; + if (value > field_mask) return 0; + + unsigned int num_fields = 32 / field_size; + unsigned int reg = base + ((pin_number / num_fields) * 4); + unsigned int shift = (pin_number % num_fields) * field_size; + + unsigned int curval = mmio_read(reg); + curval &= ~(field_mask << shift); + curval |= value << shift; + mmio_write(reg, curval); + + return 1; +} + +unsigned int gpio_set (unsigned int pin_number, unsigned int value) { return gpio_call(pin_number, value, GPSET0, 1, GPIO_MAX_PIN); } +unsigned int gpio_clear (unsigned int pin_number, unsigned int value) { return gpio_call(pin_number, value, GPCLR0, 1, GPIO_MAX_PIN); } +unsigned int gpio_pull (unsigned int pin_number, unsigned int value) { return gpio_call(pin_number, value, GPPUPPDN0, 2, GPIO_MAX_PIN); } +unsigned int gpio_function(unsigned int pin_number, unsigned int value) { return gpio_call(pin_number, value, GPFSEL0, 3, GPIO_MAX_PIN); } + +void gpio_useAsAlt3(unsigned int pin_number) { + gpio_pull(pin_number, Pull_None); + gpio_function(pin_number, GPIO_FUNCTION_ALT3); +} + +void gpio_useAsAlt5(unsigned int pin_number) { + gpio_pull(pin_number, Pull_None); + gpio_function(pin_number, GPIO_FUNCTION_ALT5); +} + +void gpio_initOutputPinWithPullNone(unsigned int pin_number) { + gpio_pull(pin_number, Pull_None); + gpio_function(pin_number, GPIO_FUNCTION_OUT); +} + +void gpio_setPinOutputBool(unsigned int pin_number, unsigned int onOrOff) { + if (onOrOff) { + gpio_set(pin_number, 1); + } else { + gpio_clear(pin_number, 1); + } +} + +// UART + +enum { + AUX_BASE = PERIPHERAL_BASE + 0x215000, + AUX_IRQ = AUX_BASE, + AUX_ENABLES = AUX_BASE + 4, + AUX_MU_IO_REG = AUX_BASE + 64, + AUX_MU_IER_REG = AUX_BASE + 68, + AUX_MU_IIR_REG = AUX_BASE + 72, + AUX_MU_LCR_REG = AUX_BASE + 76, + AUX_MU_MCR_REG = AUX_BASE + 80, + AUX_MU_LSR_REG = AUX_BASE + 84, + AUX_MU_MSR_REG = AUX_BASE + 88, + AUX_MU_SCRATCH = AUX_BASE + 92, + AUX_MU_CNTL_REG = AUX_BASE + 96, + AUX_MU_STAT_REG = AUX_BASE + 100, + AUX_MU_BAUD_REG = AUX_BASE + 104, + AUX_UART_CLOCK = 500000000, + UART_MAX_QUEUE = 16 * 1024 +}; + +#define AUX_MU_BAUD(baud) ((AUX_UART_CLOCK/(baud*8))-1) + +unsigned char uart_output_queue[UART_MAX_QUEUE]; +unsigned int uart_output_queue_write = 0; +unsigned int uart_output_queue_read = 0; + +void uart_init(void) { + mmio_write(AUX_ENABLES, 1); //enable UART1 + mmio_write(AUX_MU_IER_REG, 0); + mmio_write(AUX_MU_CNTL_REG, 0); + mmio_write(AUX_MU_LCR_REG, 3); //8 bits + mmio_write(AUX_MU_MCR_REG, 0); + mmio_write(AUX_MU_IER_REG, 0); + mmio_write(AUX_MU_IIR_REG, 0xC6); //disable interrupts + mmio_write(AUX_MU_BAUD_REG, AUX_MU_BAUD(115200)); + gpio_useAsAlt5(14); + gpio_useAsAlt5(15); + mmio_write(AUX_MU_CNTL_REG, 3); //enable RX/TX +} + +unsigned int uart_isOutputQueueEmpty(void) { + return uart_output_queue_read == uart_output_queue_write; +} + +unsigned int uart_isReadByteReady(void) { return mmio_read(AUX_MU_LSR_REG) & 0x01; } +unsigned int uart_isWriteByteReady(void) { return mmio_read(AUX_MU_LSR_REG) & 0x20; } + +unsigned char uart_readByte(void) { + while (!uart_isReadByteReady()); + return (unsigned char)mmio_read(AUX_MU_IO_REG); +} + +void uart_writeByteBlockingActual(unsigned char ch) { + while (!uart_isWriteByteReady()); + mmio_write(AUX_MU_IO_REG, (unsigned int)ch); +} + +void uart_loadOutputFifo(void) { + while (!uart_isOutputQueueEmpty() && uart_isWriteByteReady()) { + uart_writeByteBlockingActual(uart_output_queue[uart_output_queue_read]); + uart_output_queue_read = (uart_output_queue_read + 1) & (UART_MAX_QUEUE - 1); // Don't overrun + } +} + +void uart_writeByteBlocking(unsigned char ch) { + unsigned int next = (uart_output_queue_write + 1) & (UART_MAX_QUEUE - 1); // Don't overrun + + while (next == uart_output_queue_read) uart_loadOutputFifo(); + + uart_output_queue[uart_output_queue_write] = ch; + uart_output_queue_write = next; +} + +void uart_writeText(const char *buffer) { + while (*buffer) { + if (*buffer == '\n') uart_writeByteBlocking('\r'); + uart_writeByteBlocking(*buffer++); + } +} + +void uart_drainOutputQueue(void) { + while (!uart_isOutputQueueEmpty()) uart_loadOutputFifo(); +} + +void uart_update(void) { + uart_loadOutputFifo(); + + if (uart_isReadByteReady()) { + unsigned char ch = uart_readByte(); + if (ch == '\r') uart_writeText("\n"); else uart_writeByteBlocking(ch); + } +} diff --git a/hw/mcu/broadcom/bcm2711/io.h b/hw/mcu/broadcom/bcm2711/io.h new file mode 100644 index 000000000..9f70ce504 --- /dev/null +++ b/hw/mcu/broadcom/bcm2711/io.h @@ -0,0 +1,13 @@ +// From: https://github.com/isometimes/rpi4-osdev/blob/master/part4-miniuart/io.h +// CC-0 License + +void uart_init(void); +void uart_writeText(const char *buffer); +void uart_loadOutputFifo(void); +unsigned char uart_readByte(void); +unsigned int uart_isReadByteReady(void); +void uart_writeByteBlocking(unsigned char ch); +void uart_update(void); +void gpio_setPinOutputBool(unsigned int pin_number, unsigned int onOrOff); +void uart_writeByteBlockingActual(unsigned char ch); +void gpio_initOutputPinWithPullNone(unsigned int pin_number); diff --git a/hw/mcu/broadcom/bcm2711/link.ld b/hw/mcu/broadcom/bcm2711/link.ld new file mode 100644 index 000000000..0d5ebe2ab --- /dev/null +++ b/hw/mcu/broadcom/bcm2711/link.ld @@ -0,0 +1,20 @@ +SECTIONS +{ + . = 0x80000; /* Kernel load address for AArch64 */ + .text : { KEEP(*(.text.boot)) *(.text .text.* .gnu.linkonce.t*) } + .rodata : { *(.rodata .rodata.* .gnu.linkonce.r*) } + PROVIDE(_data = .); + .data : { *(.data .data.* .gnu.linkonce.d*) } + .bss (NOLOAD) : { + . = ALIGN(16); + __bss_start = .; + *(.bss .bss.*) + *(COMMON) + __bss_end = .; + } + _end = .; + end = .; + + /DISCARD/ : { *(.comment) *(.gnu*) *(.note*) *(.eh_frame*) } +} +__bss_size = (__bss_end - __bss_start)>>3; diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c index 0fd592129..5eb28e694 100644 --- a/src/class/msc/msc_device.c +++ b/src/class/msc/msc_device.c @@ -476,7 +476,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t if (p_cbw->total_bytes) { // 6.7 The 13 Cases: case 4 (Hi > Dn) - TU_LOG(MSC_DEBUG, " SCSI case 4 (Hi > Dn): %lu\r\n", p_cbw->total_bytes); + // TU_LOG(MSC_DEBUG, " SCSI case 4 (Hi > Dn): %lu\r\n", p_cbw->total_bytes); fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED); }else { @@ -489,7 +489,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t if ( p_cbw->total_bytes == 0 ) { // 6.7 The 13 Cases: case 2 (Hn < Di) - TU_LOG(MSC_DEBUG, " SCSI case 2 (Hn < Di): %lu\r\n", p_cbw->total_bytes); + // TU_LOG(MSC_DEBUG, " SCSI case 2 (Hn < Di): %lu\r\n", p_cbw->total_bytes); fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED); }else { @@ -604,7 +604,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t if ( (p_cbw->total_bytes > p_msc->xferred_len) && is_data_in(p_cbw->dir) ) { // 6.7 The 13 Cases: case 5 (Hi > Di): STALL before status - TU_LOG(MSC_DEBUG, " SCSI case 5 (Hi > Di): %lu > %lu\r\n", p_cbw->total_bytes, p_msc->xferred_len); + // TU_LOG(MSC_DEBUG, " SCSI case 5 (Hi > Di): %lu > %lu\r\n", p_cbw->total_bytes, p_msc->xferred_len); usbd_edpt_stall(rhport, p_msc->ep_in); }else { diff --git a/src/device/dcd_attr.h b/src/device/dcd_attr.h index a35fc0ac5..9e833c7bb 100644 --- a/src/device/dcd_attr.h +++ b/src/device/dcd_attr.h @@ -151,6 +151,10 @@ #elif TU_CHECK_MCU(GD32VF103) #define DCD_ATTR_ENDPOINT_MAX 4 +//------------- Broadcom -------------// +#elif TU_CHECK_MCU(BCM2711) + #define DCD_ATTR_ENDPOINT_MAX 8 + #else #warning "DCD_ATTR_ENDPOINT_MAX is not defined for this MCU, default to 8" #define DCD_ATTR_ENDPOINT_MAX 8 diff --git a/src/portable/broadcom/synopsys/dcd_synopsys.c b/src/portable/broadcom/synopsys/dcd_synopsys.c new file mode 100644 index 000000000..5967565a5 --- /dev/null +++ b/src/portable/broadcom/synopsys/dcd_synopsys.c @@ -0,0 +1,1212 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2018 Scott Shawcroft, 2019 William D. Jones for Adafruit Industries + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * Copyright (c) 2020 Jan Duempelmann + * Copyright (c) 2020 Reinhard Panhuber + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "tusb_option.h" + +#include "synopsys_common.h" + +// Since TinyUSB doesn't use SOF for now, and this interrupt too often (1ms interval) +// We disable SOF for now until needed later on +#define USE_SOF 0 + +#if TUSB_OPT_DEVICE_ENABLED && \ + ( (CFG_TUSB_MCU == OPT_MCU_BCM2711 ) \ + ) + +// EP_MAX : Max number of bi-directional endpoints including EP0 +// EP_FIFO_SIZE : Size of dedicated USB SRAM +#if CFG_TUSB_MCU == OPT_MCU_BCM2711 +// #include "bcm2711.h" +#define EP_MAX_FS 8 +#define EP_FIFO_SIZE_FS 4096 +#define EP_MAX_HS 8 +#define EP_FIFO_SIZE_HS 4096 +#else +#error "Unsupported MCUs" +#endif + +#define EP_MAX 8 +#define EP_FIFO_SIZE 4096 + +// Info on values here: https://github.com/torvalds/linux/blob/79160a603bdb51916226caf4a6616cc4e1c58a58/Documentation/devicetree/bindings/usb/dwc2.yaml + +// From: https://github.com/raspberrypi/linux/blob/rpi-5.10.y/arch/arm/boot/dts/bcm283x.dtsi +// usb: usb@7e980000 { +// compatible = "brcm,bcm2835-usb"; +// reg = <0x7e980000 0x10000>; +// interrupts = <1 9>; +// #address-cells = <1>; +// #size-cells = <0>; +// clocks = <&clk_usb>; +// clock-names = "otg"; +// phys = <&usbphy>; +// phy-names = "usb2-phy"; +// }; + +// From: https://github.com/raspberrypi/linux/blob/rpi-5.10.y/arch/arm/boot/dts/bcm283x-rpi-usb-otg.dtsi +// SPDX-License-Identifier: GPL-2.0 +// &usb { +// dr_mode = "otg"; +// g-rx-fifo-size = <256>; +// g-np-tx-fifo-size = <32>; + +// * According to dwc2 the sum of all device EP +// * fifo sizes shouldn't exceed 3776 bytes. + +// g-tx-fifo-size = <256 256 512 512 512 768 768>; +// }; + +// From: https://github.com/raspberrypi/linux/blob/rpi-5.10.y/arch/arm/boot/dts/bcm2711-rpi.dtsi +// &usb { +// /* Enable the FIQ support */ +// reg = <0x7e980000 0x10000>, +// <0x7e00b200 0x200>; +// interrupts = , +// ; +// status = "disabled"; +// }; + +// From: https://github.com/raspberrypi/linux/blob/rpi-5.10.y/arch/arm/boot/dts/bcm2711.dtsi +// &usb { +// interrupts = ; +// }; + +// From: https://github.com/torvalds/linux/blob/1d597682d3e669ec7021aa33d088ed3d136a5149/drivers/usb/dwc2/params.c +// static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg) +// { +// struct dwc2_core_params *p = &hsotg->params; + +// p->host_rx_fifo_size = 774; +// p->max_transfer_size = 65535; +// p->max_packet_count = 511; +// p->ahbcfg = 0x10; +// } + +#include "device/dcd.h" + +//--------------------------------------------------------------------+ +// MACRO TYPEDEF CONSTANT ENUM +//--------------------------------------------------------------------+ + +#define RHPORT_REGS_BASE 0x7e980000 + +#define GLOBAL_BASE(_port) ((USB_OTG_GlobalTypeDef*) RHPORT_REGS_BASE) +#define DEVICE_BASE(_port) (USB_OTG_DeviceTypeDef *) (RHPORT_REGS_BASE + USB_OTG_DEVICE_BASE) +#define OUT_EP_BASE(_port) (USB_OTG_OUTEndpointTypeDef *) (RHPORT_REGS_BASE + USB_OTG_OUT_ENDPOINT_BASE) +#define IN_EP_BASE(_port) (USB_OTG_INEndpointTypeDef *) (RHPORT_REGS_BASE + USB_OTG_IN_ENDPOINT_BASE) +#define FIFO_BASE(_port, _x) ((volatile uint32_t *) (RHPORT_REGS_BASE + USB_OTG_FIFO_BASE + (_x) * USB_OTG_FIFO_SIZE)) + +enum +{ + DCD_HIGH_SPEED = 0, // Highspeed mode + DCD_FULL_SPEED_USE_HS = 1, // Full speed in Highspeed port (probably with internal PHY) + DCD_FULL_SPEED = 3, // Full speed with internal PHY +}; + +static TU_ATTR_ALIGNED(4) uint32_t _setup_packet[2]; + +typedef struct { + uint8_t * buffer; + tu_fifo_t * ff; + uint16_t total_len; + uint16_t max_size; + uint8_t interval; +} xfer_ctl_t; + +typedef volatile uint32_t * usb_fifo_t; + +xfer_ctl_t xfer_status[EP_MAX][2]; +#define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir] + +// EP0 transfers are limited to 1 packet - larger sizes has to be split +static uint16_t ep0_pending[2]; // Index determines direction as tusb_dir_t type + +// TX FIFO RAM allocation so far in words - RX FIFO size is readily available from usb_otg->GRXFSIZ +static uint16_t _allocated_fifo_words_tx; // TX FIFO size in words (IN EPs) +static bool _out_ep_closed; // Flag to check if RX FIFO size needs an update (reduce its size) + +// Calculate the RX FIFO size according to recommendations from reference manual +static inline uint16_t calc_rx_ff_size(uint16_t ep_size) +{ + return 15 + 2*(ep_size/4) + 2*EP_MAX; +} + +static void update_grxfsiz(uint8_t rhport) +{ + (void) rhport; + + USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport); + + // Determine largest EP size for RX FIFO + uint16_t max_epsize = 0; + for (uint8_t epnum = 0; epnum < EP_MAX; epnum++) + { + max_epsize = tu_max16(max_epsize, xfer_status[epnum][TUSB_DIR_OUT].max_size); + } + + // Update size of RX FIFO + usb_otg->GRXFSIZ = calc_rx_ff_size(max_epsize); +} + +// Setup the control endpoint 0. +static void bus_reset(uint8_t rhport) +{ + (void) rhport; + + USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport); + USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport); + USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport); + USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport); + + tu_memclr(xfer_status, sizeof(xfer_status)); + _out_ep_closed = false; + + // clear device address + dev->DCFG &= ~USB_OTG_DCFG_DAD_Msk; + + // 1. NAK for all OUT endpoints + for(uint8_t n = 0; n < EP_MAX; n++) { + out_ep[n].DOEPCTL |= USB_OTG_DOEPCTL_SNAK; + } + + // 2. Un-mask interrupt bits + dev->DAINTMSK = (1 << USB_OTG_DAINTMSK_OEPM_Pos) | (1 << USB_OTG_DAINTMSK_IEPM_Pos); + dev->DOEPMSK = USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM; + dev->DIEPMSK = USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM; + + // "USB Data FIFOs" section in reference manual + // Peripheral FIFO architecture + // + // The FIFO is split up in a lower part where the RX FIFO is located and an upper part where the TX FIFOs start. + // We do this to allow the RX FIFO to grow dynamically which is possible since the free space is located + // between the RX and TX FIFOs. This is required by ISO OUT EPs which need a bigger FIFO than the standard + // configuration done below. + // + // Dynamically FIFO sizes are of interest only for ISO EPs since all others are usually not opened and closed. + // All EPs other than ISO are opened as soon as the driver starts up i.e. when the host sends a + // configure interface command. Hence, all IN EPs other the ISO will be located at the top. IN ISO EPs are usually + // opened when the host sends an additional command: setInterface. At this point in time + // the ISO EP will be located next to the free space and can change its size. In case more IN EPs change its size + // an additional memory + // + // --------------- 320 or 1024 ( 1280 or 4096 bytes ) + // | IN FIFO 0 | + // --------------- (320 or 1024) - 16 + // | IN FIFO 1 | + // --------------- (320 or 1024) - 16 - x + // | . . . . | + // --------------- (320 or 1024) - 16 - x - y - ... - z + // | IN FIFO MAX | + // --------------- + // | FREE | + // --------------- GRXFSIZ + // | OUT FIFO | + // | ( Shared ) | + // --------------- 0 + // + // According to "FIFO RAM allocation" section in RM, FIFO RAM are allocated as follows (each word 32-bits): + // - Each EP IN needs at least max packet size, 16 words is sufficient for EP0 IN + // + // - All EP OUT shared a unique OUT FIFO which uses + // - 13 for setup packets + control words (up to 3 setup packets). + // - 1 for global NAK (not required/used here). + // - Largest-EPsize / 4 + 1. ( FS: 64 bytes, HS: 512 bytes). Recommended is "2 x (Largest-EPsize/4) + 1" + // - 2 for each used OUT endpoint + // + // Therefore GRXFSIZ = 13 + 1 + 1 + 2 x (Largest-EPsize/4) + 2 x EPOUTnum + // - FullSpeed (64 Bytes ): GRXFSIZ = 15 + 2 x 16 + 2 x EP_MAX = 47 + 2 x EP_MAX + // - Highspeed (512 bytes): GRXFSIZ = 15 + 2 x 128 + 2 x EP_MAX = 271 + 2 x EP_MAX + // + // NOTE: Largest-EPsize & EPOUTnum is actual used endpoints in configuration. Since DCD has no knowledge + // of the overall picture yet. We will use the worst scenario: largest possible + EP_MAX + // + // For Isochronous, largest EP size can be 1023/1024 for FS/HS respectively. In addition if multiple ISO + // are enabled at least "2 x (Largest-EPsize/4) + 1" are recommended. Maybe provide a macro for application to + // overwrite this. + + #if TUD_OPT_HIGH_SPEED + usb_otg->GRXFSIZ = calc_rx_ff_size(512); + #else + usb_otg->GRXFSIZ = calc_rx_ff_size(64); + #endif + + _allocated_fifo_words_tx = 16; + + // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word ) + usb_otg->DIEPTXF0_HNPTXFSIZ = (16 << USB_OTG_TX0FD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx); + + // Fixed control EP0 size to 64 bytes + in_ep[0].DIEPCTL &= ~(0x03 << USB_OTG_DIEPCTL_MPSIZ_Pos); + xfer_status[0][TUSB_DIR_OUT].max_size = xfer_status[0][TUSB_DIR_IN].max_size = 64; + + out_ep[0].DOEPTSIZ |= (3 << USB_OTG_DOEPTSIZ_STUPCNT_Pos); + + usb_otg->GINTMSK |= USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IEPINT; +} + +// Set turn-around timeout according to link speed +extern uint32_t SystemCoreClock; +static void set_turnaround(USB_OTG_GlobalTypeDef * usb_otg, tusb_speed_t speed) +{ + usb_otg->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT; + + if ( speed == TUSB_SPEED_HIGH ) + { + // Use fixed 0x09 for Highspeed + usb_otg->GUSBCFG |= (0x09 << USB_OTG_GUSBCFG_TRDT_Pos); + } + else + { + // Turnaround timeout depends on the MCU clock + uint32_t turnaround; + + if ( SystemCoreClock >= 32000000U ) + turnaround = 0x6U; + else if ( SystemCoreClock >= 27500000U ) + turnaround = 0x7U; + else if ( SystemCoreClock >= 24000000U ) + turnaround = 0x8U; + else if ( SystemCoreClock >= 21800000U ) + turnaround = 0x9U; + else if ( SystemCoreClock >= 20000000U ) + turnaround = 0xAU; + else if ( SystemCoreClock >= 18500000U ) + turnaround = 0xBU; + else if ( SystemCoreClock >= 17200000U ) + turnaround = 0xCU; + else if ( SystemCoreClock >= 16000000U ) + turnaround = 0xDU; + else if ( SystemCoreClock >= 15000000U ) + turnaround = 0xEU; + else + turnaround = 0xFU; + + // Fullspeed depends on MCU clocks, but we will use 0x06 for 32+ Mhz + usb_otg->GUSBCFG |= (turnaround << USB_OTG_GUSBCFG_TRDT_Pos); + } +} + +static tusb_speed_t get_speed(uint8_t rhport) +{ + (void) rhport; + USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport); + uint32_t const enum_spd = (dev->DSTS & USB_OTG_DSTS_ENUMSPD_Msk) >> USB_OTG_DSTS_ENUMSPD_Pos; + return (enum_spd == DCD_HIGH_SPEED) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL; +} + +static void set_speed(uint8_t rhport, tusb_speed_t speed) +{ + uint32_t bitvalue; + + if ( rhport == 1 ) + { + bitvalue = ((TUSB_SPEED_HIGH == speed) ? DCD_HIGH_SPEED : DCD_FULL_SPEED_USE_HS); + } + else + { + bitvalue = DCD_FULL_SPEED; + } + + USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport); + + // Clear and set speed bits + dev->DCFG &= ~(3 << USB_OTG_DCFG_DSPD_Pos); + dev->DCFG |= (bitvalue << USB_OTG_DCFG_DSPD_Pos); +} + +#if defined(USB_HS_PHYC) +static bool USB_HS_PHYCInit(void) +{ + USB_HS_PHYC_GlobalTypeDef *usb_hs_phyc = (USB_HS_PHYC_GlobalTypeDef*) USB_HS_PHYC_CONTROLLER_BASE; + + // Enable LDO + usb_hs_phyc->USB_HS_PHYC_LDO |= USB_HS_PHYC_LDO_ENABLE; + + // Wait until LDO ready + while ( 0 == (usb_hs_phyc->USB_HS_PHYC_LDO & USB_HS_PHYC_LDO_STATUS) ) {} + + uint32_t phyc_pll = 0; + + // TODO Try to get HSE_VALUE from registers instead of depending CFLAGS + switch ( HSE_VALUE ) + { + case 12000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12MHZ ; break; + case 12500000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12_5MHZ ; break; + case 16000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_16MHZ ; break; + case 24000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_24MHZ ; break; + case 25000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_25MHZ ; break; + case 32000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_Msk ; break; // Value not defined in header + default: + TU_ASSERT(0); + } + usb_hs_phyc->USB_HS_PHYC_PLL = phyc_pll; + + // Control the tuning interface of the High Speed PHY + // Use magic value (USB_HS_PHYC_TUNE_VALUE) from ST driver + usb_hs_phyc->USB_HS_PHYC_TUNE |= 0x00000F13U; + + // Enable PLL internal PHY + usb_hs_phyc->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN; + + // Original ST code has 2 ms delay for PLL stabilization. + // Primitive test shows that more than 10 USB un/replug cycle showed no error with enumeration + + return true; +} +#endif + +static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t const dir, uint16_t const num_packets, uint16_t total_bytes) +{ + (void) rhport; + + USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport); + USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport); + USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport); + + // EP0 is limited to one packet each xfer + // We use multiple transaction of xfer->max_size length to get a whole transfer done + if(epnum == 0) { + xfer_ctl_t * const xfer = XFER_CTL_BASE(epnum, dir); + total_bytes = tu_min16(ep0_pending[dir], xfer->max_size); + ep0_pending[dir] -= total_bytes; + } + + // IN and OUT endpoint xfers are interrupt-driven, we just schedule them here. + if(dir == TUSB_DIR_IN) { + // A full IN transfer (multiple packets, possibly) triggers XFRC. + in_ep[epnum].DIEPTSIZ = (num_packets << USB_OTG_DIEPTSIZ_PKTCNT_Pos) | + ((total_bytes << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) & USB_OTG_DIEPTSIZ_XFRSIZ_Msk); + + in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_EPENA | USB_OTG_DIEPCTL_CNAK; + // For ISO endpoint set correct odd/even bit for next frame. + if ((in_ep[epnum].DIEPCTL & USB_OTG_DIEPCTL_EPTYP) == USB_OTG_DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) + { + // Take odd/even bit from frame counter. + uint32_t const odd_frame_now = (dev->DSTS & (1u << USB_OTG_DSTS_FNSOF_Pos)); + in_ep[epnum].DIEPCTL |= (odd_frame_now ? USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk : USB_OTG_DIEPCTL_SODDFRM_Msk); + } + // Enable fifo empty interrupt only if there are something to put in the fifo. + if(total_bytes != 0) { + dev->DIEPEMPMSK |= (1 << epnum); + } + } else { + // A full OUT transfer (multiple packets, possibly) triggers XFRC. + out_ep[epnum].DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT_Msk | USB_OTG_DOEPTSIZ_XFRSIZ); + out_ep[epnum].DOEPTSIZ |= (num_packets << USB_OTG_DOEPTSIZ_PKTCNT_Pos) | + ((total_bytes << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) & USB_OTG_DOEPTSIZ_XFRSIZ_Msk); + + out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_CNAK; + if ((out_ep[epnum].DOEPCTL & USB_OTG_DOEPCTL_EPTYP) == USB_OTG_DOEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) + { + // Take odd/even bit from frame counter. + uint32_t const odd_frame_now = (dev->DSTS & (1u << USB_OTG_DSTS_FNSOF_Pos)); + out_ep[epnum].DOEPCTL |= (odd_frame_now ? USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk : USB_OTG_DOEPCTL_SODDFRM_Msk); + } + } +} + +/*------------------------------------------------------------------*/ +/* Controller API + *------------------------------------------------------------------*/ +void dcd_init (uint8_t rhport) +{ + // Programming model begins in the last section of the chapter on the USB + // peripheral in each Reference Manual. + + USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport); + + // No HNP/SRP (no OTG support), program timeout later. + if ( rhport == 1 ) + { + // On selected MCUs HS port1 can be used with external PHY via ULPI interface +#if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED + // deactivate internal PHY + usb_otg->GCCFG &= ~USB_OTG_GCCFG_PWRDWN; + + // Init The UTMI Interface + usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL); + + // Select default internal VBUS Indicator and Drive for ULPI + usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); +#else + usb_otg->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; +#endif + +#if defined(USB_HS_PHYC) + // Highspeed with embedded UTMI PHYC + + // Select UTMI Interface + usb_otg->GUSBCFG &= ~USB_OTG_GUSBCFG_ULPI_UTMI_SEL; + usb_otg->GCCFG |= USB_OTG_GCCFG_PHYHSEN; + + // Enables control of a High Speed USB PHY + USB_HS_PHYCInit(); +#endif + } else + { + // Enable internal PHY + usb_otg->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; + } + + // Reset core after selecting PHY + // Wait AHB IDLE, reset then wait until it is cleared + while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U) {} + usb_otg->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; + while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST) {} + + // Restart PHY clock + *((volatile uint32_t *)(RHPORT_REGS_BASE + USB_OTG_PCGCCTL_BASE)) = 0; + + // Clear all interrupts + usb_otg->GINTSTS |= usb_otg->GINTSTS; + + // Required as part of core initialization. + // TODO: How should mode mismatch be handled? It will cause + // the core to stop working/require reset. + usb_otg->GINTMSK |= USB_OTG_GINTMSK_OTGINT | USB_OTG_GINTMSK_MMISM; + + USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport); + + // If USB host misbehaves during status portion of control xfer + // (non zero-length packet), send STALL back and discard. + dev->DCFG |= USB_OTG_DCFG_NZLSOHSK; + + #if TUD_OPT_HIGH_SPEED + set_speed(rhport, TUSB_SPEED_HIGH); + #else + set_speed(rhport, TUSB_SPEED_FULL); + #endif + + // Enable internal USB transceiver, unless using HS core (port 1) with external PHY. + if (!(rhport == 1 && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED))) usb_otg->GCCFG |= USB_OTG_GCCFG_PWRDWN; + + usb_otg->GINTMSK |= USB_OTG_GINTMSK_USBRST | USB_OTG_GINTMSK_ENUMDNEM | + USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_WUIM | + USB_OTG_GINTMSK_RXFLVLM | (USE_SOF ? USB_OTG_GINTMSK_SOFM : 0); + + // Enable global interrupt + usb_otg->GAHBCFG |= USB_OTG_GAHBCFG_GINT; + + dcd_connect(rhport); +} + +void dcd_int_enable (uint8_t rhport) +{ + (void) rhport; + // NVIC_EnableIRQ(RHPORT_IRQn); +} + +void dcd_int_disable (uint8_t rhport) +{ + (void) rhport; + // NVIC_DisableIRQ(RHPORT_IRQn); +} + +void dcd_set_address (uint8_t rhport, uint8_t dev_addr) +{ + USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport); + dev->DCFG = (dev->DCFG & ~USB_OTG_DCFG_DAD_Msk) | (dev_addr << USB_OTG_DCFG_DAD_Pos); + + // Response with status after changing device address + dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0); +} + +static void remote_wakeup_delay(void) +{ + // try to delay for 1 ms + uint32_t count = SystemCoreClock / 1000; + while ( count-- ) + { + // __NOP(); + } +} + +void dcd_remote_wakeup(uint8_t rhport) +{ + (void) rhport; + + USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport); + USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport); + + // set remote wakeup + dev->DCTL |= USB_OTG_DCTL_RWUSIG; + + // enable SOF to detect bus resume + usb_otg->GINTSTS = USB_OTG_GINTSTS_SOF; + usb_otg->GINTMSK |= USB_OTG_GINTMSK_SOFM; + + // Per specs: remote wakeup signal bit must be clear within 1-15ms + remote_wakeup_delay(); + + dev->DCTL &= ~USB_OTG_DCTL_RWUSIG; +} + +void dcd_connect(uint8_t rhport) +{ + (void) rhport; + USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport); + dev->DCTL &= ~USB_OTG_DCTL_SDIS; +} + +void dcd_disconnect(uint8_t rhport) +{ + (void) rhport; + USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport); + dev->DCTL |= USB_OTG_DCTL_SDIS; +} + + +/*------------------------------------------------------------------*/ +/* DCD Endpoint port + *------------------------------------------------------------------*/ + +bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) +{ + (void) rhport; + + USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport); + USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport); + USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport); + USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport); + + uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress); + uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress); + + TU_ASSERT(epnum < EP_MAX); + + xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir); + xfer->max_size = desc_edpt->wMaxPacketSize.size; + xfer->interval = desc_edpt->bInterval; + + uint16_t const fifo_size = (desc_edpt->wMaxPacketSize.size + 3) / 4; // Round up to next full word + + if(dir == TUSB_DIR_OUT) + { + // Calculate required size of RX FIFO + uint16_t const sz = calc_rx_ff_size(4*fifo_size); + + // If size_rx needs to be extended check if possible and if so enlarge it + if (usb_otg->GRXFSIZ < sz) + { + TU_ASSERT(sz + _allocated_fifo_words_tx <= EP_FIFO_SIZE/4); + + // Enlarge RX FIFO + usb_otg->GRXFSIZ = sz; + } + + out_ep[epnum].DOEPCTL |= (1 << USB_OTG_DOEPCTL_USBAEP_Pos) | + (desc_edpt->bmAttributes.xfer << USB_OTG_DOEPCTL_EPTYP_Pos) | + (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_OTG_DOEPCTL_SD0PID_SEVNFRM : 0) | + (desc_edpt->wMaxPacketSize.size << USB_OTG_DOEPCTL_MPSIZ_Pos); + + dev->DAINTMSK |= (1 << (USB_OTG_DAINTMSK_OEPM_Pos + epnum)); + } + else + { + // "USB Data FIFOs" section in reference manual + // Peripheral FIFO architecture + // + // --------------- 320 or 1024 ( 1280 or 4096 bytes ) + // | IN FIFO 0 | + // --------------- (320 or 1024) - 16 + // | IN FIFO 1 | + // --------------- (320 or 1024) - 16 - x + // | . . . . | + // --------------- (320 or 1024) - 16 - x - y - ... - z + // | IN FIFO MAX | + // --------------- + // | FREE | + // --------------- GRXFSIZ + // | OUT FIFO | + // | ( Shared ) | + // --------------- 0 + // + // In FIFO is allocated by following rules: + // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n". + + // Check if free space is available + TU_ASSERT(_allocated_fifo_words_tx + fifo_size + usb_otg->GRXFSIZ <= EP_FIFO_SIZE/4); + + _allocated_fifo_words_tx += fifo_size; + + TU_LOG(2, " Allocated %u bytes at offset %u", fifo_size*4, EP_FIFO_SIZE-_allocated_fifo_words_tx*4); + + // DIEPTXF starts at FIFO #1. + // Both TXFD and TXSA are in unit of 32-bit words. + usb_otg->DIEPTXF[epnum - 1] = (fifo_size << USB_OTG_DIEPTXF_INEPTXFD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx); + + in_ep[epnum].DIEPCTL |= (1 << USB_OTG_DIEPCTL_USBAEP_Pos) | + (epnum << USB_OTG_DIEPCTL_TXFNUM_Pos) | + (desc_edpt->bmAttributes.xfer << USB_OTG_DIEPCTL_EPTYP_Pos) | + (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_OTG_DIEPCTL_SD0PID_SEVNFRM : 0) | + (desc_edpt->wMaxPacketSize.size << USB_OTG_DIEPCTL_MPSIZ_Pos); + + dev->DAINTMSK |= (1 << (USB_OTG_DAINTMSK_IEPM_Pos + epnum)); + } + + return true; +} + +// Close all non-control endpoints, cancel all pending transfers if any. +void dcd_edpt_close_all (uint8_t rhport) +{ + (void) rhport; + +// USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport); + USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport); + USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport); + USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport); + + // Disable non-control interrupt + dev->DAINTMSK = (1 << USB_OTG_DAINTMSK_OEPM_Pos) | (1 << USB_OTG_DAINTMSK_IEPM_Pos); + + for(uint8_t n = 1; n < EP_MAX; n++) + { + // disable OUT endpoint + out_ep[n].DOEPCTL = 0; + xfer_status[n][TUSB_DIR_OUT].max_size = 0; + + // disable IN endpoint + in_ep[n].DIEPCTL = 0; + xfer_status[n][TUSB_DIR_IN].max_size = 0; + } + + // reset allocated fifo IN + _allocated_fifo_words_tx = 16; +} + +bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) +{ + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir); + xfer->buffer = buffer; + xfer->ff = NULL; + xfer->total_len = total_bytes; + + // EP0 can only handle one packet + if(epnum == 0) { + ep0_pending[dir] = total_bytes; + // Schedule the first transaction for EP0 transfer + edpt_schedule_packets(rhport, epnum, dir, 1, ep0_pending[dir]); + return true; + } + + uint16_t num_packets = (total_bytes / xfer->max_size); + uint16_t const short_packet_size = total_bytes % xfer->max_size; + + // Zero-size packet is special case. + if(short_packet_size > 0 || (total_bytes == 0)) { + num_packets++; + } + + // Schedule packets to be sent within interrupt + edpt_schedule_packets(rhport, epnum, dir, num_packets, total_bytes); + + return true; +} + +// The number of bytes has to be given explicitly to allow more flexible control of how many +// bytes should be written and second to keep the return value free to give back a boolean +// success message. If total_bytes is too big, the FIFO will copy only what is available +// into the USB buffer! +bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes) +{ + // USB buffers always work in bytes so to avoid unnecessary divisions we demand item_size = 1 + TU_ASSERT(ff->item_size == 1); + + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir); + xfer->buffer = NULL; + xfer->ff = ff; + xfer->total_len = total_bytes; + + uint16_t num_packets = (total_bytes / xfer->max_size); + uint16_t const short_packet_size = total_bytes % xfer->max_size; + + // Zero-size packet is special case. + if(short_packet_size > 0 || (total_bytes == 0)) num_packets++; + + // Schedule packets to be sent within interrupt + edpt_schedule_packets(rhport, epnum, dir, num_packets, total_bytes); + + return true; +} + +static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall) +{ + (void) rhport; + + USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport); + USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport); + USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport); + USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport); + + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + if(dir == TUSB_DIR_IN) { + // Only disable currently enabled non-control endpoint + if ( (epnum == 0) || !(in_ep[epnum].DIEPCTL & USB_OTG_DIEPCTL_EPENA) ){ + in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SNAK | (stall ? USB_OTG_DIEPCTL_STALL : 0); + } else { + // Stop transmitting packets and NAK IN xfers. + in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SNAK; + while((in_ep[epnum].DIEPINT & USB_OTG_DIEPINT_INEPNE) == 0); + + // Disable the endpoint. + in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_EPDIS | (stall ? USB_OTG_DIEPCTL_STALL : 0); + while((in_ep[epnum].DIEPINT & USB_OTG_DIEPINT_EPDISD_Msk) == 0); + in_ep[epnum].DIEPINT = USB_OTG_DIEPINT_EPDISD; + } + + // Flush the FIFO, and wait until we have confirmed it cleared. + usb_otg->GRSTCTL |= (epnum << USB_OTG_GRSTCTL_TXFNUM_Pos); + usb_otg->GRSTCTL |= USB_OTG_GRSTCTL_TXFFLSH; + while((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH_Msk) != 0); + } else { + // Only disable currently enabled non-control endpoint + if ( (epnum == 0) || !(out_ep[epnum].DOEPCTL & USB_OTG_DOEPCTL_EPENA) ){ + out_ep[epnum].DOEPCTL |= stall ? USB_OTG_DOEPCTL_STALL : 0; + } else { + // Asserting GONAK is required to STALL an OUT endpoint. + // Simpler to use polling here, we don't use the "B"OUTNAKEFF interrupt + // anyway, and it can't be cleared by user code. If this while loop never + // finishes, we have bigger problems than just the stack. + dev->DCTL |= USB_OTG_DCTL_SGONAK; + while((usb_otg->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF_Msk) == 0); + + // Ditto here- disable the endpoint. + out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_EPDIS | (stall ? USB_OTG_DOEPCTL_STALL : 0); + while((out_ep[epnum].DOEPINT & USB_OTG_DOEPINT_EPDISD_Msk) == 0); + out_ep[epnum].DOEPINT = USB_OTG_DOEPINT_EPDISD; + + // Allow other OUT endpoints to keep receiving. + dev->DCTL |= USB_OTG_DCTL_CGONAK; + } + } +} + +/** + * Close an endpoint. + */ +void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr) +{ + USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport); + + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + dcd_edpt_disable(rhport, ep_addr, false); + + // Update max_size + xfer_status[epnum][dir].max_size = 0; // max_size = 0 marks a disabled EP - required for changing FIFO allocation + + if (dir == TUSB_DIR_IN) + { + uint16_t const fifo_size = (usb_otg->DIEPTXF[epnum - 1] & USB_OTG_DIEPTXF_INEPTXFD_Msk) >> USB_OTG_DIEPTXF_INEPTXFD_Pos; + uint16_t const fifo_start = (usb_otg->DIEPTXF[epnum - 1] & USB_OTG_DIEPTXF_INEPTXSA_Msk) >> USB_OTG_DIEPTXF_INEPTXSA_Pos; + // For now only the last opened endpoint can be closed without fuss. + TU_ASSERT(fifo_start == EP_FIFO_SIZE/4 - _allocated_fifo_words_tx,); + _allocated_fifo_words_tx -= fifo_size; + } + else + { + _out_ep_closed = true; // Set flag such that RX FIFO gets reduced in size once RX FIFO is empty + } +} + +void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr) +{ + dcd_edpt_disable(rhport, ep_addr, true); +} + +void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) +{ + (void) rhport; + + USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport); + USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport); + + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + // Clear stall and reset data toggle + if(dir == TUSB_DIR_IN) { + in_ep[epnum].DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; + in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; + } else { + out_ep[epnum].DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; + out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; + } +} + +/*------------------------------------------------------------------*/ + +// Read a single data packet from receive FIFO +static void read_fifo_packet(uint8_t rhport, uint8_t * dst, uint16_t len) +{ + (void) rhport; + + usb_fifo_t rx_fifo = FIFO_BASE(rhport, 0); + + // Reading full available 32 bit words from fifo + uint16_t full_words = len >> 2; + for(uint16_t i = 0; i < full_words; i++) { + uint32_t tmp = *rx_fifo; + dst[0] = tmp & 0x000000FF; + dst[1] = (tmp & 0x0000FF00) >> 8; + dst[2] = (tmp & 0x00FF0000) >> 16; + dst[3] = (tmp & 0xFF000000) >> 24; + dst += 4; + } + + // Read the remaining 1-3 bytes from fifo + uint8_t bytes_rem = len & 0x03; + if(bytes_rem != 0) { + uint32_t tmp = *rx_fifo; + dst[0] = tmp & 0x000000FF; + if(bytes_rem > 1) { + dst[1] = (tmp & 0x0000FF00) >> 8; + } + if(bytes_rem > 2) { + dst[2] = (tmp & 0x00FF0000) >> 16; + } + } +} + +// Write a single data packet to EPIN FIFO +static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t * src, uint16_t len) +{ + (void) rhport; + + usb_fifo_t tx_fifo = FIFO_BASE(rhport, fifo_num); + + // Pushing full available 32 bit words to fifo + uint16_t full_words = len >> 2; + for(uint16_t i = 0; i < full_words; i++){ + *tx_fifo = (src[3] << 24) | (src[2] << 16) | (src[1] << 8) | src[0]; + src += 4; + } + + // Write the remaining 1-3 bytes into fifo + uint8_t bytes_rem = len & 0x03; + if(bytes_rem){ + uint32_t tmp_word = 0; + tmp_word |= src[0]; + if(bytes_rem > 1){ + tmp_word |= src[1] << 8; + } + if(bytes_rem > 2){ + tmp_word |= src[2] << 16; + } + *tx_fifo = tmp_word; + } +} + +static void handle_rxflvl_ints(uint8_t rhport, USB_OTG_OUTEndpointTypeDef * out_ep) { + USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport); + usb_fifo_t rx_fifo = FIFO_BASE(rhport, 0); + + // Pop control word off FIFO + uint32_t ctl_word = usb_otg->GRXSTSP; + uint8_t pktsts = (ctl_word & USB_OTG_GRXSTSP_PKTSTS_Msk) >> USB_OTG_GRXSTSP_PKTSTS_Pos; + uint8_t epnum = (ctl_word & USB_OTG_GRXSTSP_EPNUM_Msk) >> USB_OTG_GRXSTSP_EPNUM_Pos; + uint16_t bcnt = (ctl_word & USB_OTG_GRXSTSP_BCNT_Msk) >> USB_OTG_GRXSTSP_BCNT_Pos; + + switch(pktsts) { + case 0x01: // Global OUT NAK (Interrupt) + break; + + case 0x02: // Out packet recvd + { + xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT); + + // Read packet off RxFIFO + if (xfer->ff) + { + // Ring buffer + tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void *) rx_fifo, bcnt); + } + else + { + // Linear buffer + read_fifo_packet(rhport, xfer->buffer, bcnt); + + // Increment pointer to xfer data + xfer->buffer += bcnt; + } + + // Truncate transfer length in case of short packet + if(bcnt < xfer->max_size) { + xfer->total_len -= (out_ep[epnum].DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ_Msk) >> USB_OTG_DOEPTSIZ_XFRSIZ_Pos; + if(epnum == 0) { + xfer->total_len -= ep0_pending[TUSB_DIR_OUT]; + ep0_pending[TUSB_DIR_OUT] = 0; + } + } + } + break; + + case 0x03: // Out packet done (Interrupt) + break; + + case 0x04: // Setup packet done (Interrupt) + out_ep[epnum].DOEPTSIZ |= (3 << USB_OTG_DOEPTSIZ_STUPCNT_Pos); + break; + + case 0x06: // Setup packet recvd + // We can receive up to three setup packets in succession, but + // only the last one is valid. + _setup_packet[0] = (* rx_fifo); + _setup_packet[1] = (* rx_fifo); + break; + + default: // Invalid + TU_BREAKPOINT(); + break; + } +} + +static void handle_epout_ints(uint8_t rhport, USB_OTG_DeviceTypeDef * dev, USB_OTG_OUTEndpointTypeDef * out_ep) { + // DAINT for a given EP clears when DOEPINTx is cleared. + // OEPINT will be cleared when DAINT's out bits are cleared. + for(uint8_t n = 0; n < EP_MAX; n++) { + xfer_ctl_t * xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT); + + if(dev->DAINT & (1 << (USB_OTG_DAINT_OEPINT_Pos + n))) { + // SETUP packet Setup Phase done. + if(out_ep[n].DOEPINT & USB_OTG_DOEPINT_STUP) { + out_ep[n].DOEPINT = USB_OTG_DOEPINT_STUP; + dcd_event_setup_received(rhport, (uint8_t*) &_setup_packet[0], true); + } + + // OUT XFER complete + if(out_ep[n].DOEPINT & USB_OTG_DOEPINT_XFRC) { + out_ep[n].DOEPINT = USB_OTG_DOEPINT_XFRC; + + // EP0 can only handle one packet + if((n == 0) && ep0_pending[TUSB_DIR_OUT]) { + // Schedule another packet to be received. + edpt_schedule_packets(rhport, n, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]); + } else { + dcd_event_xfer_complete(rhport, n, xfer->total_len, XFER_RESULT_SUCCESS, true); + } + } + } + } +} + +static void handle_epin_ints(uint8_t rhport, USB_OTG_DeviceTypeDef * dev, USB_OTG_INEndpointTypeDef * in_ep) { + // DAINT for a given EP clears when DIEPINTx is cleared. + // IEPINT will be cleared when DAINT's out bits are cleared. + for ( uint8_t n = 0; n < EP_MAX; n++ ) + { + xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_IN); + + if ( dev->DAINT & (1 << (USB_OTG_DAINT_IEPINT_Pos + n)) ) + { + // IN XFER complete (entire xfer). + if ( in_ep[n].DIEPINT & USB_OTG_DIEPINT_XFRC ) + { + in_ep[n].DIEPINT = USB_OTG_DIEPINT_XFRC; + + // EP0 can only handle one packet + if((n == 0) && ep0_pending[TUSB_DIR_IN]) { + // Schedule another packet to be transmitted. + edpt_schedule_packets(rhport, n, TUSB_DIR_IN, 1, ep0_pending[TUSB_DIR_IN]); + } else { + dcd_event_xfer_complete(rhport, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true); + } + } + + // XFER FIFO empty + if ( (in_ep[n].DIEPINT & USB_OTG_DIEPINT_TXFE) && (dev->DIEPEMPMSK & (1 << n)) ) + { + // DIEPINT's TXFE bit is read-only, software cannot clear it. + // It will only be cleared by hardware when written bytes is more than + // - 64 bytes or + // - Half of TX FIFO size (configured by DIEPTXF) + + uint16_t remaining_packets = (in_ep[n].DIEPTSIZ & USB_OTG_DIEPTSIZ_PKTCNT_Msk) >> USB_OTG_DIEPTSIZ_PKTCNT_Pos; + + // Process every single packet (only whole packets can be written to fifo) + for(uint16_t i = 0; i < remaining_packets; i++) + { + uint16_t const remaining_bytes = (in_ep[n].DIEPTSIZ & USB_OTG_DIEPTSIZ_XFRSIZ_Msk) >> USB_OTG_DIEPTSIZ_XFRSIZ_Pos; + + // Packet can not be larger than ep max size + uint16_t const packet_size = tu_min16(remaining_bytes, xfer->max_size); + + // It's only possible to write full packets into FIFO. Therefore DTXFSTS register of current + // EP has to be checked if the buffer can take another WHOLE packet + if(packet_size > ((in_ep[n].DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV_Msk) << 2)) break; + + // Push packet to Tx-FIFO + if (xfer->ff) + { + usb_fifo_t tx_fifo = FIFO_BASE(rhport, n); + tu_fifo_read_n_const_addr_full_words(xfer->ff, (void *) tx_fifo, packet_size); + } + else + { + write_fifo_packet(rhport, n, xfer->buffer, packet_size); + + // Increment pointer to xfer data + xfer->buffer += packet_size; + } + } + + // Turn off TXFE if all bytes are written. + if (((in_ep[n].DIEPTSIZ & USB_OTG_DIEPTSIZ_XFRSIZ_Msk) >> USB_OTG_DIEPTSIZ_XFRSIZ_Pos) == 0) + { + dev->DIEPEMPMSK &= ~(1 << n); + } + } + } + } +} + +void dcd_int_handler(uint8_t rhport) +{ + USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport); + USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport); + USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport); + USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport); + + uint32_t const int_status = usb_otg->GINTSTS & usb_otg->GINTMSK; + + if(int_status & USB_OTG_GINTSTS_USBRST) + { + // USBRST is start of reset. + usb_otg->GINTSTS = USB_OTG_GINTSTS_USBRST; + bus_reset(rhport); + } + + if(int_status & USB_OTG_GINTSTS_ENUMDNE) + { + // ENUMDNE is the end of reset where speed of the link is detected + + usb_otg->GINTSTS = USB_OTG_GINTSTS_ENUMDNE; + + tusb_speed_t const speed = get_speed(rhport); + + set_turnaround(usb_otg, speed); + dcd_event_bus_reset(rhport, speed, true); + } + + if(int_status & USB_OTG_GINTSTS_USBSUSP) + { + usb_otg->GINTSTS = USB_OTG_GINTSTS_USBSUSP; + dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); + } + + if(int_status & USB_OTG_GINTSTS_WKUINT) + { + usb_otg->GINTSTS = USB_OTG_GINTSTS_WKUINT; + dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true); + } + + // TODO check USB_OTG_GINTSTS_DISCINT for disconnect detection + // if(int_status & USB_OTG_GINTSTS_DISCINT) + + if(int_status & USB_OTG_GINTSTS_OTGINT) + { + // OTG INT bit is read-only + uint32_t const otg_int = usb_otg->GOTGINT; + + if (otg_int & USB_OTG_GOTGINT_SEDET) + { + dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true); + } + + usb_otg->GOTGINT = otg_int; + } + + if(int_status & USB_OTG_GINTSTS_SOF) + { + usb_otg->GINTSTS = USB_OTG_GINTSTS_SOF; + + // Disable SOF interrupt since currently only used for remote wakeup detection + usb_otg->GINTMSK &= ~USB_OTG_GINTMSK_SOFM; + + dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true); + } + + // RxFIFO non-empty interrupt handling. + if(int_status & USB_OTG_GINTSTS_RXFLVL) + { + // RXFLVL bit is read-only + + // Mask out RXFLVL while reading data from FIFO + usb_otg->GINTMSK &= ~USB_OTG_GINTMSK_RXFLVLM; + + // Loop until all available packets were handled + do + { + handle_rxflvl_ints(rhport, out_ep); + } while(usb_otg->GINTSTS & USB_OTG_GINTSTS_RXFLVL); + + // Manage RX FIFO size + if (_out_ep_closed) + { + update_grxfsiz(rhport); + + // Disable flag + _out_ep_closed = false; + } + + usb_otg->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; + } + + // OUT endpoint interrupt handling. + if(int_status & USB_OTG_GINTSTS_OEPINT) + { + // OEPINT is read-only + handle_epout_ints(rhport, dev, out_ep); + } + + // IN endpoint interrupt handling. + if(int_status & USB_OTG_GINTSTS_IEPINT) + { + // IEPINT bit read-only + handle_epin_ints(rhport, dev, in_ep); + } + + // // Check for Incomplete isochronous IN transfer + // if(int_status & USB_OTG_GINTSTS_IISOIXFR) { + // printf(" IISOIXFR!\r\n"); + //// TU_LOG2(" IISOIXFR!\r\n"); + // } +} + +#endif diff --git a/src/portable/broadcom/synopsys/synopsys_common.h b/src/portable/broadcom/synopsys/synopsys_common.h new file mode 100644 index 000000000..6f0602fe9 --- /dev/null +++ b/src/portable/broadcom/synopsys/synopsys_common.h @@ -0,0 +1,1465 @@ +/** + ****************************************************************************** + * @file synopsys_common.h + * @author MCD Application Team + * @brief CMSIS Cortex-M3 Device USB OTG peripheral Header File. + * This file contains the USB OTG peripheral register's definitions, bits + * definitions and memory mapping for STM32F1xx devices. + * + * This file contains: + * - Data structures and the address mapping for the USB OTG peripheral + * - The Peripheral's registers declarations and bits definition + * - Macros to access the peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +#include "stdint.h" + +#pragma once + +#ifdef __cplusplus + #define __I volatile +#else + #define __I volatile const +#endif +#define __O volatile +#define __IO volatile +#define __IM volatile const +#define __OM volatile +#define __IOM volatile + +/** + * @brief __USB_OTG_Core_register + */ + +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register Address offset: 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register Address offset: 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register Address offset: 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register Address offset: 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register Address offset: 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register Address offset: 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register Address offset: 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register Address offset: 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register Address offset: 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register Address offset: 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register Address offset: 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset: 02Ch */ + uint32_t Reserved30[2]; /*!< Reserved 030h*/ + __IO uint32_t GCCFG; /*!< General Purpose IO Register Address offset: 038h */ + __IO uint32_t CID; /*!< User ID Register Address offset: 03Ch */ + uint32_t Reserved40[48]; /*!< Reserved 040h-0FFh */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg Address offset: 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO Address offset: 0x104 */ +} USB_OTG_GlobalTypeDef; + +/** + * @brief __device_Registers + */ + +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register Address offset: 800h*/ + __IO uint32_t DCTL; /*!< dev Control Register Address offset: 804h*/ + __IO uint32_t DSTS; /*!< dev Status Register (RO) Address offset: 808h*/ + uint32_t Reserved0C; /*!< Reserved 80Ch*/ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask Address offset: 810h*/ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask Address offset: 814h*/ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg Address offset: 818h*/ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask Address offset: 81Ch*/ + uint32_t Reserved20; /*!< Reserved 820h*/ + uint32_t Reserved9; /*!< Reserved 824h*/ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register Address offset: 828h*/ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register Address offset: 82Ch*/ + __IO uint32_t DTHRCTL; /*!< dev thr Address offset: 830h*/ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk Address offset: 834h*/ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset: 838h*/ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset: 83Ch*/ + uint32_t Reserved40; /*!< dedicated EP mask Address offset: 840h*/ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask Address offset: 844h*/ + uint32_t Reserved44[15]; /*!< Reserved 844-87Ch*/ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset: 884h*/ +} USB_OTG_DeviceTypeDef; + +/** + * @brief __IN_Endpoint-Specific_Register + */ + +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/ + uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h*/ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/ + uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch*/ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/ + uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/ +} USB_OTG_INEndpointTypeDef; + +/** + * @brief __OUT_Endpoint-Specific_Registers + */ + +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/ + uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h*/ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/ + uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch*/ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/ + uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/ +} USB_OTG_OUTEndpointTypeDef; + +/** + * @brief __Host_Mode_Register_Structures + */ + +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register 400h*/ + __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h*/ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h*/ + uint32_t Reserved40C; /*!< Reserved 40Ch*/ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h*/ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h*/ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h*/ +} USB_OTG_HostTypeDef; + +/** + * @brief __Host_Channel_Specific_Registers + */ + +typedef struct +{ + __IO uint32_t HCCHAR; + __IO uint32_t HCSPLT; + __IO uint32_t HCINT; + __IO uint32_t HCINTMSK; + __IO uint32_t HCTSIZ; + __IO uint32_t HCDMA; + uint32_t Reserved[2]; +} USB_OTG_HostChannelTypeDef; + +/*!< USB registers base address */ +#define USB_OTG_FS_PERIPH_BASE 0x50000000UL + +#define USB_OTG_GLOBAL_BASE 0x00000000UL +#define USB_OTG_DEVICE_BASE 0x00000800UL +#define USB_OTG_IN_ENDPOINT_BASE 0x00000900UL +#define USB_OTG_OUT_ENDPOINT_BASE 0x00000B00UL +#define USB_OTG_EP_REG_SIZE 0x00000020UL +#define USB_OTG_HOST_BASE 0x00000400UL +#define USB_OTG_HOST_PORT_BASE 0x00000440UL +#define USB_OTG_HOST_CHANNEL_BASE 0x00000500UL +#define USB_OTG_HOST_CHANNEL_SIZE 0x00000020UL +#define USB_OTG_PCGCCTL_BASE 0x00000E00UL +#define USB_OTG_FIFO_BASE 0x00001000UL +#define USB_OTG_FIFO_SIZE 0x00001000UL + +/******************************************************************************/ +/* */ +/* USB_OTG */ +/* */ +/******************************************************************************/ +/******************** Bit definition for USB_OTG_GOTGCTL register ***********/ +#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U) +#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */ +#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */ +#define USB_OTG_GOTGCTL_SRQ_Pos (1U) +#define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */ +#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */ +#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U) +#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */ +#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */ +#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U) +#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */ +#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */ +#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U) +#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */ +#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */ +#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U) +#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */ +#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */ +#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) +#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ +#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ +#define USB_OTG_GOTGCTL_DBCT_Pos (17U) +#define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ +#define USB_OTG_GOTGCTL_ASVLD_Pos (18U) +#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ +#define USB_OTG_GOTGCTL_BSVLD_Pos (19U) +#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */ + +/******************** Bit definition for USB_OTG_HCFG register ********************/ + +#define USB_OTG_HCFG_FSLSPCS_Pos (0U) +#define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */ +#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */ +#define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */ +#define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */ +#define USB_OTG_HCFG_FSLSS_Pos (2U) +#define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */ + +/******************** Bit definition for USB_OTG_DCFG register ********************/ + +#define USB_OTG_DCFG_DSPD_Pos (0U) +#define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */ +#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */ +#define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */ +#define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */ +#define USB_OTG_DCFG_NZLSOHSK_Pos (2U) +#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */ +#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */ + +#define USB_OTG_DCFG_DAD_Pos (4U) +#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */ +#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ +#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */ +#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */ +#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */ +#define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */ +#define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */ +#define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */ +#define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */ + +#define USB_OTG_DCFG_PFIVL_Pos (11U) +#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */ +#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ +#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ +#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ + +#define USB_OTG_DCFG_PERSCHIVL_Pos (24U) +#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ +#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ +#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */ +#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */ + +/******************** Bit definition for USB_OTG_PCGCR register ********************/ +#define USB_OTG_PCGCR_STPPCLK_Pos (0U) +#define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */ +#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */ +#define USB_OTG_PCGCR_GATEHCLK_Pos (1U) +#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */ +#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */ +#define USB_OTG_PCGCR_PHYSUSP_Pos (4U) +#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */ +#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */ + +/******************** Bit definition for USB_OTG_GOTGINT register ********************/ +#define USB_OTG_GOTGINT_SEDET_Pos (2U) +#define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */ +#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */ +#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U) +#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */ +#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */ +#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U) +#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */ +#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */ +#define USB_OTG_GOTGINT_HNGDET_Pos (17U) +#define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */ +#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U) +#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */ +#define USB_OTG_GOTGINT_DBCDNE_Pos (19U) +#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */ + +/******************** Bit definition for USB_OTG_DCTL register ********************/ +#define USB_OTG_DCTL_RWUSIG_Pos (0U) +#define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */ +#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */ +#define USB_OTG_DCTL_SDIS_Pos (1U) +#define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */ +#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */ +#define USB_OTG_DCTL_GINSTS_Pos (2U) +#define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */ +#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */ +#define USB_OTG_DCTL_GONSTS_Pos (3U) +#define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */ +#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */ + +#define USB_OTG_DCTL_TCTL_Pos (4U) +#define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */ +#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */ +#define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */ +#define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */ +#define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */ +#define USB_OTG_DCTL_SGINAK_Pos (7U) +#define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */ +#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */ +#define USB_OTG_DCTL_CGINAK_Pos (8U) +#define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */ +#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */ +#define USB_OTG_DCTL_SGONAK_Pos (9U) +#define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */ +#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */ +#define USB_OTG_DCTL_CGONAK_Pos (10U) +#define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */ +#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */ +#define USB_OTG_DCTL_POPRGDNE_Pos (11U) +#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ +#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ + +/******************** Bit definition for USB_OTG_HFIR register ********************/ +#define USB_OTG_HFIR_FRIVL_Pos (0U) +#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ + +/******************** Bit definition for USB_OTG_HFNUM register ********************/ +#define USB_OTG_HFNUM_FRNUM_Pos (0U) +#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */ +#define USB_OTG_HFNUM_FTREM_Pos (16U) +#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */ + +/******************** Bit definition for USB_OTG_DSTS register ********************/ +#define USB_OTG_DSTS_SUSPSTS_Pos (0U) +#define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */ +#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */ + +#define USB_OTG_DSTS_ENUMSPD_Pos (1U) +#define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */ +#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */ +#define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */ +#define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */ +#define USB_OTG_DSTS_EERR_Pos (3U) +#define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */ +#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */ +#define USB_OTG_DSTS_FNSOF_Pos (8U) +#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ +#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ + +/******************** Bit definition for USB_OTG_GAHBCFG register ********************/ +#define USB_OTG_GAHBCFG_GINT_Pos (0U) +#define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ +#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ +#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) +#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ +#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ +#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */ +#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */ +#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */ +#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */ +#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */ +#define USB_OTG_GAHBCFG_DMAEN_Pos (5U) +#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */ +#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */ +#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U) +#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */ +#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */ +#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U) +#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */ +#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */ + +/******************** Bit definition for USB_OTG_GUSBCFG register ********************/ + +#define USB_OTG_GUSBCFG_TOCAL_Pos (0U) +#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */ +#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */ +#define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */ +#define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */ +#define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */ +#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U) +#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */ +#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */ +#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U) +#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */ +#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */ +#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U) +#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */ +#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */ +#define USB_OTG_GUSBCFG_TRDT_Pos (10U) +#define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */ +#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */ +#define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */ +#define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ +#define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ +#define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ +#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) +#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ +#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ +#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) +#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ +#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ +#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U) +#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */ +#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */ +#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U) +#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */ +#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */ +#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U) +#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */ +#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */ +#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U) +#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */ +#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */ +#define USB_OTG_GUSBCFG_TSDPS_Pos (22U) +#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */ +#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */ +#define USB_OTG_GUSBCFG_PCCI_Pos (23U) +#define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */ +#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */ +#define USB_OTG_GUSBCFG_PTCI_Pos (24U) +#define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */ +#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */ +#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U) +#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */ +#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */ +#define USB_OTG_GUSBCFG_FHMOD_Pos (29U) +#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */ +#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */ +#define USB_OTG_GUSBCFG_FDMOD_Pos (30U) +#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */ +#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */ +#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U) +#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */ + +/******************** Bit definition for USB_OTG_GRSTCTL register ********************/ +#define USB_OTG_GRSTCTL_CSRST_Pos (0U) +#define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ +#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ +#define USB_OTG_GRSTCTL_HSRST_Pos (1U) +#define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ +#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ +#define USB_OTG_GRSTCTL_FCRST_Pos (2U) +#define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ +#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ +#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U) +#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */ +#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */ +#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U) +#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */ +#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */ + + +#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U) +#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */ +#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */ +#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */ +#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */ +#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */ +#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */ +#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */ +#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U) +#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */ +#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */ +#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U) +#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */ +#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */ + +/******************** Bit definition for USB_OTG_DIEPMSK register ********************/ +#define USB_OTG_DIEPMSK_XFRCM_Pos (0U) +#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */ +#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */ +#define USB_OTG_DIEPMSK_EPDM_Pos (1U) +#define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ +#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPMSK_TOM_Pos (3U) +#define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ +#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ +#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U) +#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */ +#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ +#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U) +#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ +#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U) +#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */ +#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ +#define USB_OTG_DIEPMSK_TXFURM_Pos (8U) +#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */ +#define USB_OTG_DIEPMSK_BIM_Pos (9U) +#define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ +#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ + +/******************** Bit definition for USB_OTG_HPTXSTS register ********************/ +#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) +#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */ +#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U) +#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */ +#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */ +#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */ + +#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U) +#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */ +#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for USB_OTG_HAINT register ********************/ +#define USB_OTG_HAINT_HAINT_Pos (0U) +#define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */ + +/******************** Bit definition for USB_OTG_DOEPMSK register ********************/ +#define USB_OTG_DOEPMSK_XFRCM_Pos (0U) +#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */ +#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */ +#define USB_OTG_DOEPMSK_EPDM_Pos (1U) +#define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ +#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< OUT transaction AHB Error interrupt mask */ +#define USB_OTG_DOEPMSK_STUPM_Pos (3U) +#define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ +#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ +#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) +#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ +#define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U) +#define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */ +#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) +#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ +#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ +#define USB_OTG_DOEPMSK_OPEM_Pos (8U) +#define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPMSK_BOIM_Pos (9U) +#define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ +#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DOEPMSK_BERRM_Pos (12U) +#define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ +#define USB_OTG_DOEPMSK_NAKM_Pos (13U) +#define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk /*!< OUT Packet NAK interrupt mask */ +#define USB_OTG_DOEPMSK_NYETM_Pos (14U) +#define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk /*!< NYET interrupt mask */ +/******************** Bit definition for USB_OTG_GINTSTS register ********************/ +#define USB_OTG_GINTSTS_CMOD_Pos (0U) +#define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */ +#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */ +#define USB_OTG_GINTSTS_MMIS_Pos (1U) +#define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */ +#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */ +#define USB_OTG_GINTSTS_OTGINT_Pos (2U) +#define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */ +#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */ +#define USB_OTG_GINTSTS_SOF_Pos (3U) +#define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */ +#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */ +#define USB_OTG_GINTSTS_RXFLVL_Pos (4U) +#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */ +#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */ +#define USB_OTG_GINTSTS_NPTXFE_Pos (5U) +#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */ +#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */ +#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) +#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ +#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ +#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) +#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ +#define USB_OTG_GINTSTS_ESUSP_Pos (10U) +#define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ +#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ +#define USB_OTG_GINTSTS_USBSUSP_Pos (11U) +#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */ +#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */ +#define USB_OTG_GINTSTS_USBRST_Pos (12U) +#define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */ +#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */ +#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U) +#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */ +#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */ +#define USB_OTG_GINTSTS_ISOODRP_Pos (14U) +#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */ +#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */ +#define USB_OTG_GINTSTS_EOPF_Pos (15U) +#define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */ +#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */ +#define USB_OTG_GINTSTS_IEPINT_Pos (18U) +#define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */ +#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */ +#define USB_OTG_GINTSTS_OEPINT_Pos (19U) +#define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */ +#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */ +#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U) +#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */ +#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */ +#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U) +#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */ +#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */ +#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) +#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ +#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ +#define USB_OTG_GINTSTS_HPRTINT_Pos (24U) +#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ +#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ +#define USB_OTG_GINTSTS_HCINT_Pos (25U) +#define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */ +#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */ +#define USB_OTG_GINTSTS_PTXFE_Pos (26U) +#define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */ +#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */ +#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U) +#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */ +#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */ +#define USB_OTG_GINTSTS_DISCINT_Pos (29U) +#define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */ +#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */ +#define USB_OTG_GINTSTS_SRQINT_Pos (30U) +#define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ +#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ +#define USB_OTG_GINTSTS_WKUINT_Pos (31U) +#define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ + +/******************** Bit definition for USB_OTG_GINTMSK register ********************/ +#define USB_OTG_GINTMSK_MMISM_Pos (1U) +#define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */ +#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */ +#define USB_OTG_GINTMSK_OTGINT_Pos (2U) +#define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */ +#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */ +#define USB_OTG_GINTMSK_SOFM_Pos (3U) +#define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */ +#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */ +#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U) +#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */ +#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */ +#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U) +#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */ +#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */ +#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U) +#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */ +#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */ +#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U) +#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */ +#define USB_OTG_GINTMSK_ESUSPM_Pos (10U) +#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */ +#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */ +#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U) +#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */ +#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */ +#define USB_OTG_GINTMSK_USBRST_Pos (12U) +#define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */ +#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */ +#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U) +#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */ +#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */ +#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U) +#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */ +#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */ +#define USB_OTG_GINTMSK_EOPFM_Pos (15U) +#define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */ +#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */ +#define USB_OTG_GINTMSK_EPMISM_Pos (17U) +#define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */ +#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */ +#define USB_OTG_GINTMSK_IEPINT_Pos (18U) +#define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */ +#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */ +#define USB_OTG_GINTMSK_OEPINT_Pos (19U) +#define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */ +#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */ +#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) +#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ +#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ +#define USB_OTG_GINTMSK_FSUSPM_Pos (22U) +#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ +#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ +#define USB_OTG_GINTMSK_PRTIM_Pos (24U) +#define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ +#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ +#define USB_OTG_GINTMSK_HCIM_Pos (25U) +#define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */ +#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */ +#define USB_OTG_GINTMSK_PTXFEM_Pos (26U) +#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */ +#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */ +#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U) +#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */ +#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */ +#define USB_OTG_GINTMSK_DISCINT_Pos (29U) +#define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */ +#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */ +#define USB_OTG_GINTMSK_SRQIM_Pos (30U) +#define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */ +#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */ +#define USB_OTG_GINTMSK_WUIM_Pos (31U) +#define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */ + +/******************** Bit definition for USB_OTG_DAINT register ********************/ +#define USB_OTG_DAINT_IEPINT_Pos (0U) +#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */ +#define USB_OTG_DAINT_OEPINT_Pos (16U) +#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */ + +/******************** Bit definition for USB_OTG_HAINTMSK register ********************/ +#define USB_OTG_HAINTMSK_HAINTM_Pos (0U) +#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ + +/******************** Bit definition for USB_OTG_GRXSTSP register ********************/ +#define USB_OTG_GRXSTSP_EPNUM_Pos (0U) +#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_BCNT_Pos (4U) +#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_DPID_Pos (15U) +#define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) +#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ + +/******************** Bit definition for USB_OTG_DAINTMSK register ********************/ +#define USB_OTG_DAINTMSK_IEPM_Pos (0U) +#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_DAINTMSK_OEPM_Pos (16U) +#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */ + +/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/ +#define USB_OTG_GRXFSIZ_RXFD_Pos (0U) +#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */ + +/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/ +#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U) +#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */ + +/******************** Bit definition for OTG register ********************/ +#define USB_OTG_NPTXFSA_Pos (0U) +#define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */ +#define USB_OTG_NPTXFD_Pos (16U) +#define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */ +#define USB_OTG_TX0FSA_Pos (0U) +#define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */ +#define USB_OTG_TX0FD_Pos (16U) +#define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */ + +/******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/ +#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U) +#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */ +#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */ + +/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/ +#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U) +#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */ + +#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U) +#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */ + +#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U) +#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for USB_OTG_DTHRCTL register ********************/ +#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U) +#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */ +#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */ +#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U) +#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */ +#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */ + +#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U) +#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */ +#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */ +#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */ +#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U) +#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */ +#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */ + +#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U) +#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */ +#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */ +#define USB_OTG_DTHRCTL_ARPEN_Pos (27U) +#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */ +#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */ + +/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/ +#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U) +#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */ + +/******************** Bit definition for USB_OTG_DEACHINT register ********************/ +#define USB_OTG_DEACHINT_IEP1INT_Pos (1U) +#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */ +#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */ +#define USB_OTG_DEACHINT_OEP1INT_Pos (17U) +#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */ +#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */ + +/******************** Bit definition for USB_OTG_GCCFG register ********************/ +#define USB_OTG_GCCFG_PWRDWN_Pos (16U) +#define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */ +#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */ +#define USB_OTG_GCCFG_VBUSASEN_Pos (18U) +#define USB_OTG_GCCFG_VBUSASEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */ +#define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk /*!< Enable the VBUS sensing device */ +#define USB_OTG_GCCFG_VBUSBSEN_Pos (19U) +#define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */ +#define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk /*!< Enable the VBUS sensing device */ +#define USB_OTG_GCCFG_SOFOUTEN_Pos (20U) +#define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */ +#define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk /*!< SOF output enable */ + +/******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/ +#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U) +#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */ +#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */ +#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U) +#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */ +#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */ + +/******************** Bit definition for USB_OTG_CID register ********************/ +#define USB_OTG_CID_PRODUCT_ID_Pos (0U) +#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */ +#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */ + +/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ +#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) +#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */ +#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */ +#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U) +#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */ +#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U) +#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */ +#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ +#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U) +#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */ +#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ +#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U) +#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ +#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U) +#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */ +#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ +#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U) +#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */ +#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U) +#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */ +#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U) +#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */ + +/******************** Bit definition for USB_OTG_HPRT register ********************/ +#define USB_OTG_HPRT_PCSTS_Pos (0U) +#define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */ +#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */ +#define USB_OTG_HPRT_PCDET_Pos (1U) +#define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */ +#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */ +#define USB_OTG_HPRT_PENA_Pos (2U) +#define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */ +#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */ +#define USB_OTG_HPRT_PENCHNG_Pos (3U) +#define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */ +#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */ +#define USB_OTG_HPRT_POCA_Pos (4U) +#define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */ +#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */ +#define USB_OTG_HPRT_POCCHNG_Pos (5U) +#define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */ +#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */ +#define USB_OTG_HPRT_PRES_Pos (6U) +#define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */ +#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */ +#define USB_OTG_HPRT_PSUSP_Pos (7U) +#define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */ +#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */ +#define USB_OTG_HPRT_PRST_Pos (8U) +#define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ +#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ + +#define USB_OTG_HPRT_PLSTS_Pos (10U) +#define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ +#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ +#define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */ +#define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */ +#define USB_OTG_HPRT_PPWR_Pos (12U) +#define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ +#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ + +#define USB_OTG_HPRT_PTCTL_Pos (13U) +#define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ +#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ +#define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */ +#define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ +#define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ +#define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ + +#define USB_OTG_HPRT_PSPD_Pos (17U) +#define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ +#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ +#define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */ +#define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/ +#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U) +#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */ +#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U) +#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */ +#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U) +#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */ +#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */ +#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U) +#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ +#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U) +#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ +#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U) +#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */ +#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ +#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U) +#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U) +#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */ +#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U) +#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U) +#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U) +#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */ + +/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/ +#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) +#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ +#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) +#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ + +/******************** Bit definition for USB_OTG_DIEPCTL register ********************/ +#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) +#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */ +#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */ +#define USB_OTG_DIEPCTL_USBAEP_Pos (15U) +#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */ +#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */ +#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U) +#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */ +#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */ +#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U) +#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ +#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */ + +#define USB_OTG_DIEPCTL_EPTYP_Pos (18U) +#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ +#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */ +#define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */ +#define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */ +#define USB_OTG_DIEPCTL_STALL_Pos (21U) +#define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */ +#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */ + +#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U) +#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */ +#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */ +#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */ +#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */ +#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */ +#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */ +#define USB_OTG_DIEPCTL_CNAK_Pos (26U) +#define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */ +#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */ +#define USB_OTG_DIEPCTL_SNAK_Pos (27U) +#define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */ +#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ +#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) +#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ +#define USB_OTG_DIEPCTL_EPDIS_Pos (30U) +#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ +#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ +#define USB_OTG_DIEPCTL_EPENA_Pos (31U) +#define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */ +#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */ + +/******************** Bit definition for USB_OTG_HCCHAR register ********************/ +#define USB_OTG_HCCHAR_MPSIZ_Pos (0U) +#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ +#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ + +#define USB_OTG_HCCHAR_EPNUM_Pos (11U) +#define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ +#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ +#define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */ +#define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */ +#define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */ +#define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */ +#define USB_OTG_HCCHAR_EPDIR_Pos (15U) +#define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */ +#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */ +#define USB_OTG_HCCHAR_LSDEV_Pos (17U) +#define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ +#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ + +#define USB_OTG_HCCHAR_EPTYP_Pos (18U) +#define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ +#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ +#define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ +#define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ + +#define USB_OTG_HCCHAR_MC_Pos (20U) +#define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ +#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ +#define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ +#define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ + +#define USB_OTG_HCCHAR_DAD_Pos (22U) +#define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ +#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ +#define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */ +#define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */ +#define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */ +#define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */ +#define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */ +#define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */ +#define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */ +#define USB_OTG_HCCHAR_ODDFRM_Pos (29U) +#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */ +#define USB_OTG_HCCHAR_CHDIS_Pos (30U) +#define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */ +#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */ +#define USB_OTG_HCCHAR_CHENA_Pos (31U) +#define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */ + +/******************** Bit definition for USB_OTG_HCSPLT register ********************/ + +#define USB_OTG_HCSPLT_PRTADDR_Pos (0U) +#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */ +#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */ +#define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */ +#define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */ +#define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */ +#define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */ +#define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */ +#define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */ + +#define USB_OTG_HCSPLT_HUBADDR_Pos (7U) +#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */ +#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */ +#define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */ +#define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */ +#define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */ +#define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */ +#define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */ +#define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */ +#define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */ + +#define USB_OTG_HCSPLT_XACTPOS_Pos (14U) +#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */ +#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */ +#define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */ +#define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */ +#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U) +#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */ +#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */ +#define USB_OTG_HCSPLT_SPLITEN_Pos (31U) +#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */ + +/******************** Bit definition for USB_OTG_HCINT register ********************/ +#define USB_OTG_HCINT_XFRC_Pos (0U) +#define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */ +#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */ +#define USB_OTG_HCINT_CHH_Pos (1U) +#define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */ +#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */ +#define USB_OTG_HCINT_AHBERR_Pos (2U) +#define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINT_STALL_Pos (3U) +#define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */ +#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */ +#define USB_OTG_HCINT_NAK_Pos (4U) +#define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */ +#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */ +#define USB_OTG_HCINT_ACK_Pos (5U) +#define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */ +#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */ +#define USB_OTG_HCINT_NYET_Pos (6U) +#define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */ +#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */ +#define USB_OTG_HCINT_TXERR_Pos (7U) +#define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */ +#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */ +#define USB_OTG_HCINT_BBERR_Pos (8U) +#define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */ +#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */ +#define USB_OTG_HCINT_FRMOR_Pos (9U) +#define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */ +#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */ +#define USB_OTG_HCINT_DTERR_Pos (10U) +#define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */ +#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */ + +/******************** Bit definition for USB_OTG_DIEPINT register ********************/ +#define USB_OTG_DIEPINT_XFRC_Pos (0U) +#define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */ +#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */ +#define USB_OTG_DIEPINT_EPDISD_Pos (1U) +#define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */ +#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ +#define USB_OTG_DIEPINT_AHBERR_Pos (2U) +#define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an IN transaction */ +#define USB_OTG_DIEPINT_TOC_Pos (3U) +#define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */ +#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */ +#define USB_OTG_DIEPINT_ITTXFE_Pos (4U) +#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ +#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ +#define USB_OTG_DIEPINT_INEPNM_Pos (5U) +#define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ +#define USB_OTG_DIEPINT_INEPNE_Pos (6U) +#define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ +#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ +#define USB_OTG_DIEPINT_TXFE_Pos (7U) +#define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */ +#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */ +#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U) +#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */ +#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */ +#define USB_OTG_DIEPINT_BNA_Pos (9U) +#define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */ +#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */ +#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U) +#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */ +#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */ +#define USB_OTG_DIEPINT_BERR_Pos (12U) +#define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */ +#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */ +#define USB_OTG_DIEPINT_NAK_Pos (13U) +#define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */ + +/******************** Bit definition for USB_OTG_HCINTMSK register ********************/ +#define USB_OTG_HCINTMSK_XFRCM_Pos (0U) +#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */ +#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */ +#define USB_OTG_HCINTMSK_CHHM_Pos (1U) +#define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ +#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ +#define USB_OTG_HCINTMSK_AHBERR_Pos (2U) +#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINTMSK_STALLM_Pos (3U) +#define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ +#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ +#define USB_OTG_HCINTMSK_NAKM_Pos (4U) +#define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */ +#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */ +#define USB_OTG_HCINTMSK_ACKM_Pos (5U) +#define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */ +#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */ +#define USB_OTG_HCINTMSK_NYET_Pos (6U) +#define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */ +#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */ +#define USB_OTG_HCINTMSK_TXERRM_Pos (7U) +#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */ +#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */ +#define USB_OTG_HCINTMSK_BBERRM_Pos (8U) +#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */ +#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */ +#define USB_OTG_HCINTMSK_FRMORM_Pos (9U) +#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */ +#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */ +#define USB_OTG_HCINTMSK_DTERRM_Pos (10U) +#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */ +#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */ + +/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/ + +#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U) +#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ +#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */ +#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) +#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ +#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ +#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) +#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ +#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ +/******************** Bit definition for USB_OTG_HCTSIZ register ********************/ +#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) +#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ +#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */ +#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) +#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ +#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ +#define USB_OTG_HCTSIZ_DOPING_Pos (31U) +#define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ +#define USB_OTG_HCTSIZ_DPID_Pos (29U) +#define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ +#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ +#define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ +#define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for USB_OTG_DIEPDMA register ********************/ +#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) +#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */ +#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */ + +/******************** Bit definition for USB_OTG_HCDMA register ********************/ +#define USB_OTG_HCDMA_DMAADDR_Pos (0U) +#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */ +#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */ + +/******************** Bit definition for USB_OTG_DTXFSTS register ********************/ +#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U) +#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */ + +/******************** Bit definition for USB_OTG_DIEPTXF register ********************/ +#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U) +#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */ +#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U) +#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */ + +/******************** Bit definition for USB_OTG_DOEPCTL register ********************/ + +#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U) +#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */ +#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*! Date: Sat, 18 Sep 2021 16:53:16 +0700 Subject: update dcd attr for mm32 --- src/device/dcd_attr.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/device/dcd_attr.h b/src/device/dcd_attr.h index a35fc0ac5..44f2cc1d6 100644 --- a/src/device/dcd_attr.h +++ b/src/device/dcd_attr.h @@ -63,6 +63,9 @@ #elif TU_CHECK_MCU(MKL25ZXX) || TU_CHECK_MCU(K32L2BXX) #define DCD_ATTR_ENDPOINT_MAX 16 +#elif TU_CHECK_MCU(MM32F327X) + #define DCD_ATTR_ENDPOINT_MAX 16 + //------------- Nordic -------------// #elif TU_CHECK_MCU(NRF5X) // 8 CBI + 1 ISO -- cgit v1.3.1 From 829f92d00f05167f788375a2a4e0ff5342bb30f7 Mon Sep 17 00:00:00 2001 From: Scott Shawcroft Date: Wed, 22 Sep 2021 15:19:02 -0700 Subject: Trying to setup the mmu --- hw/bsp/raspberrypi4/family.c | 24 +++++++++-------- hw/bsp/raspberrypi4/family.mk | 3 ++- hw/mcu/broadcom/bcm2711/boot.s | 4 ++- hw/mcu/broadcom/bcm2711/link.ld | 16 +++++++++--- hw/mcu/broadcom/bcm2711/mmu.c | 58 +++++++++++++++++++++++++++++++++++++++++ hw/mcu/broadcom/bcm2711/mmu.h | 44 +++++++++++++++++++++++++++++++ 6 files changed, 132 insertions(+), 17 deletions(-) create mode 100644 hw/mcu/broadcom/bcm2711/mmu.c create mode 100644 hw/mcu/broadcom/bcm2711/mmu.h diff --git a/hw/bsp/raspberrypi4/family.c b/hw/bsp/raspberrypi4/family.c index b2665f42d..6266d5a35 100644 --- a/hw/bsp/raspberrypi4/family.c +++ b/hw/bsp/raspberrypi4/family.c @@ -28,6 +28,7 @@ #include "board.h" #include "io.h" +#include "mmu.h" //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler @@ -55,6 +56,7 @@ void board_init(void) gpio_initOutputPinWithPullNone(18); gpio_setPinOutputBool(18, true); gpio_initOutputPinWithPullNone(42); + setup_mmu_flat_map(); // gpio_initOutputPinWithPullNone(23); // gpio_initOutputPinWithPullNone(24); // gpio_initOutputPinWithPullNone(25); @@ -83,17 +85,17 @@ void board_init(void) // gpio_setPinOutputBool(25, true); print(); // gpio_setPinOutputBool(25, false); - while (true) { - // for (size_t i = 0; i < 5; i++) { - for (size_t j = 0; j < 10000000000; j++) { - __asm__("nop"); - } - gpio_setPinOutputBool(42, true); - for (size_t j = 0; j < 10000000000; j++) { - __asm__("nop"); - } - gpio_setPinOutputBool(42, false); - } + // while (true) { + // // for (size_t i = 0; i < 5; i++) { + // for (size_t j = 0; j < 10000000000; j++) { + // __asm__("nop"); + // } + // gpio_setPinOutputBool(42, true); + // for (size_t j = 0; j < 10000000000; j++) { + // __asm__("nop"); + // } + // gpio_setPinOutputBool(42, false); + // } // while (1) uart_update(); } diff --git a/hw/bsp/raspberrypi4/family.mk b/hw/bsp/raspberrypi4/family.mk index 2d5c78d22..1547beee1 100644 --- a/hw/bsp/raspberrypi4/family.mk +++ b/hw/bsp/raspberrypi4/family.mk @@ -18,8 +18,9 @@ CFLAGS += \ SRC_C += \ src/portable/broadcom/synopsys/dcd_synopsys.c \ + $(MCU_DIR)/interrupts.c \ $(MCU_DIR)/io.c \ - $(MCU_DIR)/interrupts.c + $(MCU_DIR)/mmu.c CROSS_COMPILE = aarch64-none-elf- diff --git a/hw/mcu/broadcom/bcm2711/boot.s b/hw/mcu/broadcom/bcm2711/boot.s index 076b3a76a..dcc588924 100644 --- a/hw/mcu/broadcom/bcm2711/boot.s +++ b/hw/mcu/broadcom/bcm2711/boot.s @@ -19,7 +19,7 @@ _start: adr x0, vectors // load VBAR_EL1 with virtual // msr vbar_el3, x0 // vector table address msr vbar_el1, x0 // vector table address - // msr vbar_el2, x0 // vector table address + msr vbar_el2, x0 // vector table address isb // Clean the BSS section @@ -45,6 +45,8 @@ irq_entry mov x0, #\type mrs x1, esr_el1 mrs x2, elr_el1 +mrs x3, esr_el2 +mrs x4, elr_el2 b err_hang .endm diff --git a/hw/mcu/broadcom/bcm2711/link.ld b/hw/mcu/broadcom/bcm2711/link.ld index 0d5ebe2ab..43c4e722f 100644 --- a/hw/mcu/broadcom/bcm2711/link.ld +++ b/hw/mcu/broadcom/bcm2711/link.ld @@ -1,12 +1,20 @@ SECTIONS { . = 0x80000; /* Kernel load address for AArch64 */ - .text : { KEEP(*(.text.boot)) *(.text .text.* .gnu.linkonce.t*) } - .rodata : { *(.rodata .rodata.* .gnu.linkonce.r*) } + .text : { + KEEP(*(.text.boot)) + *(.text .text.* .gnu.linkonce.t*) + } + .rodata : { + . = ALIGN(4096); + *(.rodata .rodata.* .gnu.linkonce.r*) + } PROVIDE(_data = .); - .data : { *(.data .data.* .gnu.linkonce.d*) } + .data : { + . = ALIGN(4096); + *(.data .data.* .gnu.linkonce.d*) + } .bss (NOLOAD) : { - . = ALIGN(16); __bss_start = .; *(.bss .bss.*) *(COMMON) diff --git a/hw/mcu/broadcom/bcm2711/mmu.c b/hw/mcu/broadcom/bcm2711/mmu.c new file mode 100644 index 000000000..3c20436e6 --- /dev/null +++ b/hw/mcu/broadcom/bcm2711/mmu.c @@ -0,0 +1,58 @@ +#include +#include + + +#include "mmu.h" + +// Each entry is a gig. +volatile uint64_t level_1_table[32] __attribute__((aligned(4096))); + +// Third gig has peripherals +uint64_t level_2_0x0_c000_0000_to_0x1_0000_0000[512] __attribute__((aligned(4096))); + +void setup_mmu_flat_map(void) { + // Set the first gig to regular access. + level_1_table[0] = 0x0000000000000000 | + MM_DESCRIPTOR_MAIR_INDEX(MT_NORMAL_NC) | + MM_DESCRIPTOR_BLOCK | + MM_DESCRIPTOR_VALID; + level_1_table[2] = ((uint64_t) level_2_0x0_c000_0000_to_0x1_0000_0000) | + MM_DESCRIPTOR_TABLE | + MM_DESCRIPTOR_VALID; + // Set peripherals to register access. + for (uint64_t i = 480; i < 512; i++) { + level_2_0x0_c000_0000_to_0x1_0000_0000[i] = (0x00000000c0000000 + (i << 21)) | + MM_DESCRIPTOR_EXECUTE_NEVER | + MM_DESCRIPTOR_MAIR_INDEX(MT_DEVICE_nGnRnE) | + MM_DESCRIPTOR_BLOCK | + MM_DESCRIPTOR_VALID; + } + uint64_t mair = MAIR_VALUE; + uint64_t tcr = TCR_VALUE; + uint64_t ttbr0 = ((uint64_t) level_1_table) | MM_TTBR_CNP; + uint64_t sctlr = 0; + __asm__ volatile ( + // Set MAIR + "MSR MAIR_EL2, %[mair]\n\t" + // Set TTBR0 + "MSR TTBR0_EL2, %[ttbr0]\n\t" + // Set TCR + "MSR TCR_EL2, %[tcr]\n\t" + // The ISB forces these changes to be seen before the MMU is enabled. + "ISB\n\t" + // Read System Control Register configuration data + "MRS %[sctlr], SCTLR_EL2\n\t" + // Write System Control Register configuration data + "ORR %[sctlr], %[sctlr], #1\n\t" + // Set [M] bit and enable the MMU. + "MSR SCTLR_EL2, %[sctlr]\n\t" + // The ISB forces these changes to be seen by the next instruction + "ISB" + : /* No outputs. */ + : [mair] "r" (mair), + [tcr] "r" (tcr), + [ttbr0] "r" (ttbr0), + [sctlr] "r" (sctlr) + ); + while (true) {} +} diff --git a/hw/mcu/broadcom/bcm2711/mmu.h b/hw/mcu/broadcom/bcm2711/mmu.h new file mode 100644 index 000000000..9f0a7db49 --- /dev/null +++ b/hw/mcu/broadcom/bcm2711/mmu.h @@ -0,0 +1,44 @@ +#pragma once + + +// From: https://github.com/s-matyukevich/raspberry-pi-os/blob/master/docs/lesson06/rpi-os.md +/* + * Memory region attributes: + * + * n = AttrIndx[2:0] + * n MAIR + * DEVICE_nGnRnE 000 00000000 + * NORMAL_NC 001 01000100 + */ +#define MT_DEVICE_nGnRnE 0x0 +#define MT_NORMAL_NC 0x1 +#define MT_DEVICE_nGnRnE_FLAGS 0x00 +#define MT_NORMAL_NC_FLAGS 0x44 +#define MAIR_VALUE (MT_DEVICE_nGnRnE_FLAGS << (8 * MT_DEVICE_nGnRnE)) | (MT_NORMAL_NC_FLAGS << (8 * MT_NORMAL_NC)) + + +#define TCR_T0SZ (64 - 35) +#define TCR_PS (0x01 << 16) // 36-bit physical address +#define TCR_TG0_4K (0 << 14) +#define TCR_SH0_OUTER_SHAREABLE (0x2 << 12) +#define TCR_VALUE (TCR_T0SZ | TCR_PS | TCR_TG0_4K | TCR_SH0_OUTER_SHAREABLE) + +#define ENTRY_TYPE_TABLE_DESCRIPTOR 0x11 +#define ENTRY_TYPE_BLOCK_ENTRY 0x01 +#define ENTRY_TYPE_TABLE_ENTRY 0x11 +#define ENTRY_TYPE_INVALID 0x00 + +#define MM_DESCRIPTOR_VALID (0x1) + +#define MM_DESCRIPTOR_BLOCK (0x0 << 1) +#define MM_DESCRIPTOR_TABLE (0x1 << 1) + +// Block attributes +#define MM_DESCRIPTOR_EXECUTE_NEVER (0x1ull << 54) +#define MM_DESCRIPTOR_CONTIGUOUS (0x1ull << 52) + +#define MM_DESCRIPTOR_MAIR_INDEX(index) (index << 2) + +#define MM_TTBR_CNP (0x1) + +void setup_mmu_flat_map(void); -- cgit v1.3.1 From dd2a518881f975583ae0ae018c9479ab61392a7c Mon Sep 17 00:00:00 2001 From: Jerzy Kasenberg Date: Thu, 23 Sep 2021 11:51:41 +0200 Subject: da1469x_dk_pro: Fix button setup Button on board has 1k resistor to ground when pressed. When not pressed pin 6 is floating. This forces MCU pull-up for this pin for correct behavior. --- hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c b/hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c index 2b6931e4e..0441c000c 100644 --- a/hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c +++ b/hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c @@ -80,7 +80,7 @@ void board_init(void) hal_gpio_init_out(5, 0); // Button - hal_gpio_init_in(BUTTON_PIN, HAL_GPIO_PULL_NONE); + hal_gpio_init_in(BUTTON_PIN, HAL_GPIO_PULL_UP); // 1ms tick timer SysTick_Config(SystemCoreClock / 1000); -- cgit v1.3.1 From 417677aae40469594ba69b70a41d988522c5ec96 Mon Sep 17 00:00:00 2001 From: Jerzy Kasenberg Date: Thu, 23 Sep 2021 12:32:17 +0200 Subject: da14695_dk_usb: Fix button configuration Unlike da1469x_dk_pro, K1 pin (6) is connected to VCC when active. This adds required pull down and reverses active logic state. --- hw/bsp/da14695_dk_usb/da14695_dk_usb.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/bsp/da14695_dk_usb/da14695_dk_usb.c b/hw/bsp/da14695_dk_usb/da14695_dk_usb.c index bdb30e0e5..95fe70d01 100644 --- a/hw/bsp/da14695_dk_usb/da14695_dk_usb.c +++ b/hw/bsp/da14695_dk_usb/da14695_dk_usb.c @@ -68,7 +68,7 @@ void board_init(void) hal_gpio_init_out(5, 0); // Button - hal_gpio_init_in(BUTTON_PIN, HAL_GPIO_PULL_NONE); + hal_gpio_init_in(BUTTON_PIN, HAL_GPIO_PULL_DOWN); // 1ms tick timer SysTick_Config(SystemCoreClock / 1000); @@ -101,8 +101,8 @@ void board_led_write(bool state) uint32_t board_button_read(void) { - // button is active LOW - return hal_gpio_read(BUTTON_PIN) ^ 1; + // button is active HIGH + return hal_gpio_read(BUTTON_PIN); } int board_uart_read(uint8_t* buf, int len) -- cgit v1.3.1 From c4277124499430ecfc6bed9cb2789144a3872b02 Mon Sep 17 00:00:00 2001 From: Jerzy Kasenberg Date: Thu, 23 Sep 2021 13:36:28 +0200 Subject: dcd_da146xx: Handle only enabled interrupts Not much of an improvement but handle only interrupts that were enabled and are expected. --- src/portable/dialog/da146xx/dcd_da146xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/portable/dialog/da146xx/dcd_da146xx.c b/src/portable/dialog/da146xx/dcd_da146xx.c index 112cdb502..b7ef77c01 100644 --- a/src/portable/dialog/da146xx/dcd_da146xx.c +++ b/src/portable/dialog/da146xx/dcd_da146xx.c @@ -1037,7 +1037,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) void dcd_int_handler(uint8_t rhport) { - uint32_t int_status = USB->USB_MAEV_REG; + uint32_t int_status = USB->USB_MAEV_REG & USB->USB_MAMSK_REG; (void)rhport; -- cgit v1.3.1 From 428eedcd04bf6e84f15252df6aebd030942c0f01 Mon Sep 17 00:00:00 2001 From: Jerzy Kasenberg Date: Thu, 23 Sep 2021 13:40:47 +0200 Subject: dcd_da146xx: Update bus handling So far bus reset was handled (with some holes in it). Sleep and remote wakeup were not really tested and did not work. With this change: - bus reset is reworked - remote wakeup works - bus signal sleep is handled --- src/portable/dialog/da146xx/dcd_da146xx.c | 136 ++++++++++++++++++++++-------- 1 file changed, 99 insertions(+), 37 deletions(-) diff --git a/src/portable/dialog/da146xx/dcd_da146xx.c b/src/portable/dialog/da146xx/dcd_da146xx.c index b7ef77c01..3b006de91 100644 --- a/src/portable/dialog/da146xx/dcd_da146xx.c +++ b/src/portable/dialog/da146xx/dcd_da146xx.c @@ -60,10 +60,17 @@ #define EP_MAX 4 +// Node functional states #define NFSR_NODE_RESET 0 #define NFSR_NODE_RESUME 1 #define NFSR_NODE_OPERATIONAL 2 #define NFSR_NODE_SUSPEND 3 +// Those two following states are added to allow going out of sleep mode +// using frame interrupt. On remove wakeup RESUME state must be kept for +// at least 1ms. It is accomplished by using FRAME interrupt that goes +// through those two fake states before entering OPERATIONAL state. +#define NFSR_NODE_WAKING (0x10 | (NFSR_NODE_RESUME)) +#define NFSR_NODE_WAKING2 (0x20 | (NFSR_NODE_RESUME)) static TU_ATTR_ALIGNED(4) uint8_t _setup_packet[8]; @@ -218,7 +225,7 @@ static struct { bool vbus_present; bool init_called; - bool in_reset; + uint8_t nfsr; xfer_ctl_t xfer_status[EP_MAX][2]; // Endpoints that use DMA, one for each direction uint8_t dma_ep[2]; @@ -260,6 +267,15 @@ static const tusb_desc_endpoint_t ep0IN_desc = #define XFER_CTL_BASE(_ep, _dir) &_dcd.xfer_status[_ep][_dir] +static void set_nfsr(uint8_t val) +{ + _dcd.nfsr = val; + // Write only lower 2 bits to register, higher bits are used + // to count down till OPERATIONAL state can be entered when + // remote wakeup activated. + USB->USB_NFSR_REG = val & 3; +} + static void fill_tx_fifo(xfer_ctl_t * xfer) { int left_to_send; @@ -628,60 +644,81 @@ static void handle_tx_ev(void) handle_epx_tx_ev(XFER_CTL_BASE(3, TUSB_DIR_IN)); } +static uint32_t check_reset_end(uint32_t alt_ev) +{ + if (_dcd.nfsr == NFSR_NODE_RESET) + { + if (GET_BIT(alt_ev, USB_USB_ALTEV_REG_USB_RESET)) + { + // Could be still in reset, but since USB_M_RESET is disabled it can + // be also old reset state that was not cleared yet. + // If (after reading USB_ALTEV_REG register again) bit is cleared + // reset state just ended. + // Keep non-reset bits combined from two previous ALTEV read and + // one from the next line. + alt_ev = (alt_ev & ~USB_USB_ALTEV_REG_USB_RESET_Msk) | USB->USB_ALTEV_REG; + } + if (GET_BIT(alt_ev, USB_USB_ALTEV_REG_USB_RESET) == 0) + { + USB->USB_ALTMSK_REG = USB_USB_ALTMSK_REG_USB_M_RESET_Msk | + USB_USB_ALTEV_REG_USB_SD3_Msk; + set_nfsr(NFSR_NODE_OPERATIONAL); + dcd_edpt_open(0, &ep0OUT_desc); + dcd_edpt_open(0, &ep0IN_desc); + } + } + return alt_ev; +} + static void handle_bus_reset(void) { + uint32_t alt_ev; + USB->USB_NFSR_REG = 0; USB->USB_FAR_REG = 0x80; USB->USB_ALTMSK_REG = 0; USB->USB_NFSR_REG = NFSR_NODE_RESET; USB->USB_TXMSK_REG = 0; USB->USB_RXMSK_REG = 0; - (void)USB->USB_ALTEV_REG; - _dcd.in_reset = true; + set_nfsr(NFSR_NODE_RESET); dcd_event_bus_reset(0, TUSB_SPEED_FULL, true); USB->USB_DMA_CTRL_REG = 0; USB->USB_MAMSK_REG = USB_USB_MAMSK_REG_USB_M_INTR_Msk | -#if USE_SOF USB_USB_MAMSK_REG_USB_M_FRAME_Msk | -#endif USB_USB_MAMSK_REG_USB_M_WARN_Msk | USB_USB_MAMSK_REG_USB_M_ALT_Msk; - USB->USB_NFSR_REG = NFSR_NODE_OPERATIONAL; - USB->USB_ALTMSK_REG = USB_USB_ALTMSK_REG_USB_M_SD3_Msk | - USB_USB_ALTMSK_REG_USB_M_RESUME_Msk; - // There is no information about end of reset state - // USB_FRAME event will be used to enable reset detection again - REG_SET_BIT(USB_MAEV_REG, USB_FRAME); - dcd_edpt_open (0, &ep0OUT_desc); - dcd_edpt_open (0, &ep0IN_desc); + USB->USB_ALTMSK_REG = USB_USB_ALTMSK_REG_USB_M_RESUME_Msk; + alt_ev = USB->USB_ALTEV_REG; + check_reset_end(alt_ev); } static void handle_alt_ev(void) { uint32_t alt_ev = USB->USB_ALTEV_REG; - if (GET_BIT(alt_ev, USB_USB_ALTEV_REG_USB_RESET)) + alt_ev = check_reset_end(alt_ev); + if (GET_BIT(alt_ev, USB_USB_ALTEV_REG_USB_RESET) && _dcd.nfsr != NFSR_NODE_RESET) { handle_bus_reset(); } - else + else if (GET_BIT(alt_ev, USB_USB_ALTEV_REG_USB_RESUME)) { - if (GET_BIT(alt_ev, USB_USB_ALTEV_REG_USB_RESUME)) + if (USB->USB_NFSR_REG == NFSR_NODE_SUSPEND) { - USB->USB_NFSR_REG = NFSR_NODE_OPERATIONAL; - USB->USB_ALTMSK_REG &= ~USB_USB_ALTMSK_REG_USB_M_RESUME_Msk; - USB->USB_ALTMSK_REG |= USB_USB_ALTMSK_REG_USB_M_SD3_Msk; + set_nfsr(NFSR_NODE_OPERATIONAL); + USB->USB_ALTMSK_REG = USB_USB_ALTMSK_REG_USB_M_RESET_Msk | + USB_USB_ALTMSK_REG_USB_M_SD3_Msk; dcd_event_bus_signal(0, DCD_EVENT_RESUME, true); } - if (GET_BIT(alt_ev, USB_USB_ALTEV_REG_USB_SD3)) - { - USB->USB_NFSR_REG = NFSR_NODE_SUSPEND; - USB->USB_ALTMSK_REG |= USB_USB_ALTMSK_REG_USB_M_RESUME_Msk; - USB->USB_ALTMSK_REG &= ~USB_USB_ALTMSK_REG_USB_M_SD3_Msk | USB_USB_ALTMSK_REG_USB_M_SD5_Msk; - dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true); - } + } + else if (GET_BIT(alt_ev, USB_USB_ALTEV_REG_USB_SD3)) + { + set_nfsr(NFSR_NODE_SUSPEND); + USB->USB_ALTMSK_REG = USB_USB_ALTMSK_REG_USB_M_RESET_Msk | + USB_USB_ALTMSK_REG_USB_M_RESUME_Msk; + dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true); } } @@ -773,6 +810,12 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr) void dcd_remote_wakeup(uint8_t rhport) { (void)rhport; + if (_dcd.nfsr == NFSR_NODE_SUSPEND) + { + // Enter fake state that will use FRAME interrupt to wait before going operational. + set_nfsr(NFSR_NODE_WAKING); + USB->USB_MAMSK_REG |= USB_USB_MAMSK_REG_USB_M_FRAME_Msk; + } } void dcd_connect(uint8_t rhport) @@ -784,16 +827,16 @@ void dcd_connect(uint8_t rhport) USB->USB_MCTRL_REG = USB_USB_MCTRL_REG_USBEN_Msk; USB->USB_NFSR_REG = 0; USB->USB_FAR_REG = 0x80; - USB->USB_NFSR_REG = NFSR_NODE_RESET; USB->USB_TXMSK_REG = 0; USB->USB_RXMSK_REG = 0; USB->USB_MAMSK_REG = USB_USB_MAMSK_REG_USB_M_INTR_Msk | USB_USB_MAMSK_REG_USB_M_ALT_Msk | USB_USB_MAMSK_REG_USB_M_WARN_Msk; - USB->USB_ALTMSK_REG = USB_USB_ALTMSK_REG_USB_M_RESET_Msk; + USB->USB_ALTMSK_REG = USB_USB_ALTMSK_REG_USB_M_RESET_Msk | + USB_USB_ALTEV_REG_USB_SD3_Msk; - REG_SET_BIT(USB_MCTRL_REG, USB_NAT); + USB->USB_MCTRL_REG = USB_USB_MCTRL_REG_USBEN_Msk | USB_USB_MCTRL_REG_USB_NAT_Msk; // Select chosen DMA to be triggered by USB. DMA->DMA_REQ_MUX_REG = (DMA->DMA_REQ_MUX_REG & ~DA146XX_DMA_USB_MUX_MASK) | DA146XX_DMA_USB_MUX; @@ -1079,19 +1122,38 @@ void dcd_int_handler(uint8_t rhport) if (GET_BIT(int_status, USB_USB_MAEV_REG_USB_FRAME)) { - if (_dcd.in_reset) + if (_dcd.nfsr == NFSR_NODE_RESET) + { + // During reset FRAME interrupt is enabled to periodically + // check when reset state ends. + // FRAME interrupt is generated every 1ms without host sending + // actual SOF. + check_reset_end(USB_USB_ALTEV_REG_USB_RESET_Msk); + } + else if (_dcd.nfsr == NFSR_NODE_WAKING) { - // Enable reset detection - _dcd.in_reset = false; - (void)USB->USB_ALTEV_REG; + // No need to call set_nfsr, just set state + _dcd.nfsr = NFSR_NODE_WAKING2; } + else if (_dcd.nfsr == NFSR_NODE_WAKING2) + { + // No need to call set_nfsr, just set state + _dcd.nfsr = NFSR_NODE_RESUME; + } + else if (_dcd.nfsr == NFSR_NODE_RESUME) + { + set_nfsr(NFSR_NODE_OPERATIONAL); + } + else + { #if USE_SOF - dcd_event_bus_signal(0, DCD_EVENT_SOF, true); + dcd_event_bus_signal(0, DCD_EVENT_SOF, true); #else - // SOF was used to re-enable reset detection - // No need to keep it enabled - USB->USB_MAMSK_REG &= ~USB_USB_MAMSK_REG_USB_M_FRAME_Msk; + // FRAME interrupt was used to re-enable reset detection or remote + // wakeup no need to keep it enabled when USE_SOF is off. + USB->USB_MAMSK_REG &= ~USB_USB_MAMSK_REG_USB_M_FRAME_Msk; #endif + } } if (GET_BIT(int_status, USB_USB_MAEV_REG_USB_TX_EV)) -- cgit v1.3.1 From f172c5ee13fe9eb00e7560c5f2ded34290b9e4f7 Mon Sep 17 00:00:00 2001 From: Jerzy Kasenberg Date: Fri, 24 Sep 2021 09:12:52 +0200 Subject: dcd_da146xx: Remove registers pointer from xfer_ctl_t Note: this commit does not change any logic. xfer_ctl_t structure keeps all dynamic data connected with transfer. It used to have pointer to register set that was constant and was there for convenience only. Removing register pointer from structure makes cleanup easier as whole structure can be erased with memset like function. In many cases functions were using local variable regs and xfer->regs which were same, that could be confusing so this part is unified. Few macros were added for easy conversion between epnum, xfer, and regs. --- src/portable/dialog/da146xx/dcd_da146xx.c | 81 ++++++++++++++++++------------- 1 file changed, 46 insertions(+), 35 deletions(-) diff --git a/src/portable/dialog/da146xx/dcd_da146xx.c b/src/portable/dialog/da146xx/dcd_da146xx.c index 112cdb502..b98a996ee 100644 --- a/src/portable/dialog/da146xx/dcd_da146xx.c +++ b/src/portable/dialog/da146xx/dcd_da146xx.c @@ -193,8 +193,14 @@ typedef struct #define REG_CLR_BIT(reg, field) USB->reg &= ~USB_ ## reg ## _ ## field ## _Msk #define REG_SET_VAL(reg, field, val) USB->reg = (USB->reg & ~USB_ ## reg ## _ ## field ## _Msk) | (val << USB_ ## reg ## _ ## field ## _Pos) +static EPx_REGS * const ep_regs[EP_MAX] = { + EP_REGS(USB_EPC0_REG), + EP_REGS(USB_EPC1_REG), + EP_REGS(USB_EPC3_REG), + EP_REGS(USB_EPC5_REG), +}; + typedef struct { - EPx_REGS * regs; uint8_t * buffer; // Total length of current transfer uint16_t total_len; @@ -226,15 +232,15 @@ static struct { .vbus_present = false, .init_called = false, - .xfer_status = - { - { { .regs = EP_REGS(USB_EPC0_REG) }, { .regs = EP_REGS(USB_EPC0_REG) } }, - { { .regs = EP_REGS(USB_EPC1_REG) }, { .regs = EP_REGS(USB_EPC1_REG) } }, - { { .regs = EP_REGS(USB_EPC3_REG) }, { .regs = EP_REGS(USB_EPC3_REG) } }, - { { .regs = EP_REGS(USB_EPC5_REG) }, { .regs = EP_REGS(USB_EPC5_REG) } }, - } }; +// Converts xfer pointer to epnum (0,1,2,3) regardless of xfer direction +#define XFER_EPNUM(xfer) ((xfer - &_dcd.xfer_status[0][0]) >> 1) +// Converts xfer pinter to EPx_REGS pointer (returns same pointer for IN and OUT with same endpoint number) +#define XFER_REGS(xfer) ep_regs[XFER_EPNUM(xfer)] +// Converts epnum (0,1,2,3) to EPx_REGS pointer +#define EPNUM_REGS(epnum) ep_regs[epnum] + // Two endpoint 0 descriptor definition for unified dcd_edpt_open() static const tusb_desc_endpoint_t ep0OUT_desc = { @@ -264,8 +270,8 @@ static void fill_tx_fifo(xfer_ctl_t * xfer) { int left_to_send; uint8_t const *src; - EPx_REGS *regs = xfer->regs; uint8_t const epnum = tu_edpt_number(xfer->ep_addr); + EPx_REGS *regs = EPNUM_REGS(epnum); src = &xfer->buffer[xfer->transferred]; left_to_send = xfer->total_len - xfer->transferred; @@ -293,7 +299,7 @@ static void fill_tx_fifo(xfer_ctl_t * xfer) } else { - xfer->regs->txc &= ~USB_USB_TXC1_REG_USB_TFWL_Msk; + regs->txc &= ~USB_USB_TXC1_REG_USB_TFWL_Msk; USB->USB_FWMSK_REG &= ~(1 << (epnum - 1 + USB_USB_FWMSK_REG_USB_M_TXWARN31_Pos)); // Whole packet already in fifo, no need to refill it later. Mark last. regs->txc |= USB_USB_TXC1_REG_USB_LAST_Msk; @@ -334,30 +340,31 @@ static void start_rx_packet(xfer_ctl_t *xfer) uint8_t const epnum = tu_edpt_number(xfer->ep_addr); uint16_t remaining = xfer->total_len - xfer->transferred; uint16_t size = tu_min16(remaining, xfer->max_packet_size); + EPx_REGS *regs = XFER_REGS(xfer); xfer->last_packet_size = 0; if (xfer->max_packet_size > FIFO_SIZE && remaining > FIFO_SIZE) { if (try_allocate_dma(epnum, TUSB_DIR_OUT)) { - start_rx_dma(&xfer->regs->rxd, xfer->buffer + xfer->transferred, size); + start_rx_dma(®s->rxd, xfer->buffer + xfer->transferred, size); } else { // Other endpoint is using DMA in that direction, fall back to interrupts. // For endpoint size greater then FIFO size enable FIFO level warning interrupt // when FIFO has less then 17 bytes free. - xfer->regs->rxc |= USB_USB_RXC1_REG_USB_RFWL_Msk; + regs->rxc |= USB_USB_RXC1_REG_USB_RFWL_Msk; USB->USB_FWMSK_REG |= 1 << (epnum - 1 + USB_USB_FWMSK_REG_USB_M_RXWARN31_Pos); } } else if (epnum != 0) { // If max_packet_size would fit in FIFO no need for FIFO level warning interrupt. - xfer->regs->rxc &= ~USB_USB_RXC1_REG_USB_RFWL_Msk; + regs->rxc &= ~USB_USB_RXC1_REG_USB_RFWL_Msk; USB->USB_FWMSK_REG &= ~(1 << (epnum - 1 + USB_USB_FWMSK_REG_USB_M_RXWARN31_Pos)); } - xfer->regs->rxc |= USB_USB_RXC1_REG_USB_RX_EN_Msk; + regs->rxc |= USB_USB_RXC1_REG_USB_RX_EN_Msk; } static void start_tx_dma(void *src, volatile void *dst, uint16_t size) @@ -376,13 +383,13 @@ static void start_tx_packet(xfer_ctl_t *xfer) uint8_t const epnum = tu_edpt_number(xfer->ep_addr); uint16_t remaining = xfer->total_len - xfer->transferred; uint16_t size = tu_min16(remaining, xfer->max_packet_size); - EPx_REGS *regs = xfer->regs; + EPx_REGS *regs = EPNUM_REGS(epnum); xfer->last_packet_size = 0; regs->txc = USB_USB_TXC1_REG_USB_FLUSH_Msk; regs->txc = USB_USB_TXC1_REG_USB_IGN_ISOMSK_Msk; - if (xfer->data1) xfer->regs->txc |= USB_USB_TXC1_REG_USB_TOGGLE_TX_Msk; + if (xfer->data1) regs->txc |= USB_USB_TXC1_REG_USB_TOGGLE_TX_Msk; if (xfer->max_packet_size > FIFO_SIZE && remaining > FIFO_SIZE && try_allocate_dma(epnum, TUSB_DIR_IN)) { @@ -399,7 +406,7 @@ static void start_tx_packet(xfer_ctl_t *xfer) static void read_rx_fifo(xfer_ctl_t *xfer, uint16_t bytes_in_fifo) { - EPx_REGS *regs = xfer->regs; + EPx_REGS *regs = XFER_REGS(xfer); uint16_t remaining = xfer->total_len - xfer->transferred - xfer->last_packet_size; uint16_t receive_this_time = bytes_in_fifo; @@ -469,7 +476,7 @@ static void handle_ep0_tx(void) { uint32_t txs0; xfer_ctl_t *xfer = XFER_CTL_BASE(0, TUSB_DIR_IN); - EPx_REGS *regs = xfer->regs; + EPx_REGS *regs = XFER_REGS(xfer); txs0 = regs->USB_TXS0_REG; @@ -503,7 +510,7 @@ static void handle_epx_rx_ev(uint8_t ep) int fifo_bytes; xfer_ctl_t *xfer = XFER_CTL_BASE(ep, TUSB_DIR_OUT); - EPx_REGS *regs = xfer->regs; + EPx_REGS *regs = EPNUM_REGS(ep); do { @@ -582,7 +589,7 @@ static void handle_epx_tx_ev(xfer_ctl_t *xfer) { uint8_t const epnum = tu_edpt_number(xfer->ep_addr); uint32_t txs; - EPx_REGS *regs = xfer->regs; + EPx_REGS *regs = EPNUM_REGS(epnum); txs = regs->txs; @@ -843,6 +850,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress); uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress); xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir); + EPx_REGS *regs = EPNUM_REGS(epnum); uint8_t iso_mask = 0; TU_ASSERT(epnum < EP_MAX); @@ -867,13 +875,13 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) { if (dir == TUSB_DIR_OUT) { - xfer->regs->epc_out = epnum | USB_USB_EPC1_REG_USB_EP_EN_Msk | iso_mask; + regs->epc_out = epnum | USB_USB_EPC1_REG_USB_EP_EN_Msk | iso_mask; USB->USB_RXMSK_REG |= 0x101 << (epnum - 1); REG_SET_BIT(USB_MAMSK_REG, USB_M_RX_EV); } else { - xfer->regs->epc_in = epnum | USB_USB_EPC1_REG_USB_EP_EN_Msk | iso_mask; + regs->epc_in = epnum | USB_USB_EPC1_REG_USB_EP_EN_Msk | iso_mask; USB->USB_TXMSK_REG |= 0x101 << (epnum - 1); REG_SET_BIT(USB_MAMSK_REG, USB_M_TX_EV); } @@ -892,6 +900,7 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) { uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); + EPx_REGS *regs = EPNUM_REGS(epnum); xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir); (void)rhport; @@ -907,8 +916,8 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) { if (dir == TUSB_DIR_OUT) { - xfer->regs->rxc = USB_USB_RXC1_REG_USB_FLUSH_Msk; - xfer->regs->epc_out = 0; + regs->rxc = USB_USB_RXC1_REG_USB_FLUSH_Msk; + regs->epc_out = 0; USB->USB_RXMSK_REG &= ~(0x101 << (epnum - 1)); // Release DMA if needed if (_dcd.dma_ep[TUSB_DIR_OUT] == epnum) @@ -919,8 +928,8 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) } else { - xfer->regs->txc = USB_USB_TXC1_REG_USB_FLUSH_Msk; - xfer->regs->epc_in = 0; + regs->txc = USB_USB_TXC1_REG_USB_FLUSH_Msk; + regs->epc_in = 0; USB->USB_TXMSK_REG &= ~(0x101 << (epnum - 1)); // Release DMA if needed if (_dcd.dma_ep[TUSB_DIR_IN] == epnum) @@ -965,6 +974,7 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) (void)rhport; xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir); + EPx_REGS *regs = EPNUM_REGS(epnum); xfer->stall = 1; if (epnum == 0) @@ -973,11 +983,11 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) REG_SET_BIT(USB_EPC0_REG, USB_STALL); if (dir == TUSB_DIR_OUT) { - xfer->regs->USB_RXC0_REG = USB_USB_RXC0_REG_USB_RX_EN_Msk; + regs->USB_RXC0_REG = USB_USB_RXC0_REG_USB_RX_EN_Msk; } else { - if (xfer->regs->USB_RXC0_REG & USB_USB_RXC0_REG_USB_RX_EN_Msk) + if (regs->USB_RXC0_REG & USB_USB_RXC0_REG_USB_RX_EN_Msk) { // If RX is also enabled TX will not be stalled since RX has // higher priority. Enable NAK interrupt to handle stall. @@ -985,7 +995,7 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) } else { - xfer->regs->USB_TXC0_REG |= USB_USB_TXC0_REG_USB_TX_EN_Msk; + regs->USB_TXC0_REG |= USB_USB_TXC0_REG_USB_TX_EN_Msk; } } } @@ -993,13 +1003,13 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { if (dir == TUSB_DIR_OUT) { - xfer->regs->epc_out |= USB_USB_EPC1_REG_USB_STALL_Msk; - xfer->regs->rxc |= USB_USB_RXC1_REG_USB_RX_EN_Msk; + regs->epc_out |= USB_USB_EPC1_REG_USB_STALL_Msk; + regs->rxc |= USB_USB_RXC1_REG_USB_RX_EN_Msk; } else { - xfer->regs->epc_in |= USB_USB_EPC1_REG_USB_STALL_Msk; - xfer->regs->txc |= USB_USB_TXC1_REG_USB_TX_EN_Msk | USB_USB_TXC1_REG_USB_LAST_Msk; + regs->epc_in |= USB_USB_EPC1_REG_USB_STALL_Msk; + regs->txc |= USB_USB_TXC1_REG_USB_TX_EN_Msk | USB_USB_TXC1_REG_USB_LAST_Msk; } } } @@ -1012,6 +1022,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) (void)rhport; xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir); + EPx_REGS *regs = EPNUM_REGS(epnum); // Clear stall is called in response to Clear Feature ENDPOINT_HALT, reset toggle xfer->data1 = 0; @@ -1019,11 +1030,11 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) if (dir == TUSB_DIR_OUT) { - xfer->regs->epc_out &= ~USB_USB_EPC1_REG_USB_STALL_Msk; + regs->epc_out &= ~USB_USB_EPC1_REG_USB_STALL_Msk; } else { - xfer->regs->epc_in &= ~USB_USB_EPC1_REG_USB_STALL_Msk; + regs->epc_in &= ~USB_USB_EPC1_REG_USB_STALL_Msk; } if (epnum == 0) { -- cgit v1.3.1 From 1503955860ba1b0797a07dfab15a9d424f105839 Mon Sep 17 00:00:00 2001 From: Jerzy Kasenberg Date: Fri, 24 Sep 2021 09:15:18 +0200 Subject: dcd_da146xx: Clear transfer data on dcd_edpt_close Closing endpoint clears data in affected xfer_ctl_t --- src/portable/dialog/da146xx/dcd_da146xx.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/portable/dialog/da146xx/dcd_da146xx.c b/src/portable/dialog/da146xx/dcd_da146xx.c index b98a996ee..6eaba7098 100644 --- a/src/portable/dialog/da146xx/dcd_da146xx.c +++ b/src/portable/dialog/da146xx/dcd_da146xx.c @@ -939,6 +939,7 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) } } } + tu_memclr(xfer, sizeof(*xfer)); } bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) -- cgit v1.3.1 From fbac58e3e40a3741db96c258ac88ec5d19ee0251 Mon Sep 17 00:00:00 2001 From: Jerzy Kasenberg Date: Mon, 20 Sep 2021 15:32:58 +0200 Subject: dcd_da146xx: Implement dcd_edpt_close_all() Unconditionally disables all endpoints except EP0. --- src/portable/dialog/da146xx/dcd_da146xx.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/portable/dialog/da146xx/dcd_da146xx.c b/src/portable/dialog/da146xx/dcd_da146xx.c index 112cdb502..8c49d9a51 100644 --- a/src/portable/dialog/da146xx/dcd_da146xx.c +++ b/src/portable/dialog/da146xx/dcd_da146xx.c @@ -885,7 +885,12 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) void dcd_edpt_close_all (uint8_t rhport) { (void) rhport; - // TODO implement dcd_edpt_close_all() + + for (int epnum = 1; epnum < EP_MAX; ++epnum) + { + dcd_edpt_close(0, epnum | TUSB_DIR_OUT); + dcd_edpt_close(0, epnum | TUSB_DIR_IN); + } } void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) -- cgit v1.3.1 From c62c1433e7d35ee18d97a7c76a4de91aa66a9486 Mon Sep 17 00:00:00 2001 From: Jerzy Kasenberg Date: Thu, 23 Sep 2021 14:03:22 +0200 Subject: usbd: Workaround for non standard device descriptor request Windows and Linux host during enumeration requests device descriptor with request size set to 64 bytes when device was in default state (no address). Those systems do not want 64 bytes though since usb descriptors is only 18 bytes long so they silently expect that only one packet will be received possibly 18 bytes for EPS > 16 or 8 or 16 bytes for smaller EP0. For devices with CFG_TUD_ENDPOINT0_SIZE size 8 or 16 there was workaround that reduced request size to CFG_TUD_ENDPOINT0_SIZE and that was enough to satisfy Windows and Linux hosts. However USBCV testing application also requests device descriptor but with size set to 18 bytes. Workaround for Window/Linux prevented USBVC to tests devices with 8 bytes EP0 size since it send only 8 bytes while application did wanted 18 bytes. Solution that satisfies both cases it to check if in default state device descriptor request wants more bytes than descriptor size (18). If so host is expecting to receive less bytes then requested and workaround would be applied since Linux/Windows only try to read one packet. If 18 bytes was requested as is the case for USBCV, core returns descriptor in 2 or 3 packets as application expects. --- src/device/usbd.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/device/usbd.c b/src/device/usbd.c index 3043fc7bc..cf3ecea42 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -971,9 +971,11 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const uint16_t len = sizeof(tusb_desc_device_t); - // Only send up to EP0 Packet Size if not addressed + // Only send up to EP0 Packet Size if not addressed and host requested more data + // that device descriptor has. // This only happens with the very first get device descriptor and EP0 size = 8 or 16. - if ((CFG_TUD_ENDPOINT0_SIZE < sizeof(tusb_desc_device_t)) && !_usbd_dev.addressed) + if ((CFG_TUD_ENDPOINT0_SIZE < sizeof(tusb_desc_device_t)) && !_usbd_dev.addressed && + ((tusb_control_request_t*) p_request)->wLength > sizeof(tusb_desc_device_t)) { len = CFG_TUD_ENDPOINT0_SIZE; -- cgit v1.3.1 From 0a6ca65e3f8a113c182c7df0a05889b123ba67a2 Mon Sep 17 00:00:00 2001 From: Scott Shawcroft Date: Fri, 24 Sep 2021 16:14:01 -0700 Subject: MMU works --- cortex-a.py | 157 ++++++++++++++++++++++++++ hw/mcu/broadcom/bcm2711/io.c | 2 + hw/mcu/broadcom/bcm2711/mmu.c | 12 +- hw/mcu/broadcom/bcm2711/mmu.h | 5 +- src/portable/broadcom/synopsys/dcd_synopsys.c | 8 +- 5 files changed, 177 insertions(+), 7 deletions(-) create mode 100644 cortex-a.py diff --git a/cortex-a.py b/cortex-a.py new file mode 100644 index 000000000..9de16bae9 --- /dev/null +++ b/cortex-a.py @@ -0,0 +1,157 @@ +class Armv8AException(gdb.Command): + def __init__ (self): + super (Armv8AException, self).__init__ ("armv8a-exception", gdb.COMMAND_USER) + + def print_data_abort(self, frame, iss): + isv = (iss >> 23) & 0x1 + sas = (iss >> 21) & 0x3 + sse = (iss >> 20) & 0x1 + srt = (iss >> 15) & 0x1f + sf = (iss >> 14) & 0x1 + ar = (iss >> 13) & 0x1 + vncr = (iss >> 12) & 0x1 + _set = (iss >> 10) & 0x3 + fnv = (iss >> 9) & 0x1 + ea = (iss >> 8) & 0x1 + cm = (iss >> 7) & 0x1 + s1ptw = (iss >> 6) & 0x1 + wnr = (iss >> 5) & 0x1 + dfsc = iss & 0x1f + if isv: + # print("isv valid", sas, sse, srt, sf, ar) + access_sizes = ("Byte", "Halfword", "Word", "Doubleword") + print("Access size:", access_sizes[sas]) + print("Sign extended:", "Yes" if sse else "No") + print("Register:", hex(srt), "64-bit" if sf else "32-bit") + print("Acquire/Release:", "Yes" if ar else "No") + if dfsc == 0b010000: + print("Not on translation table walk") + if not fnv: + value = int(frame.read_register("FAR_EL2")) + print("FAR", hex(value)) + elif dfsc == 0b000101: + print("translation fault level 1") + elif dfsc == 0b010001: + print("tag check fault") + elif dfsc == 0b100001: + print("alignment fault") + else: + print(bin(dfsc)) + print(vncr, _set, fnv, ea, cm, s1ptw, wnr, dfsc) + + def print_instruction_abort(self, frame, iss): + _set = (iss >> 10) & 0x3 + fnv = (iss >> 9) & 0x1 + ea = (iss >> 8) & 0x1 + s1ptw = (iss >> 6) & 0x1 + ifsc = iss & 0x1f + if ifsc == 0b010000: + print("Not on translation table walk") + if not fnv: + value = int(frame.read_register("FAR_EL2")) + print("FAR", hex(value)) + elif ifsc == 0b00101: + print("translation fault level 1") + elif ifsc == 0b01001: + print("access flag fault level 1") + # elif dfsc == 0b100001: + # print("alignment fault") + else: + print(bin(ifsc)) + + def invoke (self, arg, from_tty): + frame = gdb.selected_frame() + value = int(frame.read_register("ESR_EL2")) + if value == 0: + return None + iss2 = (value >> 32) & 0x1ff + ec = (value >> 26) & 0x3ff + il = (value >> 25) & 0x1 + iss = value & 0xffffff + if ec == 0b000000: + print("Unknown fault") + elif ec == 0b000001: + print("Trapped WF*") + elif ec == 0b000011: + print("Trapped MCR or MRC") + elif ec == 0b000100: + print("Trapped MCRR or MRRC") + elif ec == 0b000101: + print("Trapped MCR or MRC") + elif ec == 0b000110: + print("Trapped LDC or STC") + elif ec == 0b000111: + print("Trapped SIMD") + elif ec == 0b001000: + print("Trapped VMRS") + elif ec == 0b001001: + print("Trapped pointer authentication") + elif ec == 0b001010: + print("Trapped LD64B or ST64B*") + elif ec == 0b001100: + print("Trapped MRRC") + elif ec == 0b001101: + print("Branch target exception") + elif ec == 0b001110: + print("Illegal execution state") + elif ec == 0b010001: + print("SVC instruction") + elif ec == 0b010010: + print("HVC instruction") + elif ec == 0b010011: + print("SMC instruction") + elif ec == 0b010101: + print("SVC instruction") + elif ec == 0b010110: + print("HVC instruction") + elif ec == 0b010111: + print("SMC instruction") + elif ec == 0b011000: + print("Trapped MRS, MRS or system instruction") + elif ec == 0b011001: + print("Trapped SVE") + elif ec == 0b011010: + print("Trapped ERET") + elif ec == 0b011100: + print("Failed pointer authentication") + elif ec == 0b100000: + print("Instruction abort from lower level") + elif ec == 0b100001: + print("Instruction abort from same level") + self.print_instruction_abort(frame, iss) + elif ec == 0b100010: + print("PC alignment failure") + elif ec == 0b100100: + print("Data abort from lower level") + elif ec == 0b100101: + print("Data abort from same level") + self.print_data_abort(frame, iss) + elif ec == 0b100110: + print("SP alignment fault") + elif ec == 0b101000: + print("32-bit floating point exception") + elif ec == 0b101100: + print("64-bit floating point exception") + elif ec == 0b101111: + print("SError interrupt") + elif ec == 0b110000: + print("Breakpoint from lower level") + elif ec == 0b110001: + print("Breakpoint from same level") + elif ec == 0b110010: + print("Software step from lower level") + elif ec == 0b110011: + print("Software step from same level") + elif ec == 0b110100: + print ("Watch point from same level") + elif ec == 0b110101: + print("Watch point from lower level") + elif ec == 0b111000: + print("Breakpoint in aarch32 mode") + elif ec == 0b111010: + print("Vector catch in aarch32") + elif ec == 0b111100: + print("Brk instruction in aarch64") + print(hex(int(value)), iss2, bin(ec), il, iss) + +Armv8AException() diff --git a/hw/mcu/broadcom/bcm2711/io.c b/hw/mcu/broadcom/bcm2711/io.c index 213d6f2fb..8ccfdc692 100644 --- a/hw/mcu/broadcom/bcm2711/io.c +++ b/hw/mcu/broadcom/bcm2711/io.c @@ -3,6 +3,8 @@ // GPIO +// Pi 4 base address: 0xFE000000 +// Pi 3 base address: 0x3F000000 enum { PERIPHERAL_BASE = 0xFE000000, GPFSEL0 = PERIPHERAL_BASE + 0x200000, diff --git a/hw/mcu/broadcom/bcm2711/mmu.c b/hw/mcu/broadcom/bcm2711/mmu.c index 3c20436e6..e5ae236bd 100644 --- a/hw/mcu/broadcom/bcm2711/mmu.c +++ b/hw/mcu/broadcom/bcm2711/mmu.c @@ -5,7 +5,7 @@ #include "mmu.h" // Each entry is a gig. -volatile uint64_t level_1_table[32] __attribute__((aligned(4096))); +volatile uint64_t level_1_table[512] __attribute__((aligned(4096))); // Third gig has peripherals uint64_t level_2_0x0_c000_0000_to_0x1_0000_0000[512] __attribute__((aligned(4096))); @@ -14,9 +14,10 @@ void setup_mmu_flat_map(void) { // Set the first gig to regular access. level_1_table[0] = 0x0000000000000000 | MM_DESCRIPTOR_MAIR_INDEX(MT_NORMAL_NC) | + MM_DESCRIPTOR_ACCESS_FLAG | MM_DESCRIPTOR_BLOCK | MM_DESCRIPTOR_VALID; - level_1_table[2] = ((uint64_t) level_2_0x0_c000_0000_to_0x1_0000_0000) | + level_1_table[3] = ((uint64_t) level_2_0x0_c000_0000_to_0x1_0000_0000) | MM_DESCRIPTOR_TABLE | MM_DESCRIPTOR_VALID; // Set peripherals to register access. @@ -24,6 +25,7 @@ void setup_mmu_flat_map(void) { level_2_0x0_c000_0000_to_0x1_0000_0000[i] = (0x00000000c0000000 + (i << 21)) | MM_DESCRIPTOR_EXECUTE_NEVER | MM_DESCRIPTOR_MAIR_INDEX(MT_DEVICE_nGnRnE) | + MM_DESCRIPTOR_ACCESS_FLAG | MM_DESCRIPTOR_BLOCK | MM_DESCRIPTOR_VALID; } @@ -47,12 +49,14 @@ void setup_mmu_flat_map(void) { // Set [M] bit and enable the MMU. "MSR SCTLR_EL2, %[sctlr]\n\t" // The ISB forces these changes to be seen by the next instruction - "ISB" + "ISB\n\t" + // "AT S1EL2R %[ttbr0]" : /* No outputs. */ : [mair] "r" (mair), [tcr] "r" (tcr), [ttbr0] "r" (ttbr0), [sctlr] "r" (sctlr) ); - while (true) {} + //__asm__ ("brk #123"); + //while (true) {} } diff --git a/hw/mcu/broadcom/bcm2711/mmu.h b/hw/mcu/broadcom/bcm2711/mmu.h index 9f0a7db49..1fe081f34 100644 --- a/hw/mcu/broadcom/bcm2711/mmu.h +++ b/hw/mcu/broadcom/bcm2711/mmu.h @@ -13,11 +13,11 @@ #define MT_DEVICE_nGnRnE 0x0 #define MT_NORMAL_NC 0x1 #define MT_DEVICE_nGnRnE_FLAGS 0x00 -#define MT_NORMAL_NC_FLAGS 0x44 +#define MT_NORMAL_NC_FLAGS 0xff #define MAIR_VALUE (MT_DEVICE_nGnRnE_FLAGS << (8 * MT_DEVICE_nGnRnE)) | (MT_NORMAL_NC_FLAGS << (8 * MT_NORMAL_NC)) -#define TCR_T0SZ (64 - 35) +#define TCR_T0SZ (64 - 36) #define TCR_PS (0x01 << 16) // 36-bit physical address #define TCR_TG0_4K (0 << 14) #define TCR_SH0_OUTER_SHAREABLE (0x2 << 12) @@ -36,6 +36,7 @@ // Block attributes #define MM_DESCRIPTOR_EXECUTE_NEVER (0x1ull << 54) #define MM_DESCRIPTOR_CONTIGUOUS (0x1ull << 52) +#define MM_DESCRIPTOR_ACCESS_FLAG (0x1ull << 10) #define MM_DESCRIPTOR_MAIR_INDEX(index) (index << 2) diff --git a/src/portable/broadcom/synopsys/dcd_synopsys.c b/src/portable/broadcom/synopsys/dcd_synopsys.c index 5967565a5..aecae503c 100644 --- a/src/portable/broadcom/synopsys/dcd_synopsys.c +++ b/src/portable/broadcom/synopsys/dcd_synopsys.c @@ -114,7 +114,7 @@ // MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ -#define RHPORT_REGS_BASE 0x7e980000 +#define RHPORT_REGS_BASE 0xfe980000 #define GLOBAL_BASE(_port) ((USB_OTG_GlobalTypeDef*) RHPORT_REGS_BASE) #define DEVICE_BASE(_port) (USB_OTG_DeviceTypeDef *) (RHPORT_REGS_BASE + USB_OTG_DEVICE_BASE) @@ -438,6 +438,7 @@ void dcd_init (uint8_t rhport) { // Programming model begins in the last section of the chapter on the USB // peripheral in each Reference Manual. + TU_LOG(2, " dcd_init"); USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport); @@ -477,9 +478,14 @@ void dcd_init (uint8_t rhport) // Reset core after selecting PHY // Wait AHB IDLE, reset then wait until it is cleared while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U) {} + + TU_LOG(2, " resetting"); usb_otg->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; + TU_LOG(2, " waiting"); while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST) {} + TU_LOG(2, " reset done"); + // Restart PHY clock *((volatile uint32_t *)(RHPORT_REGS_BASE + USB_OTG_PCGCCTL_BASE)) = 0; -- cgit v1.3.1 From 73872a5df04a8939d5f71509788c659e38efcecd Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 25 Sep 2021 16:16:55 +0700 Subject: add CFG_TUSB_OS_INC_PATH for os include path useful for freertos/ prefix with esp IDF --- examples/device/cdc_msc_freertos/Makefile | 8 +- .../device/cdc_msc_freertos/src/CMakeLists.txt | 2 - .../device/cdc_msc_freertos/src/FreeRTOSConfig.h | 182 -------------------- .../src/FreeRTOSConfig/FreeRTOSConfig.h | 186 +++++++++++++++++++++ examples/device/cdc_msc_freertos/src/main.c | 16 +- examples/device/cdc_msc_freertos/src/tusb_config.h | 5 + examples/device/hid_boot_interface/Makefile | 2 +- examples/device/hid_composite_freertos/Makefile | 7 +- .../hid_composite_freertos/src/CMakeLists.txt | 2 - .../hid_composite_freertos/src/FreeRTOSConfig.h | 182 -------------------- .../src/FreeRTOSConfig/FreeRTOSConfig.h | 186 +++++++++++++++++++++ examples/device/hid_composite_freertos/src/main.c | 17 +- .../hid_composite_freertos/src/tusb_config.h | 6 + hw/bsp/esp32s2/boards/CMakeLists.txt | 2 - src/common/tusb_compiler.h | 3 + src/osal/osal_freertos.h | 8 +- src/tusb_option.h | 6 + 17 files changed, 428 insertions(+), 392 deletions(-) delete mode 100644 examples/device/cdc_msc_freertos/src/FreeRTOSConfig.h create mode 100644 examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h delete mode 100644 examples/device/hid_composite_freertos/src/FreeRTOSConfig.h create mode 100644 examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h diff --git a/examples/device/cdc_msc_freertos/Makefile b/examples/device/cdc_msc_freertos/Makefile index 86bacd2d4..677dcac9c 100644 --- a/examples/device/cdc_msc_freertos/Makefile +++ b/examples/device/cdc_msc_freertos/Makefile @@ -7,12 +7,18 @@ FREERTOS_SRC = lib/FreeRTOS-Kernel INC += \ src \ + src/FreeRTOSConfig \ $(TOP)/hw \ $(TOP)/$(FREERTOS_SRC)/include \ $(TOP)/$(FREERTOS_SRC)/portable/GCC/$(FREERTOS_PORT) # Example source -EXAMPLE_SOURCE += $(wildcard src/*.c) +EXAMPLE_SOURCE = \ + src/freertos_hook.c \ + src/main.c \ + src/msc_disk.c \ + src/usb_descriptors.c + SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE)) # FreeRTOS source, all files in port folder diff --git a/examples/device/cdc_msc_freertos/src/CMakeLists.txt b/examples/device/cdc_msc_freertos/src/CMakeLists.txt index 6b188fd30..c0a665fa0 100644 --- a/examples/device/cdc_msc_freertos/src/CMakeLists.txt +++ b/examples/device/cdc_msc_freertos/src/CMakeLists.txt @@ -8,9 +8,7 @@ if(EXISTS ${board_cmake}) include(${board_cmake}) endif() -idf_component_get_property( FREERTOS_ORIG_INCLUDE_PATH freertos ORIG_INCLUDE_PATH) target_include_directories(${COMPONENT_TARGET} PUBLIC - "${FREERTOS_ORIG_INCLUDE_PATH}" "${TOP}/hw" "${TOP}/src" ) diff --git a/examples/device/cdc_msc_freertos/src/FreeRTOSConfig.h b/examples/device/cdc_msc_freertos/src/FreeRTOSConfig.h deleted file mode 100644 index 568b27a18..000000000 --- a/examples/device/cdc_msc_freertos/src/FreeRTOSConfig.h +++ /dev/null @@ -1,182 +0,0 @@ -/* - * FreeRTOS Kernel V10.0.0 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. If you wish to use our Amazon - * FreeRTOS name, please do so in a fair use way that does not cause confusion. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - * - * See http://www.freertos.org/a00110.html. - *----------------------------------------------------------*/ - -// Include MCU header -#include "bsp/board_mcu.h" - -extern uint32_t SystemCoreClock; - -/* Cortex M23/M33 port configuration. */ -#define configENABLE_MPU 0 -#define configENABLE_FPU 1 -#define configENABLE_TRUSTZONE 0 -#define configMINIMAL_SECURE_STACK_SIZE ( 1024 ) - -#define configUSE_PREEMPTION 1 -#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 -#define configCPU_CLOCK_HZ SystemCoreClock -#define configTICK_RATE_HZ ( 1000 ) -#define configMAX_PRIORITIES ( 5 ) -#define configMINIMAL_STACK_SIZE ( 128 ) -#define configTOTAL_HEAP_SIZE ( 0*1024 ) // dynamic is not used -#define configMAX_TASK_NAME_LEN 16 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 1 -#define configUSE_MUTEXES 1 -#define configUSE_RECURSIVE_MUTEXES 1 -#define configUSE_COUNTING_SEMAPHORES 1 -#define configQUEUE_REGISTRY_SIZE 2 -#define configUSE_QUEUE_SETS 0 -#define configUSE_TIME_SLICING 0 -#define configUSE_NEWLIB_REENTRANT 0 -#define configENABLE_BACKWARD_COMPATIBILITY 1 -#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 - -#define configSUPPORT_STATIC_ALLOCATION 1 -#define configSUPPORT_DYNAMIC_ALLOCATION 0 - -/* Hook function related definitions. */ -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 -#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning -#define configCHECK_FOR_STACK_OVERFLOW 2 - -/* Run time and task stats gathering related definitions. */ -#define configGENERATE_RUN_TIME_STATS 0 -#define configUSE_TRACE_FACILITY 1 // legacy trace -#define configUSE_STATS_FORMATTING_FUNCTIONS 0 - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES 2 - -/* Software timer related definitions. */ -#define configUSE_TIMERS 1 -#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) -#define configTIMER_QUEUE_LENGTH 32 -#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE - -/* Optional functions - most linkers will remove unused functions anyway. */ -#define INCLUDE_vTaskPrioritySet 0 -#define INCLUDE_uxTaskPriorityGet 0 -#define INCLUDE_vTaskDelete 0 -#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY -#define INCLUDE_xResumeFromISR 0 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 -#define INCLUDE_xTaskGetSchedulerState 0 -#define INCLUDE_xTaskGetCurrentTaskHandle 0 -#define INCLUDE_uxTaskGetStackHighWaterMark 0 -#define INCLUDE_xTaskGetIdleTaskHandle 0 -#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 -#define INCLUDE_pcTaskGetTaskName 0 -#define INCLUDE_eTaskGetState 0 -#define INCLUDE_xEventGroupSetBitFromISR 0 -#define INCLUDE_xTimerPendFunctionCall 0 - -/* Define to trap errors during development. */ -// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7 -#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) - #define configASSERT(_exp) \ - do {\ - if ( !(_exp) ) { \ - volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \ - if ( (*ARM_CM_DHCSR) & 1UL ) { /* Only halt mcu if debugger is attached */ \ - taskDISABLE_INTERRUPTS(); \ - __asm("BKPT #0\n"); \ - }\ - }\ - } while(0) -#else - #define configASSERT( x ) -#endif - -#ifdef __RX__ -/* Renesas RX series */ -#define vSoftwareInterruptISR INT_Excep_ICU_SWINT -#define vTickISR INT_Excep_CMT0_CMI0 -#define configPERIPHERAL_CLOCK_HZ (configCPU_CLOCK_HZ/2) -#define configKERNEL_INTERRUPT_PRIORITY 1 -#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 - -#else - -/* FreeRTOS hooks to NVIC vectors */ -#define xPortPendSVHandler PendSV_Handler -#define xPortSysTickHandler SysTick_Handler -#define vPortSVCHandler SVC_Handler - -//--------------------------------------------------------------------+ -// Interrupt nesting behavior configuration. -//--------------------------------------------------------------------+ -#if defined(__NVIC_PRIO_BITS) - // For Cortex-M specific: __NVIC_PRIO_BITS is defined in core_cmx.h - #define configPRIO_BITS __NVIC_PRIO_BITS -#elif defined(__ECLIC_INTCTLBITS) - // RISC-V Bumblebee core from nuclei - #define configPRIO_BITS __ECLIC_INTCTLBITS -#else - #error "FreeRTOS configPRIO_BITS to be defined" -#endif - -/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ -#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<DHCSR */ \ + if ( (*ARM_CM_DHCSR) & 1UL ) { /* Only halt mcu if debugger is attached */ \ + taskDISABLE_INTERRUPTS(); \ + __asm("BKPT #0\n"); \ + }\ + }\ + } while(0) +#else + #define configASSERT( x ) +#endif + +#ifdef __RX__ +/* Renesas RX series */ +#define vSoftwareInterruptISR INT_Excep_ICU_SWINT +#define vTickISR INT_Excep_CMT0_CMI0 +#define configPERIPHERAL_CLOCK_HZ (configCPU_CLOCK_HZ/2) +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + +#else + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behavior configuration. +//--------------------------------------------------------------------+ +#if defined(__NVIC_PRIO_BITS) + // For Cortex-M specific: __NVIC_PRIO_BITS is defined in core_cmx.h + #define configPRIO_BITS __NVIC_PRIO_BITS +#elif defined(__ECLIC_INTCTLBITS) + // RISC-V Bumblebee core from nuclei + #define configPRIO_BITS __ECLIC_INTCTLBITS +#else + #error "FreeRTOS configPRIO_BITS to be defined" +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1< #include -#include "FreeRTOS.h" -#include "task.h" -#include "timers.h" -#include "queue.h" -#include "semphr.h" - #include "bsp/board.h" #include "tusb.h" +// FreeRTOS headers, MCUs such as esp32sx requires "freertos/" prefix in include path. +// CFG_TUSB_OS_INC_PATH should be defined accordingly. +#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,FreeRTOS.h) +#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,semphr.h) +#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,queue.h) +#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,task.h) +#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,timers.h) + //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF PROTYPES //--------------------------------------------------------------------+ @@ -95,7 +97,7 @@ int main(void) (void) xTaskCreateStatic( cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, cdc_stack, &cdc_taskdef); // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3 -#if CFG_TUSB_MCU != OPT_MCU_ESP32S2 && CFG_TUSB_MCU != OPT_MCU_ESP32S3 +#if !( TU_CHECK_MCU(ESP32S2) || TU_CHECK_MCU(ESP32S3) ) vTaskStartScheduler(); #endif diff --git a/examples/device/cdc_msc_freertos/src/tusb_config.h b/examples/device/cdc_msc_freertos/src/tusb_config.h index ff5438349..d4bbdee48 100644 --- a/examples/device/cdc_msc_freertos/src/tusb_config.h +++ b/examples/device/cdc_msc_freertos/src/tusb_config.h @@ -67,6 +67,11 @@ // This examples use FreeRTOS #define CFG_TUSB_OS OPT_OS_FREERTOS +// Espressif IDF requires "freertos/" prefix in include path +#if TU_CHECK_MCU(ESP32S2) || TU_CHECK_MCU(ESP32S3) + #define CFG_TUSB_OS_INC_PATH freertos/ +#endif + // can be defined by compiler in DEBUG build #ifndef CFG_TUSB_DEBUG #define CFG_TUSB_DEBUG 0 diff --git a/examples/device/hid_boot_interface/Makefile b/examples/device/hid_boot_interface/Makefile index 138c27846..c6a9c5b21 100644 --- a/examples/device/hid_boot_interface/Makefile +++ b/examples/device/hid_boot_interface/Makefile @@ -6,7 +6,7 @@ INC += \ $(TOP)/hw \ # Example source -EXAMPLE_SOURCE += \ +EXAMPLE_SOURCE = \ src/main.c \ src/usb_descriptors.c diff --git a/examples/device/hid_composite_freertos/Makefile b/examples/device/hid_composite_freertos/Makefile index 1c1959590..256db3d8c 100644 --- a/examples/device/hid_composite_freertos/Makefile +++ b/examples/device/hid_composite_freertos/Makefile @@ -7,12 +7,17 @@ FREERTOS_SRC = lib/FreeRTOS-Kernel INC += \ src \ + src/FreeRTOSConfig \ $(TOP)/hw \ $(TOP)/$(FREERTOS_SRC)/include \ $(TOP)/$(FREERTOS_SRC)/portable/GCC/$(FREERTOS_PORT) # Example source -EXAMPLE_SOURCE += $(wildcard src/*.c) +EXAMPLE_SOURCE = \ + src/freertos_hook.c \ + src/main.c \ + src/usb_descriptors.c + SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE)) # FreeRTOS source, all files in port folder diff --git a/examples/device/hid_composite_freertos/src/CMakeLists.txt b/examples/device/hid_composite_freertos/src/CMakeLists.txt index 6d4a3c1e2..a2a4fc9b1 100644 --- a/examples/device/hid_composite_freertos/src/CMakeLists.txt +++ b/examples/device/hid_composite_freertos/src/CMakeLists.txt @@ -8,9 +8,7 @@ if(EXISTS ${board_cmake}) include(${board_cmake}) endif() -idf_component_get_property( FREERTOS_ORIG_INCLUDE_PATH freertos ORIG_INCLUDE_PATH) target_include_directories(${COMPONENT_TARGET} PUBLIC - "${FREERTOS_ORIG_INCLUDE_PATH}" "${TOP}/hw" "${TOP}/src" ) diff --git a/examples/device/hid_composite_freertos/src/FreeRTOSConfig.h b/examples/device/hid_composite_freertos/src/FreeRTOSConfig.h deleted file mode 100644 index 568b27a18..000000000 --- a/examples/device/hid_composite_freertos/src/FreeRTOSConfig.h +++ /dev/null @@ -1,182 +0,0 @@ -/* - * FreeRTOS Kernel V10.0.0 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. If you wish to use our Amazon - * FreeRTOS name, please do so in a fair use way that does not cause confusion. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - * - * See http://www.freertos.org/a00110.html. - *----------------------------------------------------------*/ - -// Include MCU header -#include "bsp/board_mcu.h" - -extern uint32_t SystemCoreClock; - -/* Cortex M23/M33 port configuration. */ -#define configENABLE_MPU 0 -#define configENABLE_FPU 1 -#define configENABLE_TRUSTZONE 0 -#define configMINIMAL_SECURE_STACK_SIZE ( 1024 ) - -#define configUSE_PREEMPTION 1 -#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 -#define configCPU_CLOCK_HZ SystemCoreClock -#define configTICK_RATE_HZ ( 1000 ) -#define configMAX_PRIORITIES ( 5 ) -#define configMINIMAL_STACK_SIZE ( 128 ) -#define configTOTAL_HEAP_SIZE ( 0*1024 ) // dynamic is not used -#define configMAX_TASK_NAME_LEN 16 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 1 -#define configUSE_MUTEXES 1 -#define configUSE_RECURSIVE_MUTEXES 1 -#define configUSE_COUNTING_SEMAPHORES 1 -#define configQUEUE_REGISTRY_SIZE 2 -#define configUSE_QUEUE_SETS 0 -#define configUSE_TIME_SLICING 0 -#define configUSE_NEWLIB_REENTRANT 0 -#define configENABLE_BACKWARD_COMPATIBILITY 1 -#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 - -#define configSUPPORT_STATIC_ALLOCATION 1 -#define configSUPPORT_DYNAMIC_ALLOCATION 0 - -/* Hook function related definitions. */ -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 -#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning -#define configCHECK_FOR_STACK_OVERFLOW 2 - -/* Run time and task stats gathering related definitions. */ -#define configGENERATE_RUN_TIME_STATS 0 -#define configUSE_TRACE_FACILITY 1 // legacy trace -#define configUSE_STATS_FORMATTING_FUNCTIONS 0 - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES 2 - -/* Software timer related definitions. */ -#define configUSE_TIMERS 1 -#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) -#define configTIMER_QUEUE_LENGTH 32 -#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE - -/* Optional functions - most linkers will remove unused functions anyway. */ -#define INCLUDE_vTaskPrioritySet 0 -#define INCLUDE_uxTaskPriorityGet 0 -#define INCLUDE_vTaskDelete 0 -#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY -#define INCLUDE_xResumeFromISR 0 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 -#define INCLUDE_xTaskGetSchedulerState 0 -#define INCLUDE_xTaskGetCurrentTaskHandle 0 -#define INCLUDE_uxTaskGetStackHighWaterMark 0 -#define INCLUDE_xTaskGetIdleTaskHandle 0 -#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 -#define INCLUDE_pcTaskGetTaskName 0 -#define INCLUDE_eTaskGetState 0 -#define INCLUDE_xEventGroupSetBitFromISR 0 -#define INCLUDE_xTimerPendFunctionCall 0 - -/* Define to trap errors during development. */ -// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7 -#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) - #define configASSERT(_exp) \ - do {\ - if ( !(_exp) ) { \ - volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \ - if ( (*ARM_CM_DHCSR) & 1UL ) { /* Only halt mcu if debugger is attached */ \ - taskDISABLE_INTERRUPTS(); \ - __asm("BKPT #0\n"); \ - }\ - }\ - } while(0) -#else - #define configASSERT( x ) -#endif - -#ifdef __RX__ -/* Renesas RX series */ -#define vSoftwareInterruptISR INT_Excep_ICU_SWINT -#define vTickISR INT_Excep_CMT0_CMI0 -#define configPERIPHERAL_CLOCK_HZ (configCPU_CLOCK_HZ/2) -#define configKERNEL_INTERRUPT_PRIORITY 1 -#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 - -#else - -/* FreeRTOS hooks to NVIC vectors */ -#define xPortPendSVHandler PendSV_Handler -#define xPortSysTickHandler SysTick_Handler -#define vPortSVCHandler SVC_Handler - -//--------------------------------------------------------------------+ -// Interrupt nesting behavior configuration. -//--------------------------------------------------------------------+ -#if defined(__NVIC_PRIO_BITS) - // For Cortex-M specific: __NVIC_PRIO_BITS is defined in core_cmx.h - #define configPRIO_BITS __NVIC_PRIO_BITS -#elif defined(__ECLIC_INTCTLBITS) - // RISC-V Bumblebee core from nuclei - #define configPRIO_BITS __ECLIC_INTCTLBITS -#else - #error "FreeRTOS configPRIO_BITS to be defined" -#endif - -/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ -#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<DHCSR */ \ + if ( (*ARM_CM_DHCSR) & 1UL ) { /* Only halt mcu if debugger is attached */ \ + taskDISABLE_INTERRUPTS(); \ + __asm("BKPT #0\n"); \ + }\ + }\ + } while(0) +#else + #define configASSERT( x ) +#endif + +#ifdef __RX__ +/* Renesas RX series */ +#define vSoftwareInterruptISR INT_Excep_ICU_SWINT +#define vTickISR INT_Excep_CMT0_CMI0 +#define configPERIPHERAL_CLOCK_HZ (configCPU_CLOCK_HZ/2) +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + +#else + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behavior configuration. +//--------------------------------------------------------------------+ +#if defined(__NVIC_PRIO_BITS) + // For Cortex-M specific: __NVIC_PRIO_BITS is defined in core_cmx.h + #define configPRIO_BITS __NVIC_PRIO_BITS +#elif defined(__ECLIC_INTCTLBITS) + // RISC-V Bumblebee core from nuclei + #define configPRIO_BITS __ECLIC_INTCTLBITS +#else + #error "FreeRTOS configPRIO_BITS to be defined" +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1< #include -#include "FreeRTOS.h" -#include "task.h" -#include "timers.h" -#include "queue.h" -#include "semphr.h" - #include "bsp/board.h" #include "tusb.h" - #include "usb_descriptors.h" +// FreeRTOS headers, MCUs such as esp32sx requires "freertos/" prefix in include path. +// CFG_TUSB_OS_INC_PATH should be defined accordingly. +#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,FreeRTOS.h) +#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,semphr.h) +#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,queue.h) +#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,task.h) +#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,timers.h) + //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF PROTYPES //--------------------------------------------------------------------+ @@ -96,7 +97,7 @@ int main(void) (void) xTaskCreateStatic( hid_task, "hid", HID_STACK_SZIE, NULL, configMAX_PRIORITIES-2, hid_stack, &hid_taskdef); // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3 -#if CFG_TUSB_MCU != OPT_MCU_ESP32S2 && CFG_TUSB_MCU != OPT_MCU_ESP32S3 +#if !( TU_CHECK_MCU(ESP32S2) || TU_CHECK_MCU(ESP32S3) ) vTaskStartScheduler(); #endif diff --git a/examples/device/hid_composite_freertos/src/tusb_config.h b/examples/device/hid_composite_freertos/src/tusb_config.h index 4fbccc294..b061dce3f 100644 --- a/examples/device/hid_composite_freertos/src/tusb_config.h +++ b/examples/device/hid_composite_freertos/src/tusb_config.h @@ -67,6 +67,12 @@ // This examples use FreeRTOS #define CFG_TUSB_OS OPT_OS_FREERTOS +// Espressif IDF requires "freertos/" prefix in include path +#if TU_CHECK_MCU(ESP32S2) || TU_CHECK_MCU(ESP32S3) + #define CFG_TUSB_OS_INC_PATH freertos/ +#endif + + #ifndef CFG_TUSB_DEBUG #define CFG_TUSB_DEBUG 0 #endif diff --git a/hw/bsp/esp32s2/boards/CMakeLists.txt b/hw/bsp/esp32s2/boards/CMakeLists.txt index 71753012b..c3c687a70 100644 --- a/hw/bsp/esp32s2/boards/CMakeLists.txt +++ b/hw/bsp/esp32s2/boards/CMakeLists.txt @@ -6,9 +6,7 @@ idf_component_register(SRCS esp32s2.c # Apply board specific content include("${BOARD}/board.cmake") -idf_component_get_property( FREERTOS_ORIG_INCLUDE_PATH freertos ORIG_INCLUDE_PATH) target_include_directories(${COMPONENT_TARGET} PUBLIC - "${FREERTOS_ORIG_INCLUDE_PATH}" "${TOP}/hw" "${TOP}/src" ) diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h index d3adbbc2d..3e85939b0 100644 --- a/src/common/tusb_compiler.h +++ b/src/common/tusb_compiler.h @@ -32,6 +32,7 @@ #ifndef _TUSB_COMPILER_H_ #define _TUSB_COMPILER_H_ +#define TU_TOKEN(x) x #define TU_STRING(x) #x ///< stringify without expand #define TU_XSTRING(x) TU_STRING(x) ///< expand then stringify @@ -41,6 +42,8 @@ #define TU_XSTRCAT(a, b) TU_STRCAT(a, b) ///< expand then concat #define TU_XSTRCAT3(a, b, c) TU_STRCAT3(a, b, c) ///< expand then concat 3 tokens +#define TU_INCLUDE_PATH(_dir,_file) TU_XSTRING( TU_TOKEN(_dir)TU_TOKEN(_file) ) + #if defined __COUNTER__ && __COUNTER__ != __COUNTER__ #define _TU_COUNTER_ __COUNTER__ #else diff --git a/src/osal/osal_freertos.h b/src/osal/osal_freertos.h index 66070c273..4573e01f5 100644 --- a/src/osal/osal_freertos.h +++ b/src/osal/osal_freertos.h @@ -28,10 +28,10 @@ #define _TUSB_OSAL_FREERTOS_H_ // FreeRTOS Headers -#include "FreeRTOS.h" -#include "semphr.h" -#include "queue.h" -#include "task.h" +#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,FreeRTOS.h) +#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,semphr.h) +#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,queue.h) +#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,task.h) #ifdef __cplusplus extern "C" { diff --git a/src/tusb_option.h b/src/tusb_option.h index a00f3489f..ad2a26a66 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -203,14 +203,20 @@ #define CFG_TUSB_MEM_SECTION #endif +// alignment requirement of buffer used for endpoint transferring #ifndef CFG_TUSB_MEM_ALIGN #define CFG_TUSB_MEM_ALIGN TU_ATTR_ALIGNED(4) #endif +// OS selection #ifndef CFG_TUSB_OS #define CFG_TUSB_OS OPT_OS_NONE #endif +#ifndef CFG_TUSB_OS_INC_PATH + #define CFG_TUSB_OS_INC_PATH +#endif + //-------------------------------------------------------------------- // DEVICE OPTIONS //-------------------------------------------------------------------- -- cgit v1.3.1 From 03d7988df3f491515389751a8cf4baecafb155fc Mon Sep 17 00:00:00 2001 From: Peter Lawrence <12226419+majbthrd@users.noreply.github.com> Date: Tue, 3 Aug 2021 11:28:44 -0500 Subject: add NCM driver in a compatible manner : hathach/tinyusb#550 --- .../device/cdc_msc_freertos/src/CMakeLists.txt | 3 +- .../hid_composite_freertos/src/CMakeLists.txt | 3 +- examples/device/net_lwip_webserver/src/main.c | 2 +- .../device/net_lwip_webserver/src/tusb_config.h | 1 + .../net_lwip_webserver/src/usb_descriptors.c | 20 + examples/rules.mk | 3 +- hw/bsp/rp2040/family.cmake | 3 +- src/class/cdc/cdc.h | 6 +- src/class/net/ecmrndis_device.c | 445 ++++++++++++++++++ src/class/net/ncm_device.c | 500 +++++++++++++++++++++ src/class/net/net_device.c | 441 ------------------ src/class/net/net_device.h | 21 +- src/device/usbd.h | 31 ++ src/tusb_option.h | 4 + 14 files changed, 1034 insertions(+), 449 deletions(-) create mode 100644 src/class/net/ecmrndis_device.c create mode 100644 src/class/net/ncm_device.c delete mode 100644 src/class/net/net_device.c diff --git a/examples/device/cdc_msc_freertos/src/CMakeLists.txt b/examples/device/cdc_msc_freertos/src/CMakeLists.txt index c0a665fa0..f1c1e8c5d 100644 --- a/examples/device/cdc_msc_freertos/src/CMakeLists.txt +++ b/examples/device/cdc_msc_freertos/src/CMakeLists.txt @@ -23,7 +23,8 @@ target_sources(${COMPONENT_TARGET} PUBLIC "${TOP}/src/class/hid/hid_device.c" "${TOP}/src/class/midi/midi_device.c" "${TOP}/src/class/msc/msc_device.c" - "${TOP}/src/class/net/net_device.c" + "${TOP}/src/class/net/ecmrndis_device.c" + "${TOP}/src/class/net/ncm_device.c" "${TOP}/src/class/usbtmc/usbtmc_device.c" "${TOP}/src/class/vendor/vendor_device.c" "${TOP}/src/portable/espressif/esp32sx/dcd_esp32sx.c" diff --git a/examples/device/hid_composite_freertos/src/CMakeLists.txt b/examples/device/hid_composite_freertos/src/CMakeLists.txt index a2a4fc9b1..70df447dd 100644 --- a/examples/device/hid_composite_freertos/src/CMakeLists.txt +++ b/examples/device/hid_composite_freertos/src/CMakeLists.txt @@ -23,7 +23,8 @@ target_sources(${COMPONENT_TARGET} PUBLIC "${TOP}/src/class/hid/hid_device.c" "${TOP}/src/class/midi/midi_device.c" "${TOP}/src/class/msc/msc_device.c" - "${TOP}/src/class/net/net_device.c" + "${TOP}/src/class/net/ecmrndis_device.c" + "${TOP}/src/class/net/ncm_device.c" "${TOP}/src/class/usbtmc/usbtmc_device.c" "${TOP}/src/class/vendor/vendor_device.c" "${TOP}/src/portable/espressif/esp32sx/dcd_esp32sx.c" diff --git a/examples/device/net_lwip_webserver/src/main.c b/examples/device/net_lwip_webserver/src/main.c index 80831921a..a5bd2153a 100644 --- a/examples/device/net_lwip_webserver/src/main.c +++ b/examples/device/net_lwip_webserver/src/main.c @@ -97,7 +97,7 @@ static err_t linkoutput_fn(struct netif *netif, struct pbuf *p) return ERR_USE; /* if the network driver can accept another packet, we make it happen */ - if (tud_network_can_xmit()) + if (tud_network_can_xmit(p->tot_len)) { tud_network_xmit(p, 0 /* unused for this example */); return ERR_OK; diff --git a/examples/device/net_lwip_webserver/src/tusb_config.h b/examples/device/net_lwip_webserver/src/tusb_config.h index 262d4ebce..457918cac 100644 --- a/examples/device/net_lwip_webserver/src/tusb_config.h +++ b/examples/device/net_lwip_webserver/src/tusb_config.h @@ -101,6 +101,7 @@ #define CFG_TUD_MIDI 0 #define CFG_TUD_VENDOR 0 #define CFG_TUD_NET 1 +#define CFG_TUD_NCM 0 #ifdef __cplusplus } diff --git a/examples/device/net_lwip_webserver/src/usb_descriptors.c b/examples/device/net_lwip_webserver/src/usb_descriptors.c index 71e6c4582..d9618a3dc 100644 --- a/examples/device/net_lwip_webserver/src/usb_descriptors.c +++ b/examples/device/net_lwip_webserver/src/usb_descriptors.c @@ -55,8 +55,12 @@ enum enum { +#if !CFG_TUD_NCM CONFIG_ID_RNDIS = 0, CONFIG_ID_ECM = 1, +#else + CONFIG_ID_NCM = 0, +#endif CONFIG_ID_COUNT }; @@ -99,6 +103,7 @@ uint8_t const * tud_descriptor_device_cb(void) //--------------------------------------------------------------------+ #define MAIN_CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + TUD_RNDIS_DESC_LEN) #define ALT_CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + TUD_CDC_ECM_DESC_LEN) +#define NCM_CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + TUD_CDC_NCM_DESC_LEN) #if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number @@ -120,6 +125,7 @@ uint8_t const * tud_descriptor_device_cb(void) #define EPNUM_NET_IN 0x82 #endif +#if !CFG_TUD_NCM static uint8_t const rndis_configuration[] = { // Config number (index+1), interface count, string index, total length, attribute, power in mA @@ -137,6 +143,16 @@ static uint8_t const ecm_configuration[] = // Interface number, description string index, MAC address string index, EP notification address and size, EP data address (out, in), and size, max segment size. TUD_CDC_ECM_DESCRIPTOR(ITF_NUM_CDC, STRID_INTERFACE, STRID_MAC, EPNUM_NET_NOTIF, 64, EPNUM_NET_OUT, EPNUM_NET_IN, CFG_TUD_NET_ENDPOINT_SIZE, CFG_TUD_NET_MTU), }; +#else +static uint8_t const ncm_configuration[] = +{ + // Config number (index+1), interface count, string index, total length, attribute, power in mA + TUD_CONFIG_DESCRIPTOR(CONFIG_ID_NCM+1, ITF_NUM_TOTAL, 0, NCM_CONFIG_TOTAL_LEN, 0, 100), + + // Interface number, description string index, MAC address string index, EP notification address and size, EP data address (out, in), and size, max segment size. + TUD_CDC_NCM_DESCRIPTOR(ITF_NUM_CDC, STRID_INTERFACE, STRID_MAC, EPNUM_NET_NOTIF, 64, EPNUM_NET_OUT, EPNUM_NET_IN, CFG_TUD_NET_ENDPOINT_SIZE, CFG_TUD_NET_MTU), +}; +#endif // Configuration array: RNDIS and CDC-ECM // - Windows only works with RNDIS @@ -144,8 +160,12 @@ static uint8_t const ecm_configuration[] = // - Linux will work on both static uint8_t const * const configuration_arr[2] = { +#if !CFG_TUD_NCM [CONFIG_ID_RNDIS] = rndis_configuration, [CONFIG_ID_ECM ] = ecm_configuration +#else + [CONFIG_ID_NCM ] = ncm_configuration +#endif }; // Invoked when received GET CONFIGURATION DESCRIPTOR diff --git a/examples/rules.mk b/examples/rules.mk index 861973284..a9dfa1363 100644 --- a/examples/rules.mk +++ b/examples/rules.mk @@ -33,7 +33,8 @@ SRC_C += \ src/class/hid/hid_device.c \ src/class/midi/midi_device.c \ src/class/msc/msc_device.c \ - src/class/net/net_device.c \ + src/class/net/ecmrndis_device.c \ + src/class/net/ncm_device.c \ src/class/usbtmc/usbtmc_device.c \ src/class/vendor/vendor_device.c diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake index 41960b6cd..a0f41212c 100644 --- a/hw/bsp/rp2040/family.cmake +++ b/hw/bsp/rp2040/family.cmake @@ -70,7 +70,8 @@ if (NOT TARGET _rp2040_family_inclusion_marker) ${TOP}/src/class/hid/hid_device.c ${TOP}/src/class/midi/midi_device.c ${TOP}/src/class/msc/msc_device.c - ${TOP}/src/class/net/net_device.c + ${TOP}/src/class/net/ecmrndis_device.c + ${TOP}/src/class/net/ncm_device.c ${TOP}/src/class/usbtmc/usbtmc_device.c ${TOP}/src/class/vendor/vendor_device.c ) diff --git a/src/class/cdc/cdc.h b/src/class/cdc/cdc.h index 5df47f70b..52de859ca 100644 --- a/src/class/cdc/cdc.h +++ b/src/class/cdc/cdc.h @@ -69,7 +69,8 @@ typedef enum CDC_COMM_SUBCLASS_DEVICE_MANAGEMENT , ///< Device Management [USBWMC1.1] CDC_COMM_SUBCLASS_MOBILE_DIRECT_LINE_MODEL , ///< Mobile Direct Line Model [USBWMC1.1] CDC_COMM_SUBCLASS_OBEX , ///< OBEX [USBWMC1.1] - CDC_COMM_SUBCLASS_ETHERNET_EMULATION_MODEL ///< Ethernet Emulation Model [USBEEM1.0] + CDC_COMM_SUBCLASS_ETHERNET_EMULATION_MODEL , ///< Ethernet Emulation Model [USBEEM1.0] + CDC_COMM_SUBCLASS_NETWORK_CONTROL_MODEL ///< Network Control Model [USBNCM1.0] } cdc_comm_sublcass_type_t; /// Communication Interface Protocol Codes @@ -114,7 +115,8 @@ typedef enum CDC_FUNC_DESC_COMMAND_SET = 0x16 , ///< Command Set Functional Descriptor CDC_FUNC_DESC_COMMAND_SET_DETAIL = 0x17 , ///< Command Set Detail Functional Descriptor CDC_FUNC_DESC_TELEPHONE_CONTROL_MODEL = 0x18 , ///< Telephone Control Model Functional Descriptor - CDC_FUNC_DESC_OBEX_SERVICE_IDENTIFIER = 0x19 ///< OBEX Service Identifier Functional Descriptor + CDC_FUNC_DESC_OBEX_SERVICE_IDENTIFIER = 0x19 , ///< OBEX Service Identifier Functional Descriptor + CDC_FUNC_DESC_NCM = 0x1A , ///< NCM Functional Descriptor }cdc_func_desc_type_t; //--------------------------------------------------------------------+ diff --git a/src/class/net/ecmrndis_device.c b/src/class/net/ecmrndis_device.c new file mode 100644 index 000000000..288ecb7e2 --- /dev/null +++ b/src/class/net/ecmrndis_device.c @@ -0,0 +1,445 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020 Peter Lawrence + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "tusb_option.h" + +#if ( TUSB_OPT_DEVICE_ENABLED && CFG_TUD_NET && !CFG_TUD_NCM ) + +#include "device/usbd.h" +#include "device/usbd_pvt.h" + +#include "net_device.h" +#include "rndis_protocol.h" + +void rndis_class_set_handler(uint8_t *data, int size); /* found in ./misc/networking/rndis_reports.c */ + +//--------------------------------------------------------------------+ +// MACRO CONSTANT TYPEDEF +//--------------------------------------------------------------------+ +typedef struct +{ + uint8_t itf_num; // Index number of Management Interface, +1 for Data Interface + uint8_t itf_data_alt; // Alternate setting of Data Interface. 0 : inactive, 1 : active + + uint8_t ep_notif; + uint8_t ep_in; + uint8_t ep_out; + + bool ecm_mode; + + // Endpoint descriptor use to open/close when receving SetInterface + // TODO since configuration descriptor may not be long-lived memory, we should + // keep a copy of endpoint attribute instead + uint8_t const * ecm_desc_epdata; + +} netd_interface_t; + +#define CFG_TUD_NET_PACKET_PREFIX_LEN sizeof(rndis_data_packet_t) +#define CFG_TUD_NET_PACKET_SUFFIX_LEN 0 + +CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t received[CFG_TUD_NET_PACKET_PREFIX_LEN + CFG_TUD_NET_MTU + CFG_TUD_NET_PACKET_PREFIX_LEN]; +CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t transmitted[CFG_TUD_NET_PACKET_PREFIX_LEN + CFG_TUD_NET_MTU + CFG_TUD_NET_PACKET_PREFIX_LEN]; + +struct ecm_notify_struct +{ + tusb_control_request_t header; + uint32_t downlink, uplink; +}; + +static const struct ecm_notify_struct ecm_notify_nc = +{ + .header = { + .bmRequestType = 0xA1, + .bRequest = 0 /* NETWORK_CONNECTION aka NetworkConnection */, + .wValue = 1 /* Connected */, + .wLength = 0, + }, +}; + +static const struct ecm_notify_struct ecm_notify_csc = +{ + .header = { + .bmRequestType = 0xA1, + .bRequest = 0x2A /* CONNECTION_SPEED_CHANGE aka ConnectionSpeedChange */, + .wLength = 8, + }, + .downlink = 9728000, + .uplink = 9728000, +}; + +// TODO remove CFG_TUSB_MEM_SECTION, control internal buffer is already in this special section +CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static union +{ + uint8_t rndis_buf[120]; + struct ecm_notify_struct ecm_buf; +} notify; + +//--------------------------------------------------------------------+ +// INTERNAL OBJECT & FUNCTION DECLARATION +//--------------------------------------------------------------------+ +// TODO remove CFG_TUSB_MEM_SECTION +CFG_TUSB_MEM_SECTION static netd_interface_t _netd_itf; + +static bool can_xmit; + +void tud_network_recv_renew(void) +{ + usbd_edpt_xfer(TUD_OPT_RHPORT, _netd_itf.ep_out, received, sizeof(received)); +} + +static void do_in_xfer(uint8_t *buf, uint16_t len) +{ + can_xmit = false; + usbd_edpt_xfer(TUD_OPT_RHPORT, _netd_itf.ep_in, buf, len); +} + +void netd_report(uint8_t *buf, uint16_t len) +{ + // skip if previous report not yet acknowledged by host + if ( usbd_edpt_busy(TUD_OPT_RHPORT, _netd_itf.ep_notif) ) return; + usbd_edpt_xfer(TUD_OPT_RHPORT, _netd_itf.ep_notif, buf, len); +} + +//--------------------------------------------------------------------+ +// USBD Driver API +//--------------------------------------------------------------------+ +void netd_init(void) +{ + tu_memclr(&_netd_itf, sizeof(_netd_itf)); +} + +void netd_reset(uint8_t rhport) +{ + (void) rhport; + + netd_init(); +} + +uint16_t netd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len) +{ + bool const is_rndis = (TUD_RNDIS_ITF_CLASS == itf_desc->bInterfaceClass && + TUD_RNDIS_ITF_SUBCLASS == itf_desc->bInterfaceSubClass && + TUD_RNDIS_ITF_PROTOCOL == itf_desc->bInterfaceProtocol); + + bool const is_ecm = (TUSB_CLASS_CDC == itf_desc->bInterfaceClass && + CDC_COMM_SUBCLASS_ETHERNET_CONTROL_MODEL == itf_desc->bInterfaceSubClass && + 0x00 == itf_desc->bInterfaceProtocol); + + TU_VERIFY(is_rndis || is_ecm, 0); + + // confirm interface hasn't already been allocated + TU_ASSERT(0 == _netd_itf.ep_notif, 0); + + // sanity check the descriptor + _netd_itf.ecm_mode = is_ecm; + + //------------- Management Interface -------------// + _netd_itf.itf_num = itf_desc->bInterfaceNumber; + + uint16_t drv_len = sizeof(tusb_desc_interface_t); + uint8_t const * p_desc = tu_desc_next( itf_desc ); + + // Communication Functional Descriptors + while ( TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc) && drv_len <= max_len ) + { + drv_len += tu_desc_len(p_desc); + p_desc = tu_desc_next(p_desc); + } + + // notification endpoint (if any) + if ( TUSB_DESC_ENDPOINT == tu_desc_type(p_desc) ) + { + TU_ASSERT( usbd_edpt_open(rhport, (tusb_desc_endpoint_t const *) p_desc), 0 ); + + _netd_itf.ep_notif = ((tusb_desc_endpoint_t const *) p_desc)->bEndpointAddress; + + drv_len += tu_desc_len(p_desc); + p_desc = tu_desc_next(p_desc); + } + + //------------- Data Interface -------------// + // - RNDIS Data followed immediately by a pair of endpoints + // - CDC-ECM data interface has 2 alternate settings + // - 0 : zero endpoints for inactive (default) + // - 1 : IN & OUT endpoints for active networking + TU_ASSERT(TUSB_DESC_INTERFACE == tu_desc_type(p_desc), 0); + + do + { + tusb_desc_interface_t const * data_itf_desc = (tusb_desc_interface_t const *) p_desc; + TU_ASSERT(TUSB_CLASS_CDC_DATA == data_itf_desc->bInterfaceClass, 0); + + drv_len += tu_desc_len(p_desc); + p_desc = tu_desc_next(p_desc); + }while( _netd_itf.ecm_mode && (TUSB_DESC_INTERFACE == tu_desc_type(p_desc)) && (drv_len <= max_len) ); + + // Pair of endpoints + TU_ASSERT(TUSB_DESC_ENDPOINT == tu_desc_type(p_desc), 0); + + if ( _netd_itf.ecm_mode ) + { + // ECM by default is in-active, save the endpoint attribute + // to open later when received setInterface + _netd_itf.ecm_desc_epdata = p_desc; + }else + { + // Open endpoint pair for RNDIS + TU_ASSERT( usbd_open_edpt_pair(rhport, p_desc, 2, TUSB_XFER_BULK, &_netd_itf.ep_out, &_netd_itf.ep_in), 0 ); + + tud_network_init_cb(); + + // we are ready to transmit a packet + can_xmit = true; + + // prepare for incoming packets + tud_network_recv_renew(); + } + + drv_len += 2*sizeof(tusb_desc_endpoint_t); + + return drv_len; +} + +static void ecm_report(bool nc) +{ + notify.ecm_buf = (nc) ? ecm_notify_nc : ecm_notify_csc; + notify.ecm_buf.header.wIndex = _netd_itf.itf_num; + netd_report((uint8_t *)¬ify.ecm_buf, (nc) ? sizeof(notify.ecm_buf.header) : sizeof(notify.ecm_buf)); +} + +// Invoked when a control transfer occurred on an interface of this class +// Driver response accordingly to the request and the transfer stage (setup/data/ack) +// return false to stall control endpoint (e.g unsupported request) +bool netd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t const * request) +{ + if ( stage == CONTROL_STAGE_SETUP ) + { + switch ( request->bmRequestType_bit.type ) + { + case TUSB_REQ_TYPE_STANDARD: + switch ( request->bRequest ) + { + case TUSB_REQ_GET_INTERFACE: + { + uint8_t const req_itfnum = (uint8_t) request->wIndex; + TU_VERIFY(_netd_itf.itf_num+1 == req_itfnum); + + tud_control_xfer(rhport, request, &_netd_itf.itf_data_alt, 1); + } + break; + + case TUSB_REQ_SET_INTERFACE: + { + uint8_t const req_itfnum = (uint8_t) request->wIndex; + uint8_t const req_alt = (uint8_t) request->wValue; + + // Only valid for Data Interface with Alternate is either 0 or 1 + TU_VERIFY(_netd_itf.itf_num+1 == req_itfnum && req_alt < 2); + + // ACM-ECM only: qequest to enable/disable network activities + TU_VERIFY(_netd_itf.ecm_mode); + + _netd_itf.itf_data_alt = req_alt; + + if ( _netd_itf.itf_data_alt ) + { + // TODO since we don't actually close endpoint + // hack here to not re-open it + if ( _netd_itf.ep_in == 0 && _netd_itf.ep_out == 0 ) + { + TU_ASSERT(_netd_itf.ecm_desc_epdata); + TU_ASSERT( usbd_open_edpt_pair(rhport, _netd_itf.ecm_desc_epdata, 2, TUSB_XFER_BULK, &_netd_itf.ep_out, &_netd_itf.ep_in) ); + + // TODO should be merge with RNDIS's after endpoint opened + // Also should have opposite callback for application to disable network !! + tud_network_init_cb(); + can_xmit = true; // we are ready to transmit a packet + tud_network_recv_renew(); // prepare for incoming packets + } + }else + { + // TODO close the endpoint pair + // For now pretend that we did, this should have no harm since host won't try to + // communicate with the endpoints again + // _netd_itf.ep_in = _netd_itf.ep_out = 0 + } + + tud_control_status(rhport, request); + } + break; + + // unsupported request + default: return false; + } + break; + + case TUSB_REQ_TYPE_CLASS: + TU_VERIFY (_netd_itf.itf_num == request->wIndex); + + if (_netd_itf.ecm_mode) + { + /* the only required CDC-ECM Management Element Request is SetEthernetPacketFilter */ + if (0x43 /* SET_ETHERNET_PACKET_FILTER */ == request->bRequest) + { + tud_control_xfer(rhport, request, NULL, 0); + ecm_report(true); + } + } + else + { + if (request->bmRequestType_bit.direction == TUSB_DIR_IN) + { + rndis_generic_msg_t *rndis_msg = (rndis_generic_msg_t *) ((void*) notify.rndis_buf); + uint32_t msglen = tu_le32toh(rndis_msg->MessageLength); + TU_ASSERT(msglen <= sizeof(notify.rndis_buf)); + tud_control_xfer(rhport, request, notify.rndis_buf, msglen); + } + else + { + tud_control_xfer(rhport, request, notify.rndis_buf, sizeof(notify.rndis_buf)); + } + } + break; + + // unsupported request + default: return false; + } + } + else if ( stage == CONTROL_STAGE_DATA ) + { + // Handle RNDIS class control OUT only + if (request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS && + request->bmRequestType_bit.direction == TUSB_DIR_OUT && + _netd_itf.itf_num == request->wIndex) + { + if ( !_netd_itf.ecm_mode ) + { + rndis_class_set_handler(notify.rndis_buf, request->wLength); + } + } + } + + return true; +} + +static void handle_incoming_packet(uint32_t len) +{ + uint8_t *pnt = received; + uint32_t size = 0; + + if (_netd_itf.ecm_mode) + { + size = len; + } + else + { + rndis_data_packet_t *r = (rndis_data_packet_t *) ((void*) pnt); + if (len >= sizeof(rndis_data_packet_t)) + if ( (r->MessageType == REMOTE_NDIS_PACKET_MSG) && (r->MessageLength <= len)) + if ( (r->DataOffset + offsetof(rndis_data_packet_t, DataOffset) + r->DataLength) <= len) + { + pnt = &received[r->DataOffset + offsetof(rndis_data_packet_t, DataOffset)]; + size = r->DataLength; + } + } + + if (!tud_network_recv_cb(pnt, size)) + { + /* if a buffer was never handled by user code, we must renew on the user's behalf */ + tud_network_recv_renew(); + } +} + +bool netd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) +{ + (void) rhport; + (void) result; + + /* new packet received */ + if ( ep_addr == _netd_itf.ep_out ) + { + handle_incoming_packet(xferred_bytes); + } + + /* data transmission finished */ + if ( ep_addr == _netd_itf.ep_in ) + { + /* TinyUSB requires the class driver to implement ZLP (since ZLP usage is class-specific) */ + + if ( xferred_bytes && (0 == (xferred_bytes % CFG_TUD_NET_ENDPOINT_SIZE)) ) + { + do_in_xfer(NULL, 0); /* a ZLP is needed */ + } + else + { + /* we're finally finished */ + can_xmit = true; + } + } + + if ( _netd_itf.ecm_mode && (ep_addr == _netd_itf.ep_notif) ) + { + if (sizeof(notify.ecm_buf.header) == xferred_bytes) ecm_report(false); + } + + return true; +} + +bool tud_network_can_xmit(uint16_t size) +{ + (void)size; + + return can_xmit; +} + +void tud_network_xmit(void *ref, uint16_t arg) +{ + uint8_t *data; + uint16_t len; + + if (!can_xmit) + return; + + len = (_netd_itf.ecm_mode) ? 0 : CFG_TUD_NET_PACKET_PREFIX_LEN; + data = transmitted + len; + + len += tud_network_xmit_cb(data, ref, arg); + + if (!_netd_itf.ecm_mode) + { + rndis_data_packet_t *hdr = (rndis_data_packet_t *) ((void*) transmitted); + memset(hdr, 0, sizeof(rndis_data_packet_t)); + hdr->MessageType = REMOTE_NDIS_PACKET_MSG; + hdr->MessageLength = len; + hdr->DataOffset = sizeof(rndis_data_packet_t) - offsetof(rndis_data_packet_t, DataOffset); + hdr->DataLength = len - sizeof(rndis_data_packet_t); + } + + do_in_xfer(transmitted, len); +} + +#endif diff --git a/src/class/net/ncm_device.c b/src/class/net/ncm_device.c new file mode 100644 index 000000000..1f592401e --- /dev/null +++ b/src/class/net/ncm_device.c @@ -0,0 +1,500 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020 Jacob Berg Potter + * Copyright (c) 2020 Peter Lawrence + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "tusb_option.h" + +#if ( TUSB_OPT_DEVICE_ENABLED && CFG_TUD_NET && CFG_TUD_NCM ) + +#include "device/usbd.h" +#include "device/usbd_pvt.h" +#include "net_device.h" + +//--------------------------------------------------------------------+ +// MACRO CONSTANT TYPEDEF +//--------------------------------------------------------------------+ + +#define NTH16_SIGNATURE 0x484D434E +#define NDP16_SIGNATURE_NCM0 0x304D434E +#define NDP16_SIGNATURE_NCM1 0x314D434E + +typedef struct TU_ATTR_PACKED +{ + uint16_t wLength; + uint16_t bmNtbFormatsSupported; + uint32_t dwNtbInMaxSize; + uint16_t wNdbInDivisor; + uint16_t wNdbInPayloadRemainder; + uint16_t wNdbInAlignment; + uint16_t wReserved; + uint32_t dwNtbOutMaxSize; + uint16_t wNdbOutDivisor; + uint16_t wNdbOutPayloadRemainder; + uint16_t wNdbOutAlignment; + uint16_t wNtbOutMaxDatagrams; +} ntb_parameters_t; + +typedef struct TU_ATTR_PACKED +{ + uint32_t dwSignature; + uint16_t wHeaderLength; + uint16_t wSequence; + uint16_t wBlockLength; + uint16_t wNdpIndex; +} nth16_t; + +typedef struct TU_ATTR_PACKED +{ + uint16_t wDatagramIndex; + uint16_t wDatagramLength; +} ndp16_datagram_t; + +typedef struct TU_ATTR_PACKED +{ + uint32_t dwSignature; + uint16_t wLength; + uint16_t wNextNdpIndex; + ndp16_datagram_t datagram[]; +} ndp16_t; + +typedef union TU_ATTR_PACKED { + struct { + nth16_t nth; + ndp16_t ndp; + }; + uint8_t data[CFG_TUD_NCM_IN_NTB_MAX_SIZE]; +} transmit_ntb_t; + +struct ecm_notify_struct +{ + tusb_control_request_t header; + uint32_t downlink, uplink; +}; + +typedef struct +{ + uint8_t itf_num; // Index number of Management Interface, +1 for Data Interface + uint8_t itf_data_alt; // Alternate setting of Data Interface. 0 : inactive, 1 : active + + uint8_t ep_notif; + uint8_t ep_in; + uint8_t ep_out; + + const ndp16_t *ndp; + uint8_t num_datagrams, current_datagram_index; + + enum { + REPORT_SPEED, + REPORT_CONNECTED, + REPORT_DONE + } report_state; + bool report_pending; + + uint8_t current_ntb; // Index in transmit_ntb[] that is currently being filled with datagrams + uint8_t datagram_count; // Number of datagrams in transmit_ntb[current_ntb] + uint16_t next_datagram_offset; // Offset in transmit_ntb[current_ntb].data to place the next datagram + uint16_t ntb_in_size; // Maximum size of transmitted (IN to host) NTBs; initially CFG_TUD_NCM_IN_NTB_MAX_SIZE + uint8_t max_datagrams_per_ntb; // Maximum number of datagrams per NTB; initially CFG_TUD_NCM_MAX_DATAGRAMS_PER_NTB + + uint16_t nth_sequence; // Sequence number counter for transmitted NTBs + + bool transferring; + +} ncm_interface_t; + +//--------------------------------------------------------------------+ +// INTERNAL OBJECT & FUNCTION DECLARATION +//--------------------------------------------------------------------+ + +CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static const ntb_parameters_t ntb_parameters = { + .wLength = sizeof(ntb_parameters_t), + .bmNtbFormatsSupported = 0x01, + .dwNtbInMaxSize = CFG_TUD_NCM_IN_NTB_MAX_SIZE, + .wNdbInDivisor = 4, + .wNdbInPayloadRemainder = 0, + .wNdbInAlignment = CFG_TUD_NCM_ALIGNMENT, + .wReserved = 0, + .dwNtbOutMaxSize = CFG_TUD_NCM_OUT_NTB_MAX_SIZE, + .wNdbOutDivisor = 4, + .wNdbOutPayloadRemainder = 0, + .wNdbOutAlignment = CFG_TUD_NCM_ALIGNMENT, + .wNtbOutMaxDatagrams = 0 +}; + +CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static transmit_ntb_t transmit_ntb[2]; + +CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t receive_ntb[CFG_TUD_NCM_OUT_NTB_MAX_SIZE]; + +static ncm_interface_t ncm_interface; + +/* + * Set up the NTB state in ncm_interface to be ready to add datagrams. + */ +static void ncm_prepare_for_tx(void) { + ncm_interface.datagram_count = 0; + // datagrams start after all the headers + ncm_interface.next_datagram_offset = sizeof(nth16_t) + sizeof(ndp16_t) + + ((CFG_TUD_NCM_MAX_DATAGRAMS_PER_NTB + 1) * sizeof(ndp16_datagram_t)); +} + +/* + * If not already transmitting, start sending the current NTB to the host and swap buffers + * to start filling the other one with datagrams. + */ +static void ncm_start_tx(void) { + if (ncm_interface.transferring) { + return; + } + + transmit_ntb_t *ntb = &transmit_ntb[ncm_interface.current_ntb]; + size_t ntb_length = ncm_interface.next_datagram_offset; + + // Fill in NTB header + ntb->nth.dwSignature = NTH16_SIGNATURE; + ntb->nth.wHeaderLength = sizeof(nth16_t); + ntb->nth.wSequence = ncm_interface.nth_sequence++; + ntb->nth.wBlockLength = ntb_length; + ntb->nth.wNdpIndex = sizeof(nth16_t); + + // Fill in NDP16 header and terminator + ntb->ndp.dwSignature = NDP16_SIGNATURE_NCM0; + ntb->ndp.wLength = sizeof(ndp16_t) + (ncm_interface.datagram_count + 1) * sizeof(ndp16_datagram_t); + ntb->ndp.wNextNdpIndex = 0; + ntb->ndp.datagram[ncm_interface.datagram_count].wDatagramIndex = 0; + ntb->ndp.datagram[ncm_interface.datagram_count].wDatagramLength = 0; + + // Kick off an endpoint transfer + usbd_edpt_xfer(TUD_OPT_RHPORT, ncm_interface.ep_in, ntb->data, ntb_length); + ncm_interface.transferring = true; + + // Swap to the other NTB and clear it out + ncm_interface.current_ntb = 1 - ncm_interface.current_ntb; + ncm_prepare_for_tx(); +} + +static struct ecm_notify_struct ncm_notify_connected = + { + .header = { + .bmRequestType = 0xA1, + .bRequest = 0 /* NETWORK_CONNECTION aka NetworkConnection */, + .wValue = 1 /* Connected */, + .wLength = 0, + }, + }; + +static struct ecm_notify_struct ncm_notify_speed_change = + { + .header = { + .bmRequestType = 0xA1, + .bRequest = 0x2A /* CONNECTION_SPEED_CHANGE aka ConnectionSpeedChange */, + .wLength = 8, + }, + .downlink = 10000000, + .uplink = 10000000, + }; + +void tud_network_recv_renew(void) +{ + if (!ncm_interface.num_datagrams) + { + usbd_edpt_xfer(TUD_OPT_RHPORT, ncm_interface.ep_out, receive_ntb, sizeof(receive_ntb)); + return; + } + + const ndp16_t *ndp = ncm_interface.ndp; + const int i = ncm_interface.current_datagram_index; + ncm_interface.current_datagram_index++; + ncm_interface.num_datagrams--; + + tud_network_recv_cb(receive_ntb + ndp->datagram[i].wDatagramIndex, ndp->datagram[i].wDatagramLength); +} + +//--------------------------------------------------------------------+ +// USBD Driver API +//--------------------------------------------------------------------+ + +void netd_init(void) +{ + tu_memclr(&ncm_interface, sizeof(ncm_interface)); + ncm_interface.ntb_in_size = CFG_TUD_NCM_IN_NTB_MAX_SIZE; + ncm_interface.max_datagrams_per_ntb = CFG_TUD_NCM_MAX_DATAGRAMS_PER_NTB; + ncm_prepare_for_tx(); +} + +void netd_reset(uint8_t rhport) +{ + (void) rhport; + + netd_init(); +} + +uint16_t netd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len) +{ + // confirm interface hasn't already been allocated + TU_ASSERT(0 == ncm_interface.ep_notif, 0); + + //------------- Management Interface -------------// + ncm_interface.itf_num = itf_desc->bInterfaceNumber; + + uint16_t drv_len = sizeof(tusb_desc_interface_t); + uint8_t const * p_desc = tu_desc_next( itf_desc ); + + // Communication Functional Descriptors + while ( TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc) && drv_len <= max_len ) + { + drv_len += tu_desc_len(p_desc); + p_desc = tu_desc_next(p_desc); + } + + // notification endpoint (if any) + if ( TUSB_DESC_ENDPOINT == tu_desc_type(p_desc) ) + { + TU_ASSERT( usbd_edpt_open(rhport, (tusb_desc_endpoint_t const *) p_desc), 0 ); + + ncm_interface.ep_notif = ((tusb_desc_endpoint_t const *) p_desc)->bEndpointAddress; + + drv_len += tu_desc_len(p_desc); + p_desc = tu_desc_next(p_desc); + } + + //------------- Data Interface -------------// + // - CDC-NCM data interface has 2 alternate settings + // - 0 : zero endpoints for inactive (default) + // - 1 : IN & OUT endpoints for transfer of NTBs + TU_ASSERT(TUSB_DESC_INTERFACE == tu_desc_type(p_desc), 0); + + do + { + tusb_desc_interface_t const * data_itf_desc = (tusb_desc_interface_t const *) p_desc; + TU_ASSERT(TUSB_CLASS_CDC_DATA == data_itf_desc->bInterfaceClass, 0); + + drv_len += tu_desc_len(p_desc); + p_desc = tu_desc_next(p_desc); + } while((TUSB_DESC_INTERFACE == tu_desc_type(p_desc)) && (drv_len <= max_len)); + + // Pair of endpoints + TU_ASSERT(TUSB_DESC_ENDPOINT == tu_desc_type(p_desc), 0); + + TU_ASSERT(usbd_open_edpt_pair(rhport, p_desc, 2, TUSB_XFER_BULK, &ncm_interface.ep_out, &ncm_interface.ep_in) ); + + drv_len += 2*sizeof(tusb_desc_endpoint_t); + + return drv_len; +} + +static void ncm_report(void) +{ + if (ncm_interface.report_state == REPORT_SPEED) { + ncm_notify_speed_change.header.wIndex = ncm_interface.itf_num; + usbd_edpt_xfer(TUD_OPT_RHPORT, ncm_interface.ep_notif, (uint8_t *) &ncm_notify_speed_change, sizeof(ncm_notify_speed_change)); + ncm_interface.report_state = REPORT_CONNECTED; + ncm_interface.report_pending = true; + } else if (ncm_interface.report_state == REPORT_CONNECTED) { + ncm_notify_connected.header.wIndex = ncm_interface.itf_num; + usbd_edpt_xfer(TUD_OPT_RHPORT, ncm_interface.ep_notif, (uint8_t *) &ncm_notify_connected, sizeof(ncm_notify_connected)); + ncm_interface.report_state = REPORT_DONE; + ncm_interface.report_pending = true; + } +} + +TU_ATTR_WEAK void tud_network_link_state_cb(bool state) +{ + (void)state; +} + +// Handle class control request +// return false to stall control endpoint (e.g unsupported request) +bool netd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request) +{ + if ( stage != CONTROL_STAGE_SETUP ) return true; + + switch ( request->bmRequestType_bit.type ) + { + case TUSB_REQ_TYPE_STANDARD: + switch ( request->bRequest ) + { + case TUSB_REQ_GET_INTERFACE: + { + uint8_t const req_itfnum = (uint8_t) request->wIndex; + TU_VERIFY(ncm_interface.itf_num + 1 == req_itfnum); + + tud_control_xfer(rhport, request, &ncm_interface.itf_data_alt, 1); + } + break; + + case TUSB_REQ_SET_INTERFACE: + { + uint8_t const req_itfnum = (uint8_t) request->wIndex; + uint8_t const req_alt = (uint8_t) request->wValue; + + // Only valid for Data Interface with Alternate is either 0 or 1 + TU_VERIFY(ncm_interface.itf_num + 1 == req_itfnum && req_alt < 2); + + if (req_alt != ncm_interface.itf_data_alt) { + ncm_interface.itf_data_alt = req_alt; + + if (ncm_interface.itf_data_alt) { + if (!usbd_edpt_busy(rhport, ncm_interface.ep_out)) { + tud_network_recv_renew(); // prepare for incoming datagrams + } + if (!ncm_interface.report_pending) { + ncm_report(); + } + } + + tud_network_link_state_cb(ncm_interface.itf_data_alt); + } + + tud_control_status(rhport, request); + } + break; + + // unsupported request + default: return false; + } + break; + + case TUSB_REQ_TYPE_CLASS: + TU_VERIFY (ncm_interface.itf_num == request->wIndex); + + if (0x80 /* GET_NTB_PARAMETERS */ == request->bRequest) + { + tud_control_xfer(rhport, request, (void*)&ntb_parameters, sizeof(ntb_parameters)); + } + + break; + + // unsupported request + default: return false; + } + + return true; +} + +static void handle_incoming_datagram(uint32_t len) +{ + uint32_t size = len; + + if (len == 0) { + return; + } + + TU_ASSERT(size >= sizeof(nth16_t), ); + + const nth16_t *hdr = (const nth16_t *)receive_ntb; + TU_ASSERT(hdr->dwSignature == NTH16_SIGNATURE, ); + TU_ASSERT(hdr->wNdpIndex >= sizeof(nth16_t) && (hdr->wNdpIndex + sizeof(ndp16_t)) <= len, ); + + const ndp16_t *ndp = (const ndp16_t *)(receive_ntb + hdr->wNdpIndex); + TU_ASSERT(ndp->dwSignature == NDP16_SIGNATURE_NCM0 || ndp->dwSignature == NDP16_SIGNATURE_NCM1, ); + TU_ASSERT(hdr->wNdpIndex + ndp->wLength <= len, ); + + int num_datagrams = (ndp->wLength - 12) / 4; + ncm_interface.current_datagram_index = 0; + ncm_interface.num_datagrams = 0; + ncm_interface.ndp = ndp; + for (int i = 0; i < num_datagrams && ndp->datagram[i].wDatagramIndex && ndp->datagram[i].wDatagramLength; i++) + ncm_interface.num_datagrams++; + + tud_network_recv_renew(); +} + +bool netd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) +{ + (void) rhport; + (void) result; + + /* new datagram receive_ntb */ + if (ep_addr == ncm_interface.ep_out ) + { + handle_incoming_datagram(xferred_bytes); + } + + /* data transmission finished */ + if (ep_addr == ncm_interface.ep_in ) + { + if (ncm_interface.transferring) { + ncm_interface.transferring = false; + } + + // If there are datagrams queued up that we tried to send while this NTB was being emitted, send them now + if (ncm_interface.datagram_count && ncm_interface.itf_data_alt == 1) { + ncm_start_tx(); + } + } + + if (ep_addr == ncm_interface.ep_notif ) + { + ncm_interface.report_pending = false; + ncm_report(); + } + + return true; +} + +// poll network driver for its ability to accept another packet to transmit +bool tud_network_can_xmit(uint16_t size) +{ + TU_VERIFY(ncm_interface.itf_data_alt == 1); + + if (ncm_interface.datagram_count >= ncm_interface.max_datagrams_per_ntb) { + TU_LOG2("NTB full [by count]\r\n"); + return false; + } + + size_t next_datagram_offset = ncm_interface.next_datagram_offset; + if (next_datagram_offset + size > ncm_interface.ntb_in_size) { + TU_LOG2("ntb full [by size]\r\n"); + return false; + } + + return true; +} + +void tud_network_xmit(void *ref, uint16_t arg) +{ + transmit_ntb_t *ntb = &transmit_ntb[ncm_interface.current_ntb]; + size_t next_datagram_offset = ncm_interface.next_datagram_offset; + + uint16_t size = tud_network_xmit_cb(ntb->data + next_datagram_offset, ref, arg); + + ntb->ndp.datagram[ncm_interface.datagram_count].wDatagramIndex = ncm_interface.next_datagram_offset; + ntb->ndp.datagram[ncm_interface.datagram_count].wDatagramLength = size; + + ncm_interface.datagram_count++; + next_datagram_offset += size; + + // round up so the next datagram is aligned correctly + next_datagram_offset += (CFG_TUD_NCM_ALIGNMENT - 1); + next_datagram_offset -= (next_datagram_offset % CFG_TUD_NCM_ALIGNMENT); + + ncm_interface.next_datagram_offset = next_datagram_offset; + + ncm_start_tx(); +} + +#endif diff --git a/src/class/net/net_device.c b/src/class/net/net_device.c deleted file mode 100644 index 9d9719ce4..000000000 --- a/src/class/net/net_device.c +++ /dev/null @@ -1,441 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2020 Peter Lawrence - * Copyright (c) 2019 Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#include "tusb_option.h" - -#if ( TUSB_OPT_DEVICE_ENABLED && CFG_TUD_NET ) - -#include "device/usbd.h" -#include "device/usbd_pvt.h" - -#include "net_device.h" -#include "rndis_protocol.h" - -void rndis_class_set_handler(uint8_t *data, int size); /* found in ./misc/networking/rndis_reports.c */ - -//--------------------------------------------------------------------+ -// MACRO CONSTANT TYPEDEF -//--------------------------------------------------------------------+ -typedef struct -{ - uint8_t itf_num; // Index number of Management Interface, +1 for Data Interface - uint8_t itf_data_alt; // Alternate setting of Data Interface. 0 : inactive, 1 : active - - uint8_t ep_notif; - uint8_t ep_in; - uint8_t ep_out; - - bool ecm_mode; - - // Endpoint descriptor use to open/close when receving SetInterface - // TODO since configuration descriptor may not be long-lived memory, we should - // keep a copy of endpoint attribute instead - uint8_t const * ecm_desc_epdata; - -} netd_interface_t; - -#define CFG_TUD_NET_PACKET_PREFIX_LEN sizeof(rndis_data_packet_t) -#define CFG_TUD_NET_PACKET_SUFFIX_LEN 0 - -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t received[CFG_TUD_NET_PACKET_PREFIX_LEN + CFG_TUD_NET_MTU + CFG_TUD_NET_PACKET_PREFIX_LEN]; -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t transmitted[CFG_TUD_NET_PACKET_PREFIX_LEN + CFG_TUD_NET_MTU + CFG_TUD_NET_PACKET_PREFIX_LEN]; - -struct ecm_notify_struct -{ - tusb_control_request_t header; - uint32_t downlink, uplink; -}; - -static const struct ecm_notify_struct ecm_notify_nc = -{ - .header = { - .bmRequestType = 0xA1, - .bRequest = 0 /* NETWORK_CONNECTION aka NetworkConnection */, - .wValue = 1 /* Connected */, - .wLength = 0, - }, -}; - -static const struct ecm_notify_struct ecm_notify_csc = -{ - .header = { - .bmRequestType = 0xA1, - .bRequest = 0x2A /* CONNECTION_SPEED_CHANGE aka ConnectionSpeedChange */, - .wLength = 8, - }, - .downlink = 9728000, - .uplink = 9728000, -}; - -// TODO remove CFG_TUSB_MEM_SECTION, control internal buffer is already in this special section -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static union -{ - uint8_t rndis_buf[120]; - struct ecm_notify_struct ecm_buf; -} notify; - -//--------------------------------------------------------------------+ -// INTERNAL OBJECT & FUNCTION DECLARATION -//--------------------------------------------------------------------+ -// TODO remove CFG_TUSB_MEM_SECTION -CFG_TUSB_MEM_SECTION static netd_interface_t _netd_itf; - -static bool can_xmit; - -void tud_network_recv_renew(void) -{ - usbd_edpt_xfer(TUD_OPT_RHPORT, _netd_itf.ep_out, received, sizeof(received)); -} - -static void do_in_xfer(uint8_t *buf, uint16_t len) -{ - can_xmit = false; - usbd_edpt_xfer(TUD_OPT_RHPORT, _netd_itf.ep_in, buf, len); -} - -void netd_report(uint8_t *buf, uint16_t len) -{ - usbd_edpt_xfer(TUD_OPT_RHPORT, _netd_itf.ep_notif, buf, len); -} - -//--------------------------------------------------------------------+ -// USBD Driver API -//--------------------------------------------------------------------+ -void netd_init(void) -{ - tu_memclr(&_netd_itf, sizeof(_netd_itf)); -} - -void netd_reset(uint8_t rhport) -{ - (void) rhport; - - netd_init(); -} - -uint16_t netd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len) -{ - bool const is_rndis = (TUD_RNDIS_ITF_CLASS == itf_desc->bInterfaceClass && - TUD_RNDIS_ITF_SUBCLASS == itf_desc->bInterfaceSubClass && - TUD_RNDIS_ITF_PROTOCOL == itf_desc->bInterfaceProtocol); - - bool const is_ecm = (TUSB_CLASS_CDC == itf_desc->bInterfaceClass && - CDC_COMM_SUBCLASS_ETHERNET_CONTROL_MODEL == itf_desc->bInterfaceSubClass && - 0x00 == itf_desc->bInterfaceProtocol); - - TU_VERIFY(is_rndis || is_ecm, 0); - - // confirm interface hasn't already been allocated - TU_ASSERT(0 == _netd_itf.ep_notif, 0); - - // sanity check the descriptor - _netd_itf.ecm_mode = is_ecm; - - //------------- Management Interface -------------// - _netd_itf.itf_num = itf_desc->bInterfaceNumber; - - uint16_t drv_len = sizeof(tusb_desc_interface_t); - uint8_t const * p_desc = tu_desc_next( itf_desc ); - - // Communication Functional Descriptors - while ( TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc) && drv_len <= max_len ) - { - drv_len += tu_desc_len(p_desc); - p_desc = tu_desc_next(p_desc); - } - - // notification endpoint (if any) - if ( TUSB_DESC_ENDPOINT == tu_desc_type(p_desc) ) - { - TU_ASSERT( usbd_edpt_open(rhport, (tusb_desc_endpoint_t const *) p_desc), 0 ); - - _netd_itf.ep_notif = ((tusb_desc_endpoint_t const *) p_desc)->bEndpointAddress; - - drv_len += tu_desc_len(p_desc); - p_desc = tu_desc_next(p_desc); - } - - //------------- Data Interface -------------// - // - RNDIS Data followed immediately by a pair of endpoints - // - CDC-ECM data interface has 2 alternate settings - // - 0 : zero endpoints for inactive (default) - // - 1 : IN & OUT endpoints for active networking - TU_ASSERT(TUSB_DESC_INTERFACE == tu_desc_type(p_desc), 0); - - do - { - tusb_desc_interface_t const * data_itf_desc = (tusb_desc_interface_t const *) p_desc; - TU_ASSERT(TUSB_CLASS_CDC_DATA == data_itf_desc->bInterfaceClass, 0); - - drv_len += tu_desc_len(p_desc); - p_desc = tu_desc_next(p_desc); - }while( _netd_itf.ecm_mode && (TUSB_DESC_INTERFACE == tu_desc_type(p_desc)) && (drv_len <= max_len) ); - - // Pair of endpoints - TU_ASSERT(TUSB_DESC_ENDPOINT == tu_desc_type(p_desc), 0); - - if ( _netd_itf.ecm_mode ) - { - // ECM by default is in-active, save the endpoint attribute - // to open later when received setInterface - _netd_itf.ecm_desc_epdata = p_desc; - }else - { - // Open endpoint pair for RNDIS - TU_ASSERT( usbd_open_edpt_pair(rhport, p_desc, 2, TUSB_XFER_BULK, &_netd_itf.ep_out, &_netd_itf.ep_in), 0 ); - - tud_network_init_cb(); - - // we are ready to transmit a packet - can_xmit = true; - - // prepare for incoming packets - tud_network_recv_renew(); - } - - drv_len += 2*sizeof(tusb_desc_endpoint_t); - - return drv_len; -} - -static void ecm_report(bool nc) -{ - notify.ecm_buf = (nc) ? ecm_notify_nc : ecm_notify_csc; - notify.ecm_buf.header.wIndex = _netd_itf.itf_num; - netd_report((uint8_t *)¬ify.ecm_buf, (nc) ? sizeof(notify.ecm_buf.header) : sizeof(notify.ecm_buf)); -} - -// Invoked when a control transfer occurred on an interface of this class -// Driver response accordingly to the request and the transfer stage (setup/data/ack) -// return false to stall control endpoint (e.g unsupported request) -bool netd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t const * request) -{ - if ( stage == CONTROL_STAGE_SETUP ) - { - switch ( request->bmRequestType_bit.type ) - { - case TUSB_REQ_TYPE_STANDARD: - switch ( request->bRequest ) - { - case TUSB_REQ_GET_INTERFACE: - { - uint8_t const req_itfnum = (uint8_t) request->wIndex; - TU_VERIFY(_netd_itf.itf_num+1 == req_itfnum); - - tud_control_xfer(rhport, request, &_netd_itf.itf_data_alt, 1); - } - break; - - case TUSB_REQ_SET_INTERFACE: - { - uint8_t const req_itfnum = (uint8_t) request->wIndex; - uint8_t const req_alt = (uint8_t) request->wValue; - - // Only valid for Data Interface with Alternate is either 0 or 1 - TU_VERIFY(_netd_itf.itf_num+1 == req_itfnum && req_alt < 2); - - // ACM-ECM only: qequest to enable/disable network activities - TU_VERIFY(_netd_itf.ecm_mode); - - _netd_itf.itf_data_alt = req_alt; - - if ( _netd_itf.itf_data_alt ) - { - // TODO since we don't actually close endpoint - // hack here to not re-open it - if ( _netd_itf.ep_in == 0 && _netd_itf.ep_out == 0 ) - { - TU_ASSERT(_netd_itf.ecm_desc_epdata); - TU_ASSERT( usbd_open_edpt_pair(rhport, _netd_itf.ecm_desc_epdata, 2, TUSB_XFER_BULK, &_netd_itf.ep_out, &_netd_itf.ep_in) ); - - // TODO should be merge with RNDIS's after endpoint opened - // Also should have opposite callback for application to disable network !! - tud_network_init_cb(); - can_xmit = true; // we are ready to transmit a packet - tud_network_recv_renew(); // prepare for incoming packets - } - }else - { - // TODO close the endpoint pair - // For now pretend that we did, this should have no harm since host won't try to - // communicate with the endpoints again - // _netd_itf.ep_in = _netd_itf.ep_out = 0 - } - - tud_control_status(rhport, request); - } - break; - - // unsupported request - default: return false; - } - break; - - case TUSB_REQ_TYPE_CLASS: - TU_VERIFY (_netd_itf.itf_num == request->wIndex); - - if (_netd_itf.ecm_mode) - { - /* the only required CDC-ECM Management Element Request is SetEthernetPacketFilter */ - if (0x43 /* SET_ETHERNET_PACKET_FILTER */ == request->bRequest) - { - tud_control_xfer(rhport, request, NULL, 0); - ecm_report(true); - } - } - else - { - if (request->bmRequestType_bit.direction == TUSB_DIR_IN) - { - rndis_generic_msg_t *rndis_msg = (rndis_generic_msg_t *) ((void*) notify.rndis_buf); - uint32_t msglen = tu_le32toh(rndis_msg->MessageLength); - TU_ASSERT(msglen <= sizeof(notify.rndis_buf)); - tud_control_xfer(rhport, request, notify.rndis_buf, msglen); - } - else - { - tud_control_xfer(rhport, request, notify.rndis_buf, sizeof(notify.rndis_buf)); - } - } - break; - - // unsupported request - default: return false; - } - } - else if ( stage == CONTROL_STAGE_DATA ) - { - // Handle RNDIS class control OUT only - if (request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS && - request->bmRequestType_bit.direction == TUSB_DIR_OUT && - _netd_itf.itf_num == request->wIndex) - { - if ( !_netd_itf.ecm_mode ) - { - rndis_class_set_handler(notify.rndis_buf, request->wLength); - } - } - } - - return true; -} - -static void handle_incoming_packet(uint32_t len) -{ - uint8_t *pnt = received; - uint32_t size = 0; - - if (_netd_itf.ecm_mode) - { - size = len; - } - else - { - rndis_data_packet_t *r = (rndis_data_packet_t *) ((void*) pnt); - if (len >= sizeof(rndis_data_packet_t)) - if ( (r->MessageType == REMOTE_NDIS_PACKET_MSG) && (r->MessageLength <= len)) - if ( (r->DataOffset + offsetof(rndis_data_packet_t, DataOffset) + r->DataLength) <= len) - { - pnt = &received[r->DataOffset + offsetof(rndis_data_packet_t, DataOffset)]; - size = r->DataLength; - } - } - - if (!tud_network_recv_cb(pnt, size)) - { - /* if a buffer was never handled by user code, we must renew on the user's behalf */ - tud_network_recv_renew(); - } -} - -bool netd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) -{ - (void) rhport; - (void) result; - - /* new packet received */ - if ( ep_addr == _netd_itf.ep_out ) - { - handle_incoming_packet(xferred_bytes); - } - - /* data transmission finished */ - if ( ep_addr == _netd_itf.ep_in ) - { - /* TinyUSB requires the class driver to implement ZLP (since ZLP usage is class-specific) */ - - if ( xferred_bytes && (0 == (xferred_bytes % CFG_TUD_NET_ENDPOINT_SIZE)) ) - { - do_in_xfer(NULL, 0); /* a ZLP is needed */ - } - else - { - /* we're finally finished */ - can_xmit = true; - } - } - - if ( _netd_itf.ecm_mode && (ep_addr == _netd_itf.ep_notif) ) - { - if (sizeof(notify.ecm_buf.header) == xferred_bytes) ecm_report(false); - } - - return true; -} - -bool tud_network_can_xmit(void) -{ - return can_xmit; -} - -void tud_network_xmit(void *ref, uint16_t arg) -{ - uint8_t *data; - uint16_t len; - - if (!can_xmit) - return; - - len = (_netd_itf.ecm_mode) ? 0 : CFG_TUD_NET_PACKET_PREFIX_LEN; - data = transmitted + len; - - len += tud_network_xmit_cb(data, ref, arg); - - if (!_netd_itf.ecm_mode) - { - rndis_data_packet_t *hdr = (rndis_data_packet_t *) ((void*) transmitted); - memset(hdr, 0, sizeof(rndis_data_packet_t)); - hdr->MessageType = REMOTE_NDIS_PACKET_MSG; - hdr->MessageLength = len; - hdr->DataOffset = sizeof(rndis_data_packet_t) - offsetof(rndis_data_packet_t, DataOffset); - hdr->DataLength = len - sizeof(rndis_data_packet_t); - } - - do_in_xfer(transmitted, len); -} - -#endif diff --git a/src/class/net/net_device.h b/src/class/net/net_device.h index f030f3077..e6cdc8b8b 100644 --- a/src/class/net/net_device.h +++ b/src/class/net/net_device.h @@ -38,6 +38,22 @@ #define CFG_TUD_NET_MTU 1514 #endif +#ifndef CFG_TUD_NCM_IN_NTB_MAX_SIZE +#define CFG_TUD_NCM_IN_NTB_MAX_SIZE 3200 +#endif + +#ifndef CFG_TUD_NCM_OUT_NTB_MAX_SIZE +#define CFG_TUD_NCM_OUT_NTB_MAX_SIZE 3200 +#endif + +#ifndef CFG_TUD_NCM_MAX_DATAGRAMS_PER_NTB +#define CFG_TUD_NCM_MAX_DATAGRAMS_PER_NTB 8 +#endif + +#ifndef CFG_TUD_NCM_ALIGNMENT +#define CFG_TUD_NCM_ALIGNMENT 4 +#endif + #ifdef __cplusplus extern "C" { #endif @@ -63,11 +79,14 @@ extern const uint8_t tud_network_mac_address[6]; void tud_network_recv_renew(void); // poll network driver for its ability to accept another packet to transmit -bool tud_network_can_xmit(void); +bool tud_network_can_xmit(uint16_t size); // if network_can_xmit() returns true, network_xmit() can be called once void tud_network_xmit(void *ref, uint16_t arg); +// callback to client providing optional indication of internal state of network driver +void tud_network_link_state_cb(bool state); + //--------------------------------------------------------------------+ // INTERNAL USBD-CLASS DRIVER API //--------------------------------------------------------------------+ diff --git a/src/device/usbd.h b/src/device/usbd.h index 638d93094..200e1cca1 100644 --- a/src/device/usbd.h +++ b/src/device/usbd.h @@ -781,6 +781,37 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb TUD_BTH_PRI_ITF(_itfnum, _stridx, _ep_evt, _ep_evt_size, _ep_evt_interval, _ep_in, _ep_out, _ep_size) \ TUD_BTH_ISO_ITFS(_itfnum + 1, _ep_in + 1, _ep_out + 1, __VA_ARGS__) +//------------- CDC-NCM -------------// + +// Length of template descriptor +#define TUD_CDC_NCM_DESC_LEN (8+9+5+5+13+6+7+9+9+7+7) + +// CDC-ECM Descriptor Template +// Interface number, description string index, MAC address string index, EP notification address and size, EP data address (out, in), and size, max segment size. +#define TUD_CDC_NCM_DESCRIPTOR(_itfnum, _desc_stridx, _mac_stridx, _ep_notif, _ep_notif_size, _epout, _epin, _epsize, _maxsegmentsize) \ + /* Interface Association */\ + 8, TUSB_DESC_INTERFACE_ASSOCIATION, _itfnum, 2, TUSB_CLASS_CDC, CDC_COMM_SUBCLASS_NETWORK_CONTROL_MODEL, 0, 0,\ + /* CDC Control Interface */\ + 9, TUSB_DESC_INTERFACE, _itfnum, 0, 1, TUSB_CLASS_CDC, CDC_COMM_SUBCLASS_NETWORK_CONTROL_MODEL, 0, _desc_stridx,\ + /* CDC-NCM Header */\ + 5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_HEADER, U16_TO_U8S_LE(0x0110),\ + /* CDC-NCM Union */\ + 5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_UNION, _itfnum, (uint8_t)((_itfnum) + 1),\ + /* CDC-ECM Functional Descriptor */\ + 13, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_ETHERNET_NETWORKING, _mac_stridx, 0, 0, 0, 0, U16_TO_U8S_LE(_maxsegmentsize), U16_TO_U8S_LE(0), 0, \ + /* CDC-ECM Functional Descriptor */\ + 6, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_NCM, U16_TO_U8S_LE(0x0100), 0, \ + /* Endpoint Notification */\ + 7, TUSB_DESC_ENDPOINT, _ep_notif, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_ep_notif_size), 50,\ + /* CDC Data Interface (default inactive) */\ + 9, TUSB_DESC_INTERFACE, (uint8_t)((_itfnum)+1), 0, 0, TUSB_CLASS_CDC_DATA, 0, 1, 0,\ + /* CDC Data Interface (alternative active) */\ + 9, TUSB_DESC_INTERFACE, (uint8_t)((_itfnum)+1), 1, 2, TUSB_CLASS_CDC_DATA, 0, 1, 0,\ + /* Endpoint In */\ + 7, TUSB_DESC_ENDPOINT, _epin, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0,\ + /* Endpoint Out */\ + 7, TUSB_DESC_ENDPOINT, _epout, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0 + #ifdef __cplusplus } #endif diff --git a/src/tusb_option.h b/src/tusb_option.h index ad2a26a66..12aab82fc 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -269,6 +269,10 @@ #define CFG_TUD_BTH 0 #endif +#ifndef CFG_TUD_NCM + #define CFG_TUD_NCM 0 +#endif + //-------------------------------------------------------------------- // HOST OPTIONS //-------------------------------------------------------------------- -- cgit v1.3.1 From fba5ec813423b3e3e0f08c5c54e40143a9632e4e Mon Sep 17 00:00:00 2001 From: hathach Date: Sun, 26 Sep 2021 12:23:08 +0700 Subject: make freertos header include in examples more explicit --- examples/device/cdc_msc_freertos/src/main.c | 22 +++++++++++++++------- examples/device/hid_composite_freertos/src/main.c | 22 +++++++++++++++------- 2 files changed, 30 insertions(+), 14 deletions(-) diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c index af00b3cc2..65b7fda3b 100644 --- a/examples/device/cdc_msc_freertos/src/main.c +++ b/examples/device/cdc_msc_freertos/src/main.c @@ -30,13 +30,21 @@ #include "bsp/board.h" #include "tusb.h" -// FreeRTOS headers, MCUs such as esp32sx requires "freertos/" prefix in include path. -// CFG_TUSB_OS_INC_PATH should be defined accordingly. -#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,FreeRTOS.h) -#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,semphr.h) -#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,queue.h) -#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,task.h) -#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,timers.h) +#if TU_CHECK_MCU(ESP32S2) || TU_CHECK_MCU(ESP32S3) + // ESP-IDF need "freertos/" prefix in include path. + // CFG_TUSB_OS_INC_PATH should be defined accordingly. + #include "freertos/FreeRTOS.h" + #include "freertos/semphr.h" + #include "freertos/queue.h" + #include "freertos/task.h" + #include "freertos/timers.h" +#else + #include "FreeRTOS.h" + #include "semphr.h" + #include "queue.h" + #include "task.h" + #include "timers.h" +#endif //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF PROTYPES diff --git a/examples/device/hid_composite_freertos/src/main.c b/examples/device/hid_composite_freertos/src/main.c index 8a184f60f..b25c71f64 100644 --- a/examples/device/hid_composite_freertos/src/main.c +++ b/examples/device/hid_composite_freertos/src/main.c @@ -31,13 +31,21 @@ #include "tusb.h" #include "usb_descriptors.h" -// FreeRTOS headers, MCUs such as esp32sx requires "freertos/" prefix in include path. -// CFG_TUSB_OS_INC_PATH should be defined accordingly. -#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,FreeRTOS.h) -#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,semphr.h) -#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,queue.h) -#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,task.h) -#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,timers.h) +#if TU_CHECK_MCU(ESP32S2) || TU_CHECK_MCU(ESP32S3) + // ESP-IDF need "freertos/" prefix in include path. + // CFG_TUSB_OS_INC_PATH should be defined accordingly. + #include "freertos/FreeRTOS.h" + #include "freertos/semphr.h" + #include "freertos/queue.h" + #include "freertos/task.h" + #include "freertos/timers.h" +#else + #include "FreeRTOS.h" + #include "semphr.h" + #include "queue.h" + #include "task.h" + #include "timers.h" +#endif //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF PROTYPES -- cgit v1.3.1 From 196a0da813ced4f13f04a3062873b352bc728d6d Mon Sep 17 00:00:00 2001 From: Hans Baier Date: Mon, 27 Sep 2021 05:58:58 +0700 Subject: add support for the QMTech ATMSAME70N19A board --- hw/bsp/same70_qmtech/board.mk | 56 + hw/bsp/same70_qmtech/hpl_pmc_config.h | 1053 ++++++ hw/bsp/same70_qmtech/hpl_usart_config.h | 215 ++ hw/bsp/same70_qmtech/hpl_xdmac_config.h | 4400 ++++++++++++++++++++++++++ hw/bsp/same70_qmtech/peripheral_clk_config.h | 126 + hw/bsp/same70_qmtech/same70_qmtech.c | 159 + 6 files changed, 6009 insertions(+) create mode 100644 hw/bsp/same70_qmtech/board.mk create mode 100644 hw/bsp/same70_qmtech/hpl_pmc_config.h create mode 100644 hw/bsp/same70_qmtech/hpl_usart_config.h create mode 100644 hw/bsp/same70_qmtech/hpl_xdmac_config.h create mode 100644 hw/bsp/same70_qmtech/peripheral_clk_config.h create mode 100644 hw/bsp/same70_qmtech/same70_qmtech.c diff --git a/hw/bsp/same70_qmtech/board.mk b/hw/bsp/same70_qmtech/board.mk new file mode 100644 index 000000000..6c84810f3 --- /dev/null +++ b/hw/bsp/same70_qmtech/board.mk @@ -0,0 +1,56 @@ +DEPS_SUBMODULES += hw/mcu/microchip + +CFLAGS += \ + -mthumb \ + -mabi=aapcs \ + -mcpu=cortex-m7 \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -nostdlib -nostartfiles \ + -D__SAME70N19B__ \ + -DCFG_TUSB_MCU=OPT_MCU_SAMX7X + +# suppress following warnings from mcu driver +CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align + +ASF_DIR = hw/mcu/microchip/same70 + +# All source paths should be relative to the top level. +LD_FILE = $(ASF_DIR)/same70b/gcc/gcc/same70q21b_flash.ld + +SRC_C += \ + src/portable/microchip/samx7x/dcd_samx7x.c \ + $(ASF_DIR)/same70b/gcc/gcc/startup_same70q21b.c \ + $(ASF_DIR)/same70b/gcc/system_same70q21b.c \ + $(ASF_DIR)/hpl/core/hpl_init.c \ + $(ASF_DIR)/hpl/usart/hpl_usart.c \ + $(ASF_DIR)/hpl/pmc/hpl_pmc.c \ + $(ASF_DIR)/hal/src/hal_usart_async.c \ + $(ASF_DIR)/hal/src/hal_io.c \ + $(ASF_DIR)/hal/src/hal_atomic.c \ + $(ASF_DIR)/hal/utils/src/utils_ringbuffer.c + +INC += \ + $(TOP)/hw/bsp/$(BOARD) \ + $(TOP)/$(ASF_DIR) \ + $(TOP)/$(ASF_DIR)/config \ + $(TOP)/$(ASF_DIR)/same70b/include \ + $(TOP)/$(ASF_DIR)/hal/include \ + $(TOP)/$(ASF_DIR)/hal/utils/include \ + $(TOP)/$(ASF_DIR)/hpl/core \ + $(TOP)/$(ASF_DIR)/hpl/pio \ + $(TOP)/$(ASF_DIR)/hpl/pmc \ + $(TOP)/$(ASF_DIR)/hri \ + $(TOP)/$(ASF_DIR)/CMSIS/Core/Include + +# For freeRTOS port source +FREERTOS_PORT = ARM_CM7 + +# For flash-jlink target +JLINK_DEVICE = SAME70N19B + +# flash using edbg from https://github.com/ataradov/edbg +# Note: SAME70's GPNVM1 must be set to 1 to boot from flash with +# edbg -t same70 -F w0,1,1 +flash: $(BUILD)/$(PROJECT).bin + edbg --verbose -t same70 -pv -f $< diff --git a/hw/bsp/same70_qmtech/hpl_pmc_config.h b/hw/bsp/same70_qmtech/hpl_pmc_config.h new file mode 100644 index 000000000..387aaa5df --- /dev/null +++ b/hw/bsp/same70_qmtech/hpl_pmc_config.h @@ -0,0 +1,1053 @@ +/* Auto-generated config file hpl_pmc_config.h */ +#ifndef HPL_PMC_CONFIG_H +#define HPL_PMC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#include + +#define CLK_SRC_OPTION_OSC32K 0 +#define CLK_SRC_OPTION_XOSC32K 1 +#define CLK_SRC_OPTION_OSC12M 2 +#define CLK_SRC_OPTION_XOSC20M 3 + +#define CLK_SRC_OPTION_SLCK 0 +#define CLK_SRC_OPTION_MAINCK 1 +#define CLK_SRC_OPTION_PLLACK 2 +#define CLK_SRC_OPTION_UPLLCKDIV 3 +#define CLK_SRC_OPTION_MCK 4 + +#define CLK_SRC_OPTION_UPLLCK 3 + +#define CONF_RC_4M 0 +#define CONF_RC_8M 1 +#define CONF_RC_12M 2 + +#define CONF_XOSC32K_NO_BYPASS 0 +#define CONF_XOSC32K_BYPASS 1 + +#define CONF_XOSC20M_NO_BYPASS 0 +#define CONF_XOSC20M_BYPASS 1 + +// Clock_SLCK configuration +// Indicates whether SLCK configuration is enabled or not +// enable_clk_gen_slck +#ifndef CONF_CLK_SLCK_CONFIG +#define CONF_CLK_SLCK_CONFIG 1 +#endif + +// Clock Generator +// clock generator SLCK source + +// 32kHz High Accuracy Internal Oscillator (OSC32K) + +// 32kHz External Crystal Oscillator (XOSC32K) + +// This defines the clock source for SLCK +// clk_gen_slck_oscillator +#ifndef CONF_CLK_GEN_SLCK_SRC +#define CONF_CLK_GEN_SLCK_SRC CLK_SRC_OPTION_OSC32K +#endif + +// Enable Clock_SLCK +// Indicates whether SLCK is enabled or disable +// clk_gen_slck_arch_enable +#ifndef CONF_CLK_SLCK_ENABLE +#define CONF_CLK_SLCK_ENABLE 1 +#endif + +// + +// + +// +// // Clock_MAINCK configuration +// Indicates whether MAINCK configuration is enabled or not +// enable_clk_gen_mainck +#ifndef CONF_CLK_MAINCK_CONFIG +#define CONF_CLK_MAINCK_CONFIG 1 +#endif + +// Clock Generator +// clock generator MAINCK source + +// Embedded 4/8/12MHz RC Oscillator (OSC12M) + +// External 3-20MHz Oscillator (XOSC20M) + +// This defines the clock source for MAINCK +// clk_gen_mainck_oscillator +#ifndef CONF_CLK_GEN_MAINCK_SRC +#define CONF_CLK_GEN_MAINCK_SRC CLK_SRC_OPTION_XOSC20M +#endif + +// Enable Clock_MAINCK +// Indicates whether MAINCK is enabled or disable +// clk_gen_mainck_arch_enable +#ifndef CONF_CLK_MAINCK_ENABLE +#define CONF_CLK_MAINCK_ENABLE 1 +#endif + +// Enable Main Clock Failure Detection +// Indicates whether Main Clock Failure Detection is enabled or disable. +// The 4/8/12 MHz RC oscillator must be selected as the source of MAINCK. +// clk_gen_cfden_enable +#ifndef CONF_CLK_CFDEN_ENABLE +#define CONF_CLK_CFDEN_ENABLE 0 +#endif + +// + +// + +// +// // Clock_MCKR configuration +// Indicates whether MCKR configuration is enabled or not +// enable_clk_gen_mckr +#ifndef CONF_CLK_MCKR_CONFIG +#define CONF_CLK_MCKR_CONFIG 1 +#endif + +// Clock Generator +// clock generator MCKR source + +// Slow Clock (SLCK) + +// Main Clock (MAINCK) + +// PLLA Clock (PLLACK) + +// UDPLL with Divider (MCKR UPLLDIV2) + +// This defines the clock source for MCKR +// clk_gen_mckr_oscillator +#ifndef CONF_CLK_GEN_MCKR_SRC +#define CONF_CLK_GEN_MCKR_SRC CLK_SRC_OPTION_PLLACK +#endif + +// Enable Clock_MCKR +// Indicates whether MCKR is enabled or disable +// clk_gen_mckr_arch_enable +#ifndef CONF_CLK_MCKR_ENABLE +#define CONF_CLK_MCKR_ENABLE 1 +#endif + +// + +// + +// Master Clock Prescaler +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <4=> 16 +// <5=> 32 +// <6=> 64 +// <7=> 3 +// Select the clock prescaler. +// mckr_presc +#ifndef CONF_MCKR_PRESC +#define CONF_MCKR_PRESC 0 +#endif + +// +// // Clock_MCK configuration +// Indicates whether MCK configuration is enabled or not +// enable_clk_gen_mck +#ifndef CONF_CLK_MCK_CONFIG +#define CONF_CLK_MCK_CONFIG 1 +#endif + +// Clock Generator +// clock generator MCK source + +// Master Clock Controller (PMC_MCKR) + +// This defines the clock source for MCK +// clk_gen_mck_oscillator +#ifndef CONF_CLK_GEN_MCK_SRC +#define CONF_CLK_GEN_MCK_SRC CLK_SRC_OPTION_MCKR +#endif + +// + +// + +// Master Clock Controller Divider MCK divider +// <0=> 1 +// <1=> 2 +// <3=> 3 +// <2=> 4 +// Select the master clock divider. +// mck_div +#ifndef CONF_MCK_DIV +#define CONF_MCK_DIV 1 +#endif + +// +// // Clock_SYSTICK configuration +// Indicates whether SYSTICK configuration is enabled or not +// enable_clk_gen_systick +#ifndef CONF_CLK_SYSTICK_CONFIG +#define CONF_CLK_SYSTICK_CONFIG 1 +#endif + +// Clock Generator +// clock generator SYSTICK source + +// Master Clock Controller (PMC_MCKR) + +// This defines the clock source for SYSTICK +// clk_gen_systick_oscillator +#ifndef CONF_CLK_GEN_SYSTICK_SRC +#define CONF_CLK_GEN_SYSTICK_SRC CLK_SRC_OPTION_MCKR +#endif + +// + +// + +// Systick clock divider +// <8=> 8 +// Select systick clock divider +// systick_clock_div +#ifndef CONF_SYSTICK_DIV +#define CONF_SYSTICK_DIV 8 +#endif + +// +// // Clock_FCLK configuration +// Indicates whether FCLK configuration is enabled or not +// enable_clk_gen_fclk +#ifndef CONF_CLK_FCLK_CONFIG +#define CONF_CLK_FCLK_CONFIG 1 +#endif + +// Clock Generator +// clock generator FCLK source + +// Master Clock Controller (PMC_MCKR) + +// This defines the clock source for FCLK +// clk_gen_fclk_oscillator +#ifndef CONF_CLK_GEN_FCLK_SRC +#define CONF_CLK_GEN_FCLK_SRC CLK_SRC_OPTION_MCKR +#endif + +// + +// + +// +// // Clock_GCLK0 configuration +// Indicates whether GCLK0 configuration is enabled or not +// enable_clk_gen_gclk0 +#ifndef CONF_CLK_GCLK0_CONFIG +#define CONF_CLK_GCLK0_CONFIG 1 +#endif + +// Clock Generator +// clock generator GCLK0 source + +// Slow Clock (SLCK) + +// Main Clock (MAINCK) + +// USB 480M Clock (UPLLCK) + +// PLLA Clock (PLLACK) + +// Master Clock (MCK) + +// This defines the clock source for GCLK0 +// clk_gen_gclk0_oscillator +#ifndef CONF_CLK_GEN_GCLK0_SRC +#define CONF_CLK_GEN_GCLK0_SRC CLK_SRC_OPTION_MCK +#endif + +// Enable Clock_GCLK0 +// Indicates whether GCLK0 is enabled or disable +// clk_gen_gclk0_arch_enable +#ifndef CONF_CLK_GCLK0_ENABLE +#define CONF_CLK_GCLK0_ENABLE 1 +#endif + +// + +// +// Enable GCLK0 GCLKEN +// Indicates whether GCLK0 GCLKEN is enabled or disable +// gclk0_gclken_enable +#ifndef CONF_GCLK0_GCLKEN_ENABLE +#define CONF_GCLK0_GCLKEN_ENABLE 0 +#endif + +// Generic Clock GCLK0 divider <1-256> +// Select the clock divider (divider = GCLKDIV + 1). +// gclk0_div +#ifndef CONF_GCLK0_DIV +#define CONF_GCLK0_DIV 2 +#endif + +// +// // Clock_GCLK1 configuration +// Indicates whether GCLK1 configuration is enabled or not +// enable_clk_gen_gclk1 +#ifndef CONF_CLK_GCLK1_CONFIG +#define CONF_CLK_GCLK1_CONFIG 1 +#endif + +// Clock Generator +// clock generator GCLK1 source + +// Slow Clock (SLCK) + +// Main Clock (MAINCK) + +// USB 480M Clock (UPLLCK) + +// PLLA Clock (PLLACK) + +// Master Clock (MCK) + +// This defines the clock source for GCLK1 +// clk_gen_gclk1_oscillator +#ifndef CONF_CLK_GEN_GCLK1_SRC +#define CONF_CLK_GEN_GCLK1_SRC CLK_SRC_OPTION_PLLACK +#endif + +// Enable Clock_GCLK1 +// Indicates whether GCLK1 is enabled or disable +// clk_gen_gclk1_arch_enable +#ifndef CONF_CLK_GCLK1_ENABLE +#define CONF_CLK_GCLK1_ENABLE 1 +#endif + +// + +// +// Enable GCLK1 GCLKEN +// Indicates whether GCLK1 GCLKEN is enabled or disable +// gclk1_gclken_enable +#ifndef CONF_GCLK1_GCLKEN_ENABLE +#define CONF_GCLK1_GCLKEN_ENABLE 0 +#endif + +// Generic Clock GCLK1 divider <1-256> +// Select the clock divider (divider = GCLKDIV + 1). +// gclk1_div +#ifndef CONF_GCLK1_DIV +#define CONF_GCLK1_DIV 3 +#endif + +// +// // Clock_PCK0 configuration +// Indicates whether PCK0 configuration is enabled or not +// enable_clk_gen_pck0 +#ifndef CONF_CLK_PCK0_CONFIG +#define CONF_CLK_PCK0_CONFIG 1 +#endif + +// Clock Generator +// clock generator PCK0 source + +// Slow Clock (SLCK) + +// Main Clock (MAINCK) + +// UDPLL with Divider (MCKR UPLLDIV2) + +// PLLA Clock (PLLACK) + +// Master Clock (MCK) + +// This defines the clock source for PCK0 +// clk_gen_pck0_oscillator +#ifndef CONF_CLK_GEN_PCK0_SRC +#define CONF_CLK_GEN_PCK0_SRC CLK_SRC_OPTION_MAINCK +#endif + +// Enable Clock_PCK0 +// Indicates whether PCK0 is enabled or disable +// clk_gen_pck0_arch_enable +#ifndef CONF_CLK_PCK0_ENABLE +#define CONF_CLK_PCK0_ENABLE 0 +#endif + +// + +// + +// Programmable Clock Controller Prescaler <1-256> +// Select the clock prescaler (prescaler = PRESC + 1). +// pck0_presc +#ifndef CONF_PCK0_PRESC +#define CONF_PCK0_PRESC 1 +#endif + +// +// // Clock_PCK1 configuration +// Indicates whether PCK1 configuration is enabled or not +// enable_clk_gen_pck1 +#ifndef CONF_CLK_PCK1_CONFIG +#define CONF_CLK_PCK1_CONFIG 1 +#endif + +// Clock Generator +// clock generator PCK1 source + +// Slow Clock (SLCK) + +// Main Clock (MAINCK) + +// UDPLL with Divider (MCKR UPLLDIV2) + +// PLLA Clock (PLLACK) + +// Master Clock (MCK) + +// This defines the clock source for PCK1 +// clk_gen_pck1_oscillator +#ifndef CONF_CLK_GEN_PCK1_SRC +#define CONF_CLK_GEN_PCK1_SRC CLK_SRC_OPTION_MAINCK +#endif + +// Enable Clock_PCK1 +// Indicates whether PCK1 is enabled or disable +// clk_gen_pck1_arch_enable +#ifndef CONF_CLK_PCK1_ENABLE +#define CONF_CLK_PCK1_ENABLE 0 +#endif + +// + +// + +// Programmable Clock Controller Prescaler <1-256> +// Select the clock prescaler (prescaler = PRESC + 1). +// pck1_presc +#ifndef CONF_PCK1_PRESC +#define CONF_PCK1_PRESC 2 +#endif + +// +// // Clock_PCK2 configuration +// Indicates whether PCK2 configuration is enabled or not +// enable_clk_gen_pck2 +#ifndef CONF_CLK_PCK2_CONFIG +#define CONF_CLK_PCK2_CONFIG 1 +#endif + +// Clock Generator +// clock generator PCK2 source + +// Slow Clock (SLCK) + +// Main Clock (MAINCK) + +// UDPLL with Divider (MCKR UPLLDIV2) + +// PLLA Clock (PLLACK) + +// Master Clock (MCK) + +// This defines the clock source for PCK2 +// clk_gen_pck2_oscillator +#ifndef CONF_CLK_GEN_PCK2_SRC +#define CONF_CLK_GEN_PCK2_SRC CLK_SRC_OPTION_MAINCK +#endif + +// Enable Clock_PCK2 +// Indicates whether PCK2 is enabled or disable +// clk_gen_pck2_arch_enable +#ifndef CONF_CLK_PCK2_ENABLE +#define CONF_CLK_PCK2_ENABLE 0 +#endif + +// + +// + +// Programmable Clock Controller Prescaler <1-256> +// Select the clock prescaler (prescaler = PRESC + 1). +// pck2_presc +#ifndef CONF_PCK2_PRESC +#define CONF_PCK2_PRESC 3 +#endif + +// +// // Clock_PCK3 configuration +// Indicates whether PCK3 configuration is enabled or not +// enable_clk_gen_pck3 +#ifndef CONF_CLK_PCK3_CONFIG +#define CONF_CLK_PCK3_CONFIG 1 +#endif + +// Clock Generator +// clock generator PCK3 source + +// Slow Clock (SLCK) + +// Main Clock (MAINCK) + +// UDPLL with Divider (MCKR UPLLDIV2) + +// PLLA Clock (PLLACK) + +// Master Clock (MCK) + +// This defines the clock source for PCK3 +// clk_gen_pck3_oscillator +#ifndef CONF_CLK_GEN_PCK3_SRC +#define CONF_CLK_GEN_PCK3_SRC CLK_SRC_OPTION_MAINCK +#endif + +// Enable Clock_PCK3 +// Indicates whether PCK3 is enabled or disable +// clk_gen_pck3_arch_enable +#ifndef CONF_CLK_PCK3_ENABLE +#define CONF_CLK_PCK3_ENABLE 0 +#endif + +// + +// + +// Programmable Clock Controller Prescaler <1-256> +// Select the clock prescaler (prescaler = PRESC + 1). +// pck3_presc +#ifndef CONF_PCK3_PRESC +#define CONF_PCK3_PRESC 4 +#endif + +// +// // Clock_PCK4 configuration +// Indicates whether PCK4 configuration is enabled or not +// enable_clk_gen_pck4 +#ifndef CONF_CLK_PCK4_CONFIG +#define CONF_CLK_PCK4_CONFIG 1 +#endif + +// Clock Generator +// clock generator PCK4 source + +// Slow Clock (SLCK) + +// Main Clock (MAINCK) + +// UDPLL with Divider (MCKR UPLLDIV2) + +// PLLA Clock (PLLACK) + +// Master Clock (MCK) + +// This defines the clock source for PCK4 +// clk_gen_pck4_oscillator +#ifndef CONF_CLK_GEN_PCK4_SRC +#define CONF_CLK_GEN_PCK4_SRC CLK_SRC_OPTION_MAINCK +#endif + +// Enable Clock_PCK4 +// Indicates whether PCK4 is enabled or disable +// clk_gen_pck4_arch_enable +#ifndef CONF_CLK_PCK4_ENABLE +#define CONF_CLK_PCK4_ENABLE 0 +#endif + +// + +// + +// Programmable Clock Controller Prescaler <1-256> +// Select the clock prescaler (prescaler = PRESC + 1). +// pck4_presc +#ifndef CONF_PCK4_PRESC +#define CONF_PCK4_PRESC 5 +#endif + +// +// // Clock_PCK5 configuration +// Indicates whether PCK5 configuration is enabled or not +// enable_clk_gen_pck5 +#ifndef CONF_CLK_PCK5_CONFIG +#define CONF_CLK_PCK5_CONFIG 1 +#endif + +// Clock Generator +// clock generator PCK5 source + +// Slow Clock (SLCK) + +// Main Clock (MAINCK) + +// UDPLL with Divider (MCKR UPLLDIV2) + +// PLLA Clock (PLLACK) + +// Master Clock (MCK) + +// This defines the clock source for PCK5 +// clk_gen_pck5_oscillator +#ifndef CONF_CLK_GEN_PCK5_SRC +#define CONF_CLK_GEN_PCK5_SRC CLK_SRC_OPTION_MAINCK +#endif + +// Enable Clock_PCK5 +// Indicates whether PCK5 is enabled or disable +// clk_gen_pck5_arch_enable +#ifndef CONF_CLK_PCK5_ENABLE +#define CONF_CLK_PCK5_ENABLE 0 +#endif + +// + +// + +// Programmable Clock Controller Prescaler <1-256> +// Select the clock prescaler (prescaler = PRESC + 1). +// pck5_presc +#ifndef CONF_PCK5_PRESC +#define CONF_PCK5_PRESC 6 +#endif + +// +// // Clock_PCK6 configuration +// Indicates whether PCK6 configuration is enabled or not +// enable_clk_gen_pck6 +#ifndef CONF_CLK_PCK6_CONFIG +#define CONF_CLK_PCK6_CONFIG 1 +#endif + +// Clock Generator +// clock generator PCK6 source + +// Slow Clock (SLCK) + +// Main Clock (MAINCK) + +// UDPLL with Divider (MCKR UPLLDIV2) + +// PLLA Clock (PLLACK) + +// Master Clock (MCK) + +// This defines the clock source for PCK6 +// clk_gen_pck6_oscillator +#ifndef CONF_CLK_GEN_PCK6_SRC +#define CONF_CLK_GEN_PCK6_SRC CLK_SRC_OPTION_MAINCK +#endif + +// Enable Clock_PCK6 +// Indicates whether PCK6 is enabled or disable +// clk_gen_pck6_arch_enable +#ifndef CONF_CLK_PCK6_ENABLE +#define CONF_CLK_PCK6_ENABLE 0 +#endif + +// + +// + +// Programmable Clock Controller Prescaler <1-256> +// Select the clock prescaler (prescaler = PRESC + 1). +// pck6_presc +#ifndef CONF_PCK6_PRESC +#define CONF_PCK6_PRESC 7 +#endif + +// +// // Clock_USB_480M configuration +// Indicates whether USB_480M configuration is enabled or not +// enable_clk_gen_usb_480m +#ifndef CONF_CLK_USB_480M_CONFIG +#define CONF_CLK_USB_480M_CONFIG 1 +#endif + +// Clock Generator +// clock generator USB_480M source + +// USB 480M Clock (UPLLCK) + +// This defines the clock source for USB_480M +// clk_gen_usb_480m_oscillator +#ifndef CONF_CLK_GEN_USB_480M_SRC +#define CONF_CLK_GEN_USB_480M_SRC CLK_SRC_OPTION_UPLLCK +#endif + +// + +// + +// +// // Clock_USB_48M configuration +// Indicates whether USB_48M configuration is enabled or not +// enable_clk_gen_usb_48m +#ifndef CONF_CLK_USB_48M_CONFIG +#define CONF_CLK_USB_48M_CONFIG 1 +#endif + +// Clock Generator +// clock generator USB_48M source + +// PLLA Clock (PLLACK) + +// UDPLL with Divider (MCKR UPLLDIV2) + +// This defines the clock source for USB_48M +// clk_gen_usb_48m_oscillator +#ifndef CONF_CLK_GEN_USB_48M_SRC +#define CONF_CLK_GEN_USB_48M_SRC CLK_SRC_OPTION_UPLLCKDIV +#endif + +// Enable Clock_USB_48M +// Indicates whether USB_48M is enabled or disable +// clk_gen_usb_48m_arch_enable +#ifndef CONF_CLK_USB_48M_ENABLE +#define CONF_CLK_USB_48M_ENABLE 1 +#endif + +// + +// + +// USB Clock Controller Divider <1-16> +// Select the USB clock divider (divider = USBDIV + 1). +// usb_48m_div +#ifndef CONF_USB_48M_DIV +#define CONF_USB_48M_DIV 5 +#endif + +// +// // Clock_SLCK2 configuration +// Indicates whether SLCK2 configuration is enabled or not +// enable_clk_gen_slck2 +#ifndef CONF_CLK_SLCK2_CONFIG +#define CONF_CLK_SLCK2_CONFIG 1 +#endif + +// Clock Generator +// clock generator SLCK2 source + +// Slow Clock (SLCK) + +// This defines the clock source for SLCK2 +// clk_gen_slck2_oscillator +#ifndef CONF_CLK_GEN_SLCK2_SRC +#define CONF_CLK_GEN_SLCK2_SRC CLK_SRC_OPTION_SLCK +#endif + +// + +// + +// +// + +// System Configuration +// Indicates whether configuration for system is enabled or not +// enable_hclk_clock +#ifndef CONF_SYSTEM_CONFIG +#define CONF_SYSTEM_CONFIG 1 +#endif + +// Processor Clock Settings +// Processor Clock source +// Master Clock Controller (PMC_MCKR) +// This defines the clock source for the HCLK (Processor clock) +// hclk_clock_source +#ifndef CONF_HCLK_SRC +#define CONF_HCLK_SRC MCKR +#endif + +// Flash Wait State +// <0=> 1 cycle +// <1=> 2 cycles +// <2=> 3 cycles +// <3=> 4 cycles +// <4=> 5 cycles +// <5=> 6 cycles +// <6=> 7 cycles +// This field defines the number of wait states for read and write operations. +// efc_fws +#ifndef CONF_EFC_WAIT_STATE +#define CONF_EFC_WAIT_STATE 5 +#endif + +// +// + +// SysTick Clock +// enable_systick_clk_clock +#ifndef CONF_SYSTICK_CLK_CONFIG +#define CONF_SYSTICK_CLK_CONFIG 1 +#endif + +// SysTick Clock source +// Master Clock Controller (PMC_MCKR) +// This defines the clock source for the SysTick Clock +// systick_clk_clock_source +#ifndef CONF_SYSTICK_CLK_SRC +#define CONF_SYSTICK_CLK_SRC MCKR +#endif + +// SysTick Clock Divider +// <8=> 8 +// Fixed to 8 if Systick is not using Processor clock +// systick_clk_clock_div +#ifndef CONF_SYSTICK_CLK_DIV +#define CONF_SYSTICK_CLK_DIV 8 +#endif + +// + +// OSC32K Oscillator Configuration +// Indicates whether configuration for OSC32K is enabled or not +// enable_osc32k +#ifndef CONF_OSC32K_CONFIG +#define CONF_OSC32K_CONFIG 1 +#endif + +// OSC32K Oscillator Control +// OSC32K Oscillator Enable +// Indicates whether OSC32K Oscillator is enabled or not +// osc32k_arch_enable +#ifndef CONF_OSC32K_ENABLE +#define CONF_OSC32K_ENABLE 0 +#endif +// +// + +// XOSC32K Oscillator Configuration +// Indicates whether configuration for XOSC32K is enabled or not +// enable_xosc32k +#ifndef CONF_XOSC32K_CONFIG +#define CONF_XOSC32K_CONFIG 0 +#endif + +// XOSC32K Oscillator Control +// Oscillator Bypass Select +// The 32kHz crystal oscillator is not bypassed. +// The 32kHz crystal oscillator is bypassed. +// Indicates whether XOSC32K is bypassed. +// xosc32k_bypass +#ifndef CONF_XOSC32K +#define CONF_XOSC32K CONF_XOSC32K_NO_BYPASS +#endif + +// XOSC32K Oscillator Enable +// Indicates whether XOSC32K Oscillator is enabled or not +// xosc32k_arch_enable +#ifndef CONF_XOSC32K_ENABLE +#define CONF_XOSC32K_ENABLE 0 +#endif +// +// + +// OSC12M Oscillator Configuration +// Indicates whether configuration for OSC12M is enabled or not +// enable_osc12m +#ifndef CONF_OSC12M_CONFIG +#define CONF_OSC12M_CONFIG 0 +#endif + +// OSC12M Oscillator Control +// OSC12M Oscillator Enable +// Indicates whether OSC12M Oscillator is enabled or not. +// osc12m_arch_enable +#ifndef CONF_OSC12M_ENABLE +#define CONF_OSC12M_ENABLE 0 +#endif + +// OSC12M selector +// <0=> 4000000 +// <1=> 8000000 +// <2=> 12000000 +// Select the frequency of embedded fast RC oscillator. +// osc12m_selector +#ifndef CONF_OSC12M_SELECTOR +#define CONF_OSC12M_SELECTOR 2 +#endif +// +// + +// XOSC20M Oscillator Configuration +// Indicates whether configuration for XOSC20M is enabled or not. +// enable_xosc20m +#ifndef CONF_XOSC20M_CONFIG +#define CONF_XOSC20M_CONFIG 1 +#endif + +// XOSC20M Oscillator Control +// XOSC20M selector <3000000-20000000> +// Select the frequency of crystal or ceramic resonator oscillator. +// xosc20m_selector +#ifndef CONF_XOSC20M_SELECTOR +#define CONF_XOSC20M_SELECTOR 12000000 +#endif + +// Start up time for the external oscillator (ms): <0-256> +// Select start-up time. +// xosc20m_startup_time +#ifndef CONF_XOSC20M_STARTUP_TIME +#define CONF_XOSC20M_STARTUP_TIME 62 +#endif + +// Oscillator Bypass Select +// The external crystal oscillator is not bypassed. +// The external crystal oscillator is bypassed. +// Indicates whether XOSC20M is bypassed. +// xosc20m_bypass +#ifndef CONF_XOSC20M +#define CONF_XOSC20M CONF_XOSC20M_NO_BYPASS +#endif + +// XOSC20M Oscillator Enable +// Indicates whether XOSC20M Oscillator is enabled or not +// xosc20m_arch_enable +#ifndef CONF_XOSC20M_ENABLE +#define CONF_XOSC20M_ENABLE 1 +#endif +// +// + +// PLLACK Oscillator Configuration +// Indicates whether configuration for PLLACK is enabled or not +// enable_pllack +#ifndef CONF_PLLACK_CONFIG +#define CONF_PLLACK_CONFIG 1 +#endif + +// PLLACK Reference Clock Source +// Main Clock (MAINCK) +// Select the clock source. +// pllack_ref_clock +#ifndef CONF_PLLACK_CLK +#define CONF_PLLACK_CLK MAINCK +#endif + +// PLLACK Oscillator Control +// PLLACK Oscillator Enable +// Indicates whether PLLACK Oscillator is enabled or not +// pllack_arch_enable +#ifndef CONF_PLLACK_ENABLE +#define CONF_PLLACK_ENABLE 1 +#endif + +// PLLA Frontend Divider (DIVA) <1-255> +// Select the clock divider +// pllack_div +#ifndef CONF_PLLACK_DIV +#define CONF_PLLACK_DIV 1 +#endif + +// PLLACK Muliplier <1-62> +// Indicates PLLA multiplier (multiplier = MULA + 1). +// pllack_mul +#ifndef CONF_PLLACK_MUL +#define CONF_PLLACK_MUL 25 +#endif +// +// + +// UPLLCK Oscillator Configuration +// Indicates whether configuration for UPLLCK is enabled or not +// enable_upllck +#ifndef CONF_UPLLCK_CONFIG +#define CONF_UPLLCK_CONFIG 1 +#endif + +// UPLLCK Reference Clock Source +// External 3-20MHz Oscillator (XOSC20M) +// Select the clock source,only when the input frequency is 12M or 16M, the upllck output is 480M. +// upllck_ref_clock +#ifndef CONF_UPLLCK_CLK +#define CONF_UPLLCK_CLK XOSC20M +#endif + +// UPLLCK Oscillator Control +// UPLLCK Oscillator Enable +// Indicates whether UPLLCK Oscillator is enabled or not +// upllck_arch_enable +#ifndef CONF_UPLLCK_ENABLE +#define CONF_UPLLCK_ENABLE 1 +#endif +// +// + +// UPLLCKDIV Oscillator Configuration +// Indicates whether configuration for UPLLCKDIV is enabled or not +// enable_upllckdiv +#ifndef CONF_UPLLCKDIV_CONFIG +#define CONF_UPLLCKDIV_CONFIG 1 +#endif + +// UPLLCKDIV Reference Clock Source +// USB 480M Clock (UPLLCK) +// Select the clock source. +// upllckdiv_ref_clock +#ifndef CONF_UPLLCKDIV_CLK +#define CONF_UPLLCKDIV_CLK UPLLCK +#endif + +// UPLLCKDIV Oscillator Control +// UPLLCKDIV Clock Divider +// <0=> 1 +// <1=> 2 +// Select the clock divider. +// upllckdiv_div +#ifndef CONF_UPLLCKDIV_DIV +#define CONF_UPLLCKDIV_DIV 1 +#endif +// +// + +// MCK/8 +// enable_mck_div_8 +#ifndef CONF_MCK_DIV_8_CONFIG +#define CONF_MCK_DIV_8_CONFIG 0 +#endif + +// MCK/8 Source +// <0=> Master Clock (MCK) +// mck_div_8_src +#ifndef CONF_MCK_DIV_8_SRC +#define CONF_MCK_DIV_8_SRC 0 +#endif +// + +// External Clock Input Configuration +// enable_dummy_ext +#ifndef CONF_DUMMY_EXT_CONFIG +#define CONF_DUMMY_EXT_CONFIG 1 +#endif + +// External Clock Input Source +// All here are dummy values +// Refer to the peripherals settings for actual input information +// <0=> Specific clock input from specific pin +// dummy_ext_src +#ifndef CONF_DUMMY_EXT_SRC +#define CONF_DUMMY_EXT_SRC 0 +#endif +// + +// External Clock Configuration +// enable_dummy_ext_clk +#ifndef CONF_DUMMY_EXT_CLK_CONFIG +#define CONF_DUMMY_EXT_CLK_CONFIG 1 +#endif + +// External Clock Source +// All here are dummy values +// Refer to the peripherals settings for actual input information +// <0=> External Clock Input +// dummy_ext_clk_src +#ifndef CONF_DUMMY_EXT_CLK_SRC +#define CONF_DUMMY_EXT_CLK_SRC 0 +#endif +// + +// <<< end of configuration section >>> + +#endif // HPL_PMC_CONFIG_H diff --git a/hw/bsp/same70_qmtech/hpl_usart_config.h b/hw/bsp/same70_qmtech/hpl_usart_config.h new file mode 100644 index 000000000..50ca3f15c --- /dev/null +++ b/hw/bsp/same70_qmtech/hpl_usart_config.h @@ -0,0 +1,215 @@ +/* Auto-generated config file hpl_usart_config.h */ +#ifndef HPL_USART_CONFIG_H +#define HPL_USART_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#include + +#ifndef CONF_USART_1_ENABLE +#define CONF_USART_1_ENABLE 1 +#endif + +// Basic Configuration + +// Frame parity +// <0x0=>Even parity +// <0x1=>Odd parity +// <0x2=>Parity forced to 0 +// <0x3=>Parity forced to 1 +// <0x4=>No parity +// Parity bit mode for USART frame +// usart_parity +#ifndef CONF_USART_1_PARITY +#define CONF_USART_1_PARITY 0x4 +#endif + +// Character Size +// <0x0=>5 bits +// <0x1=>6 bits +// <0x2=>7 bits +// <0x3=>8 bits +// Data character size in USART frame +// usart_character_size +#ifndef CONF_USART_1_CHSIZE +#define CONF_USART_1_CHSIZE 0x3 +#endif + +// Stop Bit +// <0=>1 stop bit +// <1=>1.5 stop bits +// <2=>2 stop bits +// Number of stop bits in USART frame +// usart_stop_bit +#ifndef CONF_USART_1_SBMODE +#define CONF_USART_1_SBMODE 0 +#endif + +// Clock Output Select +// <0=>The USART does not drive the SCK pin +// <1=>The USART drives the SCK pin if USCLKS does not select the external clock SCK +// Clock Output Select in USART sck, if in usrt master mode, please drive SCK. +// usart_clock_output_select +#ifndef CONF_USART_1_CLKO +#define CONF_USART_1_CLKO 0 +#endif + +// Baud rate <1-3000000> +// USART baud rate setting +// usart_baud_rate +#ifndef CONF_USART_1_BAUD +#define CONF_USART_1_BAUD 9600 +#endif + +// + +// Advanced configuration +// usart_advanced +#ifndef CONF_USART_1_ADVANCED_CONFIG +#define CONF_USART_1_ADVANCED_CONFIG 0 +#endif + +// Channel Mode +// <0=>Normal Mode +// <1=>Automatic Echo +// <2=>Local Loopback +// <3=>Remote Loopback +// Channel mode in USART frame +// usart_channel_mode +#ifndef CONF_USART_1_CHMODE +#define CONF_USART_1_CHMODE 0 +#endif + +// 9 bits character enable +// Enable 9 bits character, this has high priority than 5/6/7/8 bits. +// usart_9bits_enable +#ifndef CONF_USART_1_MODE9 +#define CONF_USART_1_MODE9 0 +#endif + +// Variable Sync +// <0=>User defined configuration +// <1=>sync field is updated when a character is written into US_THR +// Variable Synchronization of Command/Data Sync Start Frarm Delimiter +// variable_sync +#ifndef CONF_USART_1_VAR_SYNC +#define CONF_USART_1_VAR_SYNC 0 +#endif + +// Oversampling Mode +// <0=>16 Oversampling +// <1=>8 Oversampling +// Oversampling Mode in UART mode +// usart__oversampling_mode +#ifndef CONF_USART_1_OVER +#define CONF_USART_1_OVER 0 +#endif + +// Inhibit Non Ack +// <0=>The NACK is generated +// <1=>The NACK is not generated +// Inhibit Non Acknowledge +// usart__inack +#ifndef CONF_USART_1_INACK +#define CONF_USART_1_INACK 1 +#endif + +// Disable Successive NACK +// <0=>NACK is sent on the ISO line as soon as a parity error occurs +// <1=>Many parity errors generate a NACK on the ISO line +// Disable Successive NACK +// usart_dsnack +#ifndef CONF_USART_1_DSNACK +#define CONF_USART_1_DSNACK 0 +#endif + +// Inverted Data +// <0=>Data isn't inverted, nomal mode +// <1=>Data is inverted +// Inverted Data +// usart_invdata +#ifndef CONF_USART_1_INVDATA +#define CONF_USART_1_INVDATA 0 +#endif + +// Maximum Number of Automatic Iteration <0-7> +// Defines the maximum number of iterations in mode ISO7816, protocol T = 0. +// usart_max_iteration +#ifndef CONF_USART_1_MAX_ITERATION +#define CONF_USART_1_MAX_ITERATION 0 +#endif + +// Receive Line Filter enable +// whether the USART filters the receive line using a three-sample filter +// usart_receive_filter_enable +#ifndef CONF_USART_1_FILTER +#define CONF_USART_1_FILTER 0 +#endif + +// Manchester Encoder/Decoder Enable +// whether the USART Manchester Encoder/Decoder +// usart_manchester_filter_enable +#ifndef CONF_USART_1_MAN +#define CONF_USART_1_MAN 0 +#endif + +// Manchester Synchronization Mode +// <0=>The Manchester start bit is a 0 to 1 transition +// <1=>The Manchester start bit is a 1 to 0 transition +// Manchester Synchronization Mode +// usart_manchester_synchronization_mode +#ifndef CONF_USART_1_MODSYNC +#define CONF_USART_1_MODSYNC 0 +#endif + +// Start Frame Delimiter Selector +// <0=>Start frame delimiter is COMMAND or DATA SYNC +// <1=>Start frame delimiter is one bit +// Start Frame Delimiter Selector +// usart_start_frame_delimiter +#ifndef CONF_USART_1_ONEBIT +#define CONF_USART_1_ONEBIT 0 +#endif + +// Fractional Part <0-7> +// Fractional part of the baud rate if baud rate generator is in fractional mode +// usart_arch_fractional +#ifndef CONF_USART_1_FRACTIONAL +#define CONF_USART_1_FRACTIONAL 0x0 +#endif + +// Data Order +// <0=>LSB is transmitted first +// <1=>MSB is transmitted first +// Data order of the data bits in the frame +// usart_arch_msbf +#ifndef CONF_USART_1_MSBF +#define CONF_USART_1_MSBF 0 +#endif + +// + +#define CONF_USART_1_MODE 0x0 + +// Calculate BAUD register value in UART mode +#if CONF_USART1_CK_SRC < 3 +#ifndef CONF_USART_1_BAUD_CD +#define CONF_USART_1_BAUD_CD ((CONF_USART1_FREQUENCY) / CONF_USART_1_BAUD / 8 / (2 - CONF_USART_1_OVER)) +#endif +#ifndef CONF_USART_1_BAUD_FP +#define CONF_USART_1_BAUD_FP \ + ((CONF_USART1_FREQUENCY) / CONF_USART_1_BAUD / (2 - CONF_USART_1_OVER) - 8 * CONF_USART_1_BAUD_CD) +#endif +#elif CONF_USART1_CK_SRC == 3 +// No division is active. The value written in US_BRGR has no effect. +#ifndef CONF_USART_1_BAUD_CD +#define CONF_USART_1_BAUD_CD 1 +#endif +#ifndef CONF_USART_1_BAUD_FP +#define CONF_USART_1_BAUD_FP 1 +#endif +#endif + +// <<< end of configuration section >>> + +#endif // HPL_USART_CONFIG_H diff --git a/hw/bsp/same70_qmtech/hpl_xdmac_config.h b/hw/bsp/same70_qmtech/hpl_xdmac_config.h new file mode 100644 index 000000000..a3d62c6fc --- /dev/null +++ b/hw/bsp/same70_qmtech/hpl_xdmac_config.h @@ -0,0 +1,4400 @@ +/* Auto-generated config file hpl_xdmac_config.h */ +#ifndef HPL_XDMAC_CONFIG_H +#define HPL_XDMAC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// XDMAC enable +// Indicates whether xdmac is enabled or not +// xdmac_enable +#ifndef CONF_DMA_ENABLE +#define CONF_DMA_ENABLE 0 +#endif + +// Channel 0 settings +// dmac_channel_0_settings +#ifndef CONF_DMAC_CHANNEL_0_SETTINGS +#define CONF_DMAC_CHANNEL_0_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_0 +#ifndef CONF_DMAC_BURSTSIZE_0 +#define CONF_DMAC_BURSTSIZE_0 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_0 +#ifndef CONF_DMAC_CHUNKSIZE_0 +#define CONF_DMAC_CHUNKSIZE_0 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_0 +#ifndef CONF_DMAC_BEATSIZE_0 +#define CONF_DMAC_BEATSIZE_0 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_0 +#ifndef CONF_DMAC_SRC_INTERFACE_0 +#define CONF_DMAC_SRC_INTERFACE_0 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_0 +#ifndef CONF_DMAC_DES_INTERFACE_0 +#define CONF_DMAC_DES_INTERFACE_0 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_0 +#ifndef CONF_DMAC_SRCINC_0 +#define CONF_DMAC_SRCINC_0 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_0 +#ifndef CONF_DMAC_DSTINC_0 +#define CONF_DMAC_DSTINC_0 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_0 +#ifndef CONF_DMAC_TRANS_TYPE_0 +#define CONF_DMAC_TRANS_TYPE_0 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_0 +#ifndef CONF_DMAC_TRIGSRC_0 +#define CONF_DMAC_TRIGSRC_0 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_0 == 0 +#define CONF_DMAC_TYPE_0 0 +#define CONF_DMAC_DSYNC_0 0 +#elif CONF_DMAC_TRANS_TYPE_0 == 1 +#define CONF_DMAC_TYPE_0 1 +#define CONF_DMAC_DSYNC_0 0 +#elif CONF_DMAC_TRANS_TYPE_0 == 2 +#define CONF_DMAC_TYPE_0 1 +#define CONF_DMAC_DSYNC_0 1 +#endif + +#if CONF_DMAC_TRIGSRC_0 == 0xFF +#define CONF_DMAC_SWREQ_0 1 +#else +#define CONF_DMAC_SWREQ_0 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_0_SETTINGS == 1 && CONF_DMAC_BEATSIZE_0 != 2 && ((!CONF_DMAC_SRCINC_0) || (!CONF_DMAC_DSTINC_0))) +#if (!CONF_DMAC_SRCINC_0) +#define CONF_DMAC_SRC_STRIDE_0 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_0) +#define CONF_DMAC_DES_STRIDE_0 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_0 +#define CONF_DMAC_SRC_STRIDE_0 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_0 +#define CONF_DMAC_DES_STRIDE_0 0 +#endif + +// Channel 1 settings +// dmac_channel_1_settings +#ifndef CONF_DMAC_CHANNEL_1_SETTINGS +#define CONF_DMAC_CHANNEL_1_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_1 +#ifndef CONF_DMAC_BURSTSIZE_1 +#define CONF_DMAC_BURSTSIZE_1 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_1 +#ifndef CONF_DMAC_CHUNKSIZE_1 +#define CONF_DMAC_CHUNKSIZE_1 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_1 +#ifndef CONF_DMAC_BEATSIZE_1 +#define CONF_DMAC_BEATSIZE_1 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_1 +#ifndef CONF_DMAC_SRC_INTERFACE_1 +#define CONF_DMAC_SRC_INTERFACE_1 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_1 +#ifndef CONF_DMAC_DES_INTERFACE_1 +#define CONF_DMAC_DES_INTERFACE_1 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_1 +#ifndef CONF_DMAC_SRCINC_1 +#define CONF_DMAC_SRCINC_1 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_1 +#ifndef CONF_DMAC_DSTINC_1 +#define CONF_DMAC_DSTINC_1 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_1 +#ifndef CONF_DMAC_TRANS_TYPE_1 +#define CONF_DMAC_TRANS_TYPE_1 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_1 +#ifndef CONF_DMAC_TRIGSRC_1 +#define CONF_DMAC_TRIGSRC_1 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_1 == 0 +#define CONF_DMAC_TYPE_1 0 +#define CONF_DMAC_DSYNC_1 0 +#elif CONF_DMAC_TRANS_TYPE_1 == 1 +#define CONF_DMAC_TYPE_1 1 +#define CONF_DMAC_DSYNC_1 0 +#elif CONF_DMAC_TRANS_TYPE_1 == 2 +#define CONF_DMAC_TYPE_1 1 +#define CONF_DMAC_DSYNC_1 1 +#endif + +#if CONF_DMAC_TRIGSRC_1 == 0xFF +#define CONF_DMAC_SWREQ_1 1 +#else +#define CONF_DMAC_SWREQ_1 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_1_SETTINGS == 1 && CONF_DMAC_BEATSIZE_1 != 2 && ((!CONF_DMAC_SRCINC_1) || (!CONF_DMAC_DSTINC_1))) +#if (!CONF_DMAC_SRCINC_1) +#define CONF_DMAC_SRC_STRIDE_1 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_1) +#define CONF_DMAC_DES_STRIDE_1 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_1 +#define CONF_DMAC_SRC_STRIDE_1 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_1 +#define CONF_DMAC_DES_STRIDE_1 0 +#endif + +// Channel 2 settings +// dmac_channel_2_settings +#ifndef CONF_DMAC_CHANNEL_2_SETTINGS +#define CONF_DMAC_CHANNEL_2_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_2 +#ifndef CONF_DMAC_BURSTSIZE_2 +#define CONF_DMAC_BURSTSIZE_2 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_2 +#ifndef CONF_DMAC_CHUNKSIZE_2 +#define CONF_DMAC_CHUNKSIZE_2 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_2 +#ifndef CONF_DMAC_BEATSIZE_2 +#define CONF_DMAC_BEATSIZE_2 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_2 +#ifndef CONF_DMAC_SRC_INTERFACE_2 +#define CONF_DMAC_SRC_INTERFACE_2 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_2 +#ifndef CONF_DMAC_DES_INTERFACE_2 +#define CONF_DMAC_DES_INTERFACE_2 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_2 +#ifndef CONF_DMAC_SRCINC_2 +#define CONF_DMAC_SRCINC_2 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_2 +#ifndef CONF_DMAC_DSTINC_2 +#define CONF_DMAC_DSTINC_2 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_2 +#ifndef CONF_DMAC_TRANS_TYPE_2 +#define CONF_DMAC_TRANS_TYPE_2 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_2 +#ifndef CONF_DMAC_TRIGSRC_2 +#define CONF_DMAC_TRIGSRC_2 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_2 == 0 +#define CONF_DMAC_TYPE_2 0 +#define CONF_DMAC_DSYNC_2 0 +#elif CONF_DMAC_TRANS_TYPE_2 == 1 +#define CONF_DMAC_TYPE_2 1 +#define CONF_DMAC_DSYNC_2 0 +#elif CONF_DMAC_TRANS_TYPE_2 == 2 +#define CONF_DMAC_TYPE_2 1 +#define CONF_DMAC_DSYNC_2 1 +#endif + +#if CONF_DMAC_TRIGSRC_2 == 0xFF +#define CONF_DMAC_SWREQ_2 1 +#else +#define CONF_DMAC_SWREQ_2 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_2_SETTINGS == 1 && CONF_DMAC_BEATSIZE_2 != 2 && ((!CONF_DMAC_SRCINC_2) || (!CONF_DMAC_DSTINC_2))) +#if (!CONF_DMAC_SRCINC_2) +#define CONF_DMAC_SRC_STRIDE_2 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_2) +#define CONF_DMAC_DES_STRIDE_2 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_2 +#define CONF_DMAC_SRC_STRIDE_2 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_2 +#define CONF_DMAC_DES_STRIDE_2 0 +#endif + +// Channel 3 settings +// dmac_channel_3_settings +#ifndef CONF_DMAC_CHANNEL_3_SETTINGS +#define CONF_DMAC_CHANNEL_3_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_3 +#ifndef CONF_DMAC_BURSTSIZE_3 +#define CONF_DMAC_BURSTSIZE_3 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_3 +#ifndef CONF_DMAC_CHUNKSIZE_3 +#define CONF_DMAC_CHUNKSIZE_3 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_3 +#ifndef CONF_DMAC_BEATSIZE_3 +#define CONF_DMAC_BEATSIZE_3 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_3 +#ifndef CONF_DMAC_SRC_INTERFACE_3 +#define CONF_DMAC_SRC_INTERFACE_3 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_3 +#ifndef CONF_DMAC_DES_INTERFACE_3 +#define CONF_DMAC_DES_INTERFACE_3 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_3 +#ifndef CONF_DMAC_SRCINC_3 +#define CONF_DMAC_SRCINC_3 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_3 +#ifndef CONF_DMAC_DSTINC_3 +#define CONF_DMAC_DSTINC_3 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_3 +#ifndef CONF_DMAC_TRANS_TYPE_3 +#define CONF_DMAC_TRANS_TYPE_3 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_3 +#ifndef CONF_DMAC_TRIGSRC_3 +#define CONF_DMAC_TRIGSRC_3 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_3 == 0 +#define CONF_DMAC_TYPE_3 0 +#define CONF_DMAC_DSYNC_3 0 +#elif CONF_DMAC_TRANS_TYPE_3 == 1 +#define CONF_DMAC_TYPE_3 1 +#define CONF_DMAC_DSYNC_3 0 +#elif CONF_DMAC_TRANS_TYPE_3 == 2 +#define CONF_DMAC_TYPE_3 1 +#define CONF_DMAC_DSYNC_3 1 +#endif + +#if CONF_DMAC_TRIGSRC_3 == 0xFF +#define CONF_DMAC_SWREQ_3 1 +#else +#define CONF_DMAC_SWREQ_3 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_3_SETTINGS == 1 && CONF_DMAC_BEATSIZE_3 != 2 && ((!CONF_DMAC_SRCINC_3) || (!CONF_DMAC_DSTINC_3))) +#if (!CONF_DMAC_SRCINC_3) +#define CONF_DMAC_SRC_STRIDE_3 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_3) +#define CONF_DMAC_DES_STRIDE_3 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_3 +#define CONF_DMAC_SRC_STRIDE_3 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_3 +#define CONF_DMAC_DES_STRIDE_3 0 +#endif + +// Channel 4 settings +// dmac_channel_4_settings +#ifndef CONF_DMAC_CHANNEL_4_SETTINGS +#define CONF_DMAC_CHANNEL_4_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_4 +#ifndef CONF_DMAC_BURSTSIZE_4 +#define CONF_DMAC_BURSTSIZE_4 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_4 +#ifndef CONF_DMAC_CHUNKSIZE_4 +#define CONF_DMAC_CHUNKSIZE_4 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_4 +#ifndef CONF_DMAC_BEATSIZE_4 +#define CONF_DMAC_BEATSIZE_4 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_4 +#ifndef CONF_DMAC_SRC_INTERFACE_4 +#define CONF_DMAC_SRC_INTERFACE_4 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_4 +#ifndef CONF_DMAC_DES_INTERFACE_4 +#define CONF_DMAC_DES_INTERFACE_4 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_4 +#ifndef CONF_DMAC_SRCINC_4 +#define CONF_DMAC_SRCINC_4 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_4 +#ifndef CONF_DMAC_DSTINC_4 +#define CONF_DMAC_DSTINC_4 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_4 +#ifndef CONF_DMAC_TRANS_TYPE_4 +#define CONF_DMAC_TRANS_TYPE_4 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_4 +#ifndef CONF_DMAC_TRIGSRC_4 +#define CONF_DMAC_TRIGSRC_4 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_4 == 0 +#define CONF_DMAC_TYPE_4 0 +#define CONF_DMAC_DSYNC_4 0 +#elif CONF_DMAC_TRANS_TYPE_4 == 1 +#define CONF_DMAC_TYPE_4 1 +#define CONF_DMAC_DSYNC_4 0 +#elif CONF_DMAC_TRANS_TYPE_4 == 2 +#define CONF_DMAC_TYPE_4 1 +#define CONF_DMAC_DSYNC_4 1 +#endif + +#if CONF_DMAC_TRIGSRC_4 == 0xFF +#define CONF_DMAC_SWREQ_4 1 +#else +#define CONF_DMAC_SWREQ_4 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_4_SETTINGS == 1 && CONF_DMAC_BEATSIZE_4 != 2 && ((!CONF_DMAC_SRCINC_4) || (!CONF_DMAC_DSTINC_4))) +#if (!CONF_DMAC_SRCINC_4) +#define CONF_DMAC_SRC_STRIDE_4 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_4) +#define CONF_DMAC_DES_STRIDE_4 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_4 +#define CONF_DMAC_SRC_STRIDE_4 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_4 +#define CONF_DMAC_DES_STRIDE_4 0 +#endif + +// Channel 5 settings +// dmac_channel_5_settings +#ifndef CONF_DMAC_CHANNEL_5_SETTINGS +#define CONF_DMAC_CHANNEL_5_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_5 +#ifndef CONF_DMAC_BURSTSIZE_5 +#define CONF_DMAC_BURSTSIZE_5 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_5 +#ifndef CONF_DMAC_CHUNKSIZE_5 +#define CONF_DMAC_CHUNKSIZE_5 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_5 +#ifndef CONF_DMAC_BEATSIZE_5 +#define CONF_DMAC_BEATSIZE_5 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_5 +#ifndef CONF_DMAC_SRC_INTERFACE_5 +#define CONF_DMAC_SRC_INTERFACE_5 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_5 +#ifndef CONF_DMAC_DES_INTERFACE_5 +#define CONF_DMAC_DES_INTERFACE_5 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_5 +#ifndef CONF_DMAC_SRCINC_5 +#define CONF_DMAC_SRCINC_5 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_5 +#ifndef CONF_DMAC_DSTINC_5 +#define CONF_DMAC_DSTINC_5 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_5 +#ifndef CONF_DMAC_TRANS_TYPE_5 +#define CONF_DMAC_TRANS_TYPE_5 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_5 +#ifndef CONF_DMAC_TRIGSRC_5 +#define CONF_DMAC_TRIGSRC_5 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_5 == 0 +#define CONF_DMAC_TYPE_5 0 +#define CONF_DMAC_DSYNC_5 0 +#elif CONF_DMAC_TRANS_TYPE_5 == 1 +#define CONF_DMAC_TYPE_5 1 +#define CONF_DMAC_DSYNC_5 0 +#elif CONF_DMAC_TRANS_TYPE_5 == 2 +#define CONF_DMAC_TYPE_5 1 +#define CONF_DMAC_DSYNC_5 1 +#endif + +#if CONF_DMAC_TRIGSRC_5 == 0xFF +#define CONF_DMAC_SWREQ_5 1 +#else +#define CONF_DMAC_SWREQ_5 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_5_SETTINGS == 1 && CONF_DMAC_BEATSIZE_5 != 2 && ((!CONF_DMAC_SRCINC_5) || (!CONF_DMAC_DSTINC_5))) +#if (!CONF_DMAC_SRCINC_5) +#define CONF_DMAC_SRC_STRIDE_5 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_5) +#define CONF_DMAC_DES_STRIDE_5 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_5 +#define CONF_DMAC_SRC_STRIDE_5 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_5 +#define CONF_DMAC_DES_STRIDE_5 0 +#endif + +// Channel 6 settings +// dmac_channel_6_settings +#ifndef CONF_DMAC_CHANNEL_6_SETTINGS +#define CONF_DMAC_CHANNEL_6_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_6 +#ifndef CONF_DMAC_BURSTSIZE_6 +#define CONF_DMAC_BURSTSIZE_6 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_6 +#ifndef CONF_DMAC_CHUNKSIZE_6 +#define CONF_DMAC_CHUNKSIZE_6 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_6 +#ifndef CONF_DMAC_BEATSIZE_6 +#define CONF_DMAC_BEATSIZE_6 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_6 +#ifndef CONF_DMAC_SRC_INTERFACE_6 +#define CONF_DMAC_SRC_INTERFACE_6 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_6 +#ifndef CONF_DMAC_DES_INTERFACE_6 +#define CONF_DMAC_DES_INTERFACE_6 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_6 +#ifndef CONF_DMAC_SRCINC_6 +#define CONF_DMAC_SRCINC_6 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_6 +#ifndef CONF_DMAC_DSTINC_6 +#define CONF_DMAC_DSTINC_6 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_6 +#ifndef CONF_DMAC_TRANS_TYPE_6 +#define CONF_DMAC_TRANS_TYPE_6 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_6 +#ifndef CONF_DMAC_TRIGSRC_6 +#define CONF_DMAC_TRIGSRC_6 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_6 == 0 +#define CONF_DMAC_TYPE_6 0 +#define CONF_DMAC_DSYNC_6 0 +#elif CONF_DMAC_TRANS_TYPE_6 == 1 +#define CONF_DMAC_TYPE_6 1 +#define CONF_DMAC_DSYNC_6 0 +#elif CONF_DMAC_TRANS_TYPE_6 == 2 +#define CONF_DMAC_TYPE_6 1 +#define CONF_DMAC_DSYNC_6 1 +#endif + +#if CONF_DMAC_TRIGSRC_6 == 0xFF +#define CONF_DMAC_SWREQ_6 1 +#else +#define CONF_DMAC_SWREQ_6 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_6_SETTINGS == 1 && CONF_DMAC_BEATSIZE_6 != 2 && ((!CONF_DMAC_SRCINC_6) || (!CONF_DMAC_DSTINC_6))) +#if (!CONF_DMAC_SRCINC_6) +#define CONF_DMAC_SRC_STRIDE_6 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_6) +#define CONF_DMAC_DES_STRIDE_6 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_6 +#define CONF_DMAC_SRC_STRIDE_6 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_6 +#define CONF_DMAC_DES_STRIDE_6 0 +#endif + +// Channel 7 settings +// dmac_channel_7_settings +#ifndef CONF_DMAC_CHANNEL_7_SETTINGS +#define CONF_DMAC_CHANNEL_7_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_7 +#ifndef CONF_DMAC_BURSTSIZE_7 +#define CONF_DMAC_BURSTSIZE_7 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_7 +#ifndef CONF_DMAC_CHUNKSIZE_7 +#define CONF_DMAC_CHUNKSIZE_7 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_7 +#ifndef CONF_DMAC_BEATSIZE_7 +#define CONF_DMAC_BEATSIZE_7 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_7 +#ifndef CONF_DMAC_SRC_INTERFACE_7 +#define CONF_DMAC_SRC_INTERFACE_7 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_7 +#ifndef CONF_DMAC_DES_INTERFACE_7 +#define CONF_DMAC_DES_INTERFACE_7 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_7 +#ifndef CONF_DMAC_SRCINC_7 +#define CONF_DMAC_SRCINC_7 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_7 +#ifndef CONF_DMAC_DSTINC_7 +#define CONF_DMAC_DSTINC_7 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_7 +#ifndef CONF_DMAC_TRANS_TYPE_7 +#define CONF_DMAC_TRANS_TYPE_7 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_7 +#ifndef CONF_DMAC_TRIGSRC_7 +#define CONF_DMAC_TRIGSRC_7 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_7 == 0 +#define CONF_DMAC_TYPE_7 0 +#define CONF_DMAC_DSYNC_7 0 +#elif CONF_DMAC_TRANS_TYPE_7 == 1 +#define CONF_DMAC_TYPE_7 1 +#define CONF_DMAC_DSYNC_7 0 +#elif CONF_DMAC_TRANS_TYPE_7 == 2 +#define CONF_DMAC_TYPE_7 1 +#define CONF_DMAC_DSYNC_7 1 +#endif + +#if CONF_DMAC_TRIGSRC_7 == 0xFF +#define CONF_DMAC_SWREQ_7 1 +#else +#define CONF_DMAC_SWREQ_7 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_7_SETTINGS == 1 && CONF_DMAC_BEATSIZE_7 != 2 && ((!CONF_DMAC_SRCINC_7) || (!CONF_DMAC_DSTINC_7))) +#if (!CONF_DMAC_SRCINC_7) +#define CONF_DMAC_SRC_STRIDE_7 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_7) +#define CONF_DMAC_DES_STRIDE_7 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_7 +#define CONF_DMAC_SRC_STRIDE_7 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_7 +#define CONF_DMAC_DES_STRIDE_7 0 +#endif + +// Channel 8 settings +// dmac_channel_8_settings +#ifndef CONF_DMAC_CHANNEL_8_SETTINGS +#define CONF_DMAC_CHANNEL_8_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_8 +#ifndef CONF_DMAC_BURSTSIZE_8 +#define CONF_DMAC_BURSTSIZE_8 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_8 +#ifndef CONF_DMAC_CHUNKSIZE_8 +#define CONF_DMAC_CHUNKSIZE_8 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_8 +#ifndef CONF_DMAC_BEATSIZE_8 +#define CONF_DMAC_BEATSIZE_8 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_8 +#ifndef CONF_DMAC_SRC_INTERFACE_8 +#define CONF_DMAC_SRC_INTERFACE_8 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_8 +#ifndef CONF_DMAC_DES_INTERFACE_8 +#define CONF_DMAC_DES_INTERFACE_8 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_8 +#ifndef CONF_DMAC_SRCINC_8 +#define CONF_DMAC_SRCINC_8 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_8 +#ifndef CONF_DMAC_DSTINC_8 +#define CONF_DMAC_DSTINC_8 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_8 +#ifndef CONF_DMAC_TRANS_TYPE_8 +#define CONF_DMAC_TRANS_TYPE_8 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_8 +#ifndef CONF_DMAC_TRIGSRC_8 +#define CONF_DMAC_TRIGSRC_8 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_8 == 0 +#define CONF_DMAC_TYPE_8 0 +#define CONF_DMAC_DSYNC_8 0 +#elif CONF_DMAC_TRANS_TYPE_8 == 1 +#define CONF_DMAC_TYPE_8 1 +#define CONF_DMAC_DSYNC_8 0 +#elif CONF_DMAC_TRANS_TYPE_8 == 2 +#define CONF_DMAC_TYPE_8 1 +#define CONF_DMAC_DSYNC_8 1 +#endif + +#if CONF_DMAC_TRIGSRC_8 == 0xFF +#define CONF_DMAC_SWREQ_8 1 +#else +#define CONF_DMAC_SWREQ_8 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_8_SETTINGS == 1 && CONF_DMAC_BEATSIZE_8 != 2 && ((!CONF_DMAC_SRCINC_8) || (!CONF_DMAC_DSTINC_8))) +#if (!CONF_DMAC_SRCINC_8) +#define CONF_DMAC_SRC_STRIDE_8 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_8) +#define CONF_DMAC_DES_STRIDE_8 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_8 +#define CONF_DMAC_SRC_STRIDE_8 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_8 +#define CONF_DMAC_DES_STRIDE_8 0 +#endif + +// Channel 9 settings +// dmac_channel_9_settings +#ifndef CONF_DMAC_CHANNEL_9_SETTINGS +#define CONF_DMAC_CHANNEL_9_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_9 +#ifndef CONF_DMAC_BURSTSIZE_9 +#define CONF_DMAC_BURSTSIZE_9 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_9 +#ifndef CONF_DMAC_CHUNKSIZE_9 +#define CONF_DMAC_CHUNKSIZE_9 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_9 +#ifndef CONF_DMAC_BEATSIZE_9 +#define CONF_DMAC_BEATSIZE_9 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_9 +#ifndef CONF_DMAC_SRC_INTERFACE_9 +#define CONF_DMAC_SRC_INTERFACE_9 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_9 +#ifndef CONF_DMAC_DES_INTERFACE_9 +#define CONF_DMAC_DES_INTERFACE_9 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_9 +#ifndef CONF_DMAC_SRCINC_9 +#define CONF_DMAC_SRCINC_9 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_9 +#ifndef CONF_DMAC_DSTINC_9 +#define CONF_DMAC_DSTINC_9 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_9 +#ifndef CONF_DMAC_TRANS_TYPE_9 +#define CONF_DMAC_TRANS_TYPE_9 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_9 +#ifndef CONF_DMAC_TRIGSRC_9 +#define CONF_DMAC_TRIGSRC_9 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_9 == 0 +#define CONF_DMAC_TYPE_9 0 +#define CONF_DMAC_DSYNC_9 0 +#elif CONF_DMAC_TRANS_TYPE_9 == 1 +#define CONF_DMAC_TYPE_9 1 +#define CONF_DMAC_DSYNC_9 0 +#elif CONF_DMAC_TRANS_TYPE_9 == 2 +#define CONF_DMAC_TYPE_9 1 +#define CONF_DMAC_DSYNC_9 1 +#endif + +#if CONF_DMAC_TRIGSRC_9 == 0xFF +#define CONF_DMAC_SWREQ_9 1 +#else +#define CONF_DMAC_SWREQ_9 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_9_SETTINGS == 1 && CONF_DMAC_BEATSIZE_9 != 2 && ((!CONF_DMAC_SRCINC_9) || (!CONF_DMAC_DSTINC_9))) +#if (!CONF_DMAC_SRCINC_9) +#define CONF_DMAC_SRC_STRIDE_9 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_9) +#define CONF_DMAC_DES_STRIDE_9 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_9 +#define CONF_DMAC_SRC_STRIDE_9 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_9 +#define CONF_DMAC_DES_STRIDE_9 0 +#endif + +// Channel 10 settings +// dmac_channel_10_settings +#ifndef CONF_DMAC_CHANNEL_10_SETTINGS +#define CONF_DMAC_CHANNEL_10_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_10 +#ifndef CONF_DMAC_BURSTSIZE_10 +#define CONF_DMAC_BURSTSIZE_10 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_10 +#ifndef CONF_DMAC_CHUNKSIZE_10 +#define CONF_DMAC_CHUNKSIZE_10 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_10 +#ifndef CONF_DMAC_BEATSIZE_10 +#define CONF_DMAC_BEATSIZE_10 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_10 +#ifndef CONF_DMAC_SRC_INTERFACE_10 +#define CONF_DMAC_SRC_INTERFACE_10 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_10 +#ifndef CONF_DMAC_DES_INTERFACE_10 +#define CONF_DMAC_DES_INTERFACE_10 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_10 +#ifndef CONF_DMAC_SRCINC_10 +#define CONF_DMAC_SRCINC_10 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_10 +#ifndef CONF_DMAC_DSTINC_10 +#define CONF_DMAC_DSTINC_10 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_10 +#ifndef CONF_DMAC_TRANS_TYPE_10 +#define CONF_DMAC_TRANS_TYPE_10 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_10 +#ifndef CONF_DMAC_TRIGSRC_10 +#define CONF_DMAC_TRIGSRC_10 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_10 == 0 +#define CONF_DMAC_TYPE_10 0 +#define CONF_DMAC_DSYNC_10 0 +#elif CONF_DMAC_TRANS_TYPE_10 == 1 +#define CONF_DMAC_TYPE_10 1 +#define CONF_DMAC_DSYNC_10 0 +#elif CONF_DMAC_TRANS_TYPE_10 == 2 +#define CONF_DMAC_TYPE_10 1 +#define CONF_DMAC_DSYNC_10 1 +#endif + +#if CONF_DMAC_TRIGSRC_10 == 0xFF +#define CONF_DMAC_SWREQ_10 1 +#else +#define CONF_DMAC_SWREQ_10 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_10_SETTINGS == 1 && CONF_DMAC_BEATSIZE_10 != 2 \ + && ((!CONF_DMAC_SRCINC_10) || (!CONF_DMAC_DSTINC_10))) +#if (!CONF_DMAC_SRCINC_10) +#define CONF_DMAC_SRC_STRIDE_10 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_10) +#define CONF_DMAC_DES_STRIDE_10 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_10 +#define CONF_DMAC_SRC_STRIDE_10 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_10 +#define CONF_DMAC_DES_STRIDE_10 0 +#endif + +// Channel 11 settings +// dmac_channel_11_settings +#ifndef CONF_DMAC_CHANNEL_11_SETTINGS +#define CONF_DMAC_CHANNEL_11_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_11 +#ifndef CONF_DMAC_BURSTSIZE_11 +#define CONF_DMAC_BURSTSIZE_11 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_11 +#ifndef CONF_DMAC_CHUNKSIZE_11 +#define CONF_DMAC_CHUNKSIZE_11 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_11 +#ifndef CONF_DMAC_BEATSIZE_11 +#define CONF_DMAC_BEATSIZE_11 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_11 +#ifndef CONF_DMAC_SRC_INTERFACE_11 +#define CONF_DMAC_SRC_INTERFACE_11 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_11 +#ifndef CONF_DMAC_DES_INTERFACE_11 +#define CONF_DMAC_DES_INTERFACE_11 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_11 +#ifndef CONF_DMAC_SRCINC_11 +#define CONF_DMAC_SRCINC_11 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_11 +#ifndef CONF_DMAC_DSTINC_11 +#define CONF_DMAC_DSTINC_11 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_11 +#ifndef CONF_DMAC_TRANS_TYPE_11 +#define CONF_DMAC_TRANS_TYPE_11 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_11 +#ifndef CONF_DMAC_TRIGSRC_11 +#define CONF_DMAC_TRIGSRC_11 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_11 == 0 +#define CONF_DMAC_TYPE_11 0 +#define CONF_DMAC_DSYNC_11 0 +#elif CONF_DMAC_TRANS_TYPE_11 == 1 +#define CONF_DMAC_TYPE_11 1 +#define CONF_DMAC_DSYNC_11 0 +#elif CONF_DMAC_TRANS_TYPE_11 == 2 +#define CONF_DMAC_TYPE_11 1 +#define CONF_DMAC_DSYNC_11 1 +#endif + +#if CONF_DMAC_TRIGSRC_11 == 0xFF +#define CONF_DMAC_SWREQ_11 1 +#else +#define CONF_DMAC_SWREQ_11 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_11_SETTINGS == 1 && CONF_DMAC_BEATSIZE_11 != 2 \ + && ((!CONF_DMAC_SRCINC_11) || (!CONF_DMAC_DSTINC_11))) +#if (!CONF_DMAC_SRCINC_11) +#define CONF_DMAC_SRC_STRIDE_11 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_11) +#define CONF_DMAC_DES_STRIDE_11 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_11 +#define CONF_DMAC_SRC_STRIDE_11 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_11 +#define CONF_DMAC_DES_STRIDE_11 0 +#endif + +// Channel 12 settings +// dmac_channel_12_settings +#ifndef CONF_DMAC_CHANNEL_12_SETTINGS +#define CONF_DMAC_CHANNEL_12_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_12 +#ifndef CONF_DMAC_BURSTSIZE_12 +#define CONF_DMAC_BURSTSIZE_12 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_12 +#ifndef CONF_DMAC_CHUNKSIZE_12 +#define CONF_DMAC_CHUNKSIZE_12 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_12 +#ifndef CONF_DMAC_BEATSIZE_12 +#define CONF_DMAC_BEATSIZE_12 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_12 +#ifndef CONF_DMAC_SRC_INTERFACE_12 +#define CONF_DMAC_SRC_INTERFACE_12 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_12 +#ifndef CONF_DMAC_DES_INTERFACE_12 +#define CONF_DMAC_DES_INTERFACE_12 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_12 +#ifndef CONF_DMAC_SRCINC_12 +#define CONF_DMAC_SRCINC_12 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_12 +#ifndef CONF_DMAC_DSTINC_12 +#define CONF_DMAC_DSTINC_12 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_12 +#ifndef CONF_DMAC_TRANS_TYPE_12 +#define CONF_DMAC_TRANS_TYPE_12 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_12 +#ifndef CONF_DMAC_TRIGSRC_12 +#define CONF_DMAC_TRIGSRC_12 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_12 == 0 +#define CONF_DMAC_TYPE_12 0 +#define CONF_DMAC_DSYNC_12 0 +#elif CONF_DMAC_TRANS_TYPE_12 == 1 +#define CONF_DMAC_TYPE_12 1 +#define CONF_DMAC_DSYNC_12 0 +#elif CONF_DMAC_TRANS_TYPE_12 == 2 +#define CONF_DMAC_TYPE_12 1 +#define CONF_DMAC_DSYNC_12 1 +#endif + +#if CONF_DMAC_TRIGSRC_12 == 0xFF +#define CONF_DMAC_SWREQ_12 1 +#else +#define CONF_DMAC_SWREQ_12 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_12_SETTINGS == 1 && CONF_DMAC_BEATSIZE_12 != 2 \ + && ((!CONF_DMAC_SRCINC_12) || (!CONF_DMAC_DSTINC_12))) +#if (!CONF_DMAC_SRCINC_12) +#define CONF_DMAC_SRC_STRIDE_12 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_12) +#define CONF_DMAC_DES_STRIDE_12 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_12 +#define CONF_DMAC_SRC_STRIDE_12 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_12 +#define CONF_DMAC_DES_STRIDE_12 0 +#endif + +// Channel 13 settings +// dmac_channel_13_settings +#ifndef CONF_DMAC_CHANNEL_13_SETTINGS +#define CONF_DMAC_CHANNEL_13_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_13 +#ifndef CONF_DMAC_BURSTSIZE_13 +#define CONF_DMAC_BURSTSIZE_13 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_13 +#ifndef CONF_DMAC_CHUNKSIZE_13 +#define CONF_DMAC_CHUNKSIZE_13 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_13 +#ifndef CONF_DMAC_BEATSIZE_13 +#define CONF_DMAC_BEATSIZE_13 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_13 +#ifndef CONF_DMAC_SRC_INTERFACE_13 +#define CONF_DMAC_SRC_INTERFACE_13 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_13 +#ifndef CONF_DMAC_DES_INTERFACE_13 +#define CONF_DMAC_DES_INTERFACE_13 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_13 +#ifndef CONF_DMAC_SRCINC_13 +#define CONF_DMAC_SRCINC_13 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_13 +#ifndef CONF_DMAC_DSTINC_13 +#define CONF_DMAC_DSTINC_13 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_13 +#ifndef CONF_DMAC_TRANS_TYPE_13 +#define CONF_DMAC_TRANS_TYPE_13 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_13 +#ifndef CONF_DMAC_TRIGSRC_13 +#define CONF_DMAC_TRIGSRC_13 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_13 == 0 +#define CONF_DMAC_TYPE_13 0 +#define CONF_DMAC_DSYNC_13 0 +#elif CONF_DMAC_TRANS_TYPE_13 == 1 +#define CONF_DMAC_TYPE_13 1 +#define CONF_DMAC_DSYNC_13 0 +#elif CONF_DMAC_TRANS_TYPE_13 == 2 +#define CONF_DMAC_TYPE_13 1 +#define CONF_DMAC_DSYNC_13 1 +#endif + +#if CONF_DMAC_TRIGSRC_13 == 0xFF +#define CONF_DMAC_SWREQ_13 1 +#else +#define CONF_DMAC_SWREQ_13 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_13_SETTINGS == 1 && CONF_DMAC_BEATSIZE_13 != 2 \ + && ((!CONF_DMAC_SRCINC_13) || (!CONF_DMAC_DSTINC_13))) +#if (!CONF_DMAC_SRCINC_13) +#define CONF_DMAC_SRC_STRIDE_13 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_13) +#define CONF_DMAC_DES_STRIDE_13 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_13 +#define CONF_DMAC_SRC_STRIDE_13 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_13 +#define CONF_DMAC_DES_STRIDE_13 0 +#endif + +// Channel 14 settings +// dmac_channel_14_settings +#ifndef CONF_DMAC_CHANNEL_14_SETTINGS +#define CONF_DMAC_CHANNEL_14_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_14 +#ifndef CONF_DMAC_BURSTSIZE_14 +#define CONF_DMAC_BURSTSIZE_14 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_14 +#ifndef CONF_DMAC_CHUNKSIZE_14 +#define CONF_DMAC_CHUNKSIZE_14 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_14 +#ifndef CONF_DMAC_BEATSIZE_14 +#define CONF_DMAC_BEATSIZE_14 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_14 +#ifndef CONF_DMAC_SRC_INTERFACE_14 +#define CONF_DMAC_SRC_INTERFACE_14 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_14 +#ifndef CONF_DMAC_DES_INTERFACE_14 +#define CONF_DMAC_DES_INTERFACE_14 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_14 +#ifndef CONF_DMAC_SRCINC_14 +#define CONF_DMAC_SRCINC_14 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_14 +#ifndef CONF_DMAC_DSTINC_14 +#define CONF_DMAC_DSTINC_14 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_14 +#ifndef CONF_DMAC_TRANS_TYPE_14 +#define CONF_DMAC_TRANS_TYPE_14 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_14 +#ifndef CONF_DMAC_TRIGSRC_14 +#define CONF_DMAC_TRIGSRC_14 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_14 == 0 +#define CONF_DMAC_TYPE_14 0 +#define CONF_DMAC_DSYNC_14 0 +#elif CONF_DMAC_TRANS_TYPE_14 == 1 +#define CONF_DMAC_TYPE_14 1 +#define CONF_DMAC_DSYNC_14 0 +#elif CONF_DMAC_TRANS_TYPE_14 == 2 +#define CONF_DMAC_TYPE_14 1 +#define CONF_DMAC_DSYNC_14 1 +#endif + +#if CONF_DMAC_TRIGSRC_14 == 0xFF +#define CONF_DMAC_SWREQ_14 1 +#else +#define CONF_DMAC_SWREQ_14 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_14_SETTINGS == 1 && CONF_DMAC_BEATSIZE_14 != 2 \ + && ((!CONF_DMAC_SRCINC_14) || (!CONF_DMAC_DSTINC_14))) +#if (!CONF_DMAC_SRCINC_14) +#define CONF_DMAC_SRC_STRIDE_14 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_14) +#define CONF_DMAC_DES_STRIDE_14 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_14 +#define CONF_DMAC_SRC_STRIDE_14 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_14 +#define CONF_DMAC_DES_STRIDE_14 0 +#endif + +// Channel 15 settings +// dmac_channel_15_settings +#ifndef CONF_DMAC_CHANNEL_15_SETTINGS +#define CONF_DMAC_CHANNEL_15_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_15 +#ifndef CONF_DMAC_BURSTSIZE_15 +#define CONF_DMAC_BURSTSIZE_15 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_15 +#ifndef CONF_DMAC_CHUNKSIZE_15 +#define CONF_DMAC_CHUNKSIZE_15 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_15 +#ifndef CONF_DMAC_BEATSIZE_15 +#define CONF_DMAC_BEATSIZE_15 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_15 +#ifndef CONF_DMAC_SRC_INTERFACE_15 +#define CONF_DMAC_SRC_INTERFACE_15 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_15 +#ifndef CONF_DMAC_DES_INTERFACE_15 +#define CONF_DMAC_DES_INTERFACE_15 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_15 +#ifndef CONF_DMAC_SRCINC_15 +#define CONF_DMAC_SRCINC_15 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_15 +#ifndef CONF_DMAC_DSTINC_15 +#define CONF_DMAC_DSTINC_15 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_15 +#ifndef CONF_DMAC_TRANS_TYPE_15 +#define CONF_DMAC_TRANS_TYPE_15 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_15 +#ifndef CONF_DMAC_TRIGSRC_15 +#define CONF_DMAC_TRIGSRC_15 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_15 == 0 +#define CONF_DMAC_TYPE_15 0 +#define CONF_DMAC_DSYNC_15 0 +#elif CONF_DMAC_TRANS_TYPE_15 == 1 +#define CONF_DMAC_TYPE_15 1 +#define CONF_DMAC_DSYNC_15 0 +#elif CONF_DMAC_TRANS_TYPE_15 == 2 +#define CONF_DMAC_TYPE_15 1 +#define CONF_DMAC_DSYNC_15 1 +#endif + +#if CONF_DMAC_TRIGSRC_15 == 0xFF +#define CONF_DMAC_SWREQ_15 1 +#else +#define CONF_DMAC_SWREQ_15 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_15_SETTINGS == 1 && CONF_DMAC_BEATSIZE_15 != 2 \ + && ((!CONF_DMAC_SRCINC_15) || (!CONF_DMAC_DSTINC_15))) +#if (!CONF_DMAC_SRCINC_15) +#define CONF_DMAC_SRC_STRIDE_15 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_15) +#define CONF_DMAC_DES_STRIDE_15 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_15 +#define CONF_DMAC_SRC_STRIDE_15 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_15 +#define CONF_DMAC_DES_STRIDE_15 0 +#endif + +// Channel 16 settings +// dmac_channel_16_settings +#ifndef CONF_DMAC_CHANNEL_16_SETTINGS +#define CONF_DMAC_CHANNEL_16_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_16 +#ifndef CONF_DMAC_BURSTSIZE_16 +#define CONF_DMAC_BURSTSIZE_16 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_16 +#ifndef CONF_DMAC_CHUNKSIZE_16 +#define CONF_DMAC_CHUNKSIZE_16 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_16 +#ifndef CONF_DMAC_BEATSIZE_16 +#define CONF_DMAC_BEATSIZE_16 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_16 +#ifndef CONF_DMAC_SRC_INTERFACE_16 +#define CONF_DMAC_SRC_INTERFACE_16 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_16 +#ifndef CONF_DMAC_DES_INTERFACE_16 +#define CONF_DMAC_DES_INTERFACE_16 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_16 +#ifndef CONF_DMAC_SRCINC_16 +#define CONF_DMAC_SRCINC_16 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_16 +#ifndef CONF_DMAC_DSTINC_16 +#define CONF_DMAC_DSTINC_16 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_16 +#ifndef CONF_DMAC_TRANS_TYPE_16 +#define CONF_DMAC_TRANS_TYPE_16 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_16 +#ifndef CONF_DMAC_TRIGSRC_16 +#define CONF_DMAC_TRIGSRC_16 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_16 == 0 +#define CONF_DMAC_TYPE_16 0 +#define CONF_DMAC_DSYNC_16 0 +#elif CONF_DMAC_TRANS_TYPE_16 == 1 +#define CONF_DMAC_TYPE_16 1 +#define CONF_DMAC_DSYNC_16 0 +#elif CONF_DMAC_TRANS_TYPE_16 == 2 +#define CONF_DMAC_TYPE_16 1 +#define CONF_DMAC_DSYNC_16 1 +#endif + +#if CONF_DMAC_TRIGSRC_16 == 0xFF +#define CONF_DMAC_SWREQ_16 1 +#else +#define CONF_DMAC_SWREQ_16 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_16_SETTINGS == 1 && CONF_DMAC_BEATSIZE_16 != 2 \ + && ((!CONF_DMAC_SRCINC_16) || (!CONF_DMAC_DSTINC_16))) +#if (!CONF_DMAC_SRCINC_16) +#define CONF_DMAC_SRC_STRIDE_16 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_16) +#define CONF_DMAC_DES_STRIDE_16 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_16 +#define CONF_DMAC_SRC_STRIDE_16 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_16 +#define CONF_DMAC_DES_STRIDE_16 0 +#endif + +// Channel 17 settings +// dmac_channel_17_settings +#ifndef CONF_DMAC_CHANNEL_17_SETTINGS +#define CONF_DMAC_CHANNEL_17_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_17 +#ifndef CONF_DMAC_BURSTSIZE_17 +#define CONF_DMAC_BURSTSIZE_17 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_17 +#ifndef CONF_DMAC_CHUNKSIZE_17 +#define CONF_DMAC_CHUNKSIZE_17 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_17 +#ifndef CONF_DMAC_BEATSIZE_17 +#define CONF_DMAC_BEATSIZE_17 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_17 +#ifndef CONF_DMAC_SRC_INTERFACE_17 +#define CONF_DMAC_SRC_INTERFACE_17 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_17 +#ifndef CONF_DMAC_DES_INTERFACE_17 +#define CONF_DMAC_DES_INTERFACE_17 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_17 +#ifndef CONF_DMAC_SRCINC_17 +#define CONF_DMAC_SRCINC_17 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_17 +#ifndef CONF_DMAC_DSTINC_17 +#define CONF_DMAC_DSTINC_17 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_17 +#ifndef CONF_DMAC_TRANS_TYPE_17 +#define CONF_DMAC_TRANS_TYPE_17 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_17 +#ifndef CONF_DMAC_TRIGSRC_17 +#define CONF_DMAC_TRIGSRC_17 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_17 == 0 +#define CONF_DMAC_TYPE_17 0 +#define CONF_DMAC_DSYNC_17 0 +#elif CONF_DMAC_TRANS_TYPE_17 == 1 +#define CONF_DMAC_TYPE_17 1 +#define CONF_DMAC_DSYNC_17 0 +#elif CONF_DMAC_TRANS_TYPE_17 == 2 +#define CONF_DMAC_TYPE_17 1 +#define CONF_DMAC_DSYNC_17 1 +#endif + +#if CONF_DMAC_TRIGSRC_17 == 0xFF +#define CONF_DMAC_SWREQ_17 1 +#else +#define CONF_DMAC_SWREQ_17 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_17_SETTINGS == 1 && CONF_DMAC_BEATSIZE_17 != 2 \ + && ((!CONF_DMAC_SRCINC_17) || (!CONF_DMAC_DSTINC_17))) +#if (!CONF_DMAC_SRCINC_17) +#define CONF_DMAC_SRC_STRIDE_17 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_17) +#define CONF_DMAC_DES_STRIDE_17 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_17 +#define CONF_DMAC_SRC_STRIDE_17 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_17 +#define CONF_DMAC_DES_STRIDE_17 0 +#endif + +// Channel 18 settings +// dmac_channel_18_settings +#ifndef CONF_DMAC_CHANNEL_18_SETTINGS +#define CONF_DMAC_CHANNEL_18_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_18 +#ifndef CONF_DMAC_BURSTSIZE_18 +#define CONF_DMAC_BURSTSIZE_18 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_18 +#ifndef CONF_DMAC_CHUNKSIZE_18 +#define CONF_DMAC_CHUNKSIZE_18 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_18 +#ifndef CONF_DMAC_BEATSIZE_18 +#define CONF_DMAC_BEATSIZE_18 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_18 +#ifndef CONF_DMAC_SRC_INTERFACE_18 +#define CONF_DMAC_SRC_INTERFACE_18 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_18 +#ifndef CONF_DMAC_DES_INTERFACE_18 +#define CONF_DMAC_DES_INTERFACE_18 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_18 +#ifndef CONF_DMAC_SRCINC_18 +#define CONF_DMAC_SRCINC_18 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_18 +#ifndef CONF_DMAC_DSTINC_18 +#define CONF_DMAC_DSTINC_18 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_18 +#ifndef CONF_DMAC_TRANS_TYPE_18 +#define CONF_DMAC_TRANS_TYPE_18 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_18 +#ifndef CONF_DMAC_TRIGSRC_18 +#define CONF_DMAC_TRIGSRC_18 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_18 == 0 +#define CONF_DMAC_TYPE_18 0 +#define CONF_DMAC_DSYNC_18 0 +#elif CONF_DMAC_TRANS_TYPE_18 == 1 +#define CONF_DMAC_TYPE_18 1 +#define CONF_DMAC_DSYNC_18 0 +#elif CONF_DMAC_TRANS_TYPE_18 == 2 +#define CONF_DMAC_TYPE_18 1 +#define CONF_DMAC_DSYNC_18 1 +#endif + +#if CONF_DMAC_TRIGSRC_18 == 0xFF +#define CONF_DMAC_SWREQ_18 1 +#else +#define CONF_DMAC_SWREQ_18 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_18_SETTINGS == 1 && CONF_DMAC_BEATSIZE_18 != 2 \ + && ((!CONF_DMAC_SRCINC_18) || (!CONF_DMAC_DSTINC_18))) +#if (!CONF_DMAC_SRCINC_18) +#define CONF_DMAC_SRC_STRIDE_18 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_18) +#define CONF_DMAC_DES_STRIDE_18 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_18 +#define CONF_DMAC_SRC_STRIDE_18 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_18 +#define CONF_DMAC_DES_STRIDE_18 0 +#endif + +// Channel 19 settings +// dmac_channel_19_settings +#ifndef CONF_DMAC_CHANNEL_19_SETTINGS +#define CONF_DMAC_CHANNEL_19_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_19 +#ifndef CONF_DMAC_BURSTSIZE_19 +#define CONF_DMAC_BURSTSIZE_19 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_19 +#ifndef CONF_DMAC_CHUNKSIZE_19 +#define CONF_DMAC_CHUNKSIZE_19 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_19 +#ifndef CONF_DMAC_BEATSIZE_19 +#define CONF_DMAC_BEATSIZE_19 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_19 +#ifndef CONF_DMAC_SRC_INTERFACE_19 +#define CONF_DMAC_SRC_INTERFACE_19 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_19 +#ifndef CONF_DMAC_DES_INTERFACE_19 +#define CONF_DMAC_DES_INTERFACE_19 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_19 +#ifndef CONF_DMAC_SRCINC_19 +#define CONF_DMAC_SRCINC_19 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_19 +#ifndef CONF_DMAC_DSTINC_19 +#define CONF_DMAC_DSTINC_19 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_19 +#ifndef CONF_DMAC_TRANS_TYPE_19 +#define CONF_DMAC_TRANS_TYPE_19 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_19 +#ifndef CONF_DMAC_TRIGSRC_19 +#define CONF_DMAC_TRIGSRC_19 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_19 == 0 +#define CONF_DMAC_TYPE_19 0 +#define CONF_DMAC_DSYNC_19 0 +#elif CONF_DMAC_TRANS_TYPE_19 == 1 +#define CONF_DMAC_TYPE_19 1 +#define CONF_DMAC_DSYNC_19 0 +#elif CONF_DMAC_TRANS_TYPE_19 == 2 +#define CONF_DMAC_TYPE_19 1 +#define CONF_DMAC_DSYNC_19 1 +#endif + +#if CONF_DMAC_TRIGSRC_19 == 0xFF +#define CONF_DMAC_SWREQ_19 1 +#else +#define CONF_DMAC_SWREQ_19 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_19_SETTINGS == 1 && CONF_DMAC_BEATSIZE_19 != 2 \ + && ((!CONF_DMAC_SRCINC_19) || (!CONF_DMAC_DSTINC_19))) +#if (!CONF_DMAC_SRCINC_19) +#define CONF_DMAC_SRC_STRIDE_19 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_19) +#define CONF_DMAC_DES_STRIDE_19 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_19 +#define CONF_DMAC_SRC_STRIDE_19 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_19 +#define CONF_DMAC_DES_STRIDE_19 0 +#endif + +// Channel 20 settings +// dmac_channel_20_settings +#ifndef CONF_DMAC_CHANNEL_20_SETTINGS +#define CONF_DMAC_CHANNEL_20_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_20 +#ifndef CONF_DMAC_BURSTSIZE_20 +#define CONF_DMAC_BURSTSIZE_20 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_20 +#ifndef CONF_DMAC_CHUNKSIZE_20 +#define CONF_DMAC_CHUNKSIZE_20 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_20 +#ifndef CONF_DMAC_BEATSIZE_20 +#define CONF_DMAC_BEATSIZE_20 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_20 +#ifndef CONF_DMAC_SRC_INTERFACE_20 +#define CONF_DMAC_SRC_INTERFACE_20 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_20 +#ifndef CONF_DMAC_DES_INTERFACE_20 +#define CONF_DMAC_DES_INTERFACE_20 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_20 +#ifndef CONF_DMAC_SRCINC_20 +#define CONF_DMAC_SRCINC_20 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_20 +#ifndef CONF_DMAC_DSTINC_20 +#define CONF_DMAC_DSTINC_20 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_20 +#ifndef CONF_DMAC_TRANS_TYPE_20 +#define CONF_DMAC_TRANS_TYPE_20 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_20 +#ifndef CONF_DMAC_TRIGSRC_20 +#define CONF_DMAC_TRIGSRC_20 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_20 == 0 +#define CONF_DMAC_TYPE_20 0 +#define CONF_DMAC_DSYNC_20 0 +#elif CONF_DMAC_TRANS_TYPE_20 == 1 +#define CONF_DMAC_TYPE_20 1 +#define CONF_DMAC_DSYNC_20 0 +#elif CONF_DMAC_TRANS_TYPE_20 == 2 +#define CONF_DMAC_TYPE_20 1 +#define CONF_DMAC_DSYNC_20 1 +#endif + +#if CONF_DMAC_TRIGSRC_20 == 0xFF +#define CONF_DMAC_SWREQ_20 1 +#else +#define CONF_DMAC_SWREQ_20 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_20_SETTINGS == 1 && CONF_DMAC_BEATSIZE_20 != 2 \ + && ((!CONF_DMAC_SRCINC_20) || (!CONF_DMAC_DSTINC_20))) +#if (!CONF_DMAC_SRCINC_20) +#define CONF_DMAC_SRC_STRIDE_20 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_20) +#define CONF_DMAC_DES_STRIDE_20 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_20 +#define CONF_DMAC_SRC_STRIDE_20 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_20 +#define CONF_DMAC_DES_STRIDE_20 0 +#endif + +// Channel 21 settings +// dmac_channel_21_settings +#ifndef CONF_DMAC_CHANNEL_21_SETTINGS +#define CONF_DMAC_CHANNEL_21_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_21 +#ifndef CONF_DMAC_BURSTSIZE_21 +#define CONF_DMAC_BURSTSIZE_21 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_21 +#ifndef CONF_DMAC_CHUNKSIZE_21 +#define CONF_DMAC_CHUNKSIZE_21 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_21 +#ifndef CONF_DMAC_BEATSIZE_21 +#define CONF_DMAC_BEATSIZE_21 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_21 +#ifndef CONF_DMAC_SRC_INTERFACE_21 +#define CONF_DMAC_SRC_INTERFACE_21 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_21 +#ifndef CONF_DMAC_DES_INTERFACE_21 +#define CONF_DMAC_DES_INTERFACE_21 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_21 +#ifndef CONF_DMAC_SRCINC_21 +#define CONF_DMAC_SRCINC_21 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_21 +#ifndef CONF_DMAC_DSTINC_21 +#define CONF_DMAC_DSTINC_21 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_21 +#ifndef CONF_DMAC_TRANS_TYPE_21 +#define CONF_DMAC_TRANS_TYPE_21 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_21 +#ifndef CONF_DMAC_TRIGSRC_21 +#define CONF_DMAC_TRIGSRC_21 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_21 == 0 +#define CONF_DMAC_TYPE_21 0 +#define CONF_DMAC_DSYNC_21 0 +#elif CONF_DMAC_TRANS_TYPE_21 == 1 +#define CONF_DMAC_TYPE_21 1 +#define CONF_DMAC_DSYNC_21 0 +#elif CONF_DMAC_TRANS_TYPE_21 == 2 +#define CONF_DMAC_TYPE_21 1 +#define CONF_DMAC_DSYNC_21 1 +#endif + +#if CONF_DMAC_TRIGSRC_21 == 0xFF +#define CONF_DMAC_SWREQ_21 1 +#else +#define CONF_DMAC_SWREQ_21 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_21_SETTINGS == 1 && CONF_DMAC_BEATSIZE_21 != 2 \ + && ((!CONF_DMAC_SRCINC_21) || (!CONF_DMAC_DSTINC_21))) +#if (!CONF_DMAC_SRCINC_21) +#define CONF_DMAC_SRC_STRIDE_21 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_21) +#define CONF_DMAC_DES_STRIDE_21 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_21 +#define CONF_DMAC_SRC_STRIDE_21 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_21 +#define CONF_DMAC_DES_STRIDE_21 0 +#endif + +// Channel 22 settings +// dmac_channel_22_settings +#ifndef CONF_DMAC_CHANNEL_22_SETTINGS +#define CONF_DMAC_CHANNEL_22_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_22 +#ifndef CONF_DMAC_BURSTSIZE_22 +#define CONF_DMAC_BURSTSIZE_22 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_22 +#ifndef CONF_DMAC_CHUNKSIZE_22 +#define CONF_DMAC_CHUNKSIZE_22 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_22 +#ifndef CONF_DMAC_BEATSIZE_22 +#define CONF_DMAC_BEATSIZE_22 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_22 +#ifndef CONF_DMAC_SRC_INTERFACE_22 +#define CONF_DMAC_SRC_INTERFACE_22 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_22 +#ifndef CONF_DMAC_DES_INTERFACE_22 +#define CONF_DMAC_DES_INTERFACE_22 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_22 +#ifndef CONF_DMAC_SRCINC_22 +#define CONF_DMAC_SRCINC_22 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_22 +#ifndef CONF_DMAC_DSTINC_22 +#define CONF_DMAC_DSTINC_22 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_22 +#ifndef CONF_DMAC_TRANS_TYPE_22 +#define CONF_DMAC_TRANS_TYPE_22 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_22 +#ifndef CONF_DMAC_TRIGSRC_22 +#define CONF_DMAC_TRIGSRC_22 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_22 == 0 +#define CONF_DMAC_TYPE_22 0 +#define CONF_DMAC_DSYNC_22 0 +#elif CONF_DMAC_TRANS_TYPE_22 == 1 +#define CONF_DMAC_TYPE_22 1 +#define CONF_DMAC_DSYNC_22 0 +#elif CONF_DMAC_TRANS_TYPE_22 == 2 +#define CONF_DMAC_TYPE_22 1 +#define CONF_DMAC_DSYNC_22 1 +#endif + +#if CONF_DMAC_TRIGSRC_22 == 0xFF +#define CONF_DMAC_SWREQ_22 1 +#else +#define CONF_DMAC_SWREQ_22 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_22_SETTINGS == 1 && CONF_DMAC_BEATSIZE_22 != 2 \ + && ((!CONF_DMAC_SRCINC_22) || (!CONF_DMAC_DSTINC_22))) +#if (!CONF_DMAC_SRCINC_22) +#define CONF_DMAC_SRC_STRIDE_22 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_22) +#define CONF_DMAC_DES_STRIDE_22 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_22 +#define CONF_DMAC_SRC_STRIDE_22 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_22 +#define CONF_DMAC_DES_STRIDE_22 0 +#endif + +// Channel 23 settings +// dmac_channel_23_settings +#ifndef CONF_DMAC_CHANNEL_23_SETTINGS +#define CONF_DMAC_CHANNEL_23_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_23 +#ifndef CONF_DMAC_BURSTSIZE_23 +#define CONF_DMAC_BURSTSIZE_23 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_23 +#ifndef CONF_DMAC_CHUNKSIZE_23 +#define CONF_DMAC_CHUNKSIZE_23 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_23 +#ifndef CONF_DMAC_BEATSIZE_23 +#define CONF_DMAC_BEATSIZE_23 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_23 +#ifndef CONF_DMAC_SRC_INTERFACE_23 +#define CONF_DMAC_SRC_INTERFACE_23 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_23 +#ifndef CONF_DMAC_DES_INTERFACE_23 +#define CONF_DMAC_DES_INTERFACE_23 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_23 +#ifndef CONF_DMAC_SRCINC_23 +#define CONF_DMAC_SRCINC_23 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_23 +#ifndef CONF_DMAC_DSTINC_23 +#define CONF_DMAC_DSTINC_23 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_23 +#ifndef CONF_DMAC_TRANS_TYPE_23 +#define CONF_DMAC_TRANS_TYPE_23 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_23 +#ifndef CONF_DMAC_TRIGSRC_23 +#define CONF_DMAC_TRIGSRC_23 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_23 == 0 +#define CONF_DMAC_TYPE_23 0 +#define CONF_DMAC_DSYNC_23 0 +#elif CONF_DMAC_TRANS_TYPE_23 == 1 +#define CONF_DMAC_TYPE_23 1 +#define CONF_DMAC_DSYNC_23 0 +#elif CONF_DMAC_TRANS_TYPE_23 == 2 +#define CONF_DMAC_TYPE_23 1 +#define CONF_DMAC_DSYNC_23 1 +#endif + +#if CONF_DMAC_TRIGSRC_23 == 0xFF +#define CONF_DMAC_SWREQ_23 1 +#else +#define CONF_DMAC_SWREQ_23 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_23_SETTINGS == 1 && CONF_DMAC_BEATSIZE_23 != 2 \ + && ((!CONF_DMAC_SRCINC_23) || (!CONF_DMAC_DSTINC_23))) +#if (!CONF_DMAC_SRCINC_23) +#define CONF_DMAC_SRC_STRIDE_23 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_23) +#define CONF_DMAC_DES_STRIDE_23 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_23 +#define CONF_DMAC_SRC_STRIDE_23 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_23 +#define CONF_DMAC_DES_STRIDE_23 0 +#endif + +// + +// <<< end of configuration section >>> + +#endif // HPL_XDMAC_CONFIG_H diff --git a/hw/bsp/same70_qmtech/peripheral_clk_config.h b/hw/bsp/same70_qmtech/peripheral_clk_config.h new file mode 100644 index 000000000..84756f5ac --- /dev/null +++ b/hw/bsp/same70_qmtech/peripheral_clk_config.h @@ -0,0 +1,126 @@ +/* Auto-generated config file peripheral_clk_config.h */ +#ifndef PERIPHERAL_CLK_CONFIG_H +#define PERIPHERAL_CLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +/** + * \def CONF_HCLK_FREQUENCY + * \brief HCLK's Clock frequency + */ +#ifndef CONF_HCLK_FREQUENCY +#define CONF_HCLK_FREQUENCY 300000000 +#endif + +/** + * \def CONF_FCLK_FREQUENCY + * \brief FCLK's Clock frequency + */ +#ifndef CONF_FCLK_FREQUENCY +#define CONF_FCLK_FREQUENCY 300000000 +#endif + +/** + * \def CONF_CPU_FREQUENCY + * \brief CPU's Clock frequency + */ +#ifndef CONF_CPU_FREQUENCY +#define CONF_CPU_FREQUENCY 300000000 +#endif + +/** + * \def CONF_SLCK_FREQUENCY + * \brief Slow Clock frequency + */ +#define CONF_SLCK_FREQUENCY 0 + +/** + * \def CONF_MCK_FREQUENCY + * \brief Master Clock frequency + */ +#define CONF_MCK_FREQUENCY 150000000 + +/** + * \def CONF_PCK6_FREQUENCY + * \brief Programmable Clock Controller 6 frequency + */ +#define CONF_PCK6_FREQUENCY 1714285 + +// USART Clock Settings +// USART Clock source + +// <0=> Master Clock (MCK) +// <1=> MCK / 8 for USART +// <2=> Programmable Clock Controller 4 (PMC_PCK4) +// <3=> External Clock +// This defines the clock source for the USART +// usart_clock_source +#ifndef CONF_USART1_CK_SRC +#define CONF_USART1_CK_SRC 0 +#endif + +// USART External Clock Input on SCK <1-4294967295> +// Inputs the external clock frequency on SCK +// usart_clock_freq +#ifndef CONF_USART1_SCK_FREQ +#define CONF_USART1_SCK_FREQ 10000000 +#endif + +// + +/** + * \def USART FREQUENCY + * \brief USART's Clock frequency + */ +#ifndef CONF_USART1_FREQUENCY +#define CONF_USART1_FREQUENCY 150000000 +#endif + +#ifndef CONF_SRC_USB_480M +#define CONF_SRC_USB_480M 0 +#endif + +#ifndef CONF_SRC_USB_48M +#define CONF_SRC_USB_48M 1 +#endif + +// USB Full/Low Speed Clock +// USB Clock Controller (USB_48M) +// usb_fsls_clock_source +// 48MHz clock source for low speed and full speed. +// It must be available when low speed is supported by host driver. +// It must be available when low power mode is selected. +#ifndef CONF_USBHS_FSLS_SRC +#define CONF_USBHS_FSLS_SRC CONF_SRC_USB_48M +#endif + +// USB Clock Source(Normal/Low-power Mode Selection) +// USB High Speed Clock (USB_480M) +// USB Clock Controller (USB_48M) +// usb_clock_source +// Select the clock source for USB. +// In normal mode, use "USB High Speed Clock (USB_480M)". +// In low-power mode, use "USB Clock Controller (USB_48M)". +#ifndef CONF_USBHS_SRC +#define CONF_USBHS_SRC CONF_SRC_USB_480M +#endif + +/** + * \def CONF_USBHS_FSLS_FREQUENCY + * \brief USBHS's Full/Low Speed Clock Source frequency + */ +#ifndef CONF_USBHS_FSLS_FREQUENCY +#define CONF_USBHS_FSLS_FREQUENCY 48000000 +#endif + +/** + * \def CONF_USBHS_FREQUENCY + * \brief USBHS's Selected Clock Source frequency + */ +#ifndef CONF_USBHS_FREQUENCY +#define CONF_USBHS_FREQUENCY 480000000 +#endif + +// <<< end of configuration section >>> + +#endif // PERIPHERAL_CLK_CONFIG_H diff --git a/hw/bsp/same70_qmtech/same70_qmtech.c b/hw/bsp/same70_qmtech/same70_qmtech.c new file mode 100644 index 000000000..6e6ad0602 --- /dev/null +++ b/hw/bsp/same70_qmtech/same70_qmtech.c @@ -0,0 +1,159 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019, hathach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + */ + +#include "sam.h" +#include "bsp/board.h" + +#include "peripheral_clk_config.h" +#include "hpl/usart/hpl_usart_base.h" +#include "hpl/pmc/hpl_pmc.h" +#include "hal/include/hal_init.h" +#include "hal/include/hal_usart_async.h" +#include "hal/include/hal_gpio.h" + + +// You can get the board here: +// https://www.aliexpress.com/item/1005003173783268.html + +//--------------------------------------------------------------------+ +// MACRO TYPEDEF CONSTANT ENUM DECLARATION +//--------------------------------------------------------------------+ + +#define LED_PIN GPIO(GPIO_PORTA, 15) + +#define BUTTON_PIN GPIO(GPIO_PORTA, 21) +#define BUTTON_STATE_ACTIVE 0 + +#define UART_TX_PIN GPIO(GPIO_PORTB, 1) +#define UART_RX_PIN GPIO(GPIO_PORTB, 0) + +static struct usart_async_descriptor edbg_com; +static uint8_t edbg_com_buffer[64]; +static volatile bool uart_busy = false; + +static void tx_cb_EDBG_COM(const struct usart_async_descriptor *const io_descr) +{ + (void) io_descr; + uart_busy = false; +} + +//------------- IMPLEMENTATION -------------// +void board_init(void) +{ + init_mcu(); + + /* Disable Watchdog */ + hri_wdt_set_MR_WDDIS_bit(WDT); + + // LED + _pmc_enable_periph_clock(ID_PIOB); + gpio_set_pin_level(LED_PIN, false); + gpio_set_pin_direction(LED_PIN, GPIO_DIRECTION_OUT); + gpio_set_pin_function(LED_PIN, GPIO_PIN_FUNCTION_OFF); + + // Button + _pmc_enable_periph_clock(ID_PIOA); + gpio_set_pin_direction(BUTTON_PIN, GPIO_DIRECTION_IN); + gpio_set_pin_pull_mode(BUTTON_PIN, GPIO_PULL_UP); + gpio_set_pin_function(BUTTON_PIN, GPIO_PIN_FUNCTION_OFF); + + // Uart via EDBG Com + _pmc_enable_periph_clock(ID_USART1); + gpio_set_pin_function(UART_RX_PIN, MUX_PA21A_USART1_RXD1); + gpio_set_pin_function(UART_TX_PIN, MUX_PB4D_USART1_TXD1); + + usart_async_init(&edbg_com, USART1, edbg_com_buffer, sizeof(edbg_com_buffer), _usart_get_usart_async()); + usart_async_set_baud_rate(&edbg_com, CFG_BOARD_UART_BAUDRATE); + usart_async_register_callback(&edbg_com, USART_ASYNC_TXC_CB, tx_cb_EDBG_COM); + usart_async_enable(&edbg_com); + +#if CFG_TUSB_OS == OPT_OS_NONE + // 1ms tick timer (samd SystemCoreClock may not correct) + SysTick_Config(CONF_CPU_FREQUENCY / 1000); +#endif + + // Enable USB clock + _pmc_enable_periph_clock(ID_USBHS); + +} + +//--------------------------------------------------------------------+ +// USB Interrupt Handler +//--------------------------------------------------------------------+ +void USBHS_Handler(void) +{ + tud_int_handler(0); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +void board_led_write(bool state) +{ + gpio_set_pin_level(LED_PIN, state); +} + +uint32_t board_button_read(void) +{ + return BUTTON_STATE_ACTIVE == gpio_get_pin_level(BUTTON_PIN); +} + +int board_uart_read(uint8_t* buf, int len) +{ + (void) buf; (void) len; + return 0; +} + +int board_uart_write(void const * buf, int len) +{ + // while until previous transfer is complete + while(uart_busy) {} + uart_busy = true; + + io_write(&edbg_com.io, buf, len); + return len; +} + +#if CFG_TUSB_OS == OPT_OS_NONE +volatile uint32_t system_ticks = 0; + +void SysTick_Handler (void) +{ + system_ticks++; +} + +uint32_t board_millis(void) +{ + return system_ticks; +} +#endif + +// Required by __libc_init_array in startup code if we are compiling using +// -nostdlib/-nostartfiles. +void _init(void) +{ + +} -- cgit v1.3.1 From db862ae72501a726cb70571395725a1938c6dcc1 Mon Sep 17 00:00:00 2001 From: szymonh <12231135+szymonh@users.noreply.github.com> Date: Mon, 27 Sep 2021 21:11:44 +0200 Subject: Assure msc device block size is not zero --- src/class/msc/msc_device.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c index 0fd592129..b65abe979 100644 --- a/src/class/msc/msc_device.c +++ b/src/class/msc/msc_device.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) @@ -187,6 +187,11 @@ uint8_t rdwr10_validate_cmd(msc_cbw_t const* cbw) TU_LOG(MSC_DEBUG, " SCSI case 4 Hi > Dn\r\n"); status = MSC_CSW_STATUS_FAILED; } + else if ( SCSI_CMD_READ_10 == cbw->command[0] && cbw->total_bytes / block_count == 0) + { + TU_LOG(MSC_DEBUG, " Computed block size 0\r\n"); + status = MSC_CSW_STATUS_FAILED; + } } return status; -- cgit v1.3.1 From bbb68ffefbe867e26795567269f4815257d883f0 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 29 Sep 2021 14:55:20 +0700 Subject: remove official mm32sdk submodule --- .gitmodules | 3 --- hw/mcu/mindmotion/mm32sdk | 1 - 2 files changed, 4 deletions(-) delete mode 160000 hw/mcu/mindmotion/mm32sdk diff --git a/.gitmodules b/.gitmodules index 4c86fd55c..538b4ed66 100644 --- a/.gitmodules +++ b/.gitmodules @@ -121,9 +121,6 @@ [submodule "hw/mcu/nxp/nxp_sdk"] path = hw/mcu/nxp/nxp_sdk url = https://github.com/hathach/nxp_sdk.git -[submodule "hw/mcu/mindmotion/mm32sdk"] - path = hw/mcu/mindmotion/mm32sdk - url = https://github.com/zhangslice/mm32sdk.git [submodule "hw/mcu/gd/nuclei-sdk"] path = hw/mcu/gd/nuclei-sdk url = https://github.com/Nuclei-Software/nuclei-sdk.git diff --git a/hw/mcu/mindmotion/mm32sdk b/hw/mcu/mindmotion/mm32sdk deleted file mode 160000 index b6b99de3a..000000000 --- a/hw/mcu/mindmotion/mm32sdk +++ /dev/null @@ -1 +0,0 @@ -Subproject commit b6b99de3ab26218784ec158488bdd91377288f94 -- cgit v1.3.1 From 7af57e41b51bb491b064786748301a0a7b7365b4 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 29 Sep 2021 14:58:47 +0700 Subject: add submodule hathach/mm32sdk --- .gitmodules | 3 +++ hw/mcu/mindmotion/mm32sdk | 1 + 2 files changed, 4 insertions(+) create mode 160000 hw/mcu/mindmotion/mm32sdk diff --git a/.gitmodules b/.gitmodules index 538b4ed66..5f5bee56c 100644 --- a/.gitmodules +++ b/.gitmodules @@ -124,3 +124,6 @@ [submodule "hw/mcu/gd/nuclei-sdk"] path = hw/mcu/gd/nuclei-sdk url = https://github.com/Nuclei-Software/nuclei-sdk.git +[submodule "hw/mcu/mindmotion/mm32sdk"] + path = hw/mcu/mindmotion/mm32sdk + url = https://github.com/hathach/mm32sdk.git diff --git a/hw/mcu/mindmotion/mm32sdk b/hw/mcu/mindmotion/mm32sdk new file mode 160000 index 000000000..6512211cc --- /dev/null +++ b/hw/mcu/mindmotion/mm32sdk @@ -0,0 +1 @@ +Subproject commit 6512211cc9e7b0219b88d837a6e44f0bb661e1f5 -- cgit v1.3.1 From 3eeb79be4f54b8ab954ae2542e211bc37575e2bf Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 29 Sep 2021 15:20:14 +0700 Subject: update mm32sdk submodule --- hw/mcu/mindmotion/mm32sdk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/mcu/mindmotion/mm32sdk b/hw/mcu/mindmotion/mm32sdk index 6512211cc..708a71529 160000 --- a/hw/mcu/mindmotion/mm32sdk +++ b/hw/mcu/mindmotion/mm32sdk @@ -1 +1 @@ -Subproject commit 6512211cc9e7b0219b88d837a6e44f0bb661e1f5 +Subproject commit 708a7152952ac595d24837069dcc0f7f59a4c30b -- cgit v1.3.1 From f3c1b2a60da15d0466d3e076726c868989b77b3b Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 29 Sep 2021 15:31:03 +0700 Subject: clean up --- src/class/cdc/cdc_device.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/class/cdc/cdc_device.h b/src/class/cdc/cdc_device.h index 72e29705a..fbc7162a3 100644 --- a/src/class/cdc/cdc_device.h +++ b/src/class/cdc/cdc_device.h @@ -82,7 +82,7 @@ int32_t tud_cdc_n_read_char (uint8_t itf); void tud_cdc_n_read_flush (uint8_t itf); // Get a byte from FIFO at the specified position without removing it -bool tud_cdc_n_peek (uint8_t itf, uint8_t* uv8); +bool tud_cdc_n_peek (uint8_t itf, uint8_t* ui8); // Write bytes to TX FIFO, data may remain in the FIFO for a while uint32_t tud_cdc_n_write (uint8_t itf, void const* buffer, uint32_t bufsize); @@ -116,7 +116,7 @@ static inline uint32_t tud_cdc_available (void); static inline int32_t tud_cdc_read_char (void); static inline uint32_t tud_cdc_read (void* buffer, uint32_t bufsize); static inline void tud_cdc_read_flush (void); -static inline bool tud_cdc_peek (uint8_t* u8); +static inline bool tud_cdc_peek (uint8_t* ui8); static inline uint32_t tud_cdc_write_char (char ch); static inline uint32_t tud_cdc_write (void const* buffer, uint32_t bufsize); @@ -206,9 +206,9 @@ static inline void tud_cdc_read_flush (void) tud_cdc_n_read_flush(0); } -static inline bool tud_cdc_peek (uint8_t* uv8) +static inline bool tud_cdc_peek (uint8_t* ui8) { - return tud_cdc_n_peek(0, uv8); + return tud_cdc_n_peek(0, ui8); } static inline uint32_t tud_cdc_write_char (char ch) -- cgit v1.3.1 From b5b03e6c7f598a0ba8540d19acf798e35d24faf9 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 29 Sep 2021 15:33:44 +0700 Subject: add mm32 to ci build, also re-enable esp32s3 --- .github/workflows/build.yml | 1 + .github/workflows/build_esp.yml | 3 +-- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 8ef19b0a0..1ef0bf5ea 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -44,6 +44,7 @@ jobs: - 'lpc18' - 'lpc54' - 'lpc55' + - 'mm32' - 'nrf' - 'rp2040' - 'samd11' diff --git a/.github/workflows/build_esp.yml b/.github/workflows/build_esp.yml index 25f4e68f8..93d582361 100644 --- a/.github/workflows/build_esp.yml +++ b/.github/workflows/build_esp.yml @@ -18,8 +18,7 @@ jobs: # ESP32-S2 - 'espressif_saola_1' # ESP32-S3 - # latest IDF does not define USB0 in linker - #- 'espressif_addax_1' + - 'espressif_addax_1' steps: - name: Setup Python -- cgit v1.3.1 From 2f2fb3d8d92f35c756d66db0eb256037f0a7d62f Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 29 Sep 2021 16:18:11 +0700 Subject: clean up --- .../audio_4_channel_mic/src/usb_descriptors.c | 2 ++ examples/device/audio_test/src/usb_descriptors.c | 13 +++++++--- examples/device/uac2_headset/src/usb_descriptors.c | 29 ++++++++++++---------- src/class/vendor/vendor_device.c | 2 +- 4 files changed, 28 insertions(+), 18 deletions(-) diff --git a/examples/device/audio_4_channel_mic/src/usb_descriptors.c b/examples/device/audio_4_channel_mic/src/usb_descriptors.c index 2b66bfe34..b6a5bd5c2 100644 --- a/examples/device/audio_4_channel_mic/src/usb_descriptors.c +++ b/examples/device/audio_4_channel_mic/src/usb_descriptors.c @@ -85,9 +85,11 @@ enum // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ... #define EPNUM_AUDIO 0x03 + #elif TU_CHECK_MCU(NRF5X) // nRF5x ISO can only be endpoint 8 #define EPNUM_AUDIO 0x08 + #else #define EPNUM_AUDIO 0x01 #endif diff --git a/examples/device/audio_test/src/usb_descriptors.c b/examples/device/audio_test/src/usb_descriptors.c index a4e9dc8e1..348f5eede 100644 --- a/examples/device/audio_test/src/usb_descriptors.c +++ b/examples/device/audio_test/src/usb_descriptors.c @@ -82,11 +82,16 @@ enum #define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + CFG_TUD_AUDIO * TUD_AUDIO_MIC_ONE_CH_DESC_LEN) #if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX -// LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number -// 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ... -#define EPNUM_AUDIO 0x03 + // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number + // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ... + #define EPNUM_AUDIO 0x03 + +#elif TU_CHECK_MCU(NRF5X) + // nRF5x ISO can only be endpoint 8 + #define EPNUM_AUDIO 0x08 + #else -#define EPNUM_AUDIO 0x01 + #define EPNUM_AUDIO 0x01 #endif uint8_t const desc_configuration[] = diff --git a/examples/device/uac2_headset/src/usb_descriptors.c b/examples/device/uac2_headset/src/usb_descriptors.c index 64fa3c25b..9e97845b8 100644 --- a/examples/device/uac2_headset/src/usb_descriptors.c +++ b/examples/device/uac2_headset/src/usb_descriptors.c @@ -77,22 +77,25 @@ uint8_t const * tud_descriptor_device_cb(void) #define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + CFG_TUD_AUDIO * TUD_AUDIO_HEADSET_STEREO_DESC_LEN) #if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX -// LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number -// 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ... -#define EPNUM_AUDIO_IN 0x03 -#define EPNUM_AUDIO_OUT 0x03 + // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number + // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ... + #define EPNUM_AUDIO_IN 0x03 + #define EPNUM_AUDIO_OUT 0x03 + #elif CFG_TUSB_MCU == OPT_MCU_NRF5X -// ISO endpoints for NRF5x are fixed to 0x08 (0x88) -#define EPNUM_AUDIO_IN 0x08 -#define EPNUM_AUDIO_OUT 0x08 + // ISO endpoints for NRF5x are fixed to 0x08 (0x88) + #define EPNUM_AUDIO_IN 0x08 + #define EPNUM_AUDIO_OUT 0x08 + #elif CFG_TUSB_MCU == OPT_MCU_SAMG || CFG_TUSB_MCU == OPT_MCU_SAMX7X -// SAMG & SAME70 don't support a same endpoint number with different direction IN and OUT -// e.g EP1 OUT & EP1 IN cannot exist together -#define EPNUM_AUDIO_IN 0x01 -#define EPNUM_AUDIO_OUT 0x02 + // SAMG & SAME70 don't support a same endpoint number with different direction IN and OUT + // e.g EP1 OUT & EP1 IN cannot exist together + #define EPNUM_AUDIO_IN 0x01 + #define EPNUM_AUDIO_OUT 0x02 + #else -#define EPNUM_AUDIO_IN 0x01 -#define EPNUM_AUDIO_OUT 0x01 + #define EPNUM_AUDIO_IN 0x01 + #define EPNUM_AUDIO_OUT 0x01 #endif uint8_t const desc_configuration[] = diff --git a/src/class/vendor/vendor_device.c b/src/class/vendor/vendor_device.c index c73ca2538..188b561d7 100644 --- a/src/class/vendor/vendor_device.c +++ b/src/class/vendor/vendor_device.c @@ -216,7 +216,7 @@ uint16_t vendord_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, ui if ( p_vendor->ep_in ) maybe_transmit(p_vendor); } - return (uint16_t) true; + return drv_len; } bool vendord_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) -- cgit v1.3.1 From 1d5bdf7d396afe22b114f6f8edf45cbc3d88325b Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 29 Sep 2021 16:29:15 +0700 Subject: add same7x to board list --- docs/reference/supported.rst | 6 ++++++ src/class/vendor/vendor_device.c | 2 ++ 2 files changed, 8 insertions(+) diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst index daf5bce75..c8a441f18 100644 --- a/docs/reference/supported.rst +++ b/docs/reference/supported.rst @@ -175,6 +175,12 @@ SAMD51 & SAME54 - `D5035-01 `__ - `Microchip SAME54 Xplained Pro `__ +SAME7x +^^^^^^ + +- `Microchip SAME70 Xplained `_ +- `QMTECH ATSAME70N19 `_ + SAMG ^^^^ diff --git a/src/class/vendor/vendor_device.c b/src/class/vendor/vendor_device.c index 188b561d7..8f25141b8 100644 --- a/src/class/vendor/vendor_device.c +++ b/src/class/vendor/vendor_device.c @@ -207,6 +207,8 @@ uint16_t vendord_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, ui // Open endpoint pair with usbd helper TU_ASSERT(usbd_open_edpt_pair(rhport, p_desc, desc_itf->bNumEndpoints, TUSB_XFER_BULK, &p_vendor->ep_out, &p_vendor->ep_in), 0); + drv_len += desc_itf->bNumEndpoints*sizeof(tusb_desc_endpoint_t); + // Prepare for incoming data if ( p_vendor->ep_out ) { -- cgit v1.3.1 From 97d5d1e491565d6d546bcf27af1ff3525f3df722 Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Sat, 17 Jul 2021 18:51:33 +0900 Subject: add files for video class device --- src/class/video/video.h | 284 ++++++++++++++++++++++++++++++ src/class/video/video_device.c | 384 +++++++++++++++++++++++++++++++++++++++++ src/class/video/video_device.h | 50 ++++++ src/device/usbd.c | 12 ++ src/tusb.h | 4 + src/tusb_option.h | 4 + 6 files changed, 738 insertions(+) create mode 100644 src/class/video/video.h create mode 100644 src/class/video/video_device.c create mode 100644 src/class/video/video_device.h diff --git a/src/class/video/video.h b/src/class/video/video.h new file mode 100644 index 000000000..55ffffa7f --- /dev/null +++ b/src/class/video/video.h @@ -0,0 +1,284 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Koji KITAYAMA + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef TUSB_VIDEO_H_ +#define TUSB_VIDEO_H_ + +#include "common/tusb_common.h" + +/* A.2 */ +typedef enum { + VIDEO_SUBCLASS_UNDEFINED = 0x00, + VIDEO_SUBCLASS_CONTROL, + VIDEO_SUBCLASS_STREAMING, + VIDEO_SUBCLASS_INTERFACE_COLLECTION, +} video_subclass_type_t; + +/* A.3 */ +typedef enum +{ + VIDEO_INT_PROTOCOL_CODE_UNDEF = 0x00, + VIDEO_INT_PROTOCOL_CODE_15, +} video_interface_protocol_code_t; + +/* A.5 */ +typedef enum +{ + VIDEO_CS_VC_INTERFACE_VC_DESCRIPTOR_UNDEF = 0x00, + VIDEO_CS_VC_INTERFACE_HEADER, + VIDEO_CS_VC_INTERFACE_INPUT_TERMINAL, + VIDEO_CS_VC_INTERFACE_OUTPUT_TERMINAL, + VIDEO_CS_VC_INTERFACE_SELECTOR_UNIT, + VIDEO_CS_VC_INTERFACE_PROCESSING_UNIT, + VIDEO_CS_VC_INTERFACE_EXTENSION_UNIT, + VIDEO_CS_VC_INTERFACE_ENCODING_UNIT, +} vide_cs_vc_interface_subtype_t; + +/* A.6 */ +typedef enum +{ + VIDEO_CS_VS_INTERFACE_VS_DESCRIPTOR_UNDEF = 0x00, + VIDEO_CS_VS_INTERFACE_INPUT_HEADER, + VIDEO_CS_VS_INTERFACE_OUTPUT_HEADER, + VIDEO_CS_VS_INTERFACE_STILL_IMAGE_FRAME, + VIDEO_CS_VS_INTERFACE_FORMAT_UNCOMPRESSED, + VIDEO_CS_VS_INTERFACE_FRAME_UNCOMPRESSED, + VIDEO_CS_VS_INTERFACE_FORMAT_MJPEG, + VIDEO_CS_VS_INTERFACE_FRAME_MJPEG, + VIDEO_CS_VS_INTERFACE_FORMAT_MPEG2TS = 0x0A, + VIDEO_CS_VS_INTERFACE_FORMAT_DV = 0x0c, + VIDEO_CS_VS_INTERFACE_COLORFORMAT, + VIDEO_CS_VS_INTERFACE_FORMAT_FRAME_BASED = 0x10, + VIDEO_CS_VS_INTERFACE_FRAME_FRAME_BASED, + VIDEO_CS_VS_INTERFACE_FORMAT_STREAM_BASED, + VIDEO_CS_VS_INTERFACE_FORMAT_H264, + VIDEO_CS_VS_INTERFACE_FRAME_H264, + VIDEO_CS_VS_INTERFACE_FORMAT_H264_SIMULCAST, + VIDEO_CS_VS_INTERFACE_FORMAT_VP8, + VIDEO_CS_VS_INTERFACE_FRAME_VP8, + VIDEO_CS_VS_INTERFACE_FORMAT_VP8_SIMULCAST, +} video_cs_vs_interface_subtype_t; + +/* A.8 */ +typedef enum +{ + VIDEO_REQUEST_UNDEF = 0x00, + VIDEO_REQUEST_SET_CUR, + VIDEO_REQUEST_SET_CUR_ALL = 0x11, + VIDEO_REQUEST_GET = 0x80, + VIDEO_REQUEST_GET_CUR, + VIDEO_REQUEST_GET_MIN, + VIDEO_REQUEST_GET_MAX, + VIDEO_REQUEST_GET_RES, + VIDEO_REQUEST_GET_LEN, + VIDEO_REQUEST_GET_INFO, + VIDEO_REQUEST_GET_DEF, + VIDEO_REQUEST_GET_CUR_ALL = 0x91, + VIDEO_REQUEST_GET_MIN_ALL, + VIDEO_REQUEST_GET_MAX_ALL, + VIDEO_REQUEST_GET_RES_ALL, + VIDEO_REQUEST_GET_DEF_ALL = 0x97 +} video_control_request_t; + +/* B. Terminal Types */ +typedef enum +{ + VIDEO_TT_VENDOR_SPECIFIC = 0x0100, + VIDEO_TT_STREAMING, + VIDEO_ITT_VENDOR_SPECIFIC = 0x0200, + VIDEO_ITT_CAMERA, + VIDEO_ITT_MEDIA_TRANSPORT_INPUT, + VIDEO_OTT_VENDOR_SPECIFIC = 0x0300, + VIDEO_OTT_DISPLAY, + VIDEO_OTT_MEDIA_TRANSPORT_OUTPUT, + VIDEO_TT_EXTERNAL_VENDOR_SPEIFIC = 0x0400, + VIDEO_TT_COMPOSITE_CONNECTOR, + VIDEO_TT_SVIDEO_CONNECTOR, + VIDEO_TT_COMPONENT_CONNECTOR, +} video_terminal_type_t; + +/* 2.3.4.2 */ +typedef struct TU_ATTR_PACKED { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint16_t bcdUVC; + uint16_t wTotalLength; + uint32_t dwClockFrequency; + uint8_t bInCollection; + uint8_t baInterfaceNr[]; +} tusb_desc_video_control_interface_t; + +/* 3.9.2.1 */ +typedef struct TU_ATTR_PACKED { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bNumFormats; + uint16_t wTotalLength; + uint8_t bEndpointAddress; + uint8_t bmInfo; + uint8_t bTerminalLink; + uint8_t bStillCaptureMethod; + uint8_t bTriggerSupport; + uint8_t bTriggerUsage; + uint8_t bControlSize; + uint8_t bmaControls[]; +} tusb_desc_video_streaming_interface_input_t; + +/* 3.9.2.2 */ +typedef struct TU_ATTR_PACKED { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bNumFormats; + uint16_t wTotalLength; + uint8_t bEndpointAddress; + uint8_t bTerminalLink; + uint8_t bControlSize; + uint8_t bmaControls[]; +} tusb_desc_video_streaming_interface_output_t; + +typedef struct TU_ATTR_PACKED { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bNumFormats; + uint16_t wTotalLength; + uint8_t bEndpointAddress; + union { + struct { + uint8_t bmInfo; + uint8_t bTerminalLink; + uint8_t bStillCaptureMethod; + uint8_t bTriggerSupport; + uint8_t bTriggerUsage; + uint8_t bControlSize; + uint8_t bmaControls[]; + } in; + struct { + uint8_t bEndpointAddress; + uint8_t bTerminalLink; + uint8_t bControlSize; + uint8_t bmaControls[]; + } out; +} tusb_desc_video_streaming_interface_t; + +#define TUD_VIDEO_DESC_IAD_LEN 8 +#define TUD_VIDEO_DESC_STD_VC_LEN 9 +#define TUD_VIDEO_DESC_CS_VC_LEN 12 +#define TUD_VIDEO_DESC_INPUT_TERM_LEN 8 +#define TUD_VIDEO_DESC_OUTPUT_TERM_LEN 9 +#define TUD_VIDEO_DESC_STD_VS_LEN 9 +#define TUD_VIDEO_DESC_CS_VS_IN_LEN 13 +#define TUD_VIDEO_DESC_CS_VS_OUT_LEN 9 +#define TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN 27 +#define TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN 38 +#define TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_DISC_LEN 26 + +/* 2.2 compression formats */ +#define TUD_VIDEO_GUID_YUY2 0x59,0x55,0x59,0x32,0x00,0x00,0x10,0x00,0x00,0x80,0x71,0x9B,0x38,0x00,0xAA,0x00 +#define TUD_VIDEO_GUID_NV12 0x4E,0x56,0x31,0x32,0x00,0x00,0x10,0x00,0x00,0x80,0x71,0x9B,0x38,0x00,0xAA,0x00 +#define TUD_VIDEO_GUID_M420 0x4D,0x34,0x32,0x30,0x00,0x00,0x10,0x00,0x00,0x80,0x71,0x9B,0x38,0x00,0xAA,0x00 +#define TUD_VIDEO_GUID_I420 0x49,0x34,0x32,0x30,0x00,0x00,0x10,0x00,0x00,0x80,0x71,0x9B,0x38,0x00,0xAA,0x00 + +#define TUD_VIDEO_DESC_IAD(_firstitfs, _nitfs, _stridx) \ + TUD_VIDEO_DESC_IAD_LEN, TUSB_DESC_INTERFACE_ASSOCIATION, \ + _firstitfs, _nitfs, TUSB_CLASS_VIDEO, VIDEO_SUBCLASS_INTERFACE_COLLECTION, \ + VIDEO_INT_PROTOCOL_CODE_UNDEF, _stridx + +#define TUD_VIDEO_DESC_STD_VC(_itfnum, _nEPs, _stridx) \ + TUD_VIDEO_DESC_STD_VC_LEN, TUSB_DESC_INTERFACE, _itfnum, /* fixed to zero */ 0x00, \ + _nEPs, TUSB_CLASS_VIDEO, VIDEO_SUBCLASS_CONTROL, VIDEO_INT_PROTOCOL_CODE_15, _stridx + +/* 3.7.2 */ +#define TUD_VIDEO_DESC_CS_VC(_bcdUVC, _totallen, _clkfreq, _coll, ...) \ + TUD_VIDEO_DESC_CS_VC_LEN + _coll, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VC_INTERFACE_HEADER, \ + U16_TO_U8S_LE(_bcdUVC), U16_TO_U8S_LE(_totallen + TUD_VIDEO_DESC_CS_AC_LEN), \ + U32_TO_U8S_LE(_clkfreq), _coll, __VA_ARGS__ + +/* 3.7.2.1 */ +#define TUD_VIDEO_DESC_INPUT_TERM(_tid, _tt, _at, _stridx) \ + TUD_VIDEO_DESC_INPUT_TERM_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VC_INTERFACE_INPUT_TERMINAL, \ + _tid, U16_TO_U8S_LE(_tt), _at, _ti + +/* 3.7.2.2 */ +#define TUD_VIDEO_DESC_OUTPUT_TERM(_tid, _tt, _at, _srcid, _stridx) \ + TUD_VIDEO_DESC_INPUT_TERM_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VC_INTERFACE_OUTPUT_TERMINAL, \ + _tid, U16_TO_U8S_LE(_tt), _at, _ti + +/* 3.9.1 */ +#define TUD_VIDEO_DESC_STD_VS(_itfnum, _alt, _epn, _stridx) \ + TUD_VIDEO_DESC_STD_VC_LEN, TUSB_DESC_INTERFACE, _itfnum, _alt, \ + _epn, TUSB_CLASS_VIDEO, VIDEO_SUBCLASS_STREAMING, VIDEO_INT_PROTOCOL_CODE_15, _stridx + +/* 3.9.2.1 */ +#define TUD_VIDEO_DESC_CS_VS_INPUT(_numfmt, _totlen, _epn, _inf, _termlnk, _sticaptmeth, _trgspt, _trgusg, _ctlsz, ...) \ + TUD_VIDEO_DESC_CS_VS_IN_LEN + (_numfmt) * (_ctlsz), TUSB_DESC_CS_INTERFACE, \ + VIDEO_CS_VS_INTERFACE_INPUT_HEADER, _numfmt, \ + U16_TO_U8S_LE(_totlen + TUD_VIDEO_DESC_CS_VS_IN_LEN + (_numfmt) * (_ctlsz)), \ + _epn, _inf, _termlnk, _sticaptmeth, _trgspt, _trgusg, _ctlsz, __VA_ARGS__ + +/* 3.9.2.2 */ +#define TUD_VIDEO_DESC_CS_VS_OUTPUT(_numfmt, _totlen, _epn, _inf, _termlnk, _ctlsz, ...) \ + TUD_VIDEO_DESC_CS_VS_OUT_LEN + (_numfmt) * (_ctlsz), TUSB_DESC_CS_INTERFACE, \ + VIDEO_CS_VS_INTERFACE_OUTPUT_HEADER, _numfmt, \ + U16_TO_U8S_LE(_totlen + TUD_VIDEO_DESC_CS_VS_OUT_LEN + (_numfmt) * (_ctlsz)), \ + _epn, _inf, _termlnk, _trgusg, _ctlsz, __VA_ARGS__ + +/* Uncompressed 3.1.1 */ +#define TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR(_fmtidx, _numfrmdesc, \ + _g0,_g1,_g2,_g3,_g4,_g5,_g6,_g7,_g8,_g9,_g10,_g11,_g12,_g13,_g14,_g15, \ + _bitsperpix, _frmidx, _asrx, _asry, _interlace, _cp) \ + TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_INTERFACE_FORMAT_UNCOMPRESSED, \ + _fmtidx, _numfrmdesc,\ + _g0,_g1,_g2,_g3,_g4,_g5,_g6,_g7,_g8,_g9,_g10,_g11,_g12,_g13,_g14,_g15,\ + _bitsperpix, _frmidx, _asrx, _asry, _interlace, _cp + +/* Uncompressed 3.1.2 Table 3-3 */ +#define TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT(_frmidx, _cap, _width, _height, _minbr, _maxbr, _maxfrmbufsz, _frminterval, _minfrminterval, _maxfrminterval, _frmintervalstep) \ + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_INTERFACE_FRAME_UNCOMPRESSED, \ + _frmidx, _cap, U16_TO_U8S_LE(_width), U16_TO_U8S_LE(_height), U32_TO_U8S_LE(_minbr), U32_TO_U8S_LE(_maxbr), \ + U32_TO_U8S_LE(_maxfrmbufsz), U32_TO_U8S_LE(_frminterval), 0, \ + U32_TO_U8S_LE(_minfrminterval), U32_TO_U8S_LE(_maxfrminterval), U32_TO_U8S_LE(_frmintervalstep) + +/* Uncompressed 3.1.2 Table 3-4 */ +#define TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_DISC(_frmidx, _cap, _width, _height, _minbr, _maxbr, _maxfrmbufsz, _frminterval, _numfrminterval, ...) \ + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_DISC_LEN + _numfrminterval * 4, \ + TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_INTERFACE_FRAME_UNCOMPRESSED, \ + _frmidx, _cap, U16_TO_U8S_LE(_width), U16_TO_U8S_LE(_height), U32_TO_U8S_LE(_minbr), U32_TO_U8S_LE(_maxbr), \ + U32_TO_U8S_LE(_maxfrmbufsz), U32_TO_U8S_LE(_frminterval), _numfrminterval, __VA_ARGS__ + +/* 3.10.1.1 */ +#define TUD_VIDEO_DESC_EP_ISO(_ep, _epsize, _ep_interval) + 7, TUSB_DESC_ENDPOINT, _ep, TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS,\ + U16_TO_U8S_LE(_epsize), _ep_interval + +/* 3.10.1.2 */ +#define TUD_VIDEO_DESC_EP_BULK(_ep, _epsize, _ep_interval) + 7, TUSB_DESC_ENDPOINT, _ep, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), _ep_interval + +#endif diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c new file mode 100644 index 000000000..12526f43b --- /dev/null +++ b/src/class/video/video_device.c @@ -0,0 +1,384 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * Copyright (c) 2020 Reinhard Panhuber, Jerzy Kasenberg + * Copyright (c) 2021 Koji KITAYAMA + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "tusb_option.h" + +#if (TUSB_OPT_DEVICE_ENABLED && CFG_TUD_VIDEO) + +#include "device/usbd.h" +#include "device/usbd_pvt.h" + +#include "video_device.h" + +//--------------------------------------------------------------------+ +// MACRO CONSTANT TYPEDEF +//--------------------------------------------------------------------+ +typedef struct +{ + uint8_t itf_ctl; + uint8_t itf_in; + uint8_t itf_out; + uint8_t const *desc_beg; + uint8_t const *desc_end; + tusb_desc_video_control_interface_t const *ctl; + tusb_desc_video_streaming_interface_input_t const *stm_in; + tusb_desc_video_streaming_interface_output_t const *stm_out; + uint8_t ep_notif; /* notification */ + uint8_t ep_in; /* video IN */ + uint8_t ep_sti; /* still image IN */ + uint8_t ep_out; /* video OUT */ + + /*------------- From this point, data is not cleared by bus reset -------------*/ + + // Endpoint Transfer buffer + CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUD_CDC_EP_BUFSIZE]; + CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUD_CDC_EP_BUFSIZE]; + +} videod_interface_t; + +#define ITF_MEM_RESET_SIZE offsetof(cdcd_interface_t, wanted_char) + +//--------------------------------------------------------------------+ +// INTERNAL OBJECT & FUNCTION DECLARATION +//--------------------------------------------------------------------+ +CFG_TUSB_MEM_SECTION static videod_interface_t _videod_itf[CFG_TUD_VIDEO]; + +static tusb_desc_interface_t const* videod_next_interface_desc(void const *beg, void const *end) +{ + for (void const *cur = tu_desc_next(beg); cur < end; cur = tu_desc_next(cur)) { + if (TUSB_DESC_INTERFACE != tu_desc_type(cur)) + return (uint8_t const*)cur; + } +} + +static tusb_desc_interface_t const* videod_find_interface_desc(void const *beg, void const *end, unsigned itfnum) +{ + tusb_desc_interface_t const *cur = (tusb_desc_interface_t const *)beg; + for (; cur; cur = videod_next_interface_desc(cur, end)) { + if (cur->bInterfaceNumber == itfnum) + return cur; + } + return NULL; +} + +static void _prep_out_transaction (cdcd_interface_t* p_cdc) +{ + uint8_t const rhport = TUD_OPT_RHPORT; + uint16_t available = tu_fifo_remaining(&p_cdc->rx_ff); + + // Prepare for incoming data but only allow what we can store in the ring buffer. + // TODO Actually we can still carry out the transfer, keeping count of received bytes + // and slowly move it to the FIFO when read(). + // This pre-check reduces endpoint claiming + TU_VERIFY(available >= sizeof(p_cdc->epout_buf), ); + + // claim endpoint + TU_VERIFY(usbd_edpt_claim(rhport, p_cdc->ep_out), ); + + // fifo can be changed before endpoint is claimed + available = tu_fifo_remaining(&p_cdc->rx_ff); + + if ( available >= sizeof(p_cdc->epout_buf) ) + { + usbd_edpt_xfer(rhport, p_cdc->ep_out, p_cdc->epout_buf, sizeof(p_cdc->epout_buf)); + }else + { + // Release endpoint since we don't make any transfer + usbd_edpt_release(rhport, p_cdc->ep_out); + } +} + +//--------------------------------------------------------------------+ +// APPLICATION API +//--------------------------------------------------------------------+ +bool tud_video_n_connected(uint8_t itf) +{ + // DTR (bit 0) active is considered as connected + return tud_ready() && tu_bit_test(_cdcd_itf[itf].line_state, 0); +} + +//--------------------------------------------------------------------+ +// READ API +//--------------------------------------------------------------------+ + +//--------------------------------------------------------------------+ +// WRITE API +//--------------------------------------------------------------------+ + +//--------------------------------------------------------------------+ +// USBD Driver API +//--------------------------------------------------------------------+ +void videod_init(void) +{ + tu_memclr(_videod_itf, sizeof(_videod_itf)); + + for (unsigned i = 0; i < CFG_TUD_VIDEO; ++i) + { + videod_interface_t* p_video = &_videod_itf[i]; + + // TODO + } +} + +void videod_reset(uint8_t rhport) +{ + (void) rhport; + + for (unsigned i = 0; i < CFG_TUD_VIDEO; ++i) + { + videod_interface_t* p_video = &_videod_itf[i]; + + // TODO + tu_memclr(p_video, ITF_MEM_RESET_SIZE); + } +} + +uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len) +{ + TU_VERIFY(TUSB_CLASS_VIDEO == itf_desc->bInterfaceClass && + VIDEO_SUBCLASS_CONTROL == itf_desc->bInterfaceSubClass && + VIDEO_INT_PROTOCOL_CODE_15 == itf_desc->bFunctionProtool, 0); + + /* Find available interface */ + videod_interface_t *p_video = NULL; + for (unsigned video_id = 0; video_id < CFG_TUD_VIDEO; ++video_id) { + if (!_videod_itf[video_id].itf_in && !_videod_itf[video_id].itf_out) { + p_video = &_videod_itf[video_id]; + break; + } + } + TU_ASSERT(p_video, 0); + + /*------------- Video Control Interface -------------*/ + TU_VERIFY(itf_desc->bNumEndpoints < 2, 0); /* support only 1 notification endpoint */ + unsigned itf_ctl = itf_desc->bInterfaceNumber; + unsigned drv_len = sizeof(*itf_desc); + tusb_desc_endpoint_t const * desc_ep = NULL; + + uint8_t const *p_desc = tu_desc_next(itf_desc); + tusb_desc_video_control_interface_t const *ctl = (tusb_desc_video_control_interface_t const*)p_desc; + TU_VERIFY(TUSB_DESC_CS_INTERFACE == ctl->bDescriptorType && + VIDEO_CS_VC_INTERFACE_HEADER == ctl->bDescriptorSubType, 0); + + if (itf_desc->bNumEndpoints) { /* has a notification endpoint */ + p_desc = tu_desc_next(ctl); + /* skip to the notification endpoint descriptor */ + while (TUSB_DESC_ENDPOINT != tu_desc_type(p_desc) && drv_len <= max_len ) { + p_desc = tu_desc_next(p_desc); + } + desc_ep = (tusb_desc_endpoint_t const *)p_desc; + } + drv_len += tu_desc_len(ctl) + ctl->wTotalLength; + p_desc = tu_desc_next(ctl) + ctl->wTotalLength; + TU_VERIFY(drv_len <= max_len, 0); + + /*------------- Video Stream Interface -------------*/ + uint8_t itf_in = 0, itf_out = 0; + tusb_desc_video_streaming_interface_input_t const *stm_in = NULL; + tusb_desc_video_streaming_interface_output_t const *stm_out = NULL; + + for (unsigned itf_stm = 0; itf_stm < ctl->bInCollection; ++itf_stm) { + itf_desc = (tusb_desc_interface_t const *)p_desc; + TU_VERIFY(TUSB_DESC_INTERFACE == itf_desc->bDescriptorType && + 0 == itf_desc->bInterfaceNumber && + TUSB_CLASS_VIDEO == itf_desc->bInterfaceClass && + VIDEO_SUBCLASS_STREAMING == itf_desc->bInterfaceSubClass && + VIDEO_INT_PROTOCOL_CODE_15 == itf_desc->bFunctionProtool && + 0 == itf_desc->bNumEndpoints, 0); + drv_len += sizeof(*itf_desc); + p_desc = tu_desc_next(itf_desc); + TU_VERIFY(TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc)); + tusb_desc_video_streaming_interface_t const *stm = (tusb_desc_video_streaming_interface_t const *)p_desc; + TU_VERIFY(TUSB_DESC_CS_INTERFACE == stm->bDescriptorType); + switch (stm->bDescriptorSubType) { + default: return 0; + case VIDEO_CS_VS_INTERFACE_INPUT_HEADER: + TU_VERIFY(0 == itf_in, 0); + itf_in = itf_desc->bInterfaceNumber; + stm_in = (tusb_desc_video_streaming_interface_input_t const*)stm; + break; + case VIDEO_CS_VS_INTERFACE_OUTPUT_HEADER: + TU_VERIFY(0 == itf_out, 0); + itf_out = itf_desc->bInterfaceNumber; + stm_out = (tusb_desc_video_streaming_interface_output_t const*)stm; + break; + } + drv_len += tu_desc_len(stm) + stm->wTotalLength; + p_desc = tu_desc_next(stm) + ctl->wTotalLength; + } + if (desc_ep) { + /* open the notification endpoint */ + TU_ASSERT( usbd_edpt_open(rhport, desc_ep), 0); + p_video->ep_notif = desc_ep->bEndpointAddress; + } + p_video->itf_ctl = itf_ctl; + p_video->itf_in = itf_in; + p_video->itf_out = itf_out; + p_video->ctl = ctl; + p_video->stm_in = stm_in; + p_video->stm_out = stm_out; + + return drv_len; +} + +// Invoked when a control transfer occurred on an interface of this class +// Driver response accordingly to the request and the transfer stage (setup/data/ack) +// return false to stall control endpoint (e.g unsupported request) +bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request) +{ + /* Standard request */ + if (p_request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD) { + tusb_desc_interface_t const *itf; + unsigned itf; + switch (p_request->bRequest) { + case TUSB_REQ_GET_INTERFACE: + itf = tu_u16_low(p_request->wIndex); + return audiod_get_interface(rhport, p_request); + case TUSB_REQ_SET_INTERFACE: + itf = videod_find_interface_desc(void const *beg, void const *end, unsigned itfnum) + itf = tu_u16_low(p_request->wIndex); + + return audiod_set_interface(rhport, p_request); + /* Unknown/Unsupported request */ + default: TU_BREAKPOINT(); return false; + } + } + + uint8_t itf = 0; + videod_interface_t* p_video = _videod_itf; + + // Identify which interface to use + for ( ; ; itf++, p_video++) { + if (itf >= TU_ARRAY_SIZE(_videod_itf)) return false; + if ( p_video->itf_num == request->wIndex ) break; + } + + if (stage == CONTROL_STAGE_SETUP) { + TU_VERIFY((TUSB_DIR_IN_MASK & request->bmRequestType) == + (TUSB_DIR_IN_MASK & request->bRequest)); + } + + + unsigned cs = TU_U16_HIGH(request->wValue); + + + unsigned req = request->bRequest; + switch (request->bRequest) { + case VIDEO_REQUEST_GET_INFO: + TU_VERIFY(1 == request->wLength); + + break; + case VIDEO_REQUEST_SET_CUR: + if (stage == CONTROL_STAGE_SETUP) { + TU_LOG2(" Set Current Setting Attribute\r\n"); + tud_control_xfer(rhport, request, &p_video->line_coding, sizeof(cdc_line_coding_t)); + } else if ( stage == CONTROL_STAGE_ACK) { + if ( tud_cdc_line_coding_cb ) tud_cdc_line_coding_cb(itf, &p_video->line_coding); + } + break; + case VIDEO_REQUEST_GET_CUR: + if (stage == CONTROL_STAGE_SETUP) { + TU_LOG2(" Set Current Setting Attribute\r\n"); + tud_control_xfer(rhport, request, &p_video->line_coding, sizeof(cdc_line_coding_t)); + } else if ( stage == CONTROL_STAGE_ACK) { + if ( tud_cdc_line_coding_cb ) tud_cdc_line_coding_cb(itf, &p_video->line_coding); + } + break; + default: return false; // stall unsupported request + } + + return true; +} + +bool videod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) +{ + (void) result; + + uint8_t itf; + videod_interface_t* p_video; + + // Identify which interface to use + for (itf = 0; itf < CFG_TUD_CDC; itf++) + { + p_video = &_videod_itf[itf]; + if ( ( ep_addr == p_video->ep_out ) || ( ep_addr == p_video->ep_in ) ) break; + } + TU_ASSERT(itf < CFG_TUD_CDC); + + // Received new data + if ( ep_addr == p_video->ep_out ) + { + tu_fifo_write_n(&p_video->rx_ff, &p_video->epout_buf, xferred_bytes); + + // Check for wanted char and invoke callback if needed + if ( tud_cdc_rx_wanted_cb && (((signed char) p_video->wanted_char) != -1) ) + { + for ( uint32_t i = 0; i < xferred_bytes; i++ ) + { + if ( (p_video->wanted_char == p_video->epout_buf[i]) && !tu_fifo_empty(&p_video->rx_ff) ) + { + tud_cdc_rx_wanted_cb(itf, p_video->wanted_char); + } + } + } + + // invoke receive callback (if there is still data) + if (tud_cdc_rx_cb && !tu_fifo_empty(&p_video->rx_ff) ) tud_cdc_rx_cb(itf); + + // prepare for OUT transaction + _prep_out_transaction(p_video); + } + + // Data sent to host, we continue to fetch from tx fifo to send. + // Note: This will cause incorrect baudrate set in line coding. + // Though maybe the baudrate is not really important !!! + if ( ep_addr == p_video->ep_in ) + { + // invoke transmit callback to possibly refill tx fifo + if ( tud_cdc_tx_complete_cb ) tud_cdc_tx_complete_cb(itf); + + if ( 0 == tud_cdc_n_write_flush(itf) ) + { + // If there is no data left, a ZLP should be sent if + // xferred_bytes is multiple of EP Packet size and not zero + if ( !tu_fifo_count(&p_video->tx_ff) && xferred_bytes && (0 == (xferred_bytes & (BULK_PACKET_SIZE-1))) ) + { + if ( usbd_edpt_claim(rhport, p_video->ep_in) ) + { + usbd_edpt_xfer(rhport, p_video->ep_in, NULL, 0); + } + } + } + } + + // nothing to do with notif endpoint for now + + return true; +} + +#endif diff --git a/src/class/video/video_device.h b/src/class/video/video_device.h new file mode 100644 index 000000000..b077a9a76 --- /dev/null +++ b/src/class/video/video_device.h @@ -0,0 +1,50 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * Copyright (c) 2021 Koji KITAYAMA + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef TUSB_VIDEO_DEVICE_H_ +#define TUSB_VIDEO_DEVICE_H_ + +#include "video_device.h" + +#ifdef __cplusplus + extern "C" { +#endif + +//--------------------------------------------------------------------+ +// INTERNAL USBD-CLASS DRIVER API +//--------------------------------------------------------------------+ +void videod_init (void); +void videod_reset (uint8_t rhport); +uint16_t videod_open (uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len); +bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request); +bool videod_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes); + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/src/device/usbd.c b/src/device/usbd.c index cf3ecea42..87f0e05ca 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -143,6 +143,18 @@ static usbd_class_driver_t const _usbd_driver[] = }, #endif + #if CFG_TUD_VIDEO + { + DRIVER_NAME("VIDEO") + .init = videod_init, + .reset = videod_reset, + .open = videod_open, + .control_xfer_cb = videod_control_xfer_cb, + .xfer_cb = videod_xfer_cb, + .sof = NULL + }, + #endif + #if CFG_TUD_MIDI { DRIVER_NAME("MIDI") diff --git a/src/tusb.h b/src/tusb.h index b52f8839a..f2f72a510 100644 --- a/src/tusb.h +++ b/src/tusb.h @@ -80,6 +80,10 @@ #include "class/audio/audio_device.h" #endif + #if CFG_TUD_VIDEO + #include "class/video/video_device.h" + #endif + #if CFG_TUD_MIDI #include "class/midi/midi_device.h" #endif diff --git a/src/tusb_option.h b/src/tusb_option.h index ad2a26a66..a728581f6 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -241,6 +241,10 @@ #define CFG_TUD_AUDIO 0 #endif +#ifndef CFG_TUD_VIDEO + #define CFG_TUD_VIDEO 0 +#endif + #ifndef CFG_TUD_MIDI #define CFG_TUD_MIDI 0 #endif -- cgit v1.3.1 From e8de4113223f2a435bde87c13a4d99c1d886619f Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Mon, 19 Jul 2021 21:28:05 +0900 Subject: cleanup open() --- src/class/video/video.h | 20 +- src/class/video/video_device.c | 450 ++++++++++++++++++++++++++++++----------- src/class/video/video_device.h | 13 +- 3 files changed, 358 insertions(+), 125 deletions(-) diff --git a/src/class/video/video.h b/src/class/video/video.h index 55ffffa7f..f994c7fed 100644 --- a/src/class/video/video.h +++ b/src/class/video/video.h @@ -103,6 +103,14 @@ typedef enum VIDEO_REQUEST_GET_DEF_ALL = 0x97 } video_control_request_t; +/* A.9 */ +typedef enum +{ + VIDEO_CTL_SEL_UNDEF = 0x00, + VIDEO_CTL_SEL_VIDEO_POWER_MODE_CONTROL, + VIDEO_CTL_SEL_REQUEST_ERROR_CODE_CONTROL, +} video_interface_control_selector_t; + /* B. Terminal Types */ typedef enum { @@ -130,7 +138,7 @@ typedef struct TU_ATTR_PACKED { uint32_t dwClockFrequency; uint8_t bInCollection; uint8_t baInterfaceNr[]; -} tusb_desc_video_control_interface_t; +} tusb_desc_cs_video_ctl_itf_hdr_t; /* 3.9.2.1 */ typedef struct TU_ATTR_PACKED { @@ -147,7 +155,7 @@ typedef struct TU_ATTR_PACKED { uint8_t bTriggerUsage; uint8_t bControlSize; uint8_t bmaControls[]; -} tusb_desc_video_streaming_interface_input_t; +} tusb_desc_cs_video_stm_itf_in_hdr_t; /* 3.9.2.2 */ typedef struct TU_ATTR_PACKED { @@ -160,7 +168,7 @@ typedef struct TU_ATTR_PACKED { uint8_t bTerminalLink; uint8_t bControlSize; uint8_t bmaControls[]; -} tusb_desc_video_streaming_interface_output_t; +} tusb_desc_cs_video_stm_itf_out_hdr_t; typedef struct TU_ATTR_PACKED { uint8_t bLength; @@ -178,14 +186,14 @@ typedef struct TU_ATTR_PACKED { uint8_t bTriggerUsage; uint8_t bControlSize; uint8_t bmaControls[]; - } in; + } input; struct { uint8_t bEndpointAddress; uint8_t bTerminalLink; uint8_t bControlSize; uint8_t bmaControls[]; - } out; -} tusb_desc_video_streaming_interface_t; + } output; +} tusb_desc_cs_video_stm_itf_hdr_t; #define TUD_VIDEO_DESC_IAD_LEN 8 #define TUD_VIDEO_DESC_STD_VC_LEN 9 diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index 12526f43b..637e7a127 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -38,16 +38,38 @@ //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF //--------------------------------------------------------------------+ +typedef struct { + uint8_t num; + uint8_t alt; +} itf_setting_t; + +typedef struct { + tusb_desc_interface_t std; + tusb_desc_cs_video_ctl_itf_hdr_t ctl; +} tusb_desc_vc_itf_t; + +typedef struct { + tusb_desc_interface_t std; + tusb_desc_cs_video_stm_itf_hdr_t stm; +} tusb_desc_vs_itf_t; + +typedef struct TU_ATTR_PACKED { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + union { + uint8_t bId; + uint8_t bTerminalId; + uint8_t bUnitId; + }; +} tusb_desc_cs_video_entity_itf_t; + typedef struct { - uint8_t itf_ctl; - uint8_t itf_in; - uint8_t itf_out; - uint8_t const *desc_beg; - uint8_t const *desc_end; - tusb_desc_video_control_interface_t const *ctl; - tusb_desc_video_streaming_interface_input_t const *stm_in; - tusb_desc_video_streaming_interface_output_t const *stm_out; + void const *beg; + void const *end; + tusb_desc_vc_itf_t const *vc; /* current video control interface */ + tusb_desc_vs_itf_t const *vs[2]; /* current video streaming interfaces */ uint8_t ep_notif; /* notification */ uint8_t ep_in; /* video IN */ uint8_t ep_sti; /* still image IN */ @@ -68,24 +90,266 @@ typedef struct //--------------------------------------------------------------------+ CFG_TUSB_MEM_SECTION static videod_interface_t _videod_itf[CFG_TUD_VIDEO]; -static tusb_desc_interface_t const* videod_next_interface_desc(void const *beg, void const *end) +/** Find the first descriptor with the specified descriptor type. + * + * @param[in] beg The head of descriptor byte array. + * @param[in] end The tail of descriptor byte array. + * @param[in] target The target descriptor type. + * + * @return The pointer for interface descriptor. + * @retval end did not found interface descriptor */ +static void const* videod_find_desc(void const *beg, void const *end, uint8_t target) { - for (void const *cur = tu_desc_next(beg); cur < end; cur = tu_desc_next(cur)) { - if (TUSB_DESC_INTERFACE != tu_desc_type(cur)) + for (void const *cur = beg; cur < end; cur = tu_desc_next(cur)) { + if (target != tu_desc_type(cur)) return (uint8_t const*)cur; } + return end; +} + +/** Find the first interface descriptor with the specified interface number and alternate setting number. + * + * @param[in] beg The head of descriptor byte array. + * @param[in] end The tail of descriptor byte array. + * @param[in] itfnum The target interface number. + * @param[in] altnum The target alternate setting number. + * + * @return The pointer for interface descriptor. + * @retval end did not found interface descriptor */ +static void const* videod_find_desc_itf(void const *beg, void const *end, unsigned itfnum, unsigned altnum) +{ + for (void const *cur = beg; cur < end; cur = videod_find_desc(cur, end, TUSB_DESC_INTERFACE)) { + tusb_desc_interface_t const *itf = (tusb_desc_interface_t const *)cur; + if (itf->bInterfaceNumber == itfnum && itf->bAlternateSettings == altnum) { + return itf; + } + cur = tu_desc_next(cur); + } + return end; +} + +/** Find the first input or output terminal descriptor with the specified terminal id. + * + * @param[in] beg The head of descriptor byte array. + * @param[in] end The tail of descriptor byte array. + * @param[in] termid The target terminal id. + * + * @return The pointer for interface descriptor. + * @retval end did not found interface descriptor */ +static void const* videod_find_desc_term(void const *beg, void const *end, unsigned termid) +{ + for (void const *cur = beg; cur < end; cur = videod_find_desc(cur, end, TUSB_DESC_CS_INTERFACE)) { + tusb_desc_cs_video_entity_itf_t const *itf = (tusb_desc_cs_video_entity_itf_t const *)cur; + if ((VIDEO_CS_VC_INTERFACE_INPUT_TERMINAL == itf->bDescriptorSubtype || + VIDEO_CS_VC_INTERFACE_OUTPUT_TERMINAL == itf->bDescriptorSubtype) && + itf->bTerminalId == termid) { + return itf; + } + cur = tu_desc_next(cur); + } + return end; +} + +/** Find the first selector/processing/extension/encoding unit descriptor with the specified unit id. + * + * @param[in] beg The head of descriptor byte array. + * @param[in] end The tail of descriptor byte array. + * @param[in] unitid The target unit id. + * + * @return The pointer for interface descriptor. + * @retval end did not found interface descriptor */ +static void const* videod_find_desc_unit(void const *beg, void const *end, unsigned unitid) +{ + for (void const *cur = beg; cur < end; cur = videod_find_desc(cur, end, TUSB_DESC_CS_INTERFACE)) { + tusb_desc_cs_video_entity_itf_t const *itf = (tusb_desc_cs_video_entity_itf_t const *)cur; + if (VIDEO_CS_VC_INTERFACE_SELECTOR_UNIT <= itf->bDescriptorSubtype && + itf->bDescriptorSubtype <= VIDEO_CS_VC_INTERFACE_ENCODING_UNIT && + itf->bUnitId == unitid) { + return itf; + } + cur = tu_desc_next(cur); + } + return end; } -static tusb_desc_interface_t const* videod_find_interface_desc(void const *beg, void const *end, unsigned itfnum) +/** Set the specified alternate setting to own video control interface. + * + * @param[in,out] self The context. + * @param[in] altnum The target alternate setting number. + * + * @return The next descriptor after the video control interface descriptor. + * @retval NULL did not found interface descriptor or alternate setting */ +static void const* videod_set_vc_itf(videod_interface_t *self, unsigned altnum) { - tusb_desc_interface_t const *cur = (tusb_desc_interface_t const *)beg; - for (; cur; cur = videod_next_interface_desc(cur, end)) { - if (cur->bInterfaceNumber == itfnum) - return cur; + void const *beg = self->beg; + void const *end = self->end; + /* The head descriptor is a video control interface descriptor. */ + unsigned itfnum = ((tusb_desc_interface_t const *)beg)->bInterfaceNumber; + void const *cur = videod_find_desc_itf(beg, end, itfnum, altnum); + TU_VERIFY(cur < end, NULL); + + tusb_desc_vc_itf_t const *vc = (tusb_desc_vc_itf_t const *)cur; + /* Support for up to 2 streaming interfaces only. */ + TU_VERIFY(vc->ctl.bInCollection < 3, NULL); + + /* Close the previous notification endpoint if it is opened */ + if (self->ep_notif) { + usbd_edpt_close(rhport, self->ep_notif); + self->ep_notif = 0; + } + /* Advance to the next descriptor after the class-specific VC interface header descriptor. */ + cur += vc->std.bLength + vc->ctl.bLength; + /* Update to point the end of the video control interface descriptor. */ + end = cur + vc->ctl.wTotalLength; + /* Open the notification endpoint if it exist. */ + if (vc->std.bNumEndpoints) { + /* Support for 1 endpoint only. */ + TU_VERIFY(1 == vc->std.bNumEndpoints, NULL); + /* Find the notification endpoint descriptor. */ + cur = videod_find_desc(cur, end, TUSB_DESC_ENDPOINT); + TU_VERIFY(cur < end, NULL); + tusb_desc_endpoint_t const *notif = (tusb_desc_endpoint_t const *)cur; + /* Open the notification endpoint */ + TU_ASSERT(usbd_edpt_open(rhport, notif), NULL); + self->ep_notif = notif->bEndpointAddress; + } + self->vc = vc; + return end; +} + +/** Set the specified alternate setting to own video control interface. + * + * @param[in,out] self The context. + * @param[in] itfnum The target interface number. + * @param[in] altnum The target alternate setting number. + * + * @return The next descriptor after the video control interface descriptor. + * @retval NULL did not found interface descriptor or alternate setting */ +static void const* videod_set_vs_itf(videod_interface_t *self, unsigned itfnum, unsigned altnum) +{ + unsigned i; + tusb_desc_vc_itf_t const *vc = self->vc; + void const *end = self->end; + /* Set the end of the video control interface descriptor. */ + void const *cur = (void const*)vc + vc->std.bLength + vc->ctl.bLength + vc->ctl.wTotalLength; + + /* Check itfnum is valid */ + unsigned bInCollection = self->vc->ctl.bInCollection; + for (i = 0; (i < bInCollection) && (vc->ctl.baInterfaceNr[i] != itfnum); ++i) ; + TU_VERIFY(i < bInCollection, NULL); + + cur = videod_find_desc_itf(cur, end, itfnum, altnum); + TU_VERIFY(cur < end, NULL); + tusb_desc_vs_itf_t const *vs = (tusb_desc_vs_itf_t const*)cur; + /* Advance to the next descriptor after the class-specific VS interface header descriptor. */ + cur += vs->std.bLength + vs->stm.bLength; + /* Update to point the end of the video control interface descriptor. */ + end = cur + vs->stm.wTotalLength; + + switch (vs->stm.bDescriptorSubType) { + default: return end; + case VIDEO_CS_VS_INTERFACE_INPUT_HEADER: + /* Support for up to 2 endpoint only. */ + TU_VERIFY(vc->std.bNumEndpoints < 3, NULL); + if (self->ep_sti) { + usbd_edpt_close(rhport, self->ep_sti); + self->ep_sti = 0; + } + if (self->ep_in) { + usbd_edpt_close(rhport, self->ep_in); + self->ep_in = 0; + } + if (i = 0; i < vs->std.bNumEndpoints; ++i) { + cur = videod_find_desc(cur, end, TUSB_DESC_ENDPOINT); + TU_VERIFY(cur < end, NULL); + tusb_desc_endpoint_t const *ep = (tusb_desc_endpoint_t const *)cur; + if (vs->stm.bEndpointAddress == ep->bEndpointAddress) { + /* video input endpoint */ + TU_ASSERT(!self->ep_in, NULL); + TU_ASSERT(usbd_edpt_open(rhport, ep), NULL); + self->ep_in = ep->bEndpointAddress; + } else { + /* still image input endpoint */ + TU_ASSERT(!self->ep_sti, NULL); + TU_ASSERT(usbd_edpt_open(rhport, ep), NULL); + self->ep_sti = ep->bEndpointAddress; + } + cur += tu_desc_len(cur); + } + break; + case VIDEO_CS_VS_INTERFACE_OUTPUT_HEADER: + /* Support for up to 1 endpoint only. */ + TU_VERIFY(vc->std.bNumEndpoints < 2, NULL); + if (self->ep_out) { + usbd_edpt_close(rhport, self->ep_out); + self->ep_out = 0; + } + if (vs->std.bNumEndpoints) { + cur = videod_find_desc(cur, end, TUSB_DESC_ENDPOINT); + TU_VERIFY(cur < end, NULL); + tusb_desc_endpoint_t const *ep = (tusb_desc_endpoint_t const *)cur; + if (vs->stm.bEndpointAddress == ep->bEndpointAddress) { + /* video output endpoint */ + TU_ASSERT(usbd_edpt_open(rhport, ep), NULL); + self->ep_out = ep->bEndpointAddress; + } + } + break; + } + for (i = 0; i < sizeof(self->vs)/sizeof(self->vs[0]); ++i) { + if (!self->vs[i] || self->vs[i].stm.bInterfaceNumber == vs->stm.bInterfaceNumber) { + self->vs[i] = vs; + return end; + } } return NULL; } +static bool videod_get_itf(uint8_t rhport, videod_interface_t *self, tusb_control_request_t const * request) +{ + unsigned altnum = tu_u16_low(p_request->wValue); + unsigned itfnum = tu_u16_low(p_request->wLength); + + tusb_desc_vc_itf_t const *vc = self->vc; + if (vc->std.bInterfaceNumber == itfnum) { + tud_control_xfer(rhport, request, &vc->std.bAlternateSettings, sizeof(vc->std.bAlternateSettings)); + return true; + } + for (unsigned i = 0; i < vc->ctl.bInCollection; ++i) { + tusb_desc_vs_itf_t const *vs = self->vs[i]; + if (!vs || vs->std.bInterfaceNumber == itfnum) { + continue; + } + tud_control_xfer(rhport, request, &vs->std.bAlternateSettings, sizeof(vs->std.bAlternateSettings)); + return true; + } + return false; +} + +static bool videod_set_itf(uint8_t rhport, videod_interface_t *self, tusb_control_request_t const * request) +{ + (void)rhport; + unsigned altnum = tu_u16_low(p_request->wValue); + unsigned itfnum = tu_u16_low(p_request->wLength); + + tusb_desc_vc_itf_t const *vc = self->vc; + if (vc->std.bInterfaceNumber == itfnum) { + if (videod_set_vc_itf(self, altnum)) + return true; + return false; + } + for (unsigned i = 0; i < vc->ctl.bInCollection; ++i) { + tusb_desc_vs_itf_t const *vs = self->vs[i]; + if (!vs || vs->std.bInterfaceNumber == itfnum) { + continue; + } + if (videod_set_vs_itf(self, itfnum, altnum)) + return true; + return false; + } + return false; +} + static void _prep_out_transaction (cdcd_interface_t* p_cdc) { uint8_t const rhport = TUD_OPT_RHPORT; @@ -165,85 +429,43 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin VIDEO_INT_PROTOCOL_CODE_15 == itf_desc->bFunctionProtool, 0); /* Find available interface */ - videod_interface_t *p_video = NULL; - for (unsigned video_id = 0; video_id < CFG_TUD_VIDEO; ++video_id) { - if (!_videod_itf[video_id].itf_in && !_videod_itf[video_id].itf_out) { - p_video = &_videod_itf[video_id]; + videod_interface_t *self = NULL; + for (unsigned i = 0; i < CFG_TUD_VIDEO; ++i) { + if (!_videod_itf[i].vc) { + self = &_videod_itf[i]; break; } } - TU_ASSERT(p_video, 0); + TU_ASSERT(self, 0); + void const *end = (void const*)itf_desc + max_len; + self->beg = itf_desc; + self->end = end; /*------------- Video Control Interface -------------*/ - TU_VERIFY(itf_desc->bNumEndpoints < 2, 0); /* support only 1 notification endpoint */ - unsigned itf_ctl = itf_desc->bInterfaceNumber; - unsigned drv_len = sizeof(*itf_desc); - tusb_desc_endpoint_t const * desc_ep = NULL; - - uint8_t const *p_desc = tu_desc_next(itf_desc); - tusb_desc_video_control_interface_t const *ctl = (tusb_desc_video_control_interface_t const*)p_desc; - TU_VERIFY(TUSB_DESC_CS_INTERFACE == ctl->bDescriptorType && - VIDEO_CS_VC_INTERFACE_HEADER == ctl->bDescriptorSubType, 0); - - if (itf_desc->bNumEndpoints) { /* has a notification endpoint */ - p_desc = tu_desc_next(ctl); - /* skip to the notification endpoint descriptor */ - while (TUSB_DESC_ENDPOINT != tu_desc_type(p_desc) && drv_len <= max_len ) { - p_desc = tu_desc_next(p_desc); - } - desc_ep = (tusb_desc_endpoint_t const *)p_desc; + void const* cur = videod_set_vc_itf(self, 0); + TU_VERIFY(cur, 0); + unsigned bInCollection = self->vc->ctl.bInCollection; + /*------------- Video Stream Interface -------------*/ + unsigned itfnum = 0; + for (unsigned i = 0; i < bInCollection; ++i) { + itfnum = vc->ctl.baInterfaceNr[i]; + cur = videod_set_vs_itf(self, itfnum, 0); + TU_VERIFY(cur, 0); } - drv_len += tu_desc_len(ctl) + ctl->wTotalLength; - p_desc = tu_desc_next(ctl) + ctl->wTotalLength; - TU_VERIFY(drv_len <= max_len, 0); - /*------------- Video Stream Interface -------------*/ - uint8_t itf_in = 0, itf_out = 0; - tusb_desc_video_streaming_interface_input_t const *stm_in = NULL; - tusb_desc_video_streaming_interface_output_t const *stm_out = NULL; - - for (unsigned itf_stm = 0; itf_stm < ctl->bInCollection; ++itf_stm) { - itf_desc = (tusb_desc_interface_t const *)p_desc; - TU_VERIFY(TUSB_DESC_INTERFACE == itf_desc->bDescriptorType && - 0 == itf_desc->bInterfaceNumber && - TUSB_CLASS_VIDEO == itf_desc->bInterfaceClass && - VIDEO_SUBCLASS_STREAMING == itf_desc->bInterfaceSubClass && - VIDEO_INT_PROTOCOL_CODE_15 == itf_desc->bFunctionProtool && - 0 == itf_desc->bNumEndpoints, 0); - drv_len += sizeof(*itf_desc); - p_desc = tu_desc_next(itf_desc); - TU_VERIFY(TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc)); - tusb_desc_video_streaming_interface_t const *stm = (tusb_desc_video_streaming_interface_t const *)p_desc; - TU_VERIFY(TUSB_DESC_CS_INTERFACE == stm->bDescriptorType); - switch (stm->bDescriptorSubType) { - default: return 0; - case VIDEO_CS_VS_INTERFACE_INPUT_HEADER: - TU_VERIFY(0 == itf_in, 0); - itf_in = itf_desc->bInterfaceNumber; - stm_in = (tusb_desc_video_streaming_interface_input_t const*)stm; - break; - case VIDEO_CS_VS_INTERFACE_OUTPUT_HEADER: - TU_VERIFY(0 == itf_out, 0); - itf_out = itf_desc->bInterfaceNumber; - stm_out = (tusb_desc_video_streaming_interface_output_t const*)stm; + /* Skip alternate setting interfaces */ + while (cur < end && TUSB_DESC_INTERFACE == tu_desc_type(cur)) { + tusb_desc_vs_itf_t const *vs = (tusb_desc_vs_itf_t const *)cur; + if (itfnum != vs->std.bInterfaceNumber || + TUSB_DESC_CS_INTERFACE != vs->stm.bDescriptorType || + (VIDEO_CS_VS_INTERFACE_INPUT_HEADER != vs->stm.bDescriptorSubType && + VIDEO_CS_VS_INTERFACE_OUTPUT_HEADER!= vs->stm.bDescriptorSubType)) { break; } - drv_len += tu_desc_len(stm) + stm->wTotalLength; - p_desc = tu_desc_next(stm) + ctl->wTotalLength; + cur += itf->std.bLength + itf->stm.bLength + itf->stm.wTotalLength; } - if (desc_ep) { - /* open the notification endpoint */ - TU_ASSERT( usbd_edpt_open(rhport, desc_ep), 0); - p_video->ep_notif = desc_ep->bEndpointAddress; - } - p_video->itf_ctl = itf_ctl; - p_video->itf_in = itf_in; - p_video->itf_out = itf_out; - p_video->ctl = ctl; - p_video->stm_in = stm_in; - p_video->stm_out = stm_out; - - return drv_len; + self->end = cur; + return end - cur; } // Invoked when a control transfer occurred on an interface of this class @@ -251,43 +473,37 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin // return false to stall control endpoint (e.g unsupported request) bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request) { + if (p_request->bmRequestType_bit.recipient != TUSB_REQ_RCPT_INTERFACE) { + return false; + } + unsigned itfnum = tu_u16_low(p_request->wIndex); + /* Identify which interface to use */ + videod_interface_t *self = NULL; + for (unsigned i = 0; i < CFG_TUD_VIDEO; ++i) { + if (_videod_itf[i].vc->bInterfaceNumber == itfnum) { + self = &_videod_itf[i]; + break; + } + } + if (!self) return false; + /* Standard request */ if (p_request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD) { - tusb_desc_interface_t const *itf; - unsigned itf; + if (stage != CONTROL_STAGE_SETUP) return true; switch (p_request->bRequest) { case TUSB_REQ_GET_INTERFACE: - itf = tu_u16_low(p_request->wIndex); - return audiod_get_interface(rhport, p_request); + return videod_get_itf(rhport, self, request); case TUSB_REQ_SET_INTERFACE: - itf = videod_find_interface_desc(void const *beg, void const *end, unsigned itfnum) - itf = tu_u16_low(p_request->wIndex); - - return audiod_set_interface(rhport, p_request); - /* Unknown/Unsupported request */ - default: TU_BREAKPOINT(); return false; + return videod_set_itf(rhport, self, request); + default: /* Unknown/Unsupported request */ + TU_BREAKPOINT(); + return false; } } - uint8_t itf = 0; - videod_interface_t* p_video = _videod_itf; - - // Identify which interface to use - for ( ; ; itf++, p_video++) { - if (itf >= TU_ARRAY_SIZE(_videod_itf)) return false; - if ( p_video->itf_num == request->wIndex ) break; - } - - if (stage == CONTROL_STAGE_SETUP) { - TU_VERIFY((TUSB_DIR_IN_MASK & request->bmRequestType) == - (TUSB_DIR_IN_MASK & request->bRequest)); - } - - - unsigned cs = TU_U16_HIGH(request->wValue); - + unsigned cs = TU_U16_HIGH(request->wValue); + unsigned uid = TU_U16_HIGH(request->wIndex); - unsigned req = request->bRequest; switch (request->bRequest) { case VIDEO_REQUEST_GET_INFO: TU_VERIFY(1 == request->wLength); @@ -295,16 +511,16 @@ bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_ break; case VIDEO_REQUEST_SET_CUR: if (stage == CONTROL_STAGE_SETUP) { - TU_LOG2(" Set Current Setting Attribute\r\n"); - tud_control_xfer(rhport, request, &p_video->line_coding, sizeof(cdc_line_coding_t)); + TU_LOG2(" Set Current Setting Attribute\r\n"); + tud_control_xfer(rhport, request, &p_video->line_coding, sizeof(cdc_line_coding_t)); } else if ( stage == CONTROL_STAGE_ACK) { if ( tud_cdc_line_coding_cb ) tud_cdc_line_coding_cb(itf, &p_video->line_coding); } break; case VIDEO_REQUEST_GET_CUR: if (stage == CONTROL_STAGE_SETUP) { - TU_LOG2(" Set Current Setting Attribute\r\n"); - tud_control_xfer(rhport, request, &p_video->line_coding, sizeof(cdc_line_coding_t)); + TU_LOG2(" Set Current Setting Attribute\r\n"); + tud_control_xfer(rhport, request, &p_video->line_coding, sizeof(cdc_line_coding_t)); } else if ( stage == CONTROL_STAGE_ACK) { if ( tud_cdc_line_coding_cb ) tud_cdc_line_coding_cb(itf, &p_video->line_coding); } diff --git a/src/class/video/video_device.h b/src/class/video/video_device.h index b077a9a76..e0ff21694 100644 --- a/src/class/video/video_device.h +++ b/src/class/video/video_device.h @@ -28,12 +28,21 @@ #ifndef TUSB_VIDEO_DEVICE_H_ #define TUSB_VIDEO_DEVICE_H_ -#include "video_device.h" - #ifdef __cplusplus extern "C" { #endif +//--------------------------------------------------------------------+ +// Application Callback API (weak is optional) +//--------------------------------------------------------------------+ + +// Invoked when GET_INFO request received +TU_ATTR_WEAK bool tud_video_get_info_cb(uint8_t rhport, tusb_control_request_t const *request, uint8_t const *itf_desc); +// Invoked when GET_INFO request received +TU_ATTR_WEAK bool tud_video_set_cur_cb(uint8_t rhport, tusb_control_request_t const *request); +// Invoked when GET_CUR request received +TU_ATTR_WEAK bool tud_video_get_info_cb(uint8_t rhport, tusb_control_request_t const *request); + //--------------------------------------------------------------------+ // INTERNAL USBD-CLASS DRIVER API //--------------------------------------------------------------------+ -- cgit v1.3.1 From 033d6b28fff1644411ef430a968ca7f0d9aa3b05 Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Sun, 25 Jul 2021 14:01:35 +0900 Subject: moved ISO attributes from audio to common --- examples/rules.mk | 1 + src/class/audio/audio.h | 12 - src/class/video/video.h | 85 +++++- src/class/video/video_device.c | 634 +++++++++++++++++++++++++++++------------ src/class/video/video_device.h | 7 +- src/common/tusb_types.h | 12 + 6 files changed, 535 insertions(+), 216 deletions(-) diff --git a/examples/rules.mk b/examples/rules.mk index 861973284..6f2d5a0ee 100644 --- a/examples/rules.mk +++ b/examples/rules.mk @@ -35,6 +35,7 @@ SRC_C += \ src/class/msc/msc_device.c \ src/class/net/net_device.c \ src/class/usbtmc/usbtmc_device.c \ + src/class/video/video_device.c \ src/class/vendor/vendor_device.c # TinyUSB stack include diff --git a/src/class/audio/audio.h b/src/class/audio/audio.h index f99061eae..6f9c1a6b5 100644 --- a/src/class/audio/audio.h +++ b/src/class/audio/audio.h @@ -494,18 +494,6 @@ typedef enum /// All remaining definitions are taken from the descriptor descriptions in the UAC2 main specification -/// Isochronous End Point Attributes -typedef enum -{ - TUSB_ISO_EP_ATT_NO_SYNC = 0x00, - TUSB_ISO_EP_ATT_ASYNCHRONOUS = 0x04, - TUSB_ISO_EP_ATT_ADAPTIVE = 0x08, - TUSB_ISO_EP_ATT_SYNCHRONOUS = 0x0C, - TUSB_ISO_EP_ATT_DATA = 0x00, ///< Data End Point - TUSB_ISO_EP_ATT_EXPLICIT_FB = 0x10, ///< Feedback End Point - TUSB_ISO_EP_ATT_IMPLICIT_FB = 0x20, ///< Data endpoint that also serves as an implicit feedback -} tusb_iso_ep_attribute_t; - /// Audio Class-Control Values UAC2 typedef enum { diff --git a/src/class/video/video.h b/src/class/video/video.h index f994c7fed..081860c83 100644 --- a/src/class/video/video.h +++ b/src/class/video/video.h @@ -29,6 +29,20 @@ #include "common/tusb_common.h" +/* 4.2.1.2 */ +typedef enum { + VIDEO_NO_ERROR = 0, /* The request succeeded. */ + VIDEO_NOT_READY, + VIDEO_WRONG_STATE, + VIDEO_POWER, + VIDEO_OUT_OF_RANGE, + VIDEO_INVALID_UNIT, + VIDEO_INVALID_CONTROL, + VIDEO_INVALID_REQUEST, + VIDEO_INVALID_VALUE_WITHIN_RANGE, + VIDEO_UNKNOWN = 0xFF, +} video_error_code_t; + /* A.2 */ typedef enum { VIDEO_SUBCLASS_UNDEFINED = 0x00, @@ -103,14 +117,29 @@ typedef enum VIDEO_REQUEST_GET_DEF_ALL = 0x97 } video_control_request_t; -/* A.9 */ +/* A.9.1 */ typedef enum { - VIDEO_CTL_SEL_UNDEF = 0x00, - VIDEO_CTL_SEL_VIDEO_POWER_MODE_CONTROL, - VIDEO_CTL_SEL_REQUEST_ERROR_CODE_CONTROL, + VIDEO_VC_CTL_UNDEF = 0x00, + VIDEO_VC_CTL_VIDEO_POWER_MODE, + VIDEO_VC_CTL_REQUEST_ERROR_CODE, } video_interface_control_selector_t; +/* A.9.8 */ +typedef enum +{ + VIDEO_VS_CTL_UNDEF = 0x00, + VIDEO_VS_CTL_PROBE, + VIDEO_VS_CTL_COMMIT, + VIDEO_VS_CTL_STILL_PROBE, + VIDEO_VS_CTL_STILL_COMMIT, + VIDEO_VS_CTL_STILL_IMAGE_TRIGGER, + VIDEO_VS_CTL_STREAM_ERROR_CODE, + VIDEO_VS_CTL_GENERATE_KEY_FRAME, + VIDEO_VS_CTL_UPDATE_FRAME_SEGMENT, + VIDEO_VS_CTL_SYNCH_DELAY_CONTROL, +} video_interface_streaming_selector_t; + /* B. Terminal Types */ typedef enum { @@ -193,8 +222,37 @@ typedef struct TU_ATTR_PACKED { uint8_t bControlSize; uint8_t bmaControls[]; } output; + }; } tusb_desc_cs_video_stm_itf_hdr_t; +//--------------------------------------------------------------------+ +// Requests +//--------------------------------------------------------------------+ +typedef struct TU_ATTR_PACKED { + uint16_t bmHint; + uint8_t bFormatIndex; + uint8_t bFrameIndex; + uint32_t dwFrameInterval; + uint16_t wKeyFrameRate; + uint16_t wPFrameRate; + uint16_t wCompQuality; + uint16_t wCompWindowSize; + uint16_t wDelay; + uint32_t dwMaxVideoFrameSize; + uint32_t dwMaxPayloadTransferSize; + uint32_t dwClockFrequency; + uint8_t bmFramingInfo; + uint8_t bPreferedVersion; + uint8_t bMinVersion; + uint8_t bMaxVersion; + uint8_t bUsage; + uint8_t bBitDepthLum; + uint8_t bmSettings; + uint8_t bMaxNumberOfRefFramesPlus1; + uint16_t bmRateControlModes; + uint64_t bmLayoutPerStream; +} video_probe_and_commit_t; + #define TUD_VIDEO_DESC_IAD_LEN 8 #define TUD_VIDEO_DESC_STD_VC_LEN 9 #define TUD_VIDEO_DESC_CS_VC_LEN 12 @@ -225,18 +283,18 @@ typedef struct TU_ATTR_PACKED { /* 3.7.2 */ #define TUD_VIDEO_DESC_CS_VC(_bcdUVC, _totallen, _clkfreq, _coll, ...) \ TUD_VIDEO_DESC_CS_VC_LEN + _coll, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VC_INTERFACE_HEADER, \ - U16_TO_U8S_LE(_bcdUVC), U16_TO_U8S_LE(_totallen + TUD_VIDEO_DESC_CS_AC_LEN), \ + U16_TO_U8S_LE(_bcdUVC), U16_TO_U8S_LE(_totallen + TUD_VIDEO_DESC_CS_VC_LEN), \ U32_TO_U8S_LE(_clkfreq), _coll, __VA_ARGS__ /* 3.7.2.1 */ #define TUD_VIDEO_DESC_INPUT_TERM(_tid, _tt, _at, _stridx) \ TUD_VIDEO_DESC_INPUT_TERM_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VC_INTERFACE_INPUT_TERMINAL, \ - _tid, U16_TO_U8S_LE(_tt), _at, _ti + _tid, U16_TO_U8S_LE(_tt), _at, _stridx /* 3.7.2.2 */ #define TUD_VIDEO_DESC_OUTPUT_TERM(_tid, _tt, _at, _srcid, _stridx) \ TUD_VIDEO_DESC_INPUT_TERM_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VC_INTERFACE_OUTPUT_TERMINAL, \ - _tid, U16_TO_U8S_LE(_tt), _at, _ti + _tid, U16_TO_U8S_LE(_tt), _at, _stridx /* 3.9.1 */ #define TUD_VIDEO_DESC_STD_VS(_itfnum, _alt, _epn, _stridx) \ @@ -258,14 +316,15 @@ typedef struct TU_ATTR_PACKED { _epn, _inf, _termlnk, _trgusg, _ctlsz, __VA_ARGS__ /* Uncompressed 3.1.1 */ +#define TUD_VIDEO_GUID(_g0,_g1,_g2,_g3,_g4,_g5,_g6,_g7,_g8,_g9,_g10,_g11,_g12,_g13,_g14,_g15) _g0,_g1,_g2,_g3,_g4,_g5,_g6,_g7,_g8,_g9,_g10,_g11,_g12,_g13,_g14,_g15 #define TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR(_fmtidx, _numfrmdesc, \ - _g0,_g1,_g2,_g3,_g4,_g5,_g6,_g7,_g8,_g9,_g10,_g11,_g12,_g13,_g14,_g15, \ - _bitsperpix, _frmidx, _asrx, _asry, _interlace, _cp) \ + _guid, _bitsperpix, _frmidx, _asrx, _asry, _interlace, _cp) \ TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_INTERFACE_FORMAT_UNCOMPRESSED, \ - _fmtidx, _numfrmdesc,\ - _g0,_g1,_g2,_g3,_g4,_g5,_g6,_g7,_g8,_g9,_g10,_g11,_g12,_g13,_g14,_g15,\ + _fmtidx, _numfrmdesc, TUD_VIDEO_GUID(_guid), \ _bitsperpix, _frmidx, _asrx, _asry, _interlace, _cp +// _g0,_g1,_g2,_g3,_g4,_g5,_g6,_g7,_g8,_g9,_g10,_g11,_g12,_g13,_g14,_g15, + /* Uncompressed 3.1.2 Table 3-3 */ #define TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT(_frmidx, _cap, _width, _height, _minbr, _maxbr, _maxfrmbufsz, _frminterval, _minfrminterval, _maxfrminterval, _frmintervalstep) \ TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_INTERFACE_FRAME_UNCOMPRESSED, \ @@ -281,12 +340,12 @@ typedef struct TU_ATTR_PACKED { U32_TO_U8S_LE(_maxfrmbufsz), U32_TO_U8S_LE(_frminterval), _numfrminterval, __VA_ARGS__ /* 3.10.1.1 */ -#define TUD_VIDEO_DESC_EP_ISO(_ep, _epsize, _ep_interval) +#define TUD_VIDEO_DESC_EP_ISO(_ep, _epsize, _ep_interval) \ 7, TUSB_DESC_ENDPOINT, _ep, TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS,\ U16_TO_U8S_LE(_epsize), _ep_interval /* 3.10.1.2 */ -#define TUD_VIDEO_DESC_EP_BULK(_ep, _epsize, _ep_interval) +#define TUD_VIDEO_DESC_EP_BULK(_ep, _epsize, _ep_interval) \ 7, TUSB_DESC_ENDPOINT, _ep, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), _ep_interval #endif diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index 637e7a127..ed703d79a 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -53,33 +53,32 @@ typedef struct { tusb_desc_cs_video_stm_itf_hdr_t stm; } tusb_desc_vs_itf_t; +typedef union { + tusb_desc_cs_video_ctl_itf_hdr_t ctl; + tusb_desc_cs_video_stm_itf_hdr_t stm; +} tusb_desc_video_itf_hdr_t; + typedef struct TU_ATTR_PACKED { uint8_t bLength; uint8_t bDescriptorType; uint8_t bDescriptorSubtype; - union { - uint8_t bId; - uint8_t bTerminalId; - uint8_t bUnitId; - }; + uint8_t bEntityId; } tusb_desc_cs_video_entity_itf_t; typedef struct { - void const *beg; - void const *end; - tusb_desc_vc_itf_t const *vc; /* current video control interface */ - tusb_desc_vs_itf_t const *vs[2]; /* current video streaming interfaces */ - uint8_t ep_notif; /* notification */ - uint8_t ep_in; /* video IN */ - uint8_t ep_sti; /* still image IN */ - uint8_t ep_out; /* video OUT */ + void const *beg; /* The head of the first video control interface descriptor */ + uint16_t len; /* Byte length of the descriptors */ + uint16_t ofs[3]; /* offsets for video control/streaming interface. 0:control 1:streaming 2:streaming */ + uint8_t power_mode; + uint8_t error_code; /*------------- From this point, data is not cleared by bus reset -------------*/ // Endpoint Transfer buffer - CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUD_CDC_EP_BUFSIZE]; - CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUD_CDC_EP_BUFSIZE]; + // CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUD_CDC_EP_BUFSIZE]; + // CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUD_CDC_EP_BUFSIZE]; + uint8_t ctl_buf; } videod_interface_t; @@ -90,6 +89,26 @@ typedef struct //--------------------------------------------------------------------+ CFG_TUSB_MEM_SECTION static videod_interface_t _videod_itf[CFG_TUD_VIDEO]; +static uint8_t const _cap_get = 0x1u; /* support for GET */ +static uint8_t const _cap_get_set = 0x3u; /* support for GET and SET */ + +static tusb_desc_vc_itf_t const* _get_desc_vc(videod_interface_t const *self) +{ + return (tusb_desc_vc_itf_t const *)(self->beg + self->ofs[0]); +} + +static uint16_t* _get_desc_ofs(videod_interface_t *self, unsigned itfnum) +{ + void const *beg = self->beg; + uint16_t *ofs = self->ofs; + for (unsigned i = 1; i < sizeof(self->ofs)/sizeof(self->ofs[0]); ++i) { + if (!ofs[i]) continue; + tusb_desc_interface_t const* itf = (tusb_desc_interface_t const*)(beg + ofs[i]); + if (itfnum == itf->bInterfaceNumber) return &ofs[i]; + } + return NULL; +} + /** Find the first descriptor with the specified descriptor type. * * @param[in] beg The head of descriptor byte array. @@ -98,51 +117,47 @@ CFG_TUSB_MEM_SECTION static videod_interface_t _videod_itf[CFG_TUD_VIDEO]; * * @return The pointer for interface descriptor. * @retval end did not found interface descriptor */ -static void const* videod_find_desc(void const *beg, void const *end, uint8_t target) +static void const* _find_desc(void const *beg, void const *end, uint8_t target) { - for (void const *cur = beg; cur < end; cur = tu_desc_next(cur)) { - if (target != tu_desc_type(cur)) - return (uint8_t const*)cur; + void const *cur = beg; + while ((cur < end) && (target != tu_desc_type(cur))) { + cur = tu_desc_next(cur); } - return end; + return cur; } -/** Find the first interface descriptor with the specified interface number and alternate setting number. +/** Return the next interface descriptor except alternate ones. * * @param[in] beg The head of descriptor byte array. * @param[in] end The tail of descriptor byte array. - * @param[in] itfnum The target interface number. - * @param[in] altnum The target alternate setting number. * * @return The pointer for interface descriptor. * @retval end did not found interface descriptor */ -static void const* videod_find_desc_itf(void const *beg, void const *end, unsigned itfnum, unsigned altnum) +static void const* _next_desc_itf(void const *beg, void const *end) { - for (void const *cur = beg; cur < end; cur = videod_find_desc(cur, end, TUSB_DESC_INTERFACE)) { - tusb_desc_interface_t const *itf = (tusb_desc_interface_t const *)cur; - if (itf->bInterfaceNumber == itfnum && itf->bAlternateSettings == altnum) { - return itf; - } - cur = tu_desc_next(cur); + void const *cur = beg; + unsigned itfnum = ((tusb_desc_interface_t const*)cur)->bInterfaceNumber; + while ((cur < end) && + (itfnum == ((tusb_desc_interface_t const*)cur)->bInterfaceNumber)) { + cur = _find_desc(tu_desc_next(cur), end, TUSB_DESC_INTERFACE); } - return end; + return cur; } -/** Find the first input or output terminal descriptor with the specified terminal id. +/** Find the first interface descriptor with the specified interface number and alternate setting number. * * @param[in] beg The head of descriptor byte array. * @param[in] end The tail of descriptor byte array. - * @param[in] termid The target terminal id. + * @param[in] itfnum The target interface number. + * @param[in] altnum The target alternate setting number. * * @return The pointer for interface descriptor. * @retval end did not found interface descriptor */ -static void const* videod_find_desc_term(void const *beg, void const *end, unsigned termid) +static void const* _find_desc_itf(void const *beg, void const *end, unsigned itfnum, unsigned altnum) { - for (void const *cur = beg; cur < end; cur = videod_find_desc(cur, end, TUSB_DESC_CS_INTERFACE)) { - tusb_desc_cs_video_entity_itf_t const *itf = (tusb_desc_cs_video_entity_itf_t const *)cur; - if ((VIDEO_CS_VC_INTERFACE_INPUT_TERMINAL == itf->bDescriptorSubtype || - VIDEO_CS_VC_INTERFACE_OUTPUT_TERMINAL == itf->bDescriptorSubtype) && - itf->bTerminalId == termid) { + for (void const *cur = beg; cur < end; cur = _find_desc(cur, end, TUSB_DESC_INTERFACE)) { + tusb_desc_interface_t const *itf = (tusb_desc_interface_t const *)cur; + if (itf->bInterfaceNumber == itfnum && itf->bAlternateSetting == altnum) { return itf; } cur = tu_desc_next(cur); @@ -150,21 +165,22 @@ static void const* videod_find_desc_term(void const *beg, void const *end, unsig return end; } -/** Find the first selector/processing/extension/encoding unit descriptor with the specified unit id. +/** Find the first entity descriptor with the specified entity ID in the video control interface descriptor. * - * @param[in] beg The head of descriptor byte array. - * @param[in] end The tail of descriptor byte array. - * @param[in] unitid The target unit id. + * @param[in] vc The video control interface descriptor. + * @param[in] entityid The target entity id. * * @return The pointer for interface descriptor. * @retval end did not found interface descriptor */ -static void const* videod_find_desc_unit(void const *beg, void const *end, unsigned unitid) +static void const* _find_desc_entity(tusb_desc_vc_itf_t const *vc, unsigned entityid) { - for (void const *cur = beg; cur < end; cur = videod_find_desc(cur, end, TUSB_DESC_CS_INTERFACE)) { + void const *beg = (void const*)vc; + void const *end = beg + vc->std.bLength + vc->ctl.bLength + vc->ctl.wTotalLength; + for (void const *cur = beg; cur < end; cur = _find_desc(cur, end, TUSB_DESC_CS_INTERFACE)) { tusb_desc_cs_video_entity_itf_t const *itf = (tusb_desc_cs_video_entity_itf_t const *)cur; - if (VIDEO_CS_VC_INTERFACE_SELECTOR_UNIT <= itf->bDescriptorSubtype && - itf->bDescriptorSubtype <= VIDEO_CS_VC_INTERFACE_ENCODING_UNIT && - itf->bUnitId == unitid) { + if ((VIDEO_CS_VC_INTERFACE_INPUT_TERMINAL == itf->bDescriptorSubtype || + VIDEO_CS_VC_INTERFACE_OUTPUT_TERMINAL == itf->bDescriptorSubtype) && + itf->bEntityId == entityid) { return itf; } cur = tu_desc_next(cur); @@ -172,25 +188,72 @@ static void const* videod_find_desc_unit(void const *beg, void const *end, unsig return end; } +static bool _close_vc_itf(uint8_t rhport, videod_interface_t *self) +{ + tusb_desc_vc_itf_t const *vc = _get_desc_vc(self); + /* The next descriptor after the class-specific VC interface header descriptor. */ + void const *cur = (void const*)vc + vc->std.bLength + vc->ctl.bLength; + /* The end of the video control interface descriptor. */ + void const *end = cur + vc->ctl.wTotalLength; + if (vc->std.bNumEndpoints) { + /* Find the notification endpoint descriptor. */ + cur = _find_desc(cur, end, TUSB_DESC_ENDPOINT); + TU_ASSERT(cur < end); + tusb_desc_endpoint_t const *notif = (tusb_desc_endpoint_t const *)cur; + usbd_edpt_close(rhport, notif->bEndpointAddress); + } + self->ofs[0] = 0; + return true; +} + +static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, unsigned altnum) +{ + void const *beg = self->beg; + void const *end = beg + self->len; + /* The first descriptor is a video control interface descriptor. */ + unsigned itfnum = ((tusb_desc_interface_t const *)beg)->bInterfaceNumber; + void const *cur = _find_desc_itf(beg, end, itfnum, altnum); + TU_VERIFY(cur < end); + + tusb_desc_vc_itf_t const *vc = (tusb_desc_vc_itf_t const *)cur; + /* Support for up to 2 streaming interfaces only. */ + TU_ASSERT(vc->ctl.bInCollection < 3); + + /* Advance to the next descriptor after the class-specific VC interface header descriptor. */ + cur += vc->std.bLength + vc->ctl.bLength; + /* Update to point the end of the video control interface descriptor. */ + end = cur + vc->ctl.wTotalLength; + /* Open the notification endpoint if it exist. */ + if (vc->std.bNumEndpoints) { + /* Support for 1 endpoint only. */ + TU_VERIFY(1 == vc->std.bNumEndpoints); + /* Find the notification endpoint descriptor. */ + cur = _find_desc(cur, end, TUSB_DESC_ENDPOINT); + TU_VERIFY(cur < end); + tusb_desc_endpoint_t const *notif = (tusb_desc_endpoint_t const *)cur; + /* Open the notification endpoint */ + TU_ASSERT(usbd_edpt_open(rhport, notif)); + } + self->ofs[0] = (void const*)vc - beg; + return true; +} + /** Set the specified alternate setting to own video control interface. * * @param[in,out] self The context. - * @param[in] altnum The target alternate setting number. - * - * @return The next descriptor after the video control interface descriptor. - * @retval NULL did not found interface descriptor or alternate setting */ -static void const* videod_set_vc_itf(videod_interface_t *self, unsigned altnum) + * @param[in] altnum The target alternate setting number. */ +static bool _set_vc_itf(uint8_t rhport, videod_interface_t *self, unsigned altnum) { void const *beg = self->beg; - void const *end = self->end; + void const *end = beg + self->len; /* The head descriptor is a video control interface descriptor. */ unsigned itfnum = ((tusb_desc_interface_t const *)beg)->bInterfaceNumber; - void const *cur = videod_find_desc_itf(beg, end, itfnum, altnum); - TU_VERIFY(cur < end, NULL); + void const *cur = _find_desc_itf(beg, end, itfnum, altnum); + TU_VERIFY(cur < end); tusb_desc_vc_itf_t const *vc = (tusb_desc_vc_itf_t const *)cur; /* Support for up to 2 streaming interfaces only. */ - TU_VERIFY(vc->ctl.bInCollection < 3, NULL); + TU_VERIFY(vc->ctl.bInCollection < 3); /* Close the previous notification endpoint if it is opened */ if (self->ep_notif) { @@ -204,42 +267,104 @@ static void const* videod_set_vc_itf(videod_interface_t *self, unsigned altnum) /* Open the notification endpoint if it exist. */ if (vc->std.bNumEndpoints) { /* Support for 1 endpoint only. */ - TU_VERIFY(1 == vc->std.bNumEndpoints, NULL); + TU_VERIFY(1 == vc->std.bNumEndpoints); /* Find the notification endpoint descriptor. */ - cur = videod_find_desc(cur, end, TUSB_DESC_ENDPOINT); - TU_VERIFY(cur < end, NULL); + cur = _find_desc(cur, end, TUSB_DESC_ENDPOINT); + TU_VERIFY(cur < end); tusb_desc_endpoint_t const *notif = (tusb_desc_endpoint_t const *)cur; /* Open the notification endpoint */ - TU_ASSERT(usbd_edpt_open(rhport, notif), NULL); + TU_ASSERT(usbd_edpt_open(rhport, notif)); self->ep_notif = notif->bEndpointAddress; } - self->vc = vc; - return end; + self->ofs[0] = (void const*)vc - beg; + return true; +} + +/** Set the specified alternate setting to own video control interface. + * + * @param[in,out] self The context. + * @param[in] itfnum The target interface number. */ +static bool _close_vs_itf(uint8_t rhport, videod_interface_t *self, unsigned itfnum) +{ + uint16_t *ofs = _get_desc_ofs(self, itfnum); + if (!ofs) return true; + tusb_desc_vs_itf_t const *vs = (tusb_desc_vs_itf_t const*)(self->beg + *ofs); + /* The next of the video streaming interface header descriptor. */ + void const *cur = (void const*)vs + vs->std.bLength + vs->stm.bLength; + /* The end of the video streaming interface descriptor. */ + void const *end = cur + vs->stm.wTotalLength; + if (unsigned i = 0; i < vs->std.bNumEndpoints; ++i) { + cur = _find_desc(cur, end, TUSB_DESC_ENDPOINT); + TU_ASSERT(cur < end); + tusb_desc_endpoint_t const *ep = (tusb_desc_endpoint_t const *)cur; + usbd_edpt_close(rhport, ep->bEndpointAddress); + cur += tu_desc_len(cur); + } + *ofs = 0; + return true; } /** Set the specified alternate setting to own video control interface. * * @param[in,out] self The context. * @param[in] itfnum The target interface number. - * @param[in] altnum The target alternate setting number. + * @param[in] altnum The target alternate setting number. */ +static bool _open_vs_itf(uint8_t rhport, videod_interface_t *self, unsigned itfnum, unsigned altnum) +{ + uint16_t *ofs = NULL; + for (unsigned i = 1; i < sizeof(self->ofs)/sizeof(self->ofs[0]); ++i) { + if (!self->ofs[i]) { + ofs = &self->ofs[i]; + break; + } + } + if (!ofs) return false; + + tusb_desc_vc_itf_t const *vc = _get_desc_vc(self); + void const *end = self->beg + self->len; + /* Set the end of the video control interface descriptor. */ + void const *cur = (void const*)vc + vc->std.bLength + vc->ctl.bLength + vc->ctl.wTotalLength; + + cur = _find_desc_itf(cur, end, itfnum, altnum); + TU_VERIFY(cur < end); + tusb_desc_vs_itf_t const *vs = (tusb_desc_vs_itf_t const*)cur; + /* Support for up to 2 endpoint only. */ + TU_ASSERT(vs->std.bNumEndpoints < 3); + /* Advance to the next descriptor after the class-specific VS interface header descriptor. */ + cur += vs->std.bLength + vs->stm.bLength; + /* Update to point the end of the video control interface descriptor. */ + end = cur + vs->stm.wTotalLength; + for (unsigned i = 0; i < vs->std.bNumEndpoints; ++i) { + cur = _find_desc(cur, end, TUSB_DESC_ENDPOINT); + TU_VERIFY(cur < end); + tusb_desc_endpoint_t const *ep = (tusb_desc_endpoint_t const *)cur; + TU_ASSERT(usbd_edpt_open(rhport, ep)); + cur += tu_desc_len(cur); + } + *ofs = (void const*)vs - self->beg; + return true; +} + +/** Set the specified alternate setting to own video control interface. * - * @return The next descriptor after the video control interface descriptor. - * @retval NULL did not found interface descriptor or alternate setting */ -static void const* videod_set_vs_itf(videod_interface_t *self, unsigned itfnum, unsigned altnum) + * @param[in,out] self The context. + * @param[in] itfnum The target interface number. + * @param[in] altnum The target alternate setting number. */ +static bool _set_vs_itf(uint8_t rhport, videod_interface_t *self, unsigned itfnum, unsigned altnum) { unsigned i; - tusb_desc_vc_itf_t const *vc = self->vc; - void const *end = self->end; + tusb_desc_vc_itf_t const *vc = _get_desc_vc(self); + void const *end = self->beg + self->len; /* Set the end of the video control interface descriptor. */ void const *cur = (void const*)vc + vc->std.bLength + vc->ctl.bLength + vc->ctl.wTotalLength; /* Check itfnum is valid */ - unsigned bInCollection = self->vc->ctl.bInCollection; + unsigned bInCollection = vc->ctl.bInCollection; for (i = 0; (i < bInCollection) && (vc->ctl.baInterfaceNr[i] != itfnum); ++i) ; - TU_VERIFY(i < bInCollection, NULL); - - cur = videod_find_desc_itf(cur, end, itfnum, altnum); - TU_VERIFY(cur < end, NULL); + TU_VERIFY(i < bInCollection); + + cur = _find_desc_itf(cur, end, itfnum, altnum); + TU_VERIFY(cur < end); tusb_desc_vs_itf_t const *vs = (tusb_desc_vs_itf_t const*)cur; /* Advance to the next descriptor after the class-specific VS interface header descriptor. */ cur += vs->std.bLength + vs->stm.bLength; @@ -247,10 +372,10 @@ static void const* videod_set_vs_itf(videod_interface_t *self, unsigned itfnum, end = cur + vs->stm.wTotalLength; switch (vs->stm.bDescriptorSubType) { - default: return end; + default: return false; case VIDEO_CS_VS_INTERFACE_INPUT_HEADER: /* Support for up to 2 endpoint only. */ - TU_VERIFY(vc->std.bNumEndpoints < 3, NULL); + TU_VERIFY(vc->std.bNumEndpoints < 3); if (self->ep_sti) { usbd_edpt_close(rhport, self->ep_sti); self->ep_sti = 0; @@ -260,18 +385,18 @@ static void const* videod_set_vs_itf(videod_interface_t *self, unsigned itfnum, self->ep_in = 0; } if (i = 0; i < vs->std.bNumEndpoints; ++i) { - cur = videod_find_desc(cur, end, TUSB_DESC_ENDPOINT); - TU_VERIFY(cur < end, NULL); + cur = _find_desc(cur, end, TUSB_DESC_ENDPOINT); + TU_VERIFY(cur < end); tusb_desc_endpoint_t const *ep = (tusb_desc_endpoint_t const *)cur; if (vs->stm.bEndpointAddress == ep->bEndpointAddress) { /* video input endpoint */ - TU_ASSERT(!self->ep_in, NULL); - TU_ASSERT(usbd_edpt_open(rhport, ep), NULL); + TU_ASSERT(!self->ep_in); + TU_ASSERT(usbd_edpt_open(rhport, ep)); self->ep_in = ep->bEndpointAddress; } else { /* still image input endpoint */ - TU_ASSERT(!self->ep_sti, NULL); - TU_ASSERT(usbd_edpt_open(rhport, ep), NULL); + TU_ASSERT(!self->ep_sti); + TU_ASSERT(usbd_edpt_open(rhport, ep)); self->ep_sti = ep->bEndpointAddress; } cur += tu_desc_len(cur); @@ -279,78 +404,245 @@ static void const* videod_set_vs_itf(videod_interface_t *self, unsigned itfnum, break; case VIDEO_CS_VS_INTERFACE_OUTPUT_HEADER: /* Support for up to 1 endpoint only. */ - TU_VERIFY(vc->std.bNumEndpoints < 2, NULL); + TU_VERIFY(vc->std.bNumEndpoints < 2); if (self->ep_out) { usbd_edpt_close(rhport, self->ep_out); self->ep_out = 0; } if (vs->std.bNumEndpoints) { - cur = videod_find_desc(cur, end, TUSB_DESC_ENDPOINT); - TU_VERIFY(cur < end, NULL); + cur = _find_desc(cur, end, TUSB_DESC_ENDPOINT); + TU_VERIFY(cur < end); tusb_desc_endpoint_t const *ep = (tusb_desc_endpoint_t const *)cur; if (vs->stm.bEndpointAddress == ep->bEndpointAddress) { /* video output endpoint */ - TU_ASSERT(usbd_edpt_open(rhport, ep), NULL); + TU_ASSERT(usbd_edpt_open(rhport, ep)); self->ep_out = ep->bEndpointAddress; } } break; } + for (unsigned i = 1; i < sizeof(self->ofs)/sizeof(ofs[0]); ++i) { + if (!self->ofs[i]) { + return true; + } + tusb_desc_interface_t const* itf = (tusb_desc_interface_t const*)(beg + ofs[i]); + if (itfnum == itf->bInterfaceNumber) return itf; + } + return NULL; for (i = 0; i < sizeof(self->vs)/sizeof(self->vs[0]); ++i) { if (!self->vs[i] || self->vs[i].stm.bInterfaceNumber == vs->stm.bInterfaceNumber) { - self->vs[i] = vs; - return end; + self->ofs[i] = (void const*)vs - self->beg; + return true; } } - return NULL; + return false; } -static bool videod_get_itf(uint8_t rhport, videod_interface_t *self, tusb_control_request_t const * request) +static int handle_video_ctl_std_req_get_itf(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf) { - unsigned altnum = tu_u16_low(p_request->wValue); - unsigned itfnum = tu_u16_low(p_request->wLength); - - tusb_desc_vc_itf_t const *vc = self->vc; - if (vc->std.bInterfaceNumber == itfnum) { - tud_control_xfer(rhport, request, &vc->std.bAlternateSettings, sizeof(vc->std.bAlternateSettings)); - return true; - } - for (unsigned i = 0; i < vc->ctl.bInCollection; ++i) { - tusb_desc_vs_itf_t const *vs = self->vs[i]; - if (!vs || vs->std.bInterfaceNumber == itfnum) { - continue; + if (stage != CONTROL_STAGE_SETUP) + return VIDEO_NO_ERROR; + videod_interface_t *self = &_videod_itf[itf]; + TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN); + tusb_desc_interface_t const *p = _get_desc_cur_itf(self, itfnum); + if (!p) return VIDEO_UNKNOWN; + if (tud_control_xfer(rhport, request, &p->bAlternateSettings, sizeof(p->bAlternateSettings))) + return VIDEO_NO_ERROR; + return VIDEO_UNKNOWN; +} + +/** Handle a standard request to the video control interface. */ +static int handle_video_ctl_std_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf) +{ + switch (p_request->bRequest) { + case TUSB_REQ_GET_INTERFACE: + handle_video_ctl_std_req_get_itf(rhport, stage, request, itf); + case TUSB_REQ_SET_INTERFACE: + if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; + if (_set_vc_itf(rhport, &_videod_itf[itf], request->wValue)) + return VIDEO_NO_ERROR; + return VIDEO_UNKNOWN; + default: /* Unknown/Unsupported request */ + TU_BREAKPOINT(); + return VIDEO_INVALID_REQUEST; + } +} + +static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf) +{ + videod_interface_t *self = &_videod_itf[i]; + /* 4.2.1 Interface Control Request */ + switch (TU_U16_HIGH(request->wValue)) { + case VIDEO_VC_CTL_VIDEO_POWER_MODE: + switch (p_request->bRequest) { + case VIDEO_REQUEST_SET_CUR: + if (stage == CONTROL_STAGE_SETUP) { + TU_LOG2(" Set Power Mode\r\n"); + TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN); + if (!tud_control_xfer(rhport, request, &self->power_mode, sizeof(self->power_mode))) + return VIDEO_UNKNOWN; + } else if (stage == CONTROL_STAGE_ACK) { + if (tud_video_power_mode_cb) return tud_video_power_mode_cb(itf, &self->power_mode); + } + return VIDEO_NO_ERROR; + case VIDEO_REQUEST_GET_CUR: + if (stage == CONTROL_STAGE_SETUP) { + TU_LOG2(" Get Power Mode\r\n"); + TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN); + if (!tud_control_xfer(rhport, request, &self->power_mode, sizeof(self->power_mode))) + return VIDEO_UNKNOWN; + } + return VIDEO_NO_ERROR; + case VIDEO_REQUEST_GET_INFO: + if (stage == CONTROL_STAGE_SETUP) { + TU_LOG2(" Get Info Power Mode\r\n"); + TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN); + if (!tud_control_xfer(rhport, request, &_cap_get_set, sizeof(_cap_get_set))) + return VIDEO_UNKNOWN; + } + return VIDEO_NO_ERROR; + default: break; } - tud_control_xfer(rhport, request, &vs->std.bAlternateSettings, sizeof(vs->std.bAlternateSettings)); - return true; + break; + case VIDEO_VC_CTL_REQUEST_ERROR_CODE: + switch (p_request->bRequest) { + case VIDEO_REQUEST_GET_CUR: + if (stage == CONTROL_STAGE_SETUP) { + TU_LOG2(" Get Error Code\r\n"); + if (!tud_control_xfer(rhport, request, &self->error_code, sizeof(self->error_code))) + return VIDEO_UNKNOWN; + } + return VIDEO_NO_ERROR; + case VIDEO_REQUEST_GET_INFO: + if (stage == CONTROL_STAGE_SETUP) { + TU_LOG2(" Get Info Error Code\r\n"); + if (tud_control_xfer(rhport, request, &_cap_get, sizeof(_cap_get))) + return VIDEO_UNKNOWN; + } + return VIDEO_NO_ERROR; + default: break; + } + break; + default: break; } - return false; + /* Unknown/Unsupported request */ + TU_BREAKPOINT(); + return VIDEO_INVALID_REQUEST; } -static bool videod_set_itf(uint8_t rhport, videod_interface_t *self, tusb_control_request_t const * request) +static int handle_video_ctl_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf) { - (void)rhport; - unsigned altnum = tu_u16_low(p_request->wValue); - unsigned itfnum = tu_u16_low(p_request->wLength); + switch (p_request->bmRequestType_bit.type) { + case TUSB_REQ_TYPE_STANDARD: + return handle_video_ctl_std_req(rhport, stage, request, itf); + case TUSB_REQ_TYPE_CLASS: + if (!TU_U16_HIGH(request->wIndex)) { + return handle_video_ctl_cs_req(rhport, stage, request, itf); + } else { + /* TODO: */ + return VIDEO_INVALID_REQUEST; + } + default: + return VIDEO_INVALID_REQUEST; + } +} - tusb_desc_vc_itf_t const *vc = self->vc; - if (vc->std.bInterfaceNumber == itfnum) { - if (videod_set_vc_itf(self, altnum)) - return true; - return false; +static int handle_video_stm_std_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf) +{ + switch (p_request->bRequest) { + case TUSB_REQ_GET_INTERFACE: + handle_video_ctl_std_req_get_itf(rhport, stage, request, itf); + case TUSB_REQ_SET_INTERFACE: + videod_interface_t *self = &_videod_itf[itf]; + unsigned itfnum = tu_u16_low(p_request->wIndex); + if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; + if (_set_vs_itf(rhport, self, itfnum, request->wValue)) + return VIDEO_NO_ERROR; + return VIDEO_UNKNOWN; + default: /* Unknown/Unsupported request */ + TU_BREAKPOINT(); + return VIDEO_INVALID_REQUEST; } - for (unsigned i = 0; i < vc->ctl.bInCollection; ++i) { - tusb_desc_vs_itf_t const *vs = self->vs[i]; - if (!vs || vs->std.bInterfaceNumber == itfnum) { - continue; +} + +static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf) +{ + videod_interface_t *self = &_videod_itf[i]; + /* 4.2.1 Interface Control Request */ + switch (TU_U16_HIGH(request->wValue)) { + case VIDEO_VS_CTL_PROBE: + switch (p_request->bRequest) { + case VIDEO_REQUEST_SET_CUR: + if (stage == CONTROL_STAGE_SETUP) { + TU_LOG2(" Set Power Mode\r\n"); + TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN); + if (!tud_control_xfer(rhport, request, &self->power_mode, sizeof(self->power_mode))) + return VIDEO_UNKNOWN; + } else if (stage == CONTROL_STAGE_ACK) { + if (tud_video_power_mode_cb) return tud_video_power_mode_cb(itf, &self->power_mode); + } + return VIDEO_NO_ERROR; + case VIDEO_REQUEST_GET_CUR: + if (stage == CONTROL_STAGE_SETUP) { + TU_LOG2(" Get Power Mode\r\n"); + TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN); + if (!tud_control_xfer(rhport, request, &self->power_mode, sizeof(self->power_mode))) + return VIDEO_UNKNOWN; + } + return VIDEO_NO_ERROR; + case VIDEO_REQUEST_GET_INFO: + if (stage == CONTROL_STAGE_SETUP) { + TU_LOG2(" Get Info Power Mode\r\n"); + TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN); + if (!tud_control_xfer(rhport, request, &_cap_get_set, sizeof(_cap_get_set))) + return VIDEO_UNKNOWN; + } + return VIDEO_NO_ERROR; + default: break; } - if (videod_set_vs_itf(self, itfnum, altnum)) - return true; - return false; + break; + case VIDEO_VS_CTL_COMMIT: + switch (p_request->bRequest) { + case VIDEO_REQUEST_GET_CUR: + if (stage == CONTROL_STAGE_SETUP) { + TU_LOG2(" Get Error Code\r\n"); + if (!tud_control_xfer(rhport, request, &self->error_code, sizeof(self->error_code))) + return VIDEO_UNKNOWN; + } + return VIDEO_NO_ERROR; + case VIDEO_REQUEST_GET_INFO: + if (stage == CONTROL_STAGE_SETUP) { + TU_LOG2(" Get Info Error Code\r\n"); + if (tud_control_xfer(rhport, request, &_cap_get, sizeof(_cap_get))) + return VIDEO_UNKNOWN; + } + return VIDEO_NO_ERROR; + default: break; + } + break; + default: break; } - return false; + /* Unknown/Unsupported request */ + TU_BREAKPOINT(); + return VIDEO_INVALID_REQUEST; +} + +static int handle_video_stm_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf) +{ + switch (p_request->bmRequestType_bit.type) { + case TUSB_REQ_TYPE_STANDARD: + return handle_video_stm_std_req(rhport, stage, request, itf); + case TUSB_REQ_TYPE_CLASS: + if (TU_U16_HIGH(request->wIndex)) + return VIDEO_INVALID_REQUEST; + return handle_video_stm_cs_req(rhport, stage, request, itf); + default: + return VIDEO_INVALID_REQUEST; + } + return VIDEO_UNKNOWN; } -static void _prep_out_transaction (cdcd_interface_t* p_cdc) +static void _prep_out_transaction(cdcd_interface_t* p_cdc) { uint8_t const rhport = TUD_OPT_RHPORT; uint16_t available = tu_fifo_remaining(&p_cdc->rx_ff); @@ -440,31 +732,23 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin void const *end = (void const*)itf_desc + max_len; self->beg = itf_desc; - self->end = end; + self->len = max_len; /*------------- Video Control Interface -------------*/ - void const* cur = videod_set_vc_itf(self, 0); - TU_VERIFY(cur, 0); - unsigned bInCollection = self->vc->ctl.bInCollection; + if (!_open_vc_itf(rhport, self, 0)) return 0; + tusb_desc_vc_itf_t const *vc = _get_desc_vc(self); + unsigned bInCollection = vc->ctl.bInCollection; + /* Update end */ + void const *cur = _next_desc_itf(itf_desc, end); + for (unsigned i = 0; i < bInCollection; ++i) { + cur = _next_desc_itf(cur, end); + } + self->len = (uintptr_t)cur - (uintptr_t)itf_desc; /*------------- Video Stream Interface -------------*/ unsigned itfnum = 0; for (unsigned i = 0; i < bInCollection; ++i) { itfnum = vc->ctl.baInterfaceNr[i]; - cur = videod_set_vs_itf(self, itfnum, 0); - TU_VERIFY(cur, 0); + if (!_open_vs_itf(rhport, self, itfnum, 0)) return 0; } - - /* Skip alternate setting interfaces */ - while (cur < end && TUSB_DESC_INTERFACE == tu_desc_type(cur)) { - tusb_desc_vs_itf_t const *vs = (tusb_desc_vs_itf_t const *)cur; - if (itfnum != vs->std.bInterfaceNumber || - TUSB_DESC_CS_INTERFACE != vs->stm.bDescriptorType || - (VIDEO_CS_VS_INTERFACE_INPUT_HEADER != vs->stm.bDescriptorSubType && - VIDEO_CS_VS_INTERFACE_OUTPUT_HEADER!= vs->stm.bDescriptorSubType)) { - break; - } - cur += itf->std.bLength + itf->stm.bLength + itf->stm.wTotalLength; - } - self->end = cur; return end - cur; } @@ -473,61 +757,33 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin // return false to stall control endpoint (e.g unsupported request) bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request) { + int err; if (p_request->bmRequestType_bit.recipient != TUSB_REQ_RCPT_INTERFACE) { return false; } unsigned itfnum = tu_u16_low(p_request->wIndex); /* Identify which interface to use */ - videod_interface_t *self = NULL; - for (unsigned i = 0; i < CFG_TUD_VIDEO; ++i) { - if (_videod_itf[i].vc->bInterfaceNumber == itfnum) { - self = &_videod_itf[i]; + int itf; + tusb_desc_vc_itf_t const *vc = NULL; + for (itf = 0; itf < CFG_TUD_VIDEO; ++itf) { + vc = _videod_itf[itf].vc; + if (!vc) continue; + unsigned beg_itfnum = vc->bInterfaceNumber; + unsigned end_itfnum = vc->ctl.bInCollection; + if (beg_itfnum <= itfnum && itfnum < end_itfnum) break; - } } - if (!self) return false; - - /* Standard request */ - if (p_request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD) { - if (stage != CONTROL_STAGE_SETUP) return true; - switch (p_request->bRequest) { - case TUSB_REQ_GET_INTERFACE: - return videod_get_itf(rhport, self, request); - case TUSB_REQ_SET_INTERFACE: - return videod_set_itf(rhport, self, request); - default: /* Unknown/Unsupported request */ - TU_BREAKPOINT(); - return false; - } + if (itf == CFG_TUD_VIDEO) return false; + + if (itfnum == vc->bInterfaceNumber) { + /* To video control interface */ + err = handle_video_ctl_req(rhport, stage, request, itf); + } else { + /* To video streaming interface */ + err = handle_video_stm_req(rhport, stage, request, itf); } - - unsigned cs = TU_U16_HIGH(request->wValue); - unsigned uid = TU_U16_HIGH(request->wIndex); - - switch (request->bRequest) { - case VIDEO_REQUEST_GET_INFO: - TU_VERIFY(1 == request->wLength); - - break; - case VIDEO_REQUEST_SET_CUR: - if (stage == CONTROL_STAGE_SETUP) { - TU_LOG2(" Set Current Setting Attribute\r\n"); - tud_control_xfer(rhport, request, &p_video->line_coding, sizeof(cdc_line_coding_t)); - } else if ( stage == CONTROL_STAGE_ACK) { - if ( tud_cdc_line_coding_cb ) tud_cdc_line_coding_cb(itf, &p_video->line_coding); - } - break; - case VIDEO_REQUEST_GET_CUR: - if (stage == CONTROL_STAGE_SETUP) { - TU_LOG2(" Set Current Setting Attribute\r\n"); - tud_control_xfer(rhport, request, &p_video->line_coding, sizeof(cdc_line_coding_t)); - } else if ( stage == CONTROL_STAGE_ACK) { - if ( tud_cdc_line_coding_cb ) tud_cdc_line_coding_cb(itf, &p_video->line_coding); - } - break; - default: return false; // stall unsupported request - } - + _videod_itf[itf].error_code = (uint8_t)err; + if (err) return false; return true; } diff --git a/src/class/video/video_device.h b/src/class/video/video_device.h index e0ff21694..cd04b7391 100644 --- a/src/class/video/video_device.h +++ b/src/class/video/video_device.h @@ -28,8 +28,11 @@ #ifndef TUSB_VIDEO_DEVICE_H_ #define TUSB_VIDEO_DEVICE_H_ +#include "common/tusb_common.h" +#include "video.h" + #ifdef __cplusplus - extern "C" { +extern "C" { #endif //--------------------------------------------------------------------+ @@ -41,7 +44,7 @@ TU_ATTR_WEAK bool tud_video_get_info_cb(uint8_t rhport, tusb_control_request_t c // Invoked when GET_INFO request received TU_ATTR_WEAK bool tud_video_set_cur_cb(uint8_t rhport, tusb_control_request_t const *request); // Invoked when GET_CUR request received -TU_ATTR_WEAK bool tud_video_get_info_cb(uint8_t rhport, tusb_control_request_t const *request); +TU_ATTR_WEAK bool tud_video_get_cur_cb(uint8_t rhport, tusb_control_request_t const *request); //--------------------------------------------------------------------+ // INTERNAL USBD-CLASS DRIVER API diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h index f26983a74..897e89b39 100644 --- a/src/common/tusb_types.h +++ b/src/common/tusb_types.h @@ -69,6 +69,18 @@ typedef enum TUSB_DIR_IN_MASK = 0x80 }tusb_dir_t; +/// Isochronous End Point Attributes +typedef enum +{ + TUSB_ISO_EP_ATT_NO_SYNC = 0x00, + TUSB_ISO_EP_ATT_ASYNCHRONOUS = 0x04, + TUSB_ISO_EP_ATT_ADAPTIVE = 0x08, + TUSB_ISO_EP_ATT_SYNCHRONOUS = 0x0C, + TUSB_ISO_EP_ATT_DATA = 0x00, ///< Data End Point + TUSB_ISO_EP_ATT_EXPLICIT_FB = 0x10, ///< Feedback End Point + TUSB_ISO_EP_ATT_IMPLICIT_FB = 0x20, ///< Data endpoint that also serves as an implicit feedback +}tusb_iso_ep_attribute_t; + /// USB Descriptor Types typedef enum { -- cgit v1.3.1 From 019c1ab09e98517ce5422e9a0e2995928feff027 Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Sat, 31 Jul 2021 19:35:22 +0900 Subject: add tentative example --- examples/device/video_capture/Makefile | 12 + examples/device/video_capture/src/main.c | 123 ++++++ examples/device/video_capture/src/tusb_config.h | 106 ++++++ .../device/video_capture/src/usb_descriptors.c | 172 +++++++++ .../device/video_capture/src/usb_descriptors.h | 97 +++++ src/class/video/video.h | 18 +- src/class/video/video_device.c | 418 ++++++--------------- src/class/video/video_device.h | 2 + 8 files changed, 638 insertions(+), 310 deletions(-) create mode 100644 examples/device/video_capture/Makefile create mode 100644 examples/device/video_capture/src/main.c create mode 100644 examples/device/video_capture/src/tusb_config.h create mode 100644 examples/device/video_capture/src/usb_descriptors.c create mode 100644 examples/device/video_capture/src/usb_descriptors.h diff --git a/examples/device/video_capture/Makefile b/examples/device/video_capture/Makefile new file mode 100644 index 000000000..69b633fea --- /dev/null +++ b/examples/device/video_capture/Makefile @@ -0,0 +1,12 @@ +include ../../../tools/top.mk +include ../../make.mk + +INC += \ + src \ + $(TOP)/hw \ + +# Example source +EXAMPLE_SOURCE += $(wildcard src/*.c) +SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE)) + +include ../../rules.mk diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c new file mode 100644 index 000000000..098cd2f8d --- /dev/null +++ b/examples/device/video_capture/src/main.c @@ -0,0 +1,123 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + */ + +#include +#include +#include + +#include "bsp/board.h" +#include "tusb.h" + +//--------------------------------------------------------------------+ +// MACRO CONSTANT TYPEDEF PROTYPES +//--------------------------------------------------------------------+ + +/* Blink pattern + * - 250 ms : device not mounted + * - 1000 ms : device mounted + * - 2500 ms : device is suspended + */ +enum { + BLINK_NOT_MOUNTED = 250, + BLINK_MOUNTED = 1000, + BLINK_SUSPENDED = 2500, +}; + +static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED; + +void led_blinking_task(void); +void video_task(void); + +/*------------- MAIN -------------*/ +int main(void) +{ + board_init(); + tusb_init(); + + while (1) + { + tud_task(); // tinyusb device task + led_blinking_task(); + + video_task(); + } + + return 0; +} + +//--------------------------------------------------------------------+ +// Device callbacks +//--------------------------------------------------------------------+ + +// Invoked when device is mounted +void tud_mount_cb(void) +{ + blink_interval_ms = BLINK_MOUNTED; +} + +// Invoked when device is unmounted +void tud_umount_cb(void) +{ + blink_interval_ms = BLINK_NOT_MOUNTED; +} + +// Invoked when usb bus is suspended +// remote_wakeup_en : if host allow us to perform remote wakeup +// Within 7ms, device must draw an average of current less than 2.5 mA from bus +void tud_suspend_cb(bool remote_wakeup_en) +{ + (void) remote_wakeup_en; + blink_interval_ms = BLINK_SUSPENDED; +} + +// Invoked when usb bus is resumed +void tud_resume_cb(void) +{ + blink_interval_ms = BLINK_MOUNTED; +} + + +//--------------------------------------------------------------------+ +// USB Video +//--------------------------------------------------------------------+ +void video_task(void) +{ +} + +//--------------------------------------------------------------------+ +// BLINKING TASK +//--------------------------------------------------------------------+ +void led_blinking_task(void) +{ + static uint32_t start_ms = 0; + static bool led_state = false; + + // Blink every interval ms + if ( board_millis() - start_ms < blink_interval_ms) return; // not enough time + start_ms += blink_interval_ms; + + board_led_write(led_state); + led_state = 1 - led_state; // toggle +} diff --git a/examples/device/video_capture/src/tusb_config.h b/examples/device/video_capture/src/tusb_config.h new file mode 100644 index 000000000..ae2387357 --- /dev/null +++ b/examples/device/video_capture/src/tusb_config.h @@ -0,0 +1,106 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + */ + +#ifndef _TUSB_CONFIG_H_ +#define _TUSB_CONFIG_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +//-------------------------------------------------------------------- +// COMMON CONFIGURATION +//-------------------------------------------------------------------- + +// RHPort number used for device can be defined by board.mk, default to port 0 +#ifndef BOARD_DEVICE_RHPORT_NUM + #define BOARD_DEVICE_RHPORT_NUM 0 +#endif + +// RHPort max operational speed can defined by board.mk +// Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed +#ifndef BOARD_DEVICE_RHPORT_SPEED + #if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \ + CFG_TUSB_MCU == OPT_MCU_NUC505 || CFG_TUSB_MCU == OPT_MCU_CXD56) + #define BOARD_DEVICE_RHPORT_SPEED OPT_MODE_HIGH_SPEED + #else + #define BOARD_DEVICE_RHPORT_SPEED OPT_MODE_FULL_SPEED + #endif +#endif + +// Device mode with rhport and speed defined by board.mk +#if BOARD_DEVICE_RHPORT_NUM == 0 + #define CFG_TUSB_RHPORT0_MODE (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED) +#elif BOARD_DEVICE_RHPORT_NUM == 1 + #define CFG_TUSB_RHPORT1_MODE (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED) +#else + #error "Incorrect RHPort configuration" +#endif + +// This example doesn't use an RTOS +#ifndef CFG_TUSB_OS +#define CFG_TUSB_OS OPT_OS_NONE +#endif + +// CFG_TUSB_DEBUG is defined by compiler in DEBUG build +// #define CFG_TUSB_DEBUG 0 + +/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment. + * Tinyusb use follows macros to declare transferring memory so that they can be put + * into those specific section. + * e.g + * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") )) + * - CFG_TUSB_MEM_ALIGN : __attribute__ ((aligned(4))) + */ +#ifndef CFG_TUSB_MEM_SECTION +#define CFG_TUSB_MEM_SECTION +#endif + +#ifndef CFG_TUSB_MEM_ALIGN +#define CFG_TUSB_MEM_ALIGN __attribute__ ((aligned(4))) +#endif + +//-------------------------------------------------------------------- +// DEVICE CONFIGURATION +//-------------------------------------------------------------------- + +#ifndef CFG_TUD_ENDPOINT0_SIZE +#define CFG_TUD_ENDPOINT0_SIZE 64 +#endif + +//------------- CLASS -------------// +#define CFG_TUD_CDC 0 +#define CFG_TUD_MSC 0 +#define CFG_TUD_HID 0 +#define CFG_TUD_MIDI 0 +#define CFG_TUD_AUDIO 0 +#define CFG_TUD_VIDEO 1 +#define CFG_TUD_VENDOR 0 + +#ifdef __cplusplus + } +#endif + +#endif /* _TUSB_CONFIG_H_ */ diff --git a/examples/device/video_capture/src/usb_descriptors.c b/examples/device/video_capture/src/usb_descriptors.c new file mode 100644 index 000000000..df8c41721 --- /dev/null +++ b/examples/device/video_capture/src/usb_descriptors.c @@ -0,0 +1,172 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + */ + +#include "tusb.h" +#include "usb_descriptors.h" + +/* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug. + * Same VID/PID with different interface e.g MSC (first), then CDC (later) will possibly cause system error on PC. + * + * Auto ProductID layout's Bitmap: + * [MSB] VIDEO | AUDIO | MIDI | HID | MSC | CDC [LSB] + */ +#define _PID_MAP(itf, n) ( (CFG_TUD_##itf) << (n) ) +#define USB_PID (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \ + _PID_MAP(MIDI, 3) | _PID_MAP(AUDIO, 4) | _PID_MAP(VIDEO, 5) | _PID_MAP(VENDOR, 6) ) + +//--------------------------------------------------------------------+ +// Device Descriptors +//--------------------------------------------------------------------+ +tusb_desc_device_t const desc_device = +{ + .bLength = sizeof(tusb_desc_device_t), + .bDescriptorType = TUSB_DESC_DEVICE, + .bcdUSB = 0x0200, + + // Use Interface Association Descriptor (IAD) for CDC + // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1) + .bDeviceClass = TUSB_CLASS_MISC, + .bDeviceSubClass = MISC_SUBCLASS_COMMON, + .bDeviceProtocol = MISC_PROTOCOL_IAD, + + .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE, + + .idVendor = 0xCafe, + .idProduct = USB_PID, + .bcdDevice = 0x0100, + + .iManufacturer = 0x01, + .iProduct = 0x02, + .iSerialNumber = 0x03, + + .bNumConfigurations = 0x01 +}; + +// Invoked when received GET DEVICE DESCRIPTOR +// Application return pointer to descriptor +uint8_t const * tud_descriptor_device_cb(void) +{ + return (uint8_t const *) &desc_device; +} + +//--------------------------------------------------------------------+ +// Configuration Descriptor +//--------------------------------------------------------------------+ + +#define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + TUD_VIDEO_CAPTURE_DESC_LEN) + +#if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX + // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number + // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In, 5 Bulk etc ... + #define EPNUM_VIDEO_IN 0x83 + +#elif CFG_TUSB_MCU == OPT_MCU_SAMG || CFG_TUSB_MCU == OPT_MCU_CXD56 + // SAMG doesn't support a same endpoint number with different direction IN and OUT + // e.g EP1 OUT & EP1 IN cannot exist together + #define EPNUM_VIDEO_IN 0x81 + +#elif CFG_TUSB_MCU == OPT_MCU_CXD56 + // CXD56 doesn't support a same endpoint number with different direction IN and OUT + // e.g EP1 OUT & EP1 IN cannot exist together + // CXD56 USB driver has fixed endpoint type (bulk/interrupt/iso) and direction (IN/OUT) by its number + // 0 control (IN/OUT), 1 Bulk (IN), 2 Bulk (OUT), 3 In (IN), 4 Bulk (IN), 5 Bulk (OUT), 6 In (IN) + #define EPNUM_VIDEO_IN 0x81 + +#else + #define EPNUM_VIDEO_IN 0x81 + +#endif + +uint8_t const desc_fs_configuration[] = +{ + // Config number, interface count, string index, total length, attribute, power in mA + TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100), + // IAD for Video Control + TUD_VIDEO_CAPTURE_DESCRIPTOR(4, EPNUM_VIDEO_IN, 128, 96, 15) +}; + +// Invoked when received GET CONFIGURATION DESCRIPTOR +// Application return pointer to descriptor +// Descriptor contents must exist long enough for transfer to complete +uint8_t const * tud_descriptor_configuration_cb(uint8_t index) +{ + (void) index; // for multiple configurations + + return desc_fs_configuration; +} + +//--------------------------------------------------------------------+ +// String Descriptors +//--------------------------------------------------------------------+ + +// array of pointer to string descriptors +char const* string_desc_arr [] = +{ + (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409) + "TinyUSB", // 1: Manufacturer + "TinyUSB Device", // 2: Product + "123456", // 3: Serials, should use chip ID + "TinyUSB UVC", // 4: UVC Interface +}; + +static uint16_t _desc_str[32]; + +// Invoked when received GET STRING DESCRIPTOR request +// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete +uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid) +{ + (void) langid; + + uint8_t chr_count; + + if ( index == 0) + { + memcpy(&_desc_str[1], string_desc_arr[0], 2); + chr_count = 1; + }else + { + // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors. + // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors + + if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL; + + const char* str = string_desc_arr[index]; + + // Cap at max char + chr_count = strlen(str); + if ( chr_count > 31 ) chr_count = 31; + + // Convert ASCII string into UTF-16 + for(uint8_t i=0; ibeg + *ofs); +} + + /** Find the first descriptor with the specified descriptor type. * * @param[in] beg The head of descriptor byte array. @@ -188,6 +196,10 @@ static void const* _find_desc_entity(tusb_desc_vc_itf_t const *vc, unsigned enti return end; } +/** Close current video control interface. + * + * @param[in,out] self The context. + * @param[in] altnum The target alternate setting number. */ static bool _close_vc_itf(uint8_t rhport, videod_interface_t *self) { tusb_desc_vc_itf_t const *vc = _get_desc_vc(self); @@ -206,60 +218,23 @@ static bool _close_vc_itf(uint8_t rhport, videod_interface_t *self) return true; } -static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, unsigned altnum) -{ - void const *beg = self->beg; - void const *end = beg + self->len; - /* The first descriptor is a video control interface descriptor. */ - unsigned itfnum = ((tusb_desc_interface_t const *)beg)->bInterfaceNumber; - void const *cur = _find_desc_itf(beg, end, itfnum, altnum); - TU_VERIFY(cur < end); - - tusb_desc_vc_itf_t const *vc = (tusb_desc_vc_itf_t const *)cur; - /* Support for up to 2 streaming interfaces only. */ - TU_ASSERT(vc->ctl.bInCollection < 3); - - /* Advance to the next descriptor after the class-specific VC interface header descriptor. */ - cur += vc->std.bLength + vc->ctl.bLength; - /* Update to point the end of the video control interface descriptor. */ - end = cur + vc->ctl.wTotalLength; - /* Open the notification endpoint if it exist. */ - if (vc->std.bNumEndpoints) { - /* Support for 1 endpoint only. */ - TU_VERIFY(1 == vc->std.bNumEndpoints); - /* Find the notification endpoint descriptor. */ - cur = _find_desc(cur, end, TUSB_DESC_ENDPOINT); - TU_VERIFY(cur < end); - tusb_desc_endpoint_t const *notif = (tusb_desc_endpoint_t const *)cur; - /* Open the notification endpoint */ - TU_ASSERT(usbd_edpt_open(rhport, notif)); - } - self->ofs[0] = (void const*)vc - beg; - return true; -} - /** Set the specified alternate setting to own video control interface. * * @param[in,out] self The context. * @param[in] altnum The target alternate setting number. */ -static bool _set_vc_itf(uint8_t rhport, videod_interface_t *self, unsigned altnum) +static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, unsigned altnum) { void const *beg = self->beg; void const *end = beg + self->len; - /* The head descriptor is a video control interface descriptor. */ + /* The first descriptor is a video control interface descriptor. */ unsigned itfnum = ((tusb_desc_interface_t const *)beg)->bInterfaceNumber; void const *cur = _find_desc_itf(beg, end, itfnum, altnum); TU_VERIFY(cur < end); tusb_desc_vc_itf_t const *vc = (tusb_desc_vc_itf_t const *)cur; /* Support for up to 2 streaming interfaces only. */ - TU_VERIFY(vc->ctl.bInCollection < 3); + TU_ASSERT(vc->ctl.bInCollection < 3); - /* Close the previous notification endpoint if it is opened */ - if (self->ep_notif) { - usbd_edpt_close(rhport, self->ep_notif); - self->ep_notif = 0; - } /* Advance to the next descriptor after the class-specific VC interface header descriptor. */ cur += vc->std.bLength + vc->ctl.bLength; /* Update to point the end of the video control interface descriptor. */ @@ -274,7 +249,6 @@ static bool _set_vc_itf(uint8_t rhport, videod_interface_t *self, unsigned altnu tusb_desc_endpoint_t const *notif = (tusb_desc_endpoint_t const *)cur; /* Open the notification endpoint */ TU_ASSERT(usbd_edpt_open(rhport, notif)); - self->ep_notif = notif->bEndpointAddress; } self->ofs[0] = (void const*)vc - beg; return true; @@ -293,7 +267,7 @@ static bool _close_vs_itf(uint8_t rhport, videod_interface_t *self, unsigned itf void const *cur = (void const*)vs + vs->std.bLength + vs->stm.bLength; /* The end of the video streaming interface descriptor. */ void const *end = cur + vs->stm.wTotalLength; - if (unsigned i = 0; i < vs->std.bNumEndpoints; ++i) { + for (unsigned i = 0; i < vs->std.bNumEndpoints; ++i) { cur = _find_desc(cur, end, TUSB_DESC_ENDPOINT); TU_ASSERT(cur < end); tusb_desc_endpoint_t const *ep = (tusb_desc_endpoint_t const *)cur; @@ -345,123 +319,28 @@ static bool _open_vs_itf(uint8_t rhport, videod_interface_t *self, unsigned itfn return true; } -/** Set the specified alternate setting to own video control interface. - * - * @param[in,out] self The context. - * @param[in] itfnum The target interface number. - * @param[in] altnum The target alternate setting number. */ -static bool _set_vs_itf(uint8_t rhport, videod_interface_t *self, unsigned itfnum, unsigned altnum) -{ - unsigned i; - tusb_desc_vc_itf_t const *vc = _get_desc_vc(self); - void const *end = self->beg + self->len; - /* Set the end of the video control interface descriptor. */ - void const *cur = (void const*)vc + vc->std.bLength + vc->ctl.bLength + vc->ctl.wTotalLength; - - /* Check itfnum is valid */ - unsigned bInCollection = vc->ctl.bInCollection; - for (i = 0; (i < bInCollection) && (vc->ctl.baInterfaceNr[i] != itfnum); ++i) ; - TU_VERIFY(i < bInCollection); - - cur = _find_desc_itf(cur, end, itfnum, altnum); - TU_VERIFY(cur < end); - tusb_desc_vs_itf_t const *vs = (tusb_desc_vs_itf_t const*)cur; - /* Advance to the next descriptor after the class-specific VS interface header descriptor. */ - cur += vs->std.bLength + vs->stm.bLength; - /* Update to point the end of the video control interface descriptor. */ - end = cur + vs->stm.wTotalLength; - - switch (vs->stm.bDescriptorSubType) { - default: return false; - case VIDEO_CS_VS_INTERFACE_INPUT_HEADER: - /* Support for up to 2 endpoint only. */ - TU_VERIFY(vc->std.bNumEndpoints < 3); - if (self->ep_sti) { - usbd_edpt_close(rhport, self->ep_sti); - self->ep_sti = 0; - } - if (self->ep_in) { - usbd_edpt_close(rhport, self->ep_in); - self->ep_in = 0; - } - if (i = 0; i < vs->std.bNumEndpoints; ++i) { - cur = _find_desc(cur, end, TUSB_DESC_ENDPOINT); - TU_VERIFY(cur < end); - tusb_desc_endpoint_t const *ep = (tusb_desc_endpoint_t const *)cur; - if (vs->stm.bEndpointAddress == ep->bEndpointAddress) { - /* video input endpoint */ - TU_ASSERT(!self->ep_in); - TU_ASSERT(usbd_edpt_open(rhport, ep)); - self->ep_in = ep->bEndpointAddress; - } else { - /* still image input endpoint */ - TU_ASSERT(!self->ep_sti); - TU_ASSERT(usbd_edpt_open(rhport, ep)); - self->ep_sti = ep->bEndpointAddress; - } - cur += tu_desc_len(cur); - } - break; - case VIDEO_CS_VS_INTERFACE_OUTPUT_HEADER: - /* Support for up to 1 endpoint only. */ - TU_VERIFY(vc->std.bNumEndpoints < 2); - if (self->ep_out) { - usbd_edpt_close(rhport, self->ep_out); - self->ep_out = 0; - } - if (vs->std.bNumEndpoints) { - cur = _find_desc(cur, end, TUSB_DESC_ENDPOINT); - TU_VERIFY(cur < end); - tusb_desc_endpoint_t const *ep = (tusb_desc_endpoint_t const *)cur; - if (vs->stm.bEndpointAddress == ep->bEndpointAddress) { - /* video output endpoint */ - TU_ASSERT(usbd_edpt_open(rhport, ep)); - self->ep_out = ep->bEndpointAddress; - } - } - break; - } - for (unsigned i = 1; i < sizeof(self->ofs)/sizeof(ofs[0]); ++i) { - if (!self->ofs[i]) { - return true; - } - tusb_desc_interface_t const* itf = (tusb_desc_interface_t const*)(beg + ofs[i]); - if (itfnum == itf->bInterfaceNumber) return itf; - } - return NULL; - for (i = 0; i < sizeof(self->vs)/sizeof(self->vs[0]); ++i) { - if (!self->vs[i] || self->vs[i].stm.bInterfaceNumber == vs->stm.bInterfaceNumber) { - self->ofs[i] = (void const*)vs - self->beg; - return true; - } - } - return false; -} - -static int handle_video_ctl_std_req_get_itf(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf) -{ - if (stage != CONTROL_STAGE_SETUP) - return VIDEO_NO_ERROR; - videod_interface_t *self = &_videod_itf[itf]; - TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN); - tusb_desc_interface_t const *p = _get_desc_cur_itf(self, itfnum); - if (!p) return VIDEO_UNKNOWN; - if (tud_control_xfer(rhport, request, &p->bAlternateSettings, sizeof(p->bAlternateSettings))) - return VIDEO_NO_ERROR; - return VIDEO_UNKNOWN; -} - /** Handle a standard request to the video control interface. */ static int handle_video_ctl_std_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf) { - switch (p_request->bRequest) { + switch (request->bRequest) { case TUSB_REQ_GET_INTERFACE: - handle_video_ctl_std_req_get_itf(rhport, stage, request, itf); - case TUSB_REQ_SET_INTERFACE: if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; - if (_set_vc_itf(rhport, &_videod_itf[itf], request->wValue)) + TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN); + tusb_desc_vc_itf_t const *vc = _get_desc_vc(&_videod_itf[itf]); + if (!vc) return VIDEO_UNKNOWN; + if (tud_control_xfer(rhport, request, + (void*)&vc->std.bAlternateSetting, + sizeof(vc->std.bAlternateSetting))) return VIDEO_NO_ERROR; return VIDEO_UNKNOWN; + case TUSB_REQ_SET_INTERFACE: + if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; + TU_VERIFY(0 == request->wLength, VIDEO_UNKNOWN); + if (!_close_vc_itf(rhport, &_videod_itf[itf])) + return VIDEO_UNKNOWN; + if (!_open_vc_itf(rhport, &_videod_itf[itf], request->wValue)) + return VIDEO_UNKNOWN; + return VIDEO_NO_ERROR; default: /* Unknown/Unsupported request */ TU_BREAKPOINT(); return VIDEO_INVALID_REQUEST; @@ -470,11 +349,11 @@ static int handle_video_ctl_std_req(uint8_t rhport, uint8_t stage, tusb_control_ static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf) { - videod_interface_t *self = &_videod_itf[i]; + videod_interface_t *self = &_videod_itf[itf]; /* 4.2.1 Interface Control Request */ switch (TU_U16_HIGH(request->wValue)) { case VIDEO_VC_CTL_VIDEO_POWER_MODE: - switch (p_request->bRequest) { + switch (request->bRequest) { case VIDEO_REQUEST_SET_CUR: if (stage == CONTROL_STAGE_SETUP) { TU_LOG2(" Set Power Mode\r\n"); @@ -482,7 +361,7 @@ static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r if (!tud_control_xfer(rhport, request, &self->power_mode, sizeof(self->power_mode))) return VIDEO_UNKNOWN; } else if (stage == CONTROL_STAGE_ACK) { - if (tud_video_power_mode_cb) return tud_video_power_mode_cb(itf, &self->power_mode); + if (tud_video_power_mode_cb) return tud_video_power_mode_cb(itf, self->power_mode); } return VIDEO_NO_ERROR; case VIDEO_REQUEST_GET_CUR: @@ -497,7 +376,7 @@ static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r if (stage == CONTROL_STAGE_SETUP) { TU_LOG2(" Get Info Power Mode\r\n"); TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN); - if (!tud_control_xfer(rhport, request, &_cap_get_set, sizeof(_cap_get_set))) + if (!tud_control_xfer(rhport, request, (uint8_t*)&_cap_get_set, sizeof(_cap_get_set))) return VIDEO_UNKNOWN; } return VIDEO_NO_ERROR; @@ -505,7 +384,7 @@ static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r } break; case VIDEO_VC_CTL_REQUEST_ERROR_CODE: - switch (p_request->bRequest) { + switch (request->bRequest) { case VIDEO_REQUEST_GET_CUR: if (stage == CONTROL_STAGE_SETUP) { TU_LOG2(" Get Error Code\r\n"); @@ -516,7 +395,7 @@ static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r case VIDEO_REQUEST_GET_INFO: if (stage == CONTROL_STAGE_SETUP) { TU_LOG2(" Get Info Error Code\r\n"); - if (tud_control_xfer(rhport, request, &_cap_get, sizeof(_cap_get))) + if (tud_control_xfer(rhport, request, (uint8_t*)&_cap_get, sizeof(_cap_get))) return VIDEO_UNKNOWN; } return VIDEO_NO_ERROR; @@ -532,14 +411,17 @@ static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r static int handle_video_ctl_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf) { - switch (p_request->bmRequestType_bit.type) { + unsigned entity_id; + switch (request->bmRequestType_bit.type) { case TUSB_REQ_TYPE_STANDARD: return handle_video_ctl_std_req(rhport, stage, request, itf); case TUSB_REQ_TYPE_CLASS: - if (!TU_U16_HIGH(request->wIndex)) { + entity_id = TU_U16_HIGH(request->wIndex); + if (!entity_id) { return handle_video_ctl_cs_req(rhport, stage, request, itf); } else { - /* TODO: */ + if (!_find_desc_entity(_get_desc_vc(&_videod_itf[itf]), entity_id)) + return VIDEO_INVALID_REQUEST; return VIDEO_INVALID_REQUEST; } default: @@ -549,16 +431,27 @@ static int handle_video_ctl_req(uint8_t rhport, uint8_t stage, tusb_control_requ static int handle_video_stm_std_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf) { - switch (p_request->bRequest) { + unsigned itfnum; + switch (request->bRequest) { case TUSB_REQ_GET_INTERFACE: - handle_video_ctl_std_req_get_itf(rhport, stage, request, itf); - case TUSB_REQ_SET_INTERFACE: - videod_interface_t *self = &_videod_itf[itf]; - unsigned itfnum = tu_u16_low(p_request->wIndex); if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; - if (_set_vs_itf(rhport, self, itfnum, request->wValue)) + TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN); + itfnum = tu_u16_low(request->wIndex); + tusb_desc_vs_itf_t const *vs = _get_desc_vs(&_videod_itf[itf], itfnum); + if (!vs) return VIDEO_UNKNOWN; + if (tud_control_xfer(rhport, request, + (void*)&vs->std.bAlternateSetting, + sizeof(vs->std.bAlternateSetting))) return VIDEO_NO_ERROR; return VIDEO_UNKNOWN; + case TUSB_REQ_SET_INTERFACE: + if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; + itfnum = tu_u16_low(request->wIndex); + if (!_close_vs_itf(rhport, &_videod_itf[itf], itfnum)) + return VIDEO_UNKNOWN; + if (!_open_vs_itf(rhport, &_videod_itf[itf], itfnum, request->wValue)) + return VIDEO_UNKNOWN; + return VIDEO_NO_ERROR; default: /* Unknown/Unsupported request */ TU_BREAKPOINT(); return VIDEO_INVALID_REQUEST; @@ -567,56 +460,52 @@ static int handle_video_stm_std_req(uint8_t rhport, uint8_t stage, tusb_control_ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf) { - videod_interface_t *self = &_videod_itf[i]; + // videod_interface_t *self = &_videod_itf[itf]; + (void)rhport; (void)stage; (void)itf; /* 4.2.1 Interface Control Request */ switch (TU_U16_HIGH(request->wValue)) { case VIDEO_VS_CTL_PROBE: - switch (p_request->bRequest) { + TU_LOG2(" Probe "); + switch (request->bRequest) { case VIDEO_REQUEST_SET_CUR: - if (stage == CONTROL_STAGE_SETUP) { - TU_LOG2(" Set Power Mode\r\n"); - TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN); - if (!tud_control_xfer(rhport, request, &self->power_mode, sizeof(self->power_mode))) - return VIDEO_UNKNOWN; - } else if (stage == CONTROL_STAGE_ACK) { - if (tud_video_power_mode_cb) return tud_video_power_mode_cb(itf, &self->power_mode); - } - return VIDEO_NO_ERROR; + TU_LOG2("Set\r\n"); + return VIDEO_UNKNOWN; case VIDEO_REQUEST_GET_CUR: - if (stage == CONTROL_STAGE_SETUP) { - TU_LOG2(" Get Power Mode\r\n"); - TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN); - if (!tud_control_xfer(rhport, request, &self->power_mode, sizeof(self->power_mode))) - return VIDEO_UNKNOWN; - } - return VIDEO_NO_ERROR; + TU_LOG2("Get\r\n"); + return VIDEO_UNKNOWN; + case VIDEO_REQUEST_GET_MIN: + TU_LOG2("Get Min\r\n"); + return VIDEO_UNKNOWN; + case VIDEO_REQUEST_GET_MAX: + TU_LOG2("Get Man\r\n"); + return VIDEO_UNKNOWN; + case VIDEO_REQUEST_GET_RES: + TU_LOG2("Get Res\r\n"); + return VIDEO_UNKNOWN; + case VIDEO_REQUEST_GET_DEF: + TU_LOG2("Get Def\r\n"); + return VIDEO_UNKNOWN; + case VIDEO_REQUEST_GET_LEN: + TU_LOG2("Get Len\r\n"); + return VIDEO_UNKNOWN; case VIDEO_REQUEST_GET_INFO: - if (stage == CONTROL_STAGE_SETUP) { - TU_LOG2(" Get Info Power Mode\r\n"); - TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN); - if (!tud_control_xfer(rhport, request, &_cap_get_set, sizeof(_cap_get_set))) - return VIDEO_UNKNOWN; - } - return VIDEO_NO_ERROR; + TU_LOG2("Get Info\r\n"); + return VIDEO_UNKNOWN; default: break; } break; case VIDEO_VS_CTL_COMMIT: - switch (p_request->bRequest) { + TU_LOG2(" Commit "); + switch (request->bRequest) { + case VIDEO_REQUEST_SET_CUR: + TU_LOG2("Set\r\n"); + return VIDEO_UNKNOWN; case VIDEO_REQUEST_GET_CUR: - if (stage == CONTROL_STAGE_SETUP) { - TU_LOG2(" Get Error Code\r\n"); - if (!tud_control_xfer(rhport, request, &self->error_code, sizeof(self->error_code))) - return VIDEO_UNKNOWN; - } - return VIDEO_NO_ERROR; + TU_LOG2("Get\r\n"); + return VIDEO_UNKNOWN; case VIDEO_REQUEST_GET_INFO: - if (stage == CONTROL_STAGE_SETUP) { - TU_LOG2(" Get Info Error Code\r\n"); - if (tud_control_xfer(rhport, request, &_cap_get, sizeof(_cap_get))) - return VIDEO_UNKNOWN; - } - return VIDEO_NO_ERROR; + TU_LOG2("Get Info\r\n"); + return VIDEO_UNKNOWN; default: break; } break; @@ -629,7 +518,7 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r static int handle_video_stm_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf) { - switch (p_request->bmRequestType_bit.type) { + switch (request->bmRequestType_bit.type) { case TUSB_REQ_TYPE_STANDARD: return handle_video_stm_std_req(rhport, stage, request, itf); case TUSB_REQ_TYPE_CLASS: @@ -642,40 +531,14 @@ static int handle_video_stm_req(uint8_t rhport, uint8_t stage, tusb_control_requ return VIDEO_UNKNOWN; } -static void _prep_out_transaction(cdcd_interface_t* p_cdc) -{ - uint8_t const rhport = TUD_OPT_RHPORT; - uint16_t available = tu_fifo_remaining(&p_cdc->rx_ff); - - // Prepare for incoming data but only allow what we can store in the ring buffer. - // TODO Actually we can still carry out the transfer, keeping count of received bytes - // and slowly move it to the FIFO when read(). - // This pre-check reduces endpoint claiming - TU_VERIFY(available >= sizeof(p_cdc->epout_buf), ); - - // claim endpoint - TU_VERIFY(usbd_edpt_claim(rhport, p_cdc->ep_out), ); - - // fifo can be changed before endpoint is claimed - available = tu_fifo_remaining(&p_cdc->rx_ff); - - if ( available >= sizeof(p_cdc->epout_buf) ) - { - usbd_edpt_xfer(rhport, p_cdc->ep_out, p_cdc->epout_buf, sizeof(p_cdc->epout_buf)); - }else - { - // Release endpoint since we don't make any transfer - usbd_edpt_release(rhport, p_cdc->ep_out); - } -} - //--------------------------------------------------------------------+ // APPLICATION API //--------------------------------------------------------------------+ bool tud_video_n_connected(uint8_t itf) { + (void)itf; // DTR (bit 0) active is considered as connected - return tud_ready() && tu_bit_test(_cdcd_itf[itf].line_state, 0); + return tud_ready(); } //--------------------------------------------------------------------+ @@ -695,7 +558,7 @@ void videod_init(void) for (unsigned i = 0; i < CFG_TUD_VIDEO; ++i) { - videod_interface_t* p_video = &_videod_itf[i]; + // videod_interface_t* p_video = &_videod_itf[i]; // TODO } @@ -716,14 +579,14 @@ void videod_reset(uint8_t rhport) uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len) { - TU_VERIFY(TUSB_CLASS_VIDEO == itf_desc->bInterfaceClass && - VIDEO_SUBCLASS_CONTROL == itf_desc->bInterfaceSubClass && - VIDEO_INT_PROTOCOL_CODE_15 == itf_desc->bFunctionProtool, 0); + TU_VERIFY((TUSB_CLASS_VIDEO == itf_desc->bInterfaceClass) && + (VIDEO_SUBCLASS_CONTROL == itf_desc->bInterfaceSubClass) && + (VIDEO_INT_PROTOCOL_CODE_15 == itf_desc->bInterfaceProtocol), 0); /* Find available interface */ videod_interface_t *self = NULL; for (unsigned i = 0; i < CFG_TUD_VIDEO; ++i) { - if (!_videod_itf[i].vc) { + if (!_videod_itf[i].beg) { self = &_videod_itf[i]; break; } @@ -758,24 +621,23 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request) { int err; - if (p_request->bmRequestType_bit.recipient != TUSB_REQ_RCPT_INTERFACE) { + if (request->bmRequestType_bit.recipient != TUSB_REQ_RCPT_INTERFACE) { return false; } - unsigned itfnum = tu_u16_low(p_request->wIndex); + unsigned itfnum = tu_u16_low(request->wIndex); /* Identify which interface to use */ int itf; tusb_desc_vc_itf_t const *vc = NULL; for (itf = 0; itf < CFG_TUD_VIDEO; ++itf) { - vc = _videod_itf[itf].vc; - if (!vc) continue; - unsigned beg_itfnum = vc->bInterfaceNumber; + vc = _get_desc_vc(&_videod_itf[itf]); + unsigned beg_itfnum = vc->std.bInterfaceNumber; unsigned end_itfnum = vc->ctl.bInCollection; if (beg_itfnum <= itfnum && itfnum < end_itfnum) break; } if (itf == CFG_TUD_VIDEO) return false; - if (itfnum == vc->bInterfaceNumber) { + if (itfnum == vc->std.bInterfaceNumber) { /* To video control interface */ err = handle_video_ctl_req(rhport, stage, request, itf); } else { @@ -789,68 +651,8 @@ bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_ bool videod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) { - (void) result; - - uint8_t itf; - videod_interface_t* p_video; - - // Identify which interface to use - for (itf = 0; itf < CFG_TUD_CDC; itf++) - { - p_video = &_videod_itf[itf]; - if ( ( ep_addr == p_video->ep_out ) || ( ep_addr == p_video->ep_in ) ) break; - } - TU_ASSERT(itf < CFG_TUD_CDC); - - // Received new data - if ( ep_addr == p_video->ep_out ) - { - tu_fifo_write_n(&p_video->rx_ff, &p_video->epout_buf, xferred_bytes); - - // Check for wanted char and invoke callback if needed - if ( tud_cdc_rx_wanted_cb && (((signed char) p_video->wanted_char) != -1) ) - { - for ( uint32_t i = 0; i < xferred_bytes; i++ ) - { - if ( (p_video->wanted_char == p_video->epout_buf[i]) && !tu_fifo_empty(&p_video->rx_ff) ) - { - tud_cdc_rx_wanted_cb(itf, p_video->wanted_char); - } - } - } - - // invoke receive callback (if there is still data) - if (tud_cdc_rx_cb && !tu_fifo_empty(&p_video->rx_ff) ) tud_cdc_rx_cb(itf); - - // prepare for OUT transaction - _prep_out_transaction(p_video); - } - - // Data sent to host, we continue to fetch from tx fifo to send. - // Note: This will cause incorrect baudrate set in line coding. - // Though maybe the baudrate is not really important !!! - if ( ep_addr == p_video->ep_in ) - { - // invoke transmit callback to possibly refill tx fifo - if ( tud_cdc_tx_complete_cb ) tud_cdc_tx_complete_cb(itf); - - if ( 0 == tud_cdc_n_write_flush(itf) ) - { - // If there is no data left, a ZLP should be sent if - // xferred_bytes is multiple of EP Packet size and not zero - if ( !tu_fifo_count(&p_video->tx_ff) && xferred_bytes && (0 == (xferred_bytes & (BULK_PACKET_SIZE-1))) ) - { - if ( usbd_edpt_claim(rhport, p_video->ep_in) ) - { - usbd_edpt_xfer(rhport, p_video->ep_in, NULL, 0); - } - } - } - } - - // nothing to do with notif endpoint for now - - return true; + (void)rhport; (void)ep_addr; (void)result; (void)xferred_bytes; + return false; } #endif diff --git a/src/class/video/video_device.h b/src/class/video/video_device.h index cd04b7391..95d352524 100644 --- a/src/class/video/video_device.h +++ b/src/class/video/video_device.h @@ -46,6 +46,8 @@ TU_ATTR_WEAK bool tud_video_set_cur_cb(uint8_t rhport, tusb_control_request_t co // Invoked when GET_CUR request received TU_ATTR_WEAK bool tud_video_get_cur_cb(uint8_t rhport, tusb_control_request_t const *request); +/* @return video_error_code_t */ +TU_ATTR_WEAK int tud_video_power_mode_cb(unsigned itf, uint8_t power_mod); //--------------------------------------------------------------------+ // INTERNAL USBD-CLASS DRIVER API //--------------------------------------------------------------------+ -- cgit v1.3.1 From d026f174576b0567e2a954292bd4339349e3f139 Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Sun, 1 Aug 2021 17:11:43 +0900 Subject: fix: configuration descriptor has incorrectly sizes update some descriptors --- .../device/video_capture/src/usb_descriptors.c | 2 +- .../device/video_capture/src/usb_descriptors.h | 59 ++++++++++++-------- src/class/video/video.h | 63 +++++++++++++++++----- src/class/video/video_device.c | 23 ++++---- 4 files changed, 102 insertions(+), 45 deletions(-) diff --git a/examples/device/video_capture/src/usb_descriptors.c b/examples/device/video_capture/src/usb_descriptors.c index df8c41721..067c1d946 100644 --- a/examples/device/video_capture/src/usb_descriptors.c +++ b/examples/device/video_capture/src/usb_descriptors.c @@ -102,7 +102,7 @@ uint8_t const * tud_descriptor_device_cb(void) uint8_t const desc_fs_configuration[] = { // Config number, interface count, string index, total length, attribute, power in mA - TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100), + TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0, 500), // IAD for Video Control TUD_VIDEO_CAPTURE_DESCRIPTOR(4, EPNUM_VIDEO_IN, 128, 96, 15) }; diff --git a/examples/device/video_capture/src/usb_descriptors.h b/examples/device/video_capture/src/usb_descriptors.h index 6c6c14d35..d37ab1338 100644 --- a/examples/device/video_capture/src/usb_descriptors.h +++ b/examples/device/video_capture/src/usb_descriptors.h @@ -39,18 +39,27 @@ enum { ITF_NUM_TOTAL }; -#define TUD_VIDEO_CAPTURE_DESC_LEN (TUD_VIDEO_DESC_IAD_LEN\ +#define TUD_VIDEO_CAPTURE_DESC_LEN (\ + TUD_VIDEO_DESC_IAD_LEN\ /* control */\ + TUD_VIDEO_DESC_STD_VC_LEN\ - + TUD_VIDEO_DESC_CS_VC_LEN\ + + (TUD_VIDEO_DESC_CS_VC_LEN + 1/*bInCollection*/)\ + TUD_VIDEO_DESC_INPUT_TERM_LEN\ + TUD_VIDEO_DESC_OUTPUT_TERM_LEN\ /* Interface 1, Alternate 0 */\ + TUD_VIDEO_DESC_STD_VS_LEN\ - + TUD_VIDEO_DESC_CS_VS_IN_LEN\ + + (TUD_VIDEO_DESC_CS_VS_IN_LEN + 1/*bNumFormats x bControlSize*/)\ + TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN\ - + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN) + + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN\ + + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN\ + ) +#if 0 + /* Interface 1, Alternate 1 */\ + + TUD_VIDEO_DESC_STD_VS_LEN\ + + 7/* Endpoint */\ + +#endif #define TUD_VIDEO_DESC_CS_VS_FMT_YUY2(_fmtidx, _numfmtdesc, _frmidx, _asrx, _asry, _interlace, _cp) \ TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR(_fmtidx, _numfmtdesc, TUD_VIDEO_GUID_YUY2, 16, _frmidx, _asrx, _asry, _interlace, _cp) @@ -64,34 +73,40 @@ enum { #define TUD_VIDEO_CAPTURE_DESCRIPTOR(_stridx, _epin, _width, _height, _fps) \ TUD_VIDEO_DESC_IAD(ITF_NUM_VIDEO_CONTROL, ITF_NUM_TOTAL, _stridx), \ /* Video control 0 */ \ - TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, 0), \ + TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx), \ TUD_VIDEO_DESC_CS_VC( /* UVC 1.5*/ 0x0150, \ - TUD_VIDEO_DESC_INPUT_TERM_LEN + \ - TUD_VIDEO_DESC_OUTPUT_TERM_LEN, \ + /* wTotalLength - bLength */ \ + TUD_VIDEO_DESC_INPUT_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, \ UVC_CLOCK_FREQUENCY, 1, 1), \ TUD_VIDEO_DESC_INPUT_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL,\ VIDEO_TT_COMPOSITE_CONNECTOR, 0, 0), \ TUD_VIDEO_DESC_OUTPUT_TERM(UVC_ENTITY_CAP_OUTPUT_TERMINAL,\ - VIDEO_TT_STREAMING, 0, 1, 0), \ + VIDEO_TT_STREAMING, 0, 1, 0), \ /* Video stream alt. 0 */ \ TUD_VIDEO_DESC_STD_VS( 1, 0, 0, 0), \ /* Video stream header for without still image capture */ \ - TUD_VIDEO_DESC_CS_VS_INPUT(1, \ - TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN + \ - TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN,\ - _epin, /*bmInfo*/ 0, UVC_ENTITY_CAP_OUTPUT_TERMINAL, \ - 0, 2, 0, 0, 0, 1, 0), \ + TUD_VIDEO_DESC_CS_VS_INPUT( /*bNumFormats*/1, \ + /*wTotalLength - bLength */\ + TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN\ + + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN\ + + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\ + _epin, /*bmInfo*/0, /*bTerminalLink*/UVC_ENTITY_CAP_OUTPUT_TERMINAL, \ + /*bStillCaptureMethod*/0, /*bTriggerSupport*/0, /*bTriggerUsage*/0, \ + /*bControlSize*/1, /*bmaControls(1)*/0), \ /* Video stream format */ \ - TUD_VIDEO_DESC_CS_VS_FMT_I420(0, 1, 0, 1, 1, 0, 0), \ + TUD_VIDEO_DESC_CS_VS_FMT_I420(/*bFormatIndex*/1, /*bNumFrameDescriptors*/1,\ + /*bDefaultFrameIndex*/1, 1, 1, 0, /*bCopyProtect*/0), \ /* Video stream frame format */ \ - TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT( 1, 0, _width, _height, \ - _width * _height * 12, _width * _height * 12 * _fps, \ - _width * _height * 12, \ - (10000000/_fps), (10000000/1), (10000000/_fps), 166666), \ - /* VS alt 1 */ \ - TUD_VIDEO_DESC_STD_VS( 1, 1, 1, 0), \ - /* EP */ \ - TUD_VIDEO_DESC_EP_ISO(_epin, (_width * _height * 12 / 8) * _fps, 1) + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT(/*bFrameIndex */1, 0, _width, _height, \ + _width * _height * 12, _width * _height * 12 * _fps, \ + _width * _height * 12, \ + (10000000/_fps), (10000000/1), (10000000/_fps), 166666), \ + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING(VIDEO_COLOR_PRIMARIES_BT709,\ + VIDEO_COLOR_XFER_CH_BT709, VIDEO_COLOR_COEF_SMPTE170M), \ + /* VS alt 1 */\ + TUD_VIDEO_DESC_STD_VS(1, 1, 1, 0), \ + /* EP */ \ + TUD_VIDEO_DESC_EP_ISO(_epin, (_width * _height * 12 / 8) * _fps, 1) #endif diff --git a/src/class/video/video.h b/src/class/video/video.h index 489af8da2..597ad7d39 100644 --- a/src/class/video/video.h +++ b/src/class/video/video.h @@ -29,6 +29,35 @@ #include "common/tusb_common.h" +typedef enum { + VIDEO_COLOR_PRIMARIES_UNDEFINED = 0x00, + VIDEO_COLOR_PRIMARIES_BT709, + VIDEO_COLOR_PRIMARIES_BT470_2M, + VIDEO_COLOR_PRIMARIES_BT470_2BG, + VIDEO_COLOR_PRIMARIES_SMPTE170M, + VIDEO_COLOR_PRIMARIES_SMPTE240M, +} video_color_primaries_t; + +typedef enum { + VIDEO_COLOR_XFER_CH_UNDEFINED = 0x00, + VIDEO_COLOR_XFER_CH_BT709, + VIDEO_COLOR_XFER_CH_BT470_2M, + VIDEO_COLOR_XFER_CH_BT470_2BG, + VIDEO_COLOR_XFER_CH_SMPTE170M, + VIDEO_COLOR_XFER_CH_SMPTE240M, + VIDEO_COLOR_XFER_CH_LINEAR, + VIDEO_COLOR_XFER_CH_SRGB, +} video_color_transfer_characteristics_t; + +typedef enum { + VIDEO_COLOR_COEF_UNDEFINED = 0x00, + VIDEO_COLOR_COEF_BT709, + VIDEO_COLOR_COEF_FCC, + VIDEO_COLOR_COEF_BT470_2BG, + VIDEO_COLOR_COEF_SMPTE170M, + VIDEO_COLOR_COEF_SMPTE240M, +} video_color_matrix_coefficients_t; + /* 4.2.1.2 */ typedef enum { VIDEO_NO_ERROR = 0, /* The request succeeded. */ @@ -69,7 +98,7 @@ typedef enum VIDEO_CS_VC_INTERFACE_PROCESSING_UNIT, VIDEO_CS_VC_INTERFACE_EXTENSION_UNIT, VIDEO_CS_VC_INTERFACE_ENCODING_UNIT, -} vide_cs_vc_interface_subtype_t; +} video_cs_vc_interface_subtype_t; /* A.6 */ typedef enum @@ -278,6 +307,7 @@ typedef struct TU_ATTR_PACKED { #define TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN 27 #define TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN 38 #define TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_DISC_LEN 26 +#define TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN 6 /* 2.2 compression formats */ #define TUD_VIDEO_GUID_YUY2 0x59,0x55,0x59,0x32,0x00,0x00,0x10,0x00,0x00,0x80,0x71,0x9B,0x38,0x00,0xAA,0x00 @@ -296,8 +326,8 @@ typedef struct TU_ATTR_PACKED { /* 3.7.2 */ #define TUD_VIDEO_DESC_CS_VC(_bcdUVC, _totallen, _clkfreq, _coll, ...) \ - TUD_VIDEO_DESC_CS_VC_LEN + _coll, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VC_INTERFACE_HEADER, \ - U16_TO_U8S_LE(_bcdUVC), U16_TO_U8S_LE(_totallen + TUD_VIDEO_DESC_CS_VC_LEN), \ + TUD_VIDEO_DESC_CS_VC_LEN + (_coll), TUSB_DESC_CS_INTERFACE, VIDEO_CS_VC_INTERFACE_HEADER, \ + U16_TO_U8S_LE(_bcdUVC), U16_TO_U8S_LE((_totallen) + TUD_VIDEO_DESC_CS_VC_LEN + (_coll)), \ U32_TO_U8S_LE(_clkfreq), _coll, __VA_ARGS__ /* 3.7.2.1 */ @@ -307,30 +337,31 @@ typedef struct TU_ATTR_PACKED { /* 3.7.2.2 */ #define TUD_VIDEO_DESC_OUTPUT_TERM(_tid, _tt, _at, _srcid, _stridx) \ - TUD_VIDEO_DESC_INPUT_TERM_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VC_INTERFACE_OUTPUT_TERMINAL, \ - _tid, U16_TO_U8S_LE(_tt), _at, _stridx + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VC_INTERFACE_OUTPUT_TERMINAL, \ + _tid, U16_TO_U8S_LE(_tt), _at, _srcid, _stridx /* 3.9.1 */ -#define TUD_VIDEO_DESC_STD_VS(_itfnum, _alt, _epn, _stridx) \ - TUD_VIDEO_DESC_STD_VC_LEN, TUSB_DESC_INTERFACE, _itfnum, _alt, \ +#define TUD_VIDEO_DESC_STD_VS(_itfnum, _alt, _epn, _stridx) \ + TUD_VIDEO_DESC_STD_VS_LEN, TUSB_DESC_INTERFACE, _itfnum, _alt, \ _epn, TUSB_CLASS_VIDEO, VIDEO_SUBCLASS_STREAMING, VIDEO_INT_PROTOCOL_CODE_15, _stridx /* 3.9.2.1 */ -#define TUD_VIDEO_DESC_CS_VS_INPUT(_numfmt, _totlen, _epn, _inf, _termlnk, _sticaptmeth, _trgspt, _trgusg, _ctlsz, ...) \ +#define TUD_VIDEO_DESC_CS_VS_INPUT(_numfmt, _totallen, _ep, _inf, _termlnk, _sticaptmeth, _trgspt, _trgusg, _ctlsz, ...) \ TUD_VIDEO_DESC_CS_VS_IN_LEN + (_numfmt) * (_ctlsz), TUSB_DESC_CS_INTERFACE, \ VIDEO_CS_VS_INTERFACE_INPUT_HEADER, _numfmt, \ - U16_TO_U8S_LE(_totlen + TUD_VIDEO_DESC_CS_VS_IN_LEN + (_numfmt) * (_ctlsz)), \ - _epn, _inf, _termlnk, _sticaptmeth, _trgspt, _trgusg, _ctlsz, __VA_ARGS__ + U16_TO_U8S_LE((_totallen) + TUD_VIDEO_DESC_CS_VS_IN_LEN + (_numfmt) * (_ctlsz)), \ + _ep, _inf, _termlnk, _sticaptmeth, _trgspt, _trgusg, _ctlsz, __VA_ARGS__ /* 3.9.2.2 */ -#define TUD_VIDEO_DESC_CS_VS_OUTPUT(_numfmt, _totlen, _epn, _inf, _termlnk, _ctlsz, ...) \ +#define TUD_VIDEO_DESC_CS_VS_OUTPUT(_numfmt, _totallen, _ep, _inf, _termlnk, _ctlsz, ...) \ TUD_VIDEO_DESC_CS_VS_OUT_LEN + (_numfmt) * (_ctlsz), TUSB_DESC_CS_INTERFACE, \ VIDEO_CS_VS_INTERFACE_OUTPUT_HEADER, _numfmt, \ - U16_TO_U8S_LE(_totlen + TUD_VIDEO_DESC_CS_VS_OUT_LEN + (_numfmt) * (_ctlsz)), \ - _epn, _inf, _termlnk, _trgusg, _ctlsz, __VA_ARGS__ + U16_TO_U8S_LE((_totallen) + TUD_VIDEO_DESC_CS_VS_OUT_LEN + (_numfmt) * (_ctlsz)), \ + _ep, _inf, _termlnk, _ctlsz, __VA_ARGS__ /* Uncompressed 3.1.1 */ #define TUD_VIDEO_GUID(_g0,_g1,_g2,_g3,_g4,_g5,_g6,_g7,_g8,_g9,_g10,_g11,_g12,_g13,_g14,_g15) _g0,_g1,_g2,_g3,_g4,_g5,_g6,_g7,_g8,_g9,_g10,_g11,_g12,_g13,_g14,_g15 + #define TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR(_fmtidx, _numfrmdesc, \ _guid, _bitsperpix, _frmidx, _asrx, _asry, _interlace, _cp) \ TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_INTERFACE_FORMAT_UNCOMPRESSED, \ @@ -353,6 +384,12 @@ typedef struct TU_ATTR_PACKED { _frmidx, _cap, U16_TO_U8S_LE(_width), U16_TO_U8S_LE(_height), U32_TO_U8S_LE(_minbr), U32_TO_U8S_LE(_maxbr), \ U32_TO_U8S_LE(_maxfrmbufsz), U32_TO_U8S_LE(_frminterval), _numfrminterval, __VA_ARGS__ +/* 3.9.2.6 */ +#define TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING(_color, _trns, _mat) \ + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN, \ + TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_INTERFACE_COLORFORMAT, \ + _color, _trns, _mat + /* 3.10.1.1 */ #define TUD_VIDEO_DESC_EP_ISO(_ep, _epsize, _ep_interval) \ 7, TUSB_DESC_ENDPOINT, _ep, TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS,\ diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index badd838a1..94ae325dc 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -183,7 +183,7 @@ static void const* _find_desc_itf(void const *beg, void const *end, unsigned itf static void const* _find_desc_entity(tusb_desc_vc_itf_t const *vc, unsigned entityid) { void const *beg = (void const*)vc; - void const *end = beg + vc->std.bLength + vc->ctl.bLength + vc->ctl.wTotalLength; + void const *end = beg + vc->std.bLength + vc->ctl.wTotalLength; for (void const *cur = beg; cur < end; cur = _find_desc(cur, end, TUSB_DESC_CS_INTERFACE)) { tusb_desc_cs_video_entity_itf_t const *itf = (tusb_desc_cs_video_entity_itf_t const *)cur; if ((VIDEO_CS_VC_INTERFACE_INPUT_TERMINAL == itf->bDescriptorSubtype || @@ -206,7 +206,7 @@ static bool _close_vc_itf(uint8_t rhport, videod_interface_t *self) /* The next descriptor after the class-specific VC interface header descriptor. */ void const *cur = (void const*)vc + vc->std.bLength + vc->ctl.bLength; /* The end of the video control interface descriptor. */ - void const *end = cur + vc->ctl.wTotalLength; + void const *end = (void const*)vc + vc->std.bLength + vc->ctl.wTotalLength; if (vc->std.bNumEndpoints) { /* Find the notification endpoint descriptor. */ cur = _find_desc(cur, end, TUSB_DESC_ENDPOINT); @@ -224,21 +224,25 @@ static bool _close_vc_itf(uint8_t rhport, videod_interface_t *self) * @param[in] altnum The target alternate setting number. */ static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, unsigned altnum) { + TU_LOG2(" open VC %d\r\n", altnum); void const *beg = self->beg; void const *end = beg + self->len; /* The first descriptor is a video control interface descriptor. */ unsigned itfnum = ((tusb_desc_interface_t const *)beg)->bInterfaceNumber; void const *cur = _find_desc_itf(beg, end, itfnum, altnum); + TU_LOG2(" cur %ld\r\n", cur - beg); TU_VERIFY(cur < end); tusb_desc_vc_itf_t const *vc = (tusb_desc_vc_itf_t const *)cur; + TU_LOG2(" bInCollection %d\r\n", vc->ctl.bInCollection); /* Support for up to 2 streaming interfaces only. */ TU_ASSERT(vc->ctl.bInCollection < 3); + /* Update to point the end of the video control interface descriptor. */ + end = cur + vc->std.bLength + vc->ctl.wTotalLength; /* Advance to the next descriptor after the class-specific VC interface header descriptor. */ cur += vc->std.bLength + vc->ctl.bLength; - /* Update to point the end of the video control interface descriptor. */ - end = cur + vc->ctl.wTotalLength; + TU_LOG2(" bNumEndpoints %d\r\n", vc->std.bNumEndpoints); /* Open the notification endpoint if it exist. */ if (vc->std.bNumEndpoints) { /* Support for 1 endpoint only. */ @@ -266,7 +270,7 @@ static bool _close_vs_itf(uint8_t rhport, videod_interface_t *self, unsigned itf /* The next of the video streaming interface header descriptor. */ void const *cur = (void const*)vs + vs->std.bLength + vs->stm.bLength; /* The end of the video streaming interface descriptor. */ - void const *end = cur + vs->stm.wTotalLength; + void const *end = (void const*)vs + vs->std.bLength + vs->stm.wTotalLength; for (unsigned i = 0; i < vs->std.bNumEndpoints; ++i) { cur = _find_desc(cur, end, TUSB_DESC_ENDPOINT); TU_ASSERT(cur < end); @@ -285,6 +289,7 @@ static bool _close_vs_itf(uint8_t rhport, videod_interface_t *self, unsigned itf * @param[in] altnum The target alternate setting number. */ static bool _open_vs_itf(uint8_t rhport, videod_interface_t *self, unsigned itfnum, unsigned altnum) { + TU_LOG2(" open VS %d,%d\r\n", itfnum, altnum); uint16_t *ofs = NULL; for (unsigned i = 1; i < sizeof(self->ofs)/sizeof(self->ofs[0]); ++i) { if (!self->ofs[i]) { @@ -297,17 +302,17 @@ static bool _open_vs_itf(uint8_t rhport, videod_interface_t *self, unsigned itfn tusb_desc_vc_itf_t const *vc = _get_desc_vc(self); void const *end = self->beg + self->len; /* Set the end of the video control interface descriptor. */ - void const *cur = (void const*)vc + vc->std.bLength + vc->ctl.bLength + vc->ctl.wTotalLength; + void const *cur = (void const*)vc + vc->std.bLength + vc->ctl.wTotalLength; cur = _find_desc_itf(cur, end, itfnum, altnum); TU_VERIFY(cur < end); tusb_desc_vs_itf_t const *vs = (tusb_desc_vs_itf_t const*)cur; /* Support for up to 2 endpoint only. */ TU_ASSERT(vs->std.bNumEndpoints < 3); + /* Update to point the end of the video control interface descriptor. */ + end = cur + vs->std.bLength + vs->stm.wTotalLength; /* Advance to the next descriptor after the class-specific VS interface header descriptor. */ cur += vs->std.bLength + vs->stm.bLength; - /* Update to point the end of the video control interface descriptor. */ - end = cur + vs->stm.wTotalLength; for (unsigned i = 0; i < vs->std.bNumEndpoints; ++i) { cur = _find_desc(cur, end, TUSB_DESC_ENDPOINT); TU_VERIFY(cur < end); @@ -612,7 +617,7 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin itfnum = vc->ctl.baInterfaceNr[i]; if (!_open_vs_itf(rhport, self, itfnum, 0)) return 0; } - return end - cur; + return (uintptr_t)cur - (uintptr_t)itf_desc; } // Invoked when a control transfer occurred on an interface of this class -- cgit v1.3.1 From c52cf9c8a5c3cbc7ebe0c4409e0b6df1ea138b30 Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Sun, 1 Aug 2021 17:51:15 +0900 Subject: fix: endpoint descriptor has incorrectly settings --- examples/device/video_capture/src/usb_descriptors.c | 2 +- examples/device/video_capture/src/usb_descriptors.h | 18 +++++------------- 2 files changed, 6 insertions(+), 14 deletions(-) diff --git a/examples/device/video_capture/src/usb_descriptors.c b/examples/device/video_capture/src/usb_descriptors.c index 067c1d946..d3544cc63 100644 --- a/examples/device/video_capture/src/usb_descriptors.c +++ b/examples/device/video_capture/src/usb_descriptors.c @@ -104,7 +104,7 @@ uint8_t const desc_fs_configuration[] = // Config number, interface count, string index, total length, attribute, power in mA TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0, 500), // IAD for Video Control - TUD_VIDEO_CAPTURE_DESCRIPTOR(4, EPNUM_VIDEO_IN, 128, 96, 15) + TUD_VIDEO_CAPTURE_DESCRIPTOR(4, EPNUM_VIDEO_IN, 128, 96, 15, 256) }; // Invoked when received GET CONFIGURATION DESCRIPTOR diff --git a/examples/device/video_capture/src/usb_descriptors.h b/examples/device/video_capture/src/usb_descriptors.h index d37ab1338..246125217 100644 --- a/examples/device/video_capture/src/usb_descriptors.h +++ b/examples/device/video_capture/src/usb_descriptors.h @@ -51,15 +51,10 @@ enum { + (TUD_VIDEO_DESC_CS_VS_IN_LEN + 1/*bNumFormats x bControlSize*/)\ + TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN\ + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN\ - + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN\ - ) - -#if 0 /* Interface 1, Alternate 1 */\ + TUD_VIDEO_DESC_STD_VS_LEN\ + 7/* Endpoint */\ - -#endif + ) #define TUD_VIDEO_DESC_CS_VS_FMT_YUY2(_fmtidx, _numfmtdesc, _frmidx, _asrx, _asry, _interlace, _cp) \ TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR(_fmtidx, _numfmtdesc, TUD_VIDEO_GUID_YUY2, 16, _frmidx, _asrx, _asry, _interlace, _cp) @@ -70,7 +65,7 @@ enum { #define TUD_VIDEO_DESC_CS_VS_FMT_I420(_fmtidx, _numfmtdesc, _frmidx, _asrx, _asry, _interlace, _cp) \ TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR(_fmtidx, _numfmtdesc, TUD_VIDEO_GUID_I420, 12, _frmidx, _asrx, _asry, _interlace, _cp) -#define TUD_VIDEO_CAPTURE_DESCRIPTOR(_stridx, _epin, _width, _height, _fps) \ +#define TUD_VIDEO_CAPTURE_DESCRIPTOR(_stridx, _epin, _width, _height, _fps, _epsize) \ TUD_VIDEO_DESC_IAD(ITF_NUM_VIDEO_CONTROL, ITF_NUM_TOTAL, _stridx), \ /* Video control 0 */ \ TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx), \ @@ -88,25 +83,22 @@ enum { TUD_VIDEO_DESC_CS_VS_INPUT( /*bNumFormats*/1, \ /*wTotalLength - bLength */\ TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN\ - + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN\ - + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\ + + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN, \ _epin, /*bmInfo*/0, /*bTerminalLink*/UVC_ENTITY_CAP_OUTPUT_TERMINAL, \ /*bStillCaptureMethod*/0, /*bTriggerSupport*/0, /*bTriggerUsage*/0, \ /*bControlSize*/1, /*bmaControls(1)*/0), \ /* Video stream format */ \ TUD_VIDEO_DESC_CS_VS_FMT_I420(/*bFormatIndex*/1, /*bNumFrameDescriptors*/1,\ - /*bDefaultFrameIndex*/1, 1, 1, 0, /*bCopyProtect*/0), \ + /*bDefaultFrameIndex*/1, 0, 0, 0, /*bCopyProtect*/0), \ /* Video stream frame format */ \ TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT(/*bFrameIndex */1, 0, _width, _height, \ _width * _height * 12, _width * _height * 12 * _fps, \ _width * _height * 12, \ (10000000/_fps), (10000000/1), (10000000/_fps), 166666), \ - TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING(VIDEO_COLOR_PRIMARIES_BT709,\ - VIDEO_COLOR_XFER_CH_BT709, VIDEO_COLOR_COEF_SMPTE170M), \ /* VS alt 1 */\ TUD_VIDEO_DESC_STD_VS(1, 1, 1, 0), \ /* EP */ \ - TUD_VIDEO_DESC_EP_ISO(_epin, (_width * _height * 12 / 8) * _fps, 1) + TUD_VIDEO_DESC_EP_ISO(_epin, _epsize, 1) #endif -- cgit v1.3.1 From 20572a6ed22ef54a511b731dc6044928d9ad5993 Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Wed, 4 Aug 2021 00:32:16 +0900 Subject: Fix regarding standard video stream request --- .../device/video_capture/src/usb_descriptors.h | 5 ++++- src/class/video/video_device.c | 23 ++++++++++++---------- 2 files changed, 17 insertions(+), 11 deletions(-) diff --git a/examples/device/video_capture/src/usb_descriptors.h b/examples/device/video_capture/src/usb_descriptors.h index 246125217..396131f83 100644 --- a/examples/device/video_capture/src/usb_descriptors.h +++ b/examples/device/video_capture/src/usb_descriptors.h @@ -56,6 +56,9 @@ enum { + 7/* Endpoint */\ ) +/* Windows support YUV2 and NV12 + * https://docs.microsoft.com/en-us/windows-hardware/drivers/stream/usb-video-class-driver-overview */ + #define TUD_VIDEO_DESC_CS_VS_FMT_YUY2(_fmtidx, _numfmtdesc, _frmidx, _asrx, _asry, _interlace, _cp) \ TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR(_fmtidx, _numfmtdesc, TUD_VIDEO_GUID_YUY2, 16, _frmidx, _asrx, _asry, _interlace, _cp) #define TUD_VIDEO_DESC_CS_VS_FMT_NV12(_fmtidx, _numfmtdesc, _frmidx, _asrx, _asry, _interlace, _cp) \ @@ -88,7 +91,7 @@ enum { /*bStillCaptureMethod*/0, /*bTriggerSupport*/0, /*bTriggerUsage*/0, \ /*bControlSize*/1, /*bmaControls(1)*/0), \ /* Video stream format */ \ - TUD_VIDEO_DESC_CS_VS_FMT_I420(/*bFormatIndex*/1, /*bNumFrameDescriptors*/1,\ + TUD_VIDEO_DESC_CS_VS_FMT_NV12(/*bFormatIndex*/1, /*bNumFrameDescriptors*/1,\ /*bDefaultFrameIndex*/1, 0, 0, 0, /*bCopyProtect*/0), \ /* Video stream frame format */ \ TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT(/*bFrameIndex */1, 0, _width, _height, \ diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index 94ae325dc..bee80d6e8 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -321,6 +321,7 @@ static bool _open_vs_itf(uint8_t rhport, videod_interface_t *self, unsigned itfn cur += tu_desc_len(cur); } *ofs = (void const*)vs - self->beg; + TU_LOG2(" done\r\n"); return true; } @@ -626,6 +627,7 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request) { int err; + int (*handle_video_req)(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf) = NULL; if (request->bmRequestType_bit.recipient != TUSB_REQ_RCPT_INTERFACE) { return false; } @@ -635,20 +637,21 @@ bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_ tusb_desc_vc_itf_t const *vc = NULL; for (itf = 0; itf < CFG_TUD_VIDEO; ++itf) { vc = _get_desc_vc(&_videod_itf[itf]); - unsigned beg_itfnum = vc->std.bInterfaceNumber; - unsigned end_itfnum = vc->ctl.bInCollection; - if (beg_itfnum <= itfnum && itfnum < end_itfnum) + if (itfnum == vc->std.bInterfaceNumber) { + handle_video_req = handle_video_ctl_req; break; + } + int i; + int bInCollection = vc->ctl.bInCollection; + for (i = 0; i < bInCollection && itfnum != vc->ctl.baInterfaceNr[i]; ++i) ; + if (i < bInCollection) { + handle_video_req = handle_video_stm_req; + break; + } } if (itf == CFG_TUD_VIDEO) return false; - if (itfnum == vc->std.bInterfaceNumber) { - /* To video control interface */ - err = handle_video_ctl_req(rhport, stage, request, itf); - } else { - /* To video streaming interface */ - err = handle_video_stm_req(rhport, stage, request, itf); - } + err = handle_video_req(rhport, stage, request, itf); _videod_itf[itf].error_code = (uint8_t)err; if (err) return false; return true; -- cgit v1.3.1 From 4995d9cbd2022b703edf4ca4bdef8ee43724fd99 Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Mon, 9 Aug 2021 17:11:05 +0900 Subject: Fix handling for set_interface --- .../device/video_capture/src/usb_descriptors.h | 11 +++++--- src/class/video/video.h | 30 +++++++++++----------- src/class/video/video_device.c | 9 ++----- 3 files changed, 24 insertions(+), 26 deletions(-) diff --git a/examples/device/video_capture/src/usb_descriptors.h b/examples/device/video_capture/src/usb_descriptors.h index 396131f83..e7b47b66a 100644 --- a/examples/device/video_capture/src/usb_descriptors.h +++ b/examples/device/video_capture/src/usb_descriptors.h @@ -51,6 +51,7 @@ enum { + (TUD_VIDEO_DESC_CS_VS_IN_LEN + 1/*bNumFormats x bControlSize*/)\ + TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN\ + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN\ + + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN\ /* Interface 1, Alternate 1 */\ + TUD_VIDEO_DESC_STD_VS_LEN\ + 7/* Endpoint */\ @@ -75,7 +76,7 @@ enum { TUD_VIDEO_DESC_CS_VC( /* UVC 1.5*/ 0x0150, \ /* wTotalLength - bLength */ \ TUD_VIDEO_DESC_INPUT_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, \ - UVC_CLOCK_FREQUENCY, 1, 1), \ + UVC_CLOCK_FREQUENCY, 1), \ TUD_VIDEO_DESC_INPUT_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL,\ VIDEO_TT_COMPOSITE_CONNECTOR, 0, 0), \ TUD_VIDEO_DESC_OUTPUT_TERM(UVC_ENTITY_CAP_OUTPUT_TERMINAL,\ @@ -86,10 +87,11 @@ enum { TUD_VIDEO_DESC_CS_VS_INPUT( /*bNumFormats*/1, \ /*wTotalLength - bLength */\ TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN\ - + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN, \ + + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN\ + + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\ _epin, /*bmInfo*/0, /*bTerminalLink*/UVC_ENTITY_CAP_OUTPUT_TERMINAL, \ /*bStillCaptureMethod*/0, /*bTriggerSupport*/0, /*bTriggerUsage*/0, \ - /*bControlSize*/1, /*bmaControls(1)*/0), \ + /*bmaControls(1)*/0), \ /* Video stream format */ \ TUD_VIDEO_DESC_CS_VS_FMT_NV12(/*bFormatIndex*/1, /*bNumFrameDescriptors*/1,\ /*bDefaultFrameIndex*/1, 0, 0, 0, /*bCopyProtect*/0), \ @@ -97,7 +99,8 @@ enum { TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT(/*bFrameIndex */1, 0, _width, _height, \ _width * _height * 12, _width * _height * 12 * _fps, \ _width * _height * 12, \ - (10000000/_fps), (10000000/1), (10000000/_fps), 166666), \ + (10000000/_fps), (10000000/_fps), (10000000/_fps)*_fps, (10000000/_fps)), \ + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING(VIDEO_COLOR_PRIMARIES_BT709, VIDEO_COLOR_XFER_CH_BT709, VIDEO_COLOR_COEF_SMPTE170M), \ /* VS alt 1 */\ TUD_VIDEO_DESC_STD_VS(1, 1, 1, 0), \ /* EP */ \ diff --git a/src/class/video/video.h b/src/class/video/video.h index 597ad7d39..773c87845 100644 --- a/src/class/video/video.h +++ b/src/class/video/video.h @@ -325,10 +325,10 @@ typedef struct TU_ATTR_PACKED { _nEPs, TUSB_CLASS_VIDEO, VIDEO_SUBCLASS_CONTROL, VIDEO_INT_PROTOCOL_CODE_15, _stridx /* 3.7.2 */ -#define TUD_VIDEO_DESC_CS_VC(_bcdUVC, _totallen, _clkfreq, _coll, ...) \ - TUD_VIDEO_DESC_CS_VC_LEN + (_coll), TUSB_DESC_CS_INTERFACE, VIDEO_CS_VC_INTERFACE_HEADER, \ - U16_TO_U8S_LE(_bcdUVC), U16_TO_U8S_LE((_totallen) + TUD_VIDEO_DESC_CS_VC_LEN + (_coll)), \ - U32_TO_U8S_LE(_clkfreq), _coll, __VA_ARGS__ +#define TUD_VIDEO_DESC_CS_VC(_bcdUVC, _totallen, _clkfreq, ...) \ + TUD_VIDEO_DESC_CS_VC_LEN + (TU_ARGS_NUM(__VA_ARGS__)), TUSB_DESC_CS_INTERFACE, VIDEO_CS_VC_INTERFACE_HEADER, \ + U16_TO_U8S_LE(_bcdUVC), U16_TO_U8S_LE((_totallen) + TUD_VIDEO_DESC_CS_VC_LEN + (TU_ARGS_NUM(__VA_ARGS__))), \ + U32_TO_U8S_LE(_clkfreq), TU_ARGS_NUM(__VA_ARGS__), __VA_ARGS__ /* 3.7.2.1 */ #define TUD_VIDEO_DESC_INPUT_TERM(_tid, _tt, _at, _stridx) \ @@ -346,18 +346,18 @@ typedef struct TU_ATTR_PACKED { _epn, TUSB_CLASS_VIDEO, VIDEO_SUBCLASS_STREAMING, VIDEO_INT_PROTOCOL_CODE_15, _stridx /* 3.9.2.1 */ -#define TUD_VIDEO_DESC_CS_VS_INPUT(_numfmt, _totallen, _ep, _inf, _termlnk, _sticaptmeth, _trgspt, _trgusg, _ctlsz, ...) \ - TUD_VIDEO_DESC_CS_VS_IN_LEN + (_numfmt) * (_ctlsz), TUSB_DESC_CS_INTERFACE, \ +#define TUD_VIDEO_DESC_CS_VS_INPUT(_numfmt, _totallen, _ep, _inf, _termlnk, _sticaptmeth, _trgspt, _trgusg, ...) \ + TUD_VIDEO_DESC_CS_VS_IN_LEN + (_numfmt) * (TU_ARGS_NUM(__VA_ARGS__)), TUSB_DESC_CS_INTERFACE, \ VIDEO_CS_VS_INTERFACE_INPUT_HEADER, _numfmt, \ - U16_TO_U8S_LE((_totallen) + TUD_VIDEO_DESC_CS_VS_IN_LEN + (_numfmt) * (_ctlsz)), \ - _ep, _inf, _termlnk, _sticaptmeth, _trgspt, _trgusg, _ctlsz, __VA_ARGS__ + U16_TO_U8S_LE((_totallen) + TUD_VIDEO_DESC_CS_VS_IN_LEN + (_numfmt) * (TU_ARGS_NUM(__VA_ARGS__))), \ + _ep, _inf, _termlnk, _sticaptmeth, _trgspt, _trgusg, (TU_ARGS_NUM(__VA_ARGS__)), __VA_ARGS__ /* 3.9.2.2 */ -#define TUD_VIDEO_DESC_CS_VS_OUTPUT(_numfmt, _totallen, _ep, _inf, _termlnk, _ctlsz, ...) \ - TUD_VIDEO_DESC_CS_VS_OUT_LEN + (_numfmt) * (_ctlsz), TUSB_DESC_CS_INTERFACE, \ +#define TUD_VIDEO_DESC_CS_VS_OUTPUT(_numfmt, _totallen, _ep, _inf, _termlnk, ...) \ + TUD_VIDEO_DESC_CS_VS_OUT_LEN + (_numfmt) * (TU_ARGS_NUM(__VA_ARGS__)), TUSB_DESC_CS_INTERFACE, \ VIDEO_CS_VS_INTERFACE_OUTPUT_HEADER, _numfmt, \ - U16_TO_U8S_LE((_totallen) + TUD_VIDEO_DESC_CS_VS_OUT_LEN + (_numfmt) * (_ctlsz)), \ - _ep, _inf, _termlnk, _ctlsz, __VA_ARGS__ + U16_TO_U8S_LE((_totallen) + TUD_VIDEO_DESC_CS_VS_OUT_LEN + (_numfmt) * (TU_ARGS_NUM(__VA_ARGS__))), \ + _ep, _inf, _termlnk, (TU_ARGS_NUM(__VA_ARGS__)), __VA_ARGS__ /* Uncompressed 3.1.1 */ #define TUD_VIDEO_GUID(_g0,_g1,_g2,_g3,_g4,_g5,_g6,_g7,_g8,_g9,_g10,_g11,_g12,_g13,_g14,_g15) _g0,_g1,_g2,_g3,_g4,_g5,_g6,_g7,_g8,_g9,_g10,_g11,_g12,_g13,_g14,_g15 @@ -378,11 +378,11 @@ typedef struct TU_ATTR_PACKED { U32_TO_U8S_LE(_minfrminterval), U32_TO_U8S_LE(_maxfrminterval), U32_TO_U8S_LE(_frmintervalstep) /* Uncompressed 3.1.2 Table 3-4 */ -#define TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_DISC(_frmidx, _cap, _width, _height, _minbr, _maxbr, _maxfrmbufsz, _frminterval, _numfrminterval, ...) \ - TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_DISC_LEN + _numfrminterval * 4, \ +#define TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_DISC(_frmidx, _cap, _width, _height, _minbr, _maxbr, _maxfrmbufsz, _frminterval, ...) \ + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_DISC_LEN + (TU_ARGS_NUM(__VA_ARGS__)) * 4, \ TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_INTERFACE_FRAME_UNCOMPRESSED, \ _frmidx, _cap, U16_TO_U8S_LE(_width), U16_TO_U8S_LE(_height), U32_TO_U8S_LE(_minbr), U32_TO_U8S_LE(_maxbr), \ - U32_TO_U8S_LE(_maxfrmbufsz), U32_TO_U8S_LE(_frminterval), _numfrminterval, __VA_ARGS__ + U32_TO_U8S_LE(_maxfrmbufsz), U32_TO_U8S_LE(_frminterval), (TU_ARGS_NUM(__VA_ARGS__)), __VA_ARGS__ /* 3.9.2.6 */ #define TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING(_color, _trns, _mat) \ diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index bee80d6e8..001de388e 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -321,7 +321,6 @@ static bool _open_vs_itf(uint8_t rhport, videod_interface_t *self, unsigned itfn cur += tu_desc_len(cur); } *ofs = (void const*)vs - self->beg; - TU_LOG2(" done\r\n"); return true; } @@ -346,6 +345,7 @@ static int handle_video_ctl_std_req(uint8_t rhport, uint8_t stage, tusb_control_ return VIDEO_UNKNOWN; if (!_open_vc_itf(rhport, &_videod_itf[itf], request->wValue)) return VIDEO_UNKNOWN; + tud_control_status(rhport, request); return VIDEO_NO_ERROR; default: /* Unknown/Unsupported request */ TU_BREAKPOINT(); @@ -457,6 +457,7 @@ static int handle_video_stm_std_req(uint8_t rhport, uint8_t stage, tusb_control_ return VIDEO_UNKNOWN; if (!_open_vs_itf(rhport, &_videod_itf[itf], itfnum, request->wValue)) return VIDEO_UNKNOWN; + tud_control_status(rhport, request); return VIDEO_NO_ERROR; default: /* Unknown/Unsupported request */ TU_BREAKPOINT(); @@ -612,12 +613,6 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin cur = _next_desc_itf(cur, end); } self->len = (uintptr_t)cur - (uintptr_t)itf_desc; - /*------------- Video Stream Interface -------------*/ - unsigned itfnum = 0; - for (unsigned i = 0; i < bInCollection; ++i) { - itfnum = vc->ctl.baInterfaceNr[i]; - if (!_open_vs_itf(rhport, self, itfnum, 0)) return 0; - } return (uintptr_t)cur - (uintptr_t)itf_desc; } -- cgit v1.3.1 From 2b4e02f192446f4fdf92c7e83ab260ae743503e9 Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Sun, 15 Aug 2021 18:07:53 +0900 Subject: Implement some mandatory requests on streaming interface --- .../device/video_capture/src/usb_descriptors.h | 2 +- src/class/video/video.h | 92 ++++++--- src/class/video/video_device.c | 213 +++++++++++++++------ src/class/video/video_device.h | 6 + 4 files changed, 224 insertions(+), 89 deletions(-) diff --git a/examples/device/video_capture/src/usb_descriptors.h b/examples/device/video_capture/src/usb_descriptors.h index e7b47b66a..867e9af42 100644 --- a/examples/device/video_capture/src/usb_descriptors.h +++ b/examples/device/video_capture/src/usb_descriptors.h @@ -29,7 +29,7 @@ /* Time stamp base clock. It is a deprecated parameter. */ #define UVC_CLOCK_FREQUENCY 27000000 -// video capture path +/* video capture path */ #define UVC_ENTITY_CAP_INPUT_TERMINAL 0x01 #define UVC_ENTITY_CAP_OUTPUT_TERMINAL 0x02 diff --git a/src/class/video/video.h b/src/class/video/video.h index 773c87845..17e1658b5 100644 --- a/src/class/video/video.h +++ b/src/class/video/video.h @@ -81,15 +81,13 @@ typedef enum { } video_subclass_type_t; /* A.3 */ -typedef enum -{ +typedef enum { VIDEO_INT_PROTOCOL_CODE_UNDEF = 0x00, VIDEO_INT_PROTOCOL_CODE_15, } video_interface_protocol_code_t; /* A.5 */ -typedef enum -{ +typedef enum { VIDEO_CS_VC_INTERFACE_VC_DESCRIPTOR_UNDEF = 0x00, VIDEO_CS_VC_INTERFACE_HEADER, VIDEO_CS_VC_INTERFACE_INPUT_TERMINAL, @@ -98,11 +96,11 @@ typedef enum VIDEO_CS_VC_INTERFACE_PROCESSING_UNIT, VIDEO_CS_VC_INTERFACE_EXTENSION_UNIT, VIDEO_CS_VC_INTERFACE_ENCODING_UNIT, + VIDEO_CS_VC_INTERFACE_MAX, } video_cs_vc_interface_subtype_t; /* A.6 */ -typedef enum -{ +typedef enum { VIDEO_CS_VS_INTERFACE_VS_DESCRIPTOR_UNDEF = 0x00, VIDEO_CS_VS_INTERFACE_INPUT_HEADER, VIDEO_CS_VS_INTERFACE_OUTPUT_HEADER, @@ -126,8 +124,7 @@ typedef enum } video_cs_vs_interface_subtype_t; /* A.8 */ -typedef enum -{ +typedef enum { VIDEO_REQUEST_UNDEF = 0x00, VIDEO_REQUEST_SET_CUR, VIDEO_REQUEST_SET_CUR_ALL = 0x11, @@ -147,16 +144,14 @@ typedef enum } video_control_request_t; /* A.9.1 */ -typedef enum -{ +typedef enum { VIDEO_VC_CTL_UNDEF = 0x00, VIDEO_VC_CTL_VIDEO_POWER_MODE, VIDEO_VC_CTL_REQUEST_ERROR_CODE, } video_interface_control_selector_t; /* A.9.8 */ -typedef enum -{ +typedef enum { VIDEO_VS_CTL_UNDEF = 0x00, VIDEO_VS_CTL_PROBE, VIDEO_VS_CTL_COMMIT, @@ -170,8 +165,7 @@ typedef enum } video_interface_streaming_selector_t; /* B. Terminal Types */ -typedef enum -{ +typedef enum { VIDEO_TT_VENDOR_SPECIFIC = 0x0100, VIDEO_TT_STREAMING, VIDEO_ITT_VENDOR_SPECIFIC = 0x0200, @@ -254,20 +248,53 @@ typedef struct TU_ATTR_PACKED { }; } tusb_desc_cs_video_stm_itf_hdr_t; +typedef struct TU_ATTR_PACKED { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bFormatIndex; + uint8_t bNumFrameDescriptors; + uint8_t guidFormat[16]; + uint8_t bBitsPerPixel; + uint8_t bDefaultFrameIndex; + uint8_t bAspectRatioX; + uint8_t bAspectRatioY; + uint8_t bmInterlaceFlags; + uint8_t bCopyProtect; +} tusb_desc_cs_video_fmt_uncompressed_t; + +typedef struct TU_ATTR_PACKED { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bFrameIndex; + uint8_t bNumFrameDescriptors; + uint8_t guidFormat[16]; + uint8_t bBitsPerPixel; + uint8_t bDefaultFrameIndex; + uint8_t bAspectRatioX; + uint8_t bAspectRatioY; + uint8_t bmInterlaceFlags; + uint8_t bCopyProtect; +} tusb_desc_cs_video_frm_uncompressed_t; + //--------------------------------------------------------------------+ // Requests //--------------------------------------------------------------------+ /* 4.3.1.1 */ typedef struct TU_ATTR_PACKED { - struct TU_ATTR_PACKEDt { - uint16_t dwFrameInterval: 1; - uint16_t wKeyFrameRatel : 1; - uint16_t wPFrameRate : 1; - uint16_t wCompQuality : 1; - uint16_t wCompWindowSize: 1; - uint16_t : 0; - } bmHint; + union { + uint8_t bmHint; + struct TU_ATTR_PACKED { + uint16_t dwFrameInterval: 1; + uint16_t wKeyFrameRatel : 1; + uint16_t wPFrameRate : 1; + uint16_t wCompQuality : 1; + uint16_t wCompWindowSize: 1; + uint16_t : 0; + } Hint; + }; uint8_t bFormatIndex; uint8_t bFrameIndex; uint32_t dwFrameInterval; @@ -279,22 +306,27 @@ typedef struct TU_ATTR_PACKED { uint32_t dwMaxVideoFrameSize; uint32_t dwMaxPayloadTransferSize; uint32_t dwClockFrequency; - struct TU_ATTR_PACKED { - uint8_t FrameID : 1; - uint8_t EndOfFrame: 1; - uint8_t EndOfSlice: 1; - uint8_t : 0; - } bmFramingInfo; + union { + uint8_t bmFramingInfo; + struct TU_ATTR_PACKED { + uint8_t FrameID : 1; + uint8_t EndOfFrame: 1; + uint8_t EndOfSlice: 1; + uint8_t : 0; + } FramingInfo; + }; uint8_t bPreferedVersion; uint8_t bMinVersion; uint8_t bMaxVersion; uint8_t bUsage; - uint8_t bBitDepthLum; + uint8_t bBitDepthLuma; uint8_t bmSettings; uint8_t bMaxNumberOfRefFramesPlus1; uint16_t bmRateControlModes; uint64_t bmLayoutPerStream; -} video_probe_and_commit_t; +} video_probe_and_commit_control_t; + +TU_VERIFY_STATIC( sizeof(video_probe_and_commit_control_t) == 48, "size is not correct"); #define TUD_VIDEO_DESC_IAD_LEN 8 #define TUD_VIDEO_DESC_STD_VC_LEN 9 diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index 001de388e..ee6f0b790 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -65,20 +65,35 @@ typedef struct TU_ATTR_PACKED { uint8_t bEntityId; } tusb_desc_cs_video_entity_itf_t; -typedef struct -{ + +typedef struct { + void const *beg; /* The head of the first video control interface descriptor */ + uint16_t length; /* Byte length of the video control interface descriptors */ + uint16_t offset; /* offset bytes for the current video control interface descripter */ + uint8_t error_code; /* error code set by previous transaction */ + uint8_t power_mode; /* current power mode */ +} videod_control_interface_t; + +typedef struct { + tusb_desc_vs_itf_t const *descriptor; /* video streaming interface descriptor */ + uint16_t offset; /* video streaming interface descriptor */ + video_probe_and_commit_control_t settings; /* last video streaming interface descriptor */ + uint8_t error_code; +} videod_streaming_interface_t; + +typedef struct { void const *beg; /* The head of the first video control interface descriptor */ uint16_t len; /* Byte length of the descriptors */ uint16_t ofs[3]; /* offsets for video control/streaming interface. 0:control 1:streaming 2:streaming */ + uint8_t error_code[3]; /* error code for video control/streaming interface. 0:control 1:streaming 2:streaming */ uint8_t power_mode; - uint8_t error_code; /*------------- From this point, data is not cleared by bus reset -------------*/ // Endpoint Transfer buffer // CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUD_CDC_EP_BUFSIZE]; // CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUD_CDC_EP_BUFSIZE]; - uint8_t ctl_buf; + uint8_t ctl_buf[64]; } videod_interface_t; @@ -91,6 +106,30 @@ CFG_TUSB_MEM_SECTION static videod_interface_t _videod_itf[CFG_TUD_VIDEO]; static uint8_t const _cap_get = 0x1u; /* support for GET */ static uint8_t const _cap_get_set = 0x3u; /* support for GET and SET */ +static video_probe_and_commit_control_t const def_stm_settings = { + .bmHint = 0, + .bFormatIndex = 1, + .bFrameIndex = 1, + .dwFrameInterval = (10000000/15), + .wKeyFrameRate = 1, + .wPFrameRate = 0, + .wCompQuality = 1, /* 1 to 10000 */ + .wCompWindowSize = 1, /* Maybe it is match to GOP size */ + .wDelay = 240, /* milliseconds */ + .dwMaxVideoFrameSize = 128 * 96 * 12 / 8, + .dwMaxPayloadTransferSize = 256, /* Maybe it is the maximum packet size under this settings */ + .dwClockFrequency = 27000000, /* same as MPEG-2 system time clock */ + .bmFramingInfo = 0, + .bPreferedVersion = 1, + .bMinVersion = 1, + .bMaxVersion = 1, + .bUsage = 0, + .bBitDepthLuma = 8, + .bmSettings = 0, + .bMaxNumberOfRefFramesPlus1 = 0, + .bmRateControlModes = 0, + .bmLayoutPerStream = 0 +}; static tusb_desc_vc_itf_t const* _get_desc_vc(videod_interface_t const *self) { @@ -116,7 +155,6 @@ static tusb_desc_vs_itf_t const *_get_desc_vs(videod_interface_t const *self, un return (tusb_desc_vs_itf_t const*)(self->beg + *ofs); } - /** Find the first descriptor with the specified descriptor type. * * @param[in] beg The head of descriptor byte array. @@ -146,7 +184,7 @@ static void const* _next_desc_itf(void const *beg, void const *end) void const *cur = beg; unsigned itfnum = ((tusb_desc_interface_t const*)cur)->bInterfaceNumber; while ((cur < end) && - (itfnum == ((tusb_desc_interface_t const*)cur)->bInterfaceNumber)) { + (itfnum == ((tusb_desc_interface_t const*)cur)->bInterfaceNumber)) { cur = _find_desc(tu_desc_next(cur), end, TUSB_DESC_INTERFACE); } return cur; @@ -186,9 +224,9 @@ static void const* _find_desc_entity(tusb_desc_vc_itf_t const *vc, unsigned enti void const *end = beg + vc->std.bLength + vc->ctl.wTotalLength; for (void const *cur = beg; cur < end; cur = _find_desc(cur, end, TUSB_DESC_CS_INTERFACE)) { tusb_desc_cs_video_entity_itf_t const *itf = (tusb_desc_cs_video_entity_itf_t const *)cur; - if ((VIDEO_CS_VC_INTERFACE_INPUT_TERMINAL == itf->bDescriptorSubtype || - VIDEO_CS_VC_INTERFACE_OUTPUT_TERMINAL == itf->bDescriptorSubtype) && - itf->bEntityId == entityid) { + if ((VIDEO_CS_VC_INTERFACE_INPUT_TERMINAL <= itf->bDescriptorSubtype + && itf->bDescriptorSubtype < VIDEO_CS_VC_INTERFACE_MAX) + && itf->bEntityId == entityid) { return itf; } cur = tu_desc_next(cur); @@ -334,8 +372,8 @@ static int handle_video_ctl_std_req(uint8_t rhport, uint8_t stage, tusb_control_ tusb_desc_vc_itf_t const *vc = _get_desc_vc(&_videod_itf[itf]); if (!vc) return VIDEO_UNKNOWN; if (tud_control_xfer(rhport, request, - (void*)&vc->std.bAlternateSetting, - sizeof(vc->std.bAlternateSetting))) + (void*)&vc->std.bAlternateSetting, + sizeof(vc->std.bAlternateSetting))) return VIDEO_NO_ERROR; return VIDEO_UNKNOWN; case TUSB_REQ_SET_INTERFACE: @@ -359,10 +397,11 @@ static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r /* 4.2.1 Interface Control Request */ switch (TU_U16_HIGH(request->wValue)) { case VIDEO_VC_CTL_VIDEO_POWER_MODE: + TU_LOG2(" Power Mode "); switch (request->bRequest) { case VIDEO_REQUEST_SET_CUR: if (stage == CONTROL_STAGE_SETUP) { - TU_LOG2(" Set Power Mode\r\n"); + TU_LOG2("Set\r\n"); TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN); if (!tud_control_xfer(rhport, request, &self->power_mode, sizeof(self->power_mode))) return VIDEO_UNKNOWN; @@ -371,39 +410,36 @@ static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r } return VIDEO_NO_ERROR; case VIDEO_REQUEST_GET_CUR: - if (stage == CONTROL_STAGE_SETUP) { - TU_LOG2(" Get Power Mode\r\n"); - TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN); - if (!tud_control_xfer(rhport, request, &self->power_mode, sizeof(self->power_mode))) - return VIDEO_UNKNOWN; - } + if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; + TU_LOG2("Get\r\n"); + TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN); + if (!tud_control_xfer(rhport, request, &self->power_mode, sizeof(self->power_mode))) + return VIDEO_UNKNOWN; return VIDEO_NO_ERROR; case VIDEO_REQUEST_GET_INFO: - if (stage == CONTROL_STAGE_SETUP) { - TU_LOG2(" Get Info Power Mode\r\n"); - TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN); - if (!tud_control_xfer(rhport, request, (uint8_t*)&_cap_get_set, sizeof(_cap_get_set))) - return VIDEO_UNKNOWN; - } + if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; + TU_LOG2("GetInfo\r\n"); + TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN); + if (!tud_control_xfer(rhport, request, (uint8_t*)&_cap_get_set, sizeof(_cap_get_set))) + return VIDEO_UNKNOWN; return VIDEO_NO_ERROR; default: break; } break; case VIDEO_VC_CTL_REQUEST_ERROR_CODE: + TU_LOG2(" Error Code"); switch (request->bRequest) { case VIDEO_REQUEST_GET_CUR: - if (stage == CONTROL_STAGE_SETUP) { - TU_LOG2(" Get Error Code\r\n"); - if (!tud_control_xfer(rhport, request, &self->error_code, sizeof(self->error_code))) - return VIDEO_UNKNOWN; - } + if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; + TU_LOG2(" Get\r\n"); + if (!tud_control_xfer(rhport, request, &self->error_code[0], sizeof(uint8_t))) + return VIDEO_UNKNOWN; return VIDEO_NO_ERROR; case VIDEO_REQUEST_GET_INFO: - if (stage == CONTROL_STAGE_SETUP) { - TU_LOG2(" Get Info Error Code\r\n"); - if (tud_control_xfer(rhport, request, (uint8_t*)&_cap_get, sizeof(_cap_get))) - return VIDEO_UNKNOWN; - } + if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; + TU_LOG2(" GetInfo\r\n"); + if (tud_control_xfer(rhport, request, (uint8_t*)&_cap_get, sizeof(_cap_get))) + return VIDEO_UNKNOWN; return VIDEO_NO_ERROR; default: break; } @@ -427,7 +463,7 @@ static int handle_video_ctl_req(uint8_t rhport, uint8_t stage, tusb_control_requ return handle_video_ctl_cs_req(rhport, stage, request, itf); } else { if (!_find_desc_entity(_get_desc_vc(&_videod_itf[itf]), entity_id)) - return VIDEO_INVALID_REQUEST; + return VIDEO_INVALID_REQUEST; return VIDEO_INVALID_REQUEST; } default: @@ -446,8 +482,8 @@ static int handle_video_stm_std_req(uint8_t rhport, uint8_t stage, tusb_control_ tusb_desc_vs_itf_t const *vs = _get_desc_vs(&_videod_itf[itf], itfnum); if (!vs) return VIDEO_UNKNOWN; if (tud_control_xfer(rhport, request, - (void*)&vs->std.bAlternateSetting, - sizeof(vs->std.bAlternateSetting))) + (void*)&vs->std.bAlternateSetting, + sizeof(vs->std.bAlternateSetting))) return VIDEO_NO_ERROR; return VIDEO_UNKNOWN; case TUSB_REQ_SET_INTERFACE: @@ -467,55 +503,113 @@ static int handle_video_stm_std_req(uint8_t rhport, uint8_t stage, tusb_control_ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf) { - // videod_interface_t *self = &_videod_itf[itf]; - (void)rhport; (void)stage; (void)itf; + (void)rhport; + videod_interface_t *self = &_videod_itf[itf]; /* 4.2.1 Interface Control Request */ switch (TU_U16_HIGH(request->wValue)) { + case VIDEO_VS_CTL_STREAM_ERROR_CODE: + TU_LOG2(" Error Code "); + switch (request->bRequest) { + case VIDEO_REQUEST_GET_CUR: + if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; + TU_LOG2("Get\r\n"); + /* TODO */ + if (!tud_control_xfer(rhport, request, &self->error_code[0], sizeof(uint8_t))) + return VIDEO_UNKNOWN; + return VIDEO_NO_ERROR; + case VIDEO_REQUEST_GET_INFO: + if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; + TU_LOG2("GetInfo\r\n"); + if (tud_control_xfer(rhport, request, (uint8_t*)&_cap_get, sizeof(_cap_get))) + return VIDEO_UNKNOWN; + return VIDEO_NO_ERROR; + default: break; + } + break; case VIDEO_VS_CTL_PROBE: - TU_LOG2(" Probe "); switch (request->bRequest) { case VIDEO_REQUEST_SET_CUR: - TU_LOG2("Set\r\n"); - return VIDEO_UNKNOWN; + if (stage == CONTROL_STAGE_SETUP) { + TU_VERIFY(sizeof(video_probe_and_commit_control_t) == request->wLength, VIDEO_UNKNOWN); + if (!tud_control_xfer(rhport, request, self->ctl_buf, sizeof(video_probe_and_commit_control_t))) + return VIDEO_UNKNOWN; + } else if (stage == CONTROL_STAGE_ACK) { + if (tud_video_probe_set_cb) + return tud_video_probe_set_cb(itf, (video_probe_and_commit_control_t const*)self->ctl_buf); + } + return VIDEO_NO_ERROR; case VIDEO_REQUEST_GET_CUR: - TU_LOG2("Get\r\n"); + if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; + TU_VERIFY(request->wLength, VIDEO_UNKNOWN); + if (tud_control_xfer(rhport, request, (void*)&def_stm_settings, + sizeof(video_probe_and_commit_control_t))) + return VIDEO_NO_ERROR; return VIDEO_UNKNOWN; case VIDEO_REQUEST_GET_MIN: - TU_LOG2("Get Min\r\n"); + if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; + TU_VERIFY(request->wLength, VIDEO_UNKNOWN); + if (tud_control_xfer(rhport, request, (void*)&def_stm_settings, + sizeof(video_probe_and_commit_control_t))) + return VIDEO_NO_ERROR; return VIDEO_UNKNOWN; case VIDEO_REQUEST_GET_MAX: - TU_LOG2("Get Man\r\n"); + if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; + TU_VERIFY(request->wLength, VIDEO_UNKNOWN); + if (tud_control_xfer(rhport, request, (void*)&def_stm_settings, + sizeof(video_probe_and_commit_control_t))) + return VIDEO_NO_ERROR; return VIDEO_UNKNOWN; case VIDEO_REQUEST_GET_RES: - TU_LOG2("Get Res\r\n"); return VIDEO_UNKNOWN; case VIDEO_REQUEST_GET_DEF: - TU_LOG2("Get Def\r\n"); return VIDEO_UNKNOWN; case VIDEO_REQUEST_GET_LEN: - TU_LOG2("Get Len\r\n"); return VIDEO_UNKNOWN; case VIDEO_REQUEST_GET_INFO: - TU_LOG2("Get Info\r\n"); + if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; + TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN); + if (tud_control_xfer(rhport, request, (uint8_t*)&_cap_get_set, sizeof(_cap_get_set))) + return VIDEO_NO_ERROR; return VIDEO_UNKNOWN; default: break; } break; case VIDEO_VS_CTL_COMMIT: - TU_LOG2(" Commit "); switch (request->bRequest) { case VIDEO_REQUEST_SET_CUR: - TU_LOG2("Set\r\n"); - return VIDEO_UNKNOWN; + if (stage == CONTROL_STAGE_SETUP) { + TU_VERIFY(sizeof(video_probe_and_commit_control_t) == request->wLength, VIDEO_UNKNOWN); + if (!tud_control_xfer(rhport, request, self->ctl_buf, sizeof(video_probe_and_commit_control_t))) + return VIDEO_UNKNOWN; + } else if (stage == CONTROL_STAGE_ACK) { + if (tud_video_commit_set_cb) + return tud_video_commit_set_cb(itf, (video_probe_and_commit_control_t const*)self->ctl_buf); + } + return VIDEO_NO_ERROR; case VIDEO_REQUEST_GET_CUR: - TU_LOG2("Get\r\n"); + if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; + TU_VERIFY(request->wLength, VIDEO_UNKNOWN); + if (tud_control_xfer(rhport, request, (void*)&def_stm_settings, + sizeof(video_probe_and_commit_control_t))) + return VIDEO_NO_ERROR; return VIDEO_UNKNOWN; case VIDEO_REQUEST_GET_INFO: - TU_LOG2("Get Info\r\n"); + if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; + TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN); + if (tud_control_xfer(rhport, request, (uint8_t*)&_cap_get_set, sizeof(_cap_get_set))) + return VIDEO_NO_ERROR; return VIDEO_UNKNOWN; default: break; } break; + case VIDEO_VS_CTL_STILL_PROBE: + case VIDEO_VS_CTL_STILL_COMMIT: + case VIDEO_VS_CTL_STILL_IMAGE_TRIGGER: + case VIDEO_VS_CTL_GENERATE_KEY_FRAME: + case VIDEO_VS_CTL_UPDATE_FRAME_SEGMENT: + case VIDEO_VS_CTL_SYNCH_DELAY_CONTROL: + /* TODO */ + break; default: break; } /* Unknown/Unsupported request */ @@ -587,8 +681,8 @@ void videod_reset(uint8_t rhport) uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len) { TU_VERIFY((TUSB_CLASS_VIDEO == itf_desc->bInterfaceClass) && - (VIDEO_SUBCLASS_CONTROL == itf_desc->bInterfaceSubClass) && - (VIDEO_INT_PROTOCOL_CODE_15 == itf_desc->bInterfaceProtocol), 0); + (VIDEO_SUBCLASS_CONTROL == itf_desc->bInterfaceSubClass) && + (VIDEO_INT_PROTOCOL_CODE_15 == itf_desc->bInterfaceProtocol), 0); /* Find available interface */ videod_interface_t *self = NULL; @@ -607,7 +701,7 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin if (!_open_vc_itf(rhport, self, 0)) return 0; tusb_desc_vc_itf_t const *vc = _get_desc_vc(self); unsigned bInCollection = vc->ctl.bInCollection; - /* Update end */ + /* Find the end of the video interface descriptor */ void const *cur = _next_desc_itf(itf_desc, end); for (unsigned i = 0; i < bInCollection; ++i) { cur = _next_desc_itf(cur, end); @@ -623,6 +717,7 @@ bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_ { int err; int (*handle_video_req)(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf) = NULL; + uint8_t *error_code; if (request->bmRequestType_bit.recipient != TUSB_REQ_RCPT_INTERFACE) { return false; } @@ -634,6 +729,7 @@ bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_ vc = _get_desc_vc(&_videod_itf[itf]); if (itfnum == vc->std.bInterfaceNumber) { handle_video_req = handle_video_ctl_req; + error_code = &_videod_itf[itf].error_code[0]; break; } int i; @@ -641,13 +737,14 @@ bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_ for (i = 0; i < bInCollection && itfnum != vc->ctl.baInterfaceNr[i]; ++i) ; if (i < bInCollection) { handle_video_req = handle_video_stm_req; + error_code = &_videod_itf[itf].error_code[1 + i]; break; } } if (itf == CFG_TUD_VIDEO) return false; err = handle_video_req(rhport, stage, request, itf); - _videod_itf[itf].error_code = (uint8_t)err; + *error_code = (uint8_t)err; if (err) return false; return true; } diff --git a/src/class/video/video_device.h b/src/class/video/video_device.h index 95d352524..b4bdfc699 100644 --- a/src/class/video/video_device.h +++ b/src/class/video/video_device.h @@ -48,6 +48,12 @@ TU_ATTR_WEAK bool tud_video_get_cur_cb(uint8_t rhport, tusb_control_request_t co /* @return video_error_code_t */ TU_ATTR_WEAK int tud_video_power_mode_cb(unsigned itf, uint8_t power_mod); + +/* @return video_error_code_t */ +TU_ATTR_WEAK int tud_video_probe_set_cb(unsigned itf, video_probe_and_commit_control_t const *settings); + +/* @return video_error_code_t */ +TU_ATTR_WEAK int tud_video_commit_set_cb(unsigned itf, video_probe_and_commit_control_t const *settings); //--------------------------------------------------------------------+ // INTERNAL USBD-CLASS DRIVER API //--------------------------------------------------------------------+ -- cgit v1.3.1 From 3cb4bb391d814d88662581f47b4dc13097d7c69e Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Mon, 20 Sep 2021 14:55:56 +0900 Subject: Separate a handling resource into controller and streaming --- examples/device/video_capture/src/main.c | 41 +++ examples/device/video_capture/src/tusb_config.h | 4 + .../device/video_capture/src/usb_descriptors.c | 2 +- src/class/video/video.h | 17 + src/class/video/video_device.c | 347 +++++++++++++-------- src/class/video/video_device.h | 22 +- 6 files changed, 297 insertions(+), 136 deletions(-) diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c index 098cd2f8d..1921da4bf 100644 --- a/examples/device/video_capture/src/main.c +++ b/examples/device/video_capture/src/main.c @@ -30,10 +30,14 @@ #include "bsp/board.h" #include "tusb.h" +#include "images.h" //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF PROTYPES //--------------------------------------------------------------------+ +#define FRAME_WIDTH 128 +#define FRAME_HEIGHT 96 + /* Blink pattern * - 250 ms : device not mounted * - 1000 ms : device mounted @@ -102,8 +106,45 @@ void tud_resume_cb(void) //--------------------------------------------------------------------+ // USB Video //--------------------------------------------------------------------+ +static unsigned char const *frames[] = { + black_128x96_yuv, white_128x96_yuv +}; +uint8_t current_frame = 0; + void video_task(void) { + static unsigned start_ms = 0; + static unsigned interval_ms = 66; + static unsigned frame_num = 0; + static unsigned already_sent = 0; + + if (!tud_video_n_streaming(0)) return; + + if (!already_sent) { + tud_video_n_frame_xfer(0, 0, (void*)frames[current_frame], 128 * 96 * 12/8); + current_frame ^= 1; + already_sent = 1; + } + + unsigned cur = board_millis(); + if (cur - start_ms < interval_ms) return; // not enough time + start_ms += interval_ms; + + /* flip buffer */ + ++frame_num; + if (frame_num % 3) { + interval_ms = 66; + } else { + interval_ms = 67; + } +} + +int tud_video_frame_xfer_complete_cb(void) +{ + /* prepare tx */ + tud_video_n_frame_xfer(0, 0, (void*)frames[current_frame], 128 * 96 * 12/8); + current_frame ^= 1; + return 0; } //--------------------------------------------------------------------+ diff --git a/examples/device/video_capture/src/tusb_config.h b/examples/device/video_capture/src/tusb_config.h index ae2387357..3958b85b6 100644 --- a/examples/device/video_capture/src/tusb_config.h +++ b/examples/device/video_capture/src/tusb_config.h @@ -90,6 +90,10 @@ #define CFG_TUD_ENDPOINT0_SIZE 64 #endif +#define CFG_TUD_VIDEO_EP_BUFSIZE 256 + +#define CFG_TUD_VIDEO_STREAMING 1 + //------------- CLASS -------------// #define CFG_TUD_CDC 0 #define CFG_TUD_MSC 0 diff --git a/examples/device/video_capture/src/usb_descriptors.c b/examples/device/video_capture/src/usb_descriptors.c index d3544cc63..096ac4373 100644 --- a/examples/device/video_capture/src/usb_descriptors.c +++ b/examples/device/video_capture/src/usb_descriptors.c @@ -104,7 +104,7 @@ uint8_t const desc_fs_configuration[] = // Config number, interface count, string index, total length, attribute, power in mA TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0, 500), // IAD for Video Control - TUD_VIDEO_CAPTURE_DESCRIPTOR(4, EPNUM_VIDEO_IN, 128, 96, 15, 256) + TUD_VIDEO_CAPTURE_DESCRIPTOR(4, EPNUM_VIDEO_IN, 128, 96, 10, 256) }; // Invoked when received GET CONFIGURATION DESCRIPTOR diff --git a/src/class/video/video.h b/src/class/video/video.h index 17e1658b5..444433e86 100644 --- a/src/class/video/video.h +++ b/src/class/video/video.h @@ -192,6 +192,23 @@ typedef struct TU_ATTR_PACKED { uint8_t baInterfaceNr[]; } tusb_desc_cs_video_ctl_itf_hdr_t; +/* 2.4.3.3 */ +typedef struct TU_ATTR_PACKED { + uint8_t bHeaderLength; + union { + uint8_t bmHeaderInfo; + struct { + uint8_t FrameID: 1; + uint8_t EndOfFrame: 1; + uint8_t PresentationTime: 1; + uint8_t SourceClockReference: 1; + uint8_t StillImage: 1; + uint8_t Error: 1; + uint8_t EndOfHeader: 1; + }; + }; +} tusb_video_payload_header_t; + /* 3.9.2.1 */ typedef struct TU_ATTR_PACKED { uint8_t bLength; diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index ee6f0b790..dc6cf376c 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -66,7 +66,7 @@ typedef struct TU_ATTR_PACKED { } tusb_desc_cs_video_entity_itf_t; -typedef struct { +typedef struct TU_ATTR_PACKED { void const *beg; /* The head of the first video control interface descriptor */ uint16_t length; /* Byte length of the video control interface descriptors */ uint16_t offset; /* offset bytes for the current video control interface descripter */ @@ -74,18 +74,29 @@ typedef struct { uint8_t power_mode; /* current power mode */ } videod_control_interface_t; -typedef struct { - tusb_desc_vs_itf_t const *descriptor; /* video streaming interface descriptor */ - uint16_t offset; /* video streaming interface descriptor */ - video_probe_and_commit_control_t settings; /* last video streaming interface descriptor */ - uint8_t error_code; +typedef struct TU_ATTR_PACKED { + uint8_t index_vc; /* index of video control interface */ + uint8_t error_code;/* error code for video control/streaming interface. 0:control 1:streaming 2:streaming */ + struct { + uint16_t beg; /* Offset of the beggining of video streaming interface descriptor */ + uint16_t end; /* Offset of the end of video streaming interface descriptor */ + uint16_t cur; /* Offset of the current settings */ + uint16_t ep[2]; /* Offset of endpoint descriptors */ + } desc; + + uint8_t *buffer; /* frame buffer. assume linear buffer. no support for stride access */ + uint32_t bufsize; /* frame buffer */ + uint32_t offset; /* offset for the next payload transfer */ + uint32_t max_payload_transfer_size; + uint8_t ep_buf[CFG_TUD_VIDEO_EP_BUFSIZE]; } videod_streaming_interface_t; -typedef struct { +typedef struct TU_ATTR_PACKED { void const *beg; /* The head of the first video control interface descriptor */ uint16_t len; /* Byte length of the descriptors */ - uint16_t ofs[3]; /* offsets for video control/streaming interface. 0:control 1:streaming 2:streaming */ - uint8_t error_code[3]; /* error code for video control/streaming interface. 0:control 1:streaming 2:streaming */ + uint16_t cur; /* offset for current video control interface */ + uint8_t stm[CFG_TUD_VIDEO_STREAMING]; /* Indices of streaming interface */ + uint8_t error_code; /* error code for video control/streaming interface. */ uint8_t power_mode; /*------------- From this point, data is not cleared by bus reset -------------*/ @@ -103,6 +114,7 @@ typedef struct { // INTERNAL OBJECT & FUNCTION DECLARATION //--------------------------------------------------------------------+ CFG_TUSB_MEM_SECTION static videod_interface_t _videod_itf[CFG_TUD_VIDEO]; +CFG_TUSB_MEM_SECTION static videod_streaming_interface_t _videod_streaming_itf[CFG_TUD_VIDEO_STREAMING]; static uint8_t const _cap_get = 0x1u; /* support for GET */ static uint8_t const _cap_get_set = 0x3u; /* support for GET and SET */ @@ -110,7 +122,7 @@ static video_probe_and_commit_control_t const def_stm_settings = { .bmHint = 0, .bFormatIndex = 1, .bFrameIndex = 1, - .dwFrameInterval = (10000000/15), + .dwFrameInterval = (10000000/10), .wKeyFrameRate = 1, .wPFrameRate = 0, .wCompQuality = 1, /* 1 to 10000 */ @@ -131,28 +143,26 @@ static video_probe_and_commit_control_t const def_stm_settings = { .bmLayoutPerStream = 0 }; -static tusb_desc_vc_itf_t const* _get_desc_vc(videod_interface_t const *self) +static inline uint8_t _desc_itfnum(void const *desc) { - return (tusb_desc_vc_itf_t const *)(self->beg + self->ofs[0]); + return ((uint8_t const*)desc)[2]; } -static uint16_t* _get_desc_ofs(videod_interface_t *self, unsigned itfnum) +static inline uint8_t _desc_ep_addr(void const *desc) { - void const *beg = self->beg; - uint16_t *ofs = self->ofs; - for (unsigned i = 1; i < sizeof(self->ofs)/sizeof(self->ofs[0]); ++i) { - if (!ofs[i]) continue; - tusb_desc_interface_t const* itf = (tusb_desc_interface_t const*)(beg + ofs[i]); - if (itfnum == itf->bInterfaceNumber) return &ofs[i]; - } - return NULL; + return ((uint8_t const*)desc)[2]; } -static tusb_desc_vs_itf_t const *_get_desc_vs(videod_interface_t const *self, unsigned itfnum) +static tusb_desc_vc_itf_t const* _get_desc_vc(videod_interface_t const *self) { - uint16_t const *ofs = _get_desc_ofs((videod_interface_t*)self, itfnum); - if (!ofs) return NULL; - return (tusb_desc_vs_itf_t const*)(self->beg + *ofs); + return (tusb_desc_vc_itf_t const *)(self->beg + self->cur); +} + +static tusb_desc_vs_itf_t const *_get_desc_vs(videod_streaming_interface_t const *self) +{ + if (!self->desc.cur) return NULL; + void const *desc = _videod_itf[self->index_vc].beg; + return (tusb_desc_vs_itf_t const*)(desc + self->desc.cur); } /** Find the first descriptor with the specified descriptor type. @@ -211,6 +221,23 @@ static void const* _find_desc_itf(void const *beg, void const *end, unsigned itf return end; } +/** Find the first endpoint descriptor in front of the next interface descriptor. + * + * @param[in] beg The head of descriptor byte array. + * @param[in] end The tail of descriptor byte array. + * + * @return The pointer for endpoint descriptor. + * @retval end did not found endpoint descriptor */ +static void const* _find_desc_ep(void const *beg, void const *end) +{ + for (void const *cur = beg; cur < end; cur = tu_desc_next(cur)) { + uint8_t desc_type = tu_desc_type(cur); + if (TUSB_DESC_ENDPOINT == desc_type) return cur; + if (TUSB_DESC_INTERFACE == desc_type) break; + } + return end; +} + /** Find the first entity descriptor with the specified entity ID in the video control interface descriptor. * * @param[in] vc The video control interface descriptor. @@ -252,7 +279,7 @@ static bool _close_vc_itf(uint8_t rhport, videod_interface_t *self) tusb_desc_endpoint_t const *notif = (tusb_desc_endpoint_t const *)cur; usbd_edpt_close(rhport, notif->bEndpointAddress); } - self->ofs[0] = 0; + self->cur = 0; return true; } @@ -266,15 +293,14 @@ static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, unsigned altn void const *beg = self->beg; void const *end = beg + self->len; /* The first descriptor is a video control interface descriptor. */ - unsigned itfnum = ((tusb_desc_interface_t const *)beg)->bInterfaceNumber; - void const *cur = _find_desc_itf(beg, end, itfnum, altnum); + void const *cur = _find_desc_itf(beg, end, _desc_itfnum(beg), altnum); TU_LOG2(" cur %ld\r\n", cur - beg); TU_VERIFY(cur < end); tusb_desc_vc_itf_t const *vc = (tusb_desc_vc_itf_t const *)cur; TU_LOG2(" bInCollection %d\r\n", vc->ctl.bInCollection); /* Support for up to 2 streaming interfaces only. */ - TU_ASSERT(vc->ctl.bInCollection < 3); + TU_ASSERT(vc->ctl.bInCollection <= CFG_TUD_VIDEO_STREAMING); /* Update to point the end of the video control interface descriptor. */ end = cur + vc->std.bLength + vc->ctl.wTotalLength; @@ -292,74 +318,86 @@ static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, unsigned altn /* Open the notification endpoint */ TU_ASSERT(usbd_edpt_open(rhport, notif)); } - self->ofs[0] = (void const*)vc - beg; + self->cur = (void const*)vc - beg; return true; } /** Set the specified alternate setting to own video control interface. * * @param[in,out] self The context. - * @param[in] itfnum The target interface number. */ -static bool _close_vs_itf(uint8_t rhport, videod_interface_t *self, unsigned itfnum) + * @param[in] altnum The target alternate setting number. */ +static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, unsigned altnum) { - uint16_t *ofs = _get_desc_ofs(self, itfnum); - if (!ofs) return true; - tusb_desc_vs_itf_t const *vs = (tusb_desc_vs_itf_t const*)(self->beg + *ofs); - /* The next of the video streaming interface header descriptor. */ - void const *cur = (void const*)vs + vs->std.bLength + vs->stm.bLength; - /* The end of the video streaming interface descriptor. */ - void const *end = (void const*)vs + vs->std.bLength + vs->stm.wTotalLength; - for (unsigned i = 0; i < vs->std.bNumEndpoints; ++i) { - cur = _find_desc(cur, end, TUSB_DESC_ENDPOINT); + unsigned i; + TU_LOG1(" reopen VS %d\r\n", altnum); + void const *desc = _videod_itf[stm->index_vc].beg; + + /* Close endpoints of previous settings. */ + for (i = 0; i < TU_ARRAY_SIZE(stm->desc.ep); ++i) { + unsigned ofs_ep = stm->desc.ep[i]; + if (!ofs_ep) break; + unsigned ep_adr = _desc_ep_addr(desc + ofs_ep); + usbd_edpt_close(rhport, ep_adr); + stm->desc.ep[i] = 0; + TU_LOG1(" close EP%02x\n", ep_adr); + } + + /* Find a alternate interface */ + void const *beg = desc + stm->desc.beg; + void const *end = desc + stm->desc.end; + void const *cur = _find_desc_itf(beg, end, _desc_itfnum(beg), altnum); + TU_VERIFY(cur < end); + unsigned numeps = ((tusb_desc_interface_t const *)cur)->bNumEndpoints; + TU_ASSERT(numeps <= TU_ARRAY_SIZE(stm->desc.ep)); + stm->desc.cur = cur - desc; /* Save the offset of the new settings */ + /* Open endpoints of the new settings. */ + for (i = 0, cur = tu_desc_next(cur); i < numeps; ++i, cur = tu_desc_next(cur)) { + cur = _find_desc_ep(cur, end); TU_ASSERT(cur < end); - tusb_desc_endpoint_t const *ep = (tusb_desc_endpoint_t const *)cur; - usbd_edpt_close(rhport, ep->bEndpointAddress); - cur += tu_desc_len(cur); + TU_ASSERT(usbd_edpt_open(rhport, (tusb_desc_endpoint_t const *)cur)); + stm->desc.ep[i] = cur - desc; + stm->max_payload_transfer_size = CFG_TUD_VIDEO_EP_BUFSIZE; + TU_LOG1(" open EP%02x\n", _desc_ep_addr(cur)); } - *ofs = 0; return true; } -/** Set the specified alternate setting to own video control interface. - * - * @param[in,out] self The context. - * @param[in] itfnum The target interface number. - * @param[in] altnum The target alternate setting number. */ -static bool _open_vs_itf(uint8_t rhport, videod_interface_t *self, unsigned itfnum, unsigned altnum) +static int _payload_xfer_in(uint8_t rhport, uint8_t itf) { - TU_LOG2(" open VS %d,%d\r\n", itfnum, altnum); - uint16_t *ofs = NULL; - for (unsigned i = 1; i < sizeof(self->ofs)/sizeof(self->ofs[0]); ++i) { - if (!self->ofs[i]) { - ofs = &self->ofs[i]; + videod_streaming_interface_t *stm = &_videod_streaming_itf[itf]; + void const *desc = _videod_itf[stm->index_vc].beg; + unsigned ep_addr = 0; + for (unsigned i = 0; i < CFG_TUD_VIDEO_STREAMING; ++i) { + unsigned ofs_ep = stm->desc.ep[i]; + if (!ofs_ep) continue; + ep_addr = _desc_ep_addr(desc + ofs_ep); + if (tu_edpt_dir(ep_addr)) break; - } } - if (!ofs) return false; - - tusb_desc_vc_itf_t const *vc = _get_desc_vc(self); - void const *end = self->beg + self->len; - /* Set the end of the video control interface descriptor. */ - void const *cur = (void const*)vc + vc->std.bLength + vc->ctl.wTotalLength; - - cur = _find_desc_itf(cur, end, itfnum, altnum); - TU_VERIFY(cur < end); - tusb_desc_vs_itf_t const *vs = (tusb_desc_vs_itf_t const*)cur; - /* Support for up to 2 endpoint only. */ - TU_ASSERT(vs->std.bNumEndpoints < 3); - /* Update to point the end of the video control interface descriptor. */ - end = cur + vs->std.bLength + vs->stm.wTotalLength; - /* Advance to the next descriptor after the class-specific VS interface header descriptor. */ - cur += vs->std.bLength + vs->stm.bLength; - for (unsigned i = 0; i < vs->std.bNumEndpoints; ++i) { - cur = _find_desc(cur, end, TUSB_DESC_ENDPOINT); - TU_VERIFY(cur < end); - tusb_desc_endpoint_t const *ep = (tusb_desc_endpoint_t const *)cur; - TU_ASSERT(usbd_edpt_open(rhport, ep)); - cur += tu_desc_len(cur); + TU_ASSERT(ep_addr, 0); + /* Claim the endpoint */ + TU_VERIFY( usbd_edpt_claim(rhport, ep_addr), 0); + + /* prepare a payload */ + unsigned mps = stm->max_payload_transfer_size; + uint32_t remaining = stm->bufsize - stm->offset; + uint32_t data_len = remaining < (mps - 2) ? remaining: (mps - 2); + stm->ep_buf[0] = 1; + stm->ep_buf[1] = 0; + memcpy(&stm->ep_buf[2], stm->buffer + stm->offset, data_len); + stm->offset += data_len; + remaining -= data_len; + TU_LOG2(" %d\n", data_len, remaining); + TU_ASSERT( usbd_edpt_xfer(rhport, ep_addr, stm->ep_buf, 2 + data_len), 0 ); + + if (!remaining) { + stm->buffer = NULL; + stm->bufsize = 0; + stm->offset = 0; + if (tud_video_frame_xfer_complete_cb) + tud_video_frame_xfer_complete_cb(); } - *ofs = (void const*)vs - self->beg; - return true; + return data_len; } /** Handle a standard request to the video control interface. */ @@ -432,7 +470,7 @@ static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r case VIDEO_REQUEST_GET_CUR: if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; TU_LOG2(" Get\r\n"); - if (!tud_control_xfer(rhport, request, &self->error_code[0], sizeof(uint8_t))) + if (!tud_control_xfer(rhport, request, &self->error_code, sizeof(uint8_t))) return VIDEO_UNKNOWN; return VIDEO_NO_ERROR; case VIDEO_REQUEST_GET_INFO: @@ -473,13 +511,12 @@ static int handle_video_ctl_req(uint8_t rhport, uint8_t stage, tusb_control_requ static int handle_video_stm_std_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf) { - unsigned itfnum; + videod_streaming_interface_t *self = &_videod_streaming_itf[itf]; switch (request->bRequest) { case TUSB_REQ_GET_INTERFACE: if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN); - itfnum = tu_u16_low(request->wIndex); - tusb_desc_vs_itf_t const *vs = _get_desc_vs(&_videod_itf[itf], itfnum); + tusb_desc_vs_itf_t const *vs = _get_desc_vs(self); if (!vs) return VIDEO_UNKNOWN; if (tud_control_xfer(rhport, request, (void*)&vs->std.bAlternateSetting, @@ -488,10 +525,7 @@ static int handle_video_stm_std_req(uint8_t rhport, uint8_t stage, tusb_control_ return VIDEO_UNKNOWN; case TUSB_REQ_SET_INTERFACE: if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; - itfnum = tu_u16_low(request->wIndex); - if (!_close_vs_itf(rhport, &_videod_itf[itf], itfnum)) - return VIDEO_UNKNOWN; - if (!_open_vs_itf(rhport, &_videod_itf[itf], itfnum, request->wValue)) + if (!_open_vs_itf(rhport, self, request->wValue)) return VIDEO_UNKNOWN; tud_control_status(rhport, request); return VIDEO_NO_ERROR; @@ -504,7 +538,7 @@ static int handle_video_stm_std_req(uint8_t rhport, uint8_t stage, tusb_control_ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf) { (void)rhport; - videod_interface_t *self = &_videod_itf[itf]; + videod_streaming_interface_t *self = &_videod_streaming_itf[itf]; /* 4.2.1 Interface Control Request */ switch (TU_U16_HIGH(request->wValue)) { case VIDEO_VS_CTL_STREAM_ERROR_CODE: @@ -512,9 +546,8 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r switch (request->bRequest) { case VIDEO_REQUEST_GET_CUR: if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; - TU_LOG2("Get\r\n"); /* TODO */ - if (!tud_control_xfer(rhport, request, &self->error_code[0], sizeof(uint8_t))) + if (!tud_control_xfer(rhport, request, &self->error_code, sizeof(uint8_t))) return VIDEO_UNKNOWN; return VIDEO_NO_ERROR; case VIDEO_REQUEST_GET_INFO: @@ -531,11 +564,11 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r case VIDEO_REQUEST_SET_CUR: if (stage == CONTROL_STAGE_SETUP) { TU_VERIFY(sizeof(video_probe_and_commit_control_t) == request->wLength, VIDEO_UNKNOWN); - if (!tud_control_xfer(rhport, request, self->ctl_buf, sizeof(video_probe_and_commit_control_t))) + if (!tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t))) return VIDEO_UNKNOWN; } else if (stage == CONTROL_STAGE_ACK) { if (tud_video_probe_set_cb) - return tud_video_probe_set_cb(itf, (video_probe_and_commit_control_t const*)self->ctl_buf); + return tud_video_probe_set_cb(itf, (video_probe_and_commit_control_t const*)self->ep_buf); } return VIDEO_NO_ERROR; case VIDEO_REQUEST_GET_CUR: @@ -579,11 +612,11 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r case VIDEO_REQUEST_SET_CUR: if (stage == CONTROL_STAGE_SETUP) { TU_VERIFY(sizeof(video_probe_and_commit_control_t) == request->wLength, VIDEO_UNKNOWN); - if (!tud_control_xfer(rhport, request, self->ctl_buf, sizeof(video_probe_and_commit_control_t))) + if (!tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t))) return VIDEO_UNKNOWN; } else if (stage == CONTROL_STAGE_ACK) { if (tud_video_commit_set_cb) - return tud_video_commit_set_cb(itf, (video_probe_and_commit_control_t const*)self->ctl_buf); + return tud_video_commit_set_cb(itf, (video_probe_and_commit_control_t const*)self->ep_buf); } return VIDEO_NO_ERROR; case VIDEO_REQUEST_GET_CUR: @@ -635,6 +668,15 @@ static int handle_video_stm_req(uint8_t rhport, uint8_t stage, tusb_control_requ //--------------------------------------------------------------------+ // APPLICATION API //--------------------------------------------------------------------+ +/* itf streaming interface number */ +bool tud_video_n_streaming(uint8_t itf) +{ + videod_streaming_interface_t *stm = &_videod_streaming_itf[itf]; + if (stm->desc.ep[0]) + return true; + return false; +} + bool tud_video_n_connected(uint8_t itf) { (void)itf; @@ -642,6 +684,21 @@ bool tud_video_n_connected(uint8_t itf) return tud_ready(); } +int tud_video_n_frame_xfer(uint8_t itf, uint32_t pts, void *buffer, size_t bufsize) +{ + (void)pts; + + if (!tud_video_n_streaming(itf)) + return false; + + videod_streaming_interface_t *stm = &_videod_streaming_itf[itf]; + stm->buffer = (uint8_t*)buffer; + stm->bufsize = bufsize; + TU_LOG1(" xfer %d\n", bufsize); + _payload_xfer_in(0, itf); + return 0; +} + //--------------------------------------------------------------------+ // READ API //--------------------------------------------------------------------+ @@ -686,25 +743,40 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin /* Find available interface */ videod_interface_t *self = NULL; - for (unsigned i = 0; i < CFG_TUD_VIDEO; ++i) { - if (!_videod_itf[i].beg) { - self = &_videod_itf[i]; - break; - } + unsigned itf; + for (itf = 0; itf < CFG_TUD_VIDEO; ++itf) { + if (_videod_itf[itf].beg) + continue; + self = &_videod_itf[itf]; + break; } - TU_ASSERT(self, 0); + TU_ASSERT(itf < CFG_TUD_VIDEO, 0); void const *end = (void const*)itf_desc + max_len; self->beg = itf_desc; self->len = max_len; /*------------- Video Control Interface -------------*/ - if (!_open_vc_itf(rhport, self, 0)) return 0; + if (!_open_vc_itf(rhport, self, 0)) + return 0; tusb_desc_vc_itf_t const *vc = _get_desc_vc(self); unsigned bInCollection = vc->ctl.bInCollection; /* Find the end of the video interface descriptor */ void const *cur = _next_desc_itf(itf_desc, end); for (unsigned i = 0; i < bInCollection; ++i) { + videod_streaming_interface_t *stm = NULL; + /* find free streaming interface handle */ + for (unsigned j = 0; j < TU_ARRAY_SIZE(_videod_streaming_itf); ++j) { + if (_videod_streaming_itf[i].desc.beg) + continue; + stm = &_videod_streaming_itf[i]; + self->stm[i] = j; + break; + } + TU_ASSERT(stm, 0); + stm->index_vc = itf; + stm->desc.beg = (uintptr_t)cur - (uintptr_t)itf_desc; cur = _next_desc_itf(cur, end); + stm->desc.end = (uintptr_t)cur - (uintptr_t)itf_desc; } self->len = (uintptr_t)cur - (uintptr_t)itf_desc; return (uintptr_t)cur - (uintptr_t)itf_desc; @@ -716,43 +788,64 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request) { int err; - int (*handle_video_req)(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf) = NULL; - uint8_t *error_code; if (request->bmRequestType_bit.recipient != TUSB_REQ_RCPT_INTERFACE) { return false; } unsigned itfnum = tu_u16_low(request->wIndex); - /* Identify which interface to use */ - int itf; - tusb_desc_vc_itf_t const *vc = NULL; - for (itf = 0; itf < CFG_TUD_VIDEO; ++itf) { - vc = _get_desc_vc(&_videod_itf[itf]); - if (itfnum == vc->std.bInterfaceNumber) { - handle_video_req = handle_video_ctl_req; - error_code = &_videod_itf[itf].error_code[0]; + + /* Identify which control interface to use */ + int itf = -1; + for (unsigned i = 0; i < CFG_TUD_VIDEO; ++i) { + void const *desc = _videod_itf[i].beg; + if (!desc) break; + if (itfnum == _desc_itfnum(desc)) { + itf = i; break; } - int i; - int bInCollection = vc->ctl.bInCollection; - for (i = 0; i < bInCollection && itfnum != vc->ctl.baInterfaceNr[i]; ++i) ; - if (i < bInCollection) { - handle_video_req = handle_video_stm_req; - error_code = &_videod_itf[itf].error_code[1 + i]; + } + if (itf >= 0) { + err = handle_video_ctl_req(rhport, stage, request, itf); + _videod_itf[itf].error_code = (uint8_t)err; + if (err) return false; + return true; + } + + /* Identify which streaming interface to use */ + for (unsigned i = 0; i < CFG_TUD_VIDEO_STREAMING; ++i) { + videod_streaming_interface_t *stm = &_videod_streaming_itf[i]; + if (!stm->desc.beg) return false; + void const *desc = _videod_itf[stm->index_vc].beg; + if (itfnum == _desc_itfnum(desc + stm->desc.beg)) { + itf = i; break; } } - if (itf == CFG_TUD_VIDEO) return false; - - err = handle_video_req(rhport, stage, request, itf); - *error_code = (uint8_t)err; - if (err) return false; - return true; + if (itf >= 0) { + err = handle_video_stm_req(rhport, stage, request, itf); + _videod_streaming_itf[itf].error_code = (uint8_t)err; + if (err) return false; + return true; + } + return false; } bool videod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) { - (void)rhport; (void)ep_addr; (void)result; (void)xferred_bytes; - return false; + (void)rhport; (void)result; (void)xferred_bytes; + + /* find streaming handle */ + unsigned i; + for (i = 0; i < CFG_TUD_VIDEO_STREAMING; ++i) { + videod_streaming_interface_t *stm = &_videod_streaming_itf[i]; + unsigned const ep_ofs = stm->desc.ep[0]; + if (!ep_ofs) continue; + void const *desc = _videod_itf[stm->index_vc].beg; + if (ep_addr == _desc_ep_addr(desc + ep_ofs)) + break; + } + TU_ASSERT(i < CFG_TUD_VIDEO_STREAMING); + _payload_xfer_in(rhport, i); + return true; } #endif diff --git a/src/class/video/video_device.h b/src/class/video/video_device.h index b4bdfc699..a1b13b9af 100644 --- a/src/class/video/video_device.h +++ b/src/class/video/video_device.h @@ -36,17 +36,23 @@ extern "C" { #endif //--------------------------------------------------------------------+ -// Application Callback API (weak is optional) +// Application API (Multiple Ports) +// CFG_TUD_VIDEO > 1 //--------------------------------------------------------------------+ +bool tud_video_n_streaming(uint8_t itf); -// Invoked when GET_INFO request received -TU_ATTR_WEAK bool tud_video_get_info_cb(uint8_t rhport, tusb_control_request_t const *request, uint8_t const *itf_desc); -// Invoked when GET_INFO request received -TU_ATTR_WEAK bool tud_video_set_cur_cb(uint8_t rhport, tusb_control_request_t const *request); -// Invoked when GET_CUR request received -TU_ATTR_WEAK bool tud_video_get_cur_cb(uint8_t rhport, tusb_control_request_t const *request); -/* @return video_error_code_t */ +int tud_video_n_frame_xfer(uint8_t itf, uint32_t pts, void *buffer, size_t bufsize); + +/*------------- Optional callbacks -------------*/ +TU_ATTR_WEAK int tud_video_frame_xfer_complete_cb(void); + +//--------------------------------------------------------------------+ +// Application Callback API (weak is optional) +//--------------------------------------------------------------------+ + +/* Invoked when SET POWER_MODE request received to + * @return video_error_code_t */ TU_ATTR_WEAK int tud_video_power_mode_cb(unsigned itf, uint8_t power_mod); /* @return video_error_code_t */ -- cgit v1.3.1 From cd3f6eac2f31ccd21aae7fd9a323fe416c77409b Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Sat, 25 Sep 2021 13:08:00 +0900 Subject: Fix streaming payload handling --- src/class/video/video.h | 1 + src/class/video/video_device.c | 50 ++++++++++++++++++++++++++++-------------- 2 files changed, 34 insertions(+), 17 deletions(-) diff --git a/src/class/video/video.h b/src/class/video/video.h index 444433e86..c62706e5b 100644 --- a/src/class/video/video.h +++ b/src/class/video/video.h @@ -202,6 +202,7 @@ typedef struct TU_ATTR_PACKED { uint8_t EndOfFrame: 1; uint8_t PresentationTime: 1; uint8_t SourceClockReference: 1; + uint8_t PayloadSpecific: 1; uint8_t StillImage: 1; uint8_t Error: 1; uint8_t EndOfHeader: 1; diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index dc6cf376c..acec7a992 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -65,7 +65,6 @@ typedef struct TU_ATTR_PACKED { uint8_t bEntityId; } tusb_desc_cs_video_entity_itf_t; - typedef struct TU_ATTR_PACKED { void const *beg; /* The head of the first video control interface descriptor */ uint16_t length; /* Byte length of the video control interface descriptors */ @@ -356,9 +355,14 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, unsi TU_ASSERT(cur < end); TU_ASSERT(usbd_edpt_open(rhport, (tusb_desc_endpoint_t const *)cur)); stm->desc.ep[i] = cur - desc; - stm->max_payload_transfer_size = CFG_TUD_VIDEO_EP_BUFSIZE; + stm->max_payload_transfer_size = def_stm_settings.dwMaxPayloadTransferSize; TU_LOG1(" open EP%02x\n", _desc_ep_addr(cur)); } + /* initialize payload header */ + tusb_video_payload_header_t *hdr = (tusb_video_payload_header_t*)stm->ep_buf; + hdr->bHeaderLength = sizeof(*hdr); + hdr->bmHeaderInfo = 0; + return true; } @@ -379,24 +383,22 @@ static int _payload_xfer_in(uint8_t rhport, uint8_t itf) TU_VERIFY( usbd_edpt_claim(rhport, ep_addr), 0); /* prepare a payload */ - unsigned mps = stm->max_payload_transfer_size; uint32_t remaining = stm->bufsize - stm->offset; - uint32_t data_len = remaining < (mps - 2) ? remaining: (mps - 2); - stm->ep_buf[0] = 1; - stm->ep_buf[1] = 0; - memcpy(&stm->ep_buf[2], stm->buffer + stm->offset, data_len); + unsigned hdr_len = stm->ep_buf[0]; + unsigned pkt_len = stm->max_payload_transfer_size; + if (hdr_len + remaining < pkt_len) { + pkt_len = hdr_len + remaining; + } + uint32_t data_len = pkt_len - hdr_len; + memcpy(&stm->ep_buf[hdr_len], stm->buffer + stm->offset, data_len); stm->offset += data_len; remaining -= data_len; - TU_LOG2(" %d\n", data_len, remaining); - TU_ASSERT( usbd_edpt_xfer(rhport, ep_addr, stm->ep_buf, 2 + data_len), 0 ); - if (!remaining) { - stm->buffer = NULL; - stm->bufsize = 0; - stm->offset = 0; - if (tud_video_frame_xfer_complete_cb) - tud_video_frame_xfer_complete_cb(); + tusb_video_payload_header_t *hdr = (tusb_video_payload_header_t*)stm->ep_buf; + hdr->EndOfFrame = 1; } + TU_LOG2(" %d\n", data_len, remaining); + TU_ASSERT( usbd_edpt_xfer(rhport, ep_addr, stm->ep_buf, hdr_len + data_len), 0 ); return data_len; } @@ -691,7 +693,12 @@ int tud_video_n_frame_xfer(uint8_t itf, uint32_t pts, void *buffer, size_t bufsi if (!tud_video_n_streaming(itf)) return false; + /* update the packet header */ videod_streaming_interface_t *stm = &_videod_streaming_itf[itf]; + tusb_video_payload_header_t *hdr = (tusb_video_payload_header_t*)stm->ep_buf; + hdr->FrameID ^= 1; + hdr->EndOfFrame = 0; + stm->buffer = (uint8_t*)buffer; stm->bufsize = bufsize; TU_LOG1(" xfer %d\n", bufsize); @@ -835,8 +842,9 @@ bool videod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3 /* find streaming handle */ unsigned i; + videod_streaming_interface_t *stm; for (i = 0; i < CFG_TUD_VIDEO_STREAMING; ++i) { - videod_streaming_interface_t *stm = &_videod_streaming_itf[i]; + stm = &_videod_streaming_itf[i]; unsigned const ep_ofs = stm->desc.ep[0]; if (!ep_ofs) continue; void const *desc = _videod_itf[stm->index_vc].beg; @@ -844,7 +852,15 @@ bool videod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3 break; } TU_ASSERT(i < CFG_TUD_VIDEO_STREAMING); - _payload_xfer_in(rhport, i); + if (stm->offset < stm->bufsize) { + _payload_xfer_in(rhport, i); + } else { + stm->buffer = NULL; + stm->bufsize = 0; + stm->offset = 0; + if (tud_video_frame_xfer_complete_cb) + tud_video_frame_xfer_complete_cb(); + } return true; } -- cgit v1.3.1 From a978828c3abdf864f9806cec6aa73a36f9209cc3 Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Sat, 25 Sep 2021 17:09:05 +0900 Subject: Add green plain --- examples/device/video_capture/src/images.h | 4614 ++++++++++++++++++++++++++++ examples/device/video_capture/src/main.c | 10 +- 2 files changed, 4621 insertions(+), 3 deletions(-) create mode 100644 examples/device/video_capture/src/images.h diff --git a/examples/device/video_capture/src/images.h b/examples/device/video_capture/src/images.h new file mode 100644 index 000000000..2f4c42ad4 --- /dev/null +++ b/examples/device/video_capture/src/images.h @@ -0,0 +1,4614 @@ +static const unsigned char black_128x96_yuv[] = { + 0x00, 0x00, 0x00, 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0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80 +}; +static const unsigned char white_128x96_yuv[] = { + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 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0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, + 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, + 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, + 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, + 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, + 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a +}; diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c index 1921da4bf..ce4272639 100644 --- a/examples/device/video_capture/src/main.c +++ b/examples/device/video_capture/src/main.c @@ -107,7 +107,7 @@ void tud_resume_cb(void) // USB Video //--------------------------------------------------------------------+ static unsigned char const *frames[] = { - black_128x96_yuv, white_128x96_yuv + black_128x96_yuv, white_128x96_yuv, green_128x96_yuv }; uint8_t current_frame = 0; @@ -122,7 +122,9 @@ void video_task(void) if (!already_sent) { tud_video_n_frame_xfer(0, 0, (void*)frames[current_frame], 128 * 96 * 12/8); - current_frame ^= 1; + ++current_frame; + if (current_frame == sizeof(frames)/sizeof(frames[0])) + current_frame = 0; already_sent = 1; } @@ -143,7 +145,9 @@ int tud_video_frame_xfer_complete_cb(void) { /* prepare tx */ tud_video_n_frame_xfer(0, 0, (void*)frames[current_frame], 128 * 96 * 12/8); - current_frame ^= 1; + ++current_frame; + if (current_frame == sizeof(frames)/sizeof(frames[0])) + current_frame = 0; return 0; } -- cgit v1.3.1 From d88cc23ca5eced51167edad00ea43c86038ee481 Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Sat, 25 Sep 2021 16:59:17 +0900 Subject: Refactor packet handling --- examples/device/video_capture/src/main.c | 4 +- src/class/video/video_device.c | 173 +++++++++++++++---------------- src/class/video/video_device.h | 6 +- 3 files changed, 89 insertions(+), 94 deletions(-) diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c index ce4272639..4ca0e5d90 100644 --- a/examples/device/video_capture/src/main.c +++ b/examples/device/video_capture/src/main.c @@ -141,10 +141,10 @@ void video_task(void) } } -int tud_video_frame_xfer_complete_cb(void) +int tud_video_frame_xfer_complete_cb(unsigned itf) { /* prepare tx */ - tud_video_n_frame_xfer(0, 0, (void*)frames[current_frame], 128 * 96 * 12/8); + tud_video_n_frame_xfer(itf, 0, (void*)frames[current_frame], 128 * 96 * 12/8); ++current_frame; if (current_frame == sizeof(frames)/sizeof(frames[0])) current_frame = 0; diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index acec7a992..344c4e0f9 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -191,7 +191,7 @@ static void const* _find_desc(void const *beg, void const *end, uint8_t target) static void const* _next_desc_itf(void const *beg, void const *end) { void const *cur = beg; - unsigned itfnum = ((tusb_desc_interface_t const*)cur)->bInterfaceNumber; + uint_fast8_t itfnum = ((tusb_desc_interface_t const*)cur)->bInterfaceNumber; while ((cur < end) && (itfnum == ((tusb_desc_interface_t const*)cur)->bInterfaceNumber)) { cur = _find_desc(tu_desc_next(cur), end, TUSB_DESC_INTERFACE); @@ -208,7 +208,7 @@ static void const* _next_desc_itf(void const *beg, void const *end) * * @return The pointer for interface descriptor. * @retval end did not found interface descriptor */ -static void const* _find_desc_itf(void const *beg, void const *end, unsigned itfnum, unsigned altnum) +static void const* _find_desc_itf(void const *beg, void const *end, uint_fast8_t itfnum, uint_fast8_t altnum) { for (void const *cur = beg; cur < end; cur = _find_desc(cur, end, TUSB_DESC_INTERFACE)) { tusb_desc_interface_t const *itf = (tusb_desc_interface_t const *)cur; @@ -244,7 +244,7 @@ static void const* _find_desc_ep(void const *beg, void const *end) * * @return The pointer for interface descriptor. * @retval end did not found interface descriptor */ -static void const* _find_desc_entity(tusb_desc_vc_itf_t const *vc, unsigned entityid) +static void const* _find_desc_entity(tusb_desc_vc_itf_t const *vc, uint_fast8_t entityid) { void const *beg = (void const*)vc; void const *end = beg + vc->std.bLength + vc->ctl.wTotalLength; @@ -286,7 +286,7 @@ static bool _close_vc_itf(uint8_t rhport, videod_interface_t *self) * * @param[in,out] self The context. * @param[in] altnum The target alternate setting number. */ -static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, unsigned altnum) +static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t altnum) { TU_LOG2(" open VC %d\r\n", altnum); void const *beg = self->beg; @@ -325,17 +325,17 @@ static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, unsigned altn * * @param[in,out] self The context. * @param[in] altnum The target alternate setting number. */ -static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, unsigned altnum) +static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint_fast8_t altnum) { - unsigned i; + uint_fast8_t i; TU_LOG1(" reopen VS %d\r\n", altnum); void const *desc = _videod_itf[stm->index_vc].beg; /* Close endpoints of previous settings. */ for (i = 0; i < TU_ARRAY_SIZE(stm->desc.ep); ++i) { - unsigned ofs_ep = stm->desc.ep[i]; + uint_fast16_t ofs_ep = stm->desc.ep[i]; if (!ofs_ep) break; - unsigned ep_adr = _desc_ep_addr(desc + ofs_ep); + uint_fast8_t ep_adr = _desc_ep_addr(desc + ofs_ep); usbd_edpt_close(rhport, ep_adr); stm->desc.ep[i] = 0; TU_LOG1(" close EP%02x\n", ep_adr); @@ -346,7 +346,7 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, unsi void const *end = desc + stm->desc.end; void const *cur = _find_desc_itf(beg, end, _desc_itfnum(beg), altnum); TU_VERIFY(cur < end); - unsigned numeps = ((tusb_desc_interface_t const *)cur)->bNumEndpoints; + uint_fast8_t numeps = ((tusb_desc_interface_t const *)cur)->bNumEndpoints; TU_ASSERT(numeps <= TU_ARRAY_SIZE(stm->desc.ep)); stm->desc.cur = cur - desc; /* Save the offset of the new settings */ /* Open endpoints of the new settings. */ @@ -366,30 +366,15 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, unsi return true; } -static int _payload_xfer_in(uint8_t rhport, uint8_t itf) +static uint_fast16_t _prepair_in_payload(videod_streaming_interface_t *stm) { - videod_streaming_interface_t *stm = &_videod_streaming_itf[itf]; - void const *desc = _videod_itf[stm->index_vc].beg; - unsigned ep_addr = 0; - for (unsigned i = 0; i < CFG_TUD_VIDEO_STREAMING; ++i) { - unsigned ofs_ep = stm->desc.ep[i]; - if (!ofs_ep) continue; - ep_addr = _desc_ep_addr(desc + ofs_ep); - if (tu_edpt_dir(ep_addr)) - break; - } - TU_ASSERT(ep_addr, 0); - /* Claim the endpoint */ - TU_VERIFY( usbd_edpt_claim(rhport, ep_addr), 0); - - /* prepare a payload */ - uint32_t remaining = stm->bufsize - stm->offset; - unsigned hdr_len = stm->ep_buf[0]; - unsigned pkt_len = stm->max_payload_transfer_size; + uint_fast16_t remaining = stm->bufsize - stm->offset; + uint_fast16_t hdr_len = stm->ep_buf[0]; + uint_fast16_t pkt_len = stm->max_payload_transfer_size; if (hdr_len + remaining < pkt_len) { pkt_len = hdr_len + remaining; } - uint32_t data_len = pkt_len - hdr_len; + uint_fast16_t data_len = pkt_len - hdr_len; memcpy(&stm->ep_buf[hdr_len], stm->buffer + stm->offset, data_len); stm->offset += data_len; remaining -= data_len; @@ -397,13 +382,11 @@ static int _payload_xfer_in(uint8_t rhport, uint8_t itf) tusb_video_payload_header_t *hdr = (tusb_video_payload_header_t*)stm->ep_buf; hdr->EndOfFrame = 1; } - TU_LOG2(" %d\n", data_len, remaining); - TU_ASSERT( usbd_edpt_xfer(rhport, ep_addr, stm->ep_buf, hdr_len + data_len), 0 ); - return data_len; + return hdr_len + data_len; } /** Handle a standard request to the video control interface. */ -static int handle_video_ctl_std_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf) +static int handle_video_ctl_std_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, uint_fast8_t itf) { switch (request->bRequest) { case TUSB_REQ_GET_INTERFACE: @@ -431,7 +414,7 @@ static int handle_video_ctl_std_req(uint8_t rhport, uint8_t stage, tusb_control_ } } -static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf) +static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, uint_fast8_t itf) { videod_interface_t *self = &_videod_itf[itf]; /* 4.2.1 Interface Control Request */ @@ -491,9 +474,9 @@ static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r return VIDEO_INVALID_REQUEST; } -static int handle_video_ctl_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf) +static int handle_video_ctl_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, uint_fast8_t itf) { - unsigned entity_id; + uint_fast8_t entity_id; switch (request->bmRequestType_bit.type) { case TUSB_REQ_TYPE_STANDARD: return handle_video_ctl_std_req(rhport, stage, request, itf); @@ -511,7 +494,7 @@ static int handle_video_ctl_req(uint8_t rhport, uint8_t stage, tusb_control_requ } } -static int handle_video_stm_std_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf) +static int handle_video_stm_std_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, uint_fast8_t itf) { videod_streaming_interface_t *self = &_videod_streaming_itf[itf]; switch (request->bRequest) { @@ -537,7 +520,7 @@ static int handle_video_stm_std_req(uint8_t rhport, uint8_t stage, tusb_control_ } } -static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf) +static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, uint_fast8_t itf) { (void)rhport; videod_streaming_interface_t *self = &_videod_streaming_itf[itf]; @@ -652,7 +635,7 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r return VIDEO_INVALID_REQUEST; } -static int handle_video_stm_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf) +static int handle_video_stm_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, uint_fast8_t itf) { switch (request->bmRequestType_bit.type) { case TUSB_REQ_TYPE_STANDARD: @@ -670,6 +653,15 @@ static int handle_video_stm_req(uint8_t rhport, uint8_t stage, tusb_control_requ //--------------------------------------------------------------------+ // APPLICATION API //--------------------------------------------------------------------+ + +/* itf control interface number */ +bool tud_video_n_connected(uint8_t itf) +{ + (void)itf; + // DTR (bit 0) active is considered as connected + return tud_ready(); +} + /* itf streaming interface number */ bool tud_video_n_streaming(uint8_t itf) { @@ -679,41 +671,43 @@ bool tud_video_n_streaming(uint8_t itf) return false; } -bool tud_video_n_connected(uint8_t itf) -{ - (void)itf; - // DTR (bit 0) active is considered as connected - return tud_ready(); -} - -int tud_video_n_frame_xfer(uint8_t itf, uint32_t pts, void *buffer, size_t bufsize) +bool tud_video_n_frame_xfer(uint8_t itf, uint32_t pts, void *buffer, size_t bufsize) { (void)pts; + if (!buffer || !buffer) + return false; if (!tud_video_n_streaming(itf)) return false; + videod_streaming_interface_t *stm = &_videod_streaming_itf[itf]; + if (stm->buffer) + return false; + /* find EP address */ + void const *desc = _videod_itf[stm->index_vc].beg; + uint_fast8_t ep_addr = 0; + for (uint_fast8_t i = 0; i < CFG_TUD_VIDEO_STREAMING; ++i) { + uint_fast16_t ofs_ep = stm->desc.ep[i]; + if (!ofs_ep) continue; + ep_addr = _desc_ep_addr(desc + ofs_ep); + break; + } + if (!ep_addr) + return false; + + TU_VERIFY( usbd_edpt_claim(0, ep_addr)); /* update the packet header */ - videod_streaming_interface_t *stm = &_videod_streaming_itf[itf]; tusb_video_payload_header_t *hdr = (tusb_video_payload_header_t*)stm->ep_buf; hdr->FrameID ^= 1; hdr->EndOfFrame = 0; - - stm->buffer = (uint8_t*)buffer; - stm->bufsize = bufsize; - TU_LOG1(" xfer %d\n", bufsize); - _payload_xfer_in(0, itf); - return 0; + /* update the packet data */ + stm->buffer = (uint8_t*)buffer; + stm->bufsize = bufsize; + uint_fast16_t pkt_len = _prepair_in_payload(stm); + TU_ASSERT( usbd_edpt_xfer(0, ep_addr, stm->ep_buf, pkt_len), 0); + return true; } -//--------------------------------------------------------------------+ -// READ API -//--------------------------------------------------------------------+ - -//--------------------------------------------------------------------+ -// WRITE API -//--------------------------------------------------------------------+ - //--------------------------------------------------------------------+ // USBD Driver API //--------------------------------------------------------------------+ @@ -750,7 +744,7 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin /* Find available interface */ videod_interface_t *self = NULL; - unsigned itf; + uint_fast8_t itf; for (itf = 0; itf < CFG_TUD_VIDEO; ++itf) { if (_videod_itf[itf].beg) continue; @@ -766,13 +760,13 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin if (!_open_vc_itf(rhport, self, 0)) return 0; tusb_desc_vc_itf_t const *vc = _get_desc_vc(self); - unsigned bInCollection = vc->ctl.bInCollection; + uint_fast8_t bInCollection = vc->ctl.bInCollection; /* Find the end of the video interface descriptor */ void const *cur = _next_desc_itf(itf_desc, end); - for (unsigned i = 0; i < bInCollection; ++i) { + for (uint_fast8_t i = 0; i < bInCollection; ++i) { videod_streaming_interface_t *stm = NULL; /* find free streaming interface handle */ - for (unsigned j = 0; j < TU_ARRAY_SIZE(_videod_streaming_itf); ++j) { + for (uint_fast8_t j = 0; j < TU_ARRAY_SIZE(_videod_streaming_itf); ++j) { if (_videod_streaming_itf[i].desc.beg) continue; stm = &_videod_streaming_itf[i]; @@ -798,19 +792,17 @@ bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_ if (request->bmRequestType_bit.recipient != TUSB_REQ_RCPT_INTERFACE) { return false; } - unsigned itfnum = tu_u16_low(request->wIndex); + uint_fast8_t itfnum = tu_u16_low(request->wIndex); /* Identify which control interface to use */ - int itf = -1; - for (unsigned i = 0; i < CFG_TUD_VIDEO; ++i) { - void const *desc = _videod_itf[i].beg; - if (!desc) break; - if (itfnum == _desc_itfnum(desc)) { - itf = i; + uint_fast8_t itf; + for (itf = 0; itf < CFG_TUD_VIDEO; ++itf) { + void const *desc = _videod_itf[itf].beg; + if (!desc) continue; + if (itfnum == _desc_itfnum(desc)) break; - } } - if (itf >= 0) { + if (itf < CFG_TUD_VIDEO) { err = handle_video_ctl_req(rhport, stage, request, itf); _videod_itf[itf].error_code = (uint8_t)err; if (err) return false; @@ -818,16 +810,14 @@ bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_ } /* Identify which streaming interface to use */ - for (unsigned i = 0; i < CFG_TUD_VIDEO_STREAMING; ++i) { - videod_streaming_interface_t *stm = &_videod_streaming_itf[i]; - if (!stm->desc.beg) return false; + for (itf = 0; itf < CFG_TUD_VIDEO_STREAMING; ++itf) { + videod_streaming_interface_t *stm = &_videod_streaming_itf[itf]; + if (!stm->desc.beg) continue; void const *desc = _videod_itf[stm->index_vc].beg; - if (itfnum == _desc_itfnum(desc + stm->desc.beg)) { - itf = i; + if (itfnum == _desc_itfnum(desc + stm->desc.beg)) break; - } } - if (itf >= 0) { + if (itf < CFG_TUD_VIDEO_STREAMING) { err = handle_video_stm_req(rhport, stage, request, itf); _videod_streaming_itf[itf].error_code = (uint8_t)err; if (err) return false; @@ -838,28 +828,31 @@ bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_ bool videod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) { - (void)rhport; (void)result; (void)xferred_bytes; + (void)result; (void)xferred_bytes; /* find streaming handle */ - unsigned i; + uint_fast8_t itf; videod_streaming_interface_t *stm; - for (i = 0; i < CFG_TUD_VIDEO_STREAMING; ++i) { - stm = &_videod_streaming_itf[i]; - unsigned const ep_ofs = stm->desc.ep[0]; + for (itf = 0; itf < CFG_TUD_VIDEO_STREAMING; ++itf) { + stm = &_videod_streaming_itf[itf]; + uint_fast16_t const ep_ofs = stm->desc.ep[0]; if (!ep_ofs) continue; void const *desc = _videod_itf[stm->index_vc].beg; if (ep_addr == _desc_ep_addr(desc + ep_ofs)) break; } - TU_ASSERT(i < CFG_TUD_VIDEO_STREAMING); + TU_ASSERT(itf < CFG_TUD_VIDEO_STREAMING); if (stm->offset < stm->bufsize) { - _payload_xfer_in(rhport, i); + /* Claim the endpoint */ + TU_VERIFY( usbd_edpt_claim(rhport, ep_addr), 0); + uint_fast16_t pkt_len = _prepair_in_payload(stm); + TU_ASSERT( usbd_edpt_xfer(rhport, ep_addr, stm->ep_buf, pkt_len), 0); } else { stm->buffer = NULL; stm->bufsize = 0; stm->offset = 0; if (tud_video_frame_xfer_complete_cb) - tud_video_frame_xfer_complete_cb(); + tud_video_frame_xfer_complete_cb(itf); } return true; } diff --git a/src/class/video/video_device.h b/src/class/video/video_device.h index a1b13b9af..acf4c4d2b 100644 --- a/src/class/video/video_device.h +++ b/src/class/video/video_device.h @@ -42,10 +42,12 @@ extern "C" { bool tud_video_n_streaming(uint8_t itf); -int tud_video_n_frame_xfer(uint8_t itf, uint32_t pts, void *buffer, size_t bufsize); +/* itf instance number of streaming interface */ +bool tud_video_n_frame_xfer(uint8_t itf, uint32_t pts, void *buffer, size_t bufsize); /*------------- Optional callbacks -------------*/ -TU_ATTR_WEAK int tud_video_frame_xfer_complete_cb(void); +/* itf instance number of streaming interface */ +TU_ATTR_WEAK int tud_video_frame_xfer_complete_cb(unsigned itf); //--------------------------------------------------------------------+ // Application Callback API (weak is optional) -- cgit v1.3.1 From 0d6496886cae22f33408bd126925b5d6c4908d65 Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Sat, 25 Sep 2021 20:49:04 +0900 Subject: Change frame buffer management --- examples/device/video_capture/src/main.c | 25 +++++++++++++++---------- src/class/video/video_device.c | 4 ++-- 2 files changed, 17 insertions(+), 12 deletions(-) diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c index 4ca0e5d90..4a124c537 100644 --- a/examples/device/video_capture/src/main.c +++ b/examples/device/video_capture/src/main.c @@ -109,30 +109,35 @@ void tud_resume_cb(void) static unsigned char const *frames[] = { black_128x96_yuv, white_128x96_yuv, green_128x96_yuv }; -uint8_t current_frame = 0; +static unsigned current_frame = 0; +static unsigned tx_busy = 0; void video_task(void) { static unsigned start_ms = 0; - static unsigned interval_ms = 66; + static unsigned interval_ms = 100; static unsigned frame_num = 0; static unsigned already_sent = 0; - if (!tud_video_n_streaming(0)) return; + if (!tud_video_n_streaming(0)) { + already_sent = 0; + current_frame = 0; + return; + } if (!already_sent) { - tud_video_n_frame_xfer(0, 0, (void*)frames[current_frame], 128 * 96 * 12/8); - ++current_frame; - if (current_frame == sizeof(frames)/sizeof(frames[0])) - current_frame = 0; already_sent = 1; + start_ms = board_millis(); + tud_video_n_frame_xfer(0, 0, (void*)frames[current_frame], 128 * 96 * 12/8); } unsigned cur = board_millis(); if (cur - start_ms < interval_ms) return; // not enough time + if (tx_busy) return; start_ms += interval_ms; - /* flip buffer */ + tud_video_n_frame_xfer(0, 0, (void*)frames[current_frame], 128 * 96 * 12/8); + ++frame_num; if (frame_num % 3) { interval_ms = 66; @@ -143,8 +148,8 @@ void video_task(void) int tud_video_frame_xfer_complete_cb(unsigned itf) { - /* prepare tx */ - tud_video_n_frame_xfer(itf, 0, (void*)frames[current_frame], 128 * 96 * 12/8); + tx_busy = 0; + /* flip buffer */ ++current_frame; if (current_frame == sizeof(frames)/sizeof(frames[0])) current_frame = 0; diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index 344c4e0f9..ad7057d30 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -128,9 +128,9 @@ static video_probe_and_commit_control_t const def_stm_settings = { .wCompWindowSize = 1, /* Maybe it is match to GOP size */ .wDelay = 240, /* milliseconds */ .dwMaxVideoFrameSize = 128 * 96 * 12 / 8, - .dwMaxPayloadTransferSize = 256, /* Maybe it is the maximum packet size under this settings */ + .dwMaxPayloadTransferSize = ((128 * 96 * 12 / 8 * 10) + 999) / 1000 + 2, .dwClockFrequency = 27000000, /* same as MPEG-2 system time clock */ - .bmFramingInfo = 0, + .bmFramingInfo = 0x3, .bPreferedVersion = 1, .bMinVersion = 1, .bMaxVersion = 1, -- cgit v1.3.1 From f7bbdea0b8f360d1fcf2f835211ed5c26e0240ea Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Sun, 26 Sep 2021 17:15:00 +0900 Subject: Refactor application API parameters --- examples/device/video_capture/src/main.c | 22 +-- examples/device/video_capture/src/tusb_config.h | 12 ++ .../device/video_capture/src/usb_descriptors.c | 2 +- src/class/video/video_device.c | 163 +++++++++++---------- src/class/video/video_device.h | 20 ++- 5 files changed, 116 insertions(+), 103 deletions(-) diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c index 4a124c537..abc97a377 100644 --- a/examples/device/video_capture/src/main.c +++ b/examples/device/video_capture/src/main.c @@ -35,9 +35,6 @@ // MACRO CONSTANT TYPEDEF PROTYPES //--------------------------------------------------------------------+ -#define FRAME_WIDTH 128 -#define FRAME_HEIGHT 96 - /* Blink pattern * - 250 ms : device not mounted * - 1000 ms : device mounted @@ -115,11 +112,10 @@ static unsigned tx_busy = 0; void video_task(void) { static unsigned start_ms = 0; - static unsigned interval_ms = 100; - static unsigned frame_num = 0; + static unsigned interval_ms = 1000 / FRAME_RATE; static unsigned already_sent = 0; - if (!tud_video_n_streaming(0)) { + if (!tud_video_n_streaming(0, 0)) { already_sent = 0; current_frame = 0; return; @@ -128,7 +124,7 @@ void video_task(void) if (!already_sent) { already_sent = 1; start_ms = board_millis(); - tud_video_n_frame_xfer(0, 0, (void*)frames[current_frame], 128 * 96 * 12/8); + tud_video_n_frame_xfer(0, 0, (void*)frames[current_frame], FRAME_WIDTH * FRAME_HEIGHT * 12/8); } unsigned cur = board_millis(); @@ -136,18 +132,12 @@ void video_task(void) if (tx_busy) return; start_ms += interval_ms; - tud_video_n_frame_xfer(0, 0, (void*)frames[current_frame], 128 * 96 * 12/8); - - ++frame_num; - if (frame_num % 3) { - interval_ms = 66; - } else { - interval_ms = 67; - } + tud_video_n_frame_xfer(0, 0, (void*)frames[current_frame], FRAME_WIDTH * FRAME_HEIGHT * 12/8); } -int tud_video_frame_xfer_complete_cb(unsigned itf) +int tud_video_frame_xfer_complete_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx) { + (void)ctl_idx; (void)stm_idx; tx_busy = 0; /* flip buffer */ ++current_frame; diff --git a/examples/device/video_capture/src/tusb_config.h b/examples/device/video_capture/src/tusb_config.h index 3958b85b6..fb194c55a 100644 --- a/examples/device/video_capture/src/tusb_config.h +++ b/examples/device/video_capture/src/tusb_config.h @@ -90,8 +90,10 @@ #define CFG_TUD_ENDPOINT0_SIZE 64 #endif +// video streaming endpoint size #define CFG_TUD_VIDEO_EP_BUFSIZE 256 +// The number of video streaming interfaces #define CFG_TUD_VIDEO_STREAMING 1 //------------- CLASS -------------// @@ -100,9 +102,19 @@ #define CFG_TUD_HID 0 #define CFG_TUD_MIDI 0 #define CFG_TUD_AUDIO 0 +// The number of video control interfaces #define CFG_TUD_VIDEO 1 #define CFG_TUD_VENDOR 0 + +//-------------------------------------------------------------------- +// APPLICATION CONFIGURATION +//-------------------------------------------------------------------- +#define FRAME_WIDTH 128 +#define FRAME_HEIGHT 96 +#define FRAME_RATE 10 + + #ifdef __cplusplus } #endif diff --git a/examples/device/video_capture/src/usb_descriptors.c b/examples/device/video_capture/src/usb_descriptors.c index 096ac4373..a9fa2c043 100644 --- a/examples/device/video_capture/src/usb_descriptors.c +++ b/examples/device/video_capture/src/usb_descriptors.c @@ -104,7 +104,7 @@ uint8_t const desc_fs_configuration[] = // Config number, interface count, string index, total length, attribute, power in mA TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0, 500), // IAD for Video Control - TUD_VIDEO_CAPTURE_DESCRIPTOR(4, EPNUM_VIDEO_IN, 128, 96, 10, 256) + TUD_VIDEO_CAPTURE_DESCRIPTOR(4, EPNUM_VIDEO_IN, FRAME_WIDTH, FRAME_HEIGHT, FRAME_RATE, CFG_TUD_VIDEO_EP_BUFSIZE) }; // Invoked when received GET CONFIGURATION DESCRIPTOR diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index ad7057d30..d01bbb146 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -38,11 +38,6 @@ //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF //--------------------------------------------------------------------+ -typedef struct { - uint8_t num; - uint8_t alt; -} itf_setting_t; - typedef struct { tusb_desc_interface_t std; tusb_desc_cs_video_ctl_itf_hdr_t ctl; @@ -65,49 +60,41 @@ typedef struct TU_ATTR_PACKED { uint8_t bEntityId; } tusb_desc_cs_video_entity_itf_t; +/* video streaming interface */ typedef struct TU_ATTR_PACKED { - void const *beg; /* The head of the first video control interface descriptor */ - uint16_t length; /* Byte length of the video control interface descriptors */ - uint16_t offset; /* offset bytes for the current video control interface descripter */ - uint8_t error_code; /* error code set by previous transaction */ - uint8_t power_mode; /* current power mode */ -} videod_control_interface_t; - -typedef struct TU_ATTR_PACKED { - uint8_t index_vc; /* index of video control interface */ - uint8_t error_code;/* error code for video control/streaming interface. 0:control 1:streaming 2:streaming */ + uint8_t index_vc; /* index of bound video control interface */ + uint8_t index_vs; /* index from the video control interface */ + uint8_t error_code;/* error code */ struct { uint16_t beg; /* Offset of the beggining of video streaming interface descriptor */ uint16_t end; /* Offset of the end of video streaming interface descriptor */ uint16_t cur; /* Offset of the current settings */ - uint16_t ep[2]; /* Offset of endpoint descriptors */ + uint16_t ep[2]; /* Offset of endpoint descriptors. 0: streaming, 1: still capture */ } desc; - uint8_t *buffer; /* frame buffer. assume linear buffer. no support for stride access */ - uint32_t bufsize; /* frame buffer */ + uint32_t bufsize; /* frame buffer size */ uint32_t offset; /* offset for the next payload transfer */ uint32_t max_payload_transfer_size; - uint8_t ep_buf[CFG_TUD_VIDEO_EP_BUFSIZE]; + /*------------- From this point, data is not cleared by bus reset -------------*/ + CFG_TUSB_MEM_ALIGN uint8_t ep_buf[CFG_TUD_VIDEO_EP_BUFSIZE]; /* EP transfer buffer for streaming */ } videod_streaming_interface_t; +/* video control interface */ typedef struct TU_ATTR_PACKED { void const *beg; /* The head of the first video control interface descriptor */ uint16_t len; /* Byte length of the descriptors */ uint16_t cur; /* offset for current video control interface */ uint8_t stm[CFG_TUD_VIDEO_STREAMING]; /* Indices of streaming interface */ - uint8_t error_code; /* error code for video control/streaming interface. */ + uint8_t error_code; /* error code */ uint8_t power_mode; /*------------- From this point, data is not cleared by bus reset -------------*/ - - // Endpoint Transfer buffer - // CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUD_CDC_EP_BUFSIZE]; - // CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUD_CDC_EP_BUFSIZE]; - uint8_t ctl_buf[64]; + // + // CFG_TUSB_MEM_ALIGN uint8_t ctl_buf[64]; /* EP transfer buffer for control */ } videod_interface_t; -#define ITF_MEM_RESET_SIZE offsetof(videod_interface_t, ctl_buf) +#define ITF_STM_MEM_RESET_SIZE offsetof(videod_streaming_interface_t, ep_buf) //--------------------------------------------------------------------+ // INTERNAL OBJECT & FUNCTION DECLARATION @@ -121,14 +108,14 @@ static video_probe_and_commit_control_t const def_stm_settings = { .bmHint = 0, .bFormatIndex = 1, .bFrameIndex = 1, - .dwFrameInterval = (10000000/10), + .dwFrameInterval = (10000000/FRAME_RATE), .wKeyFrameRate = 1, .wPFrameRate = 0, .wCompQuality = 1, /* 1 to 10000 */ .wCompWindowSize = 1, /* Maybe it is match to GOP size */ .wDelay = 240, /* milliseconds */ - .dwMaxVideoFrameSize = 128 * 96 * 12 / 8, - .dwMaxPayloadTransferSize = ((128 * 96 * 12 / 8 * 10) + 999) / 1000 + 2, + .dwMaxVideoFrameSize = FRAME_WIDTH * FRAME_HEIGHT * 12 / 8, + .dwMaxPayloadTransferSize = ((FRAME_WIDTH * FRAME_HEIGHT * 12 / 8 * 10) + 999) / 1000 + 2, .dwClockFrequency = 27000000, /* same as MPEG-2 system time clock */ .bmFramingInfo = 0x3, .bPreferedVersion = 1, @@ -142,22 +129,33 @@ static video_probe_and_commit_control_t const def_stm_settings = { .bmLayoutPerStream = 0 }; +/* return bInterfaceNumber */ static inline uint8_t _desc_itfnum(void const *desc) { return ((uint8_t const*)desc)[2]; } +/* return bEndpointAddress */ static inline uint8_t _desc_ep_addr(void const *desc) { return ((uint8_t const*)desc)[2]; } +static videod_streaming_interface_t* _get_instance_streaming(uint_fast8_t ctl_idx, uint_fast8_t stm_idx) +{ + videod_interface_t *ctl = &_videod_itf[ctl_idx]; + if (!ctl->beg) return NULL; + videod_streaming_interface_t *stm = &_videod_streaming_itf[ctl->stm[stm_idx]]; + if (!stm->desc.beg) return NULL; + return stm; +} + static tusb_desc_vc_itf_t const* _get_desc_vc(videod_interface_t const *self) { return (tusb_desc_vc_itf_t const *)(self->beg + self->cur); } -static tusb_desc_vs_itf_t const *_get_desc_vs(videod_streaming_interface_t const *self) +static tusb_desc_vs_itf_t const* _get_desc_vs(videod_streaming_interface_t const *self) { if (!self->desc.cur) return NULL; void const *desc = _videod_itf[self->index_vc].beg; @@ -230,7 +228,7 @@ static void const* _find_desc_itf(void const *beg, void const *end, uint_fast8_t static void const* _find_desc_ep(void const *beg, void const *end) { for (void const *cur = beg; cur < end; cur = tu_desc_next(cur)) { - uint8_t desc_type = tu_desc_type(cur); + uint_fast8_t desc_type = tu_desc_type(cur); if (TUSB_DESC_ENDPOINT == desc_type) return cur; if (TUSB_DESC_INTERFACE == desc_type) break; } @@ -429,7 +427,8 @@ static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r if (!tud_control_xfer(rhport, request, &self->power_mode, sizeof(self->power_mode))) return VIDEO_UNKNOWN; } else if (stage == CONTROL_STAGE_ACK) { - if (tud_video_power_mode_cb) return tud_video_power_mode_cb(itf, self->power_mode); + if (tud_video_power_mode_cb) + return tud_video_power_mode_cb(itf, self->power_mode); } return VIDEO_NO_ERROR; case VIDEO_REQUEST_GET_CUR: @@ -553,7 +552,8 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r return VIDEO_UNKNOWN; } else if (stage == CONTROL_STAGE_ACK) { if (tud_video_probe_set_cb) - return tud_video_probe_set_cb(itf, (video_probe_and_commit_control_t const*)self->ep_buf); + return tud_video_probe_set_cb(self->index_vc, self->index_vs, + (video_probe_and_commit_control_t const*)self->ep_buf); } return VIDEO_NO_ERROR; case VIDEO_REQUEST_GET_CUR: @@ -601,7 +601,8 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r return VIDEO_UNKNOWN; } else if (stage == CONTROL_STAGE_ACK) { if (tud_video_commit_set_cb) - return tud_video_commit_set_cb(itf, (video_probe_and_commit_control_t const*)self->ep_buf); + return tud_video_commit_set_cb(self->index_vc, self->index_vs, + (video_probe_and_commit_control_t const*)self->ep_buf); } return VIDEO_NO_ERROR; case VIDEO_REQUEST_GET_CUR: @@ -654,33 +655,36 @@ static int handle_video_stm_req(uint8_t rhport, uint8_t stage, tusb_control_requ // APPLICATION API //--------------------------------------------------------------------+ -/* itf control interface number */ -bool tud_video_n_connected(uint8_t itf) +/* ctl_idx instance number of video control interface */ +bool tud_video_n_connected(uint_fast8_t ctl_idx) { - (void)itf; - // DTR (bit 0) active is considered as connected - return tud_ready(); -} - -/* itf streaming interface number */ -bool tud_video_n_streaming(uint8_t itf) -{ - videod_streaming_interface_t *stm = &_videod_streaming_itf[itf]; - if (stm->desc.ep[0]) + TU_ASSERT(ctl_idx < CFG_TUD_VIDEO); + videod_streaming_interface_t *stm = _get_instance_streaming(ctl_idx, 0); + if (stm) return true; return false; } -bool tud_video_n_frame_xfer(uint8_t itf, uint32_t pts, void *buffer, size_t bufsize) +/* ctl_idx instance number of video control interface + * stm_idx index number of streaming interface as per video control */ +bool tud_video_n_streaming(uint_fast8_t ctl_idx, uint_fast8_t stm_idx) { - (void)pts; + TU_ASSERT(ctl_idx < CFG_TUD_VIDEO); + TU_ASSERT(stm_idx < CFG_TUD_VIDEO_STREAMING); + videod_streaming_interface_t *stm = _get_instance_streaming(ctl_idx, stm_idx); + if (!stm || !stm->desc.ep[0]) + return false; + return true; +} +bool tud_video_n_frame_xfer(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, void *buffer, size_t bufsize) +{ + TU_ASSERT(ctl_idx < CFG_TUD_VIDEO); + TU_ASSERT(stm_idx < CFG_TUD_VIDEO_STREAMING); if (!buffer || !buffer) return false; - if (!tud_video_n_streaming(itf)) - return false; - videod_streaming_interface_t *stm = &_videod_streaming_itf[itf]; - if (stm->buffer) + videod_streaming_interface_t *stm = _get_instance_streaming(ctl_idx, stm_idx); + if (!stm || !stm->desc.ep[0] || stm->buffer) return false; /* find EP address */ @@ -713,26 +717,26 @@ bool tud_video_n_frame_xfer(uint8_t itf, uint32_t pts, void *buffer, size_t bufs //--------------------------------------------------------------------+ void videod_init(void) { - tu_memclr(_videod_itf, sizeof(_videod_itf)); - - for (unsigned i = 0; i < CFG_TUD_VIDEO; ++i) - { - // videod_interface_t* p_video = &_videod_itf[i]; - - // TODO + for (uint_fast8_t i = 0; i < CFG_TUD_VIDEO; ++i) { + videod_interface_t* ctl = &_videod_itf[i]; + tu_memclr(ctl, sizeof(*ctl)); + } + for (uint_fast8_t i = 0; i < CFG_TUD_VIDEO_STREAMING; ++i) { + videod_streaming_interface_t *stm = &_videod_streaming_itf[i]; + tu_memclr(stm, ITF_STM_MEM_RESET_SIZE); } } void videod_reset(uint8_t rhport) { (void) rhport; - - for (unsigned i = 0; i < CFG_TUD_VIDEO; ++i) - { - videod_interface_t* p_video = &_videod_itf[i]; - - // TODO - tu_memclr(p_video, ITF_MEM_RESET_SIZE); + for (uint_fast8_t i = 0; i < CFG_TUD_VIDEO; ++i) { + videod_interface_t* ctl = &_videod_itf[i]; + tu_memclr(ctl, sizeof(*ctl)); + } + for (uint_fast8_t i = 0; i < CFG_TUD_VIDEO_STREAMING; ++i) { + videod_streaming_interface_t *stm = &_videod_streaming_itf[i]; + tu_memclr(stm, ITF_STM_MEM_RESET_SIZE); } } @@ -744,14 +748,14 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin /* Find available interface */ videod_interface_t *self = NULL; - uint_fast8_t itf; - for (itf = 0; itf < CFG_TUD_VIDEO; ++itf) { - if (_videod_itf[itf].beg) + uint_fast8_t ctl_idx; + for (ctl_idx = 0; ctl_idx < CFG_TUD_VIDEO; ++ctl_idx) { + if (_videod_itf[ctl_idx].beg) continue; - self = &_videod_itf[itf]; + self = &_videod_itf[ctl_idx]; break; } - TU_ASSERT(itf < CFG_TUD_VIDEO, 0); + TU_ASSERT(ctl_idx < CFG_TUD_VIDEO, 0); void const *end = (void const*)itf_desc + max_len; self->beg = itf_desc; @@ -760,21 +764,22 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin if (!_open_vc_itf(rhport, self, 0)) return 0; tusb_desc_vc_itf_t const *vc = _get_desc_vc(self); - uint_fast8_t bInCollection = vc->ctl.bInCollection; + uint_fast8_t bInCollection = vc->ctl.bInCollection; /* Find the end of the video interface descriptor */ void const *cur = _next_desc_itf(itf_desc, end); - for (uint_fast8_t i = 0; i < bInCollection; ++i) { + for (uint_fast8_t stm_idx = 0; stm_idx < bInCollection; ++stm_idx) { videod_streaming_interface_t *stm = NULL; /* find free streaming interface handle */ - for (uint_fast8_t j = 0; j < TU_ARRAY_SIZE(_videod_streaming_itf); ++j) { + for (uint_fast8_t i = 0; i < CFG_TUD_VIDEO_STREAMING; ++i) { if (_videod_streaming_itf[i].desc.beg) continue; stm = &_videod_streaming_itf[i]; - self->stm[i] = j; + self->stm[stm_idx] = i; break; } TU_ASSERT(stm, 0); - stm->index_vc = itf; + stm->index_vc = ctl_idx; + stm->index_vs = stm_idx; stm->desc.beg = (uintptr_t)cur - (uintptr_t)itf_desc; cur = _next_desc_itf(cur, end); stm->desc.end = (uintptr_t)cur - (uintptr_t)itf_desc; @@ -832,12 +837,14 @@ bool videod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3 /* find streaming handle */ uint_fast8_t itf; + videod_interface_t *ctl; videod_streaming_interface_t *stm; for (itf = 0; itf < CFG_TUD_VIDEO_STREAMING; ++itf) { stm = &_videod_streaming_itf[itf]; uint_fast16_t const ep_ofs = stm->desc.ep[0]; if (!ep_ofs) continue; - void const *desc = _videod_itf[stm->index_vc].beg; + ctl = &_videod_itf[stm->index_vc]; + void const *desc = ctl->beg; if (ep_addr == _desc_ep_addr(desc + ep_ofs)) break; } @@ -852,7 +859,7 @@ bool videod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3 stm->bufsize = 0; stm->offset = 0; if (tud_video_frame_xfer_complete_cb) - tud_video_frame_xfer_complete_cb(itf); + tud_video_frame_xfer_complete_cb(stm->index_vc, stm->index_vs); } return true; } diff --git a/src/class/video/video_device.h b/src/class/video/video_device.h index acf4c4d2b..e6f53fed8 100644 --- a/src/class/video/video_device.h +++ b/src/class/video/video_device.h @@ -39,15 +39,19 @@ extern "C" { // Application API (Multiple Ports) // CFG_TUD_VIDEO > 1 //--------------------------------------------------------------------+ -bool tud_video_n_streaming(uint8_t itf); +/* ctl_idx instance number of control interface + * stm_idx instance number of streaming interface */ +bool tud_video_n_streaming(uint_fast8_t ctl_idx, uint_fast8_t stm_idx); -/* itf instance number of streaming interface */ -bool tud_video_n_frame_xfer(uint8_t itf, uint32_t pts, void *buffer, size_t bufsize); +/* ctl_idx instance number of control interface + * stm_idx instance number of streaming interface */ +bool tud_video_n_frame_xfer(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, void *buffer, size_t bufsize); /*------------- Optional callbacks -------------*/ -/* itf instance number of streaming interface */ -TU_ATTR_WEAK int tud_video_frame_xfer_complete_cb(unsigned itf); +/* ctl_idx instance number of control interface + * stm_idx instance number of streaming interface */ +TU_ATTR_WEAK int tud_video_frame_xfer_complete_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx); //--------------------------------------------------------------------+ // Application Callback API (weak is optional) @@ -55,13 +59,13 @@ TU_ATTR_WEAK int tud_video_frame_xfer_complete_cb(unsigned itf); /* Invoked when SET POWER_MODE request received to * @return video_error_code_t */ -TU_ATTR_WEAK int tud_video_power_mode_cb(unsigned itf, uint8_t power_mod); +TU_ATTR_WEAK int tud_video_power_mode_cb(uint_fast8_t ctl_idx, uint8_t power_mod); /* @return video_error_code_t */ -TU_ATTR_WEAK int tud_video_probe_set_cb(unsigned itf, video_probe_and_commit_control_t const *settings); +TU_ATTR_WEAK int tud_video_probe_set_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, video_probe_and_commit_control_t const *settings); /* @return video_error_code_t */ -TU_ATTR_WEAK int tud_video_commit_set_cb(unsigned itf, video_probe_and_commit_control_t const *settings); +TU_ATTR_WEAK int tud_video_commit_set_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, video_probe_and_commit_control_t const *settings); //--------------------------------------------------------------------+ // INTERNAL USBD-CLASS DRIVER API //--------------------------------------------------------------------+ -- cgit v1.3.1 From a15c3543296098ab292ef0c815000c6eb2c3a9fb Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Sun, 26 Sep 2021 17:44:36 +0900 Subject: Fix typo --- src/class/video/video_device.c | 47 +++++++++++++++++++++++------------------- 1 file changed, 26 insertions(+), 21 deletions(-) diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index d01bbb146..5b5d0b430 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -129,18 +129,32 @@ static video_probe_and_commit_control_t const def_stm_settings = { .bmLayoutPerStream = 0 }; -/* return bInterfaceNumber */ +/** Get interface number from the interface descriptor + * + * @param[in] desc interface descriptor + * + * @return bInterfaceNumber */ static inline uint8_t _desc_itfnum(void const *desc) { return ((uint8_t const*)desc)[2]; } -/* return bEndpointAddress */ +/** Get endpoint address from the endpoint descriptor + * + * @param[in] desc endpoint descriptor + * + * @return bEndpointAddress */ static inline uint8_t _desc_ep_addr(void const *desc) { return ((uint8_t const*)desc)[2]; } +/** Get instance of streaming interface + * + * @param[in] ctl_idx instance number of video control + * @param[in] stm_idx index number of streaming interface + * + * @return instance */ static videod_streaming_interface_t* _get_instance_streaming(uint_fast8_t ctl_idx, uint_fast8_t stm_idx) { videod_interface_t *ctl = &_videod_itf[ctl_idx]; @@ -286,16 +300,16 @@ static bool _close_vc_itf(uint8_t rhport, videod_interface_t *self) * @param[in] altnum The target alternate setting number. */ static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t altnum) { - TU_LOG2(" open VC %d\r\n", altnum); + TU_LOG2(" open VC %d\n", altnum); void const *beg = self->beg; void const *end = beg + self->len; /* The first descriptor is a video control interface descriptor. */ void const *cur = _find_desc_itf(beg, end, _desc_itfnum(beg), altnum); - TU_LOG2(" cur %ld\r\n", cur - beg); + TU_LOG2(" cur %ld\n", cur - beg); TU_VERIFY(cur < end); tusb_desc_vc_itf_t const *vc = (tusb_desc_vc_itf_t const *)cur; - TU_LOG2(" bInCollection %d\r\n", vc->ctl.bInCollection); + TU_LOG2(" bInCollection %d\n", vc->ctl.bInCollection); /* Support for up to 2 streaming interfaces only. */ TU_ASSERT(vc->ctl.bInCollection <= CFG_TUD_VIDEO_STREAMING); @@ -303,7 +317,7 @@ static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t end = cur + vc->std.bLength + vc->ctl.wTotalLength; /* Advance to the next descriptor after the class-specific VC interface header descriptor. */ cur += vc->std.bLength + vc->ctl.bLength; - TU_LOG2(" bNumEndpoints %d\r\n", vc->std.bNumEndpoints); + TU_LOG2(" bNumEndpoints %d\n", vc->std.bNumEndpoints); /* Open the notification endpoint if it exist. */ if (vc->std.bNumEndpoints) { /* Support for 1 endpoint only. */ @@ -326,7 +340,7 @@ static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint_fast8_t altnum) { uint_fast8_t i; - TU_LOG1(" reopen VS %d\r\n", altnum); + TU_LOG2(" reopen VS %d\n", altnum); void const *desc = _videod_itf[stm->index_vc].beg; /* Close endpoints of previous settings. */ @@ -336,7 +350,7 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint uint_fast8_t ep_adr = _desc_ep_addr(desc + ofs_ep); usbd_edpt_close(rhport, ep_adr); stm->desc.ep[i] = 0; - TU_LOG1(" close EP%02x\n", ep_adr); + TU_LOG2(" close EP%02x\n", ep_adr); } /* Find a alternate interface */ @@ -354,7 +368,7 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint TU_ASSERT(usbd_edpt_open(rhport, (tusb_desc_endpoint_t const *)cur)); stm->desc.ep[i] = cur - desc; stm->max_payload_transfer_size = def_stm_settings.dwMaxPayloadTransferSize; - TU_LOG1(" open EP%02x\n", _desc_ep_addr(cur)); + TU_LOG2(" open EP%02x\n", _desc_ep_addr(cur)); } /* initialize payload header */ tusb_video_payload_header_t *hdr = (tusb_video_payload_header_t*)stm->ep_buf; @@ -364,7 +378,7 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint return true; } -static uint_fast16_t _prepair_in_payload(videod_streaming_interface_t *stm) +static uint_fast16_t _prepare_in_payload(videod_streaming_interface_t *stm) { uint_fast16_t remaining = stm->bufsize - stm->offset; uint_fast16_t hdr_len = stm->ep_buf[0]; @@ -418,11 +432,9 @@ static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r /* 4.2.1 Interface Control Request */ switch (TU_U16_HIGH(request->wValue)) { case VIDEO_VC_CTL_VIDEO_POWER_MODE: - TU_LOG2(" Power Mode "); switch (request->bRequest) { case VIDEO_REQUEST_SET_CUR: if (stage == CONTROL_STAGE_SETUP) { - TU_LOG2("Set\r\n"); TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN); if (!tud_control_xfer(rhport, request, &self->power_mode, sizeof(self->power_mode))) return VIDEO_UNKNOWN; @@ -433,14 +445,12 @@ static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r return VIDEO_NO_ERROR; case VIDEO_REQUEST_GET_CUR: if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; - TU_LOG2("Get\r\n"); TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN); if (!tud_control_xfer(rhport, request, &self->power_mode, sizeof(self->power_mode))) return VIDEO_UNKNOWN; return VIDEO_NO_ERROR; case VIDEO_REQUEST_GET_INFO: if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; - TU_LOG2("GetInfo\r\n"); TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN); if (!tud_control_xfer(rhport, request, (uint8_t*)&_cap_get_set, sizeof(_cap_get_set))) return VIDEO_UNKNOWN; @@ -449,17 +459,14 @@ static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r } break; case VIDEO_VC_CTL_REQUEST_ERROR_CODE: - TU_LOG2(" Error Code"); switch (request->bRequest) { case VIDEO_REQUEST_GET_CUR: if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; - TU_LOG2(" Get\r\n"); if (!tud_control_xfer(rhport, request, &self->error_code, sizeof(uint8_t))) return VIDEO_UNKNOWN; return VIDEO_NO_ERROR; case VIDEO_REQUEST_GET_INFO: if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; - TU_LOG2(" GetInfo\r\n"); if (tud_control_xfer(rhport, request, (uint8_t*)&_cap_get, sizeof(_cap_get))) return VIDEO_UNKNOWN; return VIDEO_NO_ERROR; @@ -526,7 +533,6 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r /* 4.2.1 Interface Control Request */ switch (TU_U16_HIGH(request->wValue)) { case VIDEO_VS_CTL_STREAM_ERROR_CODE: - TU_LOG2(" Error Code "); switch (request->bRequest) { case VIDEO_REQUEST_GET_CUR: if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; @@ -536,7 +542,6 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r return VIDEO_NO_ERROR; case VIDEO_REQUEST_GET_INFO: if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; - TU_LOG2("GetInfo\r\n"); if (tud_control_xfer(rhport, request, (uint8_t*)&_cap_get, sizeof(_cap_get))) return VIDEO_UNKNOWN; return VIDEO_NO_ERROR; @@ -707,7 +712,7 @@ bool tud_video_n_frame_xfer(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, void *bu /* update the packet data */ stm->buffer = (uint8_t*)buffer; stm->bufsize = bufsize; - uint_fast16_t pkt_len = _prepair_in_payload(stm); + uint_fast16_t pkt_len = _prepare_in_payload(stm); TU_ASSERT( usbd_edpt_xfer(0, ep_addr, stm->ep_buf, pkt_len), 0); return true; } @@ -852,7 +857,7 @@ bool videod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3 if (stm->offset < stm->bufsize) { /* Claim the endpoint */ TU_VERIFY( usbd_edpt_claim(rhport, ep_addr), 0); - uint_fast16_t pkt_len = _prepair_in_payload(stm); + uint_fast16_t pkt_len = _prepare_in_payload(stm); TU_ASSERT( usbd_edpt_xfer(rhport, ep_addr, stm->ep_buf, pkt_len), 0); } else { stm->buffer = NULL; -- cgit v1.3.1 From 319db9573c679e45a663326fbd4baa240a3da0ea Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Sun, 26 Sep 2021 18:33:30 +0900 Subject: Change video frames to project logo --- examples/device/video_capture/src/images.h | 8594 +++++++++++++++++++--------- examples/device/video_capture/src/main.c | 4 +- 2 files changed, 5838 insertions(+), 2760 deletions(-) diff --git a/examples/device/video_capture/src/images.h b/examples/device/video_capture/src/images.h index 2f4c42ad4..a55353d91 100644 --- a/examples/device/video_capture/src/images.h +++ b/examples/device/video_capture/src/images.h @@ -1,1028 +1,1149 @@ -static const unsigned char black_128x96_yuv[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +static const unsigned char white_128x96_yuv[] = { + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 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0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, @@ -1413,45 +1534,1462 @@ static const unsigned char black_128x96_yuv[] = { 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80 +}; +static const unsigned char t_128x96_yuv[] = { + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 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0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, @@ -1536,51 +3074,395 @@ static const unsigned char black_128x96_yuv[] = { 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80 }; -static const unsigned char white_128x96_yuv[] = { +static const unsigned char ti_128x96_yuv[] = { + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 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0x1a, 0x1a, 0x12, 0x53, 0xff, 0xff, 0xff, 0xf4, + 0x02, 0x1b, 0x20, 0x1b, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1b, + 0x1f, 0x1a, 0x16, 0xde, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xb6, 0x0e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x17, 0x57, 0xff, 0xff, 0xff, 0xf5, 0x08, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1e, 0x1b, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xb3, 0x06, + 0x18, 0x18, 0x1c, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x1d, 0x18, 0x18, 0x18, 0x18, 0x10, 0x52, + 0xff, 0xff, 0xff, 0xf5, 0x08, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x1e, 0x1b, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc7, 0x43, 0x50, 0x54, 0x33, 0x1c, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x1d, 0x2e, 0x55, 0x50, 0x50, 0x50, 0x4a, 0x7c, 0xff, 0xff, 0xff, 0xf5, + 0x08, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x1e, 0x1b, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x83, 0x14, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x16, 0x6d, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x08, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1e, 0x1b, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -1588,18 +3470,31 @@ static const unsigned char white_128x96_yuv[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf5, 0x08, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x1e, 0x1b, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, + 0x08, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x1e, 0x1b, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x08, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1e, 0x1b, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -1607,18 +3502,31 @@ static const unsigned char white_128x96_yuv[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf5, 0x08, 0x20, 0x1e, 0x17, 0x14, 0x17, 0x1e, 0x1f, + 0x1a, 0x11, 0x10, 0x16, 0x1e, 0x1e, 0x1b, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, + 0x08, 0x1d, 0x18, 0x5d, 0x84, 0x59, 0x19, 0x13, 0x39, 0xa2, 0xa7, 0x6c, + 0x16, 0x1b, 0x1b, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x07, 0x0c, 0xce, 0xff, + 0xff, 0xff, 0xc1, 0x40, 0xff, 0xff, 0xff, 0xff, 0xb1, 0x14, 0x1a, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -1626,18 +3534,31 @@ static const unsigned char white_128x96_yuv[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf5, 0x01, 0x5a, 0xff, 0xff, 0xc3, 0xd8, 0xff, 0xfb, + 0xff, 0xae, 0xa8, 0xff, 0xff, 0x53, 0x13, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, + 0x00, 0xac, 0xff, 0x72, 0x00, 0x00, 0xb8, 0xff, 0x82, 0x00, 0x00, 0x7f, + 0xff, 0xa3, 0x0c, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x00, 0xbb, 0xff, 0xd4, + 0xc8, 0xc6, 0xdf, 0xff, 0xd7, 0xc8, 0xc8, 0xd5, 0xff, 0xc1, 0x09, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -1645,18 +3566,31 @@ static const unsigned char white_128x96_yuv[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf5, 0x00, 0xc4, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xca, 0x09, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, + 0x02, 0x5b, 0x79, 0x75, 0x75, 0x75, 0x75, 0x75, 0x75, 0x71, 0x70, 0x72, + 0x79, 0x5c, 0x14, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x07, 0x0f, 0x04, 0x0a, + 0x14, 0x14, 0x14, 0x0f, 0x05, 0x2b, 0x34, 0x24, 0x05, 0x15, 0x1b, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -1664,18 +3598,31 @@ static const unsigned char white_128x96_yuv[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf5, 0x01, 0x68, 0xb8, 0x83, 0x19, 0x1f, 0x14, 0x2c, + 0xbb, 0xff, 0xff, 0xfb, 0x96, 0x14, 0x1a, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf4, + 0x00, 0xcc, 0xff, 0x6c, 0x12, 0x11, 0x4d, 0xf9, 0xff, 0xff, 0xf9, 0xff, + 0xff, 0x73, 0x10, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf4, 0x00, 0xd4, 0xff, 0x79, + 0x05, 0x70, 0xff, 0xff, 0xff, 0x76, 0x10, 0x94, 0xff, 0xc2, 0x09, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -1683,18 +3630,31 @@ static const unsigned char white_128x96_yuv[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf5, 0x00, 0x91, 0xff, 0xff, 0xfc, 0xff, 0xff, 0xfb, + 0x39, 0x0e, 0x12, 0x62, 0xff, 0xc5, 0x09, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, + 0x06, 0x0d, 0xc3, 0xff, 0xff, 0xff, 0xbf, 0x1f, 0x16, 0x20, 0x0c, 0xe5, + 0xff, 0x7e, 0x0f, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x83, 0x13, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x07, 0x18, 0x05, 0x1b, + 0x34, 0x1c, 0x06, 0x12, 0x16, 0x16, 0x16, 0x12, 0x11, 0x16, 0x1b, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -1702,18 +3662,31 @@ static const unsigned char white_128x96_yuv[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x94, 0x11, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf5, 0x03, 0x52, 0x6c, 0x66, 0x64, 0x66, 0x69, 0x69, + 0x69, 0x6a, 0x5b, 0x3e, 0x0d, 0x1a, 0x1b, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0x0c, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x18, 0x53, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, + 0x00, 0xc9, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xcb, 0x20, 0x18, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, 0x0d, 0x1e, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1c, 0x2c, 0xfd, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x00, 0x9e, 0xdf, 0xd8, + 0xd8, 0xd8, 0xd8, 0xd8, 0xd8, 0xd7, 0xdf, 0xff, 0xff, 0x99, 0x0e, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -1721,18 +3694,31 @@ static const unsigned char white_128x96_yuv[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x55, 0x16, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x1f, 0x17, 0x4e, 0xc7, 0xeb, 0xed, 0xc2, 0xc6, + 0xff, 0xff, 0xff, 0xf5, 0x07, 0x0b, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, + 0x01, 0x01, 0x03, 0x5b, 0xff, 0xd8, 0x14, 0xde, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd8, + 0x06, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x1f, 0x18, 0x0d, 0x09, 0x09, 0x04, 0x4a, 0xff, 0xff, 0xff, 0xf5, + 0x03, 0x55, 0x71, 0x6d, 0x6d, 0x6d, 0x6d, 0x6d, 0x6d, 0x6d, 0x64, 0xb5, + 0xff, 0xcc, 0x0f, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, 0x09, 0x1e, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x17, 0x57, 0xff, 0xff, 0xff, 0xf5, 0x00, 0xc7, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x50, 0x13, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -1740,6 +3726,10 @@ static const unsigned char white_128x96_yuv[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x9c, 0x08, 0x10, 0x1b, 0x1f, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x17, 0x56, + 0xff, 0xff, 0xff, 0xf5, 0x00, 0xb3, 0xfe, 0xf6, 0xf6, 0xf6, 0xf6, 0xf6, + 0xf6, 0xf7, 0xd7, 0xb6, 0x41, 0x11, 0x1b, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -1747,6 +3737,10 @@ static const unsigned char white_128x96_yuv[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x93, 0x2f, 0x06, 0x0c, 0x0f, 0x12, 0x15, 0x15, 0x14, + 0x13, 0x12, 0x12, 0x10, 0x0d, 0x09, 0x01, 0x55, 0xff, 0xff, 0xff, 0xf3, + 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x07, 0x0b, 0x0a, 0xdc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -1754,6 +3748,9 @@ static const unsigned char white_128x96_yuv[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xef, 0xc7, 0xa8, 0x8a, 0x71, 0x72, 0x79, 0x81, 0x89, 0x91, 0xa1, + 0xc2, 0xe3, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0xb4, 0xbc, 0xbc, 0xbc, + 0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xbb, 0xba, 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -2102,6 +4099,637 @@ static const unsigned char white_128x96_yuv[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 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0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80 +}; +static const unsigned char tin_128x96_yuv[] = { + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -2220,18 +4848,31 @@ static const unsigned char white_128x96_yuv[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xa0, 0x54, 0x5c, 0x5c, 0x5c, 0x5c, 0x5c, 0x5c, 0x5c, 0x5c, + 0x5c, 0x5c, 0x5c, 0x5c, 0x55, 0x90, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x4c, 0x58, 0x56, 0x56, 0x56, 0x56, + 0x56, 0x56, 0x56, 0x58, 0x4f, 0xd9, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x75, 0x0b, + 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, + 0x0d, 0x60, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf1, 0x00, 0x36, 0x3a, 0x39, 0x39, 0x39, 0x39, 0x39, 0x3a, 0x34, + 0x01, 0xc9, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0x00, 0xf8, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xeb, 0x03, 0xcb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -2239,18 +4880,31 @@ static const unsigned char white_128x96_yuv[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0x00, 0xe6, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xda, 0x02, 0xcb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf3, 0x00, 0xed, 0xce, 0xad, 0xed, 0xff, 0xf1, 0xad, 0xcb, 0xe0, + 0x02, 0xcb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0x00, 0xfa, + 0x43, 0x00, 0xba, 0xff, 0xc9, 0x00, 0x38, 0xeb, 0x02, 0xcb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -2258,111 +4912,387 @@ static const unsigned char white_128x96_yuv[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0x00, 0xec, 0xdd, 0xc4, 0xf2, 0xff, + 0xf5, 0xc3, 0xdc, 0xdf, 0x02, 0xcb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf3, 0x00, 0xe6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xda, + 0x02, 0xcb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x84, 0x14, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x16, 0x6e, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0xf8, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xeb, 0x03, 0xdb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xde, 0xca, 0xbb, 0xa4, 0x9a, 0xa7, 0xc7, 0xeb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc0, 0x31, + 0x3f, 0x42, 0x2c, 0x1d, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x1d, 0x29, 0x43, 0x3f, 0x3f, 0x3f, 0x38, 0x6f, + 0xff, 0xff, 0xff, 0xf5, 0x2d, 0x3f, 0x16, 0x3d, 0x40, 0x3f, 0x3f, 0x3f, + 0x3f, 0x3f, 0x40, 0x3b, 0x19, 0x37, 0x3e, 0xe3, 0xff, 0xff, 0xff, 0xff, + 0x35, 0x3e, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, + 0x3f, 0x36, 0x86, 0xff, 0xff, 0xff, 0xce, 0x73, 0x36, 0x1d, 0x12, 0x0d, + 0x10, 0x10, 0x0f, 0x10, 0x25, 0x3d, 0x7e, 0xdb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xb4, 0x08, 0x1a, 0x1a, 0x1d, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x1d, 0x1a, 0x1a, 0x1a, 0x1a, 0x12, 0x53, 0xff, 0xff, 0xff, 0xf4, + 0x02, 0x1b, 0x20, 0x1b, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1b, + 0x1f, 0x1a, 0x16, 0xde, 0xff, 0xff, 0xff, 0xff, 0x0c, 0x18, 0x1a, 0x1a, + 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x0f, 0x6e, 0xff, + 0xe6, 0x55, 0x11, 0x13, 0x1a, 0x1d, 0x1f, 0x20, 0x20, 0x20, 0x20, 0x1f, + 0x1d, 0x1a, 0x12, 0x13, 0x6e, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xb6, 0x0e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x17, 0x57, 0xff, 0xff, 0xff, 0xf5, 0x08, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1e, 0x1b, 0xdf, + 0xff, 0xff, 0xff, 0xff, 0x12, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x15, 0x7d, 0xdd, 0x10, 0x15, 0x1e, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1e, + 0x0e, 0x45, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xb3, 0x06, + 0x18, 0x18, 0x1c, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x1d, 0x18, 0x18, 0x18, 0x18, 0x10, 0x52, + 0xff, 0xff, 0xff, 0xf5, 0x08, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x1e, 0x1b, 0xdf, 0xff, 0xff, 0xff, 0xff, + 0x12, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x1a, 0x57, 0x20, 0x1b, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1f, 0x0f, 0x5c, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 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0x66, 0x69, 0x69, + 0x69, 0x6a, 0x5b, 0x3e, 0x0d, 0x1a, 0x1b, 0xdf, 0xff, 0xff, 0xff, 0xff, + 0x12, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x1f, 0x15, 0xcb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd0, 0x0b, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1b, + 0x33, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0x0c, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x18, 0x53, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, + 0x00, 0xc9, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xcb, 0x20, 0x18, 0xdf, 0xff, 0xff, 0xff, 0xff, 0x12, 0x1e, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1f, 0x15, 0xcb, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xd0, 0x0b, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1b, 0x33, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, 0x0d, 0x1e, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1c, 0x2c, 0xfd, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x00, 0x9e, 0xdf, 0xd8, + 0xd8, 0xd8, 0xd8, 0xd8, 0xd8, 0xd7, 0xdf, 0xff, 0xff, 0x99, 0x0e, 0xdf, + 0xff, 0xff, 0xff, 0xff, 0x12, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x1f, 0x15, 0xcb, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xd0, 0x0b, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x1b, 0x33, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 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0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x1f, 0x18, 0x0d, 0x09, 0x09, 0x04, 0x4a, 0xff, 0xff, 0xff, 0xf5, + 0x03, 0x55, 0x71, 0x6d, 0x6d, 0x6d, 0x6d, 0x6d, 0x6d, 0x6d, 0x64, 0xb5, + 0xff, 0xcc, 0x0f, 0xdf, 0xff, 0xff, 0xff, 0xff, 0x12, 0x1e, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1f, 0x15, 0xcb, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xd0, 0x0b, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1b, 0x33, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, 0x09, 0x1e, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x17, 0x57, 0xff, 0xff, 0xff, 0xf5, 0x00, 0xc7, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x50, 0x13, 0xdf, + 0xff, 0xff, 0xff, 0xff, 0x12, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x1f, 0x15, 0xcb, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xd0, 0x0b, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x1b, 0x33, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x9c, 0x08, 0x10, 0x1b, 0x1f, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x17, 0x56, + 0xff, 0xff, 0xff, 0xf5, 0x00, 0xb3, 0xfe, 0xf6, 0xf6, 0xf6, 0xf6, 0xf6, + 0xf6, 0xf7, 0xd7, 0xb6, 0x41, 0x11, 0x1b, 0xdf, 0xff, 0xff, 0xff, 0xff, + 0x12, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x1f, 0x15, 0xcb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd0, 0x0b, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1b, + 0x33, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x93, 0x2f, 0x06, 0x0c, 0x0f, 0x12, 0x15, 0x15, 0x14, + 0x13, 0x12, 0x12, 0x10, 0x0d, 0x09, 0x01, 0x55, 0xff, 0xff, 0xff, 0xf3, + 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x07, 0x0b, 0x0a, 0xdc, 0xff, 0xff, 0xff, 0xff, 0x01, 0x0c, 0x0d, 0x0d, + 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0c, 0x03, 0xc6, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xcb, 0x00, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, + 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x09, 0x23, 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xef, 0xc7, 0xa8, 0x8a, 0x71, 0x72, 0x79, 0x81, 0x89, 0x91, 0xa1, + 0xc2, 0xe3, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0xb4, 0xbc, 0xbc, 0xbc, + 0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xbb, 0xba, 0xf6, + 0xff, 0xff, 0xff, 0xff, 0xb7, 0xbb, 0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xbc, + 0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xb7, 0xef, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf1, 0xb5, 0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xbc, + 0xbc, 0xbc, 0xbc, 0xba, 0xc1, 0xfd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -2561,6 +5491,408 @@ static const unsigned char white_128x96_yuv[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 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0x81, 0x81, 0x81, 0x81, 0x81, + 0x81, 0x81, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x81, 0x81, + 0x80, 0x80, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x80, 0x80, + 0x80, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x81, + 0x81, 0x81, 0x81, 0x81, 0x81, 0x80, 0x80, 0x7f, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x81, 0x80, 0x80, 0x80, 0x80, 0x81, 0x81, 0x81, 0x81, 0x81, + 0x81, 0x80, 0x80, 0x80, 0x80, 0x80, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x7f, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, @@ -2729,6 +6148,1289 @@ static const unsigned char white_128x96_yuv[] = { 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80 +}; +static const unsigned char logo_128x96_yuv[] = { + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 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0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, @@ -3074,1541 +7688,3 @@ static const unsigned char white_128x96_yuv[] = { 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80 }; -static const unsigned char green_128x96_yuv[] = { - 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, - 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, - 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, - 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, - 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, - 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, - 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, - 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, - 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, - 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0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, - 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a -}; diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c index abc97a377..6f47a1841 100644 --- a/examples/device/video_capture/src/main.c +++ b/examples/device/video_capture/src/main.c @@ -104,7 +104,9 @@ void tud_resume_cb(void) // USB Video //--------------------------------------------------------------------+ static unsigned char const *frames[] = { - black_128x96_yuv, white_128x96_yuv, green_128x96_yuv + white_128x96_yuv, white_128x96_yuv, white_128x96_yuv, + t_128x96_yuv, ti_128x96_yuv, tin_128x96_yuv, logo_128x96_yuv, + logo_128x96_yuv, logo_128x96_yuv, logo_128x96_yuv, logo_128x96_yuv }; static unsigned current_frame = 0; static unsigned tx_busy = 0; -- cgit v1.3.1 From 0c89292a8dae9e5dad98a33ed3b66a4b5e796ff0 Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Sun, 26 Sep 2021 21:52:56 +0900 Subject: Fix transfer failure when reconnecting --- examples/device/video_capture/src/tusb_config.h | 10 ++- .../device/video_capture/src/usb_descriptors.c | 6 +- src/class/video/video.h | 2 - src/class/video/video_device.c | 79 +++++++++++++--------- 4 files changed, 55 insertions(+), 42 deletions(-) diff --git a/examples/device/video_capture/src/tusb_config.h b/examples/device/video_capture/src/tusb_config.h index fb194c55a..06a949b1c 100644 --- a/examples/device/video_capture/src/tusb_config.h +++ b/examples/device/video_capture/src/tusb_config.h @@ -90,12 +90,6 @@ #define CFG_TUD_ENDPOINT0_SIZE 64 #endif -// video streaming endpoint size -#define CFG_TUD_VIDEO_EP_BUFSIZE 256 - -// The number of video streaming interfaces -#define CFG_TUD_VIDEO_STREAMING 1 - //------------- CLASS -------------// #define CFG_TUD_CDC 0 #define CFG_TUD_MSC 0 @@ -104,8 +98,12 @@ #define CFG_TUD_AUDIO 0 // The number of video control interfaces #define CFG_TUD_VIDEO 1 +// The number of video streaming interfaces +#define CFG_TUD_VIDEO_STREAMING 1 #define CFG_TUD_VENDOR 0 +// video streaming endpoint size +#define CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE 256 //-------------------------------------------------------------------- // APPLICATION CONFIGURATION diff --git a/examples/device/video_capture/src/usb_descriptors.c b/examples/device/video_capture/src/usb_descriptors.c index a9fa2c043..b0e41b97e 100644 --- a/examples/device/video_capture/src/usb_descriptors.c +++ b/examples/device/video_capture/src/usb_descriptors.c @@ -45,7 +45,7 @@ tusb_desc_device_t const desc_device = .bDescriptorType = TUSB_DESC_DEVICE, .bcdUSB = 0x0200, - // Use Interface Association Descriptor (IAD) for CDC + // Use Interface Association Descriptor (IAD) for Video // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1) .bDeviceClass = TUSB_CLASS_MISC, .bDeviceSubClass = MISC_SUBCLASS_COMMON, @@ -104,7 +104,9 @@ uint8_t const desc_fs_configuration[] = // Config number, interface count, string index, total length, attribute, power in mA TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0, 500), // IAD for Video Control - TUD_VIDEO_CAPTURE_DESCRIPTOR(4, EPNUM_VIDEO_IN, FRAME_WIDTH, FRAME_HEIGHT, FRAME_RATE, CFG_TUD_VIDEO_EP_BUFSIZE) + TUD_VIDEO_CAPTURE_DESCRIPTOR(4, EPNUM_VIDEO_IN, + FRAME_WIDTH, FRAME_HEIGHT, FRAME_RATE, + CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE) }; // Invoked when received GET CONFIGURATION DESCRIPTOR diff --git a/src/class/video/video.h b/src/class/video/video.h index c62706e5b..026857aad 100644 --- a/src/class/video/video.h +++ b/src/class/video/video.h @@ -418,8 +418,6 @@ TU_VERIFY_STATIC( sizeof(video_probe_and_commit_control_t) == 48, "size is not c _fmtidx, _numfrmdesc, TUD_VIDEO_GUID(_guid), \ _bitsperpix, _frmidx, _asrx, _asry, _interlace, _cp -// _g0,_g1,_g2,_g3,_g4,_g5,_g6,_g7,_g8,_g9,_g10,_g11,_g12,_g13,_g14,_g15, - /* Uncompressed 3.1.2 Table 3-3 */ #define TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT(_frmidx, _cap, _width, _height, _minbr, _maxbr, _maxfrmbufsz, _frminterval, _minfrminterval, _maxfrminterval, _frmintervalstep) \ TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_INTERFACE_FRAME_UNCOMPRESSED, \ diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index 5b5d0b430..e820afbd4 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -28,7 +28,7 @@ #include "tusb_option.h" -#if (TUSB_OPT_DEVICE_ENABLED && CFG_TUD_VIDEO) +#if (TUSB_OPT_DEVICE_ENABLED && CFG_TUD_VIDEO && CFG_TUD_VIDEO_STREAMING) #include "device/usbd.h" #include "device/usbd_pvt.h" @@ -66,17 +66,17 @@ typedef struct TU_ATTR_PACKED { uint8_t index_vs; /* index from the video control interface */ uint8_t error_code;/* error code */ struct { - uint16_t beg; /* Offset of the beggining of video streaming interface descriptor */ + uint16_t beg; /* Offset of the begging of video streaming interface descriptor */ uint16_t end; /* Offset of the end of video streaming interface descriptor */ uint16_t cur; /* Offset of the current settings */ uint16_t ep[2]; /* Offset of endpoint descriptors. 0: streaming, 1: still capture */ } desc; - uint8_t *buffer; /* frame buffer. assume linear buffer. no support for stride access */ - uint32_t bufsize; /* frame buffer size */ - uint32_t offset; /* offset for the next payload transfer */ + uint8_t *buffer; /* frame buffer. assume linear buffer. no support for stride access */ + uint32_t bufsize; /* frame buffer size */ + uint32_t offset; /* offset for the next payload transfer */ uint32_t max_payload_transfer_size; /*------------- From this point, data is not cleared by bus reset -------------*/ - CFG_TUSB_MEM_ALIGN uint8_t ep_buf[CFG_TUD_VIDEO_EP_BUFSIZE]; /* EP transfer buffer for streaming */ + CFG_TUSB_MEM_ALIGN uint8_t ep_buf[CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE]; /* EP transfer buffer for streaming */ } videod_streaming_interface_t; /* video control interface */ @@ -89,8 +89,7 @@ typedef struct TU_ATTR_PACKED { uint8_t power_mode; /*------------- From this point, data is not cleared by bus reset -------------*/ - // - // CFG_TUSB_MEM_ALIGN uint8_t ctl_buf[64]; /* EP transfer buffer for control */ + // CFG_TUSB_MEM_ALIGN uint8_t ctl_buf[64]; /* EP transfer buffer for interrupt transfer */ } videod_interface_t; @@ -115,7 +114,7 @@ static video_probe_and_commit_control_t const def_stm_settings = { .wCompWindowSize = 1, /* Maybe it is match to GOP size */ .wDelay = 240, /* milliseconds */ .dwMaxVideoFrameSize = FRAME_WIDTH * FRAME_HEIGHT * 12 / 8, - .dwMaxPayloadTransferSize = ((FRAME_WIDTH * FRAME_HEIGHT * 12 / 8 * 10) + 999) / 1000 + 2, + .dwMaxPayloadTransferSize = ((FRAME_WIDTH * FRAME_HEIGHT * 12 / 8 * FRAME_RATE) + 999) / 1000 + 2, .dwClockFrequency = 27000000, /* same as MPEG-2 system time clock */ .bmFramingInfo = 0x3, .bPreferedVersion = 1, @@ -274,7 +273,7 @@ static void const* _find_desc_entity(tusb_desc_vc_itf_t const *vc, uint_fast8_t /** Close current video control interface. * - * @param[in,out] self The context. + * @param[in,out] self Video control interface context. * @param[in] altnum The target alternate setting number. */ static bool _close_vc_itf(uint8_t rhport, videod_interface_t *self) { @@ -294,9 +293,9 @@ static bool _close_vc_itf(uint8_t rhport, videod_interface_t *self) return true; } -/** Set the specified alternate setting to own video control interface. +/** Set the alternate setting to own video control interface. * - * @param[in,out] self The context. + * @param[in,out] self Video control interface context. * @param[in] altnum The target alternate setting number. */ static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t altnum) { @@ -333,9 +332,9 @@ static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t return true; } -/** Set the specified alternate setting to own video control interface. +/** Set the alternate setting to own video streaming interface. * - * @param[in,out] self The context. + * @param[in,out] stm Streaming interface context. * @param[in] altnum The target alternate setting number. */ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint_fast8_t altnum) { @@ -374,6 +373,10 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint tusb_video_payload_header_t *hdr = (tusb_video_payload_header_t*)stm->ep_buf; hdr->bHeaderLength = sizeof(*hdr); hdr->bmHeaderInfo = 0; + /* clear transfer management information */ + stm->buffer = NULL; + stm->bufsize = 0; + stm->offset = 0; return true; } @@ -398,13 +401,15 @@ static uint_fast16_t _prepare_in_payload(videod_streaming_interface_t *stm) } /** Handle a standard request to the video control interface. */ -static int handle_video_ctl_std_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, uint_fast8_t itf) +static int handle_video_ctl_std_req(uint8_t rhport, uint8_t stage, + tusb_control_request_t const *request, + uint_fast8_t ctl_idx) { switch (request->bRequest) { case TUSB_REQ_GET_INTERFACE: if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN); - tusb_desc_vc_itf_t const *vc = _get_desc_vc(&_videod_itf[itf]); + tusb_desc_vc_itf_t const *vc = _get_desc_vc(&_videod_itf[ctl_idx]); if (!vc) return VIDEO_UNKNOWN; if (tud_control_xfer(rhport, request, (void*)&vc->std.bAlternateSetting, @@ -414,9 +419,9 @@ static int handle_video_ctl_std_req(uint8_t rhport, uint8_t stage, tusb_control_ case TUSB_REQ_SET_INTERFACE: if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; TU_VERIFY(0 == request->wLength, VIDEO_UNKNOWN); - if (!_close_vc_itf(rhport, &_videod_itf[itf])) + if (!_close_vc_itf(rhport, &_videod_itf[ctl_idx])) return VIDEO_UNKNOWN; - if (!_open_vc_itf(rhport, &_videod_itf[itf], request->wValue)) + if (!_open_vc_itf(rhport, &_videod_itf[ctl_idx], request->wValue)) return VIDEO_UNKNOWN; tud_control_status(rhport, request); return VIDEO_NO_ERROR; @@ -426,9 +431,11 @@ static int handle_video_ctl_std_req(uint8_t rhport, uint8_t stage, tusb_control_ } } -static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, uint_fast8_t itf) +static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage, + tusb_control_request_t const *request, + uint_fast8_t ctl_idx) { - videod_interface_t *self = &_videod_itf[itf]; + videod_interface_t *self = &_videod_itf[ctl_idx]; /* 4.2.1 Interface Control Request */ switch (TU_U16_HIGH(request->wValue)) { case VIDEO_VC_CTL_VIDEO_POWER_MODE: @@ -440,7 +447,7 @@ static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r return VIDEO_UNKNOWN; } else if (stage == CONTROL_STAGE_ACK) { if (tud_video_power_mode_cb) - return tud_video_power_mode_cb(itf, self->power_mode); + return tud_video_power_mode_cb(ctl_idx, self->power_mode); } return VIDEO_NO_ERROR; case VIDEO_REQUEST_GET_CUR: @@ -480,18 +487,20 @@ static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r return VIDEO_INVALID_REQUEST; } -static int handle_video_ctl_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, uint_fast8_t itf) +static int handle_video_ctl_req(uint8_t rhport, uint8_t stage, + tusb_control_request_t const *request, + uint_fast8_t ctl_idx) { uint_fast8_t entity_id; switch (request->bmRequestType_bit.type) { case TUSB_REQ_TYPE_STANDARD: - return handle_video_ctl_std_req(rhport, stage, request, itf); + return handle_video_ctl_std_req(rhport, stage, request, ctl_idx); case TUSB_REQ_TYPE_CLASS: entity_id = TU_U16_HIGH(request->wIndex); if (!entity_id) { - return handle_video_ctl_cs_req(rhport, stage, request, itf); + return handle_video_ctl_cs_req(rhport, stage, request, ctl_idx); } else { - if (!_find_desc_entity(_get_desc_vc(&_videod_itf[itf]), entity_id)) + if (!_find_desc_entity(_get_desc_vc(&_videod_itf[ctl_idx]), entity_id)) return VIDEO_INVALID_REQUEST; return VIDEO_INVALID_REQUEST; } @@ -500,9 +509,11 @@ static int handle_video_ctl_req(uint8_t rhport, uint8_t stage, tusb_control_requ } } -static int handle_video_stm_std_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, uint_fast8_t itf) +static int handle_video_stm_std_req(uint8_t rhport, uint8_t stage, + tusb_control_request_t const *request, + uint_fast8_t stm_idx) { - videod_streaming_interface_t *self = &_videod_streaming_itf[itf]; + videod_streaming_interface_t *self = &_videod_streaming_itf[stm_idx]; switch (request->bRequest) { case TUSB_REQ_GET_INTERFACE: if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; @@ -526,10 +537,12 @@ static int handle_video_stm_std_req(uint8_t rhport, uint8_t stage, tusb_control_ } } -static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, uint_fast8_t itf) +static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, + tusb_control_request_t const *request, + uint_fast8_t stm_idx) { (void)rhport; - videod_streaming_interface_t *self = &_videod_streaming_itf[itf]; + videod_streaming_interface_t *self = &_videod_streaming_itf[stm_idx]; /* 4.2.1 Interface Control Request */ switch (TU_U16_HIGH(request->wValue)) { case VIDEO_VS_CTL_STREAM_ERROR_CODE: @@ -641,15 +654,17 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r return VIDEO_INVALID_REQUEST; } -static int handle_video_stm_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, uint_fast8_t itf) +static int handle_video_stm_req(uint8_t rhport, uint8_t stage, + tusb_control_request_t const *request, + uint_fast8_t stm_idx) { switch (request->bmRequestType_bit.type) { case TUSB_REQ_TYPE_STANDARD: - return handle_video_stm_std_req(rhport, stage, request, itf); + return handle_video_stm_std_req(rhport, stage, request, stm_idx); case TUSB_REQ_TYPE_CLASS: if (TU_U16_HIGH(request->wIndex)) return VIDEO_INVALID_REQUEST; - return handle_video_stm_cs_req(rhport, stage, request, itf); + return handle_video_stm_cs_req(rhport, stage, request, stm_idx); default: return VIDEO_INVALID_REQUEST; } -- cgit v1.3.1 From dba5e7b17d4f39c9f74b90142a2e17056f4db6d7 Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Wed, 29 Sep 2021 01:18:33 +0900 Subject: Implement negotiation process for streaming parameters --- src/class/video/video.h | 25 ++-- src/class/video/video_device.c | 305 ++++++++++++++++++++++++++++++++--------- src/class/video/video_device.h | 7 +- 3 files changed, 257 insertions(+), 80 deletions(-) diff --git a/src/class/video/video.h b/src/class/video/video.h index 026857aad..3c27c8093 100644 --- a/src/class/video/video.h +++ b/src/class/video/video.h @@ -282,18 +282,19 @@ typedef struct TU_ATTR_PACKED { } tusb_desc_cs_video_fmt_uncompressed_t; typedef struct TU_ATTR_PACKED { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bDescriptorSubType; - uint8_t bFrameIndex; - uint8_t bNumFrameDescriptors; - uint8_t guidFormat[16]; - uint8_t bBitsPerPixel; - uint8_t bDefaultFrameIndex; - uint8_t bAspectRatioX; - uint8_t bAspectRatioY; - uint8_t bmInterlaceFlags; - uint8_t bCopyProtect; + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bFrameIndex; + uint8_t bmCapabilities; + uint16_t wWidth; + uint16_t wHeight; + uint32_t dwMinBitRate; + uint32_t dwMaxBitRate; + uint32_t dwMaxVideoFrameBufferSize; /* deprecated */ + uint32_t dwDefaultFrameInterval; + uint8_t bFrameIntervalType; + uint32_t dwFrameInterval[]; } tusb_desc_cs_video_frm_uncompressed_t; //--------------------------------------------------------------------+ diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index e820afbd4..f4ecef446 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -64,7 +64,6 @@ typedef struct TU_ATTR_PACKED { typedef struct TU_ATTR_PACKED { uint8_t index_vc; /* index of bound video control interface */ uint8_t index_vs; /* index from the video control interface */ - uint8_t error_code;/* error code */ struct { uint16_t beg; /* Offset of the begging of video streaming interface descriptor */ uint16_t end; /* Offset of the end of video streaming interface descriptor */ @@ -75,6 +74,7 @@ typedef struct TU_ATTR_PACKED { uint32_t bufsize; /* frame buffer size */ uint32_t offset; /* offset for the next payload transfer */ uint32_t max_payload_transfer_size; + uint8_t error_code;/* error code */ /*------------- From this point, data is not cleared by bus reset -------------*/ CFG_TUSB_MEM_ALIGN uint8_t ep_buf[CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE]; /* EP transfer buffer for streaming */ } videod_streaming_interface_t; @@ -103,30 +103,6 @@ CFG_TUSB_MEM_SECTION static videod_streaming_interface_t _videod_streaming_itf[C static uint8_t const _cap_get = 0x1u; /* support for GET */ static uint8_t const _cap_get_set = 0x3u; /* support for GET and SET */ -static video_probe_and_commit_control_t const def_stm_settings = { - .bmHint = 0, - .bFormatIndex = 1, - .bFrameIndex = 1, - .dwFrameInterval = (10000000/FRAME_RATE), - .wKeyFrameRate = 1, - .wPFrameRate = 0, - .wCompQuality = 1, /* 1 to 10000 */ - .wCompWindowSize = 1, /* Maybe it is match to GOP size */ - .wDelay = 240, /* milliseconds */ - .dwMaxVideoFrameSize = FRAME_WIDTH * FRAME_HEIGHT * 12 / 8, - .dwMaxPayloadTransferSize = ((FRAME_WIDTH * FRAME_HEIGHT * 12 / 8 * FRAME_RATE) + 999) / 1000 + 2, - .dwClockFrequency = 27000000, /* same as MPEG-2 system time clock */ - .bmFramingInfo = 0x3, - .bPreferedVersion = 1, - .bMinVersion = 1, - .bMaxVersion = 1, - .bUsage = 0, - .bBitDepthLuma = 8, - .bmSettings = 0, - .bMaxNumberOfRefFramesPlus1 = 0, - .bmRateControlModes = 0, - .bmLayoutPerStream = 0 -}; /** Get interface number from the interface descriptor * @@ -175,24 +151,49 @@ static tusb_desc_vs_itf_t const* _get_desc_vs(videod_streaming_interface_t const return (tusb_desc_vs_itf_t const*)(desc + self->desc.cur); } -/** Find the first descriptor with the specified descriptor type. +/** Find the first descriptor of a given type * - * @param[in] beg The head of descriptor byte array. - * @param[in] end The tail of descriptor byte array. - * @param[in] target The target descriptor type. + * @param[in] beg The head of descriptor byte array. + * @param[in] end The tail of descriptor byte array. + * @param[in] desc_type The target descriptor type. * * @return The pointer for interface descriptor. * @retval end did not found interface descriptor */ -static void const* _find_desc(void const *beg, void const *end, uint8_t target) +static void const* _find_desc(void const *beg, void const *end, uint_fast8_t desc_type) { void const *cur = beg; - while ((cur < end) && (target != tu_desc_type(cur))) { + while ((cur < end) && (desc_type != tu_desc_type(cur))) { cur = tu_desc_next(cur); } return cur; } -/** Return the next interface descriptor except alternate ones. +/** Find the first descriptor specified by the arguments + * + * @param[in] beg The head of descriptor byte array. + * @param[in] end The tail of descriptor byte array. + * @param[in] desc_type The target descriptor type + * @param[in] element_0 The target element following the desc_type + * @param[in] element_1 The target element following the element_0 + * + * @return The pointer for interface descriptor. + * @retval end did not found interface descriptor */ +static void const* _find_desc_3(void const *beg, void const *end, + uint_fast8_t desc_type, + uint_fast8_t element_0, + uint_fast8_t element_1) +{ + for (void const *cur = beg; cur < end; cur = _find_desc(cur, end, desc_type)) { + uint8_t const *p = (uint8_t const *)cur; + if ((p[2] == element_0) && (p[3] == element_1)) { + return cur; + } + cur = tu_desc_next(cur); + } + return end; +} + +/** Return the next interface descriptor which has another interface number. * * @param[in] beg The head of descriptor byte array. * @param[in] end The tail of descriptor byte array. @@ -219,19 +220,14 @@ static void const* _next_desc_itf(void const *beg, void const *end) * * @return The pointer for interface descriptor. * @retval end did not found interface descriptor */ -static void const* _find_desc_itf(void const *beg, void const *end, uint_fast8_t itfnum, uint_fast8_t altnum) +static inline void const* _find_desc_itf(void const *beg, void const *end, uint_fast8_t itfnum, uint_fast8_t altnum) { - for (void const *cur = beg; cur < end; cur = _find_desc(cur, end, TUSB_DESC_INTERFACE)) { - tusb_desc_interface_t const *itf = (tusb_desc_interface_t const *)cur; - if (itf->bInterfaceNumber == itfnum && itf->bAlternateSetting == altnum) { - return itf; - } - cur = tu_desc_next(cur); - } - return end; + return _find_desc_3(beg, end, TUSB_DESC_INTERFACE, itfnum, altnum); } -/** Find the first endpoint descriptor in front of the next interface descriptor. +/** Find the first endpoint descriptor belonging to the current interface descriptor. + * + * The search range is from `beg` to `end` or the next interface descriptor. * * @param[in] beg The head of descriptor byte array. * @param[in] end The tail of descriptor byte array. @@ -248,16 +244,18 @@ static void const* _find_desc_ep(void const *beg, void const *end) return end; } -/** Find the first entity descriptor with the specified entity ID in the video control interface descriptor. +/** Find the first entity descriptor with the entity ID + * specified by the argument belonging to the current video control descriptor. * - * @param[in] vc The video control interface descriptor. + * @param[in] desc The video control interface descriptor. * @param[in] entityid The target entity id. * * @return The pointer for interface descriptor. * @retval end did not found interface descriptor */ -static void const* _find_desc_entity(tusb_desc_vc_itf_t const *vc, uint_fast8_t entityid) +static void const* _find_desc_entity(void const *desc, uint_fast8_t entityid) { - void const *beg = (void const*)vc; + tusb_desc_vc_itf_t const *vc = (tusb_desc_vc_itf_t const*)desc; + void const *beg = vc; void const *end = beg + vc->std.bLength + vc->ctl.wTotalLength; for (void const *cur = beg; cur < end; cur = _find_desc(cur, end, TUSB_DESC_CS_INTERFACE)) { tusb_desc_cs_video_entity_itf_t const *itf = (tusb_desc_cs_video_entity_itf_t const *)cur; @@ -271,6 +269,153 @@ static void const* _find_desc_entity(tusb_desc_vc_itf_t const *vc, uint_fast8_t return end; } +/** Return the end of the video streaming descriptor. */ +static inline void const* _end_of_streaming_descriptor(void const *desc) +{ + tusb_desc_vs_itf_t const *vs = (tusb_desc_vs_itf_t const *)desc; + return desc + vs->std.bLength + vs->stm.wTotalLength; +} + +/** Find the first format descriptor with the specified format number. */ +static inline tusb_desc_cs_video_fmt_uncompressed_t const *_find_desc_format(void const *beg, void const *end, uint_fast8_t fmtnum) +{ + return (tusb_desc_cs_video_fmt_uncompressed_t const*) + _find_desc_3(beg, end, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_INTERFACE_FORMAT_UNCOMPRESSED, fmtnum); +} + +/** Find the first frame descriptor with the specified format number. */ +static inline tusb_desc_cs_video_frm_uncompressed_t const *_find_desc_frame(void const *beg, void const *end, uint_fast8_t frmnum) +{ + return (tusb_desc_cs_video_frm_uncompressed_t const*) + _find_desc_3(beg, end, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_INTERFACE_FRAME_UNCOMPRESSED, frmnum); +} + +static bool _update_streaming_parameters(videod_streaming_interface_t const *stm, + video_probe_and_commit_control_t *param) +{ + tusb_desc_vs_itf_t const *vs = _get_desc_vs(stm); + uint_fast8_t fmtnum = param->bFormatIndex; + TU_ASSERT(fmtnum <= vs->stm.bNumFormats); + if (!fmtnum) { + if (1 < vs->stm.bNumFormats) + return true; /* Need to negotiate all variables. */ + fmtnum = 1; + param->bFormatIndex = 1; + } + + /* Set the parameters determined by the format */ + param->wKeyFrameRate = 1; + param->wPFrameRate = 0; + param->wCompQuality = 1; /* 1 to 10000 */ + param->wCompWindowSize = 1; /* GOP size? */ + param->wDelay = 0; /* milliseconds */ + param->dwClockFrequency = 27000000; /* same as MPEG-2 system time clock */ + param->bmFramingInfo = 0x3; /* enables FrameID and EndOfFrame */ + param->bPreferedVersion = 1; + param->bMinVersion = 1; + param->bMaxVersion = 1; + param->bUsage = 0; + param->bBitDepthLuma = 8; + + void const *end = _end_of_streaming_descriptor(vs); + tusb_desc_cs_video_fmt_uncompressed_t const *fmt = _find_desc_format(tu_desc_next(vs), end, fmtnum); + TU_ASSERT(fmt != end); + uint_fast8_t frmnum = param->bFrameIndex; + TU_ASSERT(frmnum <= fmt->bNumFrameDescriptors); + if (!frmnum) { + if (1 < fmt->bNumFrameDescriptors) + return true; + frmnum = 1; + param->bFrameIndex = 1; + } + tusb_desc_cs_video_frm_uncompressed_t const *frm = _find_desc_frame(tu_desc_next(fmt), end, frmnum); + TU_ASSERT(frm != end); + + /* Set the parameters determined by the frame */ + uint_fast32_t frame_size = param->dwMaxVideoFrameSize; + if (!frame_size) { + frame_size = (uint_fast32_t)frm->wWidth * frm->wHeight * fmt->bBitsPerPixel / 8; + param->dwMaxVideoFrameSize = frame_size; + } + + uint_fast32_t interval = param->dwFrameInterval; + if (!interval) { + if ((1 < frm->bFrameIntervalType) || + ((0 == frm->bFrameIntervalType) && (frm->dwFrameInterval[1] != frm->dwFrameInterval[0]))) + return true; + interval = frm->dwFrameInterval[0]; + param->dwFrameInterval = interval; + } + uint_fast32_t interval_ms = interval / 10000; + TU_ASSERT(interval_ms); + uint_fast32_t payload_size = (frame_size + interval_ms - 1) / interval_ms + 2; + param->dwMaxPayloadTransferSize = payload_size; + return true; +} + +static bool _negotiate_streaming_parameters(videod_streaming_interface_t const *stm, bool set_max, + video_probe_and_commit_control_t *param) +{ + uint_fast8_t const fmtnum = param->bFormatIndex; + if (!fmtnum) { + if (set_max) { + tusb_desc_vs_itf_t const *vs = _get_desc_vs(stm); + param->bFormatIndex = vs->stm.bNumFormats; + } else { + param->bFormatIndex = 1; + } + /* Set the parameters determined by the format */ + param->wKeyFrameRate = 1; + param->wPFrameRate = 0; + param->wCompQuality = 1; /* 1 to 10000 */ + param->wCompWindowSize = 1; /* GOP size? */ + param->wDelay = 0; /* milliseconds */ + param->dwClockFrequency = 27000000; /* same as MPEG-2 system time clock */ + param->bmFramingInfo = 0x3; /* enables FrameID and EndOfFrame */ + param->bPreferedVersion = 1; + param->bMinVersion = 1; + param->bMaxVersion = 1; + param->bUsage = 0; + param->bBitDepthLuma = 8; + return true; + } + + uint_fast8_t frmnum = param->bFrameIndex; + if (!frmnum) { + tusb_desc_vs_itf_t const *vs = _get_desc_vs(stm); + void const *end = _end_of_streaming_descriptor(vs); + tusb_desc_cs_video_fmt_uncompressed_t const *fmt = _find_desc_format(tu_desc_next(vs), end, fmtnum); + frmnum = set_max ? fmt->bNumFrameDescriptors: 1; + param->bFrameIndex = frmnum; + /* Set the parameters determined by the frame */ + tusb_desc_cs_video_frm_uncompressed_t const *frm = _find_desc_frame(tu_desc_next(fmt), end, frmnum); + param->dwMaxVideoFrameSize = frm->wWidth * frm->wHeight * fmt->bBitsPerPixel / 8; + return true; + } + + if (!param->dwFrameInterval) { + tusb_desc_vs_itf_t const *vs = _get_desc_vs(stm); + void const *end = _end_of_streaming_descriptor(vs); + tusb_desc_cs_video_fmt_uncompressed_t const *fmt = _find_desc_format(tu_desc_next(vs), end, fmtnum); + tusb_desc_cs_video_frm_uncompressed_t const *frm = _find_desc_frame(tu_desc_next(fmt), end, frmnum); + + uint_fast32_t interval; + uint_fast8_t num_intervals = frm->bFrameIntervalType; + if (!num_intervals) { + interval = set_max ? frm->dwFrameInterval[1]: frm->dwFrameInterval[0]; + } else { + interval = set_max ? frm->dwFrameInterval[num_intervals - 1]: frm->dwFrameInterval[0]; + } + param->dwFrameInterval = interval; + uint_fast32_t interval_ms = interval / 10000; + TU_ASSERT(interval_ms); + uint_fast32_t frame_size = param->dwMaxVideoFrameSize; + param->dwMaxPayloadTransferSize = (frame_size + interval_ms - 1) / interval_ms + 2; + return true; + } + return true; +} + /** Close current video control interface. * * @param[in,out] self Video control interface context. @@ -351,6 +496,10 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint stm->desc.ep[i] = 0; TU_LOG2(" close EP%02x\n", ep_adr); } + /* clear transfer management information */ + stm->buffer = NULL; + stm->bufsize = 0; + stm->offset = 0; /* Find a alternate interface */ void const *beg = desc + stm->desc.beg; @@ -360,23 +509,38 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint uint_fast8_t numeps = ((tusb_desc_interface_t const *)cur)->bNumEndpoints; TU_ASSERT(numeps <= TU_ARRAY_SIZE(stm->desc.ep)); stm->desc.cur = cur - desc; /* Save the offset of the new settings */ + if (!altnum) { + /* initialize streaming settings */ + stm->max_payload_transfer_size = 0; + video_probe_and_commit_control_t *param = + (video_probe_and_commit_control_t *)&stm->ep_buf; + return _update_streaming_parameters(stm, param); + } /* Open endpoints of the new settings. */ for (i = 0, cur = tu_desc_next(cur); i < numeps; ++i, cur = tu_desc_next(cur)) { cur = _find_desc_ep(cur, end); TU_ASSERT(cur < end); - TU_ASSERT(usbd_edpt_open(rhport, (tusb_desc_endpoint_t const *)cur)); + tusb_desc_endpoint_t const *ep = (tusb_desc_endpoint_t const*)cur; + if (!stm->max_payload_transfer_size) { + video_probe_and_commit_control_t const *param = + (video_probe_and_commit_control_t const*)&stm->ep_buf; + uint_fast32_t max_size = param->dwMaxPayloadTransferSize; + if ((TUSB_XFER_ISOCHRONOUS == ep->bmAttributes.xfer) && + (ep->wMaxPacketSize.size < max_size)) { + /* FS must be less than or equal to max packet size */ + return false; + } + /* Set the negotiated value */ + stm->max_payload_transfer_size = max_size; + } + TU_ASSERT(usbd_edpt_open(rhport, ep)); stm->desc.ep[i] = cur - desc; - stm->max_payload_transfer_size = def_stm_settings.dwMaxPayloadTransferSize; TU_LOG2(" open EP%02x\n", _desc_ep_addr(cur)); } /* initialize payload header */ tusb_video_payload_header_t *hdr = (tusb_video_payload_header_t*)stm->ep_buf; hdr->bHeaderLength = sizeof(*hdr); hdr->bmHeaderInfo = 0; - /* clear transfer management information */ - stm->buffer = NULL; - stm->bufsize = 0; - stm->offset = 0; return true; } @@ -569,32 +733,40 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, if (!tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t))) return VIDEO_UNKNOWN; } else if (stage == CONTROL_STAGE_ACK) { - if (tud_video_probe_set_cb) - return tud_video_probe_set_cb(self->index_vc, self->index_vs, - (video_probe_and_commit_control_t const*)self->ep_buf); + if (!_update_streaming_parameters(self, (video_probe_and_commit_control_t*)self->ep_buf)) + return VIDEO_INVALID_VALUE_WITHIN_RANGE; } return VIDEO_NO_ERROR; case VIDEO_REQUEST_GET_CUR: if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; TU_VERIFY(request->wLength, VIDEO_UNKNOWN); - if (tud_control_xfer(rhport, request, (void*)&def_stm_settings, - sizeof(video_probe_and_commit_control_t))) + if (tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t))) return VIDEO_NO_ERROR; return VIDEO_UNKNOWN; - case VIDEO_REQUEST_GET_MIN: + case VIDEO_REQUEST_GET_MIN: { + video_probe_and_commit_control_t tmp; if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; TU_VERIFY(request->wLength, VIDEO_UNKNOWN); - if (tud_control_xfer(rhport, request, (void*)&def_stm_settings, + tmp = *(video_probe_and_commit_control_t*)&self->ep_buf; + if (!_negotiate_streaming_parameters(self, false, &tmp)) + return VIDEO_INVALID_VALUE_WITHIN_RANGE; + if (tud_control_xfer(rhport, request, &tmp, sizeof(video_probe_and_commit_control_t))) return VIDEO_NO_ERROR; return VIDEO_UNKNOWN; - case VIDEO_REQUEST_GET_MAX: + } + case VIDEO_REQUEST_GET_MAX: { + video_probe_and_commit_control_t tmp; if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; TU_VERIFY(request->wLength, VIDEO_UNKNOWN); - if (tud_control_xfer(rhport, request, (void*)&def_stm_settings, + tmp = *(video_probe_and_commit_control_t*)&self->ep_buf; + if (!_negotiate_streaming_parameters(self, true, &tmp)) + return VIDEO_INVALID_VALUE_WITHIN_RANGE; + if (tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t))) return VIDEO_NO_ERROR; return VIDEO_UNKNOWN; + } case VIDEO_REQUEST_GET_RES: return VIDEO_UNKNOWN; case VIDEO_REQUEST_GET_DEF: @@ -618,16 +790,17 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, if (!tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t))) return VIDEO_UNKNOWN; } else if (stage == CONTROL_STAGE_ACK) { - if (tud_video_commit_set_cb) - return tud_video_commit_set_cb(self->index_vc, self->index_vs, - (video_probe_and_commit_control_t const*)self->ep_buf); + if (!_update_streaming_parameters(self, (video_probe_and_commit_control_t*)self->ep_buf)) + return VIDEO_INVALID_VALUE_WITHIN_RANGE; + if (tud_video_commit_cb) + return tud_video_commit_cb(self->index_vc, self->index_vs, + (video_probe_and_commit_control_t*)self->ep_buf); } return VIDEO_NO_ERROR; case VIDEO_REQUEST_GET_CUR: if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; TU_VERIFY(request->wLength, VIDEO_UNKNOWN); - if (tud_control_xfer(rhport, request, (void*)&def_stm_settings, - sizeof(video_probe_and_commit_control_t))) + if (tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t))) return VIDEO_NO_ERROR; return VIDEO_UNKNOWN; case VIDEO_REQUEST_GET_INFO: diff --git a/src/class/video/video_device.h b/src/class/video/video_device.h index e6f53fed8..8654b63c5 100644 --- a/src/class/video/video_device.h +++ b/src/class/video/video_device.h @@ -61,8 +61,11 @@ TU_ATTR_WEAK int tud_video_frame_xfer_complete_cb(uint_fast8_t ctl_idx, uint_fas * @return video_error_code_t */ TU_ATTR_WEAK int tud_video_power_mode_cb(uint_fast8_t ctl_idx, uint8_t power_mod); -/* @return video_error_code_t */ -TU_ATTR_WEAK int tud_video_probe_set_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, video_probe_and_commit_control_t const *settings); +/** + * + * @return video_error_code_t */ +TU_ATTR_WEAK int tud_video_commit_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, + video_probe_and_commit_control_t const *parameters); /* @return video_error_code_t */ TU_ATTR_WEAK int tud_video_commit_set_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, video_probe_and_commit_control_t const *settings); -- cgit v1.3.1 From 9bcab53c2cb0b52baf8bc0c768887428ac87fbff Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Wed, 29 Sep 2021 22:53:26 +0900 Subject: Implement frame rate settings --- examples/device/video_capture/src/main.c | 13 ++++++++--- .../device/video_capture/src/usb_descriptors.h | 2 +- src/class/video/video_device.c | 11 ++++++++- src/class/video/video_device.h | 27 ++++++++++++++-------- 4 files changed, 38 insertions(+), 15 deletions(-) diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c index 6f47a1841..a38791365 100644 --- a/examples/device/video_capture/src/main.c +++ b/examples/device/video_capture/src/main.c @@ -110,11 +110,11 @@ static unsigned char const *frames[] = { }; static unsigned current_frame = 0; static unsigned tx_busy = 0; +static unsigned interval_ms = 1000 / FRAME_RATE; void video_task(void) { static unsigned start_ms = 0; - static unsigned interval_ms = 1000 / FRAME_RATE; static unsigned already_sent = 0; if (!tud_video_n_streaming(0, 0)) { @@ -137,7 +137,7 @@ void video_task(void) tud_video_n_frame_xfer(0, 0, (void*)frames[current_frame], FRAME_WIDTH * FRAME_HEIGHT * 12/8); } -int tud_video_frame_xfer_complete_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx) +void tud_video_frame_xfer_complete_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx) { (void)ctl_idx; (void)stm_idx; tx_busy = 0; @@ -145,7 +145,14 @@ int tud_video_frame_xfer_complete_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx) ++current_frame; if (current_frame == sizeof(frames)/sizeof(frames[0])) current_frame = 0; - return 0; +} + +int tud_video_commit_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, + video_probe_and_commit_control_t const *parameters) +{ + /* convert unit to ms from 100 ns */ + interval_ms = parameters->dwFrameInterval / 10000; + return VIDEO_NO_ERROR; } //--------------------------------------------------------------------+ diff --git a/examples/device/video_capture/src/usb_descriptors.h b/examples/device/video_capture/src/usb_descriptors.h index 867e9af42..eff57f1fa 100644 --- a/examples/device/video_capture/src/usb_descriptors.h +++ b/examples/device/video_capture/src/usb_descriptors.h @@ -99,7 +99,7 @@ enum { TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT(/*bFrameIndex */1, 0, _width, _height, \ _width * _height * 12, _width * _height * 12 * _fps, \ _width * _height * 12, \ - (10000000/_fps), (10000000/_fps), (10000000/_fps)*_fps, (10000000/_fps)), \ + (10000000/_fps), (10000000/_fps), 10000000, 100000), \ TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING(VIDEO_COLOR_PRIMARIES_BT709, VIDEO_COLOR_XFER_CH_BT709, VIDEO_COLOR_COEF_SMPTE170M), \ /* VS alt 1 */\ TUD_VIDEO_DESC_STD_VS(1, 1, 1, 0), \ diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index f4ecef446..28ac860e1 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -290,6 +290,9 @@ static inline tusb_desc_cs_video_frm_uncompressed_t const *_find_desc_frame(void _find_desc_3(beg, end, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_INTERFACE_FRAME_UNCOMPRESSED, frmnum); } +/** Set uniquely determined values to variables that have not been set + * + * @param[in,out] param Target */ static bool _update_streaming_parameters(videod_streaming_interface_t const *stm, video_probe_and_commit_control_t *param) { @@ -353,6 +356,11 @@ static bool _update_streaming_parameters(videod_streaming_interface_t const *stm return true; } +/** Set the minimum or the maximum values to variables which need to negotiate with the host + * + * @param[in] set_max If true, the maximum values is set, otherwise the minimum value is set. + * @param[in,out] param Target + */ static bool _negotiate_streaming_parameters(videod_streaming_interface_t const *stm, bool set_max, video_probe_and_commit_control_t *param) { @@ -514,6 +522,7 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint stm->max_payload_transfer_size = 0; video_probe_and_commit_control_t *param = (video_probe_and_commit_control_t *)&stm->ep_buf; + tu_memclr(param, sizeof(*param)); return _update_streaming_parameters(stm, param); } /* Open endpoints of the new settings. */ @@ -880,7 +889,7 @@ bool tud_video_n_frame_xfer(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, void *bu if (!stm || !stm->desc.ep[0] || stm->buffer) return false; - /* find EP address */ + /* Find EP address */ void const *desc = _videod_itf[stm->index_vc].beg; uint_fast8_t ep_addr = 0; for (uint_fast8_t i = 0; i < CFG_TUD_VIDEO_STREAMING; ++i) { diff --git a/src/class/video/video_device.h b/src/class/video/video_device.h index 8654b63c5..e5012ca7e 100644 --- a/src/class/video/video_device.h +++ b/src/class/video/video_device.h @@ -43,32 +43,39 @@ extern "C" { * stm_idx instance number of streaming interface */ bool tud_video_n_streaming(uint_fast8_t ctl_idx, uint_fast8_t stm_idx); - -/* ctl_idx instance number of control interface - * stm_idx instance number of streaming interface */ +/** + * @param[in] ctl_idx Destination control interface index + * @param[in] stm_idx Destination streaming interface index + * @param[in] buffer Frame buffer. The caller must not use this buffer until the operation is completed. + * @param[in] bufsize Byte size of the frame buffer */ bool tud_video_n_frame_xfer(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, void *buffer, size_t bufsize); /*------------- Optional callbacks -------------*/ -/* ctl_idx instance number of control interface - * stm_idx instance number of streaming interface */ -TU_ATTR_WEAK int tud_video_frame_xfer_complete_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx); +/** Invoked when compeletion of a frame transfer + * + * @param[in] ctl_idx Destination control interface index + * @param[in] stm_idx Destination streaming interface index */ +TU_ATTR_WEAK void tud_video_frame_xfer_complete_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx); //--------------------------------------------------------------------+ // Application Callback API (weak is optional) //--------------------------------------------------------------------+ -/* Invoked when SET POWER_MODE request received to +/** Invoked when SET_POWER_MODE request received + * + * @param[in] ctl_idx Destination control interface index + * @param[in] stm_idx Destination streaming interface index * @return video_error_code_t */ TU_ATTR_WEAK int tud_video_power_mode_cb(uint_fast8_t ctl_idx, uint8_t power_mod); -/** +/** Invoked when VS_COMMIT_CONTROL(SET_CUR) request received * + * @param[in] ctl_idx Destination control interface index + * @param[in] stm_idx Destination streaming interface index * @return video_error_code_t */ TU_ATTR_WEAK int tud_video_commit_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, video_probe_and_commit_control_t const *parameters); -/* @return video_error_code_t */ -TU_ATTR_WEAK int tud_video_commit_set_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, video_probe_and_commit_control_t const *settings); //--------------------------------------------------------------------+ // INTERNAL USBD-CLASS DRIVER API //--------------------------------------------------------------------+ -- cgit v1.3.1 From 4ca466b00b05d50ec338712f82a5b8b16ae7ce09 Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Wed, 29 Sep 2021 22:59:46 +0900 Subject: Update comments --- src/class/video/video_device.c | 4 +--- src/class/video/video_device.h | 15 ++++++++++----- 2 files changed, 11 insertions(+), 8 deletions(-) diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index 28ac860e1..12ccbd165 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -554,6 +554,7 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint return true; } +/** Prepare the next packet payload. */ static uint_fast16_t _prepare_in_payload(videod_streaming_interface_t *stm) { uint_fast16_t remaining = stm->bufsize - stm->offset; @@ -857,7 +858,6 @@ static int handle_video_stm_req(uint8_t rhport, uint8_t stage, // APPLICATION API //--------------------------------------------------------------------+ -/* ctl_idx instance number of video control interface */ bool tud_video_n_connected(uint_fast8_t ctl_idx) { TU_ASSERT(ctl_idx < CFG_TUD_VIDEO); @@ -867,8 +867,6 @@ bool tud_video_n_connected(uint_fast8_t ctl_idx) return false; } -/* ctl_idx instance number of video control interface - * stm_idx index number of streaming interface as per video control */ bool tud_video_n_streaming(uint_fast8_t ctl_idx, uint_fast8_t stm_idx) { TU_ASSERT(ctl_idx < CFG_TUD_VIDEO); diff --git a/src/class/video/video_device.h b/src/class/video/video_device.h index e5012ca7e..ee2fcb9d5 100644 --- a/src/class/video/video_device.h +++ b/src/class/video/video_device.h @@ -39,11 +39,15 @@ extern "C" { // Application API (Multiple Ports) // CFG_TUD_VIDEO > 1 //--------------------------------------------------------------------+ -/* ctl_idx instance number of control interface - * stm_idx instance number of streaming interface */ + +/** Return true if streaming + * + * @param[in] ctl_idx Destination control interface index + * @param[in] stm_idx Destination streaming interface index */ bool tud_video_n_streaming(uint_fast8_t ctl_idx, uint_fast8_t stm_idx); -/** +/** Transfer a frame + * * @param[in] ctl_idx Destination control interface index * @param[in] stm_idx Destination streaming interface index * @param[in] buffer Frame buffer. The caller must not use this buffer until the operation is completed. @@ -70,8 +74,9 @@ TU_ATTR_WEAK int tud_video_power_mode_cb(uint_fast8_t ctl_idx, uint8_t power_mod /** Invoked when VS_COMMIT_CONTROL(SET_CUR) request received * - * @param[in] ctl_idx Destination control interface index - * @param[in] stm_idx Destination streaming interface index + * @param[in] ctl_idx Destination control interface index + * @param[in] stm_idx Destination streaming interface index + * @param[in] parameters Video streaming parameters * @return video_error_code_t */ TU_ATTR_WEAK int tud_video_commit_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, video_probe_and_commit_control_t const *parameters); -- cgit v1.3.1 From 831443a2dce346cafab47a0a7f593e72fa33bfa4 Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Thu, 30 Sep 2021 01:13:19 +0900 Subject: Move frame settings to usb_descriptors.h --- examples/device/video_capture/src/main.c | 1 + examples/device/video_capture/src/tusb_config.h | 8 -------- examples/device/video_capture/src/usb_descriptors.h | 4 ++++ 3 files changed, 5 insertions(+), 8 deletions(-) diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c index a38791365..b24f01555 100644 --- a/examples/device/video_capture/src/main.c +++ b/examples/device/video_capture/src/main.c @@ -29,6 +29,7 @@ #include "bsp/board.h" #include "tusb.h" +#include "usb_descriptors.h" #include "images.h" //--------------------------------------------------------------------+ diff --git a/examples/device/video_capture/src/tusb_config.h b/examples/device/video_capture/src/tusb_config.h index 06a949b1c..5d2d5470c 100644 --- a/examples/device/video_capture/src/tusb_config.h +++ b/examples/device/video_capture/src/tusb_config.h @@ -105,14 +105,6 @@ // video streaming endpoint size #define CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE 256 -//-------------------------------------------------------------------- -// APPLICATION CONFIGURATION -//-------------------------------------------------------------------- -#define FRAME_WIDTH 128 -#define FRAME_HEIGHT 96 -#define FRAME_RATE 10 - - #ifdef __cplusplus } #endif diff --git a/examples/device/video_capture/src/usb_descriptors.h b/examples/device/video_capture/src/usb_descriptors.h index eff57f1fa..e52703b29 100644 --- a/examples/device/video_capture/src/usb_descriptors.h +++ b/examples/device/video_capture/src/usb_descriptors.h @@ -33,6 +33,10 @@ #define UVC_ENTITY_CAP_INPUT_TERMINAL 0x01 #define UVC_ENTITY_CAP_OUTPUT_TERMINAL 0x02 +#define FRAME_WIDTH 128 +#define FRAME_HEIGHT 96 +#define FRAME_RATE 10 + enum { ITF_NUM_VIDEO_CONTROL = 0, ITF_NUM_VIDEO_STREAMING, -- cgit v1.3.1 From 9a7795464ea88a0d8c8001a42404f791d486af64 Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Thu, 30 Sep 2021 21:08:57 +0900 Subject: Add cast operations to unused parameters --- examples/device/video_capture/src/main.c | 1 + 1 file changed, 1 insertion(+) diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c index b24f01555..b76af071a 100644 --- a/examples/device/video_capture/src/main.c +++ b/examples/device/video_capture/src/main.c @@ -151,6 +151,7 @@ void tud_video_frame_xfer_complete_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx int tud_video_commit_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, video_probe_and_commit_control_t const *parameters) { + (void)ctl_idx; (void)stm_idx; /* convert unit to ms from 100 ns */ interval_ms = parameters->dwFrameInterval / 10000; return VIDEO_NO_ERROR; -- cgit v1.3.1 From 889e4103d9aa8f9a5b51cc01ec0dae2486e31b6b Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Thu, 30 Sep 2021 21:27:09 +0900 Subject: Add files to skip building for small ROM --- examples/device/video_capture/.skip.MCU_MSP430x5xx | 1 + examples/device/video_capture/.skip.MCU_SAMD11 | 0 2 files changed, 1 insertion(+) create mode 100644 examples/device/video_capture/.skip.MCU_MSP430x5xx create mode 100644 examples/device/video_capture/.skip.MCU_SAMD11 diff --git a/examples/device/video_capture/.skip.MCU_MSP430x5xx b/examples/device/video_capture/.skip.MCU_MSP430x5xx new file mode 100644 index 000000000..17600f062 --- /dev/null +++ b/examples/device/video_capture/.skip.MCU_MSP430x5xx @@ -0,0 +1 @@ +too many warnings for 16-bit integer overflow diff --git a/examples/device/video_capture/.skip.MCU_SAMD11 b/examples/device/video_capture/.skip.MCU_SAMD11 new file mode 100644 index 000000000..e69de29bb -- cgit v1.3.1 From 98e6a93a7807e67b5589b859c2871b9a36233e3d Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Thu, 30 Sep 2021 21:38:27 +0900 Subject: Add a list file for rp2040 --- examples/device/video_capture/CMakeLists.txt | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 examples/device/video_capture/CMakeLists.txt diff --git a/examples/device/video_capture/CMakeLists.txt b/examples/device/video_capture/CMakeLists.txt new file mode 100644 index 000000000..cb321f9a8 --- /dev/null +++ b/examples/device/video_capture/CMakeLists.txt @@ -0,0 +1,28 @@ +cmake_minimum_required(VERSION 3.5) + +include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake) + +# gets PROJECT name for the example (e.g. -) +family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR}) + +project(${PROJECT}) + +# Checks this example is valid for the family and initializes the project +family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR}) + +add_executable(${PROJECT}) + +# Example source +target_sources(${PROJECT} PUBLIC + ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c + ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c +) + +# Example include +target_include_directories(${PROJECT} PUBLIC + ${CMAKE_CURRENT_SOURCE_DIR}/src +) + +# Configure compilation flags and libraries for the example... see the corresponding function +# in hw/bsp/FAMILY/family.cmake for details. +family_configure_device_example(${PROJECT}) \ No newline at end of file -- cgit v1.3.1 From 2800a6a5830e721baffdf95e4fe6cd1475771582 Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Thu, 30 Sep 2021 21:46:16 +0900 Subject: Add a file to skip bluepill --- examples/device/video_capture/.skip.MCU_STM32F1 | 0 1 file changed, 0 insertions(+), 0 deletions(-) create mode 100644 examples/device/video_capture/.skip.MCU_STM32F1 diff --git a/examples/device/video_capture/.skip.MCU_STM32F1 b/examples/device/video_capture/.skip.MCU_STM32F1 new file mode 100644 index 000000000..e69de29bb -- cgit v1.3.1 From 7708997a679f61b2ea8fdc7bec880cd19ecaa28f Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 30 Sep 2021 20:14:23 +0700 Subject: change scsis status to phase error when total_bytes < block_count --- src/class/msc/msc_device.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c index b65abe979..87ebe227f 100644 --- a/src/class/msc/msc_device.c +++ b/src/class/msc/msc_device.c @@ -182,15 +182,15 @@ uint8_t rdwr10_validate_cmd(msc_cbw_t const* cbw) TU_LOG(MSC_DEBUG, " SCSI case 8 (Hi <> Do)\r\n"); status = MSC_CSW_STATUS_PHASE_ERROR; } - else if ( !block_count ) + else if ( 0 == block_count ) { - TU_LOG(MSC_DEBUG, " SCSI case 4 Hi > Dn\r\n"); + TU_LOG(MSC_DEBUG, " SCSI case 4 Hi > Dn (READ10) or case 9 Ho > Dn (WRITE10) \r\n"); status = MSC_CSW_STATUS_FAILED; } - else if ( SCSI_CMD_READ_10 == cbw->command[0] && cbw->total_bytes / block_count == 0) + else if ( cbw->total_bytes / block_count == 0 ) { - TU_LOG(MSC_DEBUG, " Computed block size 0\r\n"); - status = MSC_CSW_STATUS_FAILED; + TU_LOG(MSC_DEBUG, " Computed block size = 0. SCSI case 7 Hi < Di (READ10) or case 13 Ho < Do (WRIT10)\r\n"); + status = MSC_CSW_STATUS_PHASE_ERROR; } } -- cgit v1.3.1 From a1788da4105b762e919dee0e1f2141288751e7b8 Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Thu, 30 Sep 2021 22:14:29 +0900 Subject: Add video class entry to rp2040 building scripts --- examples/device/CMakeLists.txt | 1 + hw/bsp/rp2040/family.cmake | 1 + 2 files changed, 2 insertions(+) diff --git a/examples/device/CMakeLists.txt b/examples/device/CMakeLists.txt index a0e4600f6..edf5ab805 100644 --- a/examples/device/CMakeLists.txt +++ b/examples/device/CMakeLists.txt @@ -24,4 +24,5 @@ family_add_subdirectory(msc_dual_lun) family_add_subdirectory(net_lwip_webserver) family_add_subdirectory(uac2_headset) family_add_subdirectory(usbtmc) +family_add_subdirectory(video_capture) family_add_subdirectory(webusb_serial) diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake index 41960b6cd..10c103a9e 100644 --- a/hw/bsp/rp2040/family.cmake +++ b/hw/bsp/rp2040/family.cmake @@ -73,6 +73,7 @@ if (NOT TARGET _rp2040_family_inclusion_marker) ${TOP}/src/class/net/net_device.c ${TOP}/src/class/usbtmc/usbtmc_device.c ${TOP}/src/class/vendor/vendor_device.c + ${TOP}/src/class/video/video_device.c ) -- cgit v1.3.1 From 0932d502c78796762a7d4ec7ee709707ede83dc8 Mon Sep 17 00:00:00 2001 From: Scott Shawcroft Date: Thu, 30 Sep 2021 14:50:38 -0700 Subject: remove bcm files --- hw/mcu/broadcom/bcm2711/boot.s | 172 ----------------------------------- hw/mcu/broadcom/bcm2711/interrupts.c | 26 ------ hw/mcu/broadcom/bcm2711/interrupts.h | 8 -- hw/mcu/broadcom/bcm2711/io.c | 170 ---------------------------------- hw/mcu/broadcom/bcm2711/io.h | 13 --- hw/mcu/broadcom/bcm2711/link.ld | 28 ------ hw/mcu/broadcom/bcm2711/mmu.c | 62 ------------- hw/mcu/broadcom/bcm2711/mmu.h | 45 --------- 8 files changed, 524 deletions(-) delete mode 100644 hw/mcu/broadcom/bcm2711/boot.s delete mode 100644 hw/mcu/broadcom/bcm2711/interrupts.c delete mode 100644 hw/mcu/broadcom/bcm2711/interrupts.h delete mode 100644 hw/mcu/broadcom/bcm2711/io.c delete mode 100644 hw/mcu/broadcom/bcm2711/io.h delete mode 100644 hw/mcu/broadcom/bcm2711/link.ld delete mode 100644 hw/mcu/broadcom/bcm2711/mmu.c delete mode 100644 hw/mcu/broadcom/bcm2711/mmu.h diff --git a/hw/mcu/broadcom/bcm2711/boot.s b/hw/mcu/broadcom/bcm2711/boot.s deleted file mode 100644 index dcc588924..000000000 --- a/hw/mcu/broadcom/bcm2711/boot.s +++ /dev/null @@ -1,172 +0,0 @@ -.section ".text.boot" // Make sure the linker puts this at the start of the kernel image - -.global _start // Execution starts here - -_start: - // Check processor ID is zero (executing on main core), else hang - mrs x1, mpidr_el1 - and x1, x1, #3 - cbz x1, 2f - // We're not on the main core, so hang in an infinite wait loop -1: wfe - b 1b -2: // We're on the main core! - - // Set stack to start below our code - ldr x1, =_start - mov sp, x1 - - adr x0, vectors // load VBAR_EL1 with virtual - // msr vbar_el3, x0 // vector table address - msr vbar_el1, x0 // vector table address - msr vbar_el2, x0 // vector table address - isb - - // Clean the BSS section - ldr x1, =__bss_start // Start address - ldr w2, =__bss_size // Size of the section -3: cbz w2, 4f // Quit loop if zero - str xzr, [x1], #8 - sub w2, w2, #1 - cbnz w2, 3b // Loop if non-zero - - // Jump to our main() routine in C (make sure it doesn't return) -4: bl main - // In case it does return, halt the master core too - b 1b - -.macro ventry label -.align 7 -b \label -.endm - -.macro handle_invalid_entry type -irq_entry -mov x0, #\type -mrs x1, esr_el1 -mrs x2, elr_el1 -mrs x3, esr_el2 -mrs x4, elr_el2 -b err_hang -.endm - -.macro irq_entry -sub sp, sp, #272 -stp x0, x1, [sp, #16 * 0] -stp x2, x3, [sp, #16 * 1] -stp x4, x5, [sp, #16 * 2] -stp x6, x7, [sp, #16 * 3] -stp x8, x9, [sp, #16 * 4] -stp x10, x11, [sp, #16 * 5] -stp x12, x13, [sp, #16 * 6] -stp x14, x15, [sp, #16 * 7] -stp x16, x17, [sp, #16 * 8] -stp x18, x19, [sp, #16 * 9] -stp x20, x21, [sp, #16 * 10] -stp x22, x23, [sp, #16 * 11] -stp x24, x25, [sp, #16 * 12] -stp x26, x27, [sp, #16 * 13] -stp x28, x29, [sp, #16 * 14] -str x30, [sp, #16 * 15] -.endm - -.macro irq_exit -ldp x0, x1, [sp, #16 * 0] -ldp x2, x3, [sp, #16 * 1] -ldp x4, x5, [sp, #16 * 2] -ldp x6, x7, [sp, #16 * 3] -ldp x8, x9, [sp, #16 * 4] -ldp x10, x11, [sp, #16 * 5] -ldp x12, x13, [sp, #16 * 6] -ldp x14, x15, [sp, #16 * 7] -ldp x16, x17, [sp, #16 * 8] -ldp x18, x19, [sp, #16 * 9] -ldp x20, x21, [sp, #16 * 10] -ldp x22, x23, [sp, #16 * 11] -ldp x24, x25, [sp, #16 * 12] -ldp x26, x27, [sp, #16 * 13] -ldp x28, x29, [sp, #16 * 14] -ldr x30, [sp, #16 * 15] -add sp, sp, #272 -eret -.endm - - -/* - * Exception vectors. - */ -.align 11 -.globl vectors -vectors: - ventry sync_invalid_el1t // Synchronous EL1t - ventry irq_invalid_el1t // IRQ EL1t - ventry fiq_invalid_el1t // FIQ EL1t - ventry error_invalid_el1t // Error EL1t - - ventry sync_invalid_el1h // Synchronous EL1h - ventry el1_irq // IRQ EL1h - ventry fiq_invalid_el1h // FIQ EL1h - ventry error_invalid_el1h // Error EL1h - - ventry sync_invalid_el0_64 // Synchronous 64-bit EL0 - ventry irq_invalid_el0_64 // IRQ 64-bit EL0 - ventry fiq_invalid_el0_64 // FIQ 64-bit EL0 - ventry error_invalid_el0_64 // Error 64-bit EL0 - - ventry sync_invalid_el0_32 // Synchronous 32-bit EL0 - ventry irq_invalid_el0_32 // IRQ 32-bit EL0 - ventry fiq_invalid_el0_32 // FIQ 32-bit EL0 - ventry error_invalid_el0_32 // Error 32-bit EL0 - -sync_invalid_el1t: - handle_invalid_entry 0 - -irq_invalid_el1t: - handle_invalid_entry 1 - -fiq_invalid_el1t: - handle_invalid_entry 2 - -error_invalid_el1t: - handle_invalid_entry 3 - -sync_invalid_el1h: - handle_invalid_entry 4 - -fiq_invalid_el1h: - handle_invalid_entry 5 - -error_invalid_el1h: - handle_invalid_entry 6 - -sync_invalid_el0_64: - handle_invalid_entry 7 - -irq_invalid_el0_64: - handle_invalid_entry 8 - -fiq_invalid_el0_64: - handle_invalid_entry 9 - -error_invalid_el0_64: - handle_invalid_entry 10 - -sync_invalid_el0_32: - handle_invalid_entry 11 - -irq_invalid_el0_32: - handle_invalid_entry 12 - -fiq_invalid_el0_32: - handle_invalid_entry 13 - -error_invalid_el0_32: - handle_invalid_entry 14 - -el1_irq: - irq_entry - bl handle_irq - irq_exit - -.globl err_hang -err_hang: b err_hang diff --git a/hw/mcu/broadcom/bcm2711/interrupts.c b/hw/mcu/broadcom/bcm2711/interrupts.c deleted file mode 100644 index cb5607526..000000000 --- a/hw/mcu/broadcom/bcm2711/interrupts.c +++ /dev/null @@ -1,26 +0,0 @@ -#include -#include - -void disable_async_interrupts(void) { - -} - -void enable_async_interrupts(void) { - -} - -void Default_Handler(void) { - while (true) {} -} - -__attribute__((weak)) void handle_irq(void) { - unsigned int irq = *((volatile uint32_t*) 0x3F00B204); - switch (irq) { - // case (SYSTEM_TIMER_IRQ_1): - // handle_timer_irq(); - // break; - default: - // printf("Unknown pending irq: %x\r\n", irq); - Default_Handler(); - } -} \ No newline at end of file diff --git a/hw/mcu/broadcom/bcm2711/interrupts.h b/hw/mcu/broadcom/bcm2711/interrupts.h deleted file mode 100644 index 5f36d6daa..000000000 --- a/hw/mcu/broadcom/bcm2711/interrupts.h +++ /dev/null @@ -1,8 +0,0 @@ -#pragma once - -void disable_async_interrupts(void); -void enable_async_interrupts(void); - -#define GIC_BASE 0x4c0040000 -#define NUM_CPUS 4 -#define NUM_SPIS 192 diff --git a/hw/mcu/broadcom/bcm2711/io.c b/hw/mcu/broadcom/bcm2711/io.c deleted file mode 100644 index 8ccfdc692..000000000 --- a/hw/mcu/broadcom/bcm2711/io.c +++ /dev/null @@ -1,170 +0,0 @@ -// From: https://github.com/isometimes/rpi4-osdev/blob/master/part4-miniuart/io.c -// CC-0 License - -// GPIO - -// Pi 4 base address: 0xFE000000 -// Pi 3 base address: 0x3F000000 -enum { - PERIPHERAL_BASE = 0xFE000000, - GPFSEL0 = PERIPHERAL_BASE + 0x200000, - GPSET0 = PERIPHERAL_BASE + 0x20001C, - GPCLR0 = PERIPHERAL_BASE + 0x200028, - GPPUPPDN0 = PERIPHERAL_BASE + 0x2000E4 -}; - -enum { - GPIO_MAX_PIN = 53, - GPIO_FUNCTION_OUT = 1, - GPIO_FUNCTION_ALT5 = 2, - GPIO_FUNCTION_ALT3 = 7 -}; - -enum { - Pull_None = 0, - Pull_Down = 1, // Are down and up the right way around? - Pull_Up = 2 -}; - -void mmio_write(long reg, unsigned int val) { *(volatile unsigned int *)reg = val; } -unsigned int mmio_read(long reg) { return *(volatile unsigned int *)reg; } - -unsigned int gpio_call(unsigned int pin_number, unsigned int value, unsigned int base, unsigned int field_size, unsigned int field_max) { - unsigned int field_mask = (1 << field_size) - 1; - - if (pin_number > field_max) return 0; - if (value > field_mask) return 0; - - unsigned int num_fields = 32 / field_size; - unsigned int reg = base + ((pin_number / num_fields) * 4); - unsigned int shift = (pin_number % num_fields) * field_size; - - unsigned int curval = mmio_read(reg); - curval &= ~(field_mask << shift); - curval |= value << shift; - mmio_write(reg, curval); - - return 1; -} - -unsigned int gpio_set (unsigned int pin_number, unsigned int value) { return gpio_call(pin_number, value, GPSET0, 1, GPIO_MAX_PIN); } -unsigned int gpio_clear (unsigned int pin_number, unsigned int value) { return gpio_call(pin_number, value, GPCLR0, 1, GPIO_MAX_PIN); } -unsigned int gpio_pull (unsigned int pin_number, unsigned int value) { return gpio_call(pin_number, value, GPPUPPDN0, 2, GPIO_MAX_PIN); } -unsigned int gpio_function(unsigned int pin_number, unsigned int value) { return gpio_call(pin_number, value, GPFSEL0, 3, GPIO_MAX_PIN); } - -void gpio_useAsAlt3(unsigned int pin_number) { - gpio_pull(pin_number, Pull_None); - gpio_function(pin_number, GPIO_FUNCTION_ALT3); -} - -void gpio_useAsAlt5(unsigned int pin_number) { - gpio_pull(pin_number, Pull_None); - gpio_function(pin_number, GPIO_FUNCTION_ALT5); -} - -void gpio_initOutputPinWithPullNone(unsigned int pin_number) { - gpio_pull(pin_number, Pull_None); - gpio_function(pin_number, GPIO_FUNCTION_OUT); -} - -void gpio_setPinOutputBool(unsigned int pin_number, unsigned int onOrOff) { - if (onOrOff) { - gpio_set(pin_number, 1); - } else { - gpio_clear(pin_number, 1); - } -} - -// UART - -enum { - AUX_BASE = PERIPHERAL_BASE + 0x215000, - AUX_IRQ = AUX_BASE, - AUX_ENABLES = AUX_BASE + 4, - AUX_MU_IO_REG = AUX_BASE + 64, - AUX_MU_IER_REG = AUX_BASE + 68, - AUX_MU_IIR_REG = AUX_BASE + 72, - AUX_MU_LCR_REG = AUX_BASE + 76, - AUX_MU_MCR_REG = AUX_BASE + 80, - AUX_MU_LSR_REG = AUX_BASE + 84, - AUX_MU_MSR_REG = AUX_BASE + 88, - AUX_MU_SCRATCH = AUX_BASE + 92, - AUX_MU_CNTL_REG = AUX_BASE + 96, - AUX_MU_STAT_REG = AUX_BASE + 100, - AUX_MU_BAUD_REG = AUX_BASE + 104, - AUX_UART_CLOCK = 500000000, - UART_MAX_QUEUE = 16 * 1024 -}; - -#define AUX_MU_BAUD(baud) ((AUX_UART_CLOCK/(baud*8))-1) - -unsigned char uart_output_queue[UART_MAX_QUEUE]; -unsigned int uart_output_queue_write = 0; -unsigned int uart_output_queue_read = 0; - -void uart_init(void) { - mmio_write(AUX_ENABLES, 1); //enable UART1 - mmio_write(AUX_MU_IER_REG, 0); - mmio_write(AUX_MU_CNTL_REG, 0); - mmio_write(AUX_MU_LCR_REG, 3); //8 bits - mmio_write(AUX_MU_MCR_REG, 0); - mmio_write(AUX_MU_IER_REG, 0); - mmio_write(AUX_MU_IIR_REG, 0xC6); //disable interrupts - mmio_write(AUX_MU_BAUD_REG, AUX_MU_BAUD(115200)); - gpio_useAsAlt5(14); - gpio_useAsAlt5(15); - mmio_write(AUX_MU_CNTL_REG, 3); //enable RX/TX -} - -unsigned int uart_isOutputQueueEmpty(void) { - return uart_output_queue_read == uart_output_queue_write; -} - -unsigned int uart_isReadByteReady(void) { return mmio_read(AUX_MU_LSR_REG) & 0x01; } -unsigned int uart_isWriteByteReady(void) { return mmio_read(AUX_MU_LSR_REG) & 0x20; } - -unsigned char uart_readByte(void) { - while (!uart_isReadByteReady()); - return (unsigned char)mmio_read(AUX_MU_IO_REG); -} - -void uart_writeByteBlockingActual(unsigned char ch) { - while (!uart_isWriteByteReady()); - mmio_write(AUX_MU_IO_REG, (unsigned int)ch); -} - -void uart_loadOutputFifo(void) { - while (!uart_isOutputQueueEmpty() && uart_isWriteByteReady()) { - uart_writeByteBlockingActual(uart_output_queue[uart_output_queue_read]); - uart_output_queue_read = (uart_output_queue_read + 1) & (UART_MAX_QUEUE - 1); // Don't overrun - } -} - -void uart_writeByteBlocking(unsigned char ch) { - unsigned int next = (uart_output_queue_write + 1) & (UART_MAX_QUEUE - 1); // Don't overrun - - while (next == uart_output_queue_read) uart_loadOutputFifo(); - - uart_output_queue[uart_output_queue_write] = ch; - uart_output_queue_write = next; -} - -void uart_writeText(const char *buffer) { - while (*buffer) { - if (*buffer == '\n') uart_writeByteBlocking('\r'); - uart_writeByteBlocking(*buffer++); - } -} - -void uart_drainOutputQueue(void) { - while (!uart_isOutputQueueEmpty()) uart_loadOutputFifo(); -} - -void uart_update(void) { - uart_loadOutputFifo(); - - if (uart_isReadByteReady()) { - unsigned char ch = uart_readByte(); - if (ch == '\r') uart_writeText("\n"); else uart_writeByteBlocking(ch); - } -} diff --git a/hw/mcu/broadcom/bcm2711/io.h b/hw/mcu/broadcom/bcm2711/io.h deleted file mode 100644 index 9f70ce504..000000000 --- a/hw/mcu/broadcom/bcm2711/io.h +++ /dev/null @@ -1,13 +0,0 @@ -// From: https://github.com/isometimes/rpi4-osdev/blob/master/part4-miniuart/io.h -// CC-0 License - -void uart_init(void); -void uart_writeText(const char *buffer); -void uart_loadOutputFifo(void); -unsigned char uart_readByte(void); -unsigned int uart_isReadByteReady(void); -void uart_writeByteBlocking(unsigned char ch); -void uart_update(void); -void gpio_setPinOutputBool(unsigned int pin_number, unsigned int onOrOff); -void uart_writeByteBlockingActual(unsigned char ch); -void gpio_initOutputPinWithPullNone(unsigned int pin_number); diff --git a/hw/mcu/broadcom/bcm2711/link.ld b/hw/mcu/broadcom/bcm2711/link.ld deleted file mode 100644 index 43c4e722f..000000000 --- a/hw/mcu/broadcom/bcm2711/link.ld +++ /dev/null @@ -1,28 +0,0 @@ -SECTIONS -{ - . = 0x80000; /* Kernel load address for AArch64 */ - .text : { - KEEP(*(.text.boot)) - *(.text .text.* .gnu.linkonce.t*) - } - .rodata : { - . = ALIGN(4096); - *(.rodata .rodata.* .gnu.linkonce.r*) - } - PROVIDE(_data = .); - .data : { - . = ALIGN(4096); - *(.data .data.* .gnu.linkonce.d*) - } - .bss (NOLOAD) : { - __bss_start = .; - *(.bss .bss.*) - *(COMMON) - __bss_end = .; - } - _end = .; - end = .; - - /DISCARD/ : { *(.comment) *(.gnu*) *(.note*) *(.eh_frame*) } -} -__bss_size = (__bss_end - __bss_start)>>3; diff --git a/hw/mcu/broadcom/bcm2711/mmu.c b/hw/mcu/broadcom/bcm2711/mmu.c deleted file mode 100644 index e5ae236bd..000000000 --- a/hw/mcu/broadcom/bcm2711/mmu.c +++ /dev/null @@ -1,62 +0,0 @@ -#include -#include - - -#include "mmu.h" - -// Each entry is a gig. -volatile uint64_t level_1_table[512] __attribute__((aligned(4096))); - -// Third gig has peripherals -uint64_t level_2_0x0_c000_0000_to_0x1_0000_0000[512] __attribute__((aligned(4096))); - -void setup_mmu_flat_map(void) { - // Set the first gig to regular access. - level_1_table[0] = 0x0000000000000000 | - MM_DESCRIPTOR_MAIR_INDEX(MT_NORMAL_NC) | - MM_DESCRIPTOR_ACCESS_FLAG | - MM_DESCRIPTOR_BLOCK | - MM_DESCRIPTOR_VALID; - level_1_table[3] = ((uint64_t) level_2_0x0_c000_0000_to_0x1_0000_0000) | - MM_DESCRIPTOR_TABLE | - MM_DESCRIPTOR_VALID; - // Set peripherals to register access. - for (uint64_t i = 480; i < 512; i++) { - level_2_0x0_c000_0000_to_0x1_0000_0000[i] = (0x00000000c0000000 + (i << 21)) | - MM_DESCRIPTOR_EXECUTE_NEVER | - MM_DESCRIPTOR_MAIR_INDEX(MT_DEVICE_nGnRnE) | - MM_DESCRIPTOR_ACCESS_FLAG | - MM_DESCRIPTOR_BLOCK | - MM_DESCRIPTOR_VALID; - } - uint64_t mair = MAIR_VALUE; - uint64_t tcr = TCR_VALUE; - uint64_t ttbr0 = ((uint64_t) level_1_table) | MM_TTBR_CNP; - uint64_t sctlr = 0; - __asm__ volatile ( - // Set MAIR - "MSR MAIR_EL2, %[mair]\n\t" - // Set TTBR0 - "MSR TTBR0_EL2, %[ttbr0]\n\t" - // Set TCR - "MSR TCR_EL2, %[tcr]\n\t" - // The ISB forces these changes to be seen before the MMU is enabled. - "ISB\n\t" - // Read System Control Register configuration data - "MRS %[sctlr], SCTLR_EL2\n\t" - // Write System Control Register configuration data - "ORR %[sctlr], %[sctlr], #1\n\t" - // Set [M] bit and enable the MMU. - "MSR SCTLR_EL2, %[sctlr]\n\t" - // The ISB forces these changes to be seen by the next instruction - "ISB\n\t" - // "AT S1EL2R %[ttbr0]" - : /* No outputs. */ - : [mair] "r" (mair), - [tcr] "r" (tcr), - [ttbr0] "r" (ttbr0), - [sctlr] "r" (sctlr) - ); - //__asm__ ("brk #123"); - //while (true) {} -} diff --git a/hw/mcu/broadcom/bcm2711/mmu.h b/hw/mcu/broadcom/bcm2711/mmu.h deleted file mode 100644 index 1fe081f34..000000000 --- a/hw/mcu/broadcom/bcm2711/mmu.h +++ /dev/null @@ -1,45 +0,0 @@ -#pragma once - - -// From: https://github.com/s-matyukevich/raspberry-pi-os/blob/master/docs/lesson06/rpi-os.md -/* - * Memory region attributes: - * - * n = AttrIndx[2:0] - * n MAIR - * DEVICE_nGnRnE 000 00000000 - * NORMAL_NC 001 01000100 - */ -#define MT_DEVICE_nGnRnE 0x0 -#define MT_NORMAL_NC 0x1 -#define MT_DEVICE_nGnRnE_FLAGS 0x00 -#define MT_NORMAL_NC_FLAGS 0xff -#define MAIR_VALUE (MT_DEVICE_nGnRnE_FLAGS << (8 * MT_DEVICE_nGnRnE)) | (MT_NORMAL_NC_FLAGS << (8 * MT_NORMAL_NC)) - - -#define TCR_T0SZ (64 - 36) -#define TCR_PS (0x01 << 16) // 36-bit physical address -#define TCR_TG0_4K (0 << 14) -#define TCR_SH0_OUTER_SHAREABLE (0x2 << 12) -#define TCR_VALUE (TCR_T0SZ | TCR_PS | TCR_TG0_4K | TCR_SH0_OUTER_SHAREABLE) - -#define ENTRY_TYPE_TABLE_DESCRIPTOR 0x11 -#define ENTRY_TYPE_BLOCK_ENTRY 0x01 -#define ENTRY_TYPE_TABLE_ENTRY 0x11 -#define ENTRY_TYPE_INVALID 0x00 - -#define MM_DESCRIPTOR_VALID (0x1) - -#define MM_DESCRIPTOR_BLOCK (0x0 << 1) -#define MM_DESCRIPTOR_TABLE (0x1 << 1) - -// Block attributes -#define MM_DESCRIPTOR_EXECUTE_NEVER (0x1ull << 54) -#define MM_DESCRIPTOR_CONTIGUOUS (0x1ull << 52) -#define MM_DESCRIPTOR_ACCESS_FLAG (0x1ull << 10) - -#define MM_DESCRIPTOR_MAIR_INDEX(index) (index << 2) - -#define MM_TTBR_CNP (0x1) - -void setup_mmu_flat_map(void); -- cgit v1.3.1 From fdd1e4fbf03726703cba701f9ea7d9541e9bab9e Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 1 Oct 2021 21:52:29 +0700 Subject: more usbd clean up --- src/device/usbd.c | 62 +++++++++++++++++++++++---------------------------- src/device/usbd.h | 59 +++++++++++++++++++++++++++++++++++------------- src/device/usbd_pvt.h | 4 ++++ 3 files changed, 75 insertions(+), 50 deletions(-) diff --git a/src/device/usbd.c b/src/device/usbd.c index fda4a343e..a33d778db 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -906,64 +906,58 @@ static bool process_set_config(uint8_t rhport, uint8_t cfg_num) TU_ASSERT( TUSB_DESC_INTERFACE == tu_desc_type(p_desc) ); tusb_desc_interface_t const * desc_itf = (tusb_desc_interface_t const*) p_desc; - // Interface number must not be used already - TU_ASSERT(DRVID_INVALID == _usbd_dev.itf2drv[desc_itf->bInterfaceNumber]); - -#if CFG_TUD_MIDI - // MIDI has 2 interfaces (Audio Control v1 + MIDIStreaming) but does not have IAD - // manually increase the associated count - if (1 == assoc_itf_count && - TUSB_CLASS_AUDIO == desc_itf->bInterfaceClass && - AUDIO_SUBCLASS_CONTROL == desc_itf->bInterfaceSubClass && - AUDIO_FUNC_PROTOCOL_CODE_UNDEF == desc_itf->bInterfaceProtocol) - { - assoc_itf_count = 2; - } -#endif - -#if CFG_TUD_BTH && CFG_TUD_BTH_ISO_ALT_COUNT - // BTH implementation currently does not use IAD. TODO should also use IAD for composite device - if (1 == assoc_itf_count && - TUD_BT_APP_CLASS == desc_itf->bInterfaceClass && - TUD_BT_APP_SUBCLASS == desc_itf->bInterfaceSubClass && - TUD_BT_PROTOCOL_PRIMARY_CONTROLLER == desc_itf->bInterfaceProtocol) - { - assoc_itf_count = 2; - } -#endif - - uint16_t const drv_len = tu_desc_get_interface_total_len(desc_itf, assoc_itf_count, desc_end-p_desc); - TU_ASSERT(drv_len >= sizeof(tusb_desc_interface_t)); - // Find driver for this interface + uint16_t const remaining_len = desc_end-p_desc; uint8_t drv_id; for (drv_id = 0; drv_id < TOTAL_DRIVER_COUNT; drv_id++) { usbd_class_driver_t const *driver = get_driver(drv_id); + uint16_t const drv_len = driver->open(rhport, desc_itf, remaining_len); - if ( driver->open(rhport, desc_itf, drv_len) ) + if ( (sizeof(tusb_desc_interface_t) <= drv_len) && (drv_len <= remaining_len) ) { // Open successfully TU_LOG2(" %s opened\r\n", driver->name); + // Some drivers use 2 or more interfaces but may not have IAD e.g MIDI (always) or + // BTH (even CDC) with class in device descriptor (single interface) + if ( assoc_itf_count == 1) + { + #if CFG_TUD_CDC + if ( driver->open == cdcd_open ) assoc_itf_count = 2; + #endif + + #if CFG_TUD_MIDI + if ( driver->open == midid_open ) assoc_itf_count = 2; + #endif + + #if CFG_TUD_BTH && CFG_TUD_BTH_ISO_ALT_COUNT + if ( driver->open == btd_open ) assoc_itf_count = 2; + #endif + } + // bind (associated) interfaces to found driver for(uint8_t i=0; ibInterfaceNumber+i] = drv_id; + uint8_t const itf_num = desc_itf->bInterfaceNumber+i; + + // Interface number must not be used already + TU_ASSERT(DRVID_INVALID == _usbd_dev.itf2drv[itf_num]); + _usbd_dev.itf2drv[itf_num] = drv_id; } // bind all endpoints to found driver tu_edpt_bind_driver(_usbd_dev.ep2drv, desc_itf, drv_len, drv_id); + // next Interface + p_desc += drv_len; + break; // exit driver find loop } } // Failed if there is no supported drivers TU_ASSERT(drv_id < TOTAL_DRIVER_COUNT); - - // next Interface or IAD descriptor - p_desc += drv_len; } // invoke callback diff --git a/src/device/usbd.h b/src/device/usbd.h index c83509234..6b19e7217 100644 --- a/src/device/usbd.h +++ b/src/device/usbd.h @@ -178,17 +178,18 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb 0x9C, 0xD2, 0x65, 0x9D, 0x9E, 0x64, 0x8A, 0x9F //--------------------------------------------------------------------+ -// Configuration & Interface Descriptor Templates +// Configuration Descriptor Templates //--------------------------------------------------------------------+ -//------------- Configuration -------------// #define TUD_CONFIG_DESC_LEN (9) // Config number, interface count, string index, total length, attribute, power in mA #define TUD_CONFIG_DESCRIPTOR(config_num, _itfcount, _stridx, _total_len, _attribute, _power_ma) \ 9, TUSB_DESC_CONFIGURATION, U16_TO_U8S_LE(_total_len), _itfcount, config_num, _stridx, TU_BIT(7) | _attribute, (_power_ma)/2 -//------------- CDC -------------// +//--------------------------------------------------------------------+ +// CDC Descriptor Templates +//--------------------------------------------------------------------+ // Length of template descriptor: 66 bytes #define TUD_CDC_DESC_LEN (8+9+5+5+4+5+7+9+7+7) @@ -217,7 +218,9 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb /* Endpoint In */\ 7, TUSB_DESC_ENDPOINT, _epin, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0 -//------------- MSC -------------// +//--------------------------------------------------------------------+ +// MSC Descriptor Templates +//--------------------------------------------------------------------+ // Length of template descriptor: 23 bytes #define TUD_MSC_DESC_LEN (9 + 7 + 7) @@ -231,7 +234,10 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb /* Endpoint In */\ 7, TUSB_DESC_ENDPOINT, _epin, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0 -//------------- HID -------------// + +//--------------------------------------------------------------------+ +// HID Descriptor Templates +//--------------------------------------------------------------------+ // Length of template descriptor: 25 bytes #define TUD_HID_DESC_LEN (9 + 9 + 7) @@ -261,8 +267,10 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb /* Endpoint In */\ 7, TUSB_DESC_ENDPOINT, _epin, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_epsize), _ep_interval -//------------- MIDI -------------// -// MIDI v1.0 is based on Audio v1.0 +//--------------------------------------------------------------------+ +// MIDI Descriptor Templates +// Note: MIDI v1.0 is based on Audio v1.0 +//--------------------------------------------------------------------+ #define TUD_MIDI_DESC_HEAD_LEN (9 + 9 + 9 + 7) #define TUD_MIDI_DESC_HEAD(_itfnum, _stridx, _numcables) \ @@ -319,7 +327,9 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb TUD_MIDI_DESC_EP(_epin, _epsize, 1),\ TUD_MIDI_JACKID_OUT_EMB(1) -//------------- AUDIO -------------// +//--------------------------------------------------------------------+ +// Audio v2.0 Descriptor Templates +//--------------------------------------------------------------------+ /* Standard Interface Association Descriptor (IAD) */ #define TUD_AUDIO_DESC_IAD_LEN 8 @@ -551,7 +561,10 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb ((((_maxFrequency + ((CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED) ? 7999 : 999)) / ((CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED) ? 8000 : 1000)) + 1) * _nBytesPerSample * _nChannels) -//------------- TUD_USBTMC/USB488 -------------// +//--------------------------------------------------------------------+ +// USBTMC/USB488 Descriptor Templates +//--------------------------------------------------------------------+ + #define TUD_USBTMC_APP_CLASS (TUSB_CLASS_APPLICATION_SPECIFIC) #define TUD_USBTMC_APP_SUBCLASS 0x03u @@ -581,8 +594,10 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb #define TUD_USBTMC_INT_DESCRIPTOR_LEN (7u) +//--------------------------------------------------------------------+ +// Vendor Descriptor Templates +//--------------------------------------------------------------------+ -//------------- Vendor -------------// #define TUD_VENDOR_DESC_LEN (9+7+7) // Interface number, string index, EP Out & IN address, EP size @@ -594,7 +609,10 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb /* Endpoint In */\ 7, TUSB_DESC_ENDPOINT, _epin, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0 -//------------- DFU Runtime -------------// +//--------------------------------------------------------------------+ +// DFU Runtime Descriptor Templates +//--------------------------------------------------------------------+ + #define TUD_DFU_APP_CLASS (TUSB_CLASS_APPLICATION_SPECIFIC) #define TUD_DFU_APP_SUBCLASS (APP_SUBCLASS_DFU_RUNTIME) @@ -609,6 +627,10 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb /* Function */ \ 9, DFU_DESC_FUNCTIONAL, _attr, U16_TO_U8S_LE(_timeout), U16_TO_U8S_LE(_xfer_size), U16_TO_U8S_LE(0x0101) +//--------------------------------------------------------------------+ +// DFU Descriptor Templates +//--------------------------------------------------------------------+ + // Length of template descriptor: 9 bytes + number of alternatives * 9 #define TUD_DFU_DESC_LEN(_alt_count) (9 + (_alt_count) * 9) @@ -654,8 +676,9 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb _TUD_DFU_ALT(_itfnum, _alt_count, _stridx), \ _TUD_DFU_ALT_7(_itfnum, _alt_count+1, _stridx+1) - -//------------- CDC-ECM -------------// +//--------------------------------------------------------------------+ +// CDC-ECM Descriptor Templates +//--------------------------------------------------------------------+ // Length of template descriptor: 71 bytes #define TUD_CDC_ECM_DESC_LEN (8+9+5+5+13+7+9+9+7+7) @@ -684,8 +707,9 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb /* Endpoint Out */\ 7, TUSB_DESC_ENDPOINT, _epout, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0 - -//------------- RNDIS -------------// +//--------------------------------------------------------------------+ +// RNDIS Descriptor Templates +//--------------------------------------------------------------------+ #if 0 /* Windows XP */ @@ -726,7 +750,10 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb /* Endpoint Out */\ 7, TUSB_DESC_ENDPOINT, _epout, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0 -//------------- BT Radio -------------// +//--------------------------------------------------------------------+ +// Bluetooth Radio Descriptor Templates +//--------------------------------------------------------------------+ + #define TUD_BT_APP_CLASS (TUSB_CLASS_WIRELESS_CONTROLLER) #define TUD_BT_APP_SUBCLASS 0x01 #define TUD_BT_PROTOCOL_PRIMARY_CONTROLLER 0x01 diff --git a/src/device/usbd_pvt.h b/src/device/usbd_pvt.h index 7607b9895..f66429a02 100644 --- a/src/device/usbd_pvt.h +++ b/src/device/usbd_pvt.h @@ -43,6 +43,10 @@ typedef struct char const* name; #endif + // Minimum number of Interfaces for this driver to work. + // Only needed for driver use 2 or more interfaces without IAD + uint8_t itf_count_min; + void (* init ) (void); void (* reset ) (uint8_t rhport); uint16_t (* open ) (uint8_t rhport, tusb_desc_interface_t const * desc_intf, uint16_t max_len); -- cgit v1.3.1 From 75ad0c7d310bf49b70e737d82b86b7ad4be1f167 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 1 Oct 2021 22:20:50 +0700 Subject: clean up --- src/device/usbd_pvt.h | 4 ---- src/host/usbh.c | 9 +++++---- 2 files changed, 5 insertions(+), 8 deletions(-) diff --git a/src/device/usbd_pvt.h b/src/device/usbd_pvt.h index f66429a02..7607b9895 100644 --- a/src/device/usbd_pvt.h +++ b/src/device/usbd_pvt.h @@ -43,10 +43,6 @@ typedef struct char const* name; #endif - // Minimum number of Interfaces for this driver to work. - // Only needed for driver use 2 or more interfaces without IAD - uint8_t itf_count_min; - void (* init ) (void); void (* reset ) (uint8_t rhport); uint16_t (* open ) (uint8_t rhport, tusb_desc_interface_t const * desc_intf, uint16_t max_len); diff --git a/src/host/usbh.c b/src/host/usbh.c index 100a17aa4..2ef936ad0 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -1000,9 +1000,6 @@ static bool parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configura TU_ASSERT( TUSB_DESC_INTERFACE == tu_desc_type(p_desc) ); tusb_desc_interface_t const* desc_itf = (tusb_desc_interface_t const*) p_desc; - // Interface number must not be used already - TU_ASSERT( DRVID_INVALID == dev->itf2drv[desc_itf->bInterfaceNumber] ); - #if CFG_TUH_MIDI // MIDI has 2 interfaces (Audio Control v1 + MIDIStreaming) but does not have IAD // manually increase the associated count @@ -1040,7 +1037,11 @@ static bool parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configura // bind (associated) interfaces to found driver for(uint8_t i=0; iitf2drv[desc_itf->bInterfaceNumber+i] = drv_id; + uint8_t const itf_num = desc_itf->bInterfaceNumber+i; + + // Interface number must not be used already + TU_ASSERT( DRVID_INVALID == dev->itf2drv[itf_num] ); + dev->itf2drv[itf_num] = drv_id; } // bind all endpoints to found driver -- cgit v1.3.1 From fec2d1598921d59b9112749e670f8ac2bcf37e2b Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 1 Oct 2021 23:00:09 +0700 Subject: clean up vendor open --- src/class/vendor/vendor_device.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/src/class/vendor/vendor_device.c b/src/class/vendor/vendor_device.c index 8f25141b8..8a4ca1d2e 100644 --- a/src/class/vendor/vendor_device.c +++ b/src/class/vendor/vendor_device.c @@ -179,8 +179,8 @@ uint16_t vendord_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, ui { TU_VERIFY(TUSB_CLASS_VENDOR_SPECIFIC == desc_itf->bInterfaceClass, 0); - uint16_t drv_len = tu_desc_len(desc_itf); uint8_t const * p_desc = tu_desc_next(desc_itf); + uint8_t const * desc_end = p_desc + max_len; // Find available interface vendord_interface_t* p_vendor = NULL; @@ -198,16 +198,15 @@ uint16_t vendord_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, ui if (desc_itf->bNumEndpoints) { // skip non-endpoint descriptors - while ( (TUSB_DESC_ENDPOINT != tu_desc_type(p_desc)) && (drv_len <= max_len) ) + while ( (TUSB_DESC_ENDPOINT != tu_desc_type(p_desc)) && (p_desc < desc_end) ) { - drv_len += tu_desc_len(p_desc); - p_desc = tu_desc_next(p_desc); + p_desc = tu_desc_next(p_desc); } // Open endpoint pair with usbd helper TU_ASSERT(usbd_open_edpt_pair(rhport, p_desc, desc_itf->bNumEndpoints, TUSB_XFER_BULK, &p_vendor->ep_out, &p_vendor->ep_in), 0); - drv_len += desc_itf->bNumEndpoints*sizeof(tusb_desc_endpoint_t); + p_desc += desc_itf->bNumEndpoints*sizeof(tusb_desc_endpoint_t); // Prepare for incoming data if ( p_vendor->ep_out ) @@ -218,7 +217,7 @@ uint16_t vendord_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, ui if ( p_vendor->ep_in ) maybe_transmit(p_vendor); } - return drv_len; + return (uintptr_t) p_desc - (uintptr_t) desc_itf; } bool vendord_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) -- cgit v1.3.1 From aa97b419b22f466c7034d42a0298fad3eafc5311 Mon Sep 17 00:00:00 2001 From: Charlie Birks Date: Mon, 4 Oct 2021 11:43:12 +0100 Subject: Handle HID devices with OUT endpoint listed first This happens on my PowerA wired Switch pro controller --- src/class/hid/hid_host.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c index 8c66477b3..ac260d39b 100644 --- a/src/class/hid/hid_host.c +++ b/src/class/hid/hid_host.c @@ -291,7 +291,15 @@ bool hidh_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *de tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) p_desc; TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType); + // first endpoint may be OUT, skip to IN endpoint // TODO also open endpoint OUT + if(tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_OUT) + { + p_desc = tu_desc_next(p_desc); + desc_ep = (tusb_desc_endpoint_t const *) p_desc; + TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType); + } + TU_ASSERT( usbh_edpt_open(rhport, dev_addr, desc_ep) ); hidh_interface_t* hid_itf = get_instance(dev_addr, hid_dev->inst_count); -- cgit v1.3.1 From a867d87072e6f25e47f209e9615e00b97a9eb36f Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 5 Oct 2021 12:32:07 +0700 Subject: rename CFG_TUD_NET to CFG_TUD_ECM_RNDIS --- .../device/cdc_msc_freertos/src/CMakeLists.txt | 2 +- .../hid_composite_freertos/src/CMakeLists.txt | 2 +- .../device/net_lwip_webserver/src/tusb_config.h | 12 +- .../net_lwip_webserver/src/usb_descriptors.c | 12 +- examples/rules.mk | 2 +- hw/bsp/rp2040/family.cmake | 2 +- src/class/net/ecm_rndis_device.c | 445 +++++++++++++++++++++ src/class/net/ecmrndis_device.c | 445 --------------------- src/class/net/ncm_device.c | 24 +- src/class/net/net_device.h | 34 +- src/device/usbd.c | 2 +- src/tusb.h | 2 +- src/tusb_option.h | 10 +- 13 files changed, 504 insertions(+), 490 deletions(-) create mode 100644 src/class/net/ecm_rndis_device.c delete mode 100644 src/class/net/ecmrndis_device.c diff --git a/examples/device/cdc_msc_freertos/src/CMakeLists.txt b/examples/device/cdc_msc_freertos/src/CMakeLists.txt index f1c1e8c5d..07fc4df89 100644 --- a/examples/device/cdc_msc_freertos/src/CMakeLists.txt +++ b/examples/device/cdc_msc_freertos/src/CMakeLists.txt @@ -23,7 +23,7 @@ target_sources(${COMPONENT_TARGET} PUBLIC "${TOP}/src/class/hid/hid_device.c" "${TOP}/src/class/midi/midi_device.c" "${TOP}/src/class/msc/msc_device.c" - "${TOP}/src/class/net/ecmrndis_device.c" + "${TOP}/src/class/net/ecm_rndis_device.c" "${TOP}/src/class/net/ncm_device.c" "${TOP}/src/class/usbtmc/usbtmc_device.c" "${TOP}/src/class/vendor/vendor_device.c" diff --git a/examples/device/hid_composite_freertos/src/CMakeLists.txt b/examples/device/hid_composite_freertos/src/CMakeLists.txt index 70df447dd..6f156379f 100644 --- a/examples/device/hid_composite_freertos/src/CMakeLists.txt +++ b/examples/device/hid_composite_freertos/src/CMakeLists.txt @@ -23,7 +23,7 @@ target_sources(${COMPONENT_TARGET} PUBLIC "${TOP}/src/class/hid/hid_device.c" "${TOP}/src/class/midi/midi_device.c" "${TOP}/src/class/msc/msc_device.c" - "${TOP}/src/class/net/ecmrndis_device.c" + "${TOP}/src/class/net/ecm_rndis_device.c" "${TOP}/src/class/net/ncm_device.c" "${TOP}/src/class/usbtmc/usbtmc_device.c" "${TOP}/src/class/vendor/vendor_device.c" diff --git a/examples/device/net_lwip_webserver/src/tusb_config.h b/examples/device/net_lwip_webserver/src/tusb_config.h index 457918cac..114961cb7 100644 --- a/examples/device/net_lwip_webserver/src/tusb_config.h +++ b/examples/device/net_lwip_webserver/src/tusb_config.h @@ -95,13 +95,11 @@ #endif //------------- CLASS -------------// -#define CFG_TUD_CDC 0 -#define CFG_TUD_MSC 0 -#define CFG_TUD_HID 0 -#define CFG_TUD_MIDI 0 -#define CFG_TUD_VENDOR 0 -#define CFG_TUD_NET 1 -#define CFG_TUD_NCM 0 + +// Network class has 2 drivers: ECM/RNDIS and NCM. +// Only one of the drivers can be enabled +#define CFG_TUD_ECM_RNDIS 1 +#define CFG_TUD_NCM (1-CFG_TUD_ECM_RNDIS) #ifdef __cplusplus } diff --git a/examples/device/net_lwip_webserver/src/usb_descriptors.c b/examples/device/net_lwip_webserver/src/usb_descriptors.c index d9618a3dc..2b4b2a0c3 100644 --- a/examples/device/net_lwip_webserver/src/usb_descriptors.c +++ b/examples/device/net_lwip_webserver/src/usb_descriptors.c @@ -33,7 +33,7 @@ */ #define _PID_MAP(itf, n) ( (CFG_TUD_##itf) << (n) ) #define USB_PID (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \ - _PID_MAP(MIDI, 3) | _PID_MAP(VENDOR, 4) | _PID_MAP(NET, 5) ) + _PID_MAP(MIDI, 3) | _PID_MAP(VENDOR, 4) | _PID_MAP(ECM_RNDIS, 5) | _PID_MAP(NCM, 5) ) // String Descriptor Index enum @@ -55,7 +55,7 @@ enum enum { -#if !CFG_TUD_NCM +#if CFG_TUD_ECM_RNDIS CONFIG_ID_RNDIS = 0, CONFIG_ID_ECM = 1, #else @@ -125,7 +125,8 @@ uint8_t const * tud_descriptor_device_cb(void) #define EPNUM_NET_IN 0x82 #endif -#if !CFG_TUD_NCM +#if CFG_TUD_ECM_RNDIS + static uint8_t const rndis_configuration[] = { // Config number (index+1), interface count, string index, total length, attribute, power in mA @@ -143,7 +144,9 @@ static uint8_t const ecm_configuration[] = // Interface number, description string index, MAC address string index, EP notification address and size, EP data address (out, in), and size, max segment size. TUD_CDC_ECM_DESCRIPTOR(ITF_NUM_CDC, STRID_INTERFACE, STRID_MAC, EPNUM_NET_NOTIF, 64, EPNUM_NET_OUT, EPNUM_NET_IN, CFG_TUD_NET_ENDPOINT_SIZE, CFG_TUD_NET_MTU), }; + #else + static uint8_t const ncm_configuration[] = { // Config number (index+1), interface count, string index, total length, attribute, power in mA @@ -152,6 +155,7 @@ static uint8_t const ncm_configuration[] = // Interface number, description string index, MAC address string index, EP notification address and size, EP data address (out, in), and size, max segment size. TUD_CDC_NCM_DESCRIPTOR(ITF_NUM_CDC, STRID_INTERFACE, STRID_MAC, EPNUM_NET_NOTIF, 64, EPNUM_NET_OUT, EPNUM_NET_IN, CFG_TUD_NET_ENDPOINT_SIZE, CFG_TUD_NET_MTU), }; + #endif // Configuration array: RNDIS and CDC-ECM @@ -160,7 +164,7 @@ static uint8_t const ncm_configuration[] = // - Linux will work on both static uint8_t const * const configuration_arr[2] = { -#if !CFG_TUD_NCM +#if CFG_TUD_ECM_RNDIS [CONFIG_ID_RNDIS] = rndis_configuration, [CONFIG_ID_ECM ] = ecm_configuration #else diff --git a/examples/rules.mk b/examples/rules.mk index a9dfa1363..5f9dd9d19 100644 --- a/examples/rules.mk +++ b/examples/rules.mk @@ -33,7 +33,7 @@ SRC_C += \ src/class/hid/hid_device.c \ src/class/midi/midi_device.c \ src/class/msc/msc_device.c \ - src/class/net/ecmrndis_device.c \ + src/class/net/ecm_rndis_device.c \ src/class/net/ncm_device.c \ src/class/usbtmc/usbtmc_device.c \ src/class/vendor/vendor_device.c diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake index a0f41212c..4ba24b3aa 100644 --- a/hw/bsp/rp2040/family.cmake +++ b/hw/bsp/rp2040/family.cmake @@ -70,7 +70,7 @@ if (NOT TARGET _rp2040_family_inclusion_marker) ${TOP}/src/class/hid/hid_device.c ${TOP}/src/class/midi/midi_device.c ${TOP}/src/class/msc/msc_device.c - ${TOP}/src/class/net/ecmrndis_device.c + ${TOP}/src/class/net/ecm_rndis_device.c ${TOP}/src/class/net/ncm_device.c ${TOP}/src/class/usbtmc/usbtmc_device.c ${TOP}/src/class/vendor/vendor_device.c diff --git a/src/class/net/ecm_rndis_device.c b/src/class/net/ecm_rndis_device.c new file mode 100644 index 000000000..c6cd388e3 --- /dev/null +++ b/src/class/net/ecm_rndis_device.c @@ -0,0 +1,445 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020 Peter Lawrence + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "tusb_option.h" + +#if ( TUSB_OPT_DEVICE_ENABLED && CFG_TUD_ECM_RNDIS ) + +#include "device/usbd.h" +#include "device/usbd_pvt.h" + +#include "net_device.h" +#include "rndis_protocol.h" + +void rndis_class_set_handler(uint8_t *data, int size); /* found in ./misc/networking/rndis_reports.c */ + +//--------------------------------------------------------------------+ +// MACRO CONSTANT TYPEDEF +//--------------------------------------------------------------------+ +typedef struct +{ + uint8_t itf_num; // Index number of Management Interface, +1 for Data Interface + uint8_t itf_data_alt; // Alternate setting of Data Interface. 0 : inactive, 1 : active + + uint8_t ep_notif; + uint8_t ep_in; + uint8_t ep_out; + + bool ecm_mode; + + // Endpoint descriptor use to open/close when receving SetInterface + // TODO since configuration descriptor may not be long-lived memory, we should + // keep a copy of endpoint attribute instead + uint8_t const * ecm_desc_epdata; + +} netd_interface_t; + +#define CFG_TUD_NET_PACKET_PREFIX_LEN sizeof(rndis_data_packet_t) +#define CFG_TUD_NET_PACKET_SUFFIX_LEN 0 + +CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t received[CFG_TUD_NET_PACKET_PREFIX_LEN + CFG_TUD_NET_MTU + CFG_TUD_NET_PACKET_PREFIX_LEN]; +CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t transmitted[CFG_TUD_NET_PACKET_PREFIX_LEN + CFG_TUD_NET_MTU + CFG_TUD_NET_PACKET_PREFIX_LEN]; + +struct ecm_notify_struct +{ + tusb_control_request_t header; + uint32_t downlink, uplink; +}; + +static const struct ecm_notify_struct ecm_notify_nc = +{ + .header = { + .bmRequestType = 0xA1, + .bRequest = 0 /* NETWORK_CONNECTION aka NetworkConnection */, + .wValue = 1 /* Connected */, + .wLength = 0, + }, +}; + +static const struct ecm_notify_struct ecm_notify_csc = +{ + .header = { + .bmRequestType = 0xA1, + .bRequest = 0x2A /* CONNECTION_SPEED_CHANGE aka ConnectionSpeedChange */, + .wLength = 8, + }, + .downlink = 9728000, + .uplink = 9728000, +}; + +// TODO remove CFG_TUSB_MEM_SECTION, control internal buffer is already in this special section +CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static union +{ + uint8_t rndis_buf[120]; + struct ecm_notify_struct ecm_buf; +} notify; + +//--------------------------------------------------------------------+ +// INTERNAL OBJECT & FUNCTION DECLARATION +//--------------------------------------------------------------------+ +// TODO remove CFG_TUSB_MEM_SECTION +CFG_TUSB_MEM_SECTION static netd_interface_t _netd_itf; + +static bool can_xmit; + +void tud_network_recv_renew(void) +{ + usbd_edpt_xfer(TUD_OPT_RHPORT, _netd_itf.ep_out, received, sizeof(received)); +} + +static void do_in_xfer(uint8_t *buf, uint16_t len) +{ + can_xmit = false; + usbd_edpt_xfer(TUD_OPT_RHPORT, _netd_itf.ep_in, buf, len); +} + +void netd_report(uint8_t *buf, uint16_t len) +{ + // skip if previous report not yet acknowledged by host + if ( usbd_edpt_busy(TUD_OPT_RHPORT, _netd_itf.ep_notif) ) return; + usbd_edpt_xfer(TUD_OPT_RHPORT, _netd_itf.ep_notif, buf, len); +} + +//--------------------------------------------------------------------+ +// USBD Driver API +//--------------------------------------------------------------------+ +void netd_init(void) +{ + tu_memclr(&_netd_itf, sizeof(_netd_itf)); +} + +void netd_reset(uint8_t rhport) +{ + (void) rhport; + + netd_init(); +} + +uint16_t netd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len) +{ + bool const is_rndis = (TUD_RNDIS_ITF_CLASS == itf_desc->bInterfaceClass && + TUD_RNDIS_ITF_SUBCLASS == itf_desc->bInterfaceSubClass && + TUD_RNDIS_ITF_PROTOCOL == itf_desc->bInterfaceProtocol); + + bool const is_ecm = (TUSB_CLASS_CDC == itf_desc->bInterfaceClass && + CDC_COMM_SUBCLASS_ETHERNET_CONTROL_MODEL == itf_desc->bInterfaceSubClass && + 0x00 == itf_desc->bInterfaceProtocol); + + TU_VERIFY(is_rndis || is_ecm, 0); + + // confirm interface hasn't already been allocated + TU_ASSERT(0 == _netd_itf.ep_notif, 0); + + // sanity check the descriptor + _netd_itf.ecm_mode = is_ecm; + + //------------- Management Interface -------------// + _netd_itf.itf_num = itf_desc->bInterfaceNumber; + + uint16_t drv_len = sizeof(tusb_desc_interface_t); + uint8_t const * p_desc = tu_desc_next( itf_desc ); + + // Communication Functional Descriptors + while ( TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc) && drv_len <= max_len ) + { + drv_len += tu_desc_len(p_desc); + p_desc = tu_desc_next(p_desc); + } + + // notification endpoint (if any) + if ( TUSB_DESC_ENDPOINT == tu_desc_type(p_desc) ) + { + TU_ASSERT( usbd_edpt_open(rhport, (tusb_desc_endpoint_t const *) p_desc), 0 ); + + _netd_itf.ep_notif = ((tusb_desc_endpoint_t const *) p_desc)->bEndpointAddress; + + drv_len += tu_desc_len(p_desc); + p_desc = tu_desc_next(p_desc); + } + + //------------- Data Interface -------------// + // - RNDIS Data followed immediately by a pair of endpoints + // - CDC-ECM data interface has 2 alternate settings + // - 0 : zero endpoints for inactive (default) + // - 1 : IN & OUT endpoints for active networking + TU_ASSERT(TUSB_DESC_INTERFACE == tu_desc_type(p_desc), 0); + + do + { + tusb_desc_interface_t const * data_itf_desc = (tusb_desc_interface_t const *) p_desc; + TU_ASSERT(TUSB_CLASS_CDC_DATA == data_itf_desc->bInterfaceClass, 0); + + drv_len += tu_desc_len(p_desc); + p_desc = tu_desc_next(p_desc); + }while( _netd_itf.ecm_mode && (TUSB_DESC_INTERFACE == tu_desc_type(p_desc)) && (drv_len <= max_len) ); + + // Pair of endpoints + TU_ASSERT(TUSB_DESC_ENDPOINT == tu_desc_type(p_desc), 0); + + if ( _netd_itf.ecm_mode ) + { + // ECM by default is in-active, save the endpoint attribute + // to open later when received setInterface + _netd_itf.ecm_desc_epdata = p_desc; + }else + { + // Open endpoint pair for RNDIS + TU_ASSERT( usbd_open_edpt_pair(rhport, p_desc, 2, TUSB_XFER_BULK, &_netd_itf.ep_out, &_netd_itf.ep_in), 0 ); + + tud_network_init_cb(); + + // we are ready to transmit a packet + can_xmit = true; + + // prepare for incoming packets + tud_network_recv_renew(); + } + + drv_len += 2*sizeof(tusb_desc_endpoint_t); + + return drv_len; +} + +static void ecm_report(bool nc) +{ + notify.ecm_buf = (nc) ? ecm_notify_nc : ecm_notify_csc; + notify.ecm_buf.header.wIndex = _netd_itf.itf_num; + netd_report((uint8_t *)¬ify.ecm_buf, (nc) ? sizeof(notify.ecm_buf.header) : sizeof(notify.ecm_buf)); +} + +// Invoked when a control transfer occurred on an interface of this class +// Driver response accordingly to the request and the transfer stage (setup/data/ack) +// return false to stall control endpoint (e.g unsupported request) +bool netd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t const * request) +{ + if ( stage == CONTROL_STAGE_SETUP ) + { + switch ( request->bmRequestType_bit.type ) + { + case TUSB_REQ_TYPE_STANDARD: + switch ( request->bRequest ) + { + case TUSB_REQ_GET_INTERFACE: + { + uint8_t const req_itfnum = (uint8_t) request->wIndex; + TU_VERIFY(_netd_itf.itf_num+1 == req_itfnum); + + tud_control_xfer(rhport, request, &_netd_itf.itf_data_alt, 1); + } + break; + + case TUSB_REQ_SET_INTERFACE: + { + uint8_t const req_itfnum = (uint8_t) request->wIndex; + uint8_t const req_alt = (uint8_t) request->wValue; + + // Only valid for Data Interface with Alternate is either 0 or 1 + TU_VERIFY(_netd_itf.itf_num+1 == req_itfnum && req_alt < 2); + + // ACM-ECM only: qequest to enable/disable network activities + TU_VERIFY(_netd_itf.ecm_mode); + + _netd_itf.itf_data_alt = req_alt; + + if ( _netd_itf.itf_data_alt ) + { + // TODO since we don't actually close endpoint + // hack here to not re-open it + if ( _netd_itf.ep_in == 0 && _netd_itf.ep_out == 0 ) + { + TU_ASSERT(_netd_itf.ecm_desc_epdata); + TU_ASSERT( usbd_open_edpt_pair(rhport, _netd_itf.ecm_desc_epdata, 2, TUSB_XFER_BULK, &_netd_itf.ep_out, &_netd_itf.ep_in) ); + + // TODO should be merge with RNDIS's after endpoint opened + // Also should have opposite callback for application to disable network !! + tud_network_init_cb(); + can_xmit = true; // we are ready to transmit a packet + tud_network_recv_renew(); // prepare for incoming packets + } + }else + { + // TODO close the endpoint pair + // For now pretend that we did, this should have no harm since host won't try to + // communicate with the endpoints again + // _netd_itf.ep_in = _netd_itf.ep_out = 0 + } + + tud_control_status(rhport, request); + } + break; + + // unsupported request + default: return false; + } + break; + + case TUSB_REQ_TYPE_CLASS: + TU_VERIFY (_netd_itf.itf_num == request->wIndex); + + if (_netd_itf.ecm_mode) + { + /* the only required CDC-ECM Management Element Request is SetEthernetPacketFilter */ + if (0x43 /* SET_ETHERNET_PACKET_FILTER */ == request->bRequest) + { + tud_control_xfer(rhport, request, NULL, 0); + ecm_report(true); + } + } + else + { + if (request->bmRequestType_bit.direction == TUSB_DIR_IN) + { + rndis_generic_msg_t *rndis_msg = (rndis_generic_msg_t *) ((void*) notify.rndis_buf); + uint32_t msglen = tu_le32toh(rndis_msg->MessageLength); + TU_ASSERT(msglen <= sizeof(notify.rndis_buf)); + tud_control_xfer(rhport, request, notify.rndis_buf, msglen); + } + else + { + tud_control_xfer(rhport, request, notify.rndis_buf, sizeof(notify.rndis_buf)); + } + } + break; + + // unsupported request + default: return false; + } + } + else if ( stage == CONTROL_STAGE_DATA ) + { + // Handle RNDIS class control OUT only + if (request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS && + request->bmRequestType_bit.direction == TUSB_DIR_OUT && + _netd_itf.itf_num == request->wIndex) + { + if ( !_netd_itf.ecm_mode ) + { + rndis_class_set_handler(notify.rndis_buf, request->wLength); + } + } + } + + return true; +} + +static void handle_incoming_packet(uint32_t len) +{ + uint8_t *pnt = received; + uint32_t size = 0; + + if (_netd_itf.ecm_mode) + { + size = len; + } + else + { + rndis_data_packet_t *r = (rndis_data_packet_t *) ((void*) pnt); + if (len >= sizeof(rndis_data_packet_t)) + if ( (r->MessageType == REMOTE_NDIS_PACKET_MSG) && (r->MessageLength <= len)) + if ( (r->DataOffset + offsetof(rndis_data_packet_t, DataOffset) + r->DataLength) <= len) + { + pnt = &received[r->DataOffset + offsetof(rndis_data_packet_t, DataOffset)]; + size = r->DataLength; + } + } + + if (!tud_network_recv_cb(pnt, size)) + { + /* if a buffer was never handled by user code, we must renew on the user's behalf */ + tud_network_recv_renew(); + } +} + +bool netd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) +{ + (void) rhport; + (void) result; + + /* new packet received */ + if ( ep_addr == _netd_itf.ep_out ) + { + handle_incoming_packet(xferred_bytes); + } + + /* data transmission finished */ + if ( ep_addr == _netd_itf.ep_in ) + { + /* TinyUSB requires the class driver to implement ZLP (since ZLP usage is class-specific) */ + + if ( xferred_bytes && (0 == (xferred_bytes % CFG_TUD_NET_ENDPOINT_SIZE)) ) + { + do_in_xfer(NULL, 0); /* a ZLP is needed */ + } + else + { + /* we're finally finished */ + can_xmit = true; + } + } + + if ( _netd_itf.ecm_mode && (ep_addr == _netd_itf.ep_notif) ) + { + if (sizeof(notify.ecm_buf.header) == xferred_bytes) ecm_report(false); + } + + return true; +} + +bool tud_network_can_xmit(uint16_t size) +{ + (void)size; + + return can_xmit; +} + +void tud_network_xmit(void *ref, uint16_t arg) +{ + uint8_t *data; + uint16_t len; + + if (!can_xmit) + return; + + len = (_netd_itf.ecm_mode) ? 0 : CFG_TUD_NET_PACKET_PREFIX_LEN; + data = transmitted + len; + + len += tud_network_xmit_cb(data, ref, arg); + + if (!_netd_itf.ecm_mode) + { + rndis_data_packet_t *hdr = (rndis_data_packet_t *) ((void*) transmitted); + memset(hdr, 0, sizeof(rndis_data_packet_t)); + hdr->MessageType = REMOTE_NDIS_PACKET_MSG; + hdr->MessageLength = len; + hdr->DataOffset = sizeof(rndis_data_packet_t) - offsetof(rndis_data_packet_t, DataOffset); + hdr->DataLength = len - sizeof(rndis_data_packet_t); + } + + do_in_xfer(transmitted, len); +} + +#endif diff --git a/src/class/net/ecmrndis_device.c b/src/class/net/ecmrndis_device.c deleted file mode 100644 index 288ecb7e2..000000000 --- a/src/class/net/ecmrndis_device.c +++ /dev/null @@ -1,445 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2020 Peter Lawrence - * Copyright (c) 2019 Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#include "tusb_option.h" - -#if ( TUSB_OPT_DEVICE_ENABLED && CFG_TUD_NET && !CFG_TUD_NCM ) - -#include "device/usbd.h" -#include "device/usbd_pvt.h" - -#include "net_device.h" -#include "rndis_protocol.h" - -void rndis_class_set_handler(uint8_t *data, int size); /* found in ./misc/networking/rndis_reports.c */ - -//--------------------------------------------------------------------+ -// MACRO CONSTANT TYPEDEF -//--------------------------------------------------------------------+ -typedef struct -{ - uint8_t itf_num; // Index number of Management Interface, +1 for Data Interface - uint8_t itf_data_alt; // Alternate setting of Data Interface. 0 : inactive, 1 : active - - uint8_t ep_notif; - uint8_t ep_in; - uint8_t ep_out; - - bool ecm_mode; - - // Endpoint descriptor use to open/close when receving SetInterface - // TODO since configuration descriptor may not be long-lived memory, we should - // keep a copy of endpoint attribute instead - uint8_t const * ecm_desc_epdata; - -} netd_interface_t; - -#define CFG_TUD_NET_PACKET_PREFIX_LEN sizeof(rndis_data_packet_t) -#define CFG_TUD_NET_PACKET_SUFFIX_LEN 0 - -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t received[CFG_TUD_NET_PACKET_PREFIX_LEN + CFG_TUD_NET_MTU + CFG_TUD_NET_PACKET_PREFIX_LEN]; -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t transmitted[CFG_TUD_NET_PACKET_PREFIX_LEN + CFG_TUD_NET_MTU + CFG_TUD_NET_PACKET_PREFIX_LEN]; - -struct ecm_notify_struct -{ - tusb_control_request_t header; - uint32_t downlink, uplink; -}; - -static const struct ecm_notify_struct ecm_notify_nc = -{ - .header = { - .bmRequestType = 0xA1, - .bRequest = 0 /* NETWORK_CONNECTION aka NetworkConnection */, - .wValue = 1 /* Connected */, - .wLength = 0, - }, -}; - -static const struct ecm_notify_struct ecm_notify_csc = -{ - .header = { - .bmRequestType = 0xA1, - .bRequest = 0x2A /* CONNECTION_SPEED_CHANGE aka ConnectionSpeedChange */, - .wLength = 8, - }, - .downlink = 9728000, - .uplink = 9728000, -}; - -// TODO remove CFG_TUSB_MEM_SECTION, control internal buffer is already in this special section -CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static union -{ - uint8_t rndis_buf[120]; - struct ecm_notify_struct ecm_buf; -} notify; - -//--------------------------------------------------------------------+ -// INTERNAL OBJECT & FUNCTION DECLARATION -//--------------------------------------------------------------------+ -// TODO remove CFG_TUSB_MEM_SECTION -CFG_TUSB_MEM_SECTION static netd_interface_t _netd_itf; - -static bool can_xmit; - -void tud_network_recv_renew(void) -{ - usbd_edpt_xfer(TUD_OPT_RHPORT, _netd_itf.ep_out, received, sizeof(received)); -} - -static void do_in_xfer(uint8_t *buf, uint16_t len) -{ - can_xmit = false; - usbd_edpt_xfer(TUD_OPT_RHPORT, _netd_itf.ep_in, buf, len); -} - -void netd_report(uint8_t *buf, uint16_t len) -{ - // skip if previous report not yet acknowledged by host - if ( usbd_edpt_busy(TUD_OPT_RHPORT, _netd_itf.ep_notif) ) return; - usbd_edpt_xfer(TUD_OPT_RHPORT, _netd_itf.ep_notif, buf, len); -} - -//--------------------------------------------------------------------+ -// USBD Driver API -//--------------------------------------------------------------------+ -void netd_init(void) -{ - tu_memclr(&_netd_itf, sizeof(_netd_itf)); -} - -void netd_reset(uint8_t rhport) -{ - (void) rhport; - - netd_init(); -} - -uint16_t netd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len) -{ - bool const is_rndis = (TUD_RNDIS_ITF_CLASS == itf_desc->bInterfaceClass && - TUD_RNDIS_ITF_SUBCLASS == itf_desc->bInterfaceSubClass && - TUD_RNDIS_ITF_PROTOCOL == itf_desc->bInterfaceProtocol); - - bool const is_ecm = (TUSB_CLASS_CDC == itf_desc->bInterfaceClass && - CDC_COMM_SUBCLASS_ETHERNET_CONTROL_MODEL == itf_desc->bInterfaceSubClass && - 0x00 == itf_desc->bInterfaceProtocol); - - TU_VERIFY(is_rndis || is_ecm, 0); - - // confirm interface hasn't already been allocated - TU_ASSERT(0 == _netd_itf.ep_notif, 0); - - // sanity check the descriptor - _netd_itf.ecm_mode = is_ecm; - - //------------- Management Interface -------------// - _netd_itf.itf_num = itf_desc->bInterfaceNumber; - - uint16_t drv_len = sizeof(tusb_desc_interface_t); - uint8_t const * p_desc = tu_desc_next( itf_desc ); - - // Communication Functional Descriptors - while ( TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc) && drv_len <= max_len ) - { - drv_len += tu_desc_len(p_desc); - p_desc = tu_desc_next(p_desc); - } - - // notification endpoint (if any) - if ( TUSB_DESC_ENDPOINT == tu_desc_type(p_desc) ) - { - TU_ASSERT( usbd_edpt_open(rhport, (tusb_desc_endpoint_t const *) p_desc), 0 ); - - _netd_itf.ep_notif = ((tusb_desc_endpoint_t const *) p_desc)->bEndpointAddress; - - drv_len += tu_desc_len(p_desc); - p_desc = tu_desc_next(p_desc); - } - - //------------- Data Interface -------------// - // - RNDIS Data followed immediately by a pair of endpoints - // - CDC-ECM data interface has 2 alternate settings - // - 0 : zero endpoints for inactive (default) - // - 1 : IN & OUT endpoints for active networking - TU_ASSERT(TUSB_DESC_INTERFACE == tu_desc_type(p_desc), 0); - - do - { - tusb_desc_interface_t const * data_itf_desc = (tusb_desc_interface_t const *) p_desc; - TU_ASSERT(TUSB_CLASS_CDC_DATA == data_itf_desc->bInterfaceClass, 0); - - drv_len += tu_desc_len(p_desc); - p_desc = tu_desc_next(p_desc); - }while( _netd_itf.ecm_mode && (TUSB_DESC_INTERFACE == tu_desc_type(p_desc)) && (drv_len <= max_len) ); - - // Pair of endpoints - TU_ASSERT(TUSB_DESC_ENDPOINT == tu_desc_type(p_desc), 0); - - if ( _netd_itf.ecm_mode ) - { - // ECM by default is in-active, save the endpoint attribute - // to open later when received setInterface - _netd_itf.ecm_desc_epdata = p_desc; - }else - { - // Open endpoint pair for RNDIS - TU_ASSERT( usbd_open_edpt_pair(rhport, p_desc, 2, TUSB_XFER_BULK, &_netd_itf.ep_out, &_netd_itf.ep_in), 0 ); - - tud_network_init_cb(); - - // we are ready to transmit a packet - can_xmit = true; - - // prepare for incoming packets - tud_network_recv_renew(); - } - - drv_len += 2*sizeof(tusb_desc_endpoint_t); - - return drv_len; -} - -static void ecm_report(bool nc) -{ - notify.ecm_buf = (nc) ? ecm_notify_nc : ecm_notify_csc; - notify.ecm_buf.header.wIndex = _netd_itf.itf_num; - netd_report((uint8_t *)¬ify.ecm_buf, (nc) ? sizeof(notify.ecm_buf.header) : sizeof(notify.ecm_buf)); -} - -// Invoked when a control transfer occurred on an interface of this class -// Driver response accordingly to the request and the transfer stage (setup/data/ack) -// return false to stall control endpoint (e.g unsupported request) -bool netd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t const * request) -{ - if ( stage == CONTROL_STAGE_SETUP ) - { - switch ( request->bmRequestType_bit.type ) - { - case TUSB_REQ_TYPE_STANDARD: - switch ( request->bRequest ) - { - case TUSB_REQ_GET_INTERFACE: - { - uint8_t const req_itfnum = (uint8_t) request->wIndex; - TU_VERIFY(_netd_itf.itf_num+1 == req_itfnum); - - tud_control_xfer(rhport, request, &_netd_itf.itf_data_alt, 1); - } - break; - - case TUSB_REQ_SET_INTERFACE: - { - uint8_t const req_itfnum = (uint8_t) request->wIndex; - uint8_t const req_alt = (uint8_t) request->wValue; - - // Only valid for Data Interface with Alternate is either 0 or 1 - TU_VERIFY(_netd_itf.itf_num+1 == req_itfnum && req_alt < 2); - - // ACM-ECM only: qequest to enable/disable network activities - TU_VERIFY(_netd_itf.ecm_mode); - - _netd_itf.itf_data_alt = req_alt; - - if ( _netd_itf.itf_data_alt ) - { - // TODO since we don't actually close endpoint - // hack here to not re-open it - if ( _netd_itf.ep_in == 0 && _netd_itf.ep_out == 0 ) - { - TU_ASSERT(_netd_itf.ecm_desc_epdata); - TU_ASSERT( usbd_open_edpt_pair(rhport, _netd_itf.ecm_desc_epdata, 2, TUSB_XFER_BULK, &_netd_itf.ep_out, &_netd_itf.ep_in) ); - - // TODO should be merge with RNDIS's after endpoint opened - // Also should have opposite callback for application to disable network !! - tud_network_init_cb(); - can_xmit = true; // we are ready to transmit a packet - tud_network_recv_renew(); // prepare for incoming packets - } - }else - { - // TODO close the endpoint pair - // For now pretend that we did, this should have no harm since host won't try to - // communicate with the endpoints again - // _netd_itf.ep_in = _netd_itf.ep_out = 0 - } - - tud_control_status(rhport, request); - } - break; - - // unsupported request - default: return false; - } - break; - - case TUSB_REQ_TYPE_CLASS: - TU_VERIFY (_netd_itf.itf_num == request->wIndex); - - if (_netd_itf.ecm_mode) - { - /* the only required CDC-ECM Management Element Request is SetEthernetPacketFilter */ - if (0x43 /* SET_ETHERNET_PACKET_FILTER */ == request->bRequest) - { - tud_control_xfer(rhport, request, NULL, 0); - ecm_report(true); - } - } - else - { - if (request->bmRequestType_bit.direction == TUSB_DIR_IN) - { - rndis_generic_msg_t *rndis_msg = (rndis_generic_msg_t *) ((void*) notify.rndis_buf); - uint32_t msglen = tu_le32toh(rndis_msg->MessageLength); - TU_ASSERT(msglen <= sizeof(notify.rndis_buf)); - tud_control_xfer(rhport, request, notify.rndis_buf, msglen); - } - else - { - tud_control_xfer(rhport, request, notify.rndis_buf, sizeof(notify.rndis_buf)); - } - } - break; - - // unsupported request - default: return false; - } - } - else if ( stage == CONTROL_STAGE_DATA ) - { - // Handle RNDIS class control OUT only - if (request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS && - request->bmRequestType_bit.direction == TUSB_DIR_OUT && - _netd_itf.itf_num == request->wIndex) - { - if ( !_netd_itf.ecm_mode ) - { - rndis_class_set_handler(notify.rndis_buf, request->wLength); - } - } - } - - return true; -} - -static void handle_incoming_packet(uint32_t len) -{ - uint8_t *pnt = received; - uint32_t size = 0; - - if (_netd_itf.ecm_mode) - { - size = len; - } - else - { - rndis_data_packet_t *r = (rndis_data_packet_t *) ((void*) pnt); - if (len >= sizeof(rndis_data_packet_t)) - if ( (r->MessageType == REMOTE_NDIS_PACKET_MSG) && (r->MessageLength <= len)) - if ( (r->DataOffset + offsetof(rndis_data_packet_t, DataOffset) + r->DataLength) <= len) - { - pnt = &received[r->DataOffset + offsetof(rndis_data_packet_t, DataOffset)]; - size = r->DataLength; - } - } - - if (!tud_network_recv_cb(pnt, size)) - { - /* if a buffer was never handled by user code, we must renew on the user's behalf */ - tud_network_recv_renew(); - } -} - -bool netd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) -{ - (void) rhport; - (void) result; - - /* new packet received */ - if ( ep_addr == _netd_itf.ep_out ) - { - handle_incoming_packet(xferred_bytes); - } - - /* data transmission finished */ - if ( ep_addr == _netd_itf.ep_in ) - { - /* TinyUSB requires the class driver to implement ZLP (since ZLP usage is class-specific) */ - - if ( xferred_bytes && (0 == (xferred_bytes % CFG_TUD_NET_ENDPOINT_SIZE)) ) - { - do_in_xfer(NULL, 0); /* a ZLP is needed */ - } - else - { - /* we're finally finished */ - can_xmit = true; - } - } - - if ( _netd_itf.ecm_mode && (ep_addr == _netd_itf.ep_notif) ) - { - if (sizeof(notify.ecm_buf.header) == xferred_bytes) ecm_report(false); - } - - return true; -} - -bool tud_network_can_xmit(uint16_t size) -{ - (void)size; - - return can_xmit; -} - -void tud_network_xmit(void *ref, uint16_t arg) -{ - uint8_t *data; - uint16_t len; - - if (!can_xmit) - return; - - len = (_netd_itf.ecm_mode) ? 0 : CFG_TUD_NET_PACKET_PREFIX_LEN; - data = transmitted + len; - - len += tud_network_xmit_cb(data, ref, arg); - - if (!_netd_itf.ecm_mode) - { - rndis_data_packet_t *hdr = (rndis_data_packet_t *) ((void*) transmitted); - memset(hdr, 0, sizeof(rndis_data_packet_t)); - hdr->MessageType = REMOTE_NDIS_PACKET_MSG; - hdr->MessageLength = len; - hdr->DataOffset = sizeof(rndis_data_packet_t) - offsetof(rndis_data_packet_t, DataOffset); - hdr->DataLength = len - sizeof(rndis_data_packet_t); - } - - do_in_xfer(transmitted, len); -} - -#endif diff --git a/src/class/net/ncm_device.c b/src/class/net/ncm_device.c index 1f592401e..2f7d58f99 100644 --- a/src/class/net/ncm_device.c +++ b/src/class/net/ncm_device.c @@ -28,7 +28,7 @@ #include "tusb_option.h" -#if ( TUSB_OPT_DEVICE_ENABLED && CFG_TUD_NET && CFG_TUD_NCM ) +#if ( TUSB_OPT_DEVICE_ENABLED && CFG_TUD_NCM ) #include "device/usbd.h" #include "device/usbd_pvt.h" @@ -131,18 +131,18 @@ typedef struct //--------------------------------------------------------------------+ CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static const ntb_parameters_t ntb_parameters = { - .wLength = sizeof(ntb_parameters_t), - .bmNtbFormatsSupported = 0x01, - .dwNtbInMaxSize = CFG_TUD_NCM_IN_NTB_MAX_SIZE, - .wNdbInDivisor = 4, - .wNdbInPayloadRemainder = 0, - .wNdbInAlignment = CFG_TUD_NCM_ALIGNMENT, - .wReserved = 0, - .dwNtbOutMaxSize = CFG_TUD_NCM_OUT_NTB_MAX_SIZE, - .wNdbOutDivisor = 4, + .wLength = sizeof(ntb_parameters_t), + .bmNtbFormatsSupported = 0x01, + .dwNtbInMaxSize = CFG_TUD_NCM_IN_NTB_MAX_SIZE, + .wNdbInDivisor = 4, + .wNdbInPayloadRemainder = 0, + .wNdbInAlignment = CFG_TUD_NCM_ALIGNMENT, + .wReserved = 0, + .dwNtbOutMaxSize = CFG_TUD_NCM_OUT_NTB_MAX_SIZE, + .wNdbOutDivisor = 4, .wNdbOutPayloadRemainder = 0, - .wNdbOutAlignment = CFG_TUD_NCM_ALIGNMENT, - .wNtbOutMaxDatagrams = 0 + .wNdbOutAlignment = CFG_TUD_NCM_ALIGNMENT, + .wNtbOutMaxDatagrams = 0 }; CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static transmit_ntb_t transmit_ntb[2]; diff --git a/src/class/net/net_device.h b/src/class/net/net_device.h index e6cdc8b8b..ad369b680 100644 --- a/src/class/net/net_device.h +++ b/src/class/net/net_device.h @@ -30,10 +30,14 @@ #include "class/cdc/cdc.h" +#if CFG_TUD_ECM_RNDIS && CFG_TUD_NCM +#error "Cannot enable both ECM_RNDIS and NCM network drivers" +#endif + /* declared here, NOT in usb_descriptors.c, so that the driver can intelligently ZLP as needed */ #define CFG_TUD_NET_ENDPOINT_SIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) -/* Maximum Tranmission Unit (in bytes) of the network, including Ethernet header */ +/* Maximum Transmission Unit (in bytes) of the network, including Ethernet header */ #ifndef CFG_TUD_NET_MTU #define CFG_TUD_NET_MTU 1514 #endif @@ -62,8 +66,18 @@ // Application API //--------------------------------------------------------------------+ -// client must provide this: initialize any network state back to the beginning -void tud_network_init_cb(void); +// indicate to network driver that client has finished with the packet provided to network_recv_cb() +void tud_network_recv_renew(void); + +// poll network driver for its ability to accept another packet to transmit +bool tud_network_can_xmit(uint16_t size); + +// if network_can_xmit() returns true, network_xmit() can be called once +void tud_network_xmit(void *ref, uint16_t arg); + +//--------------------------------------------------------------------+ +// Application Callbacks (WEAK is optional) +//--------------------------------------------------------------------+ // client must provide this: return false if the packet buffer was not accepted bool tud_network_recv_cb(const uint8_t *src, uint16_t size); @@ -71,18 +85,16 @@ bool tud_network_recv_cb(const uint8_t *src, uint16_t size); // client must provide this: copy from network stack packet pointer to dst uint16_t tud_network_xmit_cb(uint8_t *dst, void *ref, uint16_t arg); +//------------- ECM/RNDIS -------------// + +// client must provide this: initialize any network state back to the beginning +void tud_network_init_cb(void); + // client must provide this: 48-bit MAC address // TODO removed later since it is not part of tinyusb stack extern const uint8_t tud_network_mac_address[6]; -// indicate to network driver that client has finished with the packet provided to network_recv_cb() -void tud_network_recv_renew(void); - -// poll network driver for its ability to accept another packet to transmit -bool tud_network_can_xmit(uint16_t size); - -// if network_can_xmit() returns true, network_xmit() can be called once -void tud_network_xmit(void *ref, uint16_t arg); +//------------- NCM -------------// // callback to client providing optional indication of internal state of network driver void tud_network_link_state_cb(bool state); diff --git a/src/device/usbd.c b/src/device/usbd.c index a33d778db..ab1837895 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -203,7 +203,7 @@ static usbd_class_driver_t const _usbd_driver[] = }, #endif - #if CFG_TUD_NET + #if CFG_TUD_ECM_RNDIS || CFG_TUD_NCM { DRIVER_NAME("NET") .init = netd_init, diff --git a/src/tusb.h b/src/tusb.h index b52f8839a..2e1b7a43d 100644 --- a/src/tusb.h +++ b/src/tusb.h @@ -100,7 +100,7 @@ #include "class/dfu/dfu_device.h" #endif - #if CFG_TUD_NET + #if CFG_TUD_ECM_RNDIS || CFG_TUD_NCM #include "class/net/net_device.h" #endif diff --git a/src/tusb_option.h b/src/tusb_option.h index 3cb672d80..369c35e2d 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -261,16 +261,16 @@ #define CFG_TUD_DFU 0 #endif -#ifndef CFG_TUD_NET - #define CFG_TUD_NET 0 -#endif - #ifndef CFG_TUD_BTH #define CFG_TUD_BTH 0 #endif +#ifndef CFG_TUD_ECM_RNDIS + #define CFG_TUD_ECM_RNDIS 0 +#endif + #ifndef CFG_TUD_NCM - #define CFG_TUD_NCM 0 + #define CFG_TUD_NCM 0 #endif //-------------------------------------------------------------------- -- cgit v1.3.1 From 6fd62c8902915b987d600cd17e70383cbef78802 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 5 Oct 2021 16:06:54 +0700 Subject: update docs --- CONTRIBUTORS.rst | 23 +++++++++++++---------- README.rst | 2 +- 2 files changed, 14 insertions(+), 11 deletions(-) diff --git a/CONTRIBUTORS.rst b/CONTRIBUTORS.rst index 040f40166..cd1c19373 100644 --- a/CONTRIBUTORS.rst +++ b/CONTRIBUTORS.rst @@ -31,6 +31,12 @@ Notable contributors - Improve ESP32s2 DCD +`Jacob Berg Potter `__ +------------------------------------------------ + +- Add new class driver for network CDC-NCM + + `Jan Dümpelmann `__ ----------------------------------------------- @@ -93,9 +99,9 @@ Notable contributors ------------------------------------------------ - Add new DCD port for Nuvoton NUC 120, 121, 125, 126, 505 -- Add new class driver for USBNET RNDIS, CDC-ECM -- Add *net\_lwip\_webserver* example for demonstration of usbnet with - lwip +- Add new class driver for network RNDIS, CDC-ECM +- Enhance NCM network driver to compatible with RNDIS/ECM +- Add *net\_lwip\_webserver* example for demonstration of usbnet with lwip - Board support for NuTiny NUC120, NUC121s, NUC125s, NUC126V, NUC505 - Improve multiple cdc interfaces API & add cdc\_dual\_ports example @@ -118,10 +124,8 @@ Notable contributors ------------------------------------------------ - Add new class driver for USB Audio Class 2.0 (UAC2) -- Rework tu\_fifo with unmasked pointer, add DMA support, and constant - address support -- Add new DCD/USBD edpt\_xfer\_fifo() API for optimizing endpoint - transfer +- Rework tu\_fifo with unmasked pointer, add DMA support, and constant address support +- Add new DCD/USBD edpt\_xfer\_fifo() API for optimizing endpoint transfer - Add and greatly improve Isochronous transfer - Add new audio examples: audio\_test and audio\_4\_channel\_mic @@ -130,8 +134,7 @@ Notable contributors ------------------------------------------------ - Add new DCD port for SAMD21 and SAMD51 -- Add new class driver for Musical Instrument Digital Interface - (MIDI) +- Add new class driver for Musical Instrument Digital Interface (MIDI) - Improve USBD control transfer, MSC, CDC class driver - Board support for Metro M0 & M4 express - Write the excellent porting.md documentation @@ -178,7 +181,7 @@ Notable contributors `Zixun Li `__ ------------------------------------------------ +------------------------------------------- - Add new DCD port for Microchip SAMx7x - Add IAR compiler support diff --git a/README.rst b/README.rst index 52738da32..5eecd63ac 100644 --- a/README.rst +++ b/README.rst @@ -65,7 +65,7 @@ Supports multiple device configurations by dynamically changing USB descriptors, - Human Interface Device (HID): Generic (In & Out), Keyboard, Mouse, Gamepad etc ... - Mass Storage Class (MSC): with multiple LUNs - Musical Instrument Digital Interface (MIDI) -- Network with RNDIS, CDC-ECM (work in progress) +- Network with RNDIS, Ethernet Control Model (ECM), Network Control Model (NCM) - USB Test and Measurement Class (USBTMC) - Vendor-specific class support with generic In & Out endpoints. Can be used with MS OS 2.0 compatible descriptor to load winUSB driver without INF file. - `WebUSB `__ with vendor-specific class -- cgit v1.3.1 From 98ab8117d68f05bb36b9aeb857273e896199bc6a Mon Sep 17 00:00:00 2001 From: Scott Shawcroft Date: Tue, 5 Oct 2021 18:20:44 -0700 Subject: USB seems to init ok --- .gitmodules | 4 ++++ hw/bsp/raspberrypi4/family.c | 18 ++++++++++++------ hw/bsp/raspberrypi4/family.mk | 16 +++++++++------- hw/mcu/broadcom | 1 + 4 files changed, 26 insertions(+), 13 deletions(-) create mode 160000 hw/mcu/broadcom diff --git a/.gitmodules b/.gitmodules index 4c86fd55c..95f35d270 100644 --- a/.gitmodules +++ b/.gitmodules @@ -127,3 +127,7 @@ [submodule "hw/mcu/gd/nuclei-sdk"] path = hw/mcu/gd/nuclei-sdk url = https://github.com/Nuclei-Software/nuclei-sdk.git +[submodule "hw/mcu/broadcom"] + path = hw/mcu/broadcom + url = git@github.com:adafruit/broadcom-peripherals.git + branch = main-build diff --git a/hw/bsp/raspberrypi4/family.c b/hw/bsp/raspberrypi4/family.c index 6266d5a35..fe7e429d6 100644 --- a/hw/bsp/raspberrypi4/family.c +++ b/hw/bsp/raspberrypi4/family.c @@ -27,8 +27,9 @@ #include "bsp/board.h" #include "board.h" -#include "io.h" -#include "mmu.h" +#include "broadcom/io.h" +#include "broadcom/mmu.h" +#include "broadcom/vcmailbox.h" //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler @@ -46,9 +47,8 @@ void OTG_FS_IRQHandler(void) // Board porting API //--------------------------------------------------------------------+ -void print(void) { - const char* greeting2 = "hello from cm100\r\n"; - board_uart_write(greeting2, strlen(greeting2)); +void print(const char* str) { + board_uart_write(str, strlen(str)); } void board_init(void) @@ -83,7 +83,7 @@ void board_init(void) board_uart_write(greeting, strlen(greeting)); // gpio_setPinOutputBool(24, false); // gpio_setPinOutputBool(25, true); - print(); + // print(); // gpio_setPinOutputBool(25, false); // while (true) { // // for (size_t i = 0; i < 5; i++) { @@ -97,6 +97,12 @@ void board_init(void) // gpio_setPinOutputBool(42, false); // } // while (1) uart_update(); + + // Turn on USB peripheral. + print("Turning on USB power\r\n"); + + vcmailbox_set_power_state(VCMAILBOX_DEVICE_USB_HCD, true); + print("USB power on\r\n"); } void board_led_write(bool state) diff --git a/hw/bsp/raspberrypi4/family.mk b/hw/bsp/raspberrypi4/family.mk index 1547beee1..b36a83b48 100644 --- a/hw/bsp/raspberrypi4/family.mk +++ b/hw/bsp/raspberrypi4/family.mk @@ -2,7 +2,7 @@ UF2_FAMILY_ID = 0x57755a57 include $(TOP)/$(BOARD_PATH)/board.mk -MCU_DIR = hw/mcu/broadcom/bcm2711 +MCU_DIR = hw/mcu/broadcom CC = clang @@ -18,21 +18,23 @@ CFLAGS += \ SRC_C += \ src/portable/broadcom/synopsys/dcd_synopsys.c \ - $(MCU_DIR)/interrupts.c \ - $(MCU_DIR)/io.c \ - $(MCU_DIR)/mmu.c + $(MCU_DIR)/broadcom/interrupts.c \ + $(MCU_DIR)/broadcom/io.c \ + $(MCU_DIR)/broadcom/mmu.c \ + $(MCU_DIR)/broadcom/vcmailbox.c CROSS_COMPILE = aarch64-none-elf- SKIP_NANOLIB = 1 -LD_FILE = $(MCU_DIR)/link.ld +LD_FILE = $(MCU_DIR)/broadcom/link.ld INC += \ $(TOP)/$(BOARD_PATH) \ - $(TOP)/$(MCU_DIR) + $(TOP)/$(MCU_DIR) \ + $(TOP)/lib/CMSIS_5/CMSIS/Core_A/Include -SRC_S += $(MCU_DIR)/boot.S +SRC_S += $(MCU_DIR)/broadcom/boot.S $(BUILD)/kernel8.img: $(BUILD)/$(PROJECT).elf $(OBJCOPY) -O binary $^ $@ diff --git a/hw/mcu/broadcom b/hw/mcu/broadcom new file mode 160000 index 000000000..c24e8f689 --- /dev/null +++ b/hw/mcu/broadcom @@ -0,0 +1 @@ +Subproject commit c24e8f6898d7cf8e2884eb70dbabd97480526450 -- cgit v1.3.1 From a8eea9f6a540ef5c6314c400754364e0456002cd Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 9 Oct 2021 11:28:55 +0700 Subject: add backward compatible with warnings for CFG_TUD_NET --- src/tusb_option.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/tusb_option.h b/src/tusb_option.h index 057bc61c2..cda8c45ce 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -266,7 +266,12 @@ #endif #ifndef CFG_TUD_ECM_RNDIS - #define CFG_TUD_ECM_RNDIS 0 + #ifdef CFG_TUD_NET + #warning "CFG_TUD_NET is renamed to CFG_TUD_ECM_RNDIS" + #define CFG_TUD_ECM_RNDIS CFG_TUD_NET + #else + #define CFG_TUD_ECM_RNDIS 0 + #endif #endif #ifndef CFG_TUD_NCM -- cgit v1.3.1 From a3a18c9ed33a4d6f2027dc46ab32c62314d1abef Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Sat, 9 Oct 2021 19:51:51 +0900 Subject: Change the video image to scrolling color bars. --- examples/device/video_capture/src/images.h | 9339 ++++---------------- examples/device/video_capture/src/main.c | 74 +- .../device/video_capture/src/usb_descriptors.h | 8 +- hw/bsp/frdm_kl25z/board.mk | 3 +- 4 files changed, 1717 insertions(+), 7707 deletions(-) diff --git a/examples/device/video_capture/src/images.h b/examples/device/video_capture/src/images.h index a55353d91..1b13cfe81 100644 --- a/examples/device/video_capture/src/images.h +++ b/examples/device/video_capture/src/images.h @@ -1,7690 +1,1651 @@ -static const unsigned char white_128x96_yuv[] = { - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 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0x80, 0x80, 0x80, 0x80, 0x80, 0x80, - 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, - 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, - 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, - 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, - 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, - 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, - 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, - 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, - 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, - 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, - 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80 -}; -static const unsigned char t_128x96_yuv[] = { - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 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0x80, 0x80, - 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, - 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, - 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, - 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, - 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, - 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, - 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, - 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, - 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80 -}; -static const unsigned char ti_128x96_yuv[] = { - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 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0x80, 0x80, 0x80, 0x80, 0x80, 0x80, - 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, - 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, - 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, - 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80 -}; -static const unsigned char logo_128x96_yuv[] = { - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 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0x80, 0x80, 0x80, - 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, - 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80 +static const unsigned char frame_buffer[128 * (96 + 1) * 2] = { + /* 0 */ + 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, + 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, + 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, + 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, + 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, + 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, + 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, + 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 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0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, + 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, + 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, + 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, + 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, + /* 93 */ + 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, + 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, + 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, + 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, + 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, + 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, + 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, + 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, + 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, + 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, + 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, + 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, + 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, + 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, + 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, + 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, + /* 94 */ + 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, + 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, + 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, + 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, + 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, + 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, + 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, + 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, + 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, + 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, + 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, + 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, + 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, + 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, + 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, + 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, + /* 95 */ + 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, + 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, + 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, + 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, + 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, + 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, + 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, + 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, + 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, + 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, + 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, + 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, + 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, + 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, + 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, + 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, + /* 96 */ + 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, + 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, + 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, + 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, + 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, + 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, + 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, + 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, + 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, + 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, + 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, + 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, + 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, + 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, + 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, + 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, }; diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c index b76af071a..f0f4df6eb 100644 --- a/examples/device/video_capture/src/main.c +++ b/examples/device/video_capture/src/main.c @@ -31,7 +31,6 @@ #include "tusb.h" #include "usb_descriptors.h" -#include "images.h" //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF PROTYPES //--------------------------------------------------------------------+ @@ -104,15 +103,54 @@ void tud_resume_cb(void) //--------------------------------------------------------------------+ // USB Video //--------------------------------------------------------------------+ -static unsigned char const *frames[] = { - white_128x96_yuv, white_128x96_yuv, white_128x96_yuv, - t_128x96_yuv, ti_128x96_yuv, tin_128x96_yuv, logo_128x96_yuv, - logo_128x96_yuv, logo_128x96_yuv, logo_128x96_yuv, logo_128x96_yuv -}; -static unsigned current_frame = 0; +static unsigned frame_num = 0; static unsigned tx_busy = 0; static unsigned interval_ms = 1000 / FRAME_RATE; +/* YUY2 frame buffer */ +#ifdef CFG_EXAMPLE_VIDEO_READONLY +#include "images.h" +#else +static uint8_t frame_buffer[FRAME_WIDTH * FRAME_HEIGHT * 16 / 8]; +static void fill_color_bar(uint8_t *buffer, unsigned start_position) +{ + /* EBU color bars + * See also https://stackoverflow.com/questions/6939422 */ + static uint8_t const bar_color[8][4] = { + /* Y, U, Y, V */ + { 235, 128, 235, 128}, /* 100% White */ + { 219, 16, 219, 138}, /* Yellow */ + { 188, 154, 188, 16}, /* Cyan */ + { 173, 42, 173, 26}, /* Green */ + { 78, 214, 78, 230}, /* Magenta */ + { 63, 102, 63, 240}, /* Red */ + { 32, 240, 32, 118}, /* Blue */ + { 16, 128, 16, 128}, /* Black */ + }; + uint8_t *p; + + /* Generate the 1st line */ + uint8_t *end = &buffer[FRAME_WIDTH * 2]; + unsigned idx = (FRAME_WIDTH / 2 - 1) - (start_position % (FRAME_WIDTH / 2)); + p = &buffer[idx * 4]; + for (unsigned i = 0; i < 8; ++i) { + for (int j = 0; j < FRAME_WIDTH / (2 * 8); ++j) { + memcpy(p, &bar_color[i], 4); + p += 4; + if (end <= p) { + p = buffer; + } + } + } + /* Duplicate the 1st line to the others */ + p = &buffer[FRAME_WIDTH * 2]; + for (unsigned i = 1; i < FRAME_HEIGHT; ++i) { + memcpy(p, buffer, FRAME_WIDTH * 2); + p += FRAME_WIDTH * 2; + } +} +#endif + void video_task(void) { static unsigned start_ms = 0; @@ -120,14 +158,20 @@ void video_task(void) if (!tud_video_n_streaming(0, 0)) { already_sent = 0; - current_frame = 0; + frame_num = 0; return; } if (!already_sent) { already_sent = 1; start_ms = board_millis(); - tud_video_n_frame_xfer(0, 0, (void*)frames[current_frame], FRAME_WIDTH * FRAME_HEIGHT * 12/8); +#ifdef CFG_EXAMPLE_VIDEO_READONLY + tud_video_n_frame_xfer(0, 0, (void*)&frame_buffer[(frame_num % (FRAME_WIDTH / 2)) * 4], + FRAME_WIDTH * FRAME_HEIGHT * 16/8); +#else + fill_color_bar(frame_buffer, frame_num); + tud_video_n_frame_xfer(0, 0, (void*)frame_buffer, FRAME_WIDTH * FRAME_HEIGHT * 16/8); +#endif } unsigned cur = board_millis(); @@ -135,7 +179,13 @@ void video_task(void) if (tx_busy) return; start_ms += interval_ms; - tud_video_n_frame_xfer(0, 0, (void*)frames[current_frame], FRAME_WIDTH * FRAME_HEIGHT * 12/8); +#ifdef CFG_EXAMPLE_VIDEO_READONLY + tud_video_n_frame_xfer(0, 0, (void*)&frame_buffer[(frame_num % (FRAME_WIDTH / 2)) * 4], + FRAME_WIDTH * FRAME_HEIGHT * 16/8); +#else + fill_color_bar(frame_buffer, frame_num); + tud_video_n_frame_xfer(0, 0, (void*)frame_buffer, FRAME_WIDTH * FRAME_HEIGHT * 16/8); +#endif } void tud_video_frame_xfer_complete_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx) @@ -143,9 +193,7 @@ void tud_video_frame_xfer_complete_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx (void)ctl_idx; (void)stm_idx; tx_busy = 0; /* flip buffer */ - ++current_frame; - if (current_frame == sizeof(frames)/sizeof(frames[0])) - current_frame = 0; + ++frame_num; } int tud_video_commit_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, diff --git a/examples/device/video_capture/src/usb_descriptors.h b/examples/device/video_capture/src/usb_descriptors.h index e52703b29..403dc56a1 100644 --- a/examples/device/video_capture/src/usb_descriptors.h +++ b/examples/device/video_capture/src/usb_descriptors.h @@ -61,7 +61,7 @@ enum { + 7/* Endpoint */\ ) -/* Windows support YUV2 and NV12 +/* Windows support YUY2 and NV12 * https://docs.microsoft.com/en-us/windows-hardware/drivers/stream/usb-video-class-driver-overview */ #define TUD_VIDEO_DESC_CS_VS_FMT_YUY2(_fmtidx, _numfmtdesc, _frmidx, _asrx, _asry, _interlace, _cp) \ @@ -97,12 +97,12 @@ enum { /*bStillCaptureMethod*/0, /*bTriggerSupport*/0, /*bTriggerUsage*/0, \ /*bmaControls(1)*/0), \ /* Video stream format */ \ - TUD_VIDEO_DESC_CS_VS_FMT_NV12(/*bFormatIndex*/1, /*bNumFrameDescriptors*/1,\ + TUD_VIDEO_DESC_CS_VS_FMT_YUY2(/*bFormatIndex*/1, /*bNumFrameDescriptors*/1, \ /*bDefaultFrameIndex*/1, 0, 0, 0, /*bCopyProtect*/0), \ /* Video stream frame format */ \ TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT(/*bFrameIndex */1, 0, _width, _height, \ - _width * _height * 12, _width * _height * 12 * _fps, \ - _width * _height * 12, \ + _width * _height * 16, _width * _height * 16 * _fps, \ + _width * _height * 16, \ (10000000/_fps), (10000000/_fps), 10000000, 100000), \ TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING(VIDEO_COLOR_PRIMARIES_BT709, VIDEO_COLOR_XFER_CH_BT709, VIDEO_COLOR_COEF_SMPTE170M), \ /* VS alt 1 */\ diff --git a/hw/bsp/frdm_kl25z/board.mk b/hw/bsp/frdm_kl25z/board.mk index bc9240e55..15bd50eda 100644 --- a/hw/bsp/frdm_kl25z/board.mk +++ b/hw/bsp/frdm_kl25z/board.mk @@ -6,7 +6,8 @@ CFLAGS += \ -mabi=aapcs \ -mcpu=cortex-m0plus \ -DCPU_MKL25Z128VLK4 \ - -DCFG_TUSB_MCU=OPT_MCU_MKL25ZXX + -DCFG_TUSB_MCU=OPT_MCU_MKL25ZXX \ + -DCFG_EXAMPLE_VIDEO_READONLY LDFLAGS += \ -Wl,--defsym,__stack_size__=0x400 \ -- cgit v1.3.1 From b6d09ca7619b2f624cc3ee92a795ba2a9b9d68e9 Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Sat, 9 Oct 2021 23:02:18 +0900 Subject: Add compile option to allocate video data into flash in video_capture example --- examples/device/video_capture/.skip.MCU_STM32F1 | 0 hw/bsp/imxrt/boards/mimxrt1010_evk/board.mk | 2 +- hw/bsp/imxrt/boards/mimxrt1015_evk/board.mk | 2 +- hw/bsp/lpc15/boards/lpcxpresso1549/board.mk | 1 + hw/bsp/lpcxpresso11u37/board.mk | 1 + hw/bsp/lpcxpresso1347/board.mk | 1 + hw/bsp/nutiny_nuc126v/board.mk | 1 + hw/bsp/nutiny_sdk_nuc120/board.mk | 1 + hw/bsp/samd21/boards/atsamd21_xpro/board.mk | 2 +- hw/bsp/samd21/boards/circuitplayground_express/board.mk | 2 +- hw/bsp/samd21/boards/curiosity_nano/board.mk | 2 +- hw/bsp/samd21/boards/feather_m0_express/board.mk | 2 +- hw/bsp/samd21/boards/itsybitsy_m0/board.mk | 2 +- hw/bsp/samd21/boards/luna_d21/board.mk | 2 +- hw/bsp/samd21/boards/metro_m0_express/board.mk | 2 +- hw/bsp/samd21/boards/seeeduino_xiao/board.mk | 2 +- hw/bsp/saml2x/boards/atsaml21_xpro/board.mk | 2 +- hw/bsp/saml2x/boards/saml22_feather/board.mk | 2 +- hw/bsp/saml2x/boards/sensorwatch_m0/board.mk | 2 +- hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk | 2 +- hw/bsp/stm32f0/boards/stm32f072disco/board.mk | 2 +- hw/bsp/stm32f0/boards/stm32f072eval/board.mk | 2 +- hw/bsp/stm32f1/boards/stm32f103_bluepill/board.mk | 2 +- hw/bsp/stm32l0538disco/board.mk | 1 + 24 files changed, 23 insertions(+), 17 deletions(-) delete mode 100644 examples/device/video_capture/.skip.MCU_STM32F1 diff --git a/examples/device/video_capture/.skip.MCU_STM32F1 b/examples/device/video_capture/.skip.MCU_STM32F1 deleted file mode 100644 index e69de29bb..000000000 diff --git a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.mk b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.mk index 507db7f00..17dc01cd9 100644 --- a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.mk +++ b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.mk @@ -1,4 +1,4 @@ -CFLAGS += -DCPU_MIMXRT1011DAE5A +CFLAGS += -DCPU_MIMXRT1011DAE5A -DCFG_EXAMPLE_VIDEO_READONLY MCU_VARIANT = MIMXRT1011 # For flash-jlink target diff --git a/hw/bsp/imxrt/boards/mimxrt1015_evk/board.mk b/hw/bsp/imxrt/boards/mimxrt1015_evk/board.mk index 17fd25dfe..20c697ea1 100644 --- a/hw/bsp/imxrt/boards/mimxrt1015_evk/board.mk +++ b/hw/bsp/imxrt/boards/mimxrt1015_evk/board.mk @@ -1,4 +1,4 @@ -CFLAGS += -DCPU_MIMXRT1015DAF5A +CFLAGS += -DCPU_MIMXRT1015DAF5A -DCFG_EXAMPLE_VIDEO_READONLY MCU_VARIANT = MIMXRT1015 # For flash-jlink target diff --git a/hw/bsp/lpc15/boards/lpcxpresso1549/board.mk b/hw/bsp/lpc15/boards/lpcxpresso1549/board.mk index a3e04cfa1..b00fc71b0 100644 --- a/hw/bsp/lpc15/boards/lpcxpresso1549/board.mk +++ b/hw/bsp/lpc15/boards/lpcxpresso1549/board.mk @@ -1,3 +1,4 @@ +CFLAGS += -DCFG_EXAMPLE_VIDEO_READONLY LD_FILE = $(BOARD_PATH)/lpc1549.ld JLINK_DEVICE = LPC1549 diff --git a/hw/bsp/lpcxpresso11u37/board.mk b/hw/bsp/lpcxpresso11u37/board.mk index 8fcda51ee..b736eebe1 100644 --- a/hw/bsp/lpcxpresso11u37/board.mk +++ b/hw/bsp/lpcxpresso11u37/board.mk @@ -9,6 +9,7 @@ CFLAGS += \ -DCORE_M0 \ -D__USE_LPCOPEN \ -DCFG_EXAMPLE_MSC_READONLY \ + -DCFG_EXAMPLE_VIDEO_READONLY \ -DCFG_TUSB_MCU=OPT_MCU_LPC11UXX \ -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM2")))' \ -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' diff --git a/hw/bsp/lpcxpresso1347/board.mk b/hw/bsp/lpcxpresso1347/board.mk index 0d56a33a6..62135c274 100644 --- a/hw/bsp/lpcxpresso1347/board.mk +++ b/hw/bsp/lpcxpresso1347/board.mk @@ -9,6 +9,7 @@ CFLAGS += \ -DCORE_M3 \ -D__USE_LPCOPEN \ -DCFG_EXAMPLE_MSC_READONLY \ + -DCFG_EXAMPLE_VIDEO_READONLY \ -DCFG_TUSB_MCU=OPT_MCU_LPC13XX \ -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM2")))' \ -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' diff --git a/hw/bsp/nutiny_nuc126v/board.mk b/hw/bsp/nutiny_nuc126v/board.mk index 848b19f95..e9df1ed13 100644 --- a/hw/bsp/nutiny_nuc126v/board.mk +++ b/hw/bsp/nutiny_nuc126v/board.mk @@ -7,6 +7,7 @@ CFLAGS += \ -mcpu=cortex-m0 \ -D__ARM_FEATURE_DSP=0 \ -DUSE_ASSERT=0 \ + -DCFG_EXAMPLE_VIDEO_READONLY \ -D__CORTEX_SC=0 \ -DCFG_TUSB_MCU=OPT_MCU_NUC126 diff --git a/hw/bsp/nutiny_sdk_nuc120/board.mk b/hw/bsp/nutiny_sdk_nuc120/board.mk index 90b3e91fb..1fde47c5a 100644 --- a/hw/bsp/nutiny_sdk_nuc120/board.mk +++ b/hw/bsp/nutiny_sdk_nuc120/board.mk @@ -6,6 +6,7 @@ CFLAGS += \ -mabi=aapcs-linux \ -mcpu=cortex-m0 \ -DCFG_EXAMPLE_MSC_READONLY \ + -DCFG_EXAMPLE_VIDEO_READONLY \ -DCFG_TUSB_MCU=OPT_MCU_NUC120 # All source paths should be relative to the top level. diff --git a/hw/bsp/samd21/boards/atsamd21_xpro/board.mk b/hw/bsp/samd21/boards/atsamd21_xpro/board.mk index 5cd82735c..4be547a1b 100644 --- a/hw/bsp/samd21/boards/atsamd21_xpro/board.mk +++ b/hw/bsp/samd21/boards/atsamd21_xpro/board.mk @@ -1,4 +1,4 @@ -CFLAGS += -D__SAMD21J18A__ +CFLAGS += -D__SAMD21J18A__ -DCFG_EXAMPLE_VIDEO_READONLY # All source paths should be relative to the top level. LD_FILE = $(BOARD_PATH)/samd21j18a_flash.ld diff --git a/hw/bsp/samd21/boards/circuitplayground_express/board.mk b/hw/bsp/samd21/boards/circuitplayground_express/board.mk index bb426cdaa..d6c9150b3 100644 --- a/hw/bsp/samd21/boards/circuitplayground_express/board.mk +++ b/hw/bsp/samd21/boards/circuitplayground_express/board.mk @@ -1,4 +1,4 @@ -CFLAGS += -D__SAMD21G18A__ +CFLAGS += -D__SAMD21G18A__ -DCFG_EXAMPLE_VIDEO_READONLY # All source paths should be relative to the top level. LD_FILE = $(BOARD_PATH)/$(BOARD).ld diff --git a/hw/bsp/samd21/boards/curiosity_nano/board.mk b/hw/bsp/samd21/boards/curiosity_nano/board.mk index ec3217f89..112fb6946 100644 --- a/hw/bsp/samd21/boards/curiosity_nano/board.mk +++ b/hw/bsp/samd21/boards/curiosity_nano/board.mk @@ -1,4 +1,4 @@ -CFLAGS += -D__SAMD21G17A__ -DCFG_EXAMPLE_MSC_READONLY +CFLAGS += -D__SAMD21G17A__ -DCFG_EXAMPLE_MSC_READONLY -DCFG_EXAMPLE_VIDEO_READONLY # All source paths should be relative to the top level. LD_FILE = $(BOARD_PATH)/samd21g17a_flash.ld diff --git a/hw/bsp/samd21/boards/feather_m0_express/board.mk b/hw/bsp/samd21/boards/feather_m0_express/board.mk index bb426cdaa..d6c9150b3 100644 --- a/hw/bsp/samd21/boards/feather_m0_express/board.mk +++ b/hw/bsp/samd21/boards/feather_m0_express/board.mk @@ -1,4 +1,4 @@ -CFLAGS += -D__SAMD21G18A__ +CFLAGS += -D__SAMD21G18A__ -DCFG_EXAMPLE_VIDEO_READONLY # All source paths should be relative to the top level. LD_FILE = $(BOARD_PATH)/$(BOARD).ld diff --git a/hw/bsp/samd21/boards/itsybitsy_m0/board.mk b/hw/bsp/samd21/boards/itsybitsy_m0/board.mk index bb426cdaa..d6c9150b3 100644 --- a/hw/bsp/samd21/boards/itsybitsy_m0/board.mk +++ b/hw/bsp/samd21/boards/itsybitsy_m0/board.mk @@ -1,4 +1,4 @@ -CFLAGS += -D__SAMD21G18A__ +CFLAGS += -D__SAMD21G18A__ -DCFG_EXAMPLE_VIDEO_READONLY # All source paths should be relative to the top level. LD_FILE = $(BOARD_PATH)/$(BOARD).ld diff --git a/hw/bsp/samd21/boards/luna_d21/board.mk b/hw/bsp/samd21/boards/luna_d21/board.mk index 5beb5e02d..27a634e3a 100644 --- a/hw/bsp/samd21/boards/luna_d21/board.mk +++ b/hw/bsp/samd21/boards/luna_d21/board.mk @@ -1,4 +1,4 @@ -CFLAGS += -D__SAMD21G18A__ +CFLAGS += -D__SAMD21G18A__ -DCFG_EXAMPLE_VIDEO_READONLY LD_FILE = $(BOARD_PATH)/samd21g18a_flash.ld diff --git a/hw/bsp/samd21/boards/metro_m0_express/board.mk b/hw/bsp/samd21/boards/metro_m0_express/board.mk index bb426cdaa..d6c9150b3 100644 --- a/hw/bsp/samd21/boards/metro_m0_express/board.mk +++ b/hw/bsp/samd21/boards/metro_m0_express/board.mk @@ -1,4 +1,4 @@ -CFLAGS += -D__SAMD21G18A__ +CFLAGS += -D__SAMD21G18A__ -DCFG_EXAMPLE_VIDEO_READONLY # All source paths should be relative to the top level. LD_FILE = $(BOARD_PATH)/$(BOARD).ld diff --git a/hw/bsp/samd21/boards/seeeduino_xiao/board.mk b/hw/bsp/samd21/boards/seeeduino_xiao/board.mk index 54591b3a5..1c888da3a 100644 --- a/hw/bsp/samd21/boards/seeeduino_xiao/board.mk +++ b/hw/bsp/samd21/boards/seeeduino_xiao/board.mk @@ -1,4 +1,4 @@ -CFLAGS += -D__SAMD21G18A__ +CFLAGS += -D__SAMD21G18A__ -DCFG_EXAMPLE_VIDEO_READONLY LD_FILE = $(BOARD_PATH)/$(BOARD).ld diff --git a/hw/bsp/saml2x/boards/atsaml21_xpro/board.mk b/hw/bsp/saml2x/boards/atsaml21_xpro/board.mk index 81b4ecdcb..5b9acb90b 100644 --- a/hw/bsp/saml2x/boards/atsaml21_xpro/board.mk +++ b/hw/bsp/saml2x/boards/atsaml21_xpro/board.mk @@ -1,4 +1,4 @@ -CFLAGS += -D__SAML21J18B__ +CFLAGS += -D__SAML21J18B__ -DCFG_EXAMPLE_VIDEO_READONLY SAML_VARIANT = saml21 diff --git a/hw/bsp/saml2x/boards/saml22_feather/board.mk b/hw/bsp/saml2x/boards/saml22_feather/board.mk index 0605dca19..0adfdd62c 100644 --- a/hw/bsp/saml2x/boards/saml22_feather/board.mk +++ b/hw/bsp/saml2x/boards/saml22_feather/board.mk @@ -1,4 +1,4 @@ -CFLAGS += -D__SAML22J18A__ +CFLAGS += -D__SAML22J18A__ -DCFG_EXAMPLE_VIDEO_READONLY SAML_VARIANT = saml22 diff --git a/hw/bsp/saml2x/boards/sensorwatch_m0/board.mk b/hw/bsp/saml2x/boards/sensorwatch_m0/board.mk index 0605dca19..0adfdd62c 100644 --- a/hw/bsp/saml2x/boards/sensorwatch_m0/board.mk +++ b/hw/bsp/saml2x/boards/sensorwatch_m0/board.mk @@ -1,4 +1,4 @@ -CFLAGS += -D__SAML22J18A__ +CFLAGS += -D__SAML22J18A__ -DCFG_EXAMPLE_VIDEO_READONLY SAML_VARIANT = saml22 diff --git a/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk index 9e636cd76..7c0ee40b6 100644 --- a/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk +++ b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk @@ -1,4 +1,4 @@ -CFLAGS += -DSTM32F070xB +CFLAGS += -DSTM32F070xB -DCFG_EXAMPLE_VIDEO_READONLY LD_FILE = $(BOARD_PATH)/stm32F070rbtx_flash.ld diff --git a/hw/bsp/stm32f0/boards/stm32f072disco/board.mk b/hw/bsp/stm32f0/boards/stm32f072disco/board.mk index 2ef0ee63c..7c72d8f4c 100644 --- a/hw/bsp/stm32f0/boards/stm32f072disco/board.mk +++ b/hw/bsp/stm32f0/boards/stm32f072disco/board.mk @@ -1,4 +1,4 @@ -CFLAGS += -DSTM32F072xB +CFLAGS += -DSTM32F072xB -DCFG_EXAMPLE_VIDEO_READONLY LD_FILE = $(BOARD_PATH)/STM32F072RBTx_FLASH.ld diff --git a/hw/bsp/stm32f0/boards/stm32f072eval/board.mk b/hw/bsp/stm32f0/boards/stm32f072eval/board.mk index f7f8c84ee..b625c3ebd 100644 --- a/hw/bsp/stm32f0/boards/stm32f072eval/board.mk +++ b/hw/bsp/stm32f0/boards/stm32f072eval/board.mk @@ -1,4 +1,4 @@ -CFLAGS += -DSTM32F072xB -DLSI_VALUE=40000 +CFLAGS += -DSTM32F072xB -DLSI_VALUE=40000 -DCFG_EXAMPLE_VIDEO_READONLY LD_FILE = $(BOARD_PATH)/STM32F072VBTx_FLASH.ld diff --git a/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.mk b/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.mk index 9c690ca7e..db64b3a3f 100644 --- a/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.mk +++ b/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.mk @@ -1,4 +1,4 @@ -CFLAGS += -DSTM32F103xB -DHSE_VALUE=8000000U +CFLAGS += -DSTM32F103xB -DHSE_VALUE=8000000U -DCFG_EXAMPLE_VIDEO_READONLY # All source paths should be relative to the top level. LD_FILE = $(BOARD_PATH)/STM32F103X8_FLASH.ld diff --git a/hw/bsp/stm32l0538disco/board.mk b/hw/bsp/stm32l0538disco/board.mk index c46887f14..e19101d64 100644 --- a/hw/bsp/stm32l0538disco/board.mk +++ b/hw/bsp/stm32l0538disco/board.mk @@ -13,6 +13,7 @@ CFLAGS += \ -nostdlib -nostartfiles \ -DSTM32L053xx \ -DCFG_EXAMPLE_MSC_READONLY \ + -DCFG_EXAMPLE_VIDEO_READONLY \ -DCFG_TUSB_MCU=OPT_MCU_STM32L0 # mcu driver cause following warnings -- cgit v1.3.1 From a6723f556d7b302137ca42c7f811d3484f25414a Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 11 Oct 2021 12:36:03 +0700 Subject: add ncm.h for magic number mostly clean up magic number --- src/class/cdc/cdc.h | 69 ++++++++++++++++++++++------------------------ src/class/net/ncm.h | 69 ++++++++++++++++++++++++++++++++++++++++++++++ src/class/net/ncm_device.c | 56 +++++++++++++++++++++---------------- src/class/net/net_device.h | 2 ++ src/device/usbd.h | 8 +++--- 5 files changed, 141 insertions(+), 63 deletions(-) create mode 100644 src/class/net/ncm.h diff --git a/src/class/cdc/cdc.h b/src/class/cdc/cdc.h index 52de859ca..e345139ea 100644 --- a/src/class/cdc/cdc.h +++ b/src/class/cdc/cdc.h @@ -58,32 +58,32 @@ typedef enum /// Communication Interface Subclass Codes typedef enum { - CDC_COMM_SUBCLASS_DIRECT_LINE_CONTROL_MODEL = 0x01 , ///< Direct Line Control Model [USBPSTN1.2] - CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL , ///< Abstract Control Model [USBPSTN1.2] - CDC_COMM_SUBCLASS_TELEPHONE_CONTROL_MODEL , ///< Telephone Control Model [USBPSTN1.2] - CDC_COMM_SUBCLASS_MULTICHANNEL_CONTROL_MODEL , ///< Multi-Channel Control Model [USBISDN1.2] - CDC_COMM_SUBCLASS_CAPI_CONTROL_MODEL , ///< CAPI Control Model [USBISDN1.2] - CDC_COMM_SUBCLASS_ETHERNET_CONTROL_MODEL , ///< Ethernet Networking Control Model [USBECM1.2] - CDC_COMM_SUBCLASS_ATM_NETWORKING_CONTROL_MODEL , ///< ATM Networking Control Model [USBATM1.2] - CDC_COMM_SUBCLASS_WIRELESS_HANDSET_CONTROL_MODEL , ///< Wireless Handset Control Model [USBWMC1.1] - CDC_COMM_SUBCLASS_DEVICE_MANAGEMENT , ///< Device Management [USBWMC1.1] - CDC_COMM_SUBCLASS_MOBILE_DIRECT_LINE_MODEL , ///< Mobile Direct Line Model [USBWMC1.1] - CDC_COMM_SUBCLASS_OBEX , ///< OBEX [USBWMC1.1] - CDC_COMM_SUBCLASS_ETHERNET_EMULATION_MODEL , ///< Ethernet Emulation Model [USBEEM1.0] - CDC_COMM_SUBCLASS_NETWORK_CONTROL_MODEL ///< Network Control Model [USBNCM1.0] + CDC_COMM_SUBCLASS_DIRECT_LINE_CONTROL_MODEL = 0x01 , ///< Direct Line Control Model [USBPSTN1.2] + CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL = 0x02 , ///< Abstract Control Model [USBPSTN1.2] + CDC_COMM_SUBCLASS_TELEPHONE_CONTROL_MODEL = 0x03 , ///< Telephone Control Model [USBPSTN1.2] + CDC_COMM_SUBCLASS_MULTICHANNEL_CONTROL_MODEL = 0x04 , ///< Multi-Channel Control Model [USBISDN1.2] + CDC_COMM_SUBCLASS_CAPI_CONTROL_MODEL = 0x05 , ///< CAPI Control Model [USBISDN1.2] + CDC_COMM_SUBCLASS_ETHERNET_CONTROL_MODEL = 0x06 , ///< Ethernet Networking Control Model [USBECM1.2] + CDC_COMM_SUBCLASS_ATM_NETWORKING_CONTROL_MODEL = 0x07 , ///< ATM Networking Control Model [USBATM1.2] + CDC_COMM_SUBCLASS_WIRELESS_HANDSET_CONTROL_MODEL = 0x08 , ///< Wireless Handset Control Model [USBWMC1.1] + CDC_COMM_SUBCLASS_DEVICE_MANAGEMENT = 0x09 , ///< Device Management [USBWMC1.1] + CDC_COMM_SUBCLASS_MOBILE_DIRECT_LINE_MODEL = 0x0A , ///< Mobile Direct Line Model [USBWMC1.1] + CDC_COMM_SUBCLASS_OBEX = 0x0B , ///< OBEX [USBWMC1.1] + CDC_COMM_SUBCLASS_ETHERNET_EMULATION_MODEL = 0x0C , ///< Ethernet Emulation Model [USBEEM1.0] + CDC_COMM_SUBCLASS_NETWORK_CONTROL_MODEL = 0x0D ///< Network Control Model [USBNCM1.0] } cdc_comm_sublcass_type_t; /// Communication Interface Protocol Codes typedef enum { - CDC_COMM_PROTOCOL_NONE = 0x00 , ///< No specific protocol - CDC_COMM_PROTOCOL_ATCOMMAND , ///< AT Commands: V.250 etc - CDC_COMM_PROTOCOL_ATCOMMAND_PCCA_101 , ///< AT Commands defined by PCCA-101 - CDC_COMM_PROTOCOL_ATCOMMAND_PCCA_101_AND_ANNEXO , ///< AT Commands defined by PCCA-101 & Annex O - CDC_COMM_PROTOCOL_ATCOMMAND_GSM_707 , ///< AT Commands defined by GSM 07.07 - CDC_COMM_PROTOCOL_ATCOMMAND_3GPP_27007 , ///< AT Commands defined by 3GPP 27.007 - CDC_COMM_PROTOCOL_ATCOMMAND_CDMA , ///< AT Commands defined by TIA for CDMA - CDC_COMM_PROTOCOL_ETHERNET_EMULATION_MODEL ///< Ethernet Emulation Model + CDC_COMM_PROTOCOL_NONE = 0x00 , ///< No specific protocol + CDC_COMM_PROTOCOL_ATCOMMAND = 0x01 , ///< AT Commands: V.250 etc + CDC_COMM_PROTOCOL_ATCOMMAND_PCCA_101 = 0x02 , ///< AT Commands defined by PCCA-101 + CDC_COMM_PROTOCOL_ATCOMMAND_PCCA_101_AND_ANNEXO = 0x03 , ///< AT Commands defined by PCCA-101 & Annex O + CDC_COMM_PROTOCOL_ATCOMMAND_GSM_707 = 0x04 , ///< AT Commands defined by GSM 07.07 + CDC_COMM_PROTOCOL_ATCOMMAND_3GPP_27007 = 0x05 , ///< AT Commands defined by 3GPP 27.007 + CDC_COMM_PROTOCOL_ATCOMMAND_CDMA = 0x06 , ///< AT Commands defined by TIA for CDMA + CDC_COMM_PROTOCOL_ETHERNET_EMULATION_MODEL = 0x07 ///< Ethernet Emulation Model } cdc_comm_protocol_type_t; //------------- SubType Descriptor in COMM Functional Descriptor -------------// @@ -124,7 +124,8 @@ typedef enum //--------------------------------------------------------------------+ // SUBCLASS code of Data Interface is not used and should/must be zero -/// Data Interface Protocol Codes + +// Data Interface Protocol Codes typedef enum{ CDC_DATA_PROTOCOL_ISDN_BRI = 0x30, ///< Physical interface protocol for ISDN BRI CDC_DATA_PROTOCOL_HDLC = 0x31, ///< HDLC @@ -149,7 +150,6 @@ typedef enum { CDC_REQUEST_SEND_ENCAPSULATED_COMMAND = 0x00, ///< is used to issue a command in the format of the supported control protocol of the Communications Class interface CDC_REQUEST_GET_ENCAPSULATED_RESPONSE = 0x01, ///< is used to request a response in the format of the supported control protocol of the Communications Class interface. - CDC_REQUEST_SET_COMM_FEATURE = 0x02, CDC_REQUEST_GET_COMM_FEATURE = 0x03, CDC_REQUEST_CLEAR_COMM_FEATURE = 0x04, @@ -196,21 +196,18 @@ typedef enum // Management Elemenent Notification (Notification Endpoint) //--------------------------------------------------------------------+ -/// Communication Interface Management Element Notification Codes +/// 6.3 Notification Codes typedef enum { - NETWORK_CONNECTION = 0x00, ///< This notification allows the device to notify the host about network connection status. - RESPONSE_AVAILABLE = 0x01, ///< This notification allows the device to notify the hostthat a response is available. This response can be retrieved with a subsequent \ref CDC_REQUEST_GET_ENCAPSULATED_RESPONSE request. - - AUX_JACK_HOOK_STATE = 0x08, - RING_DETECT = 0x09, - - SERIAL_STATE = 0x20, - - CALL_STATE_CHANGE = 0x28, - LINE_STATE_CHANGE = 0x29, - CONNECTION_SPEED_CHANGE = 0x2A, ///< This notification allows the device to inform the host-networking driver that a change in either the upstream or the downstream bit rate of the connection has occurred - MDLM_SEMANTIC_MODEL_NOTIFICATION = 0x40, + CDC_NOTIF_NETWORK_CONNECTION = 0x00, ///< This notification allows the device to notify the host about network connection status. + CDC_NOTIF_RESPONSE_AVAILABLE = 0x01, ///< This notification allows the device to notify the hostthat a response is available. This response can be retrieved with a subsequent \ref CDC_REQUEST_GET_ENCAPSULATED_RESPONSE request. + CDC_NOTIF_AUX_JACK_HOOK_STATE = 0x08, + CDC_NOTIF_RING_DETECT = 0x09, + CDC_NOTIF_SERIAL_STATE = 0x20, + CDC_NOTIF_CALL_STATE_CHANGE = 0x28, + CDC_NOTIF_LINE_STATE_CHANGE = 0x29, + CDC_NOTIF_CONNECTION_SPEED_CHANGE = 0x2A, ///< This notification allows the device to inform the host-networking driver that a change in either the upstream or the downstream bit rate of the connection has occurred + CDC_NOTIF_MDLM_SEMANTIC_MODEL_NOTIFICATION = 0x40, }cdc_notification_request_t; //--------------------------------------------------------------------+ diff --git a/src/class/net/ncm.h b/src/class/net/ncm.h new file mode 100644 index 000000000..96ba11fbc --- /dev/null +++ b/src/class/net/ncm.h @@ -0,0 +1,69 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + + +#ifndef _TUSB_NCM_H_ +#define _TUSB_NCM_H_ + +#include "common/tusb_common.h" + +#ifdef __cplusplus + extern "C" { +#endif + +// Table 4.3 Data Class Interface Protocol Codes +typedef enum +{ + NCM_DATA_PROTOCOL_NETWORK_TRANSFER_BLOCK = 0x01 +} ncm_data_interface_protocol_code_t; + + +// Table 6.2 Class-Specific Request Codes for Network Control Model subclass +typedef enum +{ + NCM_SET_ETHERNET_MULTICAST_FILTERS = 0x40, + NCM_SET_ETHERNET_POWER_MANAGEMENT_PATTERN_FILTER = 0x41, + NCM_GET_ETHERNET_POWER_MANAGEMENT_PATTERN_FILTER = 0x42, + NCM_SET_ETHERNET_PACKET_FILTER = 0x43, + NCM_GET_ETHERNET_STATISTIC = 0x44, + NCM_GET_NTB_PARAMETERS = 0x80, + NCM_GET_NET_ADDRESS = 0x81, + NCM_SET_NET_ADDRESS = 0x82, + NCM_GET_NTB_FORMAT = 0x83, + NCM_SET_NTB_FORMAT = 0x84, + NCM_GET_NTB_INPUT_SIZE = 0x85, + NCM_SET_NTB_INPUT_SIZE = 0x86, + NCM_GET_MAX_DATAGRAM_SIZE = 0x87, + NCM_SET_MAX_DATAGRAM_SIZE = 0x88, + NCM_GET_CRC_MODE = 0x89, + NCM_SET_CRC_MODE = 0x8A, +} ncm_request_code_t; + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/src/class/net/ncm_device.c b/src/class/net/ncm_device.c index 2f7d58f99..3e131a85c 100644 --- a/src/class/net/ncm_device.c +++ b/src/class/net/ncm_device.c @@ -38,7 +38,7 @@ // MACRO CONSTANT TYPEDEF //--------------------------------------------------------------------+ -#define NTH16_SIGNATURE 0x484D434E +#define NTH16_SIGNATURE 0x484D434E #define NDP16_SIGNATURE_NCM0 0x304D434E #define NDP16_SIGNATURE_NCM1 0x314D434E @@ -114,13 +114,13 @@ typedef struct } report_state; bool report_pending; - uint8_t current_ntb; // Index in transmit_ntb[] that is currently being filled with datagrams - uint8_t datagram_count; // Number of datagrams in transmit_ntb[current_ntb] - uint16_t next_datagram_offset; // Offset in transmit_ntb[current_ntb].data to place the next datagram - uint16_t ntb_in_size; // Maximum size of transmitted (IN to host) NTBs; initially CFG_TUD_NCM_IN_NTB_MAX_SIZE - uint8_t max_datagrams_per_ntb; // Maximum number of datagrams per NTB; initially CFG_TUD_NCM_MAX_DATAGRAMS_PER_NTB + uint8_t current_ntb; // Index in transmit_ntb[] that is currently being filled with datagrams + uint8_t datagram_count; // Number of datagrams in transmit_ntb[current_ntb] + uint16_t next_datagram_offset; // Offset in transmit_ntb[current_ntb].data to place the next datagram + uint16_t ntb_in_size; // Maximum size of transmitted (IN to host) NTBs; initially CFG_TUD_NCM_IN_NTB_MAX_SIZE + uint8_t max_datagrams_per_ntb; // Maximum number of datagrams per NTB; initially CFG_TUD_NCM_MAX_DATAGRAMS_PER_NTB - uint16_t nth_sequence; // Sequence number counter for transmitted NTBs + uint16_t nth_sequence; // Sequence number counter for transmitted NTBs bool transferring; @@ -197,25 +197,33 @@ static void ncm_start_tx(void) { } static struct ecm_notify_struct ncm_notify_connected = - { - .header = { - .bmRequestType = 0xA1, - .bRequest = 0 /* NETWORK_CONNECTION aka NetworkConnection */, - .wValue = 1 /* Connected */, - .wLength = 0, +{ + .header = { + .bmRequestType_bit = { + .recipient = TUSB_REQ_RCPT_INTERFACE, + .type = TUSB_REQ_TYPE_CLASS, + .direction = TUSB_DIR_IN }, - }; + .bRequest = CDC_NOTIF_NETWORK_CONNECTION, + .wValue = 1 /* Connected */, + .wLength = 0, + }, +}; static struct ecm_notify_struct ncm_notify_speed_change = - { - .header = { - .bmRequestType = 0xA1, - .bRequest = 0x2A /* CONNECTION_SPEED_CHANGE aka ConnectionSpeedChange */, - .wLength = 8, +{ + .header = { + .bmRequestType_bit = { + .recipient = TUSB_REQ_RCPT_INTERFACE, + .type = TUSB_REQ_TYPE_CLASS, + .direction = TUSB_DIR_IN }, - .downlink = 10000000, - .uplink = 10000000, - }; + .bRequest = CDC_NOTIF_CONNECTION_SPEED_CHANGE, + .wLength = 8, + }, + .downlink = 10000000, + .uplink = 10000000, +}; void tud_network_recv_renew(void) { @@ -381,7 +389,7 @@ bool netd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t case TUSB_REQ_TYPE_CLASS: TU_VERIFY (ncm_interface.itf_num == request->wIndex); - if (0x80 /* GET_NTB_PARAMETERS */ == request->bRequest) + if (NCM_GET_NTB_PARAMETERS == request->bRequest) { tud_control_xfer(rhport, request, (void*)&ntb_parameters, sizeof(ntb_parameters)); } @@ -418,7 +426,9 @@ static void handle_incoming_datagram(uint32_t len) ncm_interface.num_datagrams = 0; ncm_interface.ndp = ndp; for (int i = 0; i < num_datagrams && ndp->datagram[i].wDatagramIndex && ndp->datagram[i].wDatagramLength; i++) + { ncm_interface.num_datagrams++; + } tud_network_recv_renew(); } diff --git a/src/class/net/net_device.h b/src/class/net/net_device.h index ad369b680..6e294465b 100644 --- a/src/class/net/net_device.h +++ b/src/class/net/net_device.h @@ -34,6 +34,8 @@ #error "Cannot enable both ECM_RNDIS and NCM network drivers" #endif +#include "ncm.h" + /* declared here, NOT in usb_descriptors.c, so that the driver can intelligently ZLP as needed */ #define CFG_TUD_NET_ENDPOINT_SIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) diff --git a/src/device/usbd.h b/src/device/usbd.h index 7575ef42c..8d02de1ff 100644 --- a/src/device/usbd.h +++ b/src/device/usbd.h @@ -827,16 +827,16 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb 5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_HEADER, U16_TO_U8S_LE(0x0110),\ /* CDC-NCM Union */\ 5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_UNION, _itfnum, (uint8_t)((_itfnum) + 1),\ - /* CDC-ECM Functional Descriptor */\ + /* CDC-NCM Functional Descriptor */\ 13, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_ETHERNET_NETWORKING, _mac_stridx, 0, 0, 0, 0, U16_TO_U8S_LE(_maxsegmentsize), U16_TO_U8S_LE(0), 0, \ - /* CDC-ECM Functional Descriptor */\ + /* CDC-NCM Functional Descriptor */\ 6, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_NCM, U16_TO_U8S_LE(0x0100), 0, \ /* Endpoint Notification */\ 7, TUSB_DESC_ENDPOINT, _ep_notif, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_ep_notif_size), 50,\ /* CDC Data Interface (default inactive) */\ - 9, TUSB_DESC_INTERFACE, (uint8_t)((_itfnum)+1), 0, 0, TUSB_CLASS_CDC_DATA, 0, 1, 0,\ + 9, TUSB_DESC_INTERFACE, (uint8_t)((_itfnum)+1), 0, 0, TUSB_CLASS_CDC_DATA, 0, NCM_DATA_PROTOCOL_NETWORK_TRANSFER_BLOCK, 0,\ /* CDC Data Interface (alternative active) */\ - 9, TUSB_DESC_INTERFACE, (uint8_t)((_itfnum)+1), 1, 2, TUSB_CLASS_CDC_DATA, 0, 1, 0,\ + 9, TUSB_DESC_INTERFACE, (uint8_t)((_itfnum)+1), 1, 2, TUSB_CLASS_CDC_DATA, 0, NCM_DATA_PROTOCOL_NETWORK_TRANSFER_BLOCK, 0,\ /* Endpoint In */\ 7, TUSB_DESC_ENDPOINT, _epin, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0,\ /* Endpoint Out */\ -- cgit v1.3.1 From b3bfce2cb7213df3d875133de26321542e7ecf08 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 8 Oct 2021 15:49:56 +0700 Subject: update the descriptor endpoint ISO for nrf5x --- examples/device/video_capture/src/usb_descriptors.c | 16 ++++------------ src/class/video/video_device.c | 2 +- 2 files changed, 5 insertions(+), 13 deletions(-) diff --git a/examples/device/video_capture/src/usb_descriptors.c b/examples/device/video_capture/src/usb_descriptors.c index b0e41b97e..404ffe070 100644 --- a/examples/device/video_capture/src/usb_descriptors.c +++ b/examples/device/video_capture/src/usb_descriptors.c @@ -77,22 +77,14 @@ uint8_t const * tud_descriptor_device_cb(void) #define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + TUD_VIDEO_CAPTURE_DESC_LEN) -#if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX +#if TU_CHECK_MCU(LPC175X_6X) || TU_CHECK_MCU(LPC177X_8X) || TU_CHECK_MCU(LPC40XX) // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In, 5 Bulk etc ... #define EPNUM_VIDEO_IN 0x83 -#elif CFG_TUSB_MCU == OPT_MCU_SAMG || CFG_TUSB_MCU == OPT_MCU_CXD56 - // SAMG doesn't support a same endpoint number with different direction IN and OUT - // e.g EP1 OUT & EP1 IN cannot exist together - #define EPNUM_VIDEO_IN 0x81 - -#elif CFG_TUSB_MCU == OPT_MCU_CXD56 - // CXD56 doesn't support a same endpoint number with different direction IN and OUT - // e.g EP1 OUT & EP1 IN cannot exist together - // CXD56 USB driver has fixed endpoint type (bulk/interrupt/iso) and direction (IN/OUT) by its number - // 0 control (IN/OUT), 1 Bulk (IN), 2 Bulk (OUT), 3 In (IN), 4 Bulk (IN), 5 Bulk (OUT), 6 In (IN) - #define EPNUM_VIDEO_IN 0x81 +#elif TU_CHECK_MCU(NRF5X) + // nRF5x ISO can only be endpoint 8 + #define EPNUM_VIDEO_IN 0x88 #else #define EPNUM_VIDEO_IN 0x81 diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index 12ccbd165..ce34b1b49 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -457,7 +457,7 @@ static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t void const *end = beg + self->len; /* The first descriptor is a video control interface descriptor. */ void const *cur = _find_desc_itf(beg, end, _desc_itfnum(beg), altnum); - TU_LOG2(" cur %ld\n", cur - beg); + TU_LOG2(" cur %d\n", cur - beg); TU_VERIFY(cur < end); tusb_desc_vc_itf_t const *vc = (tusb_desc_vc_itf_t const *)cur; -- cgit v1.3.1 From 4d170614dc31c083f8b96add1393156c89670dd7 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 11 Oct 2021 23:18:24 +0700 Subject: rename some video constants --- examples/device/video_capture/src/main.c | 2 +- examples/device/video_capture/src/tusb_config.h | 7 +- .../device/video_capture/src/usb_descriptors.h | 66 ++++--- src/class/video/video.h | 197 ++++++++++++--------- src/class/video/video_device.c | 190 ++++++++++---------- 5 files changed, 238 insertions(+), 224 deletions(-) diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c index f0f4df6eb..a2d95c8f9 100644 --- a/examples/device/video_capture/src/main.c +++ b/examples/device/video_capture/src/main.c @@ -202,7 +202,7 @@ int tud_video_commit_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, (void)ctl_idx; (void)stm_idx; /* convert unit to ms from 100 ns */ interval_ms = parameters->dwFrameInterval / 10000; - return VIDEO_NO_ERROR; + return VIDEO_ERROR_NONE; } //--------------------------------------------------------------------+ diff --git a/examples/device/video_capture/src/tusb_config.h b/examples/device/video_capture/src/tusb_config.h index 5d2d5470c..4feb6a48a 100644 --- a/examples/device/video_capture/src/tusb_config.h +++ b/examples/device/video_capture/src/tusb_config.h @@ -91,16 +91,11 @@ #endif //------------- CLASS -------------// -#define CFG_TUD_CDC 0 -#define CFG_TUD_MSC 0 -#define CFG_TUD_HID 0 -#define CFG_TUD_MIDI 0 -#define CFG_TUD_AUDIO 0 // The number of video control interfaces #define CFG_TUD_VIDEO 1 + // The number of video streaming interfaces #define CFG_TUD_VIDEO_STREAMING 1 -#define CFG_TUD_VENDOR 0 // video streaming endpoint size #define CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE 256 diff --git a/examples/device/video_capture/src/usb_descriptors.h b/examples/device/video_capture/src/usb_descriptors.h index 403dc56a1..340b3f799 100644 --- a/examples/device/video_capture/src/usb_descriptors.h +++ b/examples/device/video_capture/src/usb_descriptors.h @@ -75,40 +75,38 @@ enum { #define TUD_VIDEO_CAPTURE_DESCRIPTOR(_stridx, _epin, _width, _height, _fps, _epsize) \ TUD_VIDEO_DESC_IAD(ITF_NUM_VIDEO_CONTROL, ITF_NUM_TOTAL, _stridx), \ - /* Video control 0 */ \ - TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx), \ - TUD_VIDEO_DESC_CS_VC( /* UVC 1.5*/ 0x0150, \ - /* wTotalLength - bLength */ \ - TUD_VIDEO_DESC_INPUT_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, \ - UVC_CLOCK_FREQUENCY, 1), \ - TUD_VIDEO_DESC_INPUT_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL,\ - VIDEO_TT_COMPOSITE_CONNECTOR, 0, 0), \ - TUD_VIDEO_DESC_OUTPUT_TERM(UVC_ENTITY_CAP_OUTPUT_TERMINAL,\ - VIDEO_TT_STREAMING, 0, 1, 0), \ - /* Video stream alt. 0 */ \ - TUD_VIDEO_DESC_STD_VS( 1, 0, 0, 0), \ - /* Video stream header for without still image capture */ \ - TUD_VIDEO_DESC_CS_VS_INPUT( /*bNumFormats*/1, \ - /*wTotalLength - bLength */\ - TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN\ - + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN\ - + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\ - _epin, /*bmInfo*/0, /*bTerminalLink*/UVC_ENTITY_CAP_OUTPUT_TERMINAL, \ - /*bStillCaptureMethod*/0, /*bTriggerSupport*/0, /*bTriggerUsage*/0, \ - /*bmaControls(1)*/0), \ - /* Video stream format */ \ - TUD_VIDEO_DESC_CS_VS_FMT_YUY2(/*bFormatIndex*/1, /*bNumFrameDescriptors*/1, \ - /*bDefaultFrameIndex*/1, 0, 0, 0, /*bCopyProtect*/0), \ - /* Video stream frame format */ \ - TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT(/*bFrameIndex */1, 0, _width, _height, \ - _width * _height * 16, _width * _height * 16 * _fps, \ - _width * _height * 16, \ - (10000000/_fps), (10000000/_fps), 10000000, 100000), \ - TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING(VIDEO_COLOR_PRIMARIES_BT709, VIDEO_COLOR_XFER_CH_BT709, VIDEO_COLOR_COEF_SMPTE170M), \ - /* VS alt 1 */\ - TUD_VIDEO_DESC_STD_VS(1, 1, 1, 0), \ - /* EP */ \ - TUD_VIDEO_DESC_EP_ISO(_epin, _epsize, 1) + /* Video control 0 */ \ + TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx), \ + TUD_VIDEO_DESC_CS_VC( /* UVC 1.5*/ 0x0150, \ + /* wTotalLength - bLength */ \ + TUD_VIDEO_DESC_INPUT_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, \ + UVC_CLOCK_FREQUENCY, 1), \ + TUD_VIDEO_DESC_INPUT_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, VIDEO_ETT_COMPOSITE_CONNECTOR, 0, 0), \ + TUD_VIDEO_DESC_OUTPUT_TERM(UVC_ENTITY_CAP_OUTPUT_TERMINAL, VIDEO_TT_STREAMING, 0, 1, 0), \ + /* Video stream alt. 0 */ \ + TUD_VIDEO_DESC_STD_VS( 1, 0, 0, 0), \ + /* Video stream header for without still image capture */ \ + TUD_VIDEO_DESC_CS_VS_INPUT( /*bNumFormats*/1, \ + /*wTotalLength - bLength */\ + TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN\ + + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN\ + + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\ + _epin, /*bmInfo*/0, /*bTerminalLink*/UVC_ENTITY_CAP_OUTPUT_TERMINAL, \ + /*bStillCaptureMethod*/0, /*bTriggerSupport*/0, /*bTriggerUsage*/0, \ + /*bmaControls(1)*/0), \ + /* Video stream format */ \ + TUD_VIDEO_DESC_CS_VS_FMT_YUY2(/*bFormatIndex*/1, /*bNumFrameDescriptors*/1, \ + /*bDefaultFrameIndex*/1, 0, 0, 0, /*bCopyProtect*/0), \ + /* Video stream frame format */ \ + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT(/*bFrameIndex */1, 0, _width, _height, \ + _width * _height * 16, _width * _height * 16 * _fps, \ + _width * _height * 16, \ + (10000000/_fps), (10000000/_fps), 10000000, 100000), \ + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING(VIDEO_COLOR_PRIMARIES_BT709, VIDEO_COLOR_XFER_CH_BT709, VIDEO_COLOR_COEF_SMPTE170M), \ + /* VS alt 1 */\ + TUD_VIDEO_DESC_STD_VS(1, 1, 1, 0), \ + /* EP */ \ + TUD_VIDEO_DESC_EP_ISO(_epin, _epsize, 1) #endif diff --git a/src/class/video/video.h b/src/class/video/video.h index 3c27c8093..8288e4961 100644 --- a/src/class/video/video.h +++ b/src/class/video/video.h @@ -29,18 +29,20 @@ #include "common/tusb_common.h" +// Table 3-19 Color Matching Descriptor typedef enum { VIDEO_COLOR_PRIMARIES_UNDEFINED = 0x00, - VIDEO_COLOR_PRIMARIES_BT709, + VIDEO_COLOR_PRIMARIES_BT709, // sRGB (default) VIDEO_COLOR_PRIMARIES_BT470_2M, VIDEO_COLOR_PRIMARIES_BT470_2BG, VIDEO_COLOR_PRIMARIES_SMPTE170M, VIDEO_COLOR_PRIMARIES_SMPTE240M, } video_color_primaries_t; +// Table 3-19 Color Matching Descriptor typedef enum { VIDEO_COLOR_XFER_CH_UNDEFINED = 0x00, - VIDEO_COLOR_XFER_CH_BT709, + VIDEO_COLOR_XFER_CH_BT709, // default VIDEO_COLOR_XFER_CH_BT470_2M, VIDEO_COLOR_XFER_CH_BT470_2BG, VIDEO_COLOR_XFER_CH_SMPTE170M, @@ -49,30 +51,31 @@ typedef enum { VIDEO_COLOR_XFER_CH_SRGB, } video_color_transfer_characteristics_t; +// Table 3-19 Color Matching Descriptor typedef enum { VIDEO_COLOR_COEF_UNDEFINED = 0x00, VIDEO_COLOR_COEF_BT709, VIDEO_COLOR_COEF_FCC, VIDEO_COLOR_COEF_BT470_2BG, - VIDEO_COLOR_COEF_SMPTE170M, + VIDEO_COLOR_COEF_SMPTE170M, // BT.601 default VIDEO_COLOR_COEF_SMPTE240M, } video_color_matrix_coefficients_t; -/* 4.2.1.2 */ +/* 4.2.1.2 Request Error Code Control */ typedef enum { - VIDEO_NO_ERROR = 0, /* The request succeeded. */ - VIDEO_NOT_READY, - VIDEO_WRONG_STATE, - VIDEO_POWER, - VIDEO_OUT_OF_RANGE, - VIDEO_INVALID_UNIT, - VIDEO_INVALID_CONTROL, - VIDEO_INVALID_REQUEST, - VIDEO_INVALID_VALUE_WITHIN_RANGE, - VIDEO_UNKNOWN = 0xFF, + VIDEO_ERROR_NONE = 0, /* The request succeeded. */ + VIDEO_ERROR_NOT_READY, + VIDEO_ERROR_WRONG_STATE, + VIDEO_ERROR_POWER, + VIDEO_ERROR_OUT_OF_RANGE, + VIDEO_ERROR_INVALID_UNIT, + VIDEO_ERROR_INVALID_CONTROL, + VIDEO_ERROR_INVALID_REQUEST, + VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE, + VIDEO_ERROR_UNKNOWN = 0xFF, } video_error_code_t; -/* A.2 */ +/* A.2 Interface Subclass */ typedef enum { VIDEO_SUBCLASS_UNDEFINED = 0x00, VIDEO_SUBCLASS_CONTROL, @@ -80,79 +83,86 @@ typedef enum { VIDEO_SUBCLASS_INTERFACE_COLLECTION, } video_subclass_type_t; -/* A.3 */ +/* A.3 Interface Protocol */ typedef enum { - VIDEO_INT_PROTOCOL_CODE_UNDEF = 0x00, - VIDEO_INT_PROTOCOL_CODE_15, + VIDEO_ITF_PROTOCOL_UNDEFINED = 0x00, + VIDEO_ITF_PROTOCOL_15, } video_interface_protocol_code_t; -/* A.5 */ +/* A.5 Class-Specific VideoControl Interface Descriptor Subtypes */ typedef enum { - VIDEO_CS_VC_INTERFACE_VC_DESCRIPTOR_UNDEF = 0x00, - VIDEO_CS_VC_INTERFACE_HEADER, - VIDEO_CS_VC_INTERFACE_INPUT_TERMINAL, - VIDEO_CS_VC_INTERFACE_OUTPUT_TERMINAL, - VIDEO_CS_VC_INTERFACE_SELECTOR_UNIT, - VIDEO_CS_VC_INTERFACE_PROCESSING_UNIT, - VIDEO_CS_VC_INTERFACE_EXTENSION_UNIT, - VIDEO_CS_VC_INTERFACE_ENCODING_UNIT, - VIDEO_CS_VC_INTERFACE_MAX, + VIDEO_CS_VC_UNDEFINED = 0x00, + VIDEO_CS_VC_HEADER, + VIDEO_CS_VC_INPUT_TERMINAL, + VIDEO_CS_VC_OUTPUT_TERMINAL, + VIDEO_CS_VC_SELECTOR_UNIT, + VIDEO_CS_VC_PROCESSING_UNIT, + VIDEO_CS_VC_EXTENSION_UNIT, + VIDEO_CS_VC_ENCODING_UNIT, + VIDEO_CS_VC_MAX, } video_cs_vc_interface_subtype_t; -/* A.6 */ +/* A.6 Class-Specific VideoStreaming Interface Descriptor Subtypes */ typedef enum { - VIDEO_CS_VS_INTERFACE_VS_DESCRIPTOR_UNDEF = 0x00, - VIDEO_CS_VS_INTERFACE_INPUT_HEADER, - VIDEO_CS_VS_INTERFACE_OUTPUT_HEADER, - VIDEO_CS_VS_INTERFACE_STILL_IMAGE_FRAME, - VIDEO_CS_VS_INTERFACE_FORMAT_UNCOMPRESSED, - VIDEO_CS_VS_INTERFACE_FRAME_UNCOMPRESSED, - VIDEO_CS_VS_INTERFACE_FORMAT_MJPEG, - VIDEO_CS_VS_INTERFACE_FRAME_MJPEG, - VIDEO_CS_VS_INTERFACE_FORMAT_MPEG2TS = 0x0A, - VIDEO_CS_VS_INTERFACE_FORMAT_DV = 0x0c, - VIDEO_CS_VS_INTERFACE_COLORFORMAT, - VIDEO_CS_VS_INTERFACE_FORMAT_FRAME_BASED = 0x10, - VIDEO_CS_VS_INTERFACE_FRAME_FRAME_BASED, - VIDEO_CS_VS_INTERFACE_FORMAT_STREAM_BASED, - VIDEO_CS_VS_INTERFACE_FORMAT_H264, - VIDEO_CS_VS_INTERFACE_FRAME_H264, - VIDEO_CS_VS_INTERFACE_FORMAT_H264_SIMULCAST, - VIDEO_CS_VS_INTERFACE_FORMAT_VP8, - VIDEO_CS_VS_INTERFACE_FRAME_VP8, - VIDEO_CS_VS_INTERFACE_FORMAT_VP8_SIMULCAST, + VIDEO_CS_VS_UNDEFINED = 0x00, + VIDEO_CS_VS_INPUT_HEADER = 0x01, + VIDEO_CS_VS_OUTPUT_HEADER = 0x02, + VIDEO_CS_VS_STILL_IMAGE_FRAME = 0x03, + VIDEO_CS_VS_FORMAT_UNCOMPRESSED = 0x04, + VIDEO_CS_VS_FRAME_UNCOMPRESSED = 0x05, + VIDEO_CS_VS_FORMAT_MJPEG = 0x06, + VIDEO_CS_VS_FRAME_MJPEG = 0x07, + VIDEO_CS_VS_FORMAT_MPEG2TS = 0x0A, + VIDEO_CS_VS_FORMAT_DV = 0x0C, + VIDEO_CS_VS_COLORFORMAT = 0x0D, + VIDEO_CS_VS_FORMAT_FRAME_BASED = 0x10, + VIDEO_CS_VS_FRAME_FRAME_BASED = 0x11, + VIDEO_CS_VS_FORMAT_STREAM_BASED = 0x12, + VIDEO_CS_VS_FORMAT_H264 = 0x13, + VIDEO_CS_VS_FRAME_H264 = 0x14, + VIDEO_CS_VS_FORMAT_H264_SIMULCAST = 0x15, + VIDEO_CS_VS_FORMAT_VP8 = 0x16, + VIDEO_CS_VS_FRAME_VP8 = 0x17, + VIDEO_CS_VS_FORMAT_VP8_SIMULCAST = 0x18, } video_cs_vs_interface_subtype_t; -/* A.8 */ +/* A.7. Class-Specific Endpoint Descriptor Subtypes */ typedef enum { - VIDEO_REQUEST_UNDEF = 0x00, - VIDEO_REQUEST_SET_CUR, + VIDEO_CS_EP_UNDEFINED = 0x00, + VIDEO_CS_EP_GENERAL, + VIDEO_CS_EP_ENDPOINT, + VIDEO_CS_EP_INTERRUPT +} video_cs_ep_subtype_t; + +/* A.8 Class-Specific Request Codes */ +typedef enum { + VIDEO_REQUEST_UNDEFINED = 0x00, + VIDEO_REQUEST_SET_CUR = 0x01, VIDEO_REQUEST_SET_CUR_ALL = 0x11, - VIDEO_REQUEST_GET = 0x80, - VIDEO_REQUEST_GET_CUR, - VIDEO_REQUEST_GET_MIN, - VIDEO_REQUEST_GET_MAX, - VIDEO_REQUEST_GET_RES, - VIDEO_REQUEST_GET_LEN, - VIDEO_REQUEST_GET_INFO, - VIDEO_REQUEST_GET_DEF, + VIDEO_REQUEST_GET_CUR = 0x81, + VIDEO_REQUEST_GET_MIN = 0x82, + VIDEO_REQUEST_GET_MAX = 0x83, + VIDEO_REQUEST_GET_RES = 0x84, + VIDEO_REQUEST_GET_LEN = 0x85, + VIDEO_REQUEST_GET_INFO = 0x86, + VIDEO_REQUEST_GET_DEF = 0x87, VIDEO_REQUEST_GET_CUR_ALL = 0x91, - VIDEO_REQUEST_GET_MIN_ALL, - VIDEO_REQUEST_GET_MAX_ALL, - VIDEO_REQUEST_GET_RES_ALL, + VIDEO_REQUEST_GET_MIN_ALL = 0x92, + VIDEO_REQUEST_GET_MAX_ALL = 0x93, + VIDEO_REQUEST_GET_RES_ALL = 0x94, VIDEO_REQUEST_GET_DEF_ALL = 0x97 } video_control_request_t; -/* A.9.1 */ +/* A.9.1 VideoControl Interface Control Selectors */ typedef enum { - VIDEO_VC_CTL_UNDEF = 0x00, + VIDEO_VC_CTL_UNDEFINED = 0x00, VIDEO_VC_CTL_VIDEO_POWER_MODE, VIDEO_VC_CTL_REQUEST_ERROR_CODE, } video_interface_control_selector_t; -/* A.9.8 */ +/* A.9.8 VideoStreaming Interface Control Selectors */ typedef enum { - VIDEO_VS_CTL_UNDEF = 0x00, + VIDEO_VS_CTL_UNDEFINED = 0x00, VIDEO_VS_CTL_PROBE, VIDEO_VS_CTL_COMMIT, VIDEO_VS_CTL_STILL_PROBE, @@ -166,20 +176,31 @@ typedef enum { /* B. Terminal Types */ typedef enum { + // Terminal VIDEO_TT_VENDOR_SPECIFIC = 0x0100, - VIDEO_TT_STREAMING, + VIDEO_TT_STREAMING = 0x0101, + + // Input VIDEO_ITT_VENDOR_SPECIFIC = 0x0200, - VIDEO_ITT_CAMERA, - VIDEO_ITT_MEDIA_TRANSPORT_INPUT, + VIDEO_ITT_CAMERA = 0x0201, + VIDEO_ITT_MEDIA_TRANSPORT_INPUT = 0x0202, + + // Output VIDEO_OTT_VENDOR_SPECIFIC = 0x0300, - VIDEO_OTT_DISPLAY, - VIDEO_OTT_MEDIA_TRANSPORT_OUTPUT, - VIDEO_TT_EXTERNAL_VENDOR_SPEIFIC = 0x0400, - VIDEO_TT_COMPOSITE_CONNECTOR, - VIDEO_TT_SVIDEO_CONNECTOR, - VIDEO_TT_COMPONENT_CONNECTOR, + VIDEO_OTT_DISPLAY = 0x0301, + VIDEO_OTT_MEDIA_TRANSPORT_OUTPUT = 0x0302, + + // External + VIDEO_ETT_VENDOR_SPEIFIC = 0x0400, + VIDEO_ETT_COMPOSITE_CONNECTOR = 0x0401, + VIDEO_ETT_SVIDEO_CONNECTOR = 0x0402, + VIDEO_ETT_COMPONENT_CONNECTOR = 0x0403, } video_terminal_type_t; +//--------------------------------------------------------------------+ +// Descriptors +//--------------------------------------------------------------------+ + /* 2.3.4.2 */ typedef struct TU_ATTR_PACKED { uint8_t bLength; @@ -369,44 +390,44 @@ TU_VERIFY_STATIC( sizeof(video_probe_and_commit_control_t) == 48, "size is not c #define TUD_VIDEO_DESC_IAD(_firstitfs, _nitfs, _stridx) \ TUD_VIDEO_DESC_IAD_LEN, TUSB_DESC_INTERFACE_ASSOCIATION, \ _firstitfs, _nitfs, TUSB_CLASS_VIDEO, VIDEO_SUBCLASS_INTERFACE_COLLECTION, \ - VIDEO_INT_PROTOCOL_CODE_UNDEF, _stridx + VIDEO_ITF_PROTOCOL_UNDEFINED, _stridx #define TUD_VIDEO_DESC_STD_VC(_itfnum, _nEPs, _stridx) \ TUD_VIDEO_DESC_STD_VC_LEN, TUSB_DESC_INTERFACE, _itfnum, /* fixed to zero */ 0x00, \ - _nEPs, TUSB_CLASS_VIDEO, VIDEO_SUBCLASS_CONTROL, VIDEO_INT_PROTOCOL_CODE_15, _stridx + _nEPs, TUSB_CLASS_VIDEO, VIDEO_SUBCLASS_CONTROL, VIDEO_ITF_PROTOCOL_15, _stridx /* 3.7.2 */ #define TUD_VIDEO_DESC_CS_VC(_bcdUVC, _totallen, _clkfreq, ...) \ - TUD_VIDEO_DESC_CS_VC_LEN + (TU_ARGS_NUM(__VA_ARGS__)), TUSB_DESC_CS_INTERFACE, VIDEO_CS_VC_INTERFACE_HEADER, \ + TUD_VIDEO_DESC_CS_VC_LEN + (TU_ARGS_NUM(__VA_ARGS__)), TUSB_DESC_CS_INTERFACE, VIDEO_CS_VC_HEADER, \ U16_TO_U8S_LE(_bcdUVC), U16_TO_U8S_LE((_totallen) + TUD_VIDEO_DESC_CS_VC_LEN + (TU_ARGS_NUM(__VA_ARGS__))), \ U32_TO_U8S_LE(_clkfreq), TU_ARGS_NUM(__VA_ARGS__), __VA_ARGS__ /* 3.7.2.1 */ #define TUD_VIDEO_DESC_INPUT_TERM(_tid, _tt, _at, _stridx) \ - TUD_VIDEO_DESC_INPUT_TERM_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VC_INTERFACE_INPUT_TERMINAL, \ + TUD_VIDEO_DESC_INPUT_TERM_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VC_INPUT_TERMINAL, \ _tid, U16_TO_U8S_LE(_tt), _at, _stridx /* 3.7.2.2 */ #define TUD_VIDEO_DESC_OUTPUT_TERM(_tid, _tt, _at, _srcid, _stridx) \ - TUD_VIDEO_DESC_OUTPUT_TERM_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VC_INTERFACE_OUTPUT_TERMINAL, \ + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VC_OUTPUT_TERMINAL, \ _tid, U16_TO_U8S_LE(_tt), _at, _srcid, _stridx /* 3.9.1 */ #define TUD_VIDEO_DESC_STD_VS(_itfnum, _alt, _epn, _stridx) \ TUD_VIDEO_DESC_STD_VS_LEN, TUSB_DESC_INTERFACE, _itfnum, _alt, \ - _epn, TUSB_CLASS_VIDEO, VIDEO_SUBCLASS_STREAMING, VIDEO_INT_PROTOCOL_CODE_15, _stridx + _epn, TUSB_CLASS_VIDEO, VIDEO_SUBCLASS_STREAMING, VIDEO_ITF_PROTOCOL_15, _stridx /* 3.9.2.1 */ #define TUD_VIDEO_DESC_CS_VS_INPUT(_numfmt, _totallen, _ep, _inf, _termlnk, _sticaptmeth, _trgspt, _trgusg, ...) \ TUD_VIDEO_DESC_CS_VS_IN_LEN + (_numfmt) * (TU_ARGS_NUM(__VA_ARGS__)), TUSB_DESC_CS_INTERFACE, \ - VIDEO_CS_VS_INTERFACE_INPUT_HEADER, _numfmt, \ + VIDEO_CS_VS_INPUT_HEADER, _numfmt, \ U16_TO_U8S_LE((_totallen) + TUD_VIDEO_DESC_CS_VS_IN_LEN + (_numfmt) * (TU_ARGS_NUM(__VA_ARGS__))), \ _ep, _inf, _termlnk, _sticaptmeth, _trgspt, _trgusg, (TU_ARGS_NUM(__VA_ARGS__)), __VA_ARGS__ /* 3.9.2.2 */ #define TUD_VIDEO_DESC_CS_VS_OUTPUT(_numfmt, _totallen, _ep, _inf, _termlnk, ...) \ TUD_VIDEO_DESC_CS_VS_OUT_LEN + (_numfmt) * (TU_ARGS_NUM(__VA_ARGS__)), TUSB_DESC_CS_INTERFACE, \ - VIDEO_CS_VS_INTERFACE_OUTPUT_HEADER, _numfmt, \ + VIDEO_CS_VS_OUTPUT_HEADER, _numfmt, \ U16_TO_U8S_LE((_totallen) + TUD_VIDEO_DESC_CS_VS_OUT_LEN + (_numfmt) * (TU_ARGS_NUM(__VA_ARGS__))), \ _ep, _inf, _termlnk, (TU_ARGS_NUM(__VA_ARGS__)), __VA_ARGS__ @@ -415,13 +436,13 @@ TU_VERIFY_STATIC( sizeof(video_probe_and_commit_control_t) == 48, "size is not c #define TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR(_fmtidx, _numfrmdesc, \ _guid, _bitsperpix, _frmidx, _asrx, _asry, _interlace, _cp) \ - TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_INTERFACE_FORMAT_UNCOMPRESSED, \ + TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_FORMAT_UNCOMPRESSED, \ _fmtidx, _numfrmdesc, TUD_VIDEO_GUID(_guid), \ _bitsperpix, _frmidx, _asrx, _asry, _interlace, _cp /* Uncompressed 3.1.2 Table 3-3 */ #define TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT(_frmidx, _cap, _width, _height, _minbr, _maxbr, _maxfrmbufsz, _frminterval, _minfrminterval, _maxfrminterval, _frmintervalstep) \ - TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_INTERFACE_FRAME_UNCOMPRESSED, \ + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_FRAME_UNCOMPRESSED, \ _frmidx, _cap, U16_TO_U8S_LE(_width), U16_TO_U8S_LE(_height), U32_TO_U8S_LE(_minbr), U32_TO_U8S_LE(_maxbr), \ U32_TO_U8S_LE(_maxfrmbufsz), U32_TO_U8S_LE(_frminterval), 0, \ U32_TO_U8S_LE(_minfrminterval), U32_TO_U8S_LE(_maxfrminterval), U32_TO_U8S_LE(_frmintervalstep) @@ -429,14 +450,14 @@ TU_VERIFY_STATIC( sizeof(video_probe_and_commit_control_t) == 48, "size is not c /* Uncompressed 3.1.2 Table 3-4 */ #define TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_DISC(_frmidx, _cap, _width, _height, _minbr, _maxbr, _maxfrmbufsz, _frminterval, ...) \ TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_DISC_LEN + (TU_ARGS_NUM(__VA_ARGS__)) * 4, \ - TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_INTERFACE_FRAME_UNCOMPRESSED, \ + TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_FRAME_UNCOMPRESSED, \ _frmidx, _cap, U16_TO_U8S_LE(_width), U16_TO_U8S_LE(_height), U32_TO_U8S_LE(_minbr), U32_TO_U8S_LE(_maxbr), \ U32_TO_U8S_LE(_maxfrmbufsz), U32_TO_U8S_LE(_frminterval), (TU_ARGS_NUM(__VA_ARGS__)), __VA_ARGS__ /* 3.9.2.6 */ #define TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING(_color, _trns, _mat) \ TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN, \ - TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_INTERFACE_COLORFORMAT, \ + TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_COLORFORMAT, \ _color, _trns, _mat /* 3.10.1.1 */ diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index ce34b1b49..a1f886ed8 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -259,8 +259,8 @@ static void const* _find_desc_entity(void const *desc, uint_fast8_t entityid) void const *end = beg + vc->std.bLength + vc->ctl.wTotalLength; for (void const *cur = beg; cur < end; cur = _find_desc(cur, end, TUSB_DESC_CS_INTERFACE)) { tusb_desc_cs_video_entity_itf_t const *itf = (tusb_desc_cs_video_entity_itf_t const *)cur; - if ((VIDEO_CS_VC_INTERFACE_INPUT_TERMINAL <= itf->bDescriptorSubtype - && itf->bDescriptorSubtype < VIDEO_CS_VC_INTERFACE_MAX) + if ((VIDEO_CS_VC_INPUT_TERMINAL <= itf->bDescriptorSubtype + && itf->bDescriptorSubtype < VIDEO_CS_VC_MAX) && itf->bEntityId == entityid) { return itf; } @@ -280,14 +280,14 @@ static inline void const* _end_of_streaming_descriptor(void const *desc) static inline tusb_desc_cs_video_fmt_uncompressed_t const *_find_desc_format(void const *beg, void const *end, uint_fast8_t fmtnum) { return (tusb_desc_cs_video_fmt_uncompressed_t const*) - _find_desc_3(beg, end, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_INTERFACE_FORMAT_UNCOMPRESSED, fmtnum); + _find_desc_3(beg, end, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_FORMAT_UNCOMPRESSED, fmtnum); } /** Find the first frame descriptor with the specified format number. */ static inline tusb_desc_cs_video_frm_uncompressed_t const *_find_desc_frame(void const *beg, void const *end, uint_fast8_t frmnum) { return (tusb_desc_cs_video_frm_uncompressed_t const*) - _find_desc_3(beg, end, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_INTERFACE_FRAME_UNCOMPRESSED, frmnum); + _find_desc_3(beg, end, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_FRAME_UNCOMPRESSED, frmnum); } /** Set uniquely determined values to variables that have not been set @@ -581,27 +581,27 @@ static int handle_video_ctl_std_req(uint8_t rhport, uint8_t stage, { switch (request->bRequest) { case TUSB_REQ_GET_INTERFACE: - if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; - TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN); + if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE; + TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN); tusb_desc_vc_itf_t const *vc = _get_desc_vc(&_videod_itf[ctl_idx]); - if (!vc) return VIDEO_UNKNOWN; + if (!vc) return VIDEO_ERROR_UNKNOWN; if (tud_control_xfer(rhport, request, (void*)&vc->std.bAlternateSetting, sizeof(vc->std.bAlternateSetting))) - return VIDEO_NO_ERROR; - return VIDEO_UNKNOWN; + return VIDEO_ERROR_NONE; + return VIDEO_ERROR_UNKNOWN; case TUSB_REQ_SET_INTERFACE: - if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; - TU_VERIFY(0 == request->wLength, VIDEO_UNKNOWN); + if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE; + TU_VERIFY(0 == request->wLength, VIDEO_ERROR_UNKNOWN); if (!_close_vc_itf(rhport, &_videod_itf[ctl_idx])) - return VIDEO_UNKNOWN; + return VIDEO_ERROR_UNKNOWN; if (!_open_vc_itf(rhport, &_videod_itf[ctl_idx], request->wValue)) - return VIDEO_UNKNOWN; + return VIDEO_ERROR_UNKNOWN; tud_control_status(rhport, request); - return VIDEO_NO_ERROR; + return VIDEO_ERROR_NONE; default: /* Unknown/Unsupported request */ TU_BREAKPOINT(); - return VIDEO_INVALID_REQUEST; + return VIDEO_ERROR_INVALID_REQUEST; } } @@ -616,41 +616,41 @@ static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage, switch (request->bRequest) { case VIDEO_REQUEST_SET_CUR: if (stage == CONTROL_STAGE_SETUP) { - TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN); + TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN); if (!tud_control_xfer(rhport, request, &self->power_mode, sizeof(self->power_mode))) - return VIDEO_UNKNOWN; + return VIDEO_ERROR_UNKNOWN; } else if (stage == CONTROL_STAGE_ACK) { if (tud_video_power_mode_cb) return tud_video_power_mode_cb(ctl_idx, self->power_mode); } - return VIDEO_NO_ERROR; + return VIDEO_ERROR_NONE; case VIDEO_REQUEST_GET_CUR: - if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; - TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN); + if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE; + TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN); if (!tud_control_xfer(rhport, request, &self->power_mode, sizeof(self->power_mode))) - return VIDEO_UNKNOWN; - return VIDEO_NO_ERROR; + return VIDEO_ERROR_UNKNOWN; + return VIDEO_ERROR_NONE; case VIDEO_REQUEST_GET_INFO: - if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; - TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN); + if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE; + TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN); if (!tud_control_xfer(rhport, request, (uint8_t*)&_cap_get_set, sizeof(_cap_get_set))) - return VIDEO_UNKNOWN; - return VIDEO_NO_ERROR; + return VIDEO_ERROR_UNKNOWN; + return VIDEO_ERROR_NONE; default: break; } break; case VIDEO_VC_CTL_REQUEST_ERROR_CODE: switch (request->bRequest) { case VIDEO_REQUEST_GET_CUR: - if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; + if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE; if (!tud_control_xfer(rhport, request, &self->error_code, sizeof(uint8_t))) - return VIDEO_UNKNOWN; - return VIDEO_NO_ERROR; + return VIDEO_ERROR_UNKNOWN; + return VIDEO_ERROR_NONE; case VIDEO_REQUEST_GET_INFO: - if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; + if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE; if (tud_control_xfer(rhport, request, (uint8_t*)&_cap_get, sizeof(_cap_get))) - return VIDEO_UNKNOWN; - return VIDEO_NO_ERROR; + return VIDEO_ERROR_UNKNOWN; + return VIDEO_ERROR_NONE; default: break; } break; @@ -658,7 +658,7 @@ static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage, } /* Unknown/Unsupported request */ TU_BREAKPOINT(); - return VIDEO_INVALID_REQUEST; + return VIDEO_ERROR_INVALID_REQUEST; } static int handle_video_ctl_req(uint8_t rhport, uint8_t stage, @@ -675,11 +675,11 @@ static int handle_video_ctl_req(uint8_t rhport, uint8_t stage, return handle_video_ctl_cs_req(rhport, stage, request, ctl_idx); } else { if (!_find_desc_entity(_get_desc_vc(&_videod_itf[ctl_idx]), entity_id)) - return VIDEO_INVALID_REQUEST; - return VIDEO_INVALID_REQUEST; + return VIDEO_ERROR_INVALID_REQUEST; + return VIDEO_ERROR_INVALID_REQUEST; } default: - return VIDEO_INVALID_REQUEST; + return VIDEO_ERROR_INVALID_REQUEST; } } @@ -690,24 +690,24 @@ static int handle_video_stm_std_req(uint8_t rhport, uint8_t stage, videod_streaming_interface_t *self = &_videod_streaming_itf[stm_idx]; switch (request->bRequest) { case TUSB_REQ_GET_INTERFACE: - if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; - TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN); + if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE; + TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN); tusb_desc_vs_itf_t const *vs = _get_desc_vs(self); - if (!vs) return VIDEO_UNKNOWN; + if (!vs) return VIDEO_ERROR_UNKNOWN; if (tud_control_xfer(rhport, request, (void*)&vs->std.bAlternateSetting, sizeof(vs->std.bAlternateSetting))) - return VIDEO_NO_ERROR; - return VIDEO_UNKNOWN; + return VIDEO_ERROR_NONE; + return VIDEO_ERROR_UNKNOWN; case TUSB_REQ_SET_INTERFACE: - if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; + if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE; if (!_open_vs_itf(rhport, self, request->wValue)) - return VIDEO_UNKNOWN; + return VIDEO_ERROR_UNKNOWN; tud_control_status(rhport, request); - return VIDEO_NO_ERROR; + return VIDEO_ERROR_NONE; default: /* Unknown/Unsupported request */ TU_BREAKPOINT(); - return VIDEO_INVALID_REQUEST; + return VIDEO_ERROR_INVALID_REQUEST; } } @@ -722,16 +722,16 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, case VIDEO_VS_CTL_STREAM_ERROR_CODE: switch (request->bRequest) { case VIDEO_REQUEST_GET_CUR: - if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; + if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE; /* TODO */ if (!tud_control_xfer(rhport, request, &self->error_code, sizeof(uint8_t))) - return VIDEO_UNKNOWN; - return VIDEO_NO_ERROR; + return VIDEO_ERROR_UNKNOWN; + return VIDEO_ERROR_NONE; case VIDEO_REQUEST_GET_INFO: - if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; + if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE; if (tud_control_xfer(rhport, request, (uint8_t*)&_cap_get, sizeof(_cap_get))) - return VIDEO_UNKNOWN; - return VIDEO_NO_ERROR; + return VIDEO_ERROR_UNKNOWN; + return VIDEO_ERROR_NONE; default: break; } break; @@ -739,56 +739,56 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, switch (request->bRequest) { case VIDEO_REQUEST_SET_CUR: if (stage == CONTROL_STAGE_SETUP) { - TU_VERIFY(sizeof(video_probe_and_commit_control_t) == request->wLength, VIDEO_UNKNOWN); + TU_VERIFY(sizeof(video_probe_and_commit_control_t) == request->wLength, VIDEO_ERROR_UNKNOWN); if (!tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t))) - return VIDEO_UNKNOWN; + return VIDEO_ERROR_UNKNOWN; } else if (stage == CONTROL_STAGE_ACK) { if (!_update_streaming_parameters(self, (video_probe_and_commit_control_t*)self->ep_buf)) - return VIDEO_INVALID_VALUE_WITHIN_RANGE; + return VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE; } - return VIDEO_NO_ERROR; + return VIDEO_ERROR_NONE; case VIDEO_REQUEST_GET_CUR: - if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; - TU_VERIFY(request->wLength, VIDEO_UNKNOWN); + if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE; + TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN); if (tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t))) - return VIDEO_NO_ERROR; - return VIDEO_UNKNOWN; + return VIDEO_ERROR_NONE; + return VIDEO_ERROR_UNKNOWN; case VIDEO_REQUEST_GET_MIN: { video_probe_and_commit_control_t tmp; - if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; - TU_VERIFY(request->wLength, VIDEO_UNKNOWN); + if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE; + TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN); tmp = *(video_probe_and_commit_control_t*)&self->ep_buf; if (!_negotiate_streaming_parameters(self, false, &tmp)) - return VIDEO_INVALID_VALUE_WITHIN_RANGE; + return VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE; if (tud_control_xfer(rhport, request, &tmp, sizeof(video_probe_and_commit_control_t))) - return VIDEO_NO_ERROR; - return VIDEO_UNKNOWN; + return VIDEO_ERROR_NONE; + return VIDEO_ERROR_UNKNOWN; } case VIDEO_REQUEST_GET_MAX: { video_probe_and_commit_control_t tmp; - if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; - TU_VERIFY(request->wLength, VIDEO_UNKNOWN); + if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE; + TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN); tmp = *(video_probe_and_commit_control_t*)&self->ep_buf; if (!_negotiate_streaming_parameters(self, true, &tmp)) - return VIDEO_INVALID_VALUE_WITHIN_RANGE; + return VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE; if (tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t))) - return VIDEO_NO_ERROR; - return VIDEO_UNKNOWN; + return VIDEO_ERROR_NONE; + return VIDEO_ERROR_UNKNOWN; } case VIDEO_REQUEST_GET_RES: - return VIDEO_UNKNOWN; + return VIDEO_ERROR_UNKNOWN; case VIDEO_REQUEST_GET_DEF: - return VIDEO_UNKNOWN; + return VIDEO_ERROR_UNKNOWN; case VIDEO_REQUEST_GET_LEN: - return VIDEO_UNKNOWN; + return VIDEO_ERROR_UNKNOWN; case VIDEO_REQUEST_GET_INFO: - if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; - TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN); + if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE; + TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN); if (tud_control_xfer(rhport, request, (uint8_t*)&_cap_get_set, sizeof(_cap_get_set))) - return VIDEO_NO_ERROR; - return VIDEO_UNKNOWN; + return VIDEO_ERROR_NONE; + return VIDEO_ERROR_UNKNOWN; default: break; } break; @@ -796,29 +796,29 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, switch (request->bRequest) { case VIDEO_REQUEST_SET_CUR: if (stage == CONTROL_STAGE_SETUP) { - TU_VERIFY(sizeof(video_probe_and_commit_control_t) == request->wLength, VIDEO_UNKNOWN); + TU_VERIFY(sizeof(video_probe_and_commit_control_t) == request->wLength, VIDEO_ERROR_UNKNOWN); if (!tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t))) - return VIDEO_UNKNOWN; + return VIDEO_ERROR_UNKNOWN; } else if (stage == CONTROL_STAGE_ACK) { if (!_update_streaming_parameters(self, (video_probe_and_commit_control_t*)self->ep_buf)) - return VIDEO_INVALID_VALUE_WITHIN_RANGE; + return VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE; if (tud_video_commit_cb) return tud_video_commit_cb(self->index_vc, self->index_vs, (video_probe_and_commit_control_t*)self->ep_buf); } - return VIDEO_NO_ERROR; + return VIDEO_ERROR_NONE; case VIDEO_REQUEST_GET_CUR: - if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; - TU_VERIFY(request->wLength, VIDEO_UNKNOWN); + if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE; + TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN); if (tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t))) - return VIDEO_NO_ERROR; - return VIDEO_UNKNOWN; + return VIDEO_ERROR_NONE; + return VIDEO_ERROR_UNKNOWN; case VIDEO_REQUEST_GET_INFO: - if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR; - TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN); + if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE; + TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN); if (tud_control_xfer(rhport, request, (uint8_t*)&_cap_get_set, sizeof(_cap_get_set))) - return VIDEO_NO_ERROR; - return VIDEO_UNKNOWN; + return VIDEO_ERROR_NONE; + return VIDEO_ERROR_UNKNOWN; default: break; } break; @@ -834,7 +834,7 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, } /* Unknown/Unsupported request */ TU_BREAKPOINT(); - return VIDEO_INVALID_REQUEST; + return VIDEO_ERROR_INVALID_REQUEST; } static int handle_video_stm_req(uint8_t rhport, uint8_t stage, @@ -846,12 +846,12 @@ static int handle_video_stm_req(uint8_t rhport, uint8_t stage, return handle_video_stm_std_req(rhport, stage, request, stm_idx); case TUSB_REQ_TYPE_CLASS: if (TU_U16_HIGH(request->wIndex)) - return VIDEO_INVALID_REQUEST; + return VIDEO_ERROR_INVALID_REQUEST; return handle_video_stm_cs_req(rhport, stage, request, stm_idx); default: - return VIDEO_INVALID_REQUEST; + return VIDEO_ERROR_INVALID_REQUEST; } - return VIDEO_UNKNOWN; + return VIDEO_ERROR_UNKNOWN; } //--------------------------------------------------------------------+ @@ -942,9 +942,9 @@ void videod_reset(uint8_t rhport) uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len) { - TU_VERIFY((TUSB_CLASS_VIDEO == itf_desc->bInterfaceClass) && - (VIDEO_SUBCLASS_CONTROL == itf_desc->bInterfaceSubClass) && - (VIDEO_INT_PROTOCOL_CODE_15 == itf_desc->bInterfaceProtocol), 0); + TU_VERIFY((TUSB_CLASS_VIDEO == itf_desc->bInterfaceClass) && + (VIDEO_SUBCLASS_CONTROL == itf_desc->bInterfaceSubClass) && + (VIDEO_ITF_PROTOCOL_15 == itf_desc->bInterfaceProtocol), 0); /* Find available interface */ videod_interface_t *self = NULL; -- cgit v1.3.1 From 7afcb1e5d51ebbbbf602840887949dc69b33c5b4 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 12 Oct 2021 00:56:20 +0700 Subject: minor code clean up without functionality changes --- src/class/video/video_device.c | 505 +++++++++++++++++++++-------------------- 1 file changed, 263 insertions(+), 242 deletions(-) diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index a1f886ed8..da190da47 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -1,9 +1,8 @@ /* * The MIT License (MIT) * - * Copyright (c) 2019 Ha Thach (tinyusb.org) - * Copyright (c) 2020 Reinhard Panhuber, Jerzy Kasenberg * Copyright (c) 2021 Koji KITAYAMA + * Copyright (c) 2019 Ha Thach (tinyusb.org) * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -300,8 +299,7 @@ static bool _update_streaming_parameters(videod_streaming_interface_t const *stm uint_fast8_t fmtnum = param->bFormatIndex; TU_ASSERT(fmtnum <= vs->stm.bNumFormats); if (!fmtnum) { - if (1 < vs->stm.bNumFormats) - return true; /* Need to negotiate all variables. */ + if (1 < vs->stm.bNumFormats) return true; /* Need to negotiate all variables. */ fmtnum = 1; param->bFormatIndex = 1; } @@ -326,8 +324,7 @@ static bool _update_streaming_parameters(videod_streaming_interface_t const *stm uint_fast8_t frmnum = param->bFrameIndex; TU_ASSERT(frmnum <= fmt->bNumFrameDescriptors); if (!frmnum) { - if (1 < fmt->bNumFrameDescriptors) - return true; + if (1 < fmt->bNumFrameDescriptors) return true; frmnum = 1; param->bFrameIndex = 1; } @@ -344,8 +341,9 @@ static bool _update_streaming_parameters(videod_streaming_interface_t const *stm uint_fast32_t interval = param->dwFrameInterval; if (!interval) { if ((1 < frm->bFrameIntervalType) || - ((0 == frm->bFrameIntervalType) && (frm->dwFrameInterval[1] != frm->dwFrameInterval[0]))) + ((0 == frm->bFrameIntervalType) && (frm->dwFrameInterval[1] != frm->dwFrameInterval[0]))) { return true; + } interval = frm->dwFrameInterval[0]; param->dwFrameInterval = interval; } @@ -580,28 +578,31 @@ static int handle_video_ctl_std_req(uint8_t rhport, uint8_t stage, uint_fast8_t ctl_idx) { switch (request->bRequest) { - case TUSB_REQ_GET_INTERFACE: - if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE; - TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN); - tusb_desc_vc_itf_t const *vc = _get_desc_vc(&_videod_itf[ctl_idx]); - if (!vc) return VIDEO_ERROR_UNKNOWN; - if (tud_control_xfer(rhport, request, - (void*)&vc->std.bAlternateSetting, - sizeof(vc->std.bAlternateSetting))) + case TUSB_REQ_GET_INTERFACE: + if (stage == CONTROL_STAGE_SETUP) + { + TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN); + tusb_desc_vc_itf_t const *vc = _get_desc_vc(&_videod_itf[ctl_idx]); + TU_VERIFY(vc, VIDEO_ERROR_UNKNOWN); + + TU_VERIFY(tud_control_xfer(rhport, request, (void*)&vc->std.bAlternateSetting, sizeof(vc->std.bAlternateSetting)), + VIDEO_ERROR_UNKNOWN); + } return VIDEO_ERROR_NONE; - return VIDEO_ERROR_UNKNOWN; - case TUSB_REQ_SET_INTERFACE: - if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE; - TU_VERIFY(0 == request->wLength, VIDEO_ERROR_UNKNOWN); - if (!_close_vc_itf(rhport, &_videod_itf[ctl_idx])) - return VIDEO_ERROR_UNKNOWN; - if (!_open_vc_itf(rhport, &_videod_itf[ctl_idx], request->wValue)) - return VIDEO_ERROR_UNKNOWN; - tud_control_status(rhport, request); - return VIDEO_ERROR_NONE; - default: /* Unknown/Unsupported request */ - TU_BREAKPOINT(); - return VIDEO_ERROR_INVALID_REQUEST; + + case TUSB_REQ_SET_INTERFACE: + if (stage == CONTROL_STAGE_SETUP) + { + TU_VERIFY(0 == request->wLength, VIDEO_ERROR_UNKNOWN); + TU_VERIFY(_close_vc_itf(rhport, &_videod_itf[ctl_idx]), VIDEO_ERROR_UNKNOWN); + TU_VERIFY(_open_vc_itf(rhport, &_videod_itf[ctl_idx], request->wValue), VIDEO_ERROR_UNKNOWN); + tud_control_status(rhport, request); + } + return VIDEO_ERROR_NONE; + + default: /* Unknown/Unsupported request */ + TU_BREAKPOINT(); + return VIDEO_ERROR_INVALID_REQUEST; } } @@ -610,52 +611,63 @@ static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage, uint_fast8_t ctl_idx) { videod_interface_t *self = &_videod_itf[ctl_idx]; + /* 4.2.1 Interface Control Request */ switch (TU_U16_HIGH(request->wValue)) { - case VIDEO_VC_CTL_VIDEO_POWER_MODE: - switch (request->bRequest) { - case VIDEO_REQUEST_SET_CUR: - if (stage == CONTROL_STAGE_SETUP) { - TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN); - if (!tud_control_xfer(rhport, request, &self->power_mode, sizeof(self->power_mode))) - return VIDEO_ERROR_UNKNOWN; - } else if (stage == CONTROL_STAGE_ACK) { - if (tud_video_power_mode_cb) - return tud_video_power_mode_cb(ctl_idx, self->power_mode); + case VIDEO_VC_CTL_VIDEO_POWER_MODE: + switch (request->bRequest) { + case VIDEO_REQUEST_SET_CUR: + if (stage == CONTROL_STAGE_SETUP) { + TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN); + TU_VERIFY(tud_control_xfer(rhport, request, &self->power_mode, sizeof(self->power_mode)), VIDEO_ERROR_UNKNOWN); + } else if (stage == CONTROL_STAGE_ACK) { + if (tud_video_power_mode_cb) return tud_video_power_mode_cb(ctl_idx, self->power_mode); + } + return VIDEO_ERROR_NONE; + + case VIDEO_REQUEST_GET_CUR: + if (stage == CONTROL_STAGE_SETUP) + { + TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN); + TU_VERIFY(tud_control_xfer(rhport, request, &self->power_mode, sizeof(self->power_mode)), VIDEO_ERROR_UNKNOWN); + } + return VIDEO_ERROR_NONE; + + case VIDEO_REQUEST_GET_INFO: + if (stage == CONTROL_STAGE_SETUP) + { + TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN); + TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)&_cap_get_set, sizeof(_cap_get_set)), VIDEO_ERROR_UNKNOWN); + } + return VIDEO_ERROR_NONE; + + default: break; } - return VIDEO_ERROR_NONE; - case VIDEO_REQUEST_GET_CUR: - if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE; - TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN); - if (!tud_control_xfer(rhport, request, &self->power_mode, sizeof(self->power_mode))) - return VIDEO_ERROR_UNKNOWN; - return VIDEO_ERROR_NONE; - case VIDEO_REQUEST_GET_INFO: - if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE; - TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN); - if (!tud_control_xfer(rhport, request, (uint8_t*)&_cap_get_set, sizeof(_cap_get_set))) - return VIDEO_ERROR_UNKNOWN; - return VIDEO_ERROR_NONE; - default: break; - } - break; - case VIDEO_VC_CTL_REQUEST_ERROR_CODE: - switch (request->bRequest) { - case VIDEO_REQUEST_GET_CUR: - if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE; - if (!tud_control_xfer(rhport, request, &self->error_code, sizeof(uint8_t))) - return VIDEO_ERROR_UNKNOWN; - return VIDEO_ERROR_NONE; - case VIDEO_REQUEST_GET_INFO: - if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE; - if (tud_control_xfer(rhport, request, (uint8_t*)&_cap_get, sizeof(_cap_get))) - return VIDEO_ERROR_UNKNOWN; - return VIDEO_ERROR_NONE; + break; + + case VIDEO_VC_CTL_REQUEST_ERROR_CODE: + switch (request->bRequest) { + case VIDEO_REQUEST_GET_CUR: + if (stage == CONTROL_STAGE_SETUP) + { + TU_VERIFY(tud_control_xfer(rhport, request, &self->error_code, sizeof(uint8_t)), VIDEO_ERROR_UNKNOWN); + } + return VIDEO_ERROR_NONE; + + case VIDEO_REQUEST_GET_INFO: + if (stage == CONTROL_STAGE_SETUP) + { + TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)&_cap_get, sizeof(_cap_get)), VIDEO_ERROR_UNKNOWN); + } + return VIDEO_ERROR_NONE; + + default: break; + } + break; + default: break; - } - break; - default: break; } + /* Unknown/Unsupported request */ TU_BREAKPOINT(); return VIDEO_ERROR_INVALID_REQUEST; @@ -667,19 +679,20 @@ static int handle_video_ctl_req(uint8_t rhport, uint8_t stage, { uint_fast8_t entity_id; switch (request->bmRequestType_bit.type) { - case TUSB_REQ_TYPE_STANDARD: - return handle_video_ctl_std_req(rhport, stage, request, ctl_idx); - case TUSB_REQ_TYPE_CLASS: - entity_id = TU_U16_HIGH(request->wIndex); - if (!entity_id) { - return handle_video_ctl_cs_req(rhport, stage, request, ctl_idx); - } else { - if (!_find_desc_entity(_get_desc_vc(&_videod_itf[ctl_idx]), entity_id)) - return VIDEO_ERROR_INVALID_REQUEST; + case TUSB_REQ_TYPE_STANDARD: + return handle_video_ctl_std_req(rhport, stage, request, ctl_idx); + + case TUSB_REQ_TYPE_CLASS: + entity_id = TU_U16_HIGH(request->wIndex); + if (!entity_id) { + return handle_video_ctl_cs_req(rhport, stage, request, ctl_idx); + } else { + TU_VERIFY(_find_desc_entity(_get_desc_vc(&_videod_itf[ctl_idx]), entity_id), VIDEO_ERROR_INVALID_REQUEST); + return VIDEO_ERROR_NONE; + } + + default: return VIDEO_ERROR_INVALID_REQUEST; - } - default: - return VIDEO_ERROR_INVALID_REQUEST; } } @@ -689,25 +702,27 @@ static int handle_video_stm_std_req(uint8_t rhport, uint8_t stage, { videod_streaming_interface_t *self = &_videod_streaming_itf[stm_idx]; switch (request->bRequest) { - case TUSB_REQ_GET_INTERFACE: - if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE; - TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN); - tusb_desc_vs_itf_t const *vs = _get_desc_vs(self); - if (!vs) return VIDEO_ERROR_UNKNOWN; - if (tud_control_xfer(rhport, request, - (void*)&vs->std.bAlternateSetting, - sizeof(vs->std.bAlternateSetting))) + case TUSB_REQ_GET_INTERFACE: + if (stage == CONTROL_STAGE_SETUP) + { + TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN); + tusb_desc_vs_itf_t const *vs = _get_desc_vs(self); + TU_VERIFY(vs, VIDEO_ERROR_UNKNOWN); + TU_VERIFY(tud_control_xfer(rhport, request, (void*)&vs->std.bAlternateSetting, sizeof(vs->std.bAlternateSetting)), VIDEO_ERROR_UNKNOWN); + } return VIDEO_ERROR_NONE; - return VIDEO_ERROR_UNKNOWN; - case TUSB_REQ_SET_INTERFACE: - if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE; - if (!_open_vs_itf(rhport, self, request->wValue)) - return VIDEO_ERROR_UNKNOWN; - tud_control_status(rhport, request); - return VIDEO_ERROR_NONE; - default: /* Unknown/Unsupported request */ - TU_BREAKPOINT(); - return VIDEO_ERROR_INVALID_REQUEST; + + case TUSB_REQ_SET_INTERFACE: + if (stage == CONTROL_STAGE_SETUP) + { + TU_VERIFY(_open_vs_itf(rhport, self, request->wValue), VIDEO_ERROR_UNKNOWN); + tud_control_status(rhport, request); + } + return VIDEO_ERROR_NONE; + + default: /* Unknown/Unsupported request */ + TU_BREAKPOINT(); + return VIDEO_ERROR_INVALID_REQUEST; } } @@ -717,121 +732,136 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, { (void)rhport; videod_streaming_interface_t *self = &_videod_streaming_itf[stm_idx]; + /* 4.2.1 Interface Control Request */ switch (TU_U16_HIGH(request->wValue)) { - case VIDEO_VS_CTL_STREAM_ERROR_CODE: - switch (request->bRequest) { - case VIDEO_REQUEST_GET_CUR: - if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE; - /* TODO */ - if (!tud_control_xfer(rhport, request, &self->error_code, sizeof(uint8_t))) - return VIDEO_ERROR_UNKNOWN; - return VIDEO_ERROR_NONE; - case VIDEO_REQUEST_GET_INFO: - if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE; - if (tud_control_xfer(rhport, request, (uint8_t*)&_cap_get, sizeof(_cap_get))) - return VIDEO_ERROR_UNKNOWN; - return VIDEO_ERROR_NONE; - default: break; - } - break; - case VIDEO_VS_CTL_PROBE: - switch (request->bRequest) { - case VIDEO_REQUEST_SET_CUR: - if (stage == CONTROL_STAGE_SETUP) { - TU_VERIFY(sizeof(video_probe_and_commit_control_t) == request->wLength, VIDEO_ERROR_UNKNOWN); - if (!tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t))) - return VIDEO_ERROR_UNKNOWN; - } else if (stage == CONTROL_STAGE_ACK) { - if (!_update_streaming_parameters(self, (video_probe_and_commit_control_t*)self->ep_buf)) - return VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE; + case VIDEO_VS_CTL_STREAM_ERROR_CODE: + switch (request->bRequest) { + case VIDEO_REQUEST_GET_CUR: + if (stage == CONTROL_STAGE_SETUP) + { + /* TODO */ + TU_VERIFY(tud_control_xfer(rhport, request, &self->error_code, sizeof(uint8_t)), VIDEO_ERROR_UNKNOWN); + } + return VIDEO_ERROR_NONE; + + case VIDEO_REQUEST_GET_INFO: + if (stage == CONTROL_STAGE_SETUP) + { + TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)&_cap_get, sizeof(_cap_get)), VIDEO_ERROR_UNKNOWN); + } + return VIDEO_ERROR_NONE; + + default: break; } - return VIDEO_ERROR_NONE; - case VIDEO_REQUEST_GET_CUR: - if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE; - TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN); - if (tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t))) - return VIDEO_ERROR_NONE; - return VIDEO_ERROR_UNKNOWN; - case VIDEO_REQUEST_GET_MIN: { - video_probe_and_commit_control_t tmp; - if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE; - TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN); - tmp = *(video_probe_and_commit_control_t*)&self->ep_buf; - if (!_negotiate_streaming_parameters(self, false, &tmp)) - return VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE; - if (tud_control_xfer(rhport, request, &tmp, - sizeof(video_probe_and_commit_control_t))) - return VIDEO_ERROR_NONE; - return VIDEO_ERROR_UNKNOWN; - } - case VIDEO_REQUEST_GET_MAX: { - video_probe_and_commit_control_t tmp; - if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE; - TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN); - tmp = *(video_probe_and_commit_control_t*)&self->ep_buf; - if (!_negotiate_streaming_parameters(self, true, &tmp)) - return VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE; - if (tud_control_xfer(rhport, request, self->ep_buf, - sizeof(video_probe_and_commit_control_t))) - return VIDEO_ERROR_NONE; - return VIDEO_ERROR_UNKNOWN; - } - case VIDEO_REQUEST_GET_RES: - return VIDEO_ERROR_UNKNOWN; - case VIDEO_REQUEST_GET_DEF: - return VIDEO_ERROR_UNKNOWN; - case VIDEO_REQUEST_GET_LEN: - return VIDEO_ERROR_UNKNOWN; - case VIDEO_REQUEST_GET_INFO: - if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE; - TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN); - if (tud_control_xfer(rhport, request, (uint8_t*)&_cap_get_set, sizeof(_cap_get_set))) - return VIDEO_ERROR_NONE; - return VIDEO_ERROR_UNKNOWN; - default: break; - } - break; - case VIDEO_VS_CTL_COMMIT: - switch (request->bRequest) { - case VIDEO_REQUEST_SET_CUR: - if (stage == CONTROL_STAGE_SETUP) { - TU_VERIFY(sizeof(video_probe_and_commit_control_t) == request->wLength, VIDEO_ERROR_UNKNOWN); - if (!tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t))) - return VIDEO_ERROR_UNKNOWN; - } else if (stage == CONTROL_STAGE_ACK) { - if (!_update_streaming_parameters(self, (video_probe_and_commit_control_t*)self->ep_buf)) - return VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE; - if (tud_video_commit_cb) - return tud_video_commit_cb(self->index_vc, self->index_vs, - (video_probe_and_commit_control_t*)self->ep_buf); + break; + + case VIDEO_VS_CTL_PROBE: + switch (request->bRequest) { + case VIDEO_REQUEST_SET_CUR: + if (stage == CONTROL_STAGE_SETUP) { + TU_VERIFY(sizeof(video_probe_and_commit_control_t) == request->wLength, VIDEO_ERROR_UNKNOWN); + TU_VERIFY(tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)), + VIDEO_ERROR_UNKNOWN); + } else if (stage == CONTROL_STAGE_ACK) { + TU_VERIFY(_update_streaming_parameters(self, (video_probe_and_commit_control_t*)self->ep_buf), + VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE); + } + return VIDEO_ERROR_NONE; + + case VIDEO_REQUEST_GET_CUR: + if (stage == CONTROL_STAGE_SETUP) + { + TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN); + TU_VERIFY(tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN); + } + return VIDEO_ERROR_NONE; + + case VIDEO_REQUEST_GET_MIN: + if (stage == CONTROL_STAGE_SETUP) + { + TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN); + + video_probe_and_commit_control_t tmp; + tmp = *(video_probe_and_commit_control_t*)&self->ep_buf; + TU_VERIFY(_negotiate_streaming_parameters(self, false, &tmp), VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE); + TU_VERIFY(tud_control_xfer(rhport, request, &tmp, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN); + } + return VIDEO_ERROR_NONE; + + case VIDEO_REQUEST_GET_MAX: + if (stage == CONTROL_STAGE_SETUP) + { + TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN); + video_probe_and_commit_control_t tmp; + tmp = *(video_probe_and_commit_control_t*)&self->ep_buf; + TU_VERIFY(_negotiate_streaming_parameters(self, true, &tmp), VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE); + TU_VERIFY(tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN); + } + return VIDEO_ERROR_NONE; + + case VIDEO_REQUEST_GET_RES: return VIDEO_ERROR_UNKNOWN; + case VIDEO_REQUEST_GET_DEF: return VIDEO_ERROR_UNKNOWN; + case VIDEO_REQUEST_GET_LEN: return VIDEO_ERROR_UNKNOWN; + + case VIDEO_REQUEST_GET_INFO: + if (stage == CONTROL_STAGE_SETUP) + { + TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN); + TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)&_cap_get_set, sizeof(_cap_get_set)), VIDEO_ERROR_UNKNOWN); + } + return VIDEO_ERROR_NONE; + + default: break; } - return VIDEO_ERROR_NONE; - case VIDEO_REQUEST_GET_CUR: - if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE; - TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN); - if (tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t))) - return VIDEO_ERROR_NONE; - return VIDEO_ERROR_UNKNOWN; - case VIDEO_REQUEST_GET_INFO: - if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE; - TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN); - if (tud_control_xfer(rhport, request, (uint8_t*)&_cap_get_set, sizeof(_cap_get_set))) - return VIDEO_ERROR_NONE; - return VIDEO_ERROR_UNKNOWN; + break; + + case VIDEO_VS_CTL_COMMIT: + switch (request->bRequest) { + case VIDEO_REQUEST_SET_CUR: + if (stage == CONTROL_STAGE_SETUP) { + TU_VERIFY(sizeof(video_probe_and_commit_control_t) == request->wLength, VIDEO_ERROR_UNKNOWN); + TU_VERIFY(tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN); + } else if (stage == CONTROL_STAGE_ACK) { + TU_VERIFY(_update_streaming_parameters(self, (video_probe_and_commit_control_t*)self->ep_buf), VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE); + if (tud_video_commit_cb) { + return tud_video_commit_cb(self->index_vc, self->index_vs, (video_probe_and_commit_control_t*)self->ep_buf); + } + } + return VIDEO_ERROR_NONE; + + case VIDEO_REQUEST_GET_CUR: + if (stage == CONTROL_STAGE_SETUP) + { + TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN); + TU_VERIFY(tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN); + } + return VIDEO_ERROR_NONE; + + case VIDEO_REQUEST_GET_INFO: + if (stage == CONTROL_STAGE_SETUP) + { + TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN); + TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)&_cap_get_set, sizeof(_cap_get_set)), VIDEO_ERROR_UNKNOWN); + } + return VIDEO_ERROR_NONE; + + default: break; + } + break; + + case VIDEO_VS_CTL_STILL_PROBE: + case VIDEO_VS_CTL_STILL_COMMIT: + case VIDEO_VS_CTL_STILL_IMAGE_TRIGGER: + case VIDEO_VS_CTL_GENERATE_KEY_FRAME: + case VIDEO_VS_CTL_UPDATE_FRAME_SEGMENT: + case VIDEO_VS_CTL_SYNCH_DELAY_CONTROL: + /* TODO */ + break; + default: break; - } - break; - case VIDEO_VS_CTL_STILL_PROBE: - case VIDEO_VS_CTL_STILL_COMMIT: - case VIDEO_VS_CTL_STILL_IMAGE_TRIGGER: - case VIDEO_VS_CTL_GENERATE_KEY_FRAME: - case VIDEO_VS_CTL_UPDATE_FRAME_SEGMENT: - case VIDEO_VS_CTL_SYNCH_DELAY_CONTROL: - /* TODO */ - break; - default: break; } + /* Unknown/Unsupported request */ TU_BREAKPOINT(); return VIDEO_ERROR_INVALID_REQUEST; @@ -842,14 +872,14 @@ static int handle_video_stm_req(uint8_t rhport, uint8_t stage, uint_fast8_t stm_idx) { switch (request->bmRequestType_bit.type) { - case TUSB_REQ_TYPE_STANDARD: - return handle_video_stm_std_req(rhport, stage, request, stm_idx); - case TUSB_REQ_TYPE_CLASS: - if (TU_U16_HIGH(request->wIndex)) - return VIDEO_ERROR_INVALID_REQUEST; - return handle_video_stm_cs_req(rhport, stage, request, stm_idx); - default: - return VIDEO_ERROR_INVALID_REQUEST; + case TUSB_REQ_TYPE_STANDARD: + return handle_video_stm_std_req(rhport, stage, request, stm_idx); + + case TUSB_REQ_TYPE_CLASS: + if (TU_U16_HIGH(request->wIndex)) return VIDEO_ERROR_INVALID_REQUEST; + return handle_video_stm_cs_req(rhport, stage, request, stm_idx); + + default: return VIDEO_ERROR_INVALID_REQUEST; } return VIDEO_ERROR_UNKNOWN; } @@ -862,8 +892,7 @@ bool tud_video_n_connected(uint_fast8_t ctl_idx) { TU_ASSERT(ctl_idx < CFG_TUD_VIDEO); videod_streaming_interface_t *stm = _get_instance_streaming(ctl_idx, 0); - if (stm) - return true; + if (stm) return true; return false; } @@ -872,8 +901,7 @@ bool tud_video_n_streaming(uint_fast8_t ctl_idx, uint_fast8_t stm_idx) TU_ASSERT(ctl_idx < CFG_TUD_VIDEO); TU_ASSERT(stm_idx < CFG_TUD_VIDEO_STREAMING); videod_streaming_interface_t *stm = _get_instance_streaming(ctl_idx, stm_idx); - if (!stm || !stm->desc.ep[0]) - return false; + if (!stm || !stm->desc.ep[0]) return false; return true; } @@ -881,11 +909,9 @@ bool tud_video_n_frame_xfer(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, void *bu { TU_ASSERT(ctl_idx < CFG_TUD_VIDEO); TU_ASSERT(stm_idx < CFG_TUD_VIDEO_STREAMING); - if (!buffer || !buffer) - return false; + if (!buffer || !buffer) return false; videod_streaming_interface_t *stm = _get_instance_streaming(ctl_idx, stm_idx); - if (!stm || !stm->desc.ep[0] || stm->buffer) - return false; + if (!stm || !stm->desc.ep[0] || stm->buffer) return false; /* Find EP address */ void const *desc = _videod_itf[stm->index_vc].beg; @@ -896,8 +922,7 @@ bool tud_video_n_frame_xfer(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, void *bu ep_addr = _desc_ep_addr(desc + ofs_ep); break; } - if (!ep_addr) - return false; + if (!ep_addr) return false; TU_VERIFY( usbd_edpt_claim(0, ep_addr)); /* update the packet header */ @@ -950,8 +975,7 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin videod_interface_t *self = NULL; uint_fast8_t ctl_idx; for (ctl_idx = 0; ctl_idx < CFG_TUD_VIDEO; ++ctl_idx) { - if (_videod_itf[ctl_idx].beg) - continue; + if (_videod_itf[ctl_idx].beg) continue; self = &_videod_itf[ctl_idx]; break; } @@ -961,8 +985,7 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin self->beg = itf_desc; self->len = max_len; /*------------- Video Control Interface -------------*/ - if (!_open_vc_itf(rhport, self, 0)) - return 0; + TU_VERIFY(_open_vc_itf(rhport, self, 0), 0); tusb_desc_vc_itf_t const *vc = _get_desc_vc(self); uint_fast8_t bInCollection = vc->ctl.bInCollection; /* Find the end of the video interface descriptor */ @@ -971,8 +994,7 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin videod_streaming_interface_t *stm = NULL; /* find free streaming interface handle */ for (uint_fast8_t i = 0; i < CFG_TUD_VIDEO_STREAMING; ++i) { - if (_videod_streaming_itf[i].desc.beg) - continue; + if (_videod_streaming_itf[i].desc.beg) continue; stm = &_videod_streaming_itf[i]; self->stm[stm_idx] = i; break; @@ -994,9 +1016,7 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request) { int err; - if (request->bmRequestType_bit.recipient != TUSB_REQ_RCPT_INTERFACE) { - return false; - } + TU_VERIFY(request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_INTERFACE); uint_fast8_t itfnum = tu_u16_low(request->wIndex); /* Identify which control interface to use */ @@ -1004,9 +1024,9 @@ bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_ for (itf = 0; itf < CFG_TUD_VIDEO; ++itf) { void const *desc = _videod_itf[itf].beg; if (!desc) continue; - if (itfnum == _desc_itfnum(desc)) - break; + if (itfnum == _desc_itfnum(desc)) break; } + if (itf < CFG_TUD_VIDEO) { err = handle_video_ctl_req(rhport, stage, request, itf); _videod_itf[itf].error_code = (uint8_t)err; @@ -1019,9 +1039,9 @@ bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_ videod_streaming_interface_t *stm = &_videod_streaming_itf[itf]; if (!stm->desc.beg) continue; void const *desc = _videod_itf[stm->index_vc].beg; - if (itfnum == _desc_itfnum(desc + stm->desc.beg)) - break; + if (itfnum == _desc_itfnum(desc + stm->desc.beg)) break; } + if (itf < CFG_TUD_VIDEO_STREAMING) { err = handle_video_stm_req(rhport, stage, request, itf); _videod_streaming_itf[itf].error_code = (uint8_t)err; @@ -1045,9 +1065,9 @@ bool videod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3 if (!ep_ofs) continue; ctl = &_videod_itf[stm->index_vc]; void const *desc = ctl->beg; - if (ep_addr == _desc_ep_addr(desc + ep_ofs)) - break; + if (ep_addr == _desc_ep_addr(desc + ep_ofs)) break; } + TU_ASSERT(itf < CFG_TUD_VIDEO_STREAMING); if (stm->offset < stm->bufsize) { /* Claim the endpoint */ @@ -1058,8 +1078,9 @@ bool videod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3 stm->buffer = NULL; stm->bufsize = 0; stm->offset = 0; - if (tud_video_frame_xfer_complete_cb) + if (tud_video_frame_xfer_complete_cb) { tud_video_frame_xfer_complete_cb(stm->index_vc, stm->index_vs); + } } return true; } -- cgit v1.3.1 From 4d9e44e09c768cad57a9bd63bc8c33034a622bf1 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 12 Oct 2021 01:12:26 +0700 Subject: more rename --- src/class/video/video.h | 76 +++++++++++++++++++++--------------------- src/class/video/video_device.c | 8 ++--- 2 files changed, 42 insertions(+), 42 deletions(-) diff --git a/src/class/video/video.h b/src/class/video/video.h index 8288e4961..b24eb0bcc 100644 --- a/src/class/video/video.h +++ b/src/class/video/video.h @@ -91,39 +91,39 @@ typedef enum { /* A.5 Class-Specific VideoControl Interface Descriptor Subtypes */ typedef enum { - VIDEO_CS_VC_UNDEFINED = 0x00, - VIDEO_CS_VC_HEADER, - VIDEO_CS_VC_INPUT_TERMINAL, - VIDEO_CS_VC_OUTPUT_TERMINAL, - VIDEO_CS_VC_SELECTOR_UNIT, - VIDEO_CS_VC_PROCESSING_UNIT, - VIDEO_CS_VC_EXTENSION_UNIT, - VIDEO_CS_VC_ENCODING_UNIT, - VIDEO_CS_VC_MAX, + VIDEO_CS_ITF_VC_UNDEFINED = 0x00, + VIDEO_CS_ITF_VC_HEADER, + VIDEO_CS_ITF_VC_INPUT_TERMINAL, + VIDEO_CS_ITF_VC_OUTPUT_TERMINAL, + VIDEO_CS_ITF_VC_SELECTOR_UNIT, + VIDEO_CS_ITF_VC_PROCESSING_UNIT, + VIDEO_CS_ITF_VC_EXTENSION_UNIT, + VIDEO_CS_ITF_VC_ENCODING_UNIT, + VIDEO_CS_ITF_VC_MAX, } video_cs_vc_interface_subtype_t; /* A.6 Class-Specific VideoStreaming Interface Descriptor Subtypes */ typedef enum { - VIDEO_CS_VS_UNDEFINED = 0x00, - VIDEO_CS_VS_INPUT_HEADER = 0x01, - VIDEO_CS_VS_OUTPUT_HEADER = 0x02, - VIDEO_CS_VS_STILL_IMAGE_FRAME = 0x03, - VIDEO_CS_VS_FORMAT_UNCOMPRESSED = 0x04, - VIDEO_CS_VS_FRAME_UNCOMPRESSED = 0x05, - VIDEO_CS_VS_FORMAT_MJPEG = 0x06, - VIDEO_CS_VS_FRAME_MJPEG = 0x07, - VIDEO_CS_VS_FORMAT_MPEG2TS = 0x0A, - VIDEO_CS_VS_FORMAT_DV = 0x0C, - VIDEO_CS_VS_COLORFORMAT = 0x0D, - VIDEO_CS_VS_FORMAT_FRAME_BASED = 0x10, - VIDEO_CS_VS_FRAME_FRAME_BASED = 0x11, - VIDEO_CS_VS_FORMAT_STREAM_BASED = 0x12, - VIDEO_CS_VS_FORMAT_H264 = 0x13, - VIDEO_CS_VS_FRAME_H264 = 0x14, - VIDEO_CS_VS_FORMAT_H264_SIMULCAST = 0x15, - VIDEO_CS_VS_FORMAT_VP8 = 0x16, - VIDEO_CS_VS_FRAME_VP8 = 0x17, - VIDEO_CS_VS_FORMAT_VP8_SIMULCAST = 0x18, + VIDEO_CS_ITF_VS_UNDEFINED = 0x00, + VIDEO_CS_ITF_VS_INPUT_HEADER = 0x01, + VIDEO_CS_ITF_VS_OUTPUT_HEADER = 0x02, + VIDEO_CS_ITF_VS_STILL_IMAGE_FRAME = 0x03, + VIDEO_CS_ITF_VS_FORMAT_UNCOMPRESSED = 0x04, + VIDEO_CS_ITF_VS_FRAME_UNCOMPRESSED = 0x05, + VIDEO_CS_ITF_VS_FORMAT_MJPEG = 0x06, + VIDEO_CS_ITF_VS_FRAME_MJPEG = 0x07, + VIDEO_CS_ITF_VS_FORMAT_MPEG2TS = 0x0A, + VIDEO_CS_ITF_VS_FORMAT_DV = 0x0C, + VIDEO_CS_ITF_VS_COLORFORMAT = 0x0D, + VIDEO_CS_ITF_VS_FORMAT_FRAME_BASED = 0x10, + VIDEO_CS_ITF_VS_FRAME_FRAME_BASED = 0x11, + VIDEO_CS_ITF_VS_FORMAT_STREAM_BASED = 0x12, + VIDEO_CS_ITF_VS_FORMAT_H264 = 0x13, + VIDEO_CS_ITF_VS_FRAME_H264 = 0x14, + VIDEO_CS_ITF_VS_FORMAT_H264_SIMULCAST = 0x15, + VIDEO_CS_ITF_VS_FORMAT_VP8 = 0x16, + VIDEO_CS_ITF_VS_FRAME_VP8 = 0x17, + VIDEO_CS_ITF_VS_FORMAT_VP8_SIMULCAST = 0x18, } video_cs_vs_interface_subtype_t; /* A.7. Class-Specific Endpoint Descriptor Subtypes */ @@ -398,18 +398,18 @@ TU_VERIFY_STATIC( sizeof(video_probe_and_commit_control_t) == 48, "size is not c /* 3.7.2 */ #define TUD_VIDEO_DESC_CS_VC(_bcdUVC, _totallen, _clkfreq, ...) \ - TUD_VIDEO_DESC_CS_VC_LEN + (TU_ARGS_NUM(__VA_ARGS__)), TUSB_DESC_CS_INTERFACE, VIDEO_CS_VC_HEADER, \ + TUD_VIDEO_DESC_CS_VC_LEN + (TU_ARGS_NUM(__VA_ARGS__)), TUSB_DESC_CS_INTERFACE, VIDEO_CS_ITF_VC_HEADER, \ U16_TO_U8S_LE(_bcdUVC), U16_TO_U8S_LE((_totallen) + TUD_VIDEO_DESC_CS_VC_LEN + (TU_ARGS_NUM(__VA_ARGS__))), \ U32_TO_U8S_LE(_clkfreq), TU_ARGS_NUM(__VA_ARGS__), __VA_ARGS__ /* 3.7.2.1 */ #define TUD_VIDEO_DESC_INPUT_TERM(_tid, _tt, _at, _stridx) \ - TUD_VIDEO_DESC_INPUT_TERM_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VC_INPUT_TERMINAL, \ + TUD_VIDEO_DESC_INPUT_TERM_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_ITF_VC_INPUT_TERMINAL, \ _tid, U16_TO_U8S_LE(_tt), _at, _stridx /* 3.7.2.2 */ #define TUD_VIDEO_DESC_OUTPUT_TERM(_tid, _tt, _at, _srcid, _stridx) \ - TUD_VIDEO_DESC_OUTPUT_TERM_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VC_OUTPUT_TERMINAL, \ + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_ITF_VC_OUTPUT_TERMINAL, \ _tid, U16_TO_U8S_LE(_tt), _at, _srcid, _stridx /* 3.9.1 */ @@ -420,14 +420,14 @@ TU_VERIFY_STATIC( sizeof(video_probe_and_commit_control_t) == 48, "size is not c /* 3.9.2.1 */ #define TUD_VIDEO_DESC_CS_VS_INPUT(_numfmt, _totallen, _ep, _inf, _termlnk, _sticaptmeth, _trgspt, _trgusg, ...) \ TUD_VIDEO_DESC_CS_VS_IN_LEN + (_numfmt) * (TU_ARGS_NUM(__VA_ARGS__)), TUSB_DESC_CS_INTERFACE, \ - VIDEO_CS_VS_INPUT_HEADER, _numfmt, \ + VIDEO_CS_ITF_VS_INPUT_HEADER, _numfmt, \ U16_TO_U8S_LE((_totallen) + TUD_VIDEO_DESC_CS_VS_IN_LEN + (_numfmt) * (TU_ARGS_NUM(__VA_ARGS__))), \ _ep, _inf, _termlnk, _sticaptmeth, _trgspt, _trgusg, (TU_ARGS_NUM(__VA_ARGS__)), __VA_ARGS__ /* 3.9.2.2 */ #define TUD_VIDEO_DESC_CS_VS_OUTPUT(_numfmt, _totallen, _ep, _inf, _termlnk, ...) \ TUD_VIDEO_DESC_CS_VS_OUT_LEN + (_numfmt) * (TU_ARGS_NUM(__VA_ARGS__)), TUSB_DESC_CS_INTERFACE, \ - VIDEO_CS_VS_OUTPUT_HEADER, _numfmt, \ + VIDEO_CS_ITF_VS_OUTPUT_HEADER, _numfmt, \ U16_TO_U8S_LE((_totallen) + TUD_VIDEO_DESC_CS_VS_OUT_LEN + (_numfmt) * (TU_ARGS_NUM(__VA_ARGS__))), \ _ep, _inf, _termlnk, (TU_ARGS_NUM(__VA_ARGS__)), __VA_ARGS__ @@ -436,13 +436,13 @@ TU_VERIFY_STATIC( sizeof(video_probe_and_commit_control_t) == 48, "size is not c #define TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR(_fmtidx, _numfrmdesc, \ _guid, _bitsperpix, _frmidx, _asrx, _asry, _interlace, _cp) \ - TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_FORMAT_UNCOMPRESSED, \ + TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_ITF_VS_FORMAT_UNCOMPRESSED, \ _fmtidx, _numfrmdesc, TUD_VIDEO_GUID(_guid), \ _bitsperpix, _frmidx, _asrx, _asry, _interlace, _cp /* Uncompressed 3.1.2 Table 3-3 */ #define TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT(_frmidx, _cap, _width, _height, _minbr, _maxbr, _maxfrmbufsz, _frminterval, _minfrminterval, _maxfrminterval, _frmintervalstep) \ - TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_FRAME_UNCOMPRESSED, \ + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_ITF_VS_FRAME_UNCOMPRESSED, \ _frmidx, _cap, U16_TO_U8S_LE(_width), U16_TO_U8S_LE(_height), U32_TO_U8S_LE(_minbr), U32_TO_U8S_LE(_maxbr), \ U32_TO_U8S_LE(_maxfrmbufsz), U32_TO_U8S_LE(_frminterval), 0, \ U32_TO_U8S_LE(_minfrminterval), U32_TO_U8S_LE(_maxfrminterval), U32_TO_U8S_LE(_frmintervalstep) @@ -450,14 +450,14 @@ TU_VERIFY_STATIC( sizeof(video_probe_and_commit_control_t) == 48, "size is not c /* Uncompressed 3.1.2 Table 3-4 */ #define TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_DISC(_frmidx, _cap, _width, _height, _minbr, _maxbr, _maxfrmbufsz, _frminterval, ...) \ TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_DISC_LEN + (TU_ARGS_NUM(__VA_ARGS__)) * 4, \ - TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_FRAME_UNCOMPRESSED, \ + TUSB_DESC_CS_INTERFACE, VIDEO_CS_ITF_VS_FRAME_UNCOMPRESSED, \ _frmidx, _cap, U16_TO_U8S_LE(_width), U16_TO_U8S_LE(_height), U32_TO_U8S_LE(_minbr), U32_TO_U8S_LE(_maxbr), \ U32_TO_U8S_LE(_maxfrmbufsz), U32_TO_U8S_LE(_frminterval), (TU_ARGS_NUM(__VA_ARGS__)), __VA_ARGS__ /* 3.9.2.6 */ #define TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING(_color, _trns, _mat) \ TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN, \ - TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_COLORFORMAT, \ + TUSB_DESC_CS_INTERFACE, VIDEO_CS_ITF_VS_COLORFORMAT, \ _color, _trns, _mat /* 3.10.1.1 */ diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index da190da47..d34fe7b92 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -258,8 +258,8 @@ static void const* _find_desc_entity(void const *desc, uint_fast8_t entityid) void const *end = beg + vc->std.bLength + vc->ctl.wTotalLength; for (void const *cur = beg; cur < end; cur = _find_desc(cur, end, TUSB_DESC_CS_INTERFACE)) { tusb_desc_cs_video_entity_itf_t const *itf = (tusb_desc_cs_video_entity_itf_t const *)cur; - if ((VIDEO_CS_VC_INPUT_TERMINAL <= itf->bDescriptorSubtype - && itf->bDescriptorSubtype < VIDEO_CS_VC_MAX) + if ((VIDEO_CS_ITF_VC_INPUT_TERMINAL <= itf->bDescriptorSubtype + && itf->bDescriptorSubtype < VIDEO_CS_ITF_VC_MAX) && itf->bEntityId == entityid) { return itf; } @@ -279,14 +279,14 @@ static inline void const* _end_of_streaming_descriptor(void const *desc) static inline tusb_desc_cs_video_fmt_uncompressed_t const *_find_desc_format(void const *beg, void const *end, uint_fast8_t fmtnum) { return (tusb_desc_cs_video_fmt_uncompressed_t const*) - _find_desc_3(beg, end, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_FORMAT_UNCOMPRESSED, fmtnum); + _find_desc_3(beg, end, TUSB_DESC_CS_INTERFACE, VIDEO_CS_ITF_VS_FORMAT_UNCOMPRESSED, fmtnum); } /** Find the first frame descriptor with the specified format number. */ static inline tusb_desc_cs_video_frm_uncompressed_t const *_find_desc_frame(void const *beg, void const *end, uint_fast8_t frmnum) { return (tusb_desc_cs_video_frm_uncompressed_t const*) - _find_desc_3(beg, end, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_FRAME_UNCOMPRESSED, frmnum); + _find_desc_3(beg, end, TUSB_DESC_CS_INTERFACE, VIDEO_CS_ITF_VS_FRAME_UNCOMPRESSED, frmnum); } /** Set uniquely determined values to variables that have not been set -- cgit v1.3.1 From 67f1603833261d3d210e55c1e8a872b8d9f98a42 Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Tue, 12 Oct 2021 23:35:19 +0900 Subject: Fix a typo --- src/class/video/video_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index d34fe7b92..91d3b2b72 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -909,7 +909,7 @@ bool tud_video_n_frame_xfer(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, void *bu { TU_ASSERT(ctl_idx < CFG_TUD_VIDEO); TU_ASSERT(stm_idx < CFG_TUD_VIDEO_STREAMING); - if (!buffer || !buffer) return false; + if (!buffer || !bufsize) return false; videod_streaming_interface_t *stm = _get_instance_streaming(ctl_idx, stm_idx); if (!stm || !stm->desc.ep[0] || stm->buffer) return false; -- cgit v1.3.1 From 557fa3900a78f1c378c5653d590253ea87450013 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 12 Oct 2021 21:57:34 +0700 Subject: update docs --- CONTRIBUTORS.rst | 17 +++++++---------- README.rst | 3 ++- 2 files changed, 9 insertions(+), 11 deletions(-) diff --git a/CONTRIBUTORS.rst b/CONTRIBUTORS.rst index 040f40166..33ebef959 100644 --- a/CONTRIBUTORS.rst +++ b/CONTRIBUTORS.rst @@ -76,7 +76,8 @@ Notable contributors ----------------------------------------------- - Add new DCD port for NXP Kinetis KL25 -- Add new DCD port for Renesas RX63n with GR-CITRUS board +- Add new DCD port for Renesas RX family (RX600, RX700 ..) with GR-CITRUS, RX65n target board +- Add new class driver for USB Video Class (UVC 1.5) `Nathan Conrad `__ @@ -94,8 +95,7 @@ Notable contributors - Add new DCD port for Nuvoton NUC 120, 121, 125, 126, 505 - Add new class driver for USBNET RNDIS, CDC-ECM -- Add *net\_lwip\_webserver* example for demonstration of usbnet with - lwip +- Add *net\_lwip\_webserver* example for demonstration of usbnet with lwip - Board support for NuTiny NUC120, NUC121s, NUC125s, NUC126V, NUC505 - Improve multiple cdc interfaces API & add cdc\_dual\_ports example @@ -118,10 +118,8 @@ Notable contributors ------------------------------------------------ - Add new class driver for USB Audio Class 2.0 (UAC2) -- Rework tu\_fifo with unmasked pointer, add DMA support, and constant - address support -- Add new DCD/USBD edpt\_xfer\_fifo() API for optimizing endpoint - transfer +- Rework tu\_fifo with unmasked pointer, add DMA support, and constant address support +- Add new DCD/USBD edpt\_xfer\_fifo() API for optimizing endpoint transfer - Add and greatly improve Isochronous transfer - Add new audio examples: audio\_test and audio\_4\_channel\_mic @@ -130,8 +128,7 @@ Notable contributors ------------------------------------------------ - Add new DCD port for SAMD21 and SAMD51 -- Add new class driver for Musical Instrument Digital Interface - (MIDI) +- Add new class driver for Musical Instrument Digital Interface (MIDI) - Improve USBD control transfer, MSC, CDC class driver - Board support for Metro M0 & M4 express - Write the excellent porting.md documentation @@ -178,7 +175,7 @@ Notable contributors `Zixun Li `__ ------------------------------------------------ +------------------------------------------- - Add new DCD port for Microchip SAMx7x - Add IAR compiler support diff --git a/README.rst b/README.rst index 52738da32..055c294f6 100644 --- a/README.rst +++ b/README.rst @@ -66,7 +66,8 @@ Supports multiple device configurations by dynamically changing USB descriptors, - Mass Storage Class (MSC): with multiple LUNs - Musical Instrument Digital Interface (MIDI) - Network with RNDIS, CDC-ECM (work in progress) -- USB Test and Measurement Class (USBTMC) +- Test and Measurement Class (USBTMC) +- Video class 1.5 (UVC): work in progress - Vendor-specific class support with generic In & Out endpoints. Can be used with MS OS 2.0 compatible descriptor to load winUSB driver without INF file. - `WebUSB `__ with vendor-specific class -- cgit v1.3.1 From b26cc2cc4694d883cc060c03c57d201753b4c72a Mon Sep 17 00:00:00 2001 From: Ha Thach Date: Wed, 13 Oct 2021 00:57:45 +0700 Subject: Add linkermap for size analysis (#1136) * add NO_LTO option to make * add linkermap submodule and linkermap target * add linkermap to ci build * linkermap doesn't work with esp32sx map file yet * add note for linkermap target --- .github/workflows/build.yml | 14 ++++++++++++++ .github/workflows/build_esp.yml | 14 ++++++++++++++ .github/workflows/build_msp430.yml | 14 ++++++++++++++ .github/workflows/build_renesas.yml | 14 ++++++++++++++ .github/workflows/build_riscv.yml | 14 ++++++++++++++ docs/reference/getting_started.rst | 15 ++++++++++++--- examples/rules.mk | 31 +++++++++++++++++++++---------- hw/bsp/esp32s2/family.mk | 5 +---- 8 files changed, 104 insertions(+), 17 deletions(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 1ef0bf5ea..b16cf3f87 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -66,6 +66,12 @@ jobs: - name: Checkout common submodules in lib run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip lib/sct_neopixel + - name: Checkout hathach/linkermap + uses: actions/checkout@v2 + with: + repository: hathach/linkermap + path: linkermap + - name: Checkout pico-sdk if: matrix.family == 'rp2040' run: | @@ -95,6 +101,14 @@ jobs: - name: Build run: python3 tools/build_family.py ${{ matrix.family }} + - name: Linker Map + run: | + pip install linkermap/ + for ex in `ls -d examples/device/*/`; do \ + find ${ex} -name *.map -print -quit | \ + xargs -I % sh -c 'echo "::group::%"; linkermap -v %; echo "::endgroup::"'; \ + done + # --------------------------------------- # Build all no-family (opharned) boards # --------------------------------------- diff --git a/.github/workflows/build_esp.yml b/.github/workflows/build_esp.yml index 93d582361..15071b178 100644 --- a/.github/workflows/build_esp.yml +++ b/.github/workflows/build_esp.yml @@ -30,5 +30,19 @@ jobs: - name: Checkout TinyUSB uses: actions/checkout@v2 + - name: Checkout hathach/linkermap + uses: actions/checkout@v2 + with: + repository: hathach/linkermap + path: linkermap + - name: Build run: docker run --rm -v $PWD:/project -w /project espressif/idf:latest python3 tools/build_esp32sx.py ${{ matrix.board }} + + - name: Linker Map + run: | + pip install linkermap/ + for ex in `ls -d examples/device/*/`; do \ + find ${ex} -maxdepth 3 -name *.map -print -quit | \ + xargs -I % sh -c 'echo "::group::%"; linkermap -v %; echo "::endgroup::"'; \ + done diff --git a/.github/workflows/build_msp430.yml b/.github/workflows/build_msp430.yml index ff2ce72c9..98dc36cd9 100644 --- a/.github/workflows/build_msp430.yml +++ b/.github/workflows/build_msp430.yml @@ -26,6 +26,12 @@ jobs: - name: Checkout common submodules in lib run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip + - name: Checkout hathach/linkermap + uses: actions/checkout@v2 + with: + repository: hathach/linkermap + path: linkermap + - name: Set Toolchain URL run: echo >> $GITHUB_ENV TOOLCHAIN_URL=http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPGCC/9_2_0_0/export/msp430-gcc-9.2.0.50_linux64.tar.bz2 @@ -48,3 +54,11 @@ jobs: - name: Build run: python3 tools/build_family.py ${{ matrix.family }} + + - name: Linker Map + run: | + pip install linkermap/ + for ex in `ls -d examples/device/*/`; do \ + find ${ex} -name *.map -print -quit | \ + xargs -I % sh -c 'echo "::group::%"; linkermap -v %; echo "::endgroup::"'; \ + done diff --git a/.github/workflows/build_renesas.yml b/.github/workflows/build_renesas.yml index ee9ba8289..6eb042d72 100644 --- a/.github/workflows/build_renesas.yml +++ b/.github/workflows/build_renesas.yml @@ -26,6 +26,12 @@ jobs: - name: Checkout common submodules in lib run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip + - name: Checkout hathach/linkermap + uses: actions/checkout@v2 + with: + repository: hathach/linkermap + path: linkermap + - name: Set Toolchain URL run: echo >> $GITHUB_ENV TOOLCHAIN_URL=http://gcc-renesas.com/downloads/get.php?f=rx/8.3.0.202004-gnurx/gcc-8.3.0.202004-GNURX-ELF.run @@ -49,3 +55,11 @@ jobs: - name: Build run: python3 tools/build_family.py ${{ matrix.family }} + + - name: Linker Map + run: | + pip install linkermap/ + for ex in `ls -d examples/device/*/`; do \ + find ${ex} -name *.map -print -quit | \ + xargs -I % sh -c 'echo "::group::%"; linkermap -v %; echo "::endgroup::"'; \ + done diff --git a/.github/workflows/build_riscv.yml b/.github/workflows/build_riscv.yml index 78510751c..0c7b2d154 100644 --- a/.github/workflows/build_riscv.yml +++ b/.github/workflows/build_riscv.yml @@ -27,6 +27,12 @@ jobs: - name: Checkout common submodules in lib run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip + - name: Checkout hathach/linkermap + uses: actions/checkout@v2 + with: + repository: hathach/linkermap + path: linkermap + - name: Set Toolchain URL run: echo >> $GITHUB_ENV TOOLCHAIN_URL=https://github.com/xpack-dev-tools/riscv-none-embed-gcc-xpack/releases/download/v10.1.0-1.1/xpack-riscv-none-embed-gcc-10.1.0-1.1-linux-x64.tar.gz @@ -49,3 +55,11 @@ jobs: - name: Build run: python3 tools/build_family.py ${{ matrix.family }} + + - name: Linker Map + run: | + pip install linkermap/ + for ex in `ls -d examples/device/*/`; do \ + find ${ex} -name *.map -print -quit | \ + xargs -I % sh -c 'echo "::group::%"; linkermap -v %; echo "::endgroup::"'; \ + done diff --git a/docs/reference/getting_started.rst b/docs/reference/getting_started.rst index be2e1b5ea..044792993 100644 --- a/docs/reference/getting_started.rst +++ b/docs/reference/getting_started.rst @@ -89,6 +89,15 @@ A MCU can support multiple operational speed. By default, the example build syst $ make BOARD=stm32f746disco SPEED=full all +Size Analysis +~~~~~~~~~~~~~ + +First install `linkermap tool `_ then ``linkermap`` target can be used to analyze code size. You may want to compile with ``NO_LTO=1`` since -flto merges code across .o files and make it difficult to analyze. + +.. code-block:: + + $ make BOARD=feather_nrf52840_express NO_LTO=1 all linkermap + Debug ^^^^^ @@ -153,7 +162,7 @@ Some board use uf2 bootloader for drag & drop in to mass storage device, uf2 can $ make BOARD=feather_nrf52840_express all uf2 IAR Support ------------ +^^^^^^^^^^^ IAR Project Connection files are provided to import TinyUSB stack into your project. @@ -171,12 +180,12 @@ IAR Project Connection files are provided to import TinyUSB stack into your proj for example `C:\\tinyusb` Import stack only -^^^^^^^^^^^^^^^^^ +~~~~~~~~~~~~~~~~~ 1. Open `Project -> Add project Connection ...`, click `OK`, choose `tinyusb\\tools\\iar_template.ipcf`. Run examples -^^^^^^^^^^^^ +~~~~~~~~~~~~ 1. (Python3 is needed) Run `iar_gen.py` to generate .ipcf files of examples: diff --git a/examples/rules.mk b/examples/rules.mk index 7e494b3d8..92fa4e14d 100644 --- a/examples/rules.mk +++ b/examples/rules.mk @@ -5,12 +5,11 @@ # Set all as default goal .DEFAULT_GOAL := all -# ESP32-SX and RP2040 has its own CMake build system -ifneq ($(FAMILY),esp32s2) -ifneq ($(FAMILY),esp32s3) -ifneq ($(FAMILY),rp2040) +# ESP32-Sx and RP2040 has its own CMake build system +ifeq (,$(findstring $(FAMILY),esp32s2 esp32s3 rp2040)) + # --------------------------------------- -# GNU Make build system +# Compiler Flags # --------------------------------------- # libc @@ -44,6 +43,12 @@ INC += $(TOP)/src CFLAGS += $(addprefix -I,$(INC)) +# LTO makes it difficult to analyze map file for optimizing size purpose +# We will run this option in ci +ifeq ($(NO_LTO),1) +CFLAGS := $(filter-out -flto,$(CFLAGS)) +endif + LDFLAGS += $(CFLAGS) -Wl,-T,$(TOP)/$(LD_FILE) -Wl,-Map=$@.map -Wl,-cref -Wl,-gc-sections ifneq ($(SKIP_NANOLIB), 1) LDFLAGS += -specs=nosys.specs -specs=nano.specs @@ -67,6 +72,10 @@ $(info LDFLAGS $(LDFLAGS)) $(info ) $(info ASFLAGS $(ASFLAGS)) $(info ) endif +# --------------------------------------- +# Rules +# --------------------------------------- + all: $(BUILD)/$(PROJECT).bin $(BUILD)/$(PROJECT).hex size uf2: $(BUILD)/$(PROJECT).uf2 @@ -126,11 +135,17 @@ $(BUILD)/obj/%_asm.o: %.S @echo AS $(notdir $@) @$(CC) -x assembler-with-cpp $(ASFLAGS) -c -o $@ $< +endif # GNU Make + size: $(BUILD)/$(PROJECT).elf -@echo '' @$(SIZE) $< -@echo '' +# linkermap must be install previously at https://github.com/hathach/linkermap +linkermap: $(BUILD)/$(PROJECT).elf + @linkermap -v $<.map + .PHONY: clean clean: ifeq ($(CMDEXE),1) @@ -139,10 +154,6 @@ else $(RM) -rf $(BUILD) endif -endif -endif -endif # GNU Make - # --------------------------------------- # Flash Targets # --------------------------------------- @@ -204,4 +215,4 @@ copy-artifact: $(BIN) # Print out the value of a make variable. # https://stackoverflow.com/questions/16467718/how-to-print-out-a-variable-in-makefile print-%: - @echo $* = $($*) + @echo $* = $($*) \ No newline at end of file diff --git a/hw/bsp/esp32s2/family.mk b/hw/bsp/esp32s2/family.mk index fb9b21641..4b9000a6a 100644 --- a/hw/bsp/esp32s2/family.mk +++ b/hw/bsp/esp32s2/family.mk @@ -7,14 +7,11 @@ all: build: all -clean: - idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) clean - fullclean: if test -f sdkconfig; then $(RM) -f sdkconfig ; fi if test -d $(BUILD); then $(RM) -rf $(BUILD) ; fi -flash bootloader-flash app-flash erase monitor dfu-flash dfu: +clean flash bootloader-flash app-flash erase monitor dfu-flash dfu size size-components size-files: idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) $@ uf2: $(BUILD)/$(PROJECT).uf2 -- cgit v1.3.1 From 4ab14867daf1d9df414f1175cbaac70c0d799257 Mon Sep 17 00:00:00 2001 From: Scott Shawcroft Date: Tue, 12 Oct 2021 16:47:53 -0700 Subject: Trying to get USB init --- hw/bsp/raspberrypi4/family.c | 27 +++++++- hw/bsp/raspberrypi4/family.mk | 1 + hw/mcu/broadcom | 2 +- src/portable/broadcom/synopsys/dcd_synopsys.c | 88 ++++++++++++++------------- 4 files changed, 71 insertions(+), 47 deletions(-) diff --git a/hw/bsp/raspberrypi4/family.c b/hw/bsp/raspberrypi4/family.c index fe7e429d6..ffeb05f9f 100644 --- a/hw/bsp/raspberrypi4/family.c +++ b/hw/bsp/raspberrypi4/family.c @@ -27,14 +27,17 @@ #include "bsp/board.h" #include "board.h" +#include "broadcom/interrupts.h" #include "broadcom/io.h" #include "broadcom/mmu.h" #include "broadcom/vcmailbox.h" +uint32_t SystemCoreClock = 700 * 1000 * 1000; + //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ -void OTG_FS_IRQHandler(void) +void USB_IRQHandler(void) { tud_int_handler(0); } @@ -54,6 +57,9 @@ void print(const char* str) { void board_init(void) { gpio_initOutputPinWithPullNone(18); + gpio_initOutputPinWithPullNone(19); + gpio_initOutputPinWithPullNone(20); + gpio_initOutputPinWithPullNone(21); gpio_setPinOutputBool(18, true); gpio_initOutputPinWithPullNone(42); setup_mmu_flat_map(); @@ -72,11 +78,17 @@ void board_init(void) } gpio_setPinOutputBool(42, true); gpio_setPinOutputBool(18, true); + gpio_setPinOutputBool(19, true); + gpio_setPinOutputBool(20, true); + gpio_setPinOutputBool(21, true); for (size_t j = 0; j < 1000000; j++) { __asm__("nop"); } gpio_setPinOutputBool(42, false); gpio_setPinOutputBool(18, false); + gpio_setPinOutputBool(19, false); + gpio_setPinOutputBool(20, false); + gpio_setPinOutputBool(21, false); } // uart_writeText("hello from io\n"); // gpio_setPinOutputBool(24, true); @@ -98,11 +110,18 @@ void board_init(void) // } // while (1) uart_update(); + printf("hello %d\r\n", 21); + // Turn on USB peripheral. print("Turning on USB power\r\n"); vcmailbox_set_power_state(VCMAILBOX_DEVICE_USB_HCD, true); print("USB power on\r\n"); + + BP_SetPriority(USB_IRQn, 0x00); + BP_ClearPendingIRQ(USB_IRQn); + BP_EnableIRQ(USB_IRQn); + BP_EnableIRQs(); } void board_led_write(bool state) @@ -125,10 +144,12 @@ int board_uart_write(void const * buf, int len) { for (int i = 0; i < len; i++) { const char* cbuf = buf; + while (!UART1->STAT_b.TX_READY) {} if (cbuf[i] == '\n') { - uart_writeByteBlockingActual('\r'); + UART1->IO = '\r'; + while (!UART1->STAT_b.TX_READY) {} } - uart_writeByteBlockingActual(cbuf[i]); + UART1->IO = cbuf[i]; } return len; } diff --git a/hw/bsp/raspberrypi4/family.mk b/hw/bsp/raspberrypi4/family.mk index b36a83b48..0424b2154 100644 --- a/hw/bsp/raspberrypi4/family.mk +++ b/hw/bsp/raspberrypi4/family.mk @@ -18,6 +18,7 @@ CFLAGS += \ SRC_C += \ src/portable/broadcom/synopsys/dcd_synopsys.c \ + $(MCU_DIR)/broadcom/gen/interrupt_handlers.c \ $(MCU_DIR)/broadcom/interrupts.c \ $(MCU_DIR)/broadcom/io.c \ $(MCU_DIR)/broadcom/mmu.c \ diff --git a/hw/mcu/broadcom b/hw/mcu/broadcom index c24e8f689..e5343acda 160000 --- a/hw/mcu/broadcom +++ b/hw/mcu/broadcom @@ -1 +1 @@ -Subproject commit c24e8f6898d7cf8e2884eb70dbabd97480526450 +Subproject commit e5343acdad77b8cf4a8d09b732a11ecef17d148a diff --git a/src/portable/broadcom/synopsys/dcd_synopsys.c b/src/portable/broadcom/synopsys/dcd_synopsys.c index aecae503c..ff4ab9fb6 100644 --- a/src/portable/broadcom/synopsys/dcd_synopsys.c +++ b/src/portable/broadcom/synopsys/dcd_synopsys.c @@ -434,60 +434,63 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c /*------------------------------------------------------------------*/ /* Controller API *------------------------------------------------------------------*/ + +static void reset_core(USB_OTG_GlobalTypeDef * usb_otg) { + while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0) {} + + TU_LOG(2, " resetting\r\n"); + usb_otg->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; + TU_LOG(2, " waiting\r\n"); + while ((usb_otg->GRSTCTL & (USB_OTG_GRSTCTL_AHBIDL | USB_OTG_GRSTCTL_CSRST)) != USB_OTG_GRSTCTL_AHBIDL) {} + TU_LOG(2, " reset done\r\n"); +} + void dcd_init (uint8_t rhport) { + printf("test done\r\n"); // Programming model begins in the last section of the chapter on the USB // peripheral in each Reference Manual. - TU_LOG(2, " dcd_init"); - - USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport); - - // No HNP/SRP (no OTG support), program timeout later. - if ( rhport == 1 ) - { - // On selected MCUs HS port1 can be used with external PHY via ULPI interface -#if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED - // deactivate internal PHY - usb_otg->GCCFG &= ~USB_OTG_GCCFG_PWRDWN; + TU_LOG(2, " dcd_init\r\n"); - // Init The UTMI Interface - usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL); + TU_LOG2("Test 123\r\n"); - // Select default internal VBUS Indicator and Drive for ULPI - usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); -#else - usb_otg->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; -#endif + USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport); -#if defined(USB_HS_PHYC) - // Highspeed with embedded UTMI PHYC - // Select UTMI Interface - usb_otg->GUSBCFG &= ~USB_OTG_GUSBCFG_ULPI_UTMI_SEL; - usb_otg->GCCFG |= USB_OTG_GCCFG_PHYHSEN; + // ReadBackReg(&Core->Usb); + // Core->Usb.UlpiDriveExternalVbus = 0; + // Core->Usb.TsDlinePulseEnable = 0; + // WriteThroughReg(&Core->Usb); - // Enables control of a High Speed USB PHY - USB_HS_PHYCInit(); -#endif - } else - { - // Enable internal PHY - usb_otg->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; - } + // This sequence is modeled after: https://github.com/Chadderz121/csud/blob/e13b9355d043a9cdd384b335060f1bc0416df61e/source/hcd/dwc/designware20.c#L689 + usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIEVBUSD); + reset_core(usb_otg); - // Reset core after selecting PHY - // Wait AHB IDLE, reset then wait until it is cleared - while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U) {} + // Core->Usb.ModeSelect = UTMI; + // LOG_DEBUG("HCD: Interface: UTMI+.\n"); + // Core->Usb.PhyInterface = false; - TU_LOG(2, " resetting"); - usb_otg->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; - TU_LOG(2, " waiting"); - while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST) {} + // HcdReset(); + TU_LOG2("init phy\r\n"); + usb_otg->GUSBCFG |= (1 << 4); // bit four sets UTMI+ mode + usb_otg->GUSBCFG &= ~(1 << 3); // bit three disables phy interface + reset_core(usb_otg); - TU_LOG(2, " reset done"); + // LOG_DEBUG("HCD: ULPI FSLS configuration: disabled.\n"); + // Core->Usb.UlpiFsls = false; + // Core->Usb.ulpi_clk_sus_m = false; + usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_ULPICSM); - // Restart PHY clock - *((volatile uint32_t *)(RHPORT_REGS_BASE + USB_OTG_PCGCCTL_BASE)) = 0; + // LOG_DEBUG("HCD: DMA configuration: enabled.\n"); + // Core->Ahb.DmaEnable = true; + // Core->Ahb.DmaRemainderMode = Incremental; + usb_otg->GAHBCFG &= ~(1 << 23); // Remainder mode + usb_otg->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN; + + // LOG_DEBUG("HCD: HNP/SRP configuration: HNP, SRP.\n"); + // Core->Usb.HnpCapable = true; + // Core->Usb.SrpCapable = true; + usb_otg->GUSBCFG |= USB_OTG_GUSBCFG_SRPCAP | USB_OTG_GUSBCFG_HNPCAP; // Clear all interrupts usb_otg->GINTSTS |= usb_otg->GINTSTS; @@ -509,8 +512,7 @@ void dcd_init (uint8_t rhport) set_speed(rhport, TUSB_SPEED_FULL); #endif - // Enable internal USB transceiver, unless using HS core (port 1) with external PHY. - if (!(rhport == 1 && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED))) usb_otg->GCCFG |= USB_OTG_GCCFG_PWRDWN; + usb_otg->GCCFG |= USB_OTG_GCCFG_PWRDWN; usb_otg->GINTMSK |= USB_OTG_GINTMSK_USBRST | USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_WUIM | -- cgit v1.3.1 From 5cfe2930012d1dbec85e0923e0eda2d9aec867e6 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 13 Oct 2021 17:31:57 +0700 Subject: update changelog and increase version for 0.12.0 --- CONTRIBUTORS.rst | 3 +-- docs/info/changelog.rst | 33 ++++++++++++++++++++++++++++++++- docs/reference/getting_started.rst | 2 +- src/tusb_option.h | 2 +- 4 files changed, 35 insertions(+), 5 deletions(-) diff --git a/CONTRIBUTORS.rst b/CONTRIBUTORS.rst index 121d37789..55a291222 100644 --- a/CONTRIBUTORS.rst +++ b/CONTRIBUTORS.rst @@ -177,8 +177,7 @@ Notable contributors - Add new DCD port for Synopsys DesignWare for STM32 L4, F2, F4, F7, H7 etc ... - Add new DCD port for TI MSP430 -- Board support for STM32F407 Discovery, STM32H743 Nucleo, pyboard - v1.1, msp\_exp430f5529lp etc ... +- Board support for STM32F407 Discovery, STM32H743 Nucleo, pyboard v1.1, msp\_exp430f5529lp etc ... `Zixun Li `__ diff --git a/docs/info/changelog.rst b/docs/info/changelog.rst index 4325ff2ca..4cb30799c 100644 --- a/docs/info/changelog.rst +++ b/docs/info/changelog.rst @@ -2,6 +2,37 @@ Changelog ********* +0.12.0 +====== + +- add CFG_TUSB_OS_INC_PATH for os include path + +Device Controller Driver (DCD) +------------------------------ + +- Getting device stack to pass USB Compliance Verification test (chapter9, HID, MSC). Ports are tested: + nRF, SAMD 21/51, rp2040, stm32f4, Renesas RX, iMXRT, ESP32-S2/3, Kinetic KL25/32 +- Added dcd_edpt_close_all() for switching configuration +- [Transdimension] Support dcd_edpt_xfer_fifo() with auto wrap over if fifo buffer is 4K aligned and size is multiple of 4K. +- [Da146xx] Improve vbus, reset, suspend, resume detection, and remote wakeup. + +Device Stack +------------ + +- Add new network driver Network Control Model (CDC-NCM), update net_lwip_webserver to work with NCM (need re-configure example) +- Add new USB Video Class UVC 1.5 driver and video_capture example ((work in progress) +- Fix potential buffer overflow for HID, bluetooth drivers + +Host Controller Driver (HCD) +---------------------------- + +No notable changes + +Host Stack +---------- + +No notable changes + 0.11.0 (2021-08-29) =================== @@ -26,7 +57,7 @@ Synopsys ^^^^^^^^ - Fix Synopsys set address bug which could cause re-enumeration failed -- Fix for dcd_synopsys driver integer overflow in HS mode (issue #968) +- Fix dcd_synopsys driver integer overflow in HS mode (issue #968) nRF5x ^^^^^ diff --git a/docs/reference/getting_started.rst b/docs/reference/getting_started.rst index 044792993..875372c81 100644 --- a/docs/reference/getting_started.rst +++ b/docs/reference/getting_started.rst @@ -122,7 +122,7 @@ Logger By default log message is printed via on-board UART which is slow and take lots of CPU time comparing to USB speed. If your board support on-board/external debugger, it would be more efficient to use it for logging. There are 2 protocols: -* `LOGGER=rtt`: use [Segger RTT protocol](https://www.segger.com/products/debug-probes/j-link/technology/about-real-time-transfer/) +* `LOGGER=rtt`: use `Segger RTT protocol `_ * Cons: requires jlink as the debugger. * Pros: work with most if not all MCUs diff --git a/src/tusb_option.h b/src/tusb_option.h index b2ebfdf66..e49fc0119 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -28,7 +28,7 @@ #define _TUSB_OPTION_H_ #define TUSB_VERSION_MAJOR 0 -#define TUSB_VERSION_MINOR 11 +#define TUSB_VERSION_MINOR 12 #define TUSB_VERSION_REVISION 0 #define TUSB_VERSION_STRING TU_STRING(TUSB_VERSION_MAJOR) "." TU_STRING(TUSB_VERSION_MINOR) "." TU_STRING(TUSB_VERSION_REVISION) -- cgit v1.3.1 From 2a795d5fd0e1a18ae5fa2eeb9d47e8769efe663c Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Thu, 14 Oct 2021 23:15:35 +0900 Subject: Fix GUID of video compression formats --- src/class/video/video.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/class/video/video.h b/src/class/video/video.h index b24eb0bcc..fa2976611 100644 --- a/src/class/video/video.h +++ b/src/class/video/video.h @@ -382,10 +382,10 @@ TU_VERIFY_STATIC( sizeof(video_probe_and_commit_control_t) == 48, "size is not c #define TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN 6 /* 2.2 compression formats */ -#define TUD_VIDEO_GUID_YUY2 0x59,0x55,0x59,0x32,0x00,0x00,0x10,0x00,0x00,0x80,0x71,0x9B,0x38,0x00,0xAA,0x00 -#define TUD_VIDEO_GUID_NV12 0x4E,0x56,0x31,0x32,0x00,0x00,0x10,0x00,0x00,0x80,0x71,0x9B,0x38,0x00,0xAA,0x00 -#define TUD_VIDEO_GUID_M420 0x4D,0x34,0x32,0x30,0x00,0x00,0x10,0x00,0x00,0x80,0x71,0x9B,0x38,0x00,0xAA,0x00 -#define TUD_VIDEO_GUID_I420 0x49,0x34,0x32,0x30,0x00,0x00,0x10,0x00,0x00,0x80,0x71,0x9B,0x38,0x00,0xAA,0x00 +#define TUD_VIDEO_GUID_YUY2 0x59,0x55,0x59,0x32,0x00,0x00,0x10,0x00,0x80,0x00,0x00,0xAA,0x00,0x38,0x9B,0x71 +#define TUD_VIDEO_GUID_NV12 0x4E,0x56,0x31,0x32,0x00,0x00,0x10,0x00,0x80,0x00,0x00,0xAA,0x00,0x38,0x9B,0x71 +#define TUD_VIDEO_GUID_M420 0x4D,0x34,0x32,0x30,0x00,0x00,0x10,0x00,0x80,0x00,0x00,0xAA,0x00,0x38,0x9B,0x71 +#define TUD_VIDEO_GUID_I420 0x49,0x34,0x32,0x30,0x00,0x00,0x10,0x00,0x80,0x00,0x00,0xAA,0x00,0x38,0x9B,0x71 #define TUD_VIDEO_DESC_IAD(_firstitfs, _nitfs, _stridx) \ TUD_VIDEO_DESC_IAD_LEN, TUSB_DESC_INTERFACE_ASSOCIATION, \ -- cgit v1.3.1 From 7667299b483feb4afb783d794ea94a149cc5a5b4 Mon Sep 17 00:00:00 2001 From: graham sanderson Date: Thu, 14 Oct 2021 12:13:39 -0500 Subject: Remove compiler warning --- src/portable/raspberrypi/rp2040/rp2040_usb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c index f9b4d9b17..28c54c52f 100644 --- a/src/portable/raspberrypi/rp2040/rp2040_usb.c +++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c @@ -242,7 +242,7 @@ static void _hw_endpoint_xfer_sync (struct hw_endpoint *ep) // Update hw endpoint struct with info from hardware // after a buff status interrupt - uint32_t buf_ctrl = _hw_endpoint_buffer_control_get_value32(ep); + uint32_t __unused buf_ctrl = _hw_endpoint_buffer_control_get_value32(ep); TU_LOG(3, " Sync BufCtrl: [0] = 0x%04u [1] = 0x%04x\r\n", tu_u32_low16(buf_ctrl), tu_u32_high16(buf_ctrl)); // always sync buffer 0 -- cgit v1.3.1 From 06d955538988c3859bf6c5428a38bd8311069ed9 Mon Sep 17 00:00:00 2001 From: graham sanderson Date: Thu, 14 Oct 2021 15:20:32 -0500 Subject: More warning cleanup - physically suppress warnings in TinyUSB headers using pragmas so they don't break -Werror compilation of external files that include them - fix compiler warnings in rp2040 port - add cmake method to rp2040 port to allow an external project to suppress warnings in TinyUSB itself --- hw/bsp/rp2040/family.cmake | 25 ++++++++++++++++++++++++- src/device/dcd.h | 7 +++++++ src/osal/osal.h | 7 +++++++ src/portable/raspberrypi/rp2040/dcd_rp2040.c | 22 +++++++++++----------- src/portable/raspberrypi/rp2040/rp2040_usb.c | 8 ++++---- 5 files changed, 53 insertions(+), 16 deletions(-) diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake index 06b5e9bd6..1aa180ef8 100644 --- a/hw/bsp/rp2040/family.cmake +++ b/hw/bsp/rp2040/family.cmake @@ -77,7 +77,6 @@ if (NOT TARGET _rp2040_family_inclusion_marker) ${TOP}/src/class/video/video_device.c ) - # Base config for host mode; wrapped by SDK's tinyusb_host add_library(tinyusb_host_base INTERFACE) target_sources(tinyusb_host_base INTERFACE @@ -153,4 +152,28 @@ if (NOT TARGET _rp2040_family_inclusion_marker) enable_language(C CXX ASM) pico_sdk_init() endfunction() + + # This method must be called from the project scope to suppress known warnings in TinyUSB source files + function(suppress_tinyusb_warnings) + set_source_files_properties( + ${PICO_TINYUSB_PATH}/src/tusb.c + PROPERTIES + COMPILE_FLAGS "-Wno-conversion") + set_source_files_properties( + ${PICO_TINYUSB_PATH}/src/common/tusb_fifo.c + PROPERTIES + COMPILE_FLAGS "-Wno-conversion -Wno-cast-qual") + set_source_files_properties( + ${PICO_TINYUSB_PATH}/src/device/usbd.c + PROPERTIES + COMPILE_FLAGS "-Wno-conversion -Wno-cast-qual -Wno-null-dereference") + set_source_files_properties( + ${PICO_TINYUSB_PATH}/src/device/usbd_control.c + PROPERTIES + COMPILE_FLAGS "-Wno-conversion") + set_source_files_properties( + ${PICO_TINYUSB_PATH}/src/class/cdc/cdc_device.c + PROPERTIES + COMPILE_FLAGS "-Wno-conversion") + endfunction() endif() diff --git a/src/device/dcd.h b/src/device/dcd.h index d43a0dd9a..c042cc708 100644 --- a/src/device/dcd.h +++ b/src/device/dcd.h @@ -106,7 +106,14 @@ typedef struct TU_ATTR_ALIGNED(4) void dcd_init (uint8_t rhport); // Interrupt Handler +#if __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wredundant-decls" +#endif void dcd_int_handler(uint8_t rhport); +#if __GNUC__ +#pragma GCC diagnostic pop +#endif // Enable device interrupt void dcd_int_enable (uint8_t rhport); diff --git a/src/osal/osal.h b/src/osal/osal.h index 28bdf479c..c8131d19d 100644 --- a/src/osal/osal.h +++ b/src/osal/osal.h @@ -67,6 +67,10 @@ typedef void (*osal_task_func_t)( void * ); // OSAL Porting API //--------------------------------------------------------------------+ +#if __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wredundant-decls" +#endif //------------- Semaphore -------------// static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef); static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr); @@ -84,6 +88,9 @@ static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef); static inline bool osal_queue_receive(osal_queue_t qhdl, void* data); static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr); static inline bool osal_queue_empty(osal_queue_t qhdl); +#if __GNUC__ +#pragma GCC diagnostic pop +#endif #if 0 // TODO remove subtask related macros later // Sub Task diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c index a710bd557..4bcc9ca54 100644 --- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c @@ -70,7 +70,7 @@ static struct hw_endpoint *hw_endpoint_get_by_addr(uint8_t ep_addr) static void _hw_endpoint_alloc(struct hw_endpoint *ep, uint8_t transfer_type) { // size must be multiple of 64 - uint16_t size = tu_div_ceil(ep->wMaxPacketSize, 64) * 64u; + uint size = tu_div_ceil(ep->wMaxPacketSize, 64) * 64u; // double buffered Bulk endpoint if ( transfer_type == TUSB_XFER_BULK ) @@ -88,7 +88,7 @@ static void _hw_endpoint_alloc(struct hw_endpoint *ep, uint8_t transfer_type) pico_info(" Alloced %d bytes at offset 0x%x (0x%p)\r\n", size, dpram_offset, ep->hw_data_buf); // Fill in endpoint control register with buffer offset - uint32_t const reg = EP_CTRL_ENABLE_BITS | (transfer_type << EP_CTRL_BUFFER_TYPE_LSB) | dpram_offset; + uint32_t const reg = EP_CTRL_ENABLE_BITS | ((uint)transfer_type << EP_CTRL_BUFFER_TYPE_LSB) | dpram_offset; *ep->endpoint_control = reg; } @@ -177,7 +177,7 @@ static void hw_handle_buff_status(void) uint32_t remaining_buffers = usb_hw->buf_status; pico_trace("buf_status = 0x%08x\n", remaining_buffers); uint bit = 1u; - for (uint i = 0; remaining_buffers && i < USB_MAX_ENDPOINTS * 2; i++) + for (uint8_t i = 0; remaining_buffers && i < USB_MAX_ENDPOINTS * 2; i++) { if (remaining_buffers & bit) { @@ -365,19 +365,19 @@ void dcd_init (uint8_t rhport) dcd_connect(rhport); } -void dcd_int_enable(uint8_t rhport) +void dcd_int_enable(__unused uint8_t rhport) { assert(rhport == 0); irq_set_enabled(USBCTRL_IRQ, true); } -void dcd_int_disable(uint8_t rhport) +void dcd_int_disable(__unused uint8_t rhport) { assert(rhport == 0); irq_set_enabled(USBCTRL_IRQ, false); } -void dcd_set_address (uint8_t rhport, uint8_t dev_addr) +void dcd_set_address (__unused uint8_t rhport, __unused uint8_t dev_addr) { assert(rhport == 0); @@ -386,7 +386,7 @@ void dcd_set_address (uint8_t rhport, uint8_t dev_addr) hw_endpoint_xfer(0x80, NULL, 0); } -void dcd_remote_wakeup(uint8_t rhport) +void dcd_remote_wakeup(__unused uint8_t rhport) { pico_info("dcd_remote_wakeup %d\n", rhport); assert(rhport == 0); @@ -394,14 +394,14 @@ void dcd_remote_wakeup(uint8_t rhport) } // disconnect by disabling internal pull-up resistor on D+/D- -void dcd_disconnect(uint8_t rhport) +void dcd_disconnect(__unused uint8_t rhport) { (void) rhport; usb_hw_clear->sie_ctrl = USB_SIE_CTRL_PULLUP_EN_BITS; } // connect by enabling internal pull-up resistor on D+/D- -void dcd_connect(uint8_t rhport) +void dcd_connect(__unused uint8_t rhport) { (void) rhport; usb_hw_set->sie_ctrl = USB_SIE_CTRL_PULLUP_EN_BITS; @@ -423,7 +423,7 @@ void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * re } } -bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) +bool dcd_edpt_open (__unused uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) { assert(rhport == 0); hw_endpoint_init(desc_edpt->bEndpointAddress, desc_edpt->wMaxPacketSize.size, desc_edpt->bmAttributes.xfer); @@ -438,7 +438,7 @@ void dcd_edpt_close_all (uint8_t rhport) reset_non_control_endpoints(); } -bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) +bool dcd_edpt_xfer(__unused uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) { assert(rhport == 0); hw_endpoint_xfer(ep_addr, buffer, total_bytes); diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c index 28c54c52f..c9e2f6b26 100644 --- a/src/portable/raspberrypi/rp2040/rp2040_usb.c +++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c @@ -38,7 +38,7 @@ const char *ep_dir_string[] = { "in", }; -static inline void _hw_endpoint_lock_update(struct hw_endpoint *ep, int delta) { +static inline void _hw_endpoint_lock_update(__unused struct hw_endpoint * ep, __unused int delta) { // todo add critsec as necessary to prevent issues between worker and IRQ... // note that this is perhaps as simple as disabling IRQs because it would make // sense to have worker and IRQ on same core, however I think using critsec is about equivalent. @@ -107,7 +107,7 @@ void _hw_endpoint_buffer_control_update32(struct hw_endpoint *ep, uint32_t and_m static uint32_t prepare_ep_buffer(struct hw_endpoint *ep, uint8_t buf_id) { uint16_t const buflen = tu_min16(ep->remaining_len, ep->wMaxPacketSize); - ep->remaining_len -= buflen; + ep->remaining_len = (uint16_t)(ep->remaining_len - buflen); uint32_t buf_ctrl = buflen | USB_BUF_CTRL_AVAIL; @@ -214,7 +214,7 @@ static uint16_t sync_ep_buffer(struct hw_endpoint *ep, uint8_t buf_id) // sent some data can increase the length we have sent assert(!(buf_ctrl & USB_BUF_CTRL_FULL)); - ep->xferred_len += xferred_bytes; + ep->xferred_len = (uint16_t)(ep->xferred_len + xferred_bytes); }else { // If we have received some data, so can increase the length @@ -222,7 +222,7 @@ static uint16_t sync_ep_buffer(struct hw_endpoint *ep, uint8_t buf_id) assert(buf_ctrl & USB_BUF_CTRL_FULL); memcpy(ep->user_buf, ep->hw_data_buf + buf_id*64, xferred_bytes); - ep->xferred_len += xferred_bytes; + ep->xferred_len = (uint16_t)(ep->xferred_len + xferred_bytes); ep->user_buf += xferred_bytes; } -- cgit v1.3.1 From 7596cb30797c625a0523e0f68ef65296740538e0 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 15 Oct 2021 15:54:32 +0700 Subject: update some sense warning from -Wconversion --- examples/device/cdc_msc/src/msc_disk.c | 8 ++++---- examples/device/cdc_msc/src/usb_descriptors.c | 2 +- hw/bsp/board.c | 4 ++-- src/class/cdc/cdc_device.c | 2 +- src/class/msc/msc_device.c | 2 +- src/tusb.c | 5 ++--- 6 files changed, 11 insertions(+), 12 deletions(-) diff --git a/examples/device/cdc_msc/src/msc_disk.c b/examples/device/cdc_msc/src/msc_disk.c index cad2602a2..134bda392 100644 --- a/examples/device/cdc_msc/src/msc_disk.c +++ b/examples/device/cdc_msc/src/msc_disk.c @@ -194,7 +194,7 @@ int32_t tud_msc_read10_cb(uint8_t lun, uint32_t lba, uint32_t offset, void* buff uint8_t const* addr = msc_disk[lba] + offset; memcpy(buffer, addr, bufsize); - return bufsize; + return (int32_t) bufsize; } bool tud_msc_is_writable_cb (uint8_t lun) @@ -224,7 +224,7 @@ int32_t tud_msc_write10_cb(uint8_t lun, uint32_t lba, uint32_t offset, uint8_t* (void) lba; (void) offset; (void) buffer; #endif - return bufsize; + return (int32_t) bufsize; } // Callback invoked when received an SCSI command not in built-in list below @@ -263,14 +263,14 @@ int32_t tud_msc_scsi_cb (uint8_t lun, uint8_t const scsi_cmd[16], void* buffer, { if(in_xfer) { - memcpy(buffer, response, resplen); + memcpy(buffer, response, (size_t) resplen); }else { // SCSI output } } - return resplen; + return (int32_t) resplen; } #endif diff --git a/examples/device/cdc_msc/src/usb_descriptors.c b/examples/device/cdc_msc/src/usb_descriptors.c index 34537b8f0..5e397d15a 100644 --- a/examples/device/cdc_msc/src/usb_descriptors.c +++ b/examples/device/cdc_msc/src/usb_descriptors.c @@ -261,7 +261,7 @@ uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid) const char* str = string_desc_arr[index]; // Cap at max char - chr_count = strlen(str); + chr_count = (uint8_t) strlen(str); if ( chr_count > 31 ) chr_count = 31; // Convert ASCII string into UTF-16 diff --git a/hw/bsp/board.c b/hw/bsp/board.c index 6a26f55b7..2c18b61b4 100644 --- a/hw/bsp/board.c +++ b/hw/bsp/board.c @@ -135,13 +135,13 @@ TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count) TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count) { (void) fhdl; - return board_uart_write(buf, count); + return board_uart_write(buf, (int) count); } TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count) { (void) fhdl; - return board_uart_read((uint8_t*) buf, count); + return board_uart_read((uint8_t*) buf, (int) count); } #endif diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c index e622bd616..74c116192 100644 --- a/src/class/cdc/cdc_device.c +++ b/src/class/cdc/cdc_device.c @@ -229,7 +229,7 @@ void cdcd_init(void) { cdcd_interface_t* p_cdc = &_cdcd_itf[i]; - p_cdc->wanted_char = -1; + p_cdc->wanted_char = (char) -1; // default line coding is : stop bit = 1, parity = none, data bits = 8 p_cdc->line_coding.bit_rate = 115200; diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c index c54c4c189..81522be46 100644 --- a/src/class/msc/msc_device.c +++ b/src/class/msc/msc_device.c @@ -152,7 +152,7 @@ static inline uint16_t rdwr10_get_blocksize(msc_cbw_t const* cbw) // invalid block count if (block_count == 0) return 0; - return cbw->total_bytes / block_count; + return (uint16_t) (cbw->total_bytes / block_count); } uint8_t rdwr10_validate_cmd(msc_cbw_t const* cbw) diff --git a/src/tusb.c b/src/tusb.c index 5c6adad24..fc1936c3d 100644 --- a/src/tusb.c +++ b/src/tusb.c @@ -109,9 +109,9 @@ bool tu_edpt_validate(tusb_desc_endpoint_t const * desc_ep, tusb_speed_t speed) void tu_edpt_bind_driver(uint8_t ep2drv[][2], tusb_desc_interface_t const* desc_itf, uint16_t desc_len, uint8_t driver_id) { uint8_t const* p_desc = (uint8_t const*) desc_itf; - uint16_t len = 0; + uint8_t const* desc_end = p_desc + desc_len; - while( len < desc_len ) + while( p_desc < desc_end ) { if ( TUSB_DESC_ENDPOINT == tu_desc_type(p_desc) ) { @@ -121,7 +121,6 @@ void tu_edpt_bind_driver(uint8_t ep2drv[][2], tusb_desc_interface_t const* desc_ ep2drv[tu_edpt_number(ep_addr)][tu_edpt_dir(ep_addr)] = driver_id; } - len += (uint16_t) tu_desc_len(p_desc); p_desc = tu_desc_next(p_desc); } } -- cgit v1.3.1 From 49aa0b72a8301f21281fa6498af47ac26bcb1bea Mon Sep 17 00:00:00 2001 From: Jerzy Kasenberg Date: Fri, 15 Oct 2021 11:34:26 +0200 Subject: dcd_da146xx: Fix EPIN stall notification handling Normal TX handler for IN non-0 endpoints is called during outgoing transfer or just after it was finished. It may need to fill TX fifo with same data if TX_DONE is present but ACK_STAT is not. It may need to fill more data when called during transfer. But it may also be called when STALL was sent. In this case TX_DONE is set ACK_STAT is not, just like for packets that were sent but no ACK was received. Code was trying to send something again. There was nothing to send so empty ZLP was scheduled for stalled endpoint. This ZLP was later send to host where valid response was required. This change checks if notification was for STALL endpoint and does not try to fill TX FIFO in that case. --- src/portable/dialog/da146xx/dcd_da146xx.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/portable/dialog/da146xx/dcd_da146xx.c b/src/portable/dialog/da146xx/dcd_da146xx.c index a36165343..c4b46ac08 100644 --- a/src/portable/dialog/da146xx/dcd_da146xx.c +++ b/src/portable/dialog/da146xx/dcd_da146xx.c @@ -632,6 +632,13 @@ static void handle_epx_tx_ev(xfer_ctl_t *xfer) return; } } + else if (regs->epc_in & USB_USB_EPC1_REG_USB_STALL_Msk) + { + // TX_DONE also indicates that STALL packet was just sent, there is + // no point to put anything into transmit FIFO. It could result in + // empty packet being scheduled. + return; + } } if (txs & USB_USB_TXS1_REG_USB_TX_URUN_Msk) { -- cgit v1.3.1 From bf4b133084585d302691e53faf868c0c37b9eaf0 Mon Sep 17 00:00:00 2001 From: Jerzy Kasenberg Date: Fri, 15 Oct 2021 11:57:52 +0200 Subject: dcd_da146xx: Drop unexpected data USB3CV tool verifies MSC device by sending too short or too long packets. In case of too long packets (msc_device requested 31 bytes but incoming data had 32 bytes) extra byte(s) were left in FIFO resulting in some data mismatch later on. Now if more data is received in packet that expected extra bytes are just dropped. --- src/portable/dialog/da146xx/dcd_da146xx.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/src/portable/dialog/da146xx/dcd_da146xx.c b/src/portable/dialog/da146xx/dcd_da146xx.c index c4b46ac08..f15203ee9 100644 --- a/src/portable/dialog/da146xx/dcd_da146xx.c +++ b/src/portable/dialog/da146xx/dcd_da146xx.c @@ -368,8 +368,8 @@ static void start_rx_packet(xfer_ctl_t *xfer) else { // Other endpoint is using DMA in that direction, fall back to interrupts. - // For endpoint size greater then FIFO size enable FIFO level warning interrupt - // when FIFO has less then 17 bytes free. + // For endpoint size greater than FIFO size enable FIFO level warning interrupt + // when FIFO has less than 17 bytes free. regs->rxc |= USB_USB_RXC1_REG_USB_RFWL_Msk; USB->USB_FWMSK_REG |= 1 << (epnum - 1 + USB_USB_FWMSK_REG_USB_M_RXWARN31_Pos); } @@ -420,7 +420,7 @@ static void start_tx_packet(xfer_ctl_t *xfer) regs->txc |= USB_USB_TXC1_REG_USB_TX_EN_Msk; } -static void read_rx_fifo(xfer_ctl_t *xfer, uint16_t bytes_in_fifo) +static uint16_t read_rx_fifo(xfer_ctl_t *xfer, uint16_t bytes_in_fifo) { EPx_REGS *regs = XFER_REGS(xfer); uint16_t remaining = xfer->total_len - xfer->transferred - xfer->last_packet_size; @@ -433,6 +433,8 @@ static void read_rx_fifo(xfer_ctl_t *xfer, uint16_t bytes_in_fifo) for (int i = 0; i < receive_this_time; ++i) buf[i] = regs->rxd; xfer->last_packet_size += receive_this_time; + + return bytes_in_fifo - receive_this_time; } static void handle_ep0_rx(void) @@ -562,7 +564,7 @@ static void handle_epx_rx_ev(uint8_t ep) // FIFO maybe empty if DMA read it before or it's final iteration and function already read all that was to read. if (fifo_bytes > 0) { - read_rx_fifo(xfer, fifo_bytes); + fifo_bytes = read_rx_fifo(xfer, fifo_bytes); } if (GET_BIT(rxs, USB_USB_RXS1_REG_USB_RX_LAST)) { @@ -577,6 +579,13 @@ static void handle_epx_rx_ev(uint8_t ep) xfer->transferred += xfer->last_packet_size; if (xfer->total_len == xfer->transferred || xfer->last_packet_size < xfer->max_packet_size || xfer->iso) { + if (fifo_bytes) + { + // There are extra bytes in the FIFO just flush them + regs->rxc |= USB_USB_RXC1_REG_USB_FLUSH_Msk; + fifo_bytes = 0; + } + dcd_event_xfer_complete(0, xfer->ep_addr, xfer->transferred, XFER_RESULT_SUCCESS, true); } else -- cgit v1.3.1 From 9a688224d0b19a7b4d33c8bb767d0486d5b1bccd Mon Sep 17 00:00:00 2001 From: Jerzy Kasenberg Date: Fri, 15 Oct 2021 13:47:49 +0200 Subject: msc examples: Extend serial number to 12 digits USB3CV tool complains about too short serial number being used in MSC device. This just extends serial number to 12 characters, it makes it easier to analyze USB3CV logs where this unnecessary warning made output red. Offending warning: Serial Number string for MSC device : iSerialNumber = 0x3 Checking iSerialNumber String Descriptor: index = 0x03. String Descriptor : "123456". (ENGLISH_US) Using Language ID 0x409 MSC Serial Number length = 14 Invalid MSC Serial Number length : should be >= 26 ************************* Invalid MSC Serial Number length ************************* ************************* (MSC: 5.1.2) Serial number must be a string, 12 characters or longer (if the device supports a BOT interface, bInterfaceProtocol = 0x50), or exactly 12 characters long (if the device supports a CBI interface, bInterfaceProtocol = 0x00 or 0x01, and has a serial number). --- examples/device/cdc_msc/src/usb_descriptors.c | 2 +- examples/device/cdc_msc_freertos/src/usb_descriptors.c | 2 +- examples/device/msc_dual_lun/src/usb_descriptors.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/examples/device/cdc_msc/src/usb_descriptors.c b/examples/device/cdc_msc/src/usb_descriptors.c index 34537b8f0..524c5bfb4 100644 --- a/examples/device/cdc_msc/src/usb_descriptors.c +++ b/examples/device/cdc_msc/src/usb_descriptors.c @@ -232,7 +232,7 @@ char const* string_desc_arr [] = (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409) "TinyUSB", // 1: Manufacturer "TinyUSB Device", // 2: Product - "123456", // 3: Serials, should use chip ID + "123456789012", // 3: Serials, should use chip ID "TinyUSB CDC", // 4: CDC Interface "TinyUSB MSC", // 5: MSC Interface }; diff --git a/examples/device/cdc_msc_freertos/src/usb_descriptors.c b/examples/device/cdc_msc_freertos/src/usb_descriptors.c index f3ff305f8..9585822a3 100644 --- a/examples/device/cdc_msc_freertos/src/usb_descriptors.c +++ b/examples/device/cdc_msc_freertos/src/usb_descriptors.c @@ -218,7 +218,7 @@ char const* string_desc_arr [] = (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409) "TinyUSB", // 1: Manufacturer "TinyUSB Device", // 2: Product - "123456", // 3: Serials, should use chip ID + "123456789012", // 3: Serials, should use chip ID "TinyUSB CDC", // 4: CDC Interface "TinyUSB MSC", // 5: MSC Interface }; diff --git a/examples/device/msc_dual_lun/src/usb_descriptors.c b/examples/device/msc_dual_lun/src/usb_descriptors.c index 7e194ea7a..2afd391af 100644 --- a/examples/device/msc_dual_lun/src/usb_descriptors.c +++ b/examples/device/msc_dual_lun/src/usb_descriptors.c @@ -141,7 +141,7 @@ char const* string_desc_arr [] = (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409) "TinyUSB", // 1: Manufacturer "TinyUSB Device", // 2: Product - "123456", // 3: Serials, should use chip ID + "123456789012", // 3: Serials, should use chip ID }; static uint16_t _desc_str[32]; -- cgit v1.3.1 From 0b249618b0469529da748e3e5478751cd56acd31 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 15 Oct 2021 17:35:05 +0700 Subject: fix -Wcast-qual --- hw/bsp/nrf/family.mk | 14 +----------- src/class/dfu/dfu_device.c | 2 +- src/class/hid/hid_device.c | 12 +++++------ src/class/usbtmc/usbtmc_device.c | 40 ++++++++++++++++------------------- src/class/usbtmc/usbtmc_device.h | 6 ------ src/class/video/video_device.c | 19 ++++++++++------- src/common/tusb_common.h | 5 ++--- src/common/tusb_fifo.c | 4 ++-- src/device/usbd.c | 39 ++++++++++++++++++---------------- src/portable/nordic/nrf5x/dcd_nrf5x.c | 4 ++-- 10 files changed, 64 insertions(+), 81 deletions(-) diff --git a/hw/bsp/nrf/family.mk b/hw/bsp/nrf/family.mk index d1afd2587..d8283a9e6 100644 --- a/hw/bsp/nrf/family.mk +++ b/hw/bsp/nrf/family.mk @@ -14,19 +14,7 @@ CFLAGS += \ -DCONFIG_GPIO_AS_PINRESET # suppress warning caused by vendor mcu driver -CFLAGS += -Wno-error=undef -Wno-error=unused-parameter -Wno-error=cast-align - -# due to tusb_hal_nrf_power_event -GCCVERSION = $(firstword $(subst ., ,$(shell arm-none-eabi-gcc -dumpversion))) -ifeq ($(CMDEXE),1) - ifeq ($(shell if $(GCCVERSION) geq 8 echo 1), 1) - CFLAGS += -Wno-error=cast-function-type - endif -else - ifeq ($(shell expr $(GCCVERSION) \>= 8), 1) - CFLAGS += -Wno-error=cast-function-type - endif -endif +CFLAGS += -Wno-error=undef -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=cast-qual # All source paths should be relative to the top level. LD_FILE ?= hw/bsp/nrf/boards/$(BOARD)/nrf52840_s140_v6.ld diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c index 28abf6e83..ddfa608e4 100644 --- a/src/class/dfu/dfu_device.c +++ b/src/class/dfu/dfu_device.c @@ -190,7 +190,7 @@ uint16_t dfu_moded_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, _dfu_ctx.attrs = func_desc->bAttributes; // CFG_TUD_DFU_XFER_BUFSIZE has to be set to the buffer size used in TUD_DFU_DESCRIPTOR - uint16_t const transfer_size = tu_le16toh( tu_unaligned_read16((uint8_t*) func_desc + offsetof(tusb_desc_dfu_functional_t, wTransferSize)) ); + uint16_t const transfer_size = tu_le16toh( tu_unaligned_read16((uint8_t const*) func_desc + offsetof(tusb_desc_dfu_functional_t, wTransferSize)) ); TU_ASSERT(transfer_size <= CFG_TUD_DFU_XFER_BUFSIZE, drv_len); return drv_len; diff --git a/src/class/hid/hid_device.c b/src/class/hid/hid_device.c index 55071a5ce..588b61254 100644 --- a/src/class/hid/hid_device.c +++ b/src/class/hid/hid_device.c @@ -206,8 +206,8 @@ uint16_t hidd_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, uint1 //------------- HID descriptor -------------// p_desc = tu_desc_next(p_desc); + TU_ASSERT(HID_DESC_TYPE_HID == tu_desc_type(p_desc), 0); p_hid->hid_descriptor = (tusb_hid_descriptor_hid_t const *) p_desc; - TU_ASSERT(HID_DESC_TYPE_HID == p_hid->hid_descriptor->bDescriptorType, 0); //------------- Endpoint Descriptor -------------// p_desc = tu_desc_next(p_desc); @@ -216,10 +216,10 @@ uint16_t hidd_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, uint1 if ( desc_itf->bInterfaceSubClass == HID_SUBCLASS_BOOT ) p_hid->itf_protocol = desc_itf->bInterfaceProtocol; p_hid->protocol_mode = HID_PROTOCOL_REPORT; // Per Specs: default is report mode - p_hid->itf_num = desc_itf->bInterfaceNumber; + p_hid->itf_num = desc_itf->bInterfaceNumber; // Use offsetof to avoid pointer to the odd/misaligned address - memcpy(&p_hid->report_desc_len, (uint8_t*) p_hid->hid_descriptor + offsetof(tusb_hid_descriptor_hid_t, wReportLength), 2); + p_hid->report_desc_len = tu_unaligned_read16((uint8_t const*) p_hid->hid_descriptor + offsetof(tusb_hid_descriptor_hid_t, wReportLength)); // Prepare for output endpoint if (p_hid->ep_out) @@ -256,13 +256,13 @@ bool hidd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t if (request->bRequest == TUSB_REQ_GET_DESCRIPTOR && desc_type == HID_DESC_TYPE_HID) { - TU_VERIFY(p_hid->hid_descriptor != NULL); - TU_VERIFY(tud_control_xfer(rhport, request, (void*) p_hid->hid_descriptor, p_hid->hid_descriptor->bLength)); + TU_VERIFY(p_hid->hid_descriptor); + TU_VERIFY(tud_control_xfer(rhport, request, (void*)(uintptr_t) p_hid->hid_descriptor, p_hid->hid_descriptor->bLength)); } else if (request->bRequest == TUSB_REQ_GET_DESCRIPTOR && desc_type == HID_DESC_TYPE_REPORT) { uint8_t const * desc_report = tud_hid_descriptor_report_cb(hid_itf); - tud_control_xfer(rhport, request, (void*) desc_report, p_hid->report_desc_len); + tud_control_xfer(rhport, request, (void*)(uintptr_t) desc_report, p_hid->report_desc_len); } else { diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c index c1ee49f45..86495e3fa 100644 --- a/src/class/usbtmc/usbtmc_device.c +++ b/src/class/usbtmc/usbtmc_device.c @@ -1,10 +1,3 @@ -/* - * usbtmc.c - * - * Created on: Sep 9, 2019 - * Author: nconrad - */ - /* * The MIT License (MIT) * @@ -205,7 +198,7 @@ bool tud_usbtmc_transmit_dev_msg_data( { TU_ASSERT(usbtmc_state.capabilities->bmDevCapabilities.canEndBulkInOnTermChar); TU_ASSERT(termCharRequested); - TU_ASSERT(((uint8_t*)data)[len-1u] == termChar); + TU_ASSERT(((uint8_t const*)data)[len-1u] == termChar); } #endif @@ -228,7 +221,7 @@ bool tud_usbtmc_transmit_dev_msg_data( memcpy((uint8_t*)(usbtmc_state.ep_bulk_in_buf) + headerLen, data, dataLen); usbtmc_state.transfer_size_remaining = len - dataLen; usbtmc_state.transfer_size_sent = dataLen; - usbtmc_state.devInBuffer = (uint8_t*)data + (dataLen); + usbtmc_state.devInBuffer = (uint8_t const*) data + (dataLen); bool stateChanged = atomicChangeState(STATE_TX_REQUESTED, (packetLen >= txBufLen) ? STATE_TX_INITIATED : STATE_TX_SHORTED); @@ -508,13 +501,13 @@ bool usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint case STATE_ABORTING_BULK_OUT: TU_VERIFY(false); return false; // Should be stalled by now, shouldn't have received a packet. + case STATE_TX_REQUESTED: case STATE_TX_INITIATED: case STATE_ABORTING_BULK_IN: case STATE_ABORTING_BULK_IN_SHORTED: case STATE_ABORTING_BULK_IN_ABORTED: default: - TU_VERIFY(false); } } @@ -528,16 +521,16 @@ bool usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint case STATE_TX_INITIATED: if(usbtmc_state.transfer_size_remaining >=sizeof(usbtmc_state.ep_bulk_in_buf)) - { - // FIXME! This removes const below! - TU_VERIFY( usbd_edpt_xfer(rhport, usbtmc_state.ep_bulk_in, - (void*)usbtmc_state.devInBuffer,sizeof(usbtmc_state.ep_bulk_in_buf))); - usbtmc_state.devInBuffer += sizeof(usbtmc_state.ep_bulk_in_buf); - usbtmc_state.transfer_size_remaining -= sizeof(usbtmc_state.ep_bulk_in_buf); - usbtmc_state.transfer_size_sent += sizeof(usbtmc_state.ep_bulk_in_buf); - } - else // last packet - { + { + // FIXME! This removes const below! + TU_VERIFY( usbd_edpt_xfer(rhport, usbtmc_state.ep_bulk_in, + (void*)(uintptr_t) usbtmc_state.devInBuffer, sizeof(usbtmc_state.ep_bulk_in_buf))); + usbtmc_state.devInBuffer += sizeof(usbtmc_state.ep_bulk_in_buf); + usbtmc_state.transfer_size_remaining -= sizeof(usbtmc_state.ep_bulk_in_buf); + usbtmc_state.transfer_size_sent += sizeof(usbtmc_state.ep_bulk_in_buf); + } + else // last packet + { size_t packetLen = usbtmc_state.transfer_size_remaining; memcpy(usbtmc_state.ep_bulk_in_buf, usbtmc_state.devInBuffer, usbtmc_state.transfer_size_remaining); usbtmc_state.transfer_size_sent += sizeof(usbtmc_state.transfer_size_remaining); @@ -550,15 +543,18 @@ bool usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint } } return true; + case STATE_ABORTING_BULK_IN: // need to send short packet (ZLP?) TU_VERIFY( usbd_edpt_xfer(rhport, usbtmc_state.ep_bulk_in, usbtmc_state.ep_bulk_in_buf,(uint16_t)0u)); usbtmc_state.state = STATE_ABORTING_BULK_IN_SHORTED; return true; + case STATE_ABORTING_BULK_IN_SHORTED: /* Done. :)*/ usbtmc_state.state = STATE_ABORTING_BULK_IN_ABORTED; - return true; + return true; + default: TU_ASSERT(false); return false; @@ -787,7 +783,7 @@ bool usbtmcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request { TU_VERIFY(request->bmRequestType == 0xA1); // in,class,interface TU_VERIFY(request->wLength == sizeof(*(usbtmc_state.capabilities))); - TU_VERIFY(tud_control_xfer(rhport, request, (void*)usbtmc_state.capabilities, sizeof(*usbtmc_state.capabilities))); + TU_VERIFY(tud_control_xfer(rhport, request, (void*)(uintptr_t) usbtmc_state.capabilities, sizeof(*usbtmc_state.capabilities))); return true; } // USBTMC Optional Requests diff --git a/src/class/usbtmc/usbtmc_device.h b/src/class/usbtmc/usbtmc_device.h index 622800315..0549a1569 100644 --- a/src/class/usbtmc/usbtmc_device.h +++ b/src/class/usbtmc/usbtmc_device.h @@ -1,9 +1,3 @@ -/* - * usbtmc_device.h - * - * Created on: Sep 10, 2019 - * Author: nconrad - */ /* * The MIT License (MIT) * diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index 91d3b2b72..cc05a1e07 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -585,8 +585,9 @@ static int handle_video_ctl_std_req(uint8_t rhport, uint8_t stage, tusb_desc_vc_itf_t const *vc = _get_desc_vc(&_videod_itf[ctl_idx]); TU_VERIFY(vc, VIDEO_ERROR_UNKNOWN); - TU_VERIFY(tud_control_xfer(rhport, request, (void*)&vc->std.bAlternateSetting, sizeof(vc->std.bAlternateSetting)), - VIDEO_ERROR_UNKNOWN); + uint8_t alt_num = vc->std.bAlternateSetting; + + TU_VERIFY(tud_control_xfer(rhport, request, &alt_num, sizeof(alt_num)), VIDEO_ERROR_UNKNOWN); } return VIDEO_ERROR_NONE; @@ -637,7 +638,7 @@ static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage, if (stage == CONTROL_STAGE_SETUP) { TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN); - TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)&_cap_get_set, sizeof(_cap_get_set)), VIDEO_ERROR_UNKNOWN); + TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)(uintptr_t) &_cap_get_set, sizeof(_cap_get_set)), VIDEO_ERROR_UNKNOWN); } return VIDEO_ERROR_NONE; @@ -657,7 +658,7 @@ static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage, case VIDEO_REQUEST_GET_INFO: if (stage == CONTROL_STAGE_SETUP) { - TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)&_cap_get, sizeof(_cap_get)), VIDEO_ERROR_UNKNOWN); + TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)(uintptr_t) &_cap_get, sizeof(_cap_get)), VIDEO_ERROR_UNKNOWN); } return VIDEO_ERROR_NONE; @@ -708,7 +709,9 @@ static int handle_video_stm_std_req(uint8_t rhport, uint8_t stage, TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN); tusb_desc_vs_itf_t const *vs = _get_desc_vs(self); TU_VERIFY(vs, VIDEO_ERROR_UNKNOWN); - TU_VERIFY(tud_control_xfer(rhport, request, (void*)&vs->std.bAlternateSetting, sizeof(vs->std.bAlternateSetting)), VIDEO_ERROR_UNKNOWN); + uint8_t alt_num = vs->std.bAlternateSetting; + + TU_VERIFY(tud_control_xfer(rhport, request, &alt_num, sizeof(alt_num)), VIDEO_ERROR_UNKNOWN); } return VIDEO_ERROR_NONE; @@ -748,7 +751,7 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, case VIDEO_REQUEST_GET_INFO: if (stage == CONTROL_STAGE_SETUP) { - TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)&_cap_get, sizeof(_cap_get)), VIDEO_ERROR_UNKNOWN); + TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)(uintptr_t) &_cap_get, sizeof(_cap_get)), VIDEO_ERROR_UNKNOWN); } return VIDEO_ERROR_NONE; @@ -808,7 +811,7 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, if (stage == CONTROL_STAGE_SETUP) { TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN); - TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)&_cap_get_set, sizeof(_cap_get_set)), VIDEO_ERROR_UNKNOWN); + TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)(uintptr_t) &_cap_get_set, sizeof(_cap_get_set)), VIDEO_ERROR_UNKNOWN); } return VIDEO_ERROR_NONE; @@ -842,7 +845,7 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, if (stage == CONTROL_STAGE_SETUP) { TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN); - TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)&_cap_get_set, sizeof(_cap_get_set)), VIDEO_ERROR_UNKNOWN); + TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)(uintptr_t) &_cap_get_set, sizeof(_cap_get_set)), VIDEO_ERROR_UNKNOWN); } return VIDEO_ERROR_NONE; diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h index fc4d3bc62..8dd1dbd49 100644 --- a/src/common/tusb_common.h +++ b/src/common/tusb_common.h @@ -161,7 +161,6 @@ static inline uint8_t tu_log2(uint32_t value) #if TUP_ARCH_STRICT_ALIGN // Rely on compiler to generate correct code for unaligned access - typedef struct { uint16_t val; } TU_ATTR_PACKED tu_unaligned_uint16_t; typedef struct { uint32_t val; } TU_ATTR_PACKED tu_unaligned_uint32_t; @@ -227,8 +226,8 @@ TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write16(void* mem, uint16_ #else // MCU that could access unaligned memory natively -TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_unaligned_read32 (const void* mem ) { return *((uint32_t*) mem); } -TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_unaligned_read16 (const void* mem ) { return *((uint16_t*) mem); } +TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_unaligned_read32 (const void* mem) { return *((uint32_t const *) mem); } +TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_unaligned_read16 (const void* mem) { return *((uint16_t const *) mem); } TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write32 (void* mem, uint32_t value ) { *((uint32_t*) mem) = value; } TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write16 (void* mem, uint16_t value ) { *((uint16_t*) mem) = value; } diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c index 11b8fc5f3..564687e02 100644 --- a/src/common/tusb_fifo.c +++ b/src/common/tusb_fifo.c @@ -102,7 +102,7 @@ static inline uint16_t _ff_mod(uint16_t idx, uint16_t depth) // TODO generalize with configurable 1 byte or 4 byte each read static void _ff_push_const_addr(uint8_t * ff_buf, const void * app_buf, uint16_t len) { - volatile uint32_t * rx_fifo = (volatile uint32_t *) app_buf; + volatile const uint32_t * rx_fifo = (volatile const uint32_t *) app_buf; // Reading full available 32 bit words from const app address uint16_t full_words = len >> 2; @@ -201,7 +201,7 @@ static void _ff_push_n(tu_fifo_t* f, void const * app_buf, uint16_t n, uint16_t ff_buf += nLin_4n_bytes; // There could be odd 1-3 bytes before the wrap-around boundary - volatile uint32_t * rx_fifo = (volatile uint32_t *) app_buf; + volatile const uint32_t * rx_fifo = (volatile const uint32_t *) app_buf; uint8_t rem = nLin_bytes & 0x03; if (rem > 0) { diff --git a/src/device/usbd.c b/src/device/usbd.c index 7be41172b..b4680283f 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -990,21 +990,23 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const { TU_LOG2(" Device\r\n"); - uint16_t len = sizeof(tusb_desc_device_t); + void* desc_device = (void*) (uintptr_t) tud_descriptor_device_cb(); - // Only send up to EP0 Packet Size if not addressed and host requested more data - // that device descriptor has. + // Only response with exactly 1 Packet if: not addressed and host requested more data than device descriptor has. // This only happens with the very first get device descriptor and EP0 size = 8 or 16. if ((CFG_TUD_ENDPOINT0_SIZE < sizeof(tusb_desc_device_t)) && !_usbd_dev.addressed && - ((tusb_control_request_t*) p_request)->wLength > sizeof(tusb_desc_device_t)) + ((tusb_control_request_t const*) p_request)->wLength > sizeof(tusb_desc_device_t)) { - len = CFG_TUD_ENDPOINT0_SIZE; - // Hack here: we modify the request length to prevent usbd_control response with zlp - ((tusb_control_request_t*) p_request)->wLength = CFG_TUD_ENDPOINT0_SIZE; - } + // since we are responding with 1 packet & less data than wLength. + tusb_control_request_t mod_request = *p_request; + mod_request.wLength = CFG_TUD_ENDPOINT0_SIZE; - return tud_control_xfer(rhport, p_request, (void*) tud_descriptor_device_cb(), len); + tud_control_xfer(rhport, &mod_request, desc_device, CFG_TUD_ENDPOINT0_SIZE); + }else + { + return tud_control_xfer(rhport, p_request, desc_device, sizeof(tusb_desc_device_t)); + } } break; @@ -1015,10 +1017,11 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const // requested by host if USB > 2.0 ( i.e 2.1 or 3.x ) if (!tud_descriptor_bos_cb) return false; - tusb_desc_bos_t const* desc_bos = (tusb_desc_bos_t const*) tud_descriptor_bos_cb(); + uintptr_t desc_bos = (uintptr_t) tud_descriptor_bos_cb(); + TU_ASSERT(desc_bos); // Use offsetof to avoid pointer to the odd/misaligned address - uint16_t const total_len = tu_le16toh( tu_unaligned_read16((uint8_t*) desc_bos + offsetof(tusb_desc_bos_t, wTotalLength)) ); + uint16_t const total_len = tu_le16toh( tu_unaligned_read16((const void*) (desc_bos + offsetof(tusb_desc_bos_t, wTotalLength))) ); return tud_control_xfer(rhport, p_request, (void*) desc_bos, total_len); } @@ -1027,24 +1030,24 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const case TUSB_DESC_CONFIGURATION: case TUSB_DESC_OTHER_SPEED_CONFIG: { - tusb_desc_configuration_t const* desc_config; + uintptr_t desc_config; if ( desc_type == TUSB_DESC_CONFIGURATION ) { TU_LOG2(" Configuration[%u]\r\n", desc_index); - desc_config = (tusb_desc_configuration_t const*) tud_descriptor_configuration_cb(desc_index); + desc_config = (uintptr_t) tud_descriptor_configuration_cb(desc_index); }else { // Host only request this after getting Device Qualifier descriptor TU_LOG2(" Other Speed Configuration\r\n"); TU_VERIFY( tud_descriptor_other_speed_configuration_cb ); - desc_config = (tusb_desc_configuration_t const*) tud_descriptor_other_speed_configuration_cb(desc_index); + desc_config = (uintptr_t) tud_descriptor_other_speed_configuration_cb(desc_index); } TU_ASSERT(desc_config); // Use offsetof to avoid pointer to the odd/misaligned address - uint16_t const total_len = tu_le16toh( tu_unaligned_read16((uint8_t*) desc_config + offsetof(tusb_desc_configuration_t, wTotalLength)) ); + uint16_t const total_len = tu_le16toh( tu_unaligned_read16((const void*) (desc_config + offsetof(tusb_desc_configuration_t, wTotalLength))) ); return tud_control_xfer(rhport, p_request, (void*) desc_config, total_len); } @@ -1055,11 +1058,11 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const TU_LOG2(" String[%u]\r\n", desc_index); // String Descriptor always uses the desc set from user - uint8_t const* desc_str = (uint8_t const*) tud_descriptor_string_cb(desc_index, p_request->wIndex); + uint8_t const* desc_str = (uint8_t const*) tud_descriptor_string_cb(desc_index, tu_le16toh(p_request->wIndex)); TU_VERIFY(desc_str); // first byte of descriptor is its size - return tud_control_xfer(rhport, p_request, (void*) desc_str, desc_str[0]); + return tud_control_xfer(rhport, p_request, (void*) (uintptr_t) desc_str, tu_desc_len(desc_str)); } break; @@ -1073,7 +1076,7 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const TU_VERIFY(desc_qualifier); // first byte of descriptor is its size - return tud_control_xfer(rhport, p_request, (void*) desc_qualifier, desc_qualifier[0]); + return tud_control_xfer(rhport, p_request, (void*) (uintptr_t) desc_qualifier, tu_desc_len(desc_qualifier)); } break; diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c index f40ba2d4f..06f23f8a5 100644 --- a/src/portable/nordic/nrf5x/dcd_nrf5x.c +++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c @@ -125,7 +125,7 @@ static void edpt_dma_start(volatile uint32_t* reg_startep) if (is_in_isr()) { // Called within ISR, use usbd task to defer later - usbd_defer_func( (osal_task_func_t) edpt_dma_start, (void*) reg_startep, true ); + usbd_defer_func((osal_task_func_t) edpt_dma_start, (void*) (uintptr_t) reg_startep, true); return; } else @@ -773,7 +773,7 @@ void dcd_int_handler(uint8_t rhport) if ( _dcd.dma_pending ) { // use usbd task to defer later - usbd_defer_func( (osal_task_func_t) start_ep0_task, (void*) &NRF_USBD->TASKS_EP0RCVOUT, true ); + usbd_defer_func((osal_task_func_t) start_ep0_task, (void*) (uintptr_t) &NRF_USBD->TASKS_EP0RCVOUT, true); }else { start_ep0_task(&NRF_USBD->TASKS_EP0RCVOUT); -- cgit v1.3.1 From 7325dd633536d086491ef057a544760886190cc7 Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Sat, 16 Oct 2021 12:06:13 +0900 Subject: Change input terminal type to camera --- examples/device/video_capture/src/usb_descriptors.h | 9 +++++---- src/class/video/video.h | 8 ++++++++ 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/examples/device/video_capture/src/usb_descriptors.h b/examples/device/video_capture/src/usb_descriptors.h index 340b3f799..eeaef6bd2 100644 --- a/examples/device/video_capture/src/usb_descriptors.h +++ b/examples/device/video_capture/src/usb_descriptors.h @@ -48,7 +48,7 @@ enum { /* control */\ + TUD_VIDEO_DESC_STD_VC_LEN\ + (TUD_VIDEO_DESC_CS_VC_LEN + 1/*bInCollection*/)\ - + TUD_VIDEO_DESC_INPUT_TERM_LEN\ + + TUD_VIDEO_DESC_CAMERA_TERM_LEN\ + TUD_VIDEO_DESC_OUTPUT_TERM_LEN\ /* Interface 1, Alternate 0 */\ + TUD_VIDEO_DESC_STD_VS_LEN\ @@ -79,9 +79,11 @@ enum { TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx), \ TUD_VIDEO_DESC_CS_VC( /* UVC 1.5*/ 0x0150, \ /* wTotalLength - bLength */ \ - TUD_VIDEO_DESC_INPUT_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, \ + TUD_VIDEO_DESC_CAMERA_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, \ UVC_CLOCK_FREQUENCY, 1), \ - TUD_VIDEO_DESC_INPUT_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, VIDEO_ETT_COMPOSITE_CONNECTOR, 0, 0), \ + TUD_VIDEO_DESC_CAMERA_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, 0, 0,\ + /*wObjectiveFocalLengthMin*/0, /*wObjectiveFocalLengthMax*/0,\ + /*wObjectiveFocalLength*/0, /*bmControls*/0), \ TUD_VIDEO_DESC_OUTPUT_TERM(UVC_ENTITY_CAP_OUTPUT_TERMINAL, VIDEO_TT_STREAMING, 0, 1, 0), \ /* Video stream alt. 0 */ \ TUD_VIDEO_DESC_STD_VS( 1, 0, 0, 0), \ @@ -108,5 +110,4 @@ enum { /* EP */ \ TUD_VIDEO_DESC_EP_ISO(_epin, _epsize, 1) - #endif diff --git a/src/class/video/video.h b/src/class/video/video.h index fa2976611..844746546 100644 --- a/src/class/video/video.h +++ b/src/class/video/video.h @@ -373,6 +373,7 @@ TU_VERIFY_STATIC( sizeof(video_probe_and_commit_control_t) == 48, "size is not c #define TUD_VIDEO_DESC_CS_VC_LEN 12 #define TUD_VIDEO_DESC_INPUT_TERM_LEN 8 #define TUD_VIDEO_DESC_OUTPUT_TERM_LEN 9 +#define TUD_VIDEO_DESC_CAMERA_TERM_LEN 18 #define TUD_VIDEO_DESC_STD_VS_LEN 9 #define TUD_VIDEO_DESC_CS_VS_IN_LEN 13 #define TUD_VIDEO_DESC_CS_VS_OUT_LEN 9 @@ -412,6 +413,13 @@ TU_VERIFY_STATIC( sizeof(video_probe_and_commit_control_t) == 48, "size is not c TUD_VIDEO_DESC_OUTPUT_TERM_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_ITF_VC_OUTPUT_TERMINAL, \ _tid, U16_TO_U8S_LE(_tt), _at, _srcid, _stridx +/* 3.7.2.3 */ +#define TUD_VIDEO_DESC_CAMERA_TERM(_tid, _at, _stridx, _focal_min, _focal_max, _focal, _ctls) \ + TUD_VIDEO_DESC_CAMERA_TERM_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_ITF_VC_INPUT_TERMINAL, \ + _tid, U16_TO_U8S_LE(VIDEO_ITT_CAMERA), _at, _stridx, \ + U16_TO_U8S_LE(_focal_min), U16_TO_U8S_LE(_focal_max), U16_TO_U8S_LE(_focal), 3, \ + TU_U32_BYTE0(_ctls), TU_U32_BYTE1(_ctls), TU_U32_BYTE2(_ctls) + /* 3.9.1 */ #define TUD_VIDEO_DESC_STD_VS(_itfnum, _alt, _epn, _stridx) \ TUD_VIDEO_DESC_STD_VS_LEN, TUSB_DESC_INTERFACE, _itfnum, _alt, \ -- cgit v1.3.1 From a5f516893bbd539f11fb8d1cbb5b6db5a50fc632 Mon Sep 17 00:00:00 2001 From: hathach Date: Sun, 17 Oct 2021 16:26:27 +0700 Subject: more with -Wcast-qual --- examples/device/cdc_msc_freertos/Makefile | 3 +++ examples/device/hid_composite_freertos/Makefile | 3 +++ examples/device/uac2_headset/src/main.c | 13 +++++++------ examples/device/video_capture/src/main.c | 4 ++-- examples/device/webusb_serial/src/main.c | 4 ++-- examples/make.mk | 3 ++- hw/bsp/fomu/fomu.c | 9 +++++++-- hw/bsp/gd32vf103/family.c | 2 +- hw/bsp/imxrt/family.c | 2 +- hw/bsp/lpc15/family.mk | 2 +- hw/bsp/lpc18/family.mk | 2 +- hw/bsp/lpc54/family.c | 2 +- hw/bsp/lpc55/family.c | 2 +- hw/bsp/mm32/family.mk | 2 +- hw/bsp/rx/boards/gr_citrus/gr_citrus.c | 2 +- hw/bsp/rx/boards/rx65n_target/rx65n_target.c | 2 +- hw/bsp/samd11/family.mk | 3 +++ hw/bsp/samd21/family.mk | 3 +++ hw/bsp/samd51/family.mk | 3 ++- hw/bsp/saml2x/family.mk | 3 +++ hw/bsp/stm32f0/family.c | 2 +- hw/bsp/stm32f0/family.mk | 2 +- hw/bsp/stm32f4/family.c | 2 +- hw/bsp/stm32f7/family.c | 2 +- hw/bsp/stm32h7/family.c | 2 +- src/class/cdc/cdc_host.c | 2 +- src/class/msc/msc_host.c | 2 +- src/device/usbd.c | 2 +- src/host/usbh.c | 5 ++--- src/portable/ehci/ehci.c | 6 +++--- src/portable/nxp/transdimension/dcd_transdimension.c | 2 +- src/portable/renesas/usba/dcd_usba.c | 4 ++-- src/portable/st/synopsys/dcd_synopsys.c | 4 ++-- src/portable/valentyusb/eptri/dcd_eptri.c | 12 ++++++------ 34 files changed, 70 insertions(+), 48 deletions(-) diff --git a/examples/device/cdc_msc_freertos/Makefile b/examples/device/cdc_msc_freertos/Makefile index 677dcac9c..a155d6cb7 100644 --- a/examples/device/cdc_msc_freertos/Makefile +++ b/examples/device/cdc_msc_freertos/Makefile @@ -29,6 +29,9 @@ SRC_C += \ $(FREERTOS_SRC)/timers.c \ $(subst ../../../,,$(wildcard ../../../$(FREERTOS_SRC)/portable/GCC/$(FREERTOS_PORT)/*.c)) +# Suppress FreeRTOS warnings +CFLAGS += -Wno-error=cast-qual + # FreeRTOS (lto + Os) linker issue LDFLAGS += -Wl,--undefined=vTaskSwitchContext diff --git a/examples/device/hid_composite_freertos/Makefile b/examples/device/hid_composite_freertos/Makefile index 256db3d8c..c9b7abdf5 100644 --- a/examples/device/hid_composite_freertos/Makefile +++ b/examples/device/hid_composite_freertos/Makefile @@ -28,6 +28,9 @@ SRC_C += \ $(FREERTOS_SRC)/timers.c \ $(subst ../../../,,$(wildcard ../../../$(FREERTOS_SRC)/portable/GCC/$(FREERTOS_PORT)/*.c)) +# Suppress FreeRTOS warnings +CFLAGS += -Wno-error=cast-qual + # FreeRTOS (lto + Os) linker issue LDFLAGS += -Wl,--undefined=vTaskSwitchContext diff --git a/examples/device/uac2_headset/src/main.c b/examples/device/uac2_headset/src/main.c index 790af088f..67e287d3e 100644 --- a/examples/device/uac2_headset/src/main.c +++ b/examples/device/uac2_headset/src/main.c @@ -36,11 +36,12 @@ // List of supported sample rates #if defined(__RX__) -const uint32_t sample_rates[] = {44100, 48000}; + const uint32_t sample_rates[] = {44100, 48000}; #else -const uint32_t sample_rates[] = {44100, 48000, 88200, 96000}; + const uint32_t sample_rates[] = {44100, 48000, 88200, 96000}; #endif -uint32_t current_sample_rate = 44100; + +uint32_t current_sample_rate = 44100; #define N_SAMPLE_RATES TU_ARRAY_SIZE(sample_rates) @@ -202,7 +203,7 @@ static bool tud_audio_clock_set_request(uint8_t rhport, audio_control_request_t { TU_VERIFY(request->wLength == sizeof(audio_control_cur_4_t)); - current_sample_rate = ((audio_control_cur_4_t *)buf)->bCur; + current_sample_rate = ((audio_control_cur_4_t const *)buf)->bCur; TU_LOG1("Clock set current freq: %d\r\n", current_sample_rate); @@ -264,7 +265,7 @@ static bool tud_audio_feature_unit_set_request(uint8_t rhport, audio_control_req { TU_VERIFY(request->wLength == sizeof(audio_control_cur_1_t)); - mute[request->bChannelNumber] = ((audio_control_cur_1_t *)buf)->bCur; + mute[request->bChannelNumber] = ((audio_control_cur_1_t const *)buf)->bCur; TU_LOG1("Set channel %d Mute: %d\r\n", request->bChannelNumber, mute[request->bChannelNumber]); @@ -295,7 +296,7 @@ static bool tud_audio_feature_unit_set_request(uint8_t rhport, audio_control_req // Invoked when audio class specific get request received for an entity bool tud_audio_get_req_entity_cb(uint8_t rhport, tusb_control_request_t const *p_request) { - audio_control_request_t *request = (audio_control_request_t *)p_request; + audio_control_request_t const *request = (audio_control_request_t const *)p_request; if (request->bEntityID == UAC2_ENTITY_CLOCK) return tud_audio_clock_get_request(rhport, request); diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c index a2d95c8f9..f1d48385f 100644 --- a/examples/device/video_capture/src/main.c +++ b/examples/device/video_capture/src/main.c @@ -166,7 +166,7 @@ void video_task(void) already_sent = 1; start_ms = board_millis(); #ifdef CFG_EXAMPLE_VIDEO_READONLY - tud_video_n_frame_xfer(0, 0, (void*)&frame_buffer[(frame_num % (FRAME_WIDTH / 2)) * 4], + tud_video_n_frame_xfer(0, 0, (void*)(uintptr_t) &frame_buffer[(frame_num % (FRAME_WIDTH / 2)) * 4], FRAME_WIDTH * FRAME_HEIGHT * 16/8); #else fill_color_bar(frame_buffer, frame_num); @@ -180,7 +180,7 @@ void video_task(void) start_ms += interval_ms; #ifdef CFG_EXAMPLE_VIDEO_READONLY - tud_video_n_frame_xfer(0, 0, (void*)&frame_buffer[(frame_num % (FRAME_WIDTH / 2)) * 4], + tud_video_n_frame_xfer(0, 0, (void*)(uintptr_t) &frame_buffer[(frame_num % (FRAME_WIDTH / 2)) * 4], FRAME_WIDTH * FRAME_HEIGHT * 16/8); #else fill_color_bar(frame_buffer, frame_num); diff --git a/examples/device/webusb_serial/src/main.c b/examples/device/webusb_serial/src/main.c index aba4aedff..2716825f8 100644 --- a/examples/device/webusb_serial/src/main.c +++ b/examples/device/webusb_serial/src/main.c @@ -179,7 +179,7 @@ bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_requ case VENDOR_REQUEST_WEBUSB: // match vendor request in BOS descriptor // Get landing page url - return tud_control_xfer(rhport, request, (void*) &desc_url, desc_url.bLength); + return tud_control_xfer(rhport, request, (void*)(uintptr_t) &desc_url, desc_url.bLength); case VENDOR_REQUEST_MICROSOFT: if ( request->wIndex == 7 ) @@ -188,7 +188,7 @@ bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_requ uint16_t total_len; memcpy(&total_len, desc_ms_os_20+8, 2); - return tud_control_xfer(rhport, request, (void*) desc_ms_os_20, total_len); + return tud_control_xfer(rhport, request, (void*)(uintptr_t) desc_ms_os_20, total_len); }else { return false; diff --git a/examples/make.mk b/examples/make.mk index c894d35f4..774625577 100644 --- a/examples/make.mk +++ b/examples/make.mk @@ -104,7 +104,8 @@ CFLAGS += \ -Wmissing-format-attribute \ -Wunreachable-code \ -Wcast-align \ - -Wcast-function-type + -Wcast-function-type \ + -Wcast-qual # Debugging/Optimization ifeq ($(DEBUG), 1) diff --git a/hw/bsp/fomu/fomu.c b/hw/bsp/fomu/fomu.c index 25e5e9613..12b7bfd18 100644 --- a/hw/bsp/fomu/fomu.c +++ b/hw/bsp/fomu/fomu.c @@ -101,9 +101,14 @@ int board_uart_read(uint8_t* buf, int len) int board_uart_write(void const * buf, int len) { int32_t offset = 0; + uint8_t const* buf8 = (uint8_t const*) buf; for (offset = 0; offset < len; offset++) - if (! (messible_status_read() & CSR_MESSIBLE_STATUS_FULL_OFFSET)) - messible_in_write(((uint8_t *)buf)[offset]); + { + if (!(messible_status_read() & CSR_MESSIBLE_STATUS_FULL_OFFSET)) + { + messible_in_write(buf8[offset]); + } + } return len; } diff --git a/hw/bsp/gd32vf103/family.c b/hw/bsp/gd32vf103/family.c index d76fb9a2a..c20732302 100644 --- a/hw/bsp/gd32vf103/family.c +++ b/hw/bsp/gd32vf103/family.c @@ -158,7 +158,7 @@ int board_uart_write(void const* buf, int len) { #if defined(UART_DEV) int txsize = len; while (txsize--) { - usart_write(UART_DEV, *(uint8_t*)buf); + usart_write(UART_DEV, *(uint8_t const*)buf); buf++; } return len; diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c index 77a224a5e..716681ca9 100644 --- a/hw/bsp/imxrt/family.c +++ b/hw/bsp/imxrt/family.c @@ -172,7 +172,7 @@ int board_uart_read(uint8_t* buf, int len) int board_uart_write(void const * buf, int len) { - LPUART_WriteBlocking(UART_PORT, (uint8_t*)buf, len); + LPUART_WriteBlocking(UART_PORT, (uint8_t const*)buf, len); return len; } diff --git a/hw/bsp/lpc15/family.mk b/hw/bsp/lpc15/family.mk index e80a3bc51..c7dd3f8be 100644 --- a/hw/bsp/lpc15/family.mk +++ b/hw/bsp/lpc15/family.mk @@ -15,7 +15,7 @@ CFLAGS += \ -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' # mcu driver cause following warnings -CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter -Wno-error=unused-variable +CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter -Wno-error=unused-variable -Wno-error=cast-qual MCU_DIR = hw/mcu/nxp/lpcopen/lpc15xx/lpc_chip_15xx diff --git a/hw/bsp/lpc18/family.mk b/hw/bsp/lpc18/family.mk index 3fed0b45a..79a00cb2d 100644 --- a/hw/bsp/lpc18/family.mk +++ b/hw/bsp/lpc18/family.mk @@ -13,7 +13,7 @@ CFLAGS += \ -DCFG_TUSB_MCU=OPT_MCU_LPC18XX # mcu driver cause following warnings -CFLAGS += -Wno-error=unused-parameter -Wno-error=strict-prototypes +CFLAGS += -Wno-error=unused-parameter -Wno-error=strict-prototypes -Wno-error=cast-qual MCU_DIR = hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx diff --git a/hw/bsp/lpc54/family.c b/hw/bsp/lpc54/family.c index 4789425a3..4f1199c3a 100644 --- a/hw/bsp/lpc54/family.c +++ b/hw/bsp/lpc54/family.c @@ -210,7 +210,7 @@ int board_uart_read(uint8_t* buf, int len) int board_uart_write(void const * buf, int len) { - USART_WriteBlocking(UART_DEV, (uint8_t *)buf, len); + USART_WriteBlocking(UART_DEV, (uint8_t const *) buf, len); return 0; } diff --git a/hw/bsp/lpc55/family.c b/hw/bsp/lpc55/family.c index 4fc1f6222..f037a9f5b 100644 --- a/hw/bsp/lpc55/family.c +++ b/hw/bsp/lpc55/family.c @@ -265,7 +265,7 @@ int board_uart_read(uint8_t* buf, int len) int board_uart_write(void const * buf, int len) { - USART_WriteBlocking(UART_DEV, (uint8_t *)buf, len); + USART_WriteBlocking(UART_DEV, (uint8_t const *) buf, len); return len; } diff --git a/hw/bsp/mm32/family.mk b/hw/bsp/mm32/family.mk index 3273ff870..1a9f51191 100644 --- a/hw/bsp/mm32/family.mk +++ b/hw/bsp/mm32/family.mk @@ -14,7 +14,7 @@ CFLAGS += \ -DCFG_TUSB_MCU=OPT_MCU_MM32F327X # suppress warning caused by vendor mcu driver -CFLAGS += -Wno-error=unused-parameter -Wno-error=maybe-uninitialized +CFLAGS += -Wno-error=unused-parameter -Wno-error=maybe-uninitialized -Wno-error=cast-qual SRC_C += \ src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c \ diff --git a/hw/bsp/rx/boards/gr_citrus/gr_citrus.c b/hw/bsp/rx/boards/gr_citrus/gr_citrus.c index caf5fd6fa..633ddad16 100644 --- a/hw/bsp/rx/boards/gr_citrus/gr_citrus.c +++ b/hw/bsp/rx/boards/gr_citrus/gr_citrus.c @@ -228,7 +228,7 @@ int board_uart_read(uint8_t* buf, int len) int board_uart_write(void const *buf, int len) { - sci0_buf[0].buf = (uint8_t*)buf; + sci0_buf[0].buf = (uint8_t*)(uintptr_t) buf; sci0_buf[0].cnt = len; SCI0.SCR.BYTE |= SCI_SCR_TE | SCI_SCR_TIE; while (SCI0.SCR.BIT.TE) ; diff --git a/hw/bsp/rx/boards/rx65n_target/rx65n_target.c b/hw/bsp/rx/boards/rx65n_target/rx65n_target.c index 20867455e..ab86bc419 100644 --- a/hw/bsp/rx/boards/rx65n_target/rx65n_target.c +++ b/hw/bsp/rx/boards/rx65n_target/rx65n_target.c @@ -273,7 +273,7 @@ int board_uart_read(uint8_t* buf, int len) int board_uart_write(void const *buf, int len) { - sci_buf[0].buf = (uint8_t*)buf; + sci_buf[0].buf = (uint8_t*)(uintptr_t) buf; sci_buf[0].cnt = len; SCI5.SCR.BYTE |= SCI_SCR_TE | SCI_SCR_TIE; while (SCI5.SCR.BIT.TE) ; diff --git a/hw/bsp/samd11/family.mk b/hw/bsp/samd11/family.mk index 032d11b98..ae55be75b 100644 --- a/hw/bsp/samd11/family.mk +++ b/hw/bsp/samd11/family.mk @@ -11,6 +11,9 @@ CFLAGS += \ -DOSC32K_OVERWRITE_CALIBRATION=0 \ -DCFG_TUSB_MCU=OPT_MCU_SAMD11 +# suppress warning caused by vendor mcu driver +CFLAGS += -Wno-error=cast-qual + SRC_C += \ src/portable/microchip/samd/dcd_samd.c \ hw/mcu/microchip/samd11/gcc/gcc/startup_samd11.c \ diff --git a/hw/bsp/samd21/family.mk b/hw/bsp/samd21/family.mk index f1b063f2c..208f23789 100644 --- a/hw/bsp/samd21/family.mk +++ b/hw/bsp/samd21/family.mk @@ -12,6 +12,9 @@ CFLAGS += \ -DCONF_DFLL_OVERWRITE_CALIBRATION=0 \ -DCFG_TUSB_MCU=OPT_MCU_SAMD21 +# suppress warning caused by vendor mcu driver +CFLAGS += -Wno-error=cast-qual + SRC_C += \ src/portable/microchip/samd/dcd_samd.c \ hw/mcu/microchip/samd21/gcc/gcc/startup_samd21.c \ diff --git a/hw/bsp/samd51/family.mk b/hw/bsp/samd51/family.mk index f4e260fb1..783bed82a 100644 --- a/hw/bsp/samd51/family.mk +++ b/hw/bsp/samd51/family.mk @@ -13,7 +13,8 @@ CFLAGS += \ -nostdlib -nostartfiles \ -DCFG_TUSB_MCU=OPT_MCU_SAMD51 -CFLAGS += -Wno-error=undef +# suppress warning caused by vendor mcu driver +CFLAGS += -Wno-error=cast-qual SRC_C += \ src/portable/microchip/samd/dcd_samd.c \ diff --git a/hw/bsp/saml2x/family.mk b/hw/bsp/saml2x/family.mk index e0f6b2f77..bb1faeb7f 100644 --- a/hw/bsp/saml2x/family.mk +++ b/hw/bsp/saml2x/family.mk @@ -13,6 +13,9 @@ CFLAGS += \ -DCONF_OSC32K_CALIB_ENABLE=0 \ -DCFG_TUSB_MCU=OPT_MCU_SAML22 +# suppress warning caused by vendor mcu driver +CFLAGS += -Wno-error=cast-qual + SRC_C += \ src/portable/microchip/samd/dcd_samd.c \ $(MCU_DIR)/gcc/gcc/startup_$(SAML_VARIANT).c \ diff --git a/hw/bsp/stm32f0/family.c b/hw/bsp/stm32f0/family.c index 68b924432..8de3147e2 100644 --- a/hw/bsp/stm32f0/family.c +++ b/hw/bsp/stm32f0/family.c @@ -134,7 +134,7 @@ int board_uart_read(uint8_t* buf, int len) int board_uart_write(void const * buf, int len) { - HAL_UART_Transmit(&UartHandle, (uint8_t*) buf, len, 0xffff); + HAL_UART_Transmit(&UartHandle, (uint8_t*)(uintptr_t) buf, len, 0xffff); return len; } diff --git a/hw/bsp/stm32f0/family.mk b/hw/bsp/stm32f0/family.mk index 08cbf5626..39831e154 100644 --- a/hw/bsp/stm32f0/family.mk +++ b/hw/bsp/stm32f0/family.mk @@ -18,7 +18,7 @@ CFLAGS += \ -DCFG_TUSB_MCU=OPT_MCU_STM32F0 # suppress warning caused by vendor mcu driver -CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align +CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=cast-qual SRC_C += \ src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \ diff --git a/hw/bsp/stm32f4/family.c b/hw/bsp/stm32f4/family.c index cf0cb2b08..31f27fa3f 100644 --- a/hw/bsp/stm32f4/family.c +++ b/hw/bsp/stm32f4/family.c @@ -160,7 +160,7 @@ int board_uart_read(uint8_t* buf, int len) int board_uart_write(void const * buf, int len) { #ifdef UART_DEV - HAL_UART_Transmit(&UartHandle, (uint8_t*) buf, len, 0xffff); + HAL_UART_Transmit(&UartHandle, (uint8_t*)(uintptr_t) buf, len, 0xffff); return len; #else (void) buf; (void) len; (void) UartHandle; diff --git a/hw/bsp/stm32f7/family.c b/hw/bsp/stm32f7/family.c index 2eb737ee3..14e3b2fd9 100644 --- a/hw/bsp/stm32f7/family.c +++ b/hw/bsp/stm32f7/family.c @@ -284,7 +284,7 @@ int board_uart_read(uint8_t* buf, int len) int board_uart_write(void const * buf, int len) { - HAL_UART_Transmit(&UartHandle, (uint8_t*) buf, len, 0xffff); + HAL_UART_Transmit(&UartHandle, (uint8_t*)(uintptr_t) buf, len, 0xffff); return len; } diff --git a/hw/bsp/stm32h7/family.c b/hw/bsp/stm32h7/family.c index a2116d0bd..84976b4e4 100644 --- a/hw/bsp/stm32h7/family.c +++ b/hw/bsp/stm32h7/family.c @@ -237,7 +237,7 @@ int board_uart_read(uint8_t* buf, int len) int board_uart_write(void const * buf, int len) { - HAL_UART_Transmit(&UartHandle, (uint8_t*) buf, len, 0xffff); + HAL_UART_Transmit(&UartHandle, (uint8_t*)(uintptr_t) buf, len, 0xffff); return len; } diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index e7eaf4d05..f4fb6c1d6 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -105,7 +105,7 @@ bool tuh_cdc_send(uint8_t dev_addr, void const * p_data, uint32_t length, bool i uint8_t const ep_out = cdch_data[dev_addr-1].ep_out; if ( usbh_edpt_busy(dev_addr, ep_out) ) return false; - return usbh_edpt_xfer(dev_addr, ep_out, (void *) p_data, length); + return usbh_edpt_xfer(dev_addr, ep_out, (void*)(uintptr_t) p_data, length); } bool tuh_cdc_receive(uint8_t dev_addr, void * p_buffer, uint32_t length, bool is_notify) diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c index 8069353cd..fa6519956 100644 --- a/src/class/msc/msc_host.c +++ b/src/class/msc/msc_host.c @@ -263,7 +263,7 @@ bool tuh_msc_write10(uint8_t dev_addr, uint8_t lun, void const * buffer, uint32_ memcpy(cbw.command, &cmd_write10, cbw.cmd_len); - return tuh_msc_scsi_command(dev_addr, &cbw, (void*) buffer, complete_cb); + return tuh_msc_scsi_command(dev_addr, &cbw, (void*)(uintptr_t) buffer, complete_cb); } #if 0 diff --git a/src/device/usbd.c b/src/device/usbd.c index b4680283f..6a5210b34 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -1002,7 +1002,7 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const tusb_control_request_t mod_request = *p_request; mod_request.wLength = CFG_TUD_ENDPOINT0_SIZE; - tud_control_xfer(rhport, &mod_request, desc_device, CFG_TUD_ENDPOINT0_SIZE); + return tud_control_xfer(rhport, &mod_request, desc_device, CFG_TUD_ENDPOINT0_SIZE); }else { return tud_control_xfer(rhport, p_request, desc_device, sizeof(tusb_desc_device_t)); diff --git a/src/host/usbh.c b/src/host/usbh.c index 2ef936ad0..53e8b9715 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -894,11 +894,10 @@ static bool enum_get_9byte_config_desc_complete(uint8_t dev_addr, tusb_control_r TU_ASSERT(XFER_RESULT_SUCCESS == result); // TODO not enough buffer to hold configuration descriptor - tusb_desc_configuration_t const * desc_config = (tusb_desc_configuration_t const*) _usbh_ctrl_buf; - uint16_t total_len; + uint8_t const * desc_config = _usbh_ctrl_buf; // Use offsetof to avoid pointer to the odd/misaligned address - memcpy(&total_len, (uint8_t*) desc_config + offsetof(tusb_desc_configuration_t, wTotalLength), 2); + uint16_t const total_len = tu_le16toh( tu_unaligned_read16(desc_config + offsetof(tusb_desc_configuration_t, wTotalLength)) ); TU_ASSERT(total_len <= CFG_TUH_ENUMERATION_BUFSIZE); diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index e3b7499cc..18ddaf31a 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -128,7 +128,7 @@ static inline ehci_qtd_t* qtd_find_free (void); static inline ehci_qtd_t* qtd_next (ehci_qtd_t const * p_qtd); static inline void qtd_insert_to_qhd (ehci_qhd_t *p_qhd, ehci_qtd_t *p_qtd_new); static inline void qtd_remove_1st_from_qhd (ehci_qhd_t *p_qhd); -static void qtd_init (ehci_qtd_t* p_qtd, void* buffer, uint16_t total_bytes); +static void qtd_init (ehci_qtd_t* p_qtd, void const* buffer, uint16_t total_bytes); static inline void list_insert (ehci_link_t *current, ehci_link_t *new, uint8_t new_type); static inline ehci_link_t* list_next (ehci_link_t *p_link_pointer); @@ -392,7 +392,7 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet ehci_qhd_t* qhd = &ehci_data.control[dev_addr].qhd; ehci_qtd_t* td = &ehci_data.control[dev_addr].qtd; - qtd_init(td, (void*) setup_packet, 8); + qtd_init(td, setup_packet, 8); td->pid = EHCI_PID_SETUP; td->int_on_complete = 1; td->next.terminate = 1; @@ -857,7 +857,7 @@ static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t c } } -static void qtd_init(ehci_qtd_t* p_qtd, void* buffer, uint16_t total_bytes) +static void qtd_init(ehci_qtd_t* p_qtd, void const* buffer, uint16_t total_bytes) { tu_memclr(p_qtd, sizeof(ehci_qtd_t)); diff --git a/src/portable/nxp/transdimension/dcd_transdimension.c b/src/portable/nxp/transdimension/dcd_transdimension.c index a7c4545c2..0f58cceb9 100644 --- a/src/portable/nxp/transdimension/dcd_transdimension.c +++ b/src/portable/nxp/transdimension/dcd_transdimension.c @@ -636,7 +636,7 @@ void dcd_int_handler(uint8_t rhport) // 23.10.10.2 Operational model for setup transfers dcd_reg->ENDPTSETUPSTAT = dcd_reg->ENDPTSETUPSTAT; - dcd_event_setup_received(rhport, (uint8_t*) &_dcd_data.qhd[0][0].setup_request, true); + dcd_event_setup_received(rhport, (uint8_t*)(uintptr_t) &_dcd_data.qhd[0][0].setup_request, true); } // 23.10.12.3 Failed QTD also get ENDPTCOMPLETE set diff --git a/src/portable/renesas/usba/dcd_usba.c b/src/portable/renesas/usba/dcd_usba.c index 92e29f9bf..07d3ba898 100644 --- a/src/portable/renesas/usba/dcd_usba.c +++ b/src/portable/renesas/usba/dcd_usba.c @@ -259,7 +259,7 @@ static inline void pipe_wait_for_ready(unsigned num) static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) { - hw_fifo_t *reg = (hw_fifo_t*)fifo; + volatile hw_fifo_t *reg = (volatile hw_fifo_t*) fifo; uintptr_t addr = (uintptr_t)buf; while (len >= 2) { reg->u16 = *(const uint16_t *)addr; @@ -275,7 +275,7 @@ static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len) { uint8_t *p = (uint8_t*)buf; - uint8_t *reg = (uint8_t*)fifo; /* byte access is always at base register address */ + volatile uint8_t *reg = (volatile uint8_t*)fifo; /* byte access is always at base register address */ while (len--) *p++ = *reg; } diff --git a/src/portable/st/synopsys/dcd_synopsys.c b/src/portable/st/synopsys/dcd_synopsys.c index 85abf940e..29030784b 100644 --- a/src/portable/st/synopsys/dcd_synopsys.c +++ b/src/portable/st/synopsys/dcd_synopsys.c @@ -976,7 +976,7 @@ static void handle_rxflvl_ints(uint8_t rhport, USB_OTG_OUTEndpointTypeDef * out_ if (xfer->ff) { // Ring buffer - tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void *) rx_fifo, bcnt); + tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void *)(uintptr_t) rx_fifo, bcnt); } else { @@ -1096,7 +1096,7 @@ static void handle_epin_ints(uint8_t rhport, USB_OTG_DeviceTypeDef * dev, USB_OT if (xfer->ff) { usb_fifo_t tx_fifo = FIFO_BASE(rhport, n); - tu_fifo_read_n_const_addr_full_words(xfer->ff, (void *) tx_fifo, packet_size); + tu_fifo_read_n_const_addr_full_words(xfer->ff, (void *)(uintptr_t) tx_fifo, packet_size); } else { diff --git a/src/portable/valentyusb/eptri/dcd_eptri.c b/src/portable/valentyusb/eptri/dcd_eptri.c index 89bc7a1ab..837d0c0ce 100644 --- a/src/portable/valentyusb/eptri/dcd_eptri.c +++ b/src/portable/valentyusb/eptri/dcd_eptri.c @@ -314,13 +314,13 @@ static void dcd_reset(void) usb_in_ctrl_write(1 << CSR_USB_IN_CTRL_RESET_OFFSET); usb_out_ctrl_write(1 << CSR_USB_OUT_CTRL_RESET_OFFSET); - memset((void *)rx_buffer, 0, sizeof(rx_buffer)); - memset((void *)rx_buffer_max, 0, sizeof(rx_buffer_max)); - memset((void *)rx_buffer_offset, 0, sizeof(rx_buffer_offset)); + memset((void *)(uintptr_t) rx_buffer, 0, sizeof(rx_buffer)); + memset((void *)(uintptr_t) rx_buffer_max, 0, sizeof(rx_buffer_max)); + memset((void *)(uintptr_t) rx_buffer_offset, 0, sizeof(rx_buffer_offset)); - memset((void *)tx_buffer, 0, sizeof(tx_buffer)); - memset((void *)tx_buffer_max, 0, sizeof(tx_buffer_max)); - memset((void *)tx_buffer_offset, 0, sizeof(tx_buffer_offset)); + memset((void *)(uintptr_t) tx_buffer, 0, sizeof(tx_buffer)); + memset((void *)(uintptr_t) tx_buffer_max, 0, sizeof(tx_buffer_max)); + memset((void *)(uintptr_t) tx_buffer_offset, 0, sizeof(tx_buffer_offset)); tx_ep = 0; tx_active = false; -- cgit v1.3.1 From 31cd36693502cbeb9537dc280f674f99e4488df9 Mon Sep 17 00:00:00 2001 From: hathach Date: Sun, 17 Oct 2021 17:32:03 +0700 Subject: more -Wcast-qual --- hw/bsp/d5035_01/board.mk | 3 +++ hw/bsp/ea4088qs/board.mk | 2 +- hw/bsp/ea4357/board.mk | 2 +- hw/bsp/frdm_k32l2b/frdm_k32l2b.c | 2 +- hw/bsp/frdm_kl25z/frdm_kl25z.c | 2 +- hw/bsp/lpcxpresso1769/board.mk | 2 +- hw/bsp/mbed1768/board.mk | 2 +- hw/bsp/ngx4330/board.mk | 2 +- hw/bsp/nutiny_nuc121s/board.mk | 14 +------------- hw/bsp/nutiny_nuc126v/board.mk | 17 +---------------- hw/bsp/nutiny_sdk_nuc120/board.mk | 17 +---------------- hw/bsp/same54xplainedpro/board.mk | 2 ++ hw/bsp/same70_qmtech/board.mk | 2 +- hw/bsp/same70_xplained/board.mk | 2 +- hw/bsp/samg55xplained/board.mk | 2 +- hw/bsp/stm32l4r5nucleo/stm32l4r5nucleo.c | 2 +- src/portable/sony/cxd56/dcd_cxd56.c | 2 +- 17 files changed, 20 insertions(+), 57 deletions(-) diff --git a/hw/bsp/d5035_01/board.mk b/hw/bsp/d5035_01/board.mk index 1d09bd3d4..b7796b9d8 100644 --- a/hw/bsp/d5035_01/board.mk +++ b/hw/bsp/d5035_01/board.mk @@ -18,6 +18,9 @@ CFLAGS += \ -DSVC_Handler=SVCall_Handler \ -DHWREV=$(HWREV) +# suppress warning caused by vendor mcu driver +CFLAGS += -Wno-error=cast-qual + # All source paths should be relative to the top level. LD_FILE = hw/bsp/$(BOARD)/same51j19a_flash.ld diff --git a/hw/bsp/ea4088qs/board.mk b/hw/bsp/ea4088qs/board.mk index c624a5cf2..b325dfeb4 100644 --- a/hw/bsp/ea4088qs/board.mk +++ b/hw/bsp/ea4088qs/board.mk @@ -14,7 +14,7 @@ CFLAGS += \ -DCFG_TUSB_MCU=OPT_MCU_LPC40XX # mcu driver cause following warnings -CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter +CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter -Wno-error=cast-qual MCU_DIR = hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx diff --git a/hw/bsp/ea4357/board.mk b/hw/bsp/ea4357/board.mk index 86391ab5d..4390d1eda 100644 --- a/hw/bsp/ea4357/board.mk +++ b/hw/bsp/ea4357/board.mk @@ -13,7 +13,7 @@ CFLAGS += \ -DCFG_TUSB_MCU=OPT_MCU_LPC43XX # mcu driver cause following warnings -CFLAGS += -Wno-error=unused-parameter -Wno-error=strict-prototypes +CFLAGS += -Wno-error=unused-parameter -Wno-error=strict-prototypes -Wno-error=cast-qual MCU_DIR = hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx diff --git a/hw/bsp/frdm_k32l2b/frdm_k32l2b.c b/hw/bsp/frdm_k32l2b/frdm_k32l2b.c index c45095caa..924bb18e9 100644 --- a/hw/bsp/frdm_k32l2b/frdm_k32l2b.c +++ b/hw/bsp/frdm_k32l2b/frdm_k32l2b.c @@ -122,7 +122,7 @@ int board_uart_read(uint8_t* buf, int len) int board_uart_write(void const * buf, int len) { - LPUART_WriteBlocking(UART_PORT, (uint8_t*)buf, len); + LPUART_WriteBlocking(UART_PORT, (uint8_t const*) buf, len); return len; } diff --git a/hw/bsp/frdm_kl25z/frdm_kl25z.c b/hw/bsp/frdm_kl25z/frdm_kl25z.c index cdc996bc2..72982ed8a 100644 --- a/hw/bsp/frdm_kl25z/frdm_kl25z.c +++ b/hw/bsp/frdm_kl25z/frdm_kl25z.c @@ -153,7 +153,7 @@ int board_uart_read(uint8_t* buf, int len) int board_uart_write(void const * buf, int len) { - LPSCI_WriteBlocking(UART_PORT, (uint8_t*)buf, len); + LPSCI_WriteBlocking(UART_PORT, (uint8_t const*) buf, len); return len; } diff --git a/hw/bsp/lpcxpresso1769/board.mk b/hw/bsp/lpcxpresso1769/board.mk index b69be39bd..34b4d6dc0 100644 --- a/hw/bsp/lpcxpresso1769/board.mk +++ b/hw/bsp/lpcxpresso1769/board.mk @@ -12,7 +12,7 @@ CFLAGS += \ -DRTC_EV_SUPPORT=0 # lpc_types.h cause following errors -CFLAGS += -Wno-error=strict-prototypes +CFLAGS += -Wno-error=strict-prototypes -Wno-error=cast-qual MCU_DIR = hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x diff --git a/hw/bsp/mbed1768/board.mk b/hw/bsp/mbed1768/board.mk index e99df9f08..b0d885866 100644 --- a/hw/bsp/mbed1768/board.mk +++ b/hw/bsp/mbed1768/board.mk @@ -12,7 +12,7 @@ CFLAGS += \ -DRTC_EV_SUPPORT=0 # startup.c and lpc_types.h cause following errors -CFLAGS += -Wno-error=strict-prototypes +CFLAGS += -Wno-error=strict-prototypes -Wno-error=cast-qual MCU_DIR = hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x diff --git a/hw/bsp/ngx4330/board.mk b/hw/bsp/ngx4330/board.mk index 04c37feeb..3b193c0a5 100644 --- a/hw/bsp/ngx4330/board.mk +++ b/hw/bsp/ngx4330/board.mk @@ -13,7 +13,7 @@ CFLAGS += \ -DCFG_TUSB_MCU=OPT_MCU_LPC43XX # mcu driver cause following warnings -CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter +CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter -Wno-error=cast-qual MCU_DIR = hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx diff --git a/hw/bsp/nutiny_nuc121s/board.mk b/hw/bsp/nutiny_nuc121s/board.mk index a0a208ca7..ff1d5aa3a 100644 --- a/hw/bsp/nutiny_nuc121s/board.mk +++ b/hw/bsp/nutiny_nuc121s/board.mk @@ -16,24 +16,12 @@ LD_FILE = hw/bsp/$(BOARD)/nuc121_flash.ld SRC_C += \ src/portable/nuvoton/nuc121/dcd_nuc121.c \ hw/mcu/nuvoton/nuc121_125/Device/Nuvoton/NUC121/Source/system_NUC121.c \ - hw/mcu/nuvoton/nuc121_125/StdDriver/src/adc.c \ - hw/mcu/nuvoton/nuc121_125/StdDriver/src/bpwm.c \ hw/mcu/nuvoton/nuc121_125/StdDriver/src/clk.c \ hw/mcu/nuvoton/nuc121_125/StdDriver/src/fmc.c \ hw/mcu/nuvoton/nuc121_125/StdDriver/src/gpio.c \ - hw/mcu/nuvoton/nuc121_125/StdDriver/src/i2c.c \ - hw/mcu/nuvoton/nuc121_125/StdDriver/src/pdma.c \ - hw/mcu/nuvoton/nuc121_125/StdDriver/src/pwm.c \ - hw/mcu/nuvoton/nuc121_125/StdDriver/src/spi_i2s.c \ hw/mcu/nuvoton/nuc121_125/StdDriver/src/sys.c \ hw/mcu/nuvoton/nuc121_125/StdDriver/src/timer.c \ - hw/mcu/nuvoton/nuc121_125/StdDriver/src/uart.c \ - hw/mcu/nuvoton/nuc121_125/StdDriver/src/usbd.c \ - hw/mcu/nuvoton/nuc121_125/StdDriver/src/usci_i2c.c \ - hw/mcu/nuvoton/nuc121_125/StdDriver/src/usci_spi.c \ - hw/mcu/nuvoton/nuc121_125/StdDriver/src/usci_uart.c \ - hw/mcu/nuvoton/nuc121_125/StdDriver/src/wdt.c \ - hw/mcu/nuvoton/nuc121_125/StdDriver/src/wwdt.c + hw/mcu/nuvoton/nuc121_125/StdDriver/src/uart.c SRC_S += \ hw/mcu/nuvoton/nuc121_125/Device/Nuvoton/NUC121/Source/GCC/startup_NUC121.S diff --git a/hw/bsp/nutiny_nuc126v/board.mk b/hw/bsp/nutiny_nuc126v/board.mk index e9df1ed13..4f0ebf201 100644 --- a/hw/bsp/nutiny_nuc126v/board.mk +++ b/hw/bsp/nutiny_nuc126v/board.mk @@ -17,28 +17,13 @@ LD_FILE = hw/bsp/$(BOARD)/nuc126_flash.ld SRC_C += \ src/portable/nuvoton/nuc121/dcd_nuc121.c \ hw/mcu/nuvoton/nuc126/Device/Nuvoton/NUC126/Source/system_NUC126.c \ - hw/mcu/nuvoton/nuc126/StdDriver/src/acmp.c \ - hw/mcu/nuvoton/nuc126/StdDriver/src/adc.c \ hw/mcu/nuvoton/nuc126/StdDriver/src/clk.c \ hw/mcu/nuvoton/nuc126/StdDriver/src/crc.c \ - hw/mcu/nuvoton/nuc126/StdDriver/src/ebi.c \ - hw/mcu/nuvoton/nuc126/StdDriver/src/fmc.c \ hw/mcu/nuvoton/nuc126/StdDriver/src/gpio.c \ - hw/mcu/nuvoton/nuc126/StdDriver/src/pdma.c \ - hw/mcu/nuvoton/nuc126/StdDriver/src/pwm.c \ hw/mcu/nuvoton/nuc126/StdDriver/src/rtc.c \ - hw/mcu/nuvoton/nuc126/StdDriver/src/sc.c \ - hw/mcu/nuvoton/nuc126/StdDriver/src/scuart.c \ - hw/mcu/nuvoton/nuc126/StdDriver/src/spi.c \ hw/mcu/nuvoton/nuc126/StdDriver/src/sys.c \ hw/mcu/nuvoton/nuc126/StdDriver/src/timer.c \ - hw/mcu/nuvoton/nuc126/StdDriver/src/timer_pwm.c \ - hw/mcu/nuvoton/nuc126/StdDriver/src/uart.c \ - hw/mcu/nuvoton/nuc126/StdDriver/src/usbd.c \ - hw/mcu/nuvoton/nuc126/StdDriver/src/usci_spi.c \ - hw/mcu/nuvoton/nuc126/StdDriver/src/usci_uart.c \ - hw/mcu/nuvoton/nuc126/StdDriver/src/wdt.c \ - hw/mcu/nuvoton/nuc126/StdDriver/src/wwdt.c + hw/mcu/nuvoton/nuc126/StdDriver/src/uart.c SRC_S += \ hw/mcu/nuvoton/nuc126/Device/Nuvoton/NUC126/Source/GCC/startup_NUC126.S diff --git a/hw/bsp/nutiny_sdk_nuc120/board.mk b/hw/bsp/nutiny_sdk_nuc120/board.mk index 1fde47c5a..4d7aac7f5 100644 --- a/hw/bsp/nutiny_sdk_nuc120/board.mk +++ b/hw/bsp/nutiny_sdk_nuc120/board.mk @@ -15,26 +15,11 @@ LD_FILE = hw/bsp/nutiny_sdk_nuc120/nuc120_flash.ld SRC_C += \ src/portable/nuvoton/nuc120/dcd_nuc120.c \ hw/mcu/nuvoton/nuc100_120/Device/Nuvoton/NUC100Series/Source/system_NUC100Series.c \ - hw/mcu/nuvoton/nuc100_120/StdDriver/src/acmp.c \ - hw/mcu/nuvoton/nuc100_120/StdDriver/src/adc.c \ hw/mcu/nuvoton/nuc100_120/StdDriver/src/clk.c \ - hw/mcu/nuvoton/nuc100_120/StdDriver/src/crc.c \ - hw/mcu/nuvoton/nuc100_120/StdDriver/src/fmc.c \ hw/mcu/nuvoton/nuc100_120/StdDriver/src/gpio.c \ - hw/mcu/nuvoton/nuc100_120/StdDriver/src/i2c.c \ - hw/mcu/nuvoton/nuc100_120/StdDriver/src/i2s.c \ - hw/mcu/nuvoton/nuc100_120/StdDriver/src/pdma.c \ - hw/mcu/nuvoton/nuc100_120/StdDriver/src/ps2.c \ - hw/mcu/nuvoton/nuc100_120/StdDriver/src/pwm.c \ - hw/mcu/nuvoton/nuc100_120/StdDriver/src/rtc.c \ - hw/mcu/nuvoton/nuc100_120/StdDriver/src/sc.c \ - hw/mcu/nuvoton/nuc100_120/StdDriver/src/spi.c \ hw/mcu/nuvoton/nuc100_120/StdDriver/src/sys.c \ hw/mcu/nuvoton/nuc100_120/StdDriver/src/timer.c \ - hw/mcu/nuvoton/nuc100_120/StdDriver/src/uart.c \ - hw/mcu/nuvoton/nuc100_120/StdDriver/src/usbd.c \ - hw/mcu/nuvoton/nuc100_120/StdDriver/src/wdt.c \ - hw/mcu/nuvoton/nuc100_120/StdDriver/src/wwdt.c + hw/mcu/nuvoton/nuc100_120/StdDriver/src/uart.c SRC_S += \ hw/mcu/nuvoton/nuc100_120/Device/Nuvoton/NUC100Series/Source/GCC/startup_NUC100Series.S diff --git a/hw/bsp/same54xplainedpro/board.mk b/hw/bsp/same54xplainedpro/board.mk index 16ac786d5..2d0d928ff 100644 --- a/hw/bsp/same54xplainedpro/board.mk +++ b/hw/bsp/same54xplainedpro/board.mk @@ -15,6 +15,8 @@ CFLAGS += \ -DCFG_TUSB_MCU=OPT_MCU_SAME5X \ -DBOARD_NAME="\"Microchip SAM E54 Xplained Pro\"" +# suppress warning caused by vendor mcu driver +CFLAGS += -Wno-error=cast-qual # All source paths should be relative to the top level. LD_FILE = hw/bsp/$(BOARD)/same54p20a_flash.ld diff --git a/hw/bsp/same70_qmtech/board.mk b/hw/bsp/same70_qmtech/board.mk index 6c84810f3..ba7088e44 100644 --- a/hw/bsp/same70_qmtech/board.mk +++ b/hw/bsp/same70_qmtech/board.mk @@ -11,7 +11,7 @@ CFLAGS += \ -DCFG_TUSB_MCU=OPT_MCU_SAMX7X # suppress following warnings from mcu driver -CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align +CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=cast-qual ASF_DIR = hw/mcu/microchip/same70 diff --git a/hw/bsp/same70_xplained/board.mk b/hw/bsp/same70_xplained/board.mk index c9bc0cea3..cb2decf50 100644 --- a/hw/bsp/same70_xplained/board.mk +++ b/hw/bsp/same70_xplained/board.mk @@ -11,7 +11,7 @@ CFLAGS += \ -DCFG_TUSB_MCU=OPT_MCU_SAMX7X # suppress following warnings from mcu driver -CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align +CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=cast-qual ASF_DIR = hw/mcu/microchip/same70 diff --git a/hw/bsp/samg55xplained/board.mk b/hw/bsp/samg55xplained/board.mk index aed4de68e..f9396cb30 100644 --- a/hw/bsp/samg55xplained/board.mk +++ b/hw/bsp/samg55xplained/board.mk @@ -12,7 +12,7 @@ CFLAGS += \ -DCFG_TUSB_MCU=OPT_MCU_SAMG # suppress following warnings from mcu driver -CFLAGS += -Wno-error=undef +CFLAGS += -Wno-error=undef -Wno-error=cast-qual ASF_DIR = hw/mcu/microchip/samg55 diff --git a/hw/bsp/stm32l4r5nucleo/stm32l4r5nucleo.c b/hw/bsp/stm32l4r5nucleo/stm32l4r5nucleo.c index bab66b550..8c661b602 100644 --- a/hw/bsp/stm32l4r5nucleo/stm32l4r5nucleo.c +++ b/hw/bsp/stm32l4r5nucleo/stm32l4r5nucleo.c @@ -257,7 +257,7 @@ int board_uart_read(uint8_t* buf, int len) int board_uart_write(void const * buf, int len) { - HAL_UART_Transmit(&UartHandle, (uint8_t*) buf, len, 0xffff); + HAL_UART_Transmit(&UartHandle, (uint8_t*)(uintptr_t) buf, len, 0xffff); return len; } diff --git a/src/portable/sony/cxd56/dcd_cxd56.c b/src/portable/sony/cxd56/dcd_cxd56.c index cfd74330f..1b8a789a4 100644 --- a/src/portable/sony/cxd56/dcd_cxd56.c +++ b/src/portable/sony/cxd56/dcd_cxd56.c @@ -134,7 +134,7 @@ static int _dcd_setup(FAR struct usbdevclass_driver_s *driver, FAR struct usbdev if (usbdcd_driver.setup_processed) { usbdcd_driver.setup_processed = false; - dcd_event_setup_received(0, (uint8_t *) ctrl, true); + dcd_event_setup_received(0, (uint8_t const *) ctrl, true); } else { -- cgit v1.3.1 From 099d3b377fd619e664e60c948e6f73d7276dd81d Mon Sep 17 00:00:00 2001 From: hathach Date: Sun, 17 Oct 2021 17:33:14 +0700 Subject: add volatile to EPx_REGS for -Wcast-qual since gcc does difference between volatile struct and member when casting pointer --- src/portable/dialog/da146xx/dcd_da146xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/portable/dialog/da146xx/dcd_da146xx.c b/src/portable/dialog/da146xx/dcd_da146xx.c index a36165343..b5c656d94 100644 --- a/src/portable/dialog/da146xx/dcd_da146xx.c +++ b/src/portable/dialog/da146xx/dcd_da146xx.c @@ -140,7 +140,7 @@ typedef struct __IOM uint32_t USB_RXC2_REG; /*!< (@ 0x000000DC) Receive Command Register 2 */ __IOM uint32_t USB_RXC3_REG; /*!< (@ 0x000000FC) Receive Command Register 3 */ }; -} EPx_REGS; +} volatile EPx_REGS; #define EP_REGS(first_ep_reg) (EPx_REGS*)(&USB->first_ep_reg) -- cgit v1.3.1 From 826b34a8ac433e089c8522d949def4d8421ca4a2 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 18 Oct 2021 00:13:40 +0700 Subject: enable -Wnull-dereference --- examples/make.mk | 3 ++- hw/bsp/samg55xplained/board.mk | 2 +- src/portable/nuvoton/nuc505/dcd_nuc505.c | 7 ++++++- 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/examples/make.mk b/examples/make.mk index 774625577..793c40aa2 100644 --- a/examples/make.mk +++ b/examples/make.mk @@ -105,7 +105,8 @@ CFLAGS += \ -Wunreachable-code \ -Wcast-align \ -Wcast-function-type \ - -Wcast-qual + -Wcast-qual \ + -Wnull-dereference # Debugging/Optimization ifeq ($(DEBUG), 1) diff --git a/hw/bsp/samg55xplained/board.mk b/hw/bsp/samg55xplained/board.mk index f9396cb30..deff6944c 100644 --- a/hw/bsp/samg55xplained/board.mk +++ b/hw/bsp/samg55xplained/board.mk @@ -12,7 +12,7 @@ CFLAGS += \ -DCFG_TUSB_MCU=OPT_MCU_SAMG # suppress following warnings from mcu driver -CFLAGS += -Wno-error=undef -Wno-error=cast-qual +CFLAGS += -Wno-error=undef -Wno-error=cast-qual -Wno-error=null-dereference ASF_DIR = hw/mcu/microchip/samg55 diff --git a/src/portable/nuvoton/nuc505/dcd_nuc505.c b/src/portable/nuvoton/nuc505/dcd_nuc505.c index ea5a8bea5..11d71a285 100644 --- a/src/portable/nuvoton/nuc505/dcd_nuc505.c +++ b/src/portable/nuvoton/nuc505/dcd_nuc505.c @@ -144,7 +144,9 @@ static USBD_EP_T *ep_entry(uint8_t ep_addr, bool add) enum ep_enum ep_index; struct xfer_ctl_t *xfer; - for (ep_index = PERIPH_EPA, xfer = &xfer_table[PERIPH_EPA], ep = USBD->EP; ep_index < PERIPH_MAX_EP; ep_index++, xfer++, ep++) + for (ep_index = PERIPH_EPA, xfer = &xfer_table[PERIPH_EPA], ep = USBD->EP; + ep_index < PERIPH_MAX_EP; + ep_index++, xfer++, ep++) { if (add) { @@ -396,6 +398,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to /* mine the data for the information we need */ tusb_dir_t dir = tu_edpt_dir(ep_addr); USBD_EP_T *ep = ep_entry(ep_addr, false); + TU_ASSERT(ep); struct xfer_ctl_t *xfer = &xfer_table[ep - USBD->EP]; /* store away the information we'll needing now and later */ @@ -457,6 +460,7 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) if (tu_edpt_number(ep_addr)) { USBD_EP_T *ep = ep_entry(ep_addr, false); + TU_ASSERT(ep, ); ep->EPRSPCTL = (ep->EPRSPCTL & 0xf7) | USBD_EPRSPCTL_HALT_Msk; } else @@ -472,6 +476,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) if (tu_edpt_number(ep_addr)) { USBD_EP_T *ep = ep_entry(ep_addr, false); + TU_ASSERT(ep, ); ep->EPRSPCTL = USBD_EPRSPCTL_TOGGLE_Msk; } } -- cgit v1.3.1 From a7dd5b616cb95a4e395a148fcd2f761ce23a8faf Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 18 Oct 2021 01:11:27 +0700 Subject: fix -Wnull-dereference in midi_device --- src/class/midi/midi_device.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/class/midi/midi_device.c b/src/class/midi/midi_device.c index eb85b668c..edec57846 100644 --- a/src/class/midi/midi_device.c +++ b/src/class/midi/midi_device.c @@ -433,6 +433,7 @@ uint16_t midid_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, uint break; } } + TU_ASSERT(p_midi); p_midi->itf_num = desc_midi->bInterfaceNumber; (void) p_midi->itf_num; -- cgit v1.3.1 From 6fcf4bee8c1540618b5d8d8709ef76cd2aa1c66f Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 18 Oct 2021 11:42:00 +0700 Subject: suppress null-dereference by usbh and lwip --- examples/device/net_lwip_webserver/Makefile | 3 ++ examples/host/cdc_msc_hid/Makefile | 3 +- examples/host/hid_controller/Makefile | 3 +- src/host/usbh.c | 46 +++++++++++++++++------------ 4 files changed, 34 insertions(+), 21 deletions(-) diff --git a/examples/device/net_lwip_webserver/Makefile b/examples/device/net_lwip_webserver/Makefile index c3e0d8899..5649a172a 100644 --- a/examples/device/net_lwip_webserver/Makefile +++ b/examples/device/net_lwip_webserver/Makefile @@ -7,6 +7,9 @@ CFLAGS += \ -DPBUF_POOL_SIZE=2 \ -DTCP_WND=2*TCP_MSS \ -DHTTPD_USE_CUSTOM_FSDATA=0 + +# suppress warning caused by lwip +CFLAGS += -Wno-error=null-dereference INC += \ src \ diff --git a/examples/host/cdc_msc_hid/Makefile b/examples/host/cdc_msc_hid/Makefile index 6a2b4d902..0ad9dd856 100644 --- a/examples/host/cdc_msc_hid/Makefile +++ b/examples/host/cdc_msc_hid/Makefile @@ -9,7 +9,8 @@ INC += \ EXAMPLE_SOURCE += $(wildcard src/*.c) SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE)) -CFLAGS += -Wno-error=cast-align +# TODO: suppress warning caused by host stack +CFLAGS += -Wno-error=cast-align -Wno-error=null-dereference # TinyUSB Host Stack source SRC_C += \ diff --git a/examples/host/hid_controller/Makefile b/examples/host/hid_controller/Makefile index 6f59faeee..2595ec4a7 100644 --- a/examples/host/hid_controller/Makefile +++ b/examples/host/hid_controller/Makefile @@ -12,7 +12,8 @@ EXAMPLE_SOURCE += \ SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE)) -CFLAGS += -Wno-error=cast-align +# TODO: suppress warning caused by host stack +CFLAGS += -Wno-error=cast-align -Wno-error=null-dereference # TinyUSB Host Stack source SRC_C += \ diff --git a/src/host/usbh.c b/src/host/usbh.c index 53e8b9715..a9c2c201f 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -53,13 +53,39 @@ // USBH-HCD common data structure //--------------------------------------------------------------------+ +// device0 struct must be strictly a subset of normal device struct +typedef struct +{ + // port + uint8_t rhport; + uint8_t hub_addr; + uint8_t hub_port; + uint8_t speed; + + volatile struct TU_ATTR_PACKED + { + uint8_t connected : 1; + uint8_t addressed : 1; + uint8_t configured : 1; + uint8_t suspended : 1; + }; +} usbh_dev0_t; + typedef struct { - //------------- port -------------// + // port uint8_t rhport; uint8_t hub_addr; uint8_t hub_port; uint8_t speed; + volatile struct TU_ATTR_PACKED + { + uint8_t connected : 1; + uint8_t addressed : 1; + uint8_t configured : 1; + uint8_t suspended : 1; + }; + //------------- device descriptor -------------// uint16_t vid; uint16_t pid; @@ -73,14 +99,6 @@ typedef struct { // uint8_t interface_count; // bNumInterfaces alias //------------- device -------------// - struct TU_ATTR_PACKED - { - uint8_t connected : 1; - uint8_t addressed : 1; - uint8_t configured : 1; - uint8_t suspended : 1; - }; - volatile uint8_t state; // device state, value from enum tusbh_device_state_t uint8_t itf2drv[16]; // map interface number to driver (0xff is invalid) @@ -103,16 +121,6 @@ typedef struct { } usbh_device_t; -typedef struct -{ - uint8_t rhport; - uint8_t hub_addr; - uint8_t hub_port; - uint8_t speed; - - volatile uint8_t connected; -} usbh_dev0_t; - //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF -- cgit v1.3.1 From 4fd0ee4eef149237aa58b24e843649b16d5ca1dc Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Sat, 16 Oct 2021 15:52:46 +0900 Subject: Implement GET_DEF and GET_LEN handling on Probe/Commit entities of streaming interface --- src/class/video/video_device.c | 86 +++++++++++++++++++++++++++++++++--------- 1 file changed, 68 insertions(+), 18 deletions(-) diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index 91d3b2b72..cd6459a18 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -354,21 +354,25 @@ static bool _update_streaming_parameters(videod_streaming_interface_t const *stm return true; } -/** Set the minimum or the maximum values to variables which need to negotiate with the host +/** Set the minimum, maximum or default values to variables which need to negotiate with the host * - * @param[in] set_max If true, the maximum values is set, otherwise the minimum value is set. + * @param[in] request GET_MAX, GET_MIN or GET_DEF * @param[in,out] param Target */ -static bool _negotiate_streaming_parameters(videod_streaming_interface_t const *stm, bool set_max, +static bool _negotiate_streaming_parameters(videod_streaming_interface_t const *stm, uint_fast8_t request, video_probe_and_commit_control_t *param) { uint_fast8_t const fmtnum = param->bFormatIndex; if (!fmtnum) { - if (set_max) { - tusb_desc_vs_itf_t const *vs = _get_desc_vs(stm); - param->bFormatIndex = vs->stm.bNumFormats; - } else { - param->bFormatIndex = 1; + switch (request) { + case VIDEO_REQUEST_GET_MAX: + param->bFormatIndex = _get_desc_vs(stm)->stm.bNumFormats; + break; + case VIDEO_REQUEST_GET_MIN: + case VIDEO_REQUEST_GET_DEF: + param->bFormatIndex = 1; + break; + default: return false; } /* Set the parameters determined by the format */ param->wKeyFrameRate = 1; @@ -391,7 +395,18 @@ static bool _negotiate_streaming_parameters(videod_streaming_interface_t const * tusb_desc_vs_itf_t const *vs = _get_desc_vs(stm); void const *end = _end_of_streaming_descriptor(vs); tusb_desc_cs_video_fmt_uncompressed_t const *fmt = _find_desc_format(tu_desc_next(vs), end, fmtnum); - frmnum = set_max ? fmt->bNumFrameDescriptors: 1; + switch (request) { + case VIDEO_REQUEST_GET_MAX: + frmnum = fmt->bNumFrameDescriptors; + break; + case VIDEO_REQUEST_GET_MIN: + frmnum = 1; + break; + case VIDEO_REQUEST_GET_DEF: + frmnum = fmt->bDefaultFrameIndex; + break; + default: return false; + } param->bFrameIndex = frmnum; /* Set the parameters determined by the frame */ tusb_desc_cs_video_frm_uncompressed_t const *frm = _find_desc_frame(tu_desc_next(fmt), end, frmnum); @@ -406,11 +421,20 @@ static bool _negotiate_streaming_parameters(videod_streaming_interface_t const * tusb_desc_cs_video_frm_uncompressed_t const *frm = _find_desc_frame(tu_desc_next(fmt), end, frmnum); uint_fast32_t interval; - uint_fast8_t num_intervals = frm->bFrameIntervalType; - if (!num_intervals) { - interval = set_max ? frm->dwFrameInterval[1]: frm->dwFrameInterval[0]; - } else { - interval = set_max ? frm->dwFrameInterval[num_intervals - 1]: frm->dwFrameInterval[0]; + switch (request) { + case VIDEO_REQUEST_GET_MAX: + { + uint_fast8_t num_intervals = frm->bFrameIntervalType; + interval = num_intervals ? frm->dwFrameInterval[num_intervals - 1]: frm->dwFrameInterval[1]; + } + break; + case VIDEO_REQUEST_GET_MIN: + interval = frm->dwFrameInterval[0]; + break; + case VIDEO_REQUEST_GET_DEF: + interval = frm->dwDefaultFrameInterval; + break; + default: return false; } param->dwFrameInterval = interval; uint_fast32_t interval_ms = interval / 10000; @@ -784,7 +808,7 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, video_probe_and_commit_control_t tmp; tmp = *(video_probe_and_commit_control_t*)&self->ep_buf; - TU_VERIFY(_negotiate_streaming_parameters(self, false, &tmp), VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE); + TU_VERIFY(_negotiate_streaming_parameters(self, VIDEO_REQUEST_GET_MIN, &tmp), VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE); TU_VERIFY(tud_control_xfer(rhport, request, &tmp, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN); } return VIDEO_ERROR_NONE; @@ -795,14 +819,31 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN); video_probe_and_commit_control_t tmp; tmp = *(video_probe_and_commit_control_t*)&self->ep_buf; - TU_VERIFY(_negotiate_streaming_parameters(self, true, &tmp), VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE); + TU_VERIFY(_negotiate_streaming_parameters(self, VIDEO_REQUEST_GET_MAX, &tmp), VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE); TU_VERIFY(tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN); } return VIDEO_ERROR_NONE; case VIDEO_REQUEST_GET_RES: return VIDEO_ERROR_UNKNOWN; - case VIDEO_REQUEST_GET_DEF: return VIDEO_ERROR_UNKNOWN; - case VIDEO_REQUEST_GET_LEN: return VIDEO_ERROR_UNKNOWN; + case VIDEO_REQUEST_GET_DEF: + if (stage == CONTROL_STAGE_SETUP) + { + TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN); + video_probe_and_commit_control_t tmp; + tmp = *(video_probe_and_commit_control_t*)&self->ep_buf; + TU_VERIFY(_negotiate_streaming_parameters(self, VIDEO_REQUEST_GET_DEF, &tmp), VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE); + TU_VERIFY(tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN); + } + return VIDEO_ERROR_UNKNOWN; + + case VIDEO_REQUEST_GET_LEN: + if (stage == CONTROL_STAGE_SETUP) + { + TU_VERIFY(2 == request->wLength, VIDEO_ERROR_UNKNOWN); + uint16_t len = sizeof(video_probe_and_commit_control_t); + TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)&len, sizeof(len)), VIDEO_ERROR_UNKNOWN); + } + return VIDEO_ERROR_NONE; case VIDEO_REQUEST_GET_INFO: if (stage == CONTROL_STAGE_SETUP) @@ -838,6 +879,15 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, } return VIDEO_ERROR_NONE; + case VIDEO_REQUEST_GET_LEN: + if (stage == CONTROL_STAGE_SETUP) + { + TU_VERIFY(2 == request->wLength, VIDEO_ERROR_UNKNOWN); + uint16_t len = sizeof(video_probe_and_commit_control_t); + TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)&len, sizeof(len)), VIDEO_ERROR_UNKNOWN); + } + return VIDEO_ERROR_NONE; + case VIDEO_REQUEST_GET_INFO: if (stage == CONTROL_STAGE_SETUP) { -- cgit v1.3.1 From 3485c82246ce17be1ca9649bb36dfc8b1782e593 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 19 Oct 2021 12:35:35 +0700 Subject: update changelog --- docs/info/changelog.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/info/changelog.rst b/docs/info/changelog.rst index 4cb30799c..8eec729d6 100644 --- a/docs/info/changelog.rst +++ b/docs/info/changelog.rst @@ -11,10 +11,10 @@ Device Controller Driver (DCD) ------------------------------ - Getting device stack to pass USB Compliance Verification test (chapter9, HID, MSC). Ports are tested: - nRF, SAMD 21/51, rp2040, stm32f4, Renesas RX, iMXRT, ESP32-S2/3, Kinetic KL25/32 + nRF, SAMD 21/51, rp2040, stm32f4, Renesas RX, iMXRT, ESP32-S2/3, Kinetic KL25/32, DA146xx - Added dcd_edpt_close_all() for switching configuration - [Transdimension] Support dcd_edpt_xfer_fifo() with auto wrap over if fifo buffer is 4K aligned and size is multiple of 4K. -- [Da146xx] Improve vbus, reset, suspend, resume detection, and remote wakeup. +- [DA146xx] Improve vbus, reset, suspend, resume detection, and remote wakeup. Device Stack ------------ -- cgit v1.3.1 From b3b6b4f785de6916ce352c308108242227ce8a47 Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Tue, 19 Oct 2021 21:49:00 +0900 Subject: Update _negotiate_streaming_parameters() to handle some requests --- src/class/video/video_device.c | 74 +++++++++++++++++++++++------------------- 1 file changed, 41 insertions(+), 33 deletions(-) diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index cd6459a18..3cd25628b 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -354,9 +354,9 @@ static bool _update_streaming_parameters(videod_streaming_interface_t const *stm return true; } -/** Set the minimum, maximum or default values to variables which need to negotiate with the host +/** Set the minimum, maximum, default values or resolutions to variables which need to negotiate with the host * - * @param[in] request GET_MAX, GET_MIN or GET_DEF + * @param[in] request GET_MAX, GET_MIN, GET_RES or GET_DEF * @param[in,out] param Target */ static bool _negotiate_streaming_parameters(videod_streaming_interface_t const *stm, uint_fast8_t request, @@ -420,27 +420,56 @@ static bool _negotiate_streaming_parameters(videod_streaming_interface_t const * tusb_desc_cs_video_fmt_uncompressed_t const *fmt = _find_desc_format(tu_desc_next(vs), end, fmtnum); tusb_desc_cs_video_frm_uncompressed_t const *frm = _find_desc_frame(tu_desc_next(fmt), end, frmnum); - uint_fast32_t interval; + uint_fast32_t interval, interval_ms; switch (request) { case VIDEO_REQUEST_GET_MAX: { + uint_fast32_t min_interval, max_interval; uint_fast8_t num_intervals = frm->bFrameIntervalType; - interval = num_intervals ? frm->dwFrameInterval[num_intervals - 1]: frm->dwFrameInterval[1]; + max_interval = num_intervals ? frm->dwFrameInterval[num_intervals - 1]: frm->dwFrameInterval[1]; + min_interval = frm->dwFrameInterval[0]; + interval = max_interval; + interval_ms = min_interval / 10000; } break; case VIDEO_REQUEST_GET_MIN: - interval = frm->dwFrameInterval[0]; + { + uint_fast32_t min_interval, max_interval; + uint_fast8_t num_intervals = frm->bFrameIntervalType; + max_interval = num_intervals ? frm->dwFrameInterval[num_intervals - 1]: frm->dwFrameInterval[1]; + min_interval = frm->dwFrameInterval[0]; + interval = min_interval; + interval_ms = max_interval / 10000; + } break; case VIDEO_REQUEST_GET_DEF: interval = frm->dwDefaultFrameInterval; + interval_ms = interval / 10000; + break; + case VIDEO_REQUEST_GET_RES: + { + uint_fast8_t num_intervals = frm->bFrameIntervalType; + if (num_intervals) { + interval = 0; + } else { + interval = frm->dwFrameInterval[2]; + interval_ms = interval / 10000; + } + } break; default: return false; } param->dwFrameInterval = interval; - uint_fast32_t interval_ms = interval / 10000; - TU_ASSERT(interval_ms); - uint_fast32_t frame_size = param->dwMaxVideoFrameSize; - param->dwMaxPayloadTransferSize = (frame_size + interval_ms - 1) / interval_ms + 2; + if (!interval) { + param->dwMaxPayloadTransferSize = 0; + } else { + uint_fast32_t frame_size = param->dwMaxVideoFrameSize; + if (!interval_ms) { + param->dwMaxPayloadTransferSize = frame_size + 2; + } else { + param->dwMaxPayloadTransferSize = (frame_size + interval_ms - 1) / interval_ms + 2; + } + } return true; } return true; @@ -802,39 +831,18 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, return VIDEO_ERROR_NONE; case VIDEO_REQUEST_GET_MIN: - if (stage == CONTROL_STAGE_SETUP) - { - TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN); - - video_probe_and_commit_control_t tmp; - tmp = *(video_probe_and_commit_control_t*)&self->ep_buf; - TU_VERIFY(_negotiate_streaming_parameters(self, VIDEO_REQUEST_GET_MIN, &tmp), VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE); - TU_VERIFY(tud_control_xfer(rhport, request, &tmp, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN); - } - return VIDEO_ERROR_NONE; - case VIDEO_REQUEST_GET_MAX: - if (stage == CONTROL_STAGE_SETUP) - { - TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN); - video_probe_and_commit_control_t tmp; - tmp = *(video_probe_and_commit_control_t*)&self->ep_buf; - TU_VERIFY(_negotiate_streaming_parameters(self, VIDEO_REQUEST_GET_MAX, &tmp), VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE); - TU_VERIFY(tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN); - } - return VIDEO_ERROR_NONE; - - case VIDEO_REQUEST_GET_RES: return VIDEO_ERROR_UNKNOWN; + case VIDEO_REQUEST_GET_RES: case VIDEO_REQUEST_GET_DEF: if (stage == CONTROL_STAGE_SETUP) { TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN); video_probe_and_commit_control_t tmp; tmp = *(video_probe_and_commit_control_t*)&self->ep_buf; - TU_VERIFY(_negotiate_streaming_parameters(self, VIDEO_REQUEST_GET_DEF, &tmp), VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE); + TU_VERIFY(_negotiate_streaming_parameters(self, request->bRequest, &tmp), VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE); TU_VERIFY(tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN); } - return VIDEO_ERROR_UNKNOWN; + return VIDEO_ERROR_NONE; case VIDEO_REQUEST_GET_LEN: if (stage == CONTROL_STAGE_SETUP) -- cgit v1.3.1 From d42b5604ce6ccdd9c5acba009e6a3d95c27ca573 Mon Sep 17 00:00:00 2001 From: Peter Lawrence <12226419+majbthrd@users.noreply.github.com> Date: Fri, 15 Oct 2021 20:10:19 -0500 Subject: net_lwip_webserver: allow users to enable LWIP_IP6 if desired --- examples/device/net_lwip_webserver/Makefile | 14 ++++++-- examples/device/net_lwip_webserver/src/lwipopts.h | 12 +++++++ examples/device/net_lwip_webserver/src/main.c | 40 ++++++++++++++++------- lib/networking/dhserver.c | 16 ++++----- lib/networking/dhserver.h | 10 +++--- lib/networking/dnserver.c | 2 +- lib/networking/dnserver.h | 2 +- 7 files changed, 66 insertions(+), 30 deletions(-) diff --git a/examples/device/net_lwip_webserver/Makefile b/examples/device/net_lwip_webserver/Makefile index c3e0d8899..03f298cec 100644 --- a/examples/device/net_lwip_webserver/Makefile +++ b/examples/device/net_lwip_webserver/Makefile @@ -4,9 +4,8 @@ include ../../../tools/top.mk include ../../make.mk CFLAGS += \ - -DPBUF_POOL_SIZE=2 \ - -DTCP_WND=2*TCP_MSS \ - -DHTTPD_USE_CUSTOM_FSDATA=0 + -Wno-error=unused-parameter \ + -Wno-error=unused-variable INC += \ src \ @@ -50,6 +49,15 @@ SRC_C += \ lib/lwip/src/core/ipv4/ip4.c \ lib/lwip/src/core/ipv4/ip4_addr.c \ lib/lwip/src/core/ipv4/ip4_frag.c \ + lib/lwip/src/core/ipv6/dhcp6.c \ + lib/lwip/src/core/ipv6/ethip6.c \ + lib/lwip/src/core/ipv6/icmp6.c \ + lib/lwip/src/core/ipv6/inet6.c \ + lib/lwip/src/core/ipv6/ip6.c \ + lib/lwip/src/core/ipv6/ip6_addr.c \ + lib/lwip/src/core/ipv6/ip6_frag.c \ + lib/lwip/src/core/ipv6/mld6.c \ + lib/lwip/src/core/ipv6/nd6.c \ lib/lwip/src/netif/ethernet.c \ lib/lwip/src/netif/slipif.c \ lib/lwip/src/apps/http/httpd.c \ diff --git a/examples/device/net_lwip_webserver/src/lwipopts.h b/examples/device/net_lwip_webserver/src/lwipopts.h index 5a8096f50..a215017c7 100644 --- a/examples/device/net_lwip_webserver/src/lwipopts.h +++ b/examples/device/net_lwip_webserver/src/lwipopts.h @@ -42,11 +42,14 @@ #define LWIP_ICMP 1 #define LWIP_UDP 1 #define LWIP_TCP 1 +#define LWIP_IPV4 1 +#define LWIP_IPV6 0 #define ETH_PAD_SIZE 0 #define LWIP_IP_ACCEPT_UDP_PORT(p) ((p) == PP_NTOHS(67)) #define TCP_MSS (1500 /*mtu*/ - 20 /*iphdr*/ - 20 /*tcphhr*/) #define TCP_SND_BUF (2 * TCP_MSS) +#define TCP_WND (TCP_MSS) #define ETHARP_SUPPORT_STATIC_ENTRIES 1 @@ -56,4 +59,13 @@ #define LWIP_SINGLE_NETIF 1 +#define PBUF_POOL_SIZE 2 + +#define HTTPD_USE_CUSTOM_FSDATA 0 + +#define LWIP_MULTICAST_PING 1 +#define LWIP_BROADCAST_PING 1 +#define LWIP_IPV6_MLD 0 +#define LWIP_IPV6_SEND_ROUTER_SOLICIT 0 + #endif /* __LWIPOPTS_H__ */ diff --git a/examples/device/net_lwip_webserver/src/main.c b/examples/device/net_lwip_webserver/src/main.c index a5bd2153a..30bb3577b 100644 --- a/examples/device/net_lwip_webserver/src/main.c +++ b/examples/device/net_lwip_webserver/src/main.c @@ -50,8 +50,11 @@ try changing the first byte of tud_network_mac_address[] below from 0x02 to 0x00 #include "dnserver.h" #include "lwip/init.h" #include "lwip/timeouts.h" +#include "lwip/ethip6.h" #include "httpd.h" +#define INIT_IP4(a,b,c,d) { PP_HTONL(LWIP_MAKEU32(a,b,c,d)) } + /* lwip context */ static struct netif netif_data; @@ -64,24 +67,24 @@ static struct pbuf *received_frame; const uint8_t tud_network_mac_address[6] = {0x02,0x02,0x84,0x6A,0x96,0x00}; /* network parameters of this MCU */ -static const ip_addr_t ipaddr = IPADDR4_INIT_BYTES(192, 168, 7, 1); -static const ip_addr_t netmask = IPADDR4_INIT_BYTES(255, 255, 255, 0); -static const ip_addr_t gateway = IPADDR4_INIT_BYTES(0, 0, 0, 0); +static const ip4_addr_t ipaddr = INIT_IP4(192, 168, 7, 1); +static const ip4_addr_t netmask = INIT_IP4(255, 255, 255, 0); +static const ip4_addr_t gateway = INIT_IP4(0, 0, 0, 0); /* database IP addresses that can be offered to the host; this must be in RAM to store assigned MAC addresses */ static dhcp_entry_t entries[] = { /* mac ip address lease time */ - { {0}, IPADDR4_INIT_BYTES(192, 168, 7, 2), 24 * 60 * 60 }, - { {0}, IPADDR4_INIT_BYTES(192, 168, 7, 3), 24 * 60 * 60 }, - { {0}, IPADDR4_INIT_BYTES(192, 168, 7, 4), 24 * 60 * 60 }, + { {0}, INIT_IP4(192, 168, 7, 2), 24 * 60 * 60 }, + { {0}, INIT_IP4(192, 168, 7, 3), 24 * 60 * 60 }, + { {0}, INIT_IP4(192, 168, 7, 4), 24 * 60 * 60 }, }; static const dhcp_config_t dhcp_config = { - .router = IPADDR4_INIT_BYTES(0, 0, 0, 0), /* router address (if any) */ + .router = INIT_IP4(0, 0, 0, 0), /* router address (if any) */ .port = 67, /* listen port */ - .dns = IPADDR4_INIT_BYTES(192, 168, 7, 1), /* dns server (if any) */ + .dns = INIT_IP4(192, 168, 7, 1), /* dns server (if any) */ "usb", /* dns suffix */ TU_ARRAY_SIZE(entries), /* num entry */ entries /* entries */ @@ -108,11 +111,18 @@ static err_t linkoutput_fn(struct netif *netif, struct pbuf *p) } } -static err_t output_fn(struct netif *netif, struct pbuf *p, const ip_addr_t *addr) +static err_t ip4_output_fn(struct netif *netif, struct pbuf *p, const ip4_addr_t *addr) { return etharp_output(netif, p, addr); } +#if LWIP_IPV6 +static err_t ip6_output_fn(struct netif *netif, struct pbuf *p, const ip6_addr_t *addr) +{ + return ethip6_output(netif, p, addr); +} +#endif + static err_t netif_init_cb(struct netif *netif) { LWIP_ASSERT("netif != NULL", (netif != NULL)); @@ -122,7 +132,10 @@ static err_t netif_init_cb(struct netif *netif) netif->name[0] = 'E'; netif->name[1] = 'X'; netif->linkoutput = linkoutput_fn; - netif->output = output_fn; + netif->output = ip4_output_fn; +#if LWIP_IPV6 + netif->output_ip6 = ip6_output_fn; +#endif return ERR_OK; } @@ -138,11 +151,14 @@ static void init_lwip(void) netif->hwaddr[5] ^= 0x01; netif = netif_add(netif, &ipaddr, &netmask, &gateway, NULL, netif_init_cb, ip_input); +#if LWIP_IPV6 + netif_create_ip6_linklocal_address(netif, 1); +#endif netif_set_default(netif); } /* handle any DNS requests from dns-server */ -bool dns_query_proc(const char *name, ip_addr_t *addr) +bool dns_query_proc(const char *name, ip4_addr_t *addr) { if (0 == strcmp(name, "tiny.usb")) { @@ -218,7 +234,7 @@ int main(void) init_lwip(); while (!netif_is_up(&netif_data)); while (dhserv_init(&dhcp_config) != ERR_OK); - while (dnserv_init(&ipaddr, 53, dns_query_proc) != ERR_OK); + while (dnserv_init(IP_ADDR_ANY, 53, dns_query_proc) != ERR_OK); httpd_init(); while (1) diff --git a/lib/networking/dhserver.c b/lib/networking/dhserver.c index 9287858ea..590739236 100644 --- a/lib/networking/dhserver.c +++ b/lib/networking/dhserver.c @@ -96,19 +96,19 @@ static const dhcp_config_t *config = NULL; char magic_cookie[] = {0x63,0x82,0x53,0x63}; -static ip_addr_t get_ip(const uint8_t *pnt) +static ip4_addr_t get_ip(const uint8_t *pnt) { - ip_addr_t result; + ip4_addr_t result; memcpy(&result, pnt, sizeof(result)); return result; } -static void set_ip(uint8_t *pnt, ip_addr_t value) +static void set_ip(uint8_t *pnt, ip4_addr_t value) { memcpy(pnt, &value.addr, sizeof(value.addr)); } -static dhcp_entry_t *entry_by_ip(ip_addr_t ip) +static dhcp_entry_t *entry_by_ip(ip4_addr_t ip) { int i; for (i = 0; i < config->num_entry; i++) @@ -162,11 +162,11 @@ uint8_t *find_dhcp_option(uint8_t *attrs, int size, uint8_t attr) int fill_options(void *dest, uint8_t msg_type, const char *domain, - ip_addr_t dns, + ip4_addr_t dns, int lease_time, - ip_addr_t serverid, - ip_addr_t router, - ip_addr_t subnet) + ip4_addr_t serverid, + ip4_addr_t router, + ip4_addr_t subnet) { uint8_t *ptr = (uint8_t *)dest; /* ACK message type */ diff --git a/lib/networking/dhserver.h b/lib/networking/dhserver.h index 0d22461c7..2a0b15854 100644 --- a/lib/networking/dhserver.h +++ b/lib/networking/dhserver.h @@ -41,16 +41,16 @@ typedef struct dhcp_entry { - uint8_t mac[6]; - ip_addr_t addr; - uint32_t lease; + uint8_t mac[6]; + ip4_addr_t addr; + uint32_t lease; } dhcp_entry_t; typedef struct dhcp_config { - ip_addr_t router; + ip4_addr_t router; uint16_t port; - ip_addr_t dns; + ip4_addr_t dns; const char *domain; int num_entry; dhcp_entry_t *entries; diff --git a/lib/networking/dnserver.c b/lib/networking/dnserver.c index 6df0bd0c4..e4e7c3492 100644 --- a/lib/networking/dnserver.c +++ b/lib/networking/dnserver.c @@ -136,7 +136,7 @@ static void udp_recv_proc(void *arg, struct udp_pcb *upcb, struct pbuf *p, const dns_header_t *header; static dns_query_t query; struct pbuf *out; - ip_addr_t host_addr; + ip4_addr_t host_addr; dns_answer_t *answer; (void)arg; diff --git a/lib/networking/dnserver.h b/lib/networking/dnserver.h index 130991f5f..a062e3aa7 100644 --- a/lib/networking/dnserver.h +++ b/lib/networking/dnserver.h @@ -39,7 +39,7 @@ #include "lwip/udp.h" #include "netif/etharp.h" -typedef bool (*dns_query_proc_t)(const char *name, ip_addr_t *addr); +typedef bool (*dns_query_proc_t)(const char *name, ip4_addr_t *addr); err_t dnserv_init(const ip_addr_t *bind, uint16_t port, dns_query_proc_t query_proc); void dnserv_free(void); -- cgit v1.3.1 From 5e437ee1861363e6b02facc5ab814abd67173680 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 22 Oct 2021 15:37:34 +0700 Subject: pi cm4 enumerated as full speed device --- examples/device/cdc_msc/src/tusb_config.h | 3 +- src/common/tusb_common.h | 4 +- src/portable/broadcom/synopsys/dcd_synopsys.c | 59 +++++++++++++++++++++--- src/portable/broadcom/synopsys/synopsys_common.h | 15 +++++- 4 files changed, 69 insertions(+), 12 deletions(-) diff --git a/examples/device/cdc_msc/src/tusb_config.h b/examples/device/cdc_msc/src/tusb_config.h index bf6af06bc..a3802f536 100644 --- a/examples/device/cdc_msc/src/tusb_config.h +++ b/examples/device/cdc_msc/src/tusb_config.h @@ -48,7 +48,8 @@ // Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed #ifndef BOARD_DEVICE_RHPORT_SPEED #if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \ - CFG_TUSB_MCU == OPT_MCU_NUC505 || CFG_TUSB_MCU == OPT_MCU_CXD56 || CFG_TUSB_MCU == OPT_MCU_SAMX7X) + CFG_TUSB_MCU == OPT_MCU_NUC505 || CFG_TUSB_MCU == OPT_MCU_CXD56 || CFG_TUSB_MCU == OPT_MCU_SAMX7X || \ + CFG_TUSB_MCU == OPT_MCU_BCM2711) #define BOARD_DEVICE_RHPORT_SPEED OPT_MODE_HIGH_SPEED #else #define BOARD_DEVICE_RHPORT_SPEED OPT_MODE_FULL_SPEED diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h index 1899b35cc..9614c12cf 100644 --- a/src/common/tusb_common.h +++ b/src/common/tusb_common.h @@ -337,8 +337,8 @@ void tu_print_var(uint8_t const* buf, uint32_t bufsize) #define TU_LOG1 tu_printf #define TU_LOG1_MEM tu_print_mem #define TU_LOG1_VAR(_x) tu_print_var((uint8_t const*)(_x), sizeof(*(_x))) -#define TU_LOG1_INT(_x) tu_printf(#_x " = %ld\r\n", (uint32_t) (_x) ) -#define TU_LOG1_HEX(_x) tu_printf(#_x " = %lX\r\n", (uint32_t) (_x) ) +#define TU_LOG1_INT(_x) tu_printf(#_x " = %ld\r\n", (unsigned long) (_x) ) +#define TU_LOG1_HEX(_x) tu_printf(#_x " = %lX\r\n", (unsigned long) (_x) ) // Log Level 2: Warn #if CFG_TUSB_DEBUG >= 2 diff --git a/src/portable/broadcom/synopsys/dcd_synopsys.c b/src/portable/broadcom/synopsys/dcd_synopsys.c index ff4ab9fb6..e70e5d4f3 100644 --- a/src/portable/broadcom/synopsys/dcd_synopsys.c +++ b/src/portable/broadcom/synopsys/dcd_synopsys.c @@ -110,6 +110,8 @@ #include "device/dcd.h" +TU_VERIFY_STATIC(sizeof(USB_OTG_GlobalTypeDef) == 0x140, "size is incorrect"); + //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ @@ -340,7 +342,10 @@ static void set_speed(uint8_t rhport, tusb_speed_t speed) dev->DCFG |= (bitvalue << USB_OTG_DCFG_DSPD_Pos); } -#if defined(USB_HS_PHYC) +#if 0 +// From CM4IO xtal to usb hub, may not be correct +#define HSE_VALUE 24000000 + static bool USB_HS_PHYCInit(void) { USB_HS_PHYC_GlobalTypeDef *usb_hs_phyc = (USB_HS_PHYC_GlobalTypeDef*) USB_HS_PHYC_CONTROLLER_BASE; @@ -435,6 +440,7 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c /* Controller API *------------------------------------------------------------------*/ +TU_ATTR_UNUSED static void reset_core(USB_OTG_GlobalTypeDef * usb_otg) { while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0) {} @@ -456,6 +462,46 @@ void dcd_init (uint8_t rhport) USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport); +#if 1 + // No VBUS sense + usb_otg->GCCFG &= ~(1UL << 21); // USB_OTG_GCCFG_VBDEN + + // B-peripheral session valid override enable + usb_otg->GOTGCTL |= (1UL << 6); // USB_OTG_GOTGCTL_BVALOEN + usb_otg->GOTGCTL |= (1UL << 7); // USB_OTG_GOTGCTL_BVALOVAL + + // Force device mode + usb_otg->GUSBCFG &= ~USB_OTG_GUSBCFG_FHMOD; + usb_otg->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; + + // deactivate internal PHY + usb_otg->GCCFG &= ~USB_OTG_GCCFG_PWRDWN; + + // Init The UTMI Interface + usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL); + + // Select default internal VBUS Indicator and Drive for ULPI + usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); + + // Select UTMI Interface + usb_otg->GUSBCFG &= ~(1UL << 4); // USB_OTG_GUSBCFG_ULPI_UTMI_SEL + usb_otg->GCCFG |= (1UL << 32); // USB_OTG_GCCFG_PHYHSEN + + // Enables control of a High Speed USB PHY + //USB_HS_PHYCInit(); + + // Reset core after selecting PHY + // Wait AHB IDLE, reset then wait until it is cleared +// while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U) {} +// usb_otg->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; +// while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST) {} + + reset_core(usb_otg); + + // Restart PHY clock + *((volatile uint32_t *)(RHPORT_REGS_BASE + USB_OTG_PCGCCTL_BASE)) = 0; + +#else // ReadBackReg(&Core->Usb); // Core->Usb.UlpiDriveExternalVbus = 0; @@ -470,7 +516,7 @@ void dcd_init (uint8_t rhport) // LOG_DEBUG("HCD: Interface: UTMI+.\n"); // Core->Usb.PhyInterface = false; - // HcdReset(); + // HcdReset(); TU_LOG2("init phy\r\n"); usb_otg->GUSBCFG |= (1 << 4); // bit four sets UTMI+ mode usb_otg->GUSBCFG &= ~(1 << 3); // bit three disables phy interface @@ -486,12 +532,14 @@ void dcd_init (uint8_t rhport) // Core->Ahb.DmaRemainderMode = Incremental; usb_otg->GAHBCFG &= ~(1 << 23); // Remainder mode usb_otg->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN; - + // LOG_DEBUG("HCD: HNP/SRP configuration: HNP, SRP.\n"); // Core->Usb.HnpCapable = true; // Core->Usb.SrpCapable = true; usb_otg->GUSBCFG |= USB_OTG_GUSBCFG_SRPCAP | USB_OTG_GUSBCFG_HNPCAP; +#endif + // Clear all interrupts usb_otg->GINTSTS |= usb_otg->GINTSTS; @@ -506,12 +554,9 @@ void dcd_init (uint8_t rhport) // (non zero-length packet), send STALL back and discard. dev->DCFG |= USB_OTG_DCFG_NZLSOHSK; - #if TUD_OPT_HIGH_SPEED set_speed(rhport, TUSB_SPEED_HIGH); - #else - set_speed(rhport, TUSB_SPEED_FULL); - #endif + // TODO internal phy (full speed) usb_otg->GCCFG |= USB_OTG_GCCFG_PWRDWN; usb_otg->GINTMSK |= USB_OTG_GINTMSK_USBRST | USB_OTG_GINTMSK_ENUMDNEM | diff --git a/src/portable/broadcom/synopsys/synopsys_common.h b/src/portable/broadcom/synopsys/synopsys_common.h index 6f0602fe9..2ec6f4487 100644 --- a/src/portable/broadcom/synopsys/synopsys_common.h +++ b/src/portable/broadcom/synopsys/synopsys_common.h @@ -60,12 +60,23 @@ typedef struct __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset: 02Ch */ uint32_t Reserved30[2]; /*!< Reserved 030h*/ __IO uint32_t GCCFG; /*!< General Purpose IO Register Address offset: 038h */ - __IO uint32_t CID; /*!< User ID Register Address offset: 03Ch */ - uint32_t Reserved40[48]; /*!< Reserved 040h-0FFh */ + __IO uint32_t CID; /*!< User ID Register 03Ch */ + __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/ + __IO uint32_t GHWCFG1; /* User HW config1 044h*/ + __IO uint32_t GHWCFG2; /* User HW config2 048h*/ + __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */ + uint32_t Reserved6; /*!< Reserved 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */ + uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg Address offset: 100h */ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO Address offset: 0x104 */ } USB_OTG_GlobalTypeDef; + + /** * @brief __device_Registers */ -- cgit v1.3.1 From 35b62810c3a4b8e2924109905334f054425f16ba Mon Sep 17 00:00:00 2001 From: Scott Shawcroft Date: Fri, 22 Oct 2021 09:00:09 -0700 Subject: Update submodule --- cortex-a.py | 157 ----------------------- hw/mcu/broadcom | 2 +- src/portable/broadcom/synopsys/dcd_synopsys.c | 10 +- src/portable/broadcom/synopsys/synopsys_common.h | 6 +- 4 files changed, 10 insertions(+), 165 deletions(-) delete mode 100644 cortex-a.py diff --git a/cortex-a.py b/cortex-a.py deleted file mode 100644 index 9de16bae9..000000000 --- a/cortex-a.py +++ /dev/null @@ -1,157 +0,0 @@ -class Armv8AException(gdb.Command): - def __init__ (self): - super (Armv8AException, self).__init__ ("armv8a-exception", gdb.COMMAND_USER) - - def print_data_abort(self, frame, iss): - isv = (iss >> 23) & 0x1 - sas = (iss >> 21) & 0x3 - sse = (iss >> 20) & 0x1 - srt = (iss >> 15) & 0x1f - sf = (iss >> 14) & 0x1 - ar = (iss >> 13) & 0x1 - vncr = (iss >> 12) & 0x1 - _set = (iss >> 10) & 0x3 - fnv = (iss >> 9) & 0x1 - ea = (iss >> 8) & 0x1 - cm = (iss >> 7) & 0x1 - s1ptw = (iss >> 6) & 0x1 - wnr = (iss >> 5) & 0x1 - dfsc = iss & 0x1f - if isv: - # print("isv valid", sas, sse, srt, sf, ar) - access_sizes = ("Byte", "Halfword", "Word", "Doubleword") - print("Access size:", access_sizes[sas]) - print("Sign extended:", "Yes" if sse else "No") - print("Register:", hex(srt), "64-bit" if sf else "32-bit") - print("Acquire/Release:", "Yes" if ar else "No") - if dfsc == 0b010000: - print("Not on translation table walk") - if not fnv: - value = int(frame.read_register("FAR_EL2")) - print("FAR", hex(value)) - elif dfsc == 0b000101: - print("translation fault level 1") - elif dfsc == 0b010001: - print("tag check fault") - elif dfsc == 0b100001: - print("alignment fault") - else: - print(bin(dfsc)) - print(vncr, _set, fnv, ea, cm, s1ptw, wnr, dfsc) - - def print_instruction_abort(self, frame, iss): - _set = (iss >> 10) & 0x3 - fnv = (iss >> 9) & 0x1 - ea = (iss >> 8) & 0x1 - s1ptw = (iss >> 6) & 0x1 - ifsc = iss & 0x1f - if ifsc == 0b010000: - print("Not on translation table walk") - if not fnv: - value = int(frame.read_register("FAR_EL2")) - print("FAR", hex(value)) - elif ifsc == 0b00101: - print("translation fault level 1") - elif ifsc == 0b01001: - print("access flag fault level 1") - # elif dfsc == 0b100001: - # print("alignment fault") - else: - print(bin(ifsc)) - - def invoke (self, arg, from_tty): - frame = gdb.selected_frame() - value = int(frame.read_register("ESR_EL2")) - if value == 0: - return None - iss2 = (value >> 32) & 0x1ff - ec = (value >> 26) & 0x3ff - il = (value >> 25) & 0x1 - iss = value & 0xffffff - if ec == 0b000000: - print("Unknown fault") - elif ec == 0b000001: - print("Trapped WF*") - elif ec == 0b000011: - print("Trapped MCR or MRC") - elif ec == 0b000100: - print("Trapped MCRR or MRRC") - elif ec == 0b000101: - print("Trapped MCR or MRC") - elif ec == 0b000110: - print("Trapped LDC or STC") - elif ec == 0b000111: - print("Trapped SIMD") - elif ec == 0b001000: - print("Trapped VMRS") - elif ec == 0b001001: - print("Trapped pointer authentication") - elif ec == 0b001010: - print("Trapped LD64B or ST64B*") - elif ec == 0b001100: - print("Trapped MRRC") - elif ec == 0b001101: - print("Branch target exception") - elif ec == 0b001110: - print("Illegal execution state") - elif ec == 0b010001: - print("SVC instruction") - elif ec == 0b010010: - print("HVC instruction") - elif ec == 0b010011: - print("SMC instruction") - elif ec == 0b010101: - print("SVC instruction") - elif ec == 0b010110: - print("HVC instruction") - elif ec == 0b010111: - print("SMC instruction") - elif ec == 0b011000: - print("Trapped MRS, MRS or system instruction") - elif ec == 0b011001: - print("Trapped SVE") - elif ec == 0b011010: - print("Trapped ERET") - elif ec == 0b011100: - print("Failed pointer authentication") - elif ec == 0b100000: - print("Instruction abort from lower level") - elif ec == 0b100001: - print("Instruction abort from same level") - self.print_instruction_abort(frame, iss) - elif ec == 0b100010: - print("PC alignment failure") - elif ec == 0b100100: - print("Data abort from lower level") - elif ec == 0b100101: - print("Data abort from same level") - self.print_data_abort(frame, iss) - elif ec == 0b100110: - print("SP alignment fault") - elif ec == 0b101000: - print("32-bit floating point exception") - elif ec == 0b101100: - print("64-bit floating point exception") - elif ec == 0b101111: - print("SError interrupt") - elif ec == 0b110000: - print("Breakpoint from lower level") - elif ec == 0b110001: - print("Breakpoint from same level") - elif ec == 0b110010: - print("Software step from lower level") - elif ec == 0b110011: - print("Software step from same level") - elif ec == 0b110100: - print ("Watch point from same level") - elif ec == 0b110101: - print("Watch point from lower level") - elif ec == 0b111000: - print("Breakpoint in aarch32 mode") - elif ec == 0b111010: - print("Vector catch in aarch32") - elif ec == 0b111100: - print("Brk instruction in aarch64") - print(hex(int(value)), iss2, bin(ec), il, iss) - -Armv8AException() diff --git a/hw/mcu/broadcom b/hw/mcu/broadcom index e5343acda..7a8f4b747 160000 --- a/hw/mcu/broadcom +++ b/hw/mcu/broadcom @@ -1 +1 @@ -Subproject commit e5343acdad77b8cf4a8d09b732a11ecef17d148a +Subproject commit 7a8f4b7471ad4aad2e808b3a4cc88b4c23b529f2 diff --git a/src/portable/broadcom/synopsys/dcd_synopsys.c b/src/portable/broadcom/synopsys/dcd_synopsys.c index e70e5d4f3..32cfd6d2a 100644 --- a/src/portable/broadcom/synopsys/dcd_synopsys.c +++ b/src/portable/broadcom/synopsys/dcd_synopsys.c @@ -31,6 +31,8 @@ #include "synopsys_common.h" +#include "broadcom/interrupts.h" + // Since TinyUSB doesn't use SOF for now, and this interrupt too often (1ms interval) // We disable SOF for now until needed later on #define USE_SOF 0 @@ -116,10 +118,10 @@ TU_VERIFY_STATIC(sizeof(USB_OTG_GlobalTypeDef) == 0x140, "size is incorrect"); // MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ -#define RHPORT_REGS_BASE 0xfe980000 +#define RHPORT_REGS_BASE USB_OTG_GLOBAL_BASE #define GLOBAL_BASE(_port) ((USB_OTG_GlobalTypeDef*) RHPORT_REGS_BASE) -#define DEVICE_BASE(_port) (USB_OTG_DeviceTypeDef *) (RHPORT_REGS_BASE + USB_OTG_DEVICE_BASE) +#define DEVICE_BASE(_port) (USB_OTG_DeviceTypeDef *) (USB_OTG_DEVICE_BASE) #define OUT_EP_BASE(_port) (USB_OTG_OUTEndpointTypeDef *) (RHPORT_REGS_BASE + USB_OTG_OUT_ENDPOINT_BASE) #define IN_EP_BASE(_port) (USB_OTG_INEndpointTypeDef *) (RHPORT_REGS_BASE + USB_OTG_IN_ENDPOINT_BASE) #define FIFO_BASE(_port, _x) ((volatile uint32_t *) (RHPORT_REGS_BASE + USB_OTG_FIFO_BASE + (_x) * USB_OTG_FIFO_SIZE)) @@ -572,13 +574,13 @@ void dcd_init (uint8_t rhport) void dcd_int_enable (uint8_t rhport) { (void) rhport; - // NVIC_EnableIRQ(RHPORT_IRQn); + // BP_EnableIRQ(USB_IRQn); } void dcd_int_disable (uint8_t rhport) { (void) rhport; - // NVIC_DisableIRQ(RHPORT_IRQn); + // BP_DisableIRQ(USB_IRQn); } void dcd_set_address (uint8_t rhport, uint8_t dev_addr) diff --git a/src/portable/broadcom/synopsys/synopsys_common.h b/src/portable/broadcom/synopsys/synopsys_common.h index 2ec6f4487..81ce3b4a9 100644 --- a/src/portable/broadcom/synopsys/synopsys_common.h +++ b/src/portable/broadcom/synopsys/synopsys_common.h @@ -169,12 +169,12 @@ typedef struct /*!< USB registers base address */ #define USB_OTG_FS_PERIPH_BASE 0x50000000UL -#define USB_OTG_GLOBAL_BASE 0x00000000UL -#define USB_OTG_DEVICE_BASE 0x00000800UL +// #define USB_OTG_GLOBAL_BASE 0x00000000UL +// #define USB_OTG_DEVICE_BASE 0x00000800UL #define USB_OTG_IN_ENDPOINT_BASE 0x00000900UL #define USB_OTG_OUT_ENDPOINT_BASE 0x00000B00UL #define USB_OTG_EP_REG_SIZE 0x00000020UL -#define USB_OTG_HOST_BASE 0x00000400UL +// #define USB_OTG_HOST_BASE 0x00000400UL #define USB_OTG_HOST_PORT_BASE 0x00000440UL #define USB_OTG_HOST_CHANNEL_BASE 0x00000500UL #define USB_OTG_HOST_CHANNEL_SIZE 0x00000020UL -- cgit v1.3.1 From 2ef200003d06f8e3f19e713cfbc38f474491d4d8 Mon Sep 17 00:00:00 2001 From: Scott Shawcroft Date: Fri, 22 Oct 2021 09:31:24 -0700 Subject: Update broadcom library --- hw/mcu/broadcom | 2 +- src/portable/broadcom/synopsys/dcd_synopsys.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/mcu/broadcom b/hw/mcu/broadcom index 7a8f4b747..55cd6f798 160000 --- a/hw/mcu/broadcom +++ b/hw/mcu/broadcom @@ -1 +1 @@ -Subproject commit 7a8f4b7471ad4aad2e808b3a4cc88b4c23b529f2 +Subproject commit 55cd6f798a45cac905d7bf81baa2bcbf7de7c42e diff --git a/src/portable/broadcom/synopsys/dcd_synopsys.c b/src/portable/broadcom/synopsys/dcd_synopsys.c index 32cfd6d2a..87150f683 100644 --- a/src/portable/broadcom/synopsys/dcd_synopsys.c +++ b/src/portable/broadcom/synopsys/dcd_synopsys.c @@ -574,13 +574,13 @@ void dcd_init (uint8_t rhport) void dcd_int_enable (uint8_t rhport) { (void) rhport; - // BP_EnableIRQ(USB_IRQn); + BP_EnableIRQ(USB_IRQn); } void dcd_int_disable (uint8_t rhport) { (void) rhport; - // BP_DisableIRQ(USB_IRQn); + BP_DisableIRQ(USB_IRQn); } void dcd_set_address (uint8_t rhport, uint8_t dev_addr) -- cgit v1.3.1 From 07c74c76d0bf420c63757af2b66838090c2fd9d3 Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Sat, 23 Oct 2021 13:43:46 -0400 Subject: msp430x5xx: Set base of transmit_packet buffer earlier to avoid incrementing past unsent data. --- src/portable/ti/msp430x5xx/dcd_msp430x5xx.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c index ee85f0a77..6830fd1fa 100644 --- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c +++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c @@ -547,6 +547,7 @@ static void transmit_packet(uint8_t ep_num) } // Then actually commit to transmit a packet. + uint8_t * base = (xfer->buffer + xfer->queued_len); uint16_t remaining = xfer->total_len - xfer->queued_len; uint8_t xfer_size = (xfer->max_size < xfer->total_len) ? xfer->max_size : remaining; @@ -560,7 +561,6 @@ static void transmit_packet(uint8_t ep_num) if(ep_num == 0) { volatile uint8_t * ep0in_buf = &USBIEP0BUF; - uint8_t * base = (xfer->buffer + xfer->queued_len); for(uint16_t i = 0; i < xfer_size; i++) { ep0in_buf[i] = base[i]; @@ -582,7 +582,6 @@ static void transmit_packet(uint8_t ep_num) else #endif { - uint8_t * base = (xfer->buffer + xfer->queued_len); for(int i = 0; i < xfer_size; i++) { ep_buf[i] = base[i]; -- cgit v1.3.1 From 6f5b197a98545c70efeeb4adcad0d41a3d30a57c Mon Sep 17 00:00:00 2001 From: hathach Date: Sun, 24 Oct 2021 08:44:58 +0700 Subject: indent --- src/class/usbtmc/usbtmc_device.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c index 86495e3fa..6c916d2f3 100644 --- a/src/class/usbtmc/usbtmc_device.c +++ b/src/class/usbtmc/usbtmc_device.c @@ -522,21 +522,21 @@ bool usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint case STATE_TX_INITIATED: if(usbtmc_state.transfer_size_remaining >=sizeof(usbtmc_state.ep_bulk_in_buf)) { - // FIXME! This removes const below! - TU_VERIFY( usbd_edpt_xfer(rhport, usbtmc_state.ep_bulk_in, - (void*)(uintptr_t) usbtmc_state.devInBuffer, sizeof(usbtmc_state.ep_bulk_in_buf))); - usbtmc_state.devInBuffer += sizeof(usbtmc_state.ep_bulk_in_buf); - usbtmc_state.transfer_size_remaining -= sizeof(usbtmc_state.ep_bulk_in_buf); - usbtmc_state.transfer_size_sent += sizeof(usbtmc_state.ep_bulk_in_buf); + // FIXME! This removes const below! + TU_VERIFY( usbd_edpt_xfer(rhport, usbtmc_state.ep_bulk_in, + (void*)(uintptr_t) usbtmc_state.devInBuffer, sizeof(usbtmc_state.ep_bulk_in_buf))); + usbtmc_state.devInBuffer += sizeof(usbtmc_state.ep_bulk_in_buf); + usbtmc_state.transfer_size_remaining -= sizeof(usbtmc_state.ep_bulk_in_buf); + usbtmc_state.transfer_size_sent += sizeof(usbtmc_state.ep_bulk_in_buf); } else // last packet { - size_t packetLen = usbtmc_state.transfer_size_remaining; - memcpy(usbtmc_state.ep_bulk_in_buf, usbtmc_state.devInBuffer, usbtmc_state.transfer_size_remaining); - usbtmc_state.transfer_size_sent += sizeof(usbtmc_state.transfer_size_remaining); - usbtmc_state.transfer_size_remaining = 0; - usbtmc_state.devInBuffer = NULL; - TU_VERIFY( usbd_edpt_xfer(rhport, usbtmc_state.ep_bulk_in, usbtmc_state.ep_bulk_in_buf,(uint16_t)packetLen)); + size_t packetLen = usbtmc_state.transfer_size_remaining; + memcpy(usbtmc_state.ep_bulk_in_buf, usbtmc_state.devInBuffer, usbtmc_state.transfer_size_remaining); + usbtmc_state.transfer_size_sent += sizeof(usbtmc_state.transfer_size_remaining); + usbtmc_state.transfer_size_remaining = 0; + usbtmc_state.devInBuffer = NULL; + TU_VERIFY( usbd_edpt_xfer(rhport, usbtmc_state.ep_bulk_in, usbtmc_state.ep_bulk_in_buf, (uint16_t)packetLen) ); if(((packetLen % USBTMCD_MAX_PACKET_SIZE) != 0) || (packetLen == 0 )) { usbtmc_state.state = STATE_TX_SHORTED; -- cgit v1.3.1 From 5af989384bd95dbf16f824bcc48e56f3ea283080 Mon Sep 17 00:00:00 2001 From: hathach Date: Sun, 24 Oct 2021 13:11:21 +0700 Subject: remove ep descriptor wMaxPacketSize bitfield due to endian issue --- CONTRIBUTORS.rst | 2 +- src/class/audio/audio_device.c | 15 +++++----- src/class/bth/bth_device.c | 8 ++--- src/class/hid/hid_host.c | 2 +- src/class/usbtmc/usbtmc_device.c | 2 +- src/class/video/video_device.c | 6 ++-- src/common/tusb_common.h | 21 ++++++------- src/common/tusb_types.h | 35 ++++++++++------------ src/host/usbh.c | 2 +- src/portable/dialog/da146xx/dcd_da146xx.c | 2 +- src/portable/ehci/ehci.c | 2 +- src/portable/espressif/esp32sx/dcd_esp32sx.c | 7 ++--- src/portable/microchip/samd/dcd_samd.c | 4 +-- src/portable/microchip/samg/dcd_samg.c | 2 +- src/portable/microchip/samx7x/dcd_samx7x.c | 2 +- src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c | 2 +- src/portable/nordic/nrf5x/dcd_nrf5x.c | 2 +- src/portable/nuvoton/nuc120/dcd_nuc120.c | 2 +- src/portable/nuvoton/nuc121/dcd_nuc121.c | 2 +- src/portable/nuvoton/nuc505/dcd_nuc505.c | 2 +- src/portable/nxp/khci/dcd_khci.c | 2 +- src/portable/nxp/lpc17_40/dcd_lpc17_40.c | 5 ++-- .../nxp/transdimension/dcd_transdimension.c | 2 +- src/portable/ohci/ohci.c | 2 +- src/portable/raspberrypi/rp2040/dcd_rp2040.c | 2 +- src/portable/raspberrypi/rp2040/hcd_rp2040.c | 2 +- src/portable/renesas/usba/dcd_usba.c | 2 +- src/portable/silabs/efm32/dcd_efm32.c | 7 ++--- src/portable/sony/cxd56/dcd_cxd56.c | 8 +++-- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 12 ++++---- src/portable/st/synopsys/dcd_synopsys.c | 8 ++--- src/portable/ti/msp430x5xx/dcd_msp430x5xx.c | 4 +-- src/tusb.c | 2 +- 33 files changed, 90 insertions(+), 90 deletions(-) diff --git a/CONTRIBUTORS.rst b/CONTRIBUTORS.rst index 55a291222..e3186f086 100644 --- a/CONTRIBUTORS.rst +++ b/CONTRIBUTORS.rst @@ -110,7 +110,7 @@ Notable contributors `Rafael Silva `__ ---------------------------------------------- -- Add new DCD port for Silabs EFM32GG12 with SLTB009A board +- Port DCD Synopsys to support Silabs EFM32GG12 with SLTB009A board - Rewrite documentation in rst and setup for readthedocs diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c index e16771cd3..28b1c1a7c 100644 --- a/src/class/audio/audio_device.c +++ b/src/class/audio/audio_device.c @@ -1569,20 +1569,21 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const * { if (tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT) { - TU_ASSERT(usbd_edpt_open(rhport, (tusb_desc_endpoint_t const *)p_desc)); + tusb_desc_endpoint_t const* desc_ep = (tusb_desc_endpoint_t const *) p_desc; + TU_ASSERT(usbd_edpt_open(rhport, desc_ep)); - uint8_t ep_addr = ((tusb_desc_endpoint_t const *) p_desc)->bEndpointAddress; + uint8_t const ep_addr = desc_ep->bEndpointAddress; //TODO: We need to set EP non busy since this is not taken care of right now in ep_close() - THIS IS A WORKAROUND! usbd_edpt_clear_stall(rhport, ep_addr); #if CFG_TUD_AUDIO_ENABLE_EP_IN - if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN && ((tusb_desc_endpoint_t const *) p_desc)->bmAttributes.usage == 0x00) // Check if usage is data EP + if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN && desc_ep->bmAttributes.usage == 0x00) // Check if usage is data EP { // Save address audio->ep_in = ep_addr; audio->ep_in_as_intf_num = itf; - audio->ep_in_sz = ((tusb_desc_endpoint_t const *) p_desc)->wMaxPacketSize.size; + audio->ep_in_sz = tu_edpt_packet_size(desc_ep); // If software encoding is enabled, parse for the corresponding parameters - doing this here means only AS interfaces with EPs get scanned for parameters #if CFG_TUD_AUDIO_ENABLE_ENCODING @@ -1616,7 +1617,7 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const * // Save address audio->ep_out = ep_addr; audio->ep_out_as_intf_num = itf; - audio->ep_out_sz = ((tusb_desc_endpoint_t const *) p_desc)->wMaxPacketSize.size; + audio->ep_out_sz = tu_edpt_packet_size(desc_ep); #if CFG_TUD_AUDIO_ENABLE_DECODING audiod_parse_for_AS_params(audio, p_desc_parse_for_params, p_desc_end, itf); @@ -1635,7 +1636,7 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const * #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP // In case of asynchronous EP, call Cb after ep_fb is set - if (!(((tusb_desc_endpoint_t const *) p_desc)->bmAttributes.sync == 0x01 && audio->ep_fb == 0)) + if ( !(desc_ep->bmAttributes.sync == 0x01 && audio->ep_fb == 0) ) { if (tud_audio_set_itf_cb) TU_VERIFY(tud_audio_set_itf_cb(rhport, p_request)); } @@ -1652,7 +1653,7 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const * } #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP - if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN && ((tusb_desc_endpoint_t const *) p_desc)->bmAttributes.usage == 1) // Check if usage is explicit data feedback + if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN && desc_ep->bmAttributes.usage == 1) // Check if usage is explicit data feedback { audio->ep_fb = ep_addr; diff --git a/src/class/bth/bth_device.c b/src/class/bth/bth_device.c index b73f829cc..f445deed2 100755 --- a/src/class/bth/bth_device.c +++ b/src/class/bth/bth_device.c @@ -142,14 +142,14 @@ uint16_t btd_open(uint8_t rhport, tusb_desc_interface_t const *itf_desc, uint16_ dir = tu_edpt_dir(desc_ep->bEndpointAddress); _btd_itf.ep_voice[dir] = desc_ep->bEndpointAddress; // Store endpoint size for alternative - _btd_itf.ep_voice_size[dir][itf_desc->bAlternateSetting] = (uint8_t)desc_ep->wMaxPacketSize.size; + _btd_itf.ep_voice_size[dir][itf_desc->bAlternateSetting] = (uint8_t) tu_edpt_packet_size(desc_ep); desc_ep = (tusb_desc_endpoint_t const *)tu_desc_next(desc_ep); TU_ASSERT(desc_ep->bDescriptorType == TUSB_DESC_ENDPOINT, 0); dir = tu_edpt_dir(desc_ep->bEndpointAddress); _btd_itf.ep_voice[dir] = desc_ep->bEndpointAddress; // Store endpoint size for alternative - _btd_itf.ep_voice_size[dir][itf_desc->bAlternateSetting] = (uint8_t)desc_ep->wMaxPacketSize.size; + _btd_itf.ep_voice_size[dir][itf_desc->bAlternateSetting] = (uint8_t) tu_edpt_packet_size(desc_ep); drv_len += iso_alt_itf_size; for (int i = 1; i < CFG_TUD_BTH_ISO_ALT_COUNT && drv_len + iso_alt_itf_size <= max_len; ++i) { @@ -170,14 +170,14 @@ uint16_t btd_open(uint8_t rhport, tusb_desc_interface_t const *itf_desc, uint16_ // Verify that alternative endpoint are same as first ones TU_ASSERT(desc_ep->bDescriptorType == TUSB_DESC_ENDPOINT && _btd_itf.ep_voice[dir] == desc_ep->bEndpointAddress, 0); - _btd_itf.ep_voice_size[dir][itf_desc->bAlternateSetting] = (uint8_t)desc_ep->wMaxPacketSize.size; + _btd_itf.ep_voice_size[dir][itf_desc->bAlternateSetting] = (uint8_t) tu_edpt_packet_size(desc_ep); desc_ep = (tusb_desc_endpoint_t const *)tu_desc_next(desc_ep); dir = tu_edpt_dir(desc_ep->bEndpointAddress); // Verify that alternative endpoint are same as first ones TU_ASSERT(desc_ep->bDescriptorType == TUSB_DESC_ENDPOINT && _btd_itf.ep_voice[dir] == desc_ep->bEndpointAddress, 0); - _btd_itf.ep_voice_size[dir][itf_desc->bAlternateSetting] = (uint8_t)desc_ep->wMaxPacketSize.size; + _btd_itf.ep_voice_size[dir][itf_desc->bAlternateSetting] = (uint8_t) tu_edpt_packet_size(desc_ep); drv_len += iso_alt_itf_size; } } diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c index ac260d39b..f19f1ba81 100644 --- a/src/class/hid/hid_host.c +++ b/src/class/hid/hid_host.c @@ -307,7 +307,7 @@ bool hidh_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *de hid_itf->itf_num = desc_itf->bInterfaceNumber; hid_itf->ep_in = desc_ep->bEndpointAddress; - hid_itf->epin_size = desc_ep->wMaxPacketSize.size; + hid_itf->epin_size = tu_edpt_packet_size(desc_ep); // Assume bNumDescriptors = 1 hid_itf->report_desc_type = desc_hid->bReportType; diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c index 6c916d2f3..4bd1edf12 100644 --- a/src/class/usbtmc/usbtmc_device.c +++ b/src/class/usbtmc/usbtmc_device.c @@ -280,7 +280,7 @@ uint16_t usbtmcd_open_cb(uint8_t rhport, tusb_desc_interface_t const * itf_desc, tusb_desc_endpoint_t const *ep_desc = (tusb_desc_endpoint_t const *)p_desc; switch(ep_desc->bmAttributes.xfer) { case TUSB_XFER_BULK: - TU_ASSERT(ep_desc->wMaxPacketSize.size == USBTMCD_MAX_PACKET_SIZE, 0); + TU_ASSERT(tu_edpt_packet_size(ep_desc) == USBTMCD_MAX_PACKET_SIZE, 0); if (tu_edpt_dir(ep_desc->bEndpointAddress) == TUSB_DIR_IN) { usbtmc_state.ep_bulk_in = ep_desc->bEndpointAddress; diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index d9bd44f61..eeb068197 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -582,11 +582,11 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint TU_ASSERT(cur < end); tusb_desc_endpoint_t const *ep = (tusb_desc_endpoint_t const*)cur; if (!stm->max_payload_transfer_size) { - video_probe_and_commit_control_t const *param = - (video_probe_and_commit_control_t const*)&stm->ep_buf; + video_probe_and_commit_control_t const *param = (video_probe_and_commit_control_t const*)&stm->ep_buf; uint_fast32_t max_size = param->dwMaxPayloadTransferSize; if ((TUSB_XFER_ISOCHRONOUS == ep->bmAttributes.xfer) && - (ep->wMaxPacketSize.size < max_size)) { + (tu_edpt_packet_size(ep) < max_size)) + { /* FS must be less than or equal to max packet size */ return false; } diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h index 8dd1dbd49..fc92654b7 100644 --- a/src/common/tusb_common.h +++ b/src/common/tusb_common.h @@ -38,20 +38,21 @@ #define TU_MIN(_x, _y) ( ( (_x) < (_y) ) ? (_x) : (_y) ) #define TU_MAX(_x, _y) ( ( (_x) > (_y) ) ? (_x) : (_y) ) -#define TU_U16_HIGH(_u16) ((uint8_t) (((_u16) >> 8) & 0x00ff)) -#define TU_U16_LOW(_u16) ((uint8_t) ((_u16) & 0x00ff)) -#define U16_TO_U8S_BE(_u16) TU_U16_HIGH(_u16), TU_U16_LOW(_u16) -#define U16_TO_U8S_LE(_u16) TU_U16_LOW(_u16), TU_U16_HIGH(_u16) +#define TU_U16_HIGH(_u16) ((uint8_t) (((_u16) >> 8) & 0x00ff)) +#define TU_U16_LOW(_u16) ((uint8_t) ((_u16) & 0x00ff)) +#define U16_TO_U8S_BE(_u16) TU_U16_HIGH(_u16), TU_U16_LOW(_u16) +#define U16_TO_U8S_LE(_u16) TU_U16_LOW(_u16), TU_U16_HIGH(_u16) -#define TU_U32_BYTE3(_u32) ((uint8_t) ((((uint32_t) _u32) >> 24) & 0x000000ff)) // MSB -#define TU_U32_BYTE2(_u32) ((uint8_t) ((((uint32_t) _u32) >> 16) & 0x000000ff)) -#define TU_U32_BYTE1(_u32) ((uint8_t) ((((uint32_t) _u32) >> 8) & 0x000000ff)) -#define TU_U32_BYTE0(_u32) ((uint8_t) (((uint32_t) _u32) & 0x000000ff)) // LSB +#define TU_U32_BYTE3(_u32) ((uint8_t) ((((uint32_t) _u32) >> 24) & 0x000000ff)) // MSB +#define TU_U32_BYTE2(_u32) ((uint8_t) ((((uint32_t) _u32) >> 16) & 0x000000ff)) +#define TU_U32_BYTE1(_u32) ((uint8_t) ((((uint32_t) _u32) >> 8) & 0x000000ff)) +#define TU_U32_BYTE0(_u32) ((uint8_t) (((uint32_t) _u32) & 0x000000ff)) // LSB -#define U32_TO_U8S_BE(_u32) TU_U32_BYTE3(_u32), TU_U32_BYTE2(_u32), TU_U32_BYTE1(_u32), TU_U32_BYTE0(_u32) -#define U32_TO_U8S_LE(_u32) TU_U32_BYTE0(_u32), TU_U32_BYTE1(_u32), TU_U32_BYTE2(_u32), TU_U32_BYTE3(_u32) +#define U32_TO_U8S_BE(_u32) TU_U32_BYTE3(_u32), TU_U32_BYTE2(_u32), TU_U32_BYTE1(_u32), TU_U32_BYTE0(_u32) +#define U32_TO_U8S_LE(_u32) TU_U32_BYTE0(_u32), TU_U32_BYTE1(_u32), TU_U32_BYTE2(_u32), TU_U32_BYTE3(_u32) #define TU_BIT(n) (1UL << (n)) +#define TU_GENMASK(h, l) ( (UINT32_MAX << (l)) & (UINT32_MAX >> (31 - (h))) ) //--------------------------------------------------------------------+ // Includes diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h index 897e89b39..233def466 100644 --- a/src/common/tusb_types.h +++ b/src/common/tusb_types.h @@ -349,32 +349,24 @@ TU_VERIFY_STATIC( sizeof(tusb_desc_interface_t) == 9, "size is not correct"); /// USB Endpoint Descriptor typedef struct TU_ATTR_PACKED { - uint8_t bLength ; ///< Size of this descriptor in bytes - uint8_t bDescriptorType ; ///< ENDPOINT Descriptor Type + uint8_t bLength ; // Size of this descriptor in bytes + uint8_t bDescriptorType ; // ENDPOINT Descriptor Type - uint8_t bEndpointAddress ; ///< The address of the endpoint on the USB device described by this descriptor. The address is encoded as follows: \n Bit 3...0: The endpoint number \n Bit 6...4: Reserved, reset to zero \n Bit 7: Direction, ignored for control endpoints 0 = OUT endpoint 1 = IN endpoint. + uint8_t bEndpointAddress ; // The address of the endpoint struct TU_ATTR_PACKED { - uint8_t xfer : 2; - uint8_t sync : 2; - uint8_t usage : 2; + uint8_t xfer : 2; // Control, ISO, Bulk, Interrupt + uint8_t sync : 2; // None, Asynchronous, Adaptive, Synchronous + uint8_t usage : 2; // Data, Feedback, Implicit feedback uint8_t : 2; - } bmAttributes ; ///< This field describes the endpoint's attributes when it is configured using the bConfigurationValue. \n Bits 1..0: Transfer Type \n- 00 = Control \n- 01 = Isochronous \n- 10 = Bulk \n- 11 = Interrupt \n If not an isochronous endpoint, bits 5..2 are reserved and must be set to zero. If isochronous, they are defined as follows: \n Bits 3..2: Synchronization Type \n- 00 = No Synchronization \n- 01 = Asynchronous \n- 10 = Adaptive \n- 11 = Synchronous \n Bits 5..4: Usage Type \n- 00 = Data endpoint \n- 01 = Feedback endpoint \n- 10 = Implicit feedback Data endpoint \n- 11 = Reserved \n Refer to Chapter 5 of USB 2.0 specification for more information. \n All other bits are reserved and must be reset to zero. Reserved bits must be ignored by the host. + } bmAttributes; - struct TU_ATTR_PACKED { -#if defined(__CCRX__) - //FIXME the original defined bit field has a problem with the CCRX toolchain, so only a size field is defined - uint16_t size; -#else - uint16_t size : 11; ///< Maximum packet size this endpoint is capable of sending or receiving when this configuration is selected. \n For isochronous endpoints, this value is used to reserve the bus time in the schedule, required for the per-(micro)frame data payloads. The pipe may, on an ongoing basis, actually use less bandwidth than that reserved. The device reports, if necessary, the actual bandwidth used via its normal, non-USB defined mechanisms. \n For all endpoints, bits 10..0 specify the maximum packet size (in bytes). \n For high-speed isochronous and interrupt endpoints: \n Bits 12..11 specify the number of additional transaction opportunities per microframe: \n- 00 = None (1 transaction per microframe) \n- 01 = 1 additional (2 per microframe) \n- 10 = 2 additional (3 per microframe) \n- 11 = Reserved \n Bits 15..13 are reserved and must be set to zero. - uint16_t hs_period_mult : 2; - uint16_t TU_RESERVED : 3; -#endif - }wMaxPacketSize; - - uint8_t bInterval ; ///< Interval for polling endpoint for data transfers. Expressed in frames or microframes depending on the device operating speed (i.e., either 1 millisecond or 125 us units). \n- For full-/high-speed isochronous endpoints, this value must be in the range from 1 to 16. The bInterval value is used as the exponent for a \f$ 2^(bInterval-1) \f$ value; e.g., a bInterval of 4 means a period of 8 (\f$ 2^(4-1) \f$). \n- For full-/low-speed interrupt endpoints, the value of this field may be from 1 to 255. \n- For high-speed interrupt endpoints, the bInterval value is used as the exponent for a \f$ 2^(bInterval-1) \f$ value; e.g., a bInterval of 4 means a period of 8 (\f$ 2^(4-1) \f$) . This value must be from 1 to 16. \n- For high-speed bulk/control OUT endpoints, the bInterval must specify the maximum NAK rate of the endpoint. A value of 0 indicates the endpoint never NAKs. Other values indicate at most 1 NAK each bInterval number of microframes. This value must be in the range from 0 to 255. \n Refer to Chapter 5 of USB 2.0 specification for more information. + uint16_t wMaxPacketSize ; // Bit 10..0 : max packet size, bit 12..11 additional transaction per highspeed micro-frame + uint8_t bInterval ; // Polling interval, in frames or microframes depending on the operating speed } tusb_desc_endpoint_t; +TU_VERIFY_STATIC( sizeof(tusb_desc_endpoint_t) == 7, "size is not correct"); + /// USB Other Speed Configuration Descriptor typedef struct TU_ATTR_PACKED { @@ -521,6 +513,11 @@ static inline uint8_t tu_edpt_addr(uint8_t num, uint8_t dir) return (uint8_t)(num | (dir ? TUSB_DIR_IN_MASK : 0)); } +static inline uint16_t tu_edpt_packet_size(tusb_desc_endpoint_t const* desc_ep) +{ + return tu_le16toh(desc_ep->wMaxPacketSize) & TU_GENMASK(10, 0); +} + //--------------------------------------------------------------------+ // Descriptor helper //--------------------------------------------------------------------+ diff --git a/src/host/usbh.c b/src/host/usbh.c index a9c2c201f..f74e7114c 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -1172,7 +1172,7 @@ static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size) .bDescriptorType = TUSB_DESC_ENDPOINT, .bEndpointAddress = 0, .bmAttributes = { .xfer = TUSB_XFER_CONTROL }, - .wMaxPacketSize = { .size = max_packet_size }, + .wMaxPacketSize = max_packet_size, .bInterval = 0 }; diff --git a/src/portable/dialog/da146xx/dcd_da146xx.c b/src/portable/dialog/da146xx/dcd_da146xx.c index c9d1d9b3c..51957829f 100644 --- a/src/portable/dialog/da146xx/dcd_da146xx.c +++ b/src/portable/dialog/da146xx/dcd_da146xx.c @@ -914,7 +914,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) TU_ASSERT(epnum < EP_MAX); - xfer->max_packet_size = desc_edpt->wMaxPacketSize.size; + xfer->max_packet_size = tu_edpt_packet_size(desc_edpt); xfer->ep_addr = desc_edpt->bEndpointAddress; xfer->data1 = 0; xfer->iso = 0; diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index 18ddaf31a..e92f8a951 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -802,7 +802,7 @@ static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t c p_qhd->ep_speed = devtree_info.speed; p_qhd->data_toggle_control= (xfer_type == TUSB_XFER_CONTROL) ? 1 : 0; p_qhd->head_list_flag = (dev_addr == 0) ? 1 : 0; // addr0's endpoint is the static asyn list head - p_qhd->max_packet_size = ep_desc->wMaxPacketSize.size; + p_qhd->max_packet_size = tu_edpt_packet_size(ep_desc); p_qhd->fl_ctrl_ep_flag = ((xfer_type == TUSB_XFER_CONTROL) && (p_qhd->ep_speed != TUSB_SPEED_HIGH)) ? 1 : 0; p_qhd->nak_reload = 0; diff --git a/src/portable/espressif/esp32sx/dcd_esp32sx.c b/src/portable/espressif/esp32sx/dcd_esp32sx.c index cfbbab233..c27fc2922 100644 --- a/src/portable/espressif/esp32sx/dcd_esp32sx.c +++ b/src/portable/espressif/esp32sx/dcd_esp32sx.c @@ -256,17 +256,16 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_edpt) uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress); uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress); - TU_ASSERT(desc_edpt->wMaxPacketSize.size <= 64); TU_ASSERT(epnum < EP_MAX); xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir); - xfer->max_size = desc_edpt->wMaxPacketSize.size; + xfer->max_size = tu_edpt_packet_size(desc_edpt); if (dir == TUSB_DIR_OUT) { out_ep[epnum].doepctl |= USB_USBACTEP1_M | desc_edpt->bmAttributes.xfer << USB_EPTYPE1_S | (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_DO_SETD0PID1_M : 0) | - desc_edpt->wMaxPacketSize.size << USB_MPS1_S; + xfer->max_size << USB_MPS1_S; USB0.daintmsk |= (1 << (16 + epnum)); } else { // "USB Data FIFOs" section in reference manual @@ -300,7 +299,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_edpt) fifo_num << USB_D_TXFNUM1_S | desc_edpt->bmAttributes.xfer << USB_D_EPTYPE1_S | (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? (1 << USB_DI_SETD0PID1_S) : 0) | - desc_edpt->wMaxPacketSize.size << 0; + xfer->max_size << 0; USB0.daintmsk |= (1 << (0 + epnum)); diff --git a/src/portable/microchip/samd/dcd_samd.c b/src/portable/microchip/samd/dcd_samd.c index 526a6fb63..46aabc5aa 100644 --- a/src/portable/microchip/samd/dcd_samd.c +++ b/src/portable/microchip/samd/dcd_samd.c @@ -214,14 +214,14 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) UsbDeviceDescBank* bank = &sram_registers[epnum][dir]; uint32_t size_value = 0; while (size_value < 7) { - if (1 << (size_value + 3) == desc_edpt->wMaxPacketSize.size) { + if (1 << (size_value + 3) == tu_edpt_packet_size(desc_edpt)) { break; } size_value++; } // unsupported endpoint size - if ( size_value == 7 && desc_edpt->wMaxPacketSize.size != 1023 ) return false; + if ( size_value == 7 && tu_edpt_packet_size(desc_edpt) != 1023 ) return false; bank->PCKSIZE.bit.SIZE = size_value; diff --git a/src/portable/microchip/samg/dcd_samg.c b/src/portable/microchip/samg/dcd_samg.c index 81779c56b..2e9854153 100644 --- a/src/portable/microchip/samg/dcd_samg.c +++ b/src/portable/microchip/samg/dcd_samg.c @@ -258,7 +258,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) // Must not already enabled TU_ASSERT((UDP->UDP_CSR[epnum] & UDP_CSR_EPEDS_Msk) == 0); - xfer_epsize_set(&_dcd_xfer[epnum], ep_desc->wMaxPacketSize.size); + xfer_epsize_set(&_dcd_xfer[epnum], tu_edpt_packet_size(ep_desc)); // Configure type and enable EP csr_write(epnum, UDP_CSR_EPEDS_Msk | UDP_CSR_EPTYPE(ep_desc->bmAttributes.xfer + 4*dir)); diff --git a/src/portable/microchip/samx7x/dcd_samx7x.c b/src/portable/microchip/samx7x/dcd_samx7x.c index 032547e47..d716e8fed 100644 --- a/src/portable/microchip/samx7x/dcd_samx7x.c +++ b/src/portable/microchip/samx7x/dcd_samx7x.c @@ -460,7 +460,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) (void) rhport; uint8_t const epnum = tu_edpt_number(ep_desc->bEndpointAddress); uint8_t const dir = tu_edpt_dir(ep_desc->bEndpointAddress); - uint16_t const epMaxPktSize = ep_desc->wMaxPacketSize.size; + uint16_t const epMaxPktSize = tu_edpt_packet_size(ep_desc); tusb_xfer_type_t const eptype = (tusb_xfer_type_t)ep_desc->bmAttributes.xfer; uint8_t fifoSize = 0; // FIFO size uint16_t defaultEndpointSize = 8; // Default size of Endpoint diff --git a/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c b/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c index 6cc0fcac3..a3b69b987 100644 --- a/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c +++ b/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c @@ -323,7 +323,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) /* No support for control transfer */ TU_ASSERT(epn && (xfer != TUSB_XFER_CONTROL)); - ep->max_packet_size = ep_desc->wMaxPacketSize.size; + ep->max_packet_size = tu_edpt_packet_size(ep_desc); unsigned val = USB_ENDPT_EPCTLDIS_MASK; val |= (xfer != TUSB_XFER_ISOCHRONOUS) ? USB_ENDPT_EPHSHK_MASK: 0; val |= dir ? USB_ENDPT_EPTXEN_MASK : USB_ENDPT_EPRXEN_MASK; diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c index 06f23f8a5..9d7db11b2 100644 --- a/src/portable/nordic/nrf5x/dcd_nrf5x.c +++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c @@ -311,7 +311,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); - _dcd.xfer[epnum][dir].mps = desc_edpt->wMaxPacketSize.size; + _dcd.xfer[epnum][dir].mps = tu_edpt_packet_size(desc_edpt); if (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS) { diff --git a/src/portable/nuvoton/nuc120/dcd_nuc120.c b/src/portable/nuvoton/nuc120/dcd_nuc120.c index 7618f288d..0d45090d1 100644 --- a/src/portable/nuvoton/nuc120/dcd_nuc120.c +++ b/src/portable/nuvoton/nuc120/dcd_nuc120.c @@ -251,7 +251,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) /* mine the data for the information we need */ int const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress); - int const size = p_endpoint_desc->wMaxPacketSize.size; + int const size = tu_edpt_packet_size(p_endpoint_desc); tusb_xfer_type_t const type = (tusb_xfer_type_t) p_endpoint_desc->bmAttributes.xfer; struct xfer_ctl_t *xfer = &xfer_table[ep - USBD->EP]; diff --git a/src/portable/nuvoton/nuc121/dcd_nuc121.c b/src/portable/nuvoton/nuc121/dcd_nuc121.c index dbc5cd18a..fc7150508 100644 --- a/src/portable/nuvoton/nuc121/dcd_nuc121.c +++ b/src/portable/nuvoton/nuc121/dcd_nuc121.c @@ -279,7 +279,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) /* mine the data for the information we need */ int const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress); - int const size = p_endpoint_desc->wMaxPacketSize.size; + int const size = tu_edpt_packet_size(p_endpoint_desc); tusb_xfer_type_t const type = (tusb_xfer_type_t) p_endpoint_desc->bmAttributes.xfer; struct xfer_ctl_t *xfer = &xfer_table[ep - USBD->EP]; diff --git a/src/portable/nuvoton/nuc505/dcd_nuc505.c b/src/portable/nuvoton/nuc505/dcd_nuc505.c index 11d71a285..aefb09f4e 100644 --- a/src/portable/nuvoton/nuc505/dcd_nuc505.c +++ b/src/portable/nuvoton/nuc505/dcd_nuc505.c @@ -327,7 +327,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) /* mine the data for the information we need */ int const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress); - int const size = p_endpoint_desc->wMaxPacketSize.size; + int const size = tu_edpt_packet_size(p_endpoint_desc); tusb_xfer_type_t const type = p_endpoint_desc->bmAttributes.xfer; struct xfer_ctl_t *xfer = &xfer_table[ep - USBD->EP]; diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c index ff1997440..8de924f90 100644 --- a/src/portable/nxp/khci/dcd_khci.c +++ b/src/portable/nxp/khci/dcd_khci.c @@ -346,7 +346,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) /* No support for control transfer */ TU_ASSERT(epn && (xfer != TUSB_XFER_CONTROL)); - ep->max_packet_size = ep_desc->wMaxPacketSize.size; + ep->max_packet_size = tu_edpt_packet_size(ep_desc); unsigned val = USB_ENDPT_EPCTLDIS_MASK; val |= (xfer != TUSB_XFER_ISOCHRONOUS) ? USB_ENDPT_EPHSHK_MASK: 0; val |= dir ? USB_ENDPT_EPTXEN_MASK : USB_ENDPT_EPRXEN_MASK; diff --git a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c index 2eae6d0f7..0f500a88f 100644 --- a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c +++ b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c @@ -311,14 +311,15 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) } //------------- Realize Endpoint with Max Packet Size -------------// - set_ep_size(ep_id, p_endpoint_desc->wMaxPacketSize.size); + const uint16_t ep_size = tu_edpt_packet_size(p_endpoint_desc); + set_ep_size(ep_id, ep_size); //------------- first DD prepare -------------// dma_desc_t* const dd = &_dcd.dd[ep_id]; tu_memclr(dd, sizeof(dma_desc_t)); dd->isochronous = (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) ? 1 : 0; - dd->max_packet_size = p_endpoint_desc->wMaxPacketSize.size; + dd->max_packet_size = ep_size; dd->retired = 1; // invalid at first sie_write(SIE_CMDCODE_ENDPOINT_SET_STATUS + ep_id, 1, 0); // clear all endpoint status diff --git a/src/portable/nxp/transdimension/dcd_transdimension.c b/src/portable/nxp/transdimension/dcd_transdimension.c index 0f58cceb9..5ac041fbf 100644 --- a/src/portable/nxp/transdimension/dcd_transdimension.c +++ b/src/portable/nxp/transdimension/dcd_transdimension.c @@ -365,7 +365,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) tu_memclr(p_qhd, sizeof(dcd_qhd_t)); p_qhd->zero_length_termination = 1; - p_qhd->max_packet_size = p_endpoint_desc->wMaxPacketSize.size; + p_qhd->max_packet_size = tu_edpt_packet_size(p_endpoint_desc); if (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) { p_qhd->iso_mult = 1; diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c index bcee34938..daa8075b7 100644 --- a/src/portable/ohci/ohci.c +++ b/src/portable/ohci/ohci.c @@ -412,7 +412,7 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const } TU_ASSERT(p_ed); - ed_init( p_ed, dev_addr, ep_desc->wMaxPacketSize.size, ep_desc->bEndpointAddress, + ed_init( p_ed, dev_addr, tu_edpt_packet_size(ep_desc), ep_desc->bEndpointAddress, ep_desc->bmAttributes.xfer, ep_desc->bInterval ); // control of dev0 is used as static async head diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c index 4bcc9ca54..e084478e0 100644 --- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c @@ -426,7 +426,7 @@ void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * re bool dcd_edpt_open (__unused uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) { assert(rhport == 0); - hw_endpoint_init(desc_edpt->bEndpointAddress, desc_edpt->wMaxPacketSize.size, desc_edpt->bmAttributes.xfer); + hw_endpoint_init(desc_edpt->bEndpointAddress, tu_edpt_packet_size(desc_edpt), desc_edpt->bmAttributes.xfer); return true; } diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c index 5e5bb4906..627e957e8 100644 --- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c @@ -454,7 +454,7 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const _hw_endpoint_init(ep, dev_addr, ep_desc->bEndpointAddress, - ep_desc->wMaxPacketSize.size, + tu_edpt_packet_size(ep_desc), ep_desc->bmAttributes.xfer, ep_desc->bInterval); diff --git a/src/portable/renesas/usba/dcd_usba.c b/src/portable/renesas/usba/dcd_usba.c index 07d3ba898..ae7d2fd0c 100644 --- a/src/portable/renesas/usba/dcd_usba.c +++ b/src/portable/renesas/usba/dcd_usba.c @@ -695,7 +695,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) const unsigned dir = tu_edpt_dir(ep_addr); const unsigned xfer = ep_desc->bmAttributes.xfer; - const unsigned mps = tu_le16toh(ep_desc->wMaxPacketSize.size); + const unsigned mps = tu_edpt_packet_size(ep_desc); if (xfer == TUSB_XFER_ISOCHRONOUS && mps > 256) { /* USBa supports up to 256 bytes */ return false; diff --git a/src/portable/silabs/efm32/dcd_efm32.c b/src/portable/silabs/efm32/dcd_efm32.c index 3bef83408..ccae113a3 100644 --- a/src/portable/silabs/efm32/dcd_efm32.c +++ b/src/portable/silabs/efm32/dcd_efm32.c @@ -393,18 +393,17 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress); uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress); - TU_ASSERT(p_endpoint_desc->wMaxPacketSize.size <= 64); TU_ASSERT(epnum < EP_COUNT); TU_ASSERT(epnum != 0); xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir); - xfer->max_size = p_endpoint_desc->wMaxPacketSize.size; + xfer->max_size = tu_edpt_packet_size(p_endpoint_desc); if(dir == TUSB_DIR_OUT) { USB->DOEP[epnum - 1].CTL |= USB_DOEP_CTL_USBACTEP | (p_endpoint_desc->bmAttributes.xfer << _USB_DOEP_CTL_EPTYPE_SHIFT) | - (p_endpoint_desc->wMaxPacketSize.size << _USB_DOEP_CTL_MPS_SHIFT); + (xfer->max_size << _USB_DOEP_CTL_MPS_SHIFT); USB->DAINTMSK |= (1 << (_USB_DAINTMSK_OUTEPMSK0_SHIFT + epnum)); } else @@ -417,7 +416,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) (fifo_num << _USB_DIEP_CTL_TXFNUM_SHIFT) | (p_endpoint_desc->bmAttributes.xfer << _USB_DIEP_CTL_EPTYPE_SHIFT) | ((p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS) ? USB_DIEP_CTL_SETD0PIDEF : 0) | - (p_endpoint_desc->wMaxPacketSize.size << 0); + (xfer->max_size << 0); USB->DAINTMSK |= (1 << epnum); diff --git a/src/portable/sony/cxd56/dcd_cxd56.c b/src/portable/sony/cxd56/dcd_cxd56.c index 1b8a789a4..dfe409383 100644 --- a/src/portable/sony/cxd56/dcd_cxd56.c +++ b/src/portable/sony/cxd56/dcd_cxd56.c @@ -257,6 +257,8 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *p_endpoint_desc) uint8_t epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress); uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress); uint8_t xfrtype = 0; + uint16_t const ep_mps = tu_edpt_packet_size(p_endpoint_desc); + struct usb_epdesc_s epdesc; if (epnum >= CXD56_EPNUM) @@ -287,7 +289,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *p_endpoint_desc) usbdcd_driver.req[epnum] = EP_ALLOCREQ(usbdcd_driver.ep[epnum]); if (usbdcd_driver.req[epnum] != NULL) { - usbdcd_driver.req[epnum]->len = p_endpoint_desc->wMaxPacketSize.size; + usbdcd_driver.req[epnum]->len = ep_mps; } else { @@ -300,8 +302,8 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *p_endpoint_desc) epdesc.type = p_endpoint_desc->bDescriptorType; epdesc.addr = p_endpoint_desc->bEndpointAddress; epdesc.attr = xfrtype; - epdesc.mxpacketsize[0] = LSBYTE(p_endpoint_desc->wMaxPacketSize.size); - epdesc.mxpacketsize[1] = MSBYTE(p_endpoint_desc->wMaxPacketSize.size); + epdesc.mxpacketsize[0] = LSBYTE(ep_mps); + epdesc.mxpacketsize[1] = MSBYTE(ep_mps); epdesc.interval = p_endpoint_desc->bInterval; if (EP_CONFIGURE(usbdcd_driver.ep[epnum], &epdesc, false) < 0) diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index ccffa42d7..ca6564d46 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -394,7 +394,7 @@ static const tusb_desc_endpoint_t ep0OUT_desc = .bEndpointAddress = 0x00, .bmAttributes = { .xfer = TUSB_XFER_CONTROL }, - .wMaxPacketSize = { .size = CFG_TUD_ENDPOINT0_SIZE }, + .wMaxPacketSize = CFG_TUD_ENDPOINT0_SIZE, .bInterval = 0 }; @@ -405,7 +405,7 @@ static const tusb_desc_endpoint_t ep0IN_desc = .bEndpointAddress = 0x80, .bmAttributes = { .xfer = TUSB_XFER_CONTROL }, - .wMaxPacketSize = { .size = CFG_TUD_ENDPOINT0_SIZE }, + .wMaxPacketSize = CFG_TUD_ENDPOINT0_SIZE, .bInterval = 0 }; @@ -741,7 +741,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc (void)rhport; uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress); uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress); - const uint16_t epMaxPktSize = p_endpoint_desc->wMaxPacketSize.size; + const uint16_t epMaxPktSize = tu_edpt_packet_size(p_endpoint_desc); uint16_t pma_addr; uint32_t wType; @@ -778,19 +778,19 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc // or being double-buffered (bulk endpoints) pcd_clear_ep_kind(USB,0); - pma_addr = dcd_pma_alloc(p_endpoint_desc->bEndpointAddress, p_endpoint_desc->wMaxPacketSize.size); + pma_addr = dcd_pma_alloc(p_endpoint_desc->bEndpointAddress, epMaxPktSize); if(dir == TUSB_DIR_IN) { *pcd_ep_tx_address_ptr(USB, epnum) = pma_addr; - pcd_set_ep_tx_cnt(USB, epnum, p_endpoint_desc->wMaxPacketSize.size); + pcd_set_ep_tx_cnt(USB, epnum, epMaxPktSize); pcd_clear_tx_dtog(USB, epnum); pcd_set_ep_tx_status(USB,epnum,USB_EP_TX_NAK); } else { *pcd_ep_rx_address_ptr(USB, epnum) = pma_addr; - pcd_set_ep_rx_cnt(USB, epnum, p_endpoint_desc->wMaxPacketSize.size); + pcd_set_ep_rx_cnt(USB, epnum, epMaxPktSize); pcd_clear_rx_dtog(USB, epnum); pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_NAK); } diff --git a/src/portable/st/synopsys/dcd_synopsys.c b/src/portable/st/synopsys/dcd_synopsys.c index 29030784b..4e2bbd076 100644 --- a/src/portable/st/synopsys/dcd_synopsys.c +++ b/src/portable/st/synopsys/dcd_synopsys.c @@ -622,10 +622,10 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) TU_ASSERT(epnum < EP_MAX); xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir); - xfer->max_size = desc_edpt->wMaxPacketSize.size; + xfer->max_size = tu_edpt_packet_size(desc_edpt); xfer->interval = desc_edpt->bInterval; - uint16_t const fifo_size = (desc_edpt->wMaxPacketSize.size + 3) / 4; // Round up to next full word + uint16_t const fifo_size = (xfer->max_size + 3) / 4; // Round up to next full word if(dir == TUSB_DIR_OUT) { @@ -644,7 +644,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) out_ep[epnum].DOEPCTL |= (1 << USB_OTG_DOEPCTL_USBAEP_Pos) | (desc_edpt->bmAttributes.xfer << USB_OTG_DOEPCTL_EPTYP_Pos) | (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_OTG_DOEPCTL_SD0PID_SEVNFRM : 0) | - (desc_edpt->wMaxPacketSize.size << USB_OTG_DOEPCTL_MPSIZ_Pos); + (xfer->max_size << USB_OTG_DOEPCTL_MPSIZ_Pos); dev->DAINTMSK |= (1 << (USB_OTG_DAINTMSK_OEPM_Pos + epnum)); } @@ -686,7 +686,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) (epnum << USB_OTG_DIEPCTL_TXFNUM_Pos) | (desc_edpt->bmAttributes.xfer << USB_OTG_DIEPCTL_EPTYP_Pos) | (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_OTG_DIEPCTL_SD0PID_SEVNFRM : 0) | - (desc_edpt->wMaxPacketSize.size << USB_OTG_DIEPCTL_MPSIZ_Pos); + (xfer->max_size << USB_OTG_DIEPCTL_MPSIZ_Pos); dev->DAINTMSK |= (1 << (USB_OTG_DAINTMSK_IEPM_Pos + epnum)); } diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c index ee85f0a77..7a2a0156f 100644 --- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c +++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c @@ -242,7 +242,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) } xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir); - xfer->max_size = desc_edpt->wMaxPacketSize.size; + xfer->max_size = tu_edpt_packet_size(desc_edpt); // Buffer allocation scheme: // For simplicity, only single buffer for now, since tinyusb currently waits @@ -275,7 +275,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) // Also, DBUF got set on OUT EP 2 while debugging. Only OUT EPs seem to be // affected at this time. USB RAM directly precedes main RAM; perhaps I'm // overwriting registers via buffer overflow w/ my debugging code? - ep_regs[SIZXY] = desc_edpt->wMaxPacketSize.size; + ep_regs[SIZXY] = tu_edpt_packet_size(desc_edpt); ep_regs[BCTX] |= NAK; ep_regs[BBAX] = buf_base; ep_regs[CNF] &= ~(TOGGLE | STALL | DBUF); // ISO xfers not supported on diff --git a/src/tusb.c b/src/tusb.c index fc1936c3d..9583f509d 100644 --- a/src/tusb.c +++ b/src/tusb.c @@ -69,7 +69,7 @@ bool tusb_inited(void) bool tu_edpt_validate(tusb_desc_endpoint_t const * desc_ep, tusb_speed_t speed) { - uint16_t const max_packet_size = tu_le16toh(desc_ep->wMaxPacketSize.size); + uint16_t const max_packet_size = tu_edpt_packet_size(desc_ep); TU_LOG2(" Open EP %02X with Size = %u\r\n", desc_ep->bEndpointAddress, max_packet_size); switch (desc_ep->bmAttributes.xfer) -- cgit v1.3.1 From 109b7a666155eb1b59bf946be7319ac11bc625ea Mon Sep 17 00:00:00 2001 From: hathach Date: Sun, 24 Oct 2021 14:39:02 +0700 Subject: more wMaxPacketSize --- src/portable/dialog/da146xx/dcd_da146xx.c | 4 ++-- src/portable/microchip/samx7x/dcd_samx7x.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/portable/dialog/da146xx/dcd_da146xx.c b/src/portable/dialog/da146xx/dcd_da146xx.c index 51957829f..311119747 100644 --- a/src/portable/dialog/da146xx/dcd_da146xx.c +++ b/src/portable/dialog/da146xx/dcd_da146xx.c @@ -256,7 +256,7 @@ static const tusb_desc_endpoint_t ep0OUT_desc = .bEndpointAddress = 0x00, .bmAttributes = { .xfer = TUSB_XFER_CONTROL }, - .wMaxPacketSize = { .size = CFG_TUD_ENDPOINT0_SIZE }, + .wMaxPacketSize = CFG_TUD_ENDPOINT0_SIZE, .bInterval = 0 }; @@ -267,7 +267,7 @@ static const tusb_desc_endpoint_t ep0IN_desc = .bEndpointAddress = 0x80, .bmAttributes = { .xfer = TUSB_XFER_CONTROL }, - .wMaxPacketSize = { .size = CFG_TUD_ENDPOINT0_SIZE }, + .wMaxPacketSize = CFG_TUD_ENDPOINT0_SIZE, .bInterval = 0 }; diff --git a/src/portable/microchip/samx7x/dcd_samx7x.c b/src/portable/microchip/samx7x/dcd_samx7x.c index d716e8fed..9e3b43840 100644 --- a/src/portable/microchip/samx7x/dcd_samx7x.c +++ b/src/portable/microchip/samx7x/dcd_samx7x.c @@ -84,7 +84,7 @@ static xfer_ctl_t xfer_status[EP_MAX]; static const tusb_desc_endpoint_t ep0_desc = { .bEndpointAddress = 0x00, - .wMaxPacketSize = { .size = CFG_TUD_ENDPOINT0_SIZE }, + .wMaxPacketSize = CFG_TUD_ENDPOINT0_SIZE, }; TU_ATTR_ALWAYS_INLINE static inline void CleanInValidateCache(uint32_t *addr, int32_t size) -- cgit v1.3.1 From 06de6b725c9d1ccadce0905f85335e4708ad1524 Mon Sep 17 00:00:00 2001 From: hathach Date: Sun, 24 Oct 2021 23:24:46 +0700 Subject: adding generalized dwc2 driver --- hw/bsp/stm32f4/family.mk | 2 +- src/device/dcd_attr.h | 45 +- src/portable/synopsys/dwc2/dcd_dwc2.c | 1155 ++++++++++++++++++++++++ src/portable/synopsys/dwc2/dwc2_gd32.h | 56 ++ src/portable/synopsys/dwc2/dwc2_stm32.h | 72 ++ src/portable/synopsys/dwc2/dwc2_type.h | 1471 +++++++++++++++++++++++++++++++ 6 files changed, 2792 insertions(+), 9 deletions(-) create mode 100644 src/portable/synopsys/dwc2/dcd_dwc2.c create mode 100644 src/portable/synopsys/dwc2/dwc2_gd32.h create mode 100644 src/portable/synopsys/dwc2/dwc2_stm32.h create mode 100644 src/portable/synopsys/dwc2/dwc2_type.h diff --git a/hw/bsp/stm32f4/family.mk b/hw/bsp/stm32f4/family.mk index 584d69405..9811d3371 100644 --- a/hw/bsp/stm32f4/family.mk +++ b/hw/bsp/stm32f4/family.mk @@ -21,7 +21,7 @@ CFLAGS += \ CFLAGS += -Wno-error=cast-align SRC_C += \ - src/portable/st/synopsys/dcd_synopsys.c \ + src/portable/synopsys/dwc2/dcd_dwc2.c \ $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \ $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \ $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \ diff --git a/src/device/dcd_attr.h b/src/device/dcd_attr.h index 44f2cc1d6..3690985c6 100644 --- a/src/device/dcd_attr.h +++ b/src/device/dcd_attr.h @@ -85,24 +85,53 @@ #define DCD_ATTR_ENDPOINT_EXCLUSIVE_NUMBER //------------- ST -------------// -#elif TU_CHECK_MCU(STM32F0) || TU_CHECK_MCU(STM32F1) || TU_CHECK_MCU(STM32F3) || \ - TU_CHECK_MCU(STM32L0) || TU_CHECK_MCU(STM32L1) || TU_CHECK_MCU(STM32L4) - // F1: F102, F103 - // L4: L4x2, L4x3 +#elif TU_CHECK_MCU(STM32F0) #define DCD_ATTR_ENDPOINT_MAX 8 -#elif TU_CHECK_MCU(STM32F2) || TU_CHECK_MCU(STM32F4) || TU_CHECK_MCU(STM32F3) - // F1: F105, F107 only has 4 - // L4: L4x5, L4x6 has 6 - // For most mcu, FS has 4, HS has 6 +#elif TU_CHECK_MCU(STM32F1) + #if defined (STM32F105x8) || defined (STM32F105xB) || defined (STM32F105xC) || \ + defined (STM32F107xB) || defined (STM32F107xC) + #define DCD_ATTR_ENDPOINT_MAX 4 + #define DCD_ATTR_DWC2_STM32 + #else + #define DCD_ATTR_ENDPOINT_MAX 8 + #endif + +#elif TU_CHECK_MCU(STM32F2) + // FS has 4 ep, HS has 5 ep #define DCD_ATTR_ENDPOINT_MAX 6 + #define DCD_ATTR_DWC2_STM32 + +#elif TU_CHECK_MCU(STM32F3) + #define DCD_ATTR_ENDPOINT_MAX 8 + +#elif TU_CHECK_MCU(STM32F4) + // For most mcu, FS has 4, HS has 6. TODO 446/469/479 HS has 9 + #define DCD_ATTR_ENDPOINT_MAX 6 + #define DCD_ATTR_DWC2_STM32 #elif TU_CHECK_MCU(STM32F7) // FS has 6, HS has 9 #define DCD_ATTR_ENDPOINT_MAX 9 + #define DCD_ATTR_DWC2_STM32 #elif TU_CHECK_MCU(STM32H7) #define DCD_ATTR_ENDPOINT_MAX 9 + #define DCD_ATTR_DWC2_STM32 + +#elif TU_CHECK_MCU(STM32L0) || TU_CHECK_MCU(STM32L1) + #define DCD_ATTR_ENDPOINT_MAX 8 + +#elif TU_CHECK_MCU(STM32L4) + #if defined (STM32L475xx) || defined (STM32L476xx) || \ + defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || \ + defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || \ + defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) + #define DCD_ATTR_ENDPOINT_MAX 6 + #define DCD_ATTR_DWC2_STM32 + #else + #define DCD_ATTR_ENDPOINT_MAX 8 + #endif //------------- Sony -------------// #elif TU_CHECK_MCU(CXD56) diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c new file mode 100644 index 000000000..597f4c813 --- /dev/null +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -0,0 +1,1155 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 William D. Jones + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * Copyright (c) 2020 Jan Duempelmann + * Copyright (c) 2020 Reinhard Panhuber + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "tusb_option.h" +#include "device/dcd_attr.h" + +#if TUSB_OPT_DEVICE_ENABLED && (defined(DCD_ATTR_DWC2_STM32) || TU_CHECK_MCU(GD32VF103)) + +#include "dwc2_type.h" + +#if defined(DCD_ATTR_DWC2_STM32) + #include "dwc2_stm32.h" +#elif TU_CHECK_MCU(GD32VF103) + #include "dwc2_gd32.h" +#else + #error "Unsupported MCUs" +#endif + +#include "device/dcd.h" + +// Since TinyUSB doesn't use SOF for now, and this interrupt too often (1ms interval) +// We disable SOF for now until needed later on +#define USE_SOF 0 + +//--------------------------------------------------------------------+ +// MACRO TYPEDEF CONSTANT ENUM +//--------------------------------------------------------------------+ + +// On STM32 we associate Port0 to OTG_FS, and Port1 to OTG_HS +#if TUD_OPT_RHPORT == 0 +#define EP_MAX EP_MAX_FS +#define EP_FIFO_SIZE EP_FIFO_SIZE_FS +#define RHPORT_REGS_BASE USB_OTG_FS_PERIPH_BASE +#define RHPORT_IRQn OTG_FS_IRQn + +#else +#define EP_MAX EP_MAX_HS +#define EP_FIFO_SIZE EP_FIFO_SIZE_HS +#define RHPORT_REGS_BASE USB_OTG_HS_PERIPH_BASE +#define RHPORT_IRQn OTG_HS_IRQn + +#endif + +#define GLOBAL_BASE(_port) ((dwc2_core_t*) RHPORT_REGS_BASE) +#define DEVICE_BASE(_port) ((dwc2_device_t *) (RHPORT_REGS_BASE + USB_OTG_DEVICE_BASE)) +#define OUT_EP_BASE(_port) ((dwc2_epout_t *) (RHPORT_REGS_BASE + USB_OTG_OUT_ENDPOINT_BASE)) +#define IN_EP_BASE(_port) ((dwc2_epin_t *) (RHPORT_REGS_BASE + USB_OTG_IN_ENDPOINT_BASE)) +#define FIFO_BASE(_port, _x) ((volatile uint32_t *) (RHPORT_REGS_BASE + USB_OTG_FIFO_BASE + (_x) * USB_OTG_FIFO_SIZE)) + +enum +{ + DCD_HIGH_SPEED = 0, // Highspeed mode + DCD_FULL_SPEED_USE_HS = 1, // Full speed in Highspeed port (probably with internal PHY) + DCD_FULL_SPEED = 3, // Full speed with internal PHY +}; + +static TU_ATTR_ALIGNED(4) uint32_t _setup_packet[2]; + +typedef struct { + uint8_t * buffer; + tu_fifo_t * ff; + uint16_t total_len; + uint16_t max_size; + uint8_t interval; +} xfer_ctl_t; + +typedef volatile uint32_t * usb_fifo_t; + +xfer_ctl_t xfer_status[EP_MAX][2]; +#define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir] + +// EP0 transfers are limited to 1 packet - larger sizes has to be split +static uint16_t ep0_pending[2]; // Index determines direction as tusb_dir_t type + +// TX FIFO RAM allocation so far in words - RX FIFO size is readily available from usb_otg->GRXFSIZ +static uint16_t _allocated_fifo_words_tx; // TX FIFO size in words (IN EPs) +static bool _out_ep_closed; // Flag to check if RX FIFO size needs an update (reduce its size) + +// Calculate the RX FIFO size according to recommendations from reference manual +static inline uint16_t calc_rx_ff_size(uint16_t ep_size) +{ + return 15 + 2*(ep_size/4) + 2*EP_MAX; +} + +static void update_grxfsiz(uint8_t rhport) +{ + (void) rhport; + + dwc2_core_t * usb_otg = GLOBAL_BASE(rhport); + + // Determine largest EP size for RX FIFO + uint16_t max_epsize = 0; + for (uint8_t epnum = 0; epnum < EP_MAX; epnum++) + { + max_epsize = tu_max16(max_epsize, xfer_status[epnum][TUSB_DIR_OUT].max_size); + } + + // Update size of RX FIFO + usb_otg->GRXFSIZ = calc_rx_ff_size(max_epsize); +} + +// Setup the control endpoint 0. +static void bus_reset(uint8_t rhport) +{ + (void) rhport; + + dwc2_core_t * usb_otg = GLOBAL_BASE(rhport); + dwc2_device_t * dev = DEVICE_BASE(rhport); + dwc2_epout_t * out_ep = OUT_EP_BASE(rhport); + dwc2_epin_t * in_ep = IN_EP_BASE(rhport); + + tu_memclr(xfer_status, sizeof(xfer_status)); + _out_ep_closed = false; + + // clear device address + dev->DCFG &= ~USB_OTG_DCFG_DAD_Msk; + + // 1. NAK for all OUT endpoints + for(uint8_t n = 0; n < EP_MAX; n++) { + out_ep[n].DOEPCTL |= USB_OTG_DOEPCTL_SNAK; + } + + // 2. Un-mask interrupt bits + dev->DAINTMSK = (1 << USB_OTG_DAINTMSK_OEPM_Pos) | (1 << USB_OTG_DAINTMSK_IEPM_Pos); + dev->DOEPMSK = USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM; + dev->DIEPMSK = USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM; + + // "USB Data FIFOs" section in reference manual + // Peripheral FIFO architecture + // + // The FIFO is split up in a lower part where the RX FIFO is located and an upper part where the TX FIFOs start. + // We do this to allow the RX FIFO to grow dynamically which is possible since the free space is located + // between the RX and TX FIFOs. This is required by ISO OUT EPs which need a bigger FIFO than the standard + // configuration done below. + // + // Dynamically FIFO sizes are of interest only for ISO EPs since all others are usually not opened and closed. + // All EPs other than ISO are opened as soon as the driver starts up i.e. when the host sends a + // configure interface command. Hence, all IN EPs other the ISO will be located at the top. IN ISO EPs are usually + // opened when the host sends an additional command: setInterface. At this point in time + // the ISO EP will be located next to the free space and can change its size. In case more IN EPs change its size + // an additional memory + // + // --------------- 320 or 1024 ( 1280 or 4096 bytes ) + // | IN FIFO 0 | + // --------------- (320 or 1024) - 16 + // | IN FIFO 1 | + // --------------- (320 or 1024) - 16 - x + // | . . . . | + // --------------- (320 or 1024) - 16 - x - y - ... - z + // | IN FIFO MAX | + // --------------- + // | FREE | + // --------------- GRXFSIZ + // | OUT FIFO | + // | ( Shared ) | + // --------------- 0 + // + // According to "FIFO RAM allocation" section in RM, FIFO RAM are allocated as follows (each word 32-bits): + // - Each EP IN needs at least max packet size, 16 words is sufficient for EP0 IN + // + // - All EP OUT shared a unique OUT FIFO which uses + // - 13 for setup packets + control words (up to 3 setup packets). + // - 1 for global NAK (not required/used here). + // - Largest-EPsize / 4 + 1. ( FS: 64 bytes, HS: 512 bytes). Recommended is "2 x (Largest-EPsize/4) + 1" + // - 2 for each used OUT endpoint + // + // Therefore GRXFSIZ = 13 + 1 + 1 + 2 x (Largest-EPsize/4) + 2 x EPOUTnum + // - FullSpeed (64 Bytes ): GRXFSIZ = 15 + 2 x 16 + 2 x EP_MAX = 47 + 2 x EP_MAX + // - Highspeed (512 bytes): GRXFSIZ = 15 + 2 x 128 + 2 x EP_MAX = 271 + 2 x EP_MAX + // + // NOTE: Largest-EPsize & EPOUTnum is actual used endpoints in configuration. Since DCD has no knowledge + // of the overall picture yet. We will use the worst scenario: largest possible + EP_MAX + // + // For Isochronous, largest EP size can be 1023/1024 for FS/HS respectively. In addition if multiple ISO + // are enabled at least "2 x (Largest-EPsize/4) + 1" are recommended. Maybe provide a macro for application to + // overwrite this. + + usb_otg->GRXFSIZ = calc_rx_ff_size(TUD_OPT_HIGH_SPEED ? 512 : 64); + + _allocated_fifo_words_tx = 16; + + // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word ) + usb_otg->DIEPTXF0_HNPTXFSIZ = (16 << USB_OTG_TX0FD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx); + + // Fixed control EP0 size to 64 bytes + in_ep[0].DIEPCTL &= ~(0x03 << USB_OTG_DIEPCTL_MPSIZ_Pos); + xfer_status[0][TUSB_DIR_OUT].max_size = xfer_status[0][TUSB_DIR_IN].max_size = 64; + + out_ep[0].DOEPTSIZ |= (3 << USB_OTG_DOEPTSIZ_STUPCNT_Pos); + + usb_otg->GINTMSK |= USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IEPINT; +} + +// Set turn-around timeout according to link speed +extern uint32_t SystemCoreClock; +static void set_turnaround(dwc2_core_t * usb_otg, tusb_speed_t speed) +{ + usb_otg->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT; + + if ( speed == TUSB_SPEED_HIGH ) + { + // Use fixed 0x09 for Highspeed + usb_otg->GUSBCFG |= (0x09 << USB_OTG_GUSBCFG_TRDT_Pos); + } + else + { + // Turnaround timeout depends on the MCU clock + uint32_t turnaround; + + if ( SystemCoreClock >= 32000000U ) + turnaround = 0x6U; + else if ( SystemCoreClock >= 27500000U ) + turnaround = 0x7U; + else if ( SystemCoreClock >= 24000000U ) + turnaround = 0x8U; + else if ( SystemCoreClock >= 21800000U ) + turnaround = 0x9U; + else if ( SystemCoreClock >= 20000000U ) + turnaround = 0xAU; + else if ( SystemCoreClock >= 18500000U ) + turnaround = 0xBU; + else if ( SystemCoreClock >= 17200000U ) + turnaround = 0xCU; + else if ( SystemCoreClock >= 16000000U ) + turnaround = 0xDU; + else if ( SystemCoreClock >= 15000000U ) + turnaround = 0xEU; + else + turnaround = 0xFU; + + // Fullspeed depends on MCU clocks, but we will use 0x06 for 32+ Mhz + usb_otg->GUSBCFG |= (turnaround << USB_OTG_GUSBCFG_TRDT_Pos); + } +} + +static tusb_speed_t get_speed(uint8_t rhport) +{ + (void) rhport; + dwc2_device_t * dev = DEVICE_BASE(rhport); + uint32_t const enum_spd = (dev->DSTS & USB_OTG_DSTS_ENUMSPD_Msk) >> USB_OTG_DSTS_ENUMSPD_Pos; + return (enum_spd == DCD_HIGH_SPEED) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL; +} + +static void set_speed(uint8_t rhport, tusb_speed_t speed) +{ + uint32_t bitvalue; + + if ( rhport == 1 ) + { + bitvalue = ((TUSB_SPEED_HIGH == speed) ? DCD_HIGH_SPEED : DCD_FULL_SPEED_USE_HS); + } + else + { + bitvalue = DCD_FULL_SPEED; + } + + dwc2_device_t * dev = DEVICE_BASE(rhport); + + // Clear and set speed bits + dev->DCFG &= ~(3 << USB_OTG_DCFG_DSPD_Pos); + dev->DCFG |= (bitvalue << USB_OTG_DCFG_DSPD_Pos); +} + +#if defined(USB_HS_PHYC) +static bool USB_HS_PHYCInit(void) +{ + USB_HS_PHYC_GlobalTypeDef *usb_hs_phyc = (USB_HS_PHYC_GlobalTypeDef*) USB_HS_PHYC_CONTROLLER_BASE; + + // Enable LDO + usb_hs_phyc->USB_HS_PHYC_LDO |= USB_HS_PHYC_LDO_ENABLE; + + // Wait until LDO ready + while ( 0 == (usb_hs_phyc->USB_HS_PHYC_LDO & USB_HS_PHYC_LDO_STATUS) ) {} + + uint32_t phyc_pll = 0; + + // TODO Try to get HSE_VALUE from registers instead of depending CFLAGS + switch ( HSE_VALUE ) + { + case 12000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12MHZ ; break; + case 12500000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12_5MHZ ; break; + case 16000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_16MHZ ; break; + case 24000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_24MHZ ; break; + case 25000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_25MHZ ; break; + case 32000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_Msk ; break; // Value not defined in header + default: + TU_ASSERT(0); + } + usb_hs_phyc->USB_HS_PHYC_PLL = phyc_pll; + + // Control the tuning interface of the High Speed PHY + // Use magic value (USB_HS_PHYC_TUNE_VALUE) from ST driver + usb_hs_phyc->USB_HS_PHYC_TUNE |= 0x00000F13U; + + // Enable PLL internal PHY + usb_hs_phyc->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN; + + // Original ST code has 2 ms delay for PLL stabilization. + // Primitive test shows that more than 10 USB un/replug cycle showed no error with enumeration + + return true; +} +#endif + +static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t const dir, uint16_t const num_packets, uint16_t total_bytes) +{ + (void) rhport; + + dwc2_device_t * dev = DEVICE_BASE(rhport); + dwc2_epout_t * out_ep = OUT_EP_BASE(rhport); + dwc2_epin_t * in_ep = IN_EP_BASE(rhport); + + // EP0 is limited to one packet each xfer + // We use multiple transaction of xfer->max_size length to get a whole transfer done + if(epnum == 0) { + xfer_ctl_t * const xfer = XFER_CTL_BASE(epnum, dir); + total_bytes = tu_min16(ep0_pending[dir], xfer->max_size); + ep0_pending[dir] -= total_bytes; + } + + // IN and OUT endpoint xfers are interrupt-driven, we just schedule them here. + if(dir == TUSB_DIR_IN) { + // A full IN transfer (multiple packets, possibly) triggers XFRC. + in_ep[epnum].DIEPTSIZ = (num_packets << USB_OTG_DIEPTSIZ_PKTCNT_Pos) | + ((total_bytes << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) & USB_OTG_DIEPTSIZ_XFRSIZ_Msk); + + in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_EPENA | USB_OTG_DIEPCTL_CNAK; + // For ISO endpoint set correct odd/even bit for next frame. + if ((in_ep[epnum].DIEPCTL & USB_OTG_DIEPCTL_EPTYP) == USB_OTG_DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) + { + // Take odd/even bit from frame counter. + uint32_t const odd_frame_now = (dev->DSTS & (1u << USB_OTG_DSTS_FNSOF_Pos)); + in_ep[epnum].DIEPCTL |= (odd_frame_now ? USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk : USB_OTG_DIEPCTL_SODDFRM_Msk); + } + // Enable fifo empty interrupt only if there are something to put in the fifo. + if(total_bytes != 0) { + dev->DIEPEMPMSK |= (1 << epnum); + } + } else { + // A full OUT transfer (multiple packets, possibly) triggers XFRC. + out_ep[epnum].DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT_Msk | USB_OTG_DOEPTSIZ_XFRSIZ); + out_ep[epnum].DOEPTSIZ |= (num_packets << USB_OTG_DOEPTSIZ_PKTCNT_Pos) | + ((total_bytes << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) & USB_OTG_DOEPTSIZ_XFRSIZ_Msk); + + out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_CNAK; + if ((out_ep[epnum].DOEPCTL & USB_OTG_DOEPCTL_EPTYP) == USB_OTG_DOEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) + { + // Take odd/even bit from frame counter. + uint32_t const odd_frame_now = (dev->DSTS & (1u << USB_OTG_DSTS_FNSOF_Pos)); + out_ep[epnum].DOEPCTL |= (odd_frame_now ? USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk : USB_OTG_DOEPCTL_SODDFRM_Msk); + } + } +} + +/*------------------------------------------------------------------*/ +/* Controller API + *------------------------------------------------------------------*/ +void dcd_init (uint8_t rhport) +{ + // Programming model begins in the last section of the chapter on the USB + // peripheral in each Reference Manual. + + dwc2_core_t * usb_otg = GLOBAL_BASE(rhport); + + // No HNP/SRP (no OTG support), program timeout later. + if ( rhport == 1 ) + { + // On selected MCUs HS port1 can be used with external PHY via ULPI interface +#if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED + // deactivate internal PHY + usb_otg->GCCFG &= ~USB_OTG_GCCFG_PWRDWN; + + // Init The UTMI Interface + usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL); + + // Select default internal VBUS Indicator and Drive for ULPI + usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); +#else + usb_otg->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; +#endif + +#if defined(USB_HS_PHYC) + // Highspeed with embedded UTMI PHYC + + // Select UTMI Interface + usb_otg->GUSBCFG &= ~USB_OTG_GUSBCFG_ULPI_UTMI_SEL; + usb_otg->GCCFG |= USB_OTG_GCCFG_PHYHSEN; + + // Enables control of a High Speed USB PHY + USB_HS_PHYCInit(); +#endif + } else + { + // Enable internal PHY + usb_otg->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; + } + + // Reset core after selecting PHY + // Wait AHB IDLE, reset then wait until it is cleared + while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U) {} + usb_otg->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; + while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST) {} + + // Restart PHY clock + *((volatile uint32_t *)(RHPORT_REGS_BASE + USB_OTG_PCGCCTL_BASE)) = 0; + + // Clear all interrupts + usb_otg->GINTSTS |= usb_otg->GINTSTS; + + // Required as part of core initialization. + // TODO: How should mode mismatch be handled? It will cause + // the core to stop working/require reset. + usb_otg->GINTMSK |= USB_OTG_GINTMSK_OTGINT | USB_OTG_GINTMSK_MMISM; + + dwc2_device_t * dev = DEVICE_BASE(rhport); + + // If USB host misbehaves during status portion of control xfer + // (non zero-length packet), send STALL back and discard. + dev->DCFG |= USB_OTG_DCFG_NZLSOHSK; + + set_speed(rhport, TUD_OPT_HIGH_SPEED ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL); + + // Enable internal USB transceiver, unless using HS core (port 1) with external PHY. + if (!(rhport == 1 && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED))) usb_otg->GCCFG |= USB_OTG_GCCFG_PWRDWN; + + usb_otg->GINTMSK |= USB_OTG_GINTMSK_USBRST | USB_OTG_GINTMSK_ENUMDNEM | + USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_WUIM | + USB_OTG_GINTMSK_RXFLVLM | (USE_SOF ? USB_OTG_GINTMSK_SOFM : 0); + + // Enable global interrupt + usb_otg->GAHBCFG |= USB_OTG_GAHBCFG_GINT; + + dcd_connect(rhport); +} + +void dcd_int_enable (uint8_t rhport) +{ + (void) rhport; + NVIC_EnableIRQ(RHPORT_IRQn); +} + +void dcd_int_disable (uint8_t rhport) +{ + (void) rhport; + NVIC_DisableIRQ(RHPORT_IRQn); +} + +void dcd_set_address (uint8_t rhport, uint8_t dev_addr) +{ + dwc2_device_t * dev = DEVICE_BASE(rhport); + dev->DCFG = (dev->DCFG & ~USB_OTG_DCFG_DAD_Msk) | (dev_addr << USB_OTG_DCFG_DAD_Pos); + + // Response with status after changing device address + dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0); +} + +static void remote_wakeup_delay(void) +{ + // try to delay for 1 ms + uint32_t count = SystemCoreClock / 1000; + while ( count-- ) + { + __NOP(); + } +} + +void dcd_remote_wakeup(uint8_t rhport) +{ + (void) rhport; + + dwc2_core_t * usb_otg = GLOBAL_BASE(rhport); + dwc2_device_t * dev = DEVICE_BASE(rhport); + + // set remote wakeup + dev->DCTL |= USB_OTG_DCTL_RWUSIG; + + // enable SOF to detect bus resume + usb_otg->GINTSTS = USB_OTG_GINTSTS_SOF; + usb_otg->GINTMSK |= USB_OTG_GINTMSK_SOFM; + + // Per specs: remote wakeup signal bit must be clear within 1-15ms + remote_wakeup_delay(); + + dev->DCTL &= ~USB_OTG_DCTL_RWUSIG; +} + +void dcd_connect(uint8_t rhport) +{ + (void) rhport; + dwc2_device_t * dev = DEVICE_BASE(rhport); + dev->DCTL &= ~USB_OTG_DCTL_SDIS; +} + +void dcd_disconnect(uint8_t rhport) +{ + (void) rhport; + dwc2_device_t * dev = DEVICE_BASE(rhport); + dev->DCTL |= USB_OTG_DCTL_SDIS; +} + + +/*------------------------------------------------------------------*/ +/* DCD Endpoint port + *------------------------------------------------------------------*/ + +bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) +{ + (void) rhport; + + dwc2_core_t * usb_otg = GLOBAL_BASE(rhport); + dwc2_device_t * dev = DEVICE_BASE(rhport); + dwc2_epout_t * out_ep = OUT_EP_BASE(rhport); + dwc2_epin_t * in_ep = IN_EP_BASE(rhport); + + uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress); + uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress); + + TU_ASSERT(epnum < EP_MAX); + + xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir); + xfer->max_size = tu_edpt_packet_size(desc_edpt); + xfer->interval = desc_edpt->bInterval; + + uint16_t const fifo_size = (xfer->max_size + 3) / 4; // Round up to next full word + + if(dir == TUSB_DIR_OUT) + { + // Calculate required size of RX FIFO + uint16_t const sz = calc_rx_ff_size(4*fifo_size); + + // If size_rx needs to be extended check if possible and if so enlarge it + if (usb_otg->GRXFSIZ < sz) + { + TU_ASSERT(sz + _allocated_fifo_words_tx <= EP_FIFO_SIZE/4); + + // Enlarge RX FIFO + usb_otg->GRXFSIZ = sz; + } + + out_ep[epnum].DOEPCTL |= (1 << USB_OTG_DOEPCTL_USBAEP_Pos) | + (desc_edpt->bmAttributes.xfer << USB_OTG_DOEPCTL_EPTYP_Pos) | + (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_OTG_DOEPCTL_SD0PID_SEVNFRM : 0) | + (xfer->max_size << USB_OTG_DOEPCTL_MPSIZ_Pos); + + dev->DAINTMSK |= (1 << (USB_OTG_DAINTMSK_OEPM_Pos + epnum)); + } + else + { + // "USB Data FIFOs" section in reference manual + // Peripheral FIFO architecture + // + // --------------- 320 or 1024 ( 1280 or 4096 bytes ) + // | IN FIFO 0 | + // --------------- (320 or 1024) - 16 + // | IN FIFO 1 | + // --------------- (320 or 1024) - 16 - x + // | . . . . | + // --------------- (320 or 1024) - 16 - x - y - ... - z + // | IN FIFO MAX | + // --------------- + // | FREE | + // --------------- GRXFSIZ + // | OUT FIFO | + // | ( Shared ) | + // --------------- 0 + // + // In FIFO is allocated by following rules: + // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n". + + // Check if free space is available + TU_ASSERT(_allocated_fifo_words_tx + fifo_size + usb_otg->GRXFSIZ <= EP_FIFO_SIZE/4); + + _allocated_fifo_words_tx += fifo_size; + + TU_LOG(2, " Allocated %u bytes at offset %u", fifo_size*4, EP_FIFO_SIZE-_allocated_fifo_words_tx*4); + + // DIEPTXF starts at FIFO #1. + // Both TXFD and TXSA are in unit of 32-bit words. + usb_otg->DIEPTXF[epnum - 1] = (fifo_size << USB_OTG_DIEPTXF_INEPTXFD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx); + + in_ep[epnum].DIEPCTL |= (1 << USB_OTG_DIEPCTL_USBAEP_Pos) | + (epnum << USB_OTG_DIEPCTL_TXFNUM_Pos) | + (desc_edpt->bmAttributes.xfer << USB_OTG_DIEPCTL_EPTYP_Pos) | + (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_OTG_DIEPCTL_SD0PID_SEVNFRM : 0) | + (xfer->max_size << USB_OTG_DIEPCTL_MPSIZ_Pos); + + dev->DAINTMSK |= (1 << (USB_OTG_DAINTMSK_IEPM_Pos + epnum)); + } + + return true; +} + +// Close all non-control endpoints, cancel all pending transfers if any. +void dcd_edpt_close_all (uint8_t rhport) +{ + (void) rhport; + +// dwc2_core_t * usb_otg = GLOBAL_BASE(rhport); + dwc2_device_t * dev = DEVICE_BASE(rhport); + dwc2_epout_t * out_ep = OUT_EP_BASE(rhport); + dwc2_epin_t * in_ep = IN_EP_BASE(rhport); + + // Disable non-control interrupt + dev->DAINTMSK = (1 << USB_OTG_DAINTMSK_OEPM_Pos) | (1 << USB_OTG_DAINTMSK_IEPM_Pos); + + for(uint8_t n = 1; n < EP_MAX; n++) + { + // disable OUT endpoint + out_ep[n].DOEPCTL = 0; + xfer_status[n][TUSB_DIR_OUT].max_size = 0; + + // disable IN endpoint + in_ep[n].DIEPCTL = 0; + xfer_status[n][TUSB_DIR_IN].max_size = 0; + } + + // reset allocated fifo IN + _allocated_fifo_words_tx = 16; +} + +bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) +{ + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir); + xfer->buffer = buffer; + xfer->ff = NULL; + xfer->total_len = total_bytes; + + // EP0 can only handle one packet + if(epnum == 0) { + ep0_pending[dir] = total_bytes; + // Schedule the first transaction for EP0 transfer + edpt_schedule_packets(rhport, epnum, dir, 1, ep0_pending[dir]); + return true; + } + + uint16_t num_packets = (total_bytes / xfer->max_size); + uint16_t const short_packet_size = total_bytes % xfer->max_size; + + // Zero-size packet is special case. + if(short_packet_size > 0 || (total_bytes == 0)) { + num_packets++; + } + + // Schedule packets to be sent within interrupt + edpt_schedule_packets(rhport, epnum, dir, num_packets, total_bytes); + + return true; +} + +// The number of bytes has to be given explicitly to allow more flexible control of how many +// bytes should be written and second to keep the return value free to give back a boolean +// success message. If total_bytes is too big, the FIFO will copy only what is available +// into the USB buffer! +bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes) +{ + // USB buffers always work in bytes so to avoid unnecessary divisions we demand item_size = 1 + TU_ASSERT(ff->item_size == 1); + + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir); + xfer->buffer = NULL; + xfer->ff = ff; + xfer->total_len = total_bytes; + + uint16_t num_packets = (total_bytes / xfer->max_size); + uint16_t const short_packet_size = total_bytes % xfer->max_size; + + // Zero-size packet is special case. + if(short_packet_size > 0 || (total_bytes == 0)) num_packets++; + + // Schedule packets to be sent within interrupt + edpt_schedule_packets(rhport, epnum, dir, num_packets, total_bytes); + + return true; +} + +static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall) +{ + (void) rhport; + + dwc2_core_t * usb_otg = GLOBAL_BASE(rhport); + dwc2_device_t * dev = DEVICE_BASE(rhport); + dwc2_epout_t * out_ep = OUT_EP_BASE(rhport); + dwc2_epin_t * in_ep = IN_EP_BASE(rhport); + + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + if(dir == TUSB_DIR_IN) { + // Only disable currently enabled non-control endpoint + if ( (epnum == 0) || !(in_ep[epnum].DIEPCTL & USB_OTG_DIEPCTL_EPENA) ){ + in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SNAK | (stall ? USB_OTG_DIEPCTL_STALL : 0); + } else { + // Stop transmitting packets and NAK IN xfers. + in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SNAK; + while((in_ep[epnum].DIEPINT & USB_OTG_DIEPINT_INEPNE) == 0); + + // Disable the endpoint. + in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_EPDIS | (stall ? USB_OTG_DIEPCTL_STALL : 0); + while((in_ep[epnum].DIEPINT & USB_OTG_DIEPINT_EPDISD_Msk) == 0); + in_ep[epnum].DIEPINT = USB_OTG_DIEPINT_EPDISD; + } + + // Flush the FIFO, and wait until we have confirmed it cleared. + usb_otg->GRSTCTL |= (epnum << USB_OTG_GRSTCTL_TXFNUM_Pos); + usb_otg->GRSTCTL |= USB_OTG_GRSTCTL_TXFFLSH; + while((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH_Msk) != 0); + } else { + // Only disable currently enabled non-control endpoint + if ( (epnum == 0) || !(out_ep[epnum].DOEPCTL & USB_OTG_DOEPCTL_EPENA) ){ + out_ep[epnum].DOEPCTL |= stall ? USB_OTG_DOEPCTL_STALL : 0; + } else { + // Asserting GONAK is required to STALL an OUT endpoint. + // Simpler to use polling here, we don't use the "B"OUTNAKEFF interrupt + // anyway, and it can't be cleared by user code. If this while loop never + // finishes, we have bigger problems than just the stack. + dev->DCTL |= USB_OTG_DCTL_SGONAK; + while((usb_otg->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF_Msk) == 0); + + // Ditto here- disable the endpoint. + out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_EPDIS | (stall ? USB_OTG_DOEPCTL_STALL : 0); + while((out_ep[epnum].DOEPINT & USB_OTG_DOEPINT_EPDISD_Msk) == 0); + out_ep[epnum].DOEPINT = USB_OTG_DOEPINT_EPDISD; + + // Allow other OUT endpoints to keep receiving. + dev->DCTL |= USB_OTG_DCTL_CGONAK; + } + } +} + +/** + * Close an endpoint. + */ +void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr) +{ + dwc2_core_t * usb_otg = GLOBAL_BASE(rhport); + + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + dcd_edpt_disable(rhport, ep_addr, false); + + // Update max_size + xfer_status[epnum][dir].max_size = 0; // max_size = 0 marks a disabled EP - required for changing FIFO allocation + + if (dir == TUSB_DIR_IN) + { + uint16_t const fifo_size = (usb_otg->DIEPTXF[epnum - 1] & USB_OTG_DIEPTXF_INEPTXFD_Msk) >> USB_OTG_DIEPTXF_INEPTXFD_Pos; + uint16_t const fifo_start = (usb_otg->DIEPTXF[epnum - 1] & USB_OTG_DIEPTXF_INEPTXSA_Msk) >> USB_OTG_DIEPTXF_INEPTXSA_Pos; + // For now only the last opened endpoint can be closed without fuss. + TU_ASSERT(fifo_start == EP_FIFO_SIZE/4 - _allocated_fifo_words_tx,); + _allocated_fifo_words_tx -= fifo_size; + } + else + { + _out_ep_closed = true; // Set flag such that RX FIFO gets reduced in size once RX FIFO is empty + } +} + +void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr) +{ + dcd_edpt_disable(rhport, ep_addr, true); +} + +void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) +{ + (void) rhport; + + dwc2_epout_t * out_ep = OUT_EP_BASE(rhport); + dwc2_epin_t * in_ep = IN_EP_BASE(rhport); + + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + // Clear stall and reset data toggle + if(dir == TUSB_DIR_IN) { + in_ep[epnum].DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; + in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; + } else { + out_ep[epnum].DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; + out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; + } +} + +/*------------------------------------------------------------------*/ + +// Read a single data packet from receive FIFO +static void read_fifo_packet(uint8_t rhport, uint8_t * dst, uint16_t len) +{ + (void) rhport; + + usb_fifo_t rx_fifo = FIFO_BASE(rhport, 0); + + // Reading full available 32 bit words from fifo + uint16_t full_words = len >> 2; + for(uint16_t i = 0; i < full_words; i++) { + uint32_t tmp = *rx_fifo; + dst[0] = tmp & 0x000000FF; + dst[1] = (tmp & 0x0000FF00) >> 8; + dst[2] = (tmp & 0x00FF0000) >> 16; + dst[3] = (tmp & 0xFF000000) >> 24; + dst += 4; + } + + // Read the remaining 1-3 bytes from fifo + uint8_t bytes_rem = len & 0x03; + if(bytes_rem != 0) { + uint32_t tmp = *rx_fifo; + dst[0] = tmp & 0x000000FF; + if(bytes_rem > 1) { + dst[1] = (tmp & 0x0000FF00) >> 8; + } + if(bytes_rem > 2) { + dst[2] = (tmp & 0x00FF0000) >> 16; + } + } +} + +// Write a single data packet to EPIN FIFO +static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t * src, uint16_t len) +{ + (void) rhport; + + usb_fifo_t tx_fifo = FIFO_BASE(rhport, fifo_num); + + // Pushing full available 32 bit words to fifo + uint16_t full_words = len >> 2; + for(uint16_t i = 0; i < full_words; i++){ + *tx_fifo = (src[3] << 24) | (src[2] << 16) | (src[1] << 8) | src[0]; + src += 4; + } + + // Write the remaining 1-3 bytes into fifo + uint8_t bytes_rem = len & 0x03; + if(bytes_rem){ + uint32_t tmp_word = 0; + tmp_word |= src[0]; + if(bytes_rem > 1){ + tmp_word |= src[1] << 8; + } + if(bytes_rem > 2){ + tmp_word |= src[2] << 16; + } + *tx_fifo = tmp_word; + } +} + +static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep) { + dwc2_core_t * usb_otg = GLOBAL_BASE(rhport); + usb_fifo_t rx_fifo = FIFO_BASE(rhport, 0); + + // Pop control word off FIFO + uint32_t ctl_word = usb_otg->GRXSTSP; + uint8_t pktsts = (ctl_word & USB_OTG_GRXSTSP_PKTSTS_Msk) >> USB_OTG_GRXSTSP_PKTSTS_Pos; + uint8_t epnum = (ctl_word & USB_OTG_GRXSTSP_EPNUM_Msk) >> USB_OTG_GRXSTSP_EPNUM_Pos; + uint16_t bcnt = (ctl_word & USB_OTG_GRXSTSP_BCNT_Msk) >> USB_OTG_GRXSTSP_BCNT_Pos; + + switch(pktsts) { + case 0x01: // Global OUT NAK (Interrupt) + break; + + case 0x02: // Out packet recvd + { + xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT); + + // Read packet off RxFIFO + if (xfer->ff) + { + // Ring buffer + tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void *)(uintptr_t) rx_fifo, bcnt); + } + else + { + // Linear buffer + read_fifo_packet(rhport, xfer->buffer, bcnt); + + // Increment pointer to xfer data + xfer->buffer += bcnt; + } + + // Truncate transfer length in case of short packet + if(bcnt < xfer->max_size) { + xfer->total_len -= (out_ep[epnum].DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ_Msk) >> USB_OTG_DOEPTSIZ_XFRSIZ_Pos; + if(epnum == 0) { + xfer->total_len -= ep0_pending[TUSB_DIR_OUT]; + ep0_pending[TUSB_DIR_OUT] = 0; + } + } + } + break; + + case 0x03: // Out packet done (Interrupt) + break; + + case 0x04: // Setup packet done (Interrupt) + out_ep[epnum].DOEPTSIZ |= (3 << USB_OTG_DOEPTSIZ_STUPCNT_Pos); + break; + + case 0x06: // Setup packet recvd + // We can receive up to three setup packets in succession, but + // only the last one is valid. + _setup_packet[0] = (* rx_fifo); + _setup_packet[1] = (* rx_fifo); + break; + + default: // Invalid + TU_BREAKPOINT(); + break; + } +} + +static void handle_epout_ints(uint8_t rhport, dwc2_device_t * dev, dwc2_epout_t * out_ep) { + // DAINT for a given EP clears when DOEPINTx is cleared. + // OEPINT will be cleared when DAINT's out bits are cleared. + for(uint8_t n = 0; n < EP_MAX; n++) { + xfer_ctl_t * xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT); + + if(dev->DAINT & (1 << (USB_OTG_DAINT_OEPINT_Pos + n))) { + // SETUP packet Setup Phase done. + if(out_ep[n].DOEPINT & USB_OTG_DOEPINT_STUP) { + out_ep[n].DOEPINT = USB_OTG_DOEPINT_STUP; + dcd_event_setup_received(rhport, (uint8_t*) &_setup_packet[0], true); + } + + // OUT XFER complete + if(out_ep[n].DOEPINT & USB_OTG_DOEPINT_XFRC) { + out_ep[n].DOEPINT = USB_OTG_DOEPINT_XFRC; + + // EP0 can only handle one packet + if((n == 0) && ep0_pending[TUSB_DIR_OUT]) { + // Schedule another packet to be received. + edpt_schedule_packets(rhport, n, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]); + } else { + dcd_event_xfer_complete(rhport, n, xfer->total_len, XFER_RESULT_SUCCESS, true); + } + } + } + } +} + +static void handle_epin_ints(uint8_t rhport, dwc2_device_t * dev, dwc2_epin_t * in_ep) { + // DAINT for a given EP clears when DIEPINTx is cleared. + // IEPINT will be cleared when DAINT's out bits are cleared. + for ( uint8_t n = 0; n < EP_MAX; n++ ) + { + xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_IN); + + if ( dev->DAINT & (1 << (USB_OTG_DAINT_IEPINT_Pos + n)) ) + { + // IN XFER complete (entire xfer). + if ( in_ep[n].DIEPINT & USB_OTG_DIEPINT_XFRC ) + { + in_ep[n].DIEPINT = USB_OTG_DIEPINT_XFRC; + + // EP0 can only handle one packet + if((n == 0) && ep0_pending[TUSB_DIR_IN]) { + // Schedule another packet to be transmitted. + edpt_schedule_packets(rhport, n, TUSB_DIR_IN, 1, ep0_pending[TUSB_DIR_IN]); + } else { + dcd_event_xfer_complete(rhport, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true); + } + } + + // XFER FIFO empty + if ( (in_ep[n].DIEPINT & USB_OTG_DIEPINT_TXFE) && (dev->DIEPEMPMSK & (1 << n)) ) + { + // DIEPINT's TXFE bit is read-only, software cannot clear it. + // It will only be cleared by hardware when written bytes is more than + // - 64 bytes or + // - Half of TX FIFO size (configured by DIEPTXF) + + uint16_t remaining_packets = (in_ep[n].DIEPTSIZ & USB_OTG_DIEPTSIZ_PKTCNT_Msk) >> USB_OTG_DIEPTSIZ_PKTCNT_Pos; + + // Process every single packet (only whole packets can be written to fifo) + for(uint16_t i = 0; i < remaining_packets; i++) + { + uint16_t const remaining_bytes = (in_ep[n].DIEPTSIZ & USB_OTG_DIEPTSIZ_XFRSIZ_Msk) >> USB_OTG_DIEPTSIZ_XFRSIZ_Pos; + + // Packet can not be larger than ep max size + uint16_t const packet_size = tu_min16(remaining_bytes, xfer->max_size); + + // It's only possible to write full packets into FIFO. Therefore DTXFSTS register of current + // EP has to be checked if the buffer can take another WHOLE packet + if(packet_size > ((in_ep[n].DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV_Msk) << 2)) break; + + // Push packet to Tx-FIFO + if (xfer->ff) + { + usb_fifo_t tx_fifo = FIFO_BASE(rhport, n); + tu_fifo_read_n_const_addr_full_words(xfer->ff, (void *)(uintptr_t) tx_fifo, packet_size); + } + else + { + write_fifo_packet(rhport, n, xfer->buffer, packet_size); + + // Increment pointer to xfer data + xfer->buffer += packet_size; + } + } + + // Turn off TXFE if all bytes are written. + if (((in_ep[n].DIEPTSIZ & USB_OTG_DIEPTSIZ_XFRSIZ_Msk) >> USB_OTG_DIEPTSIZ_XFRSIZ_Pos) == 0) + { + dev->DIEPEMPMSK &= ~(1 << n); + } + } + } + } +} + +void dcd_int_handler(uint8_t rhport) +{ + dwc2_core_t * usb_otg = GLOBAL_BASE(rhport); + dwc2_device_t * dev = DEVICE_BASE(rhport); + dwc2_epout_t * out_ep = OUT_EP_BASE(rhport); + dwc2_epin_t * in_ep = IN_EP_BASE(rhport); + + uint32_t const int_status = usb_otg->GINTSTS & usb_otg->GINTMSK; + + if(int_status & USB_OTG_GINTSTS_USBRST) + { + // USBRST is start of reset. + usb_otg->GINTSTS = USB_OTG_GINTSTS_USBRST; + bus_reset(rhport); + } + + if(int_status & USB_OTG_GINTSTS_ENUMDNE) + { + // ENUMDNE is the end of reset where speed of the link is detected + + usb_otg->GINTSTS = USB_OTG_GINTSTS_ENUMDNE; + + tusb_speed_t const speed = get_speed(rhport); + + set_turnaround(usb_otg, speed); + dcd_event_bus_reset(rhport, speed, true); + } + + if(int_status & USB_OTG_GINTSTS_USBSUSP) + { + usb_otg->GINTSTS = USB_OTG_GINTSTS_USBSUSP; + dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); + } + + if(int_status & USB_OTG_GINTSTS_WKUINT) + { + usb_otg->GINTSTS = USB_OTG_GINTSTS_WKUINT; + dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true); + } + + // TODO check USB_OTG_GINTSTS_DISCINT for disconnect detection + // if(int_status & USB_OTG_GINTSTS_DISCINT) + + if(int_status & USB_OTG_GINTSTS_OTGINT) + { + // OTG INT bit is read-only + uint32_t const otg_int = usb_otg->GOTGINT; + + if (otg_int & USB_OTG_GOTGINT_SEDET) + { + dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true); + } + + usb_otg->GOTGINT = otg_int; + } + + if(int_status & USB_OTG_GINTSTS_SOF) + { + usb_otg->GINTSTS = USB_OTG_GINTSTS_SOF; + + // Disable SOF interrupt since currently only used for remote wakeup detection + usb_otg->GINTMSK &= ~USB_OTG_GINTMSK_SOFM; + + dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true); + } + + // RxFIFO non-empty interrupt handling. + if(int_status & USB_OTG_GINTSTS_RXFLVL) + { + // RXFLVL bit is read-only + + // Mask out RXFLVL while reading data from FIFO + usb_otg->GINTMSK &= ~USB_OTG_GINTMSK_RXFLVLM; + + // Loop until all available packets were handled + do + { + handle_rxflvl_ints(rhport, out_ep); + } while(usb_otg->GINTSTS & USB_OTG_GINTSTS_RXFLVL); + + // Manage RX FIFO size + if (_out_ep_closed) + { + update_grxfsiz(rhport); + + // Disable flag + _out_ep_closed = false; + } + + usb_otg->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; + } + + // OUT endpoint interrupt handling. + if(int_status & USB_OTG_GINTSTS_OEPINT) + { + // OEPINT is read-only + handle_epout_ints(rhport, dev, out_ep); + } + + // IN endpoint interrupt handling. + if(int_status & USB_OTG_GINTSTS_IEPINT) + { + // IEPINT bit read-only + handle_epin_ints(rhport, dev, in_ep); + } + + // // Check for Incomplete isochronous IN transfer + // if(int_status & USB_OTG_GINTSTS_IISOIXFR) { + // printf(" IISOIXFR!\r\n"); + //// TU_LOG2(" IISOIXFR!\r\n"); + // } +} + +#endif diff --git a/src/portable/synopsys/dwc2/dwc2_gd32.h b/src/portable/synopsys/dwc2/dwc2_gd32.h new file mode 100644 index 000000000..5abbd225f --- /dev/null +++ b/src/portable/synopsys/dwc2/dwc2_gd32.h @@ -0,0 +1,56 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + + +#ifndef DWC2_GD32_H_ +#define DWC2_GD32_H_ + +// for remote wakeup delay +#define __NOP() __asm volatile ("nop") + +// These numbers are the same for the whole GD32VF103 family. +#define OTG_FS_IRQn 86 +#define EP_MAX_FS 4 +#define EP_FIFO_SIZE_FS 1280 + +// The GD32VF103 is a RISC-V MCU, which implements the ECLIC Core-Local +// Interrupt Controller by Nuclei. It is nearly API compatible to the +// NVIC used by ARM MCUs. +#define ECLIC_INTERRUPT_ENABLE_BASE 0xD2001001UL + +#define NVIC_EnableIRQ __eclic_enable_interrupt +#define NVIC_DisableIRQ __eclic_disable_interrupt + +static inline void __eclic_enable_interrupt (uint32_t irq) { + *(volatile uint8_t*)(ECLIC_INTERRUPT_ENABLE_BASE + (irq * 4)) = 1; +} + +static inline void __eclic_disable_interrupt (uint32_t irq){ + *(volatile uint8_t*)(ECLIC_INTERRUPT_ENABLE_BASE + (irq * 4)) = 0; +} + + +#endif /* DWC2_GD32_H_ */ diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h new file mode 100644 index 000000000..efed6d14a --- /dev/null +++ b/src/portable/synopsys/dwc2/dwc2_stm32.h @@ -0,0 +1,72 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef _TUSB_DWC2_STM32_H_ +#define _TUSB_DWC2_STM32_H_ + +// EP_MAX : Max number of bi-directional endpoints including EP0 +// EP_FIFO_SIZE : Size of dedicated USB SRAM +#if CFG_TUSB_MCU == OPT_MCU_STM32F1 + #include "stm32f1xx.h" + #define EP_MAX_FS 4 + #define EP_FIFO_SIZE_FS 1280 + +#elif CFG_TUSB_MCU == OPT_MCU_STM32F2 + #include "stm32f2xx.h" + #define EP_MAX_FS USB_OTG_FS_MAX_IN_ENDPOINTS + #define EP_FIFO_SIZE_FS USB_OTG_FS_TOTAL_FIFO_SIZE + +#elif CFG_TUSB_MCU == OPT_MCU_STM32F4 + #include "stm32f4xx.h" + #define EP_MAX_FS USB_OTG_FS_MAX_IN_ENDPOINTS + #define EP_FIFO_SIZE_FS USB_OTG_FS_TOTAL_FIFO_SIZE + #define EP_MAX_HS USB_OTG_HS_MAX_IN_ENDPOINTS + #define EP_FIFO_SIZE_HS USB_OTG_HS_TOTAL_FIFO_SIZE + +#elif CFG_TUSB_MCU == OPT_MCU_STM32H7 + #include "stm32h7xx.h" + #define EP_MAX_FS 9 + #define EP_FIFO_SIZE_FS 4096 + #define EP_MAX_HS 9 + #define EP_FIFO_SIZE_HS 4096 + +#elif CFG_TUSB_MCU == OPT_MCU_STM32F7 + #include "stm32f7xx.h" + #define EP_MAX_FS 6 + #define EP_FIFO_SIZE_FS 1280 + #define EP_MAX_HS 9 + #define EP_FIFO_SIZE_HS 4096 + +#elif CFG_TUSB_MCU == OPT_MCU_STM32L4 + #include "stm32l4xx.h" + #define EP_MAX_FS 6 + #define EP_FIFO_SIZE_FS 1280 + +#else + #error "Unsupported MCUs" +#endif + +#endif /* DWC2_STM32_H_ */ diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h new file mode 100644 index 000000000..8f48c71eb --- /dev/null +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -0,0 +1,1471 @@ +/** + * @author MCD Application Team + * Ha Thach (tinyusb.org) + * + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + */ + +#ifndef _TUSB_DWC2_TYPES_H_ +#define _TUSB_DWC2_TYPES_H_ + +#include "stdint.h" + +#ifdef __cplusplus + extern "C" { +#endif + +#ifdef __cplusplus + #define __I volatile +#else + #define __I volatile const +#endif +#define __O volatile +#define __IO volatile +#define __IM volatile const +#define __OM volatile +#define __IOM volatile + +#if 0 +// HS PHY +typedef struct +{ + +__IO uint32_t USB_HS_PHYC_PLL; /*!< This register is used to control the PLL of the HS PHY. 000h */ +__IO uint32_t Reserved04; /*!< Reserved 004h */ +__IO uint32_t Reserved08; /*!< Reserved 008h */ +__IO uint32_t USB_HS_PHYC_TUNE; /*!< This register is used to control the tuning interface of the High Speed PHY. 00Ch */ +__IO uint32_t Reserved10; /*!< Reserved 010h */ +__IO uint32_t Reserved14; /*!< Reserved 014h */ +__IO uint32_t USB_HS_PHYC_LDO; /*!< This register is used to control the regulator (LDO). 018h */ +} USB_HS_PHYC_GlobalTypeDef; +#endif + +// Core +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ + uint32_t Reserved30[2]; /*!< Reserved 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */ + __IO uint32_t CID; /*!< User ID Register 03Ch */ + __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/ + __IO uint32_t GHWCFG1; /* User HW config1 044h*/ + __IO uint32_t GHWCFG2; /* User HW config2 048h*/ + __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */ + uint32_t Reserved6; /*!< Reserved 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */ + uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO 104h-13Ch */ +} dwc2_core_t; + +// Host +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */ + uint32_t Reserved40C; /*!< Reserved 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ +} dwc2_host_t; + +// Host Channel +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */ + uint32_t Reserved[2]; /*!< Reserved */ +} dwc2_channel_t; + +// Device +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ + __IO uint32_t DCTL; /*!< dev Control Register 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */ + uint32_t Reserved0C; /*!< Reserved 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ + uint32_t Reserved20; /*!< Reserved 820h */ + uint32_t Reserved9; /*!< Reserved 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ + uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ +} dwc2_device_t; + +// Endpoint IN +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ + uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ +} dwc2_epin_t; + +// Endpoint OUT +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ + uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ +} dwc2_epout_t; + + +/*!< USB registers base address */ +#define DWC2_GLOBAL_BASE 0x00000000UL +#define DWC2_DEVICE_BASE 0x00000800UL +#define DWC2_IN_ENDPOINT_BASE 0x00000900UL +#define DWC2_OUT_ENDPOINT_BASE 0x00000B00UL +#define DWC2_EP_REG_SIZE 0x00000020UL +#define DWC2_HOST_BASE 0x00000400UL +#define DWC2_HOST_PORT_BASE 0x00000440UL +#define DWC2_HOST_CHANNEL_BASE 0x00000500UL +#define DWC2_HOST_CHANNEL_SIZE 0x00000020UL +#define DWC2_PCGCCTL_BASE 0x00000E00UL +#define DWC2_FIFO_BASE 0x00001000UL +#define DWC2_FIFO_SIZE 0x00001000UL + +#if 0 +/******************************************************************************/ +/* */ +/* USB_OTG */ +/* */ +/******************************************************************************/ +/******************** Bit definition for USB_OTG_GOTGCTL register ***********/ +#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U) +#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */ +#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */ +#define USB_OTG_GOTGCTL_SRQ_Pos (1U) +#define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */ +#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */ +#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U) +#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */ +#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */ +#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U) +#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */ +#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */ +#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U) +#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */ +#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */ +#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U) +#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */ +#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */ +#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) +#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ +#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ +#define USB_OTG_GOTGCTL_DBCT_Pos (17U) +#define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ +#define USB_OTG_GOTGCTL_ASVLD_Pos (18U) +#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ +#define USB_OTG_GOTGCTL_BSVLD_Pos (19U) +#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */ + +/******************** Bit definition for USB_OTG_HCFG register ********************/ + +#define USB_OTG_HCFG_FSLSPCS_Pos (0U) +#define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */ +#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */ +#define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */ +#define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */ +#define USB_OTG_HCFG_FSLSS_Pos (2U) +#define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */ + +/******************** Bit definition for USB_OTG_DCFG register ********************/ + +#define USB_OTG_DCFG_DSPD_Pos (0U) +#define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */ +#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */ +#define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */ +#define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */ +#define USB_OTG_DCFG_NZLSOHSK_Pos (2U) +#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */ +#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */ + +#define USB_OTG_DCFG_DAD_Pos (4U) +#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */ +#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ +#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */ +#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */ +#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */ +#define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */ +#define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */ +#define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */ +#define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */ + +#define USB_OTG_DCFG_PFIVL_Pos (11U) +#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */ +#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ +#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ +#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ + +#define USB_OTG_DCFG_PERSCHIVL_Pos (24U) +#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ +#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ +#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */ +#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */ + +/******************** Bit definition for USB_OTG_PCGCR register ********************/ +#define USB_OTG_PCGCR_STPPCLK_Pos (0U) +#define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */ +#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */ +#define USB_OTG_PCGCR_GATEHCLK_Pos (1U) +#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */ +#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */ +#define USB_OTG_PCGCR_PHYSUSP_Pos (4U) +#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */ +#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */ + +/******************** Bit definition for USB_OTG_GOTGINT register ********************/ +#define USB_OTG_GOTGINT_SEDET_Pos (2U) +#define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */ +#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */ +#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U) +#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */ +#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */ +#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U) +#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */ +#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */ +#define USB_OTG_GOTGINT_HNGDET_Pos (17U) +#define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */ +#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U) +#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */ +#define USB_OTG_GOTGINT_DBCDNE_Pos (19U) +#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */ + +/******************** Bit definition for USB_OTG_DCTL register ********************/ +#define USB_OTG_DCTL_RWUSIG_Pos (0U) +#define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */ +#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */ +#define USB_OTG_DCTL_SDIS_Pos (1U) +#define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */ +#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */ +#define USB_OTG_DCTL_GINSTS_Pos (2U) +#define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */ +#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */ +#define USB_OTG_DCTL_GONSTS_Pos (3U) +#define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */ +#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */ + +#define USB_OTG_DCTL_TCTL_Pos (4U) +#define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */ +#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */ +#define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */ +#define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */ +#define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */ +#define USB_OTG_DCTL_SGINAK_Pos (7U) +#define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */ +#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */ +#define USB_OTG_DCTL_CGINAK_Pos (8U) +#define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */ +#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */ +#define USB_OTG_DCTL_SGONAK_Pos (9U) +#define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */ +#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */ +#define USB_OTG_DCTL_CGONAK_Pos (10U) +#define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */ +#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */ +#define USB_OTG_DCTL_POPRGDNE_Pos (11U) +#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ +#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ + +/******************** Bit definition for USB_OTG_HFIR register ********************/ +#define USB_OTG_HFIR_FRIVL_Pos (0U) +#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ + +/******************** Bit definition for USB_OTG_HFNUM register ********************/ +#define USB_OTG_HFNUM_FRNUM_Pos (0U) +#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */ +#define USB_OTG_HFNUM_FTREM_Pos (16U) +#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */ + +/******************** Bit definition for USB_OTG_DSTS register ********************/ +#define USB_OTG_DSTS_SUSPSTS_Pos (0U) +#define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */ +#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */ + +#define USB_OTG_DSTS_ENUMSPD_Pos (1U) +#define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */ +#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */ +#define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */ +#define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */ +#define USB_OTG_DSTS_EERR_Pos (3U) +#define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */ +#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */ +#define USB_OTG_DSTS_FNSOF_Pos (8U) +#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ +#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ + +/******************** Bit definition for USB_OTG_GAHBCFG register ********************/ +#define USB_OTG_GAHBCFG_GINT_Pos (0U) +#define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ +#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ +#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) +#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ +#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ +#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */ +#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */ +#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */ +#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */ +#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */ +#define USB_OTG_GAHBCFG_DMAEN_Pos (5U) +#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */ +#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */ +#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U) +#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */ +#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */ +#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U) +#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */ +#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */ + +/******************** Bit definition for USB_OTG_GUSBCFG register ********************/ + +#define USB_OTG_GUSBCFG_TOCAL_Pos (0U) +#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */ +#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */ +#define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */ +#define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */ +#define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */ +#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U) +#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */ +#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */ +#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U) +#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */ +#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */ +#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U) +#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */ +#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */ +#define USB_OTG_GUSBCFG_TRDT_Pos (10U) +#define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */ +#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */ +#define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */ +#define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ +#define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ +#define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ +#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) +#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ +#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ +#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) +#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ +#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ +#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U) +#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */ +#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */ +#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U) +#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */ +#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */ +#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U) +#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */ +#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */ +#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U) +#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */ +#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */ +#define USB_OTG_GUSBCFG_TSDPS_Pos (22U) +#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */ +#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */ +#define USB_OTG_GUSBCFG_PCCI_Pos (23U) +#define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */ +#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */ +#define USB_OTG_GUSBCFG_PTCI_Pos (24U) +#define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */ +#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */ +#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U) +#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */ +#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */ +#define USB_OTG_GUSBCFG_FHMOD_Pos (29U) +#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */ +#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */ +#define USB_OTG_GUSBCFG_FDMOD_Pos (30U) +#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */ +#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */ +#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U) +#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */ + +/******************** Bit definition for USB_OTG_GRSTCTL register ********************/ +#define USB_OTG_GRSTCTL_CSRST_Pos (0U) +#define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ +#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ +#define USB_OTG_GRSTCTL_HSRST_Pos (1U) +#define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ +#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ +#define USB_OTG_GRSTCTL_FCRST_Pos (2U) +#define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ +#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ +#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U) +#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */ +#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */ +#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U) +#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */ +#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */ + + +#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U) +#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */ +#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */ +#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */ +#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */ +#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */ +#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */ +#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */ +#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U) +#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */ +#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */ +#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U) +#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */ +#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */ + +/******************** Bit definition for USB_OTG_DIEPMSK register ********************/ +#define USB_OTG_DIEPMSK_XFRCM_Pos (0U) +#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */ +#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */ +#define USB_OTG_DIEPMSK_EPDM_Pos (1U) +#define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ +#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPMSK_TOM_Pos (3U) +#define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ +#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ +#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U) +#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */ +#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ +#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U) +#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ +#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U) +#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */ +#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ +#define USB_OTG_DIEPMSK_TXFURM_Pos (8U) +#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */ +#define USB_OTG_DIEPMSK_BIM_Pos (9U) +#define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ +#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ + +/******************** Bit definition for USB_OTG_HPTXSTS register ********************/ +#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) +#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */ +#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U) +#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */ +#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */ +#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */ + +#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U) +#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */ +#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for USB_OTG_HAINT register ********************/ +#define USB_OTG_HAINT_HAINT_Pos (0U) +#define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */ + +/******************** Bit definition for USB_OTG_DOEPMSK register ********************/ +#define USB_OTG_DOEPMSK_XFRCM_Pos (0U) +#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */ +#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */ +#define USB_OTG_DOEPMSK_EPDM_Pos (1U) +#define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ +#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< OUT transaction AHB Error interrupt mask */ +#define USB_OTG_DOEPMSK_STUPM_Pos (3U) +#define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ +#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ +#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) +#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ +#define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U) +#define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */ +#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) +#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ +#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ +#define USB_OTG_DOEPMSK_OPEM_Pos (8U) +#define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPMSK_BOIM_Pos (9U) +#define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ +#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DOEPMSK_BERRM_Pos (12U) +#define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ +#define USB_OTG_DOEPMSK_NAKM_Pos (13U) +#define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk /*!< OUT Packet NAK interrupt mask */ +#define USB_OTG_DOEPMSK_NYETM_Pos (14U) +#define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk /*!< NYET interrupt mask */ +/******************** Bit definition for USB_OTG_GINTSTS register ********************/ +#define USB_OTG_GINTSTS_CMOD_Pos (0U) +#define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */ +#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */ +#define USB_OTG_GINTSTS_MMIS_Pos (1U) +#define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */ +#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */ +#define USB_OTG_GINTSTS_OTGINT_Pos (2U) +#define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */ +#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */ +#define USB_OTG_GINTSTS_SOF_Pos (3U) +#define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */ +#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */ +#define USB_OTG_GINTSTS_RXFLVL_Pos (4U) +#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */ +#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */ +#define USB_OTG_GINTSTS_NPTXFE_Pos (5U) +#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */ +#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */ +#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) +#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ +#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ +#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) +#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ +#define USB_OTG_GINTSTS_ESUSP_Pos (10U) +#define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ +#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ +#define USB_OTG_GINTSTS_USBSUSP_Pos (11U) +#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */ +#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */ +#define USB_OTG_GINTSTS_USBRST_Pos (12U) +#define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */ +#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */ +#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U) +#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */ +#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */ +#define USB_OTG_GINTSTS_ISOODRP_Pos (14U) +#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */ +#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */ +#define USB_OTG_GINTSTS_EOPF_Pos (15U) +#define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */ +#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */ +#define USB_OTG_GINTSTS_IEPINT_Pos (18U) +#define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */ +#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */ +#define USB_OTG_GINTSTS_OEPINT_Pos (19U) +#define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */ +#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */ +#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U) +#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */ +#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */ +#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U) +#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */ +#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */ +#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) +#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ +#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ +#define USB_OTG_GINTSTS_HPRTINT_Pos (24U) +#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ +#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ +#define USB_OTG_GINTSTS_HCINT_Pos (25U) +#define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */ +#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */ +#define USB_OTG_GINTSTS_PTXFE_Pos (26U) +#define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */ +#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */ +#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U) +#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */ +#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */ +#define USB_OTG_GINTSTS_DISCINT_Pos (29U) +#define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */ +#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */ +#define USB_OTG_GINTSTS_SRQINT_Pos (30U) +#define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ +#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ +#define USB_OTG_GINTSTS_WKUINT_Pos (31U) +#define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ + +/******************** Bit definition for USB_OTG_GINTMSK register ********************/ +#define USB_OTG_GINTMSK_MMISM_Pos (1U) +#define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */ +#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */ +#define USB_OTG_GINTMSK_OTGINT_Pos (2U) +#define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */ +#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */ +#define USB_OTG_GINTMSK_SOFM_Pos (3U) +#define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */ +#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */ +#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U) +#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */ +#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */ +#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U) +#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */ +#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */ +#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U) +#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */ +#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */ +#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U) +#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */ +#define USB_OTG_GINTMSK_ESUSPM_Pos (10U) +#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */ +#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */ +#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U) +#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */ +#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */ +#define USB_OTG_GINTMSK_USBRST_Pos (12U) +#define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */ +#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */ +#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U) +#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */ +#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */ +#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U) +#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */ +#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */ +#define USB_OTG_GINTMSK_EOPFM_Pos (15U) +#define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */ +#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */ +#define USB_OTG_GINTMSK_EPMISM_Pos (17U) +#define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */ +#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */ +#define USB_OTG_GINTMSK_IEPINT_Pos (18U) +#define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */ +#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */ +#define USB_OTG_GINTMSK_OEPINT_Pos (19U) +#define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */ +#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */ +#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) +#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ +#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ +#define USB_OTG_GINTMSK_FSUSPM_Pos (22U) +#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ +#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ +#define USB_OTG_GINTMSK_PRTIM_Pos (24U) +#define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ +#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ +#define USB_OTG_GINTMSK_HCIM_Pos (25U) +#define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */ +#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */ +#define USB_OTG_GINTMSK_PTXFEM_Pos (26U) +#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */ +#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */ +#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U) +#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */ +#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */ +#define USB_OTG_GINTMSK_DISCINT_Pos (29U) +#define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */ +#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */ +#define USB_OTG_GINTMSK_SRQIM_Pos (30U) +#define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */ +#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */ +#define USB_OTG_GINTMSK_WUIM_Pos (31U) +#define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */ + +/******************** Bit definition for USB_OTG_DAINT register ********************/ +#define USB_OTG_DAINT_IEPINT_Pos (0U) +#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */ +#define USB_OTG_DAINT_OEPINT_Pos (16U) +#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */ + +/******************** Bit definition for USB_OTG_HAINTMSK register ********************/ +#define USB_OTG_HAINTMSK_HAINTM_Pos (0U) +#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ + +/******************** Bit definition for USB_OTG_GRXSTSP register ********************/ +#define USB_OTG_GRXSTSP_EPNUM_Pos (0U) +#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_BCNT_Pos (4U) +#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_DPID_Pos (15U) +#define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) +#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ + +/******************** Bit definition for USB_OTG_DAINTMSK register ********************/ +#define USB_OTG_DAINTMSK_IEPM_Pos (0U) +#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_DAINTMSK_OEPM_Pos (16U) +#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */ + +/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/ +#define USB_OTG_GRXFSIZ_RXFD_Pos (0U) +#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */ + +/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/ +#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U) +#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */ + +/******************** Bit definition for OTG register ********************/ +#define USB_OTG_NPTXFSA_Pos (0U) +#define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */ +#define USB_OTG_NPTXFD_Pos (16U) +#define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */ +#define USB_OTG_TX0FSA_Pos (0U) +#define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */ +#define USB_OTG_TX0FD_Pos (16U) +#define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */ + +/******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/ +#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U) +#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */ +#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */ + +/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/ +#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U) +#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */ + +#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U) +#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */ + +#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U) +#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for USB_OTG_DTHRCTL register ********************/ +#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U) +#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */ +#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */ +#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U) +#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */ +#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */ + +#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U) +#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */ +#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */ +#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */ +#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U) +#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */ +#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */ + +#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U) +#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */ +#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */ +#define USB_OTG_DTHRCTL_ARPEN_Pos (27U) +#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */ +#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */ + +/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/ +#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U) +#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */ + +/******************** Bit definition for USB_OTG_DEACHINT register ********************/ +#define USB_OTG_DEACHINT_IEP1INT_Pos (1U) +#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */ +#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */ +#define USB_OTG_DEACHINT_OEP1INT_Pos (17U) +#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */ +#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */ + +/******************** Bit definition for USB_OTG_GCCFG register ********************/ +#define USB_OTG_GCCFG_PWRDWN_Pos (16U) +#define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */ +#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */ +#define USB_OTG_GCCFG_VBUSASEN_Pos (18U) +#define USB_OTG_GCCFG_VBUSASEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */ +#define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk /*!< Enable the VBUS sensing device */ +#define USB_OTG_GCCFG_VBUSBSEN_Pos (19U) +#define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */ +#define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk /*!< Enable the VBUS sensing device */ +#define USB_OTG_GCCFG_SOFOUTEN_Pos (20U) +#define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */ +#define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk /*!< SOF output enable */ + +/******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/ +#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U) +#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */ +#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */ +#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U) +#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */ +#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */ + +/******************** Bit definition for USB_OTG_CID register ********************/ +#define USB_OTG_CID_PRODUCT_ID_Pos (0U) +#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */ +#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */ + +/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ +#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) +#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */ +#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */ +#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U) +#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */ +#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U) +#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */ +#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ +#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U) +#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */ +#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ +#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U) +#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ +#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U) +#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */ +#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ +#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U) +#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */ +#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U) +#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */ +#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U) +#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */ + +/******************** Bit definition for USB_OTG_HPRT register ********************/ +#define USB_OTG_HPRT_PCSTS_Pos (0U) +#define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */ +#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */ +#define USB_OTG_HPRT_PCDET_Pos (1U) +#define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */ +#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */ +#define USB_OTG_HPRT_PENA_Pos (2U) +#define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */ +#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */ +#define USB_OTG_HPRT_PENCHNG_Pos (3U) +#define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */ +#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */ +#define USB_OTG_HPRT_POCA_Pos (4U) +#define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */ +#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */ +#define USB_OTG_HPRT_POCCHNG_Pos (5U) +#define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */ +#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */ +#define USB_OTG_HPRT_PRES_Pos (6U) +#define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */ +#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */ +#define USB_OTG_HPRT_PSUSP_Pos (7U) +#define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */ +#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */ +#define USB_OTG_HPRT_PRST_Pos (8U) +#define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ +#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ + +#define USB_OTG_HPRT_PLSTS_Pos (10U) +#define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ +#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ +#define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */ +#define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */ +#define USB_OTG_HPRT_PPWR_Pos (12U) +#define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ +#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ + +#define USB_OTG_HPRT_PTCTL_Pos (13U) +#define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ +#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ +#define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */ +#define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ +#define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ +#define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ + +#define USB_OTG_HPRT_PSPD_Pos (17U) +#define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ +#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ +#define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */ +#define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/ +#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U) +#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */ +#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U) +#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */ +#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U) +#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */ +#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */ +#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U) +#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ +#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U) +#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ +#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U) +#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */ +#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ +#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U) +#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U) +#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */ +#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U) +#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U) +#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U) +#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */ + +/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/ +#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) +#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ +#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) +#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ + +/******************** Bit definition for USB_OTG_DIEPCTL register ********************/ +#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) +#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */ +#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */ +#define USB_OTG_DIEPCTL_USBAEP_Pos (15U) +#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */ +#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */ +#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U) +#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */ +#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */ +#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U) +#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ +#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */ + +#define USB_OTG_DIEPCTL_EPTYP_Pos (18U) +#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ +#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */ +#define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */ +#define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */ +#define USB_OTG_DIEPCTL_STALL_Pos (21U) +#define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */ +#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */ + +#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U) +#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */ +#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */ +#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */ +#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */ +#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */ +#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */ +#define USB_OTG_DIEPCTL_CNAK_Pos (26U) +#define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */ +#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */ +#define USB_OTG_DIEPCTL_SNAK_Pos (27U) +#define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */ +#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ +#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) +#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ +#define USB_OTG_DIEPCTL_EPDIS_Pos (30U) +#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ +#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ +#define USB_OTG_DIEPCTL_EPENA_Pos (31U) +#define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */ +#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */ + +/******************** Bit definition for USB_OTG_HCCHAR register ********************/ +#define USB_OTG_HCCHAR_MPSIZ_Pos (0U) +#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ +#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ + +#define USB_OTG_HCCHAR_EPNUM_Pos (11U) +#define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ +#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ +#define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */ +#define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */ +#define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */ +#define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */ +#define USB_OTG_HCCHAR_EPDIR_Pos (15U) +#define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */ +#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */ +#define USB_OTG_HCCHAR_LSDEV_Pos (17U) +#define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ +#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ + +#define USB_OTG_HCCHAR_EPTYP_Pos (18U) +#define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ +#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ +#define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ +#define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ + +#define USB_OTG_HCCHAR_MC_Pos (20U) +#define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ +#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ +#define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ +#define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ + +#define USB_OTG_HCCHAR_DAD_Pos (22U) +#define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ +#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ +#define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */ +#define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */ +#define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */ +#define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */ +#define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */ +#define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */ +#define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */ +#define USB_OTG_HCCHAR_ODDFRM_Pos (29U) +#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */ +#define USB_OTG_HCCHAR_CHDIS_Pos (30U) +#define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */ +#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */ +#define USB_OTG_HCCHAR_CHENA_Pos (31U) +#define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */ + +/******************** Bit definition for USB_OTG_HCSPLT register ********************/ + +#define USB_OTG_HCSPLT_PRTADDR_Pos (0U) +#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */ +#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */ +#define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */ +#define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */ +#define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */ +#define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */ +#define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */ +#define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */ + +#define USB_OTG_HCSPLT_HUBADDR_Pos (7U) +#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */ +#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */ +#define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */ +#define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */ +#define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */ +#define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */ +#define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */ +#define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */ +#define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */ + +#define USB_OTG_HCSPLT_XACTPOS_Pos (14U) +#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */ +#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */ +#define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */ +#define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */ +#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U) +#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */ +#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */ +#define USB_OTG_HCSPLT_SPLITEN_Pos (31U) +#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */ + +/******************** Bit definition for USB_OTG_HCINT register ********************/ +#define USB_OTG_HCINT_XFRC_Pos (0U) +#define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */ +#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */ +#define USB_OTG_HCINT_CHH_Pos (1U) +#define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */ +#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */ +#define USB_OTG_HCINT_AHBERR_Pos (2U) +#define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINT_STALL_Pos (3U) +#define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */ +#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */ +#define USB_OTG_HCINT_NAK_Pos (4U) +#define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */ +#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */ +#define USB_OTG_HCINT_ACK_Pos (5U) +#define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */ +#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */ +#define USB_OTG_HCINT_NYET_Pos (6U) +#define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */ +#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */ +#define USB_OTG_HCINT_TXERR_Pos (7U) +#define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */ +#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */ +#define USB_OTG_HCINT_BBERR_Pos (8U) +#define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */ +#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */ +#define USB_OTG_HCINT_FRMOR_Pos (9U) +#define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */ +#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */ +#define USB_OTG_HCINT_DTERR_Pos (10U) +#define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */ +#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */ + +/******************** Bit definition for USB_OTG_DIEPINT register ********************/ +#define USB_OTG_DIEPINT_XFRC_Pos (0U) +#define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */ +#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */ +#define USB_OTG_DIEPINT_EPDISD_Pos (1U) +#define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */ +#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ +#define USB_OTG_DIEPINT_AHBERR_Pos (2U) +#define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an IN transaction */ +#define USB_OTG_DIEPINT_TOC_Pos (3U) +#define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */ +#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */ +#define USB_OTG_DIEPINT_ITTXFE_Pos (4U) +#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ +#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ +#define USB_OTG_DIEPINT_INEPNM_Pos (5U) +#define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ +#define USB_OTG_DIEPINT_INEPNE_Pos (6U) +#define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ +#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ +#define USB_OTG_DIEPINT_TXFE_Pos (7U) +#define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */ +#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */ +#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U) +#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */ +#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */ +#define USB_OTG_DIEPINT_BNA_Pos (9U) +#define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */ +#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */ +#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U) +#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */ +#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */ +#define USB_OTG_DIEPINT_BERR_Pos (12U) +#define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */ +#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */ +#define USB_OTG_DIEPINT_NAK_Pos (13U) +#define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */ + +/******************** Bit definition for USB_OTG_HCINTMSK register ********************/ +#define USB_OTG_HCINTMSK_XFRCM_Pos (0U) +#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */ +#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */ +#define USB_OTG_HCINTMSK_CHHM_Pos (1U) +#define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ +#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ +#define USB_OTG_HCINTMSK_AHBERR_Pos (2U) +#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINTMSK_STALLM_Pos (3U) +#define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ +#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ +#define USB_OTG_HCINTMSK_NAKM_Pos (4U) +#define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */ +#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */ +#define USB_OTG_HCINTMSK_ACKM_Pos (5U) +#define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */ +#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */ +#define USB_OTG_HCINTMSK_NYET_Pos (6U) +#define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */ +#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */ +#define USB_OTG_HCINTMSK_TXERRM_Pos (7U) +#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */ +#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */ +#define USB_OTG_HCINTMSK_BBERRM_Pos (8U) +#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */ +#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */ +#define USB_OTG_HCINTMSK_FRMORM_Pos (9U) +#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */ +#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */ +#define USB_OTG_HCINTMSK_DTERRM_Pos (10U) +#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */ +#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */ + +/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/ + +#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U) +#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ +#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */ +#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) +#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ +#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ +#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) +#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ +#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ +/******************** Bit definition for USB_OTG_HCTSIZ register ********************/ +#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) +#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ +#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */ +#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) +#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ +#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ +#define USB_OTG_HCTSIZ_DOPING_Pos (31U) +#define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ +#define USB_OTG_HCTSIZ_DPID_Pos (29U) +#define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ +#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ +#define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ +#define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for USB_OTG_DIEPDMA register ********************/ +#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) +#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */ +#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */ + +/******************** Bit definition for USB_OTG_HCDMA register ********************/ +#define USB_OTG_HCDMA_DMAADDR_Pos (0U) +#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */ +#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */ + +/******************** Bit definition for USB_OTG_DTXFSTS register ********************/ +#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U) +#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */ + +/******************** Bit definition for USB_OTG_DIEPTXF register ********************/ +#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U) +#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */ +#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U) +#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */ + +/******************** Bit definition for USB_OTG_DOEPCTL register ********************/ + +#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U) +#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */ +#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*! Date: Mon, 25 Oct 2021 00:06:57 +0700 Subject: switch gd32 and stm32f4 to use new dwc2 driver --- hw/bsp/gd32vf103/family.mk | 2 +- src/portable/synopsys/dwc2/dcd_dwc2.c | 288 ++-- src/portable/synopsys/dwc2/dwc2_gd32.h | 7 +- src/portable/synopsys/dwc2/dwc2_stm32.h | 15 + src/portable/synopsys/dwc2/dwc2_type.h | 2728 ++++++++++++++++--------------- 5 files changed, 1591 insertions(+), 1449 deletions(-) diff --git a/hw/bsp/gd32vf103/family.mk b/hw/bsp/gd32vf103/family.mk index 9148e7f8b..4de23ac17 100644 --- a/hw/bsp/gd32vf103/family.mk +++ b/hw/bsp/gd32vf103/family.mk @@ -35,7 +35,7 @@ CFLAGS += \ CFLAGS += -Wno-error=unused-parameter SRC_C += \ - src/portable/st/synopsys/dcd_synopsys.c \ + src/portable/synopsys/dwc2/dcd_dwc2.c \ $(GD32VF103_SDK_DRIVER)/gd32vf103_rcu.c \ $(GD32VF103_SDK_DRIVER)/gd32vf103_gpio.c \ $(GD32VF103_SDK_DRIVER)/Usb/gd32vf103_usb_hw.c \ diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 597f4c813..5811afa5a 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -52,26 +52,11 @@ // MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ -// On STM32 we associate Port0 to OTG_FS, and Port1 to OTG_HS -#if TUD_OPT_RHPORT == 0 -#define EP_MAX EP_MAX_FS -#define EP_FIFO_SIZE EP_FIFO_SIZE_FS -#define RHPORT_REGS_BASE USB_OTG_FS_PERIPH_BASE -#define RHPORT_IRQn OTG_FS_IRQn - -#else -#define EP_MAX EP_MAX_HS -#define EP_FIFO_SIZE EP_FIFO_SIZE_HS -#define RHPORT_REGS_BASE USB_OTG_HS_PERIPH_BASE -#define RHPORT_IRQn OTG_HS_IRQn - -#endif - -#define GLOBAL_BASE(_port) ((dwc2_core_t*) RHPORT_REGS_BASE) -#define DEVICE_BASE(_port) ((dwc2_device_t *) (RHPORT_REGS_BASE + USB_OTG_DEVICE_BASE)) -#define OUT_EP_BASE(_port) ((dwc2_epout_t *) (RHPORT_REGS_BASE + USB_OTG_OUT_ENDPOINT_BASE)) -#define IN_EP_BASE(_port) ((dwc2_epin_t *) (RHPORT_REGS_BASE + USB_OTG_IN_ENDPOINT_BASE)) -#define FIFO_BASE(_port, _x) ((volatile uint32_t *) (RHPORT_REGS_BASE + USB_OTG_FIFO_BASE + (_x) * USB_OTG_FIFO_SIZE)) +#define GLOBAL_BASE(_port) ((dwc2_core_t*) DWC2_REG_BASE) +#define DEVICE_BASE(_port) ((dwc2_device_t*) (DWC2_REG_BASE + DWC2_DEVICE_BASE)) +#define IN_EP_BASE(_port) ((dwc2_epin_t*) (DWC2_REG_BASE + DWC2_IN_ENDPOINT_BASE)) +#define OUT_EP_BASE(_port) ((dwc2_epout_t*) (DWC2_REG_BASE + DWC2_OUT_ENDPOINT_BASE)) +#define FIFO_BASE(_port, _x) ((volatile uint32_t*) (DWC2_REG_BASE + DWC2_FIFO_BASE + (_x) * DWC2_FIFO_SIZE)) enum { @@ -139,17 +124,17 @@ static void bus_reset(uint8_t rhport) _out_ep_closed = false; // clear device address - dev->DCFG &= ~USB_OTG_DCFG_DAD_Msk; + dev->DCFG &= ~DCFG_DAD_Msk; // 1. NAK for all OUT endpoints for(uint8_t n = 0; n < EP_MAX; n++) { - out_ep[n].DOEPCTL |= USB_OTG_DOEPCTL_SNAK; + out_ep[n].DOEPCTL |= DOEPCTL_SNAK; } // 2. Un-mask interrupt bits - dev->DAINTMSK = (1 << USB_OTG_DAINTMSK_OEPM_Pos) | (1 << USB_OTG_DAINTMSK_IEPM_Pos); - dev->DOEPMSK = USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM; - dev->DIEPMSK = USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM; + dev->DAINTMSK = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos); + dev->DOEPMSK = DOEPMSK_STUPM | DOEPMSK_XFRCM; + dev->DIEPMSK = DIEPMSK_TOM | DIEPMSK_XFRCM; // "USB Data FIFOs" section in reference manual // Peripheral FIFO architecture @@ -206,27 +191,27 @@ static void bus_reset(uint8_t rhport) _allocated_fifo_words_tx = 16; // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word ) - usb_otg->DIEPTXF0_HNPTXFSIZ = (16 << USB_OTG_TX0FD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx); + usb_otg->DIEPTXF0_HNPTXFSIZ = (16 << TX0FD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx); // Fixed control EP0 size to 64 bytes - in_ep[0].DIEPCTL &= ~(0x03 << USB_OTG_DIEPCTL_MPSIZ_Pos); + in_ep[0].DIEPCTL &= ~(0x03 << DIEPCTL_MPSIZ_Pos); xfer_status[0][TUSB_DIR_OUT].max_size = xfer_status[0][TUSB_DIR_IN].max_size = 64; - out_ep[0].DOEPTSIZ |= (3 << USB_OTG_DOEPTSIZ_STUPCNT_Pos); + out_ep[0].DOEPTSIZ |= (3 << DOEPTSIZ_STUPCNT_Pos); - usb_otg->GINTMSK |= USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IEPINT; + usb_otg->GINTMSK |= GINTMSK_OEPINT | GINTMSK_IEPINT; } // Set turn-around timeout according to link speed extern uint32_t SystemCoreClock; static void set_turnaround(dwc2_core_t * usb_otg, tusb_speed_t speed) { - usb_otg->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT; + usb_otg->GUSBCFG &= ~GUSBCFG_TRDT; if ( speed == TUSB_SPEED_HIGH ) { // Use fixed 0x09 for Highspeed - usb_otg->GUSBCFG |= (0x09 << USB_OTG_GUSBCFG_TRDT_Pos); + usb_otg->GUSBCFG |= (0x09 << GUSBCFG_TRDT_Pos); } else { @@ -255,7 +240,7 @@ static void set_turnaround(dwc2_core_t * usb_otg, tusb_speed_t speed) turnaround = 0xFU; // Fullspeed depends on MCU clocks, but we will use 0x06 for 32+ Mhz - usb_otg->GUSBCFG |= (turnaround << USB_OTG_GUSBCFG_TRDT_Pos); + usb_otg->GUSBCFG |= (turnaround << GUSBCFG_TRDT_Pos); } } @@ -263,7 +248,7 @@ static tusb_speed_t get_speed(uint8_t rhport) { (void) rhport; dwc2_device_t * dev = DEVICE_BASE(rhport); - uint32_t const enum_spd = (dev->DSTS & USB_OTG_DSTS_ENUMSPD_Msk) >> USB_OTG_DSTS_ENUMSPD_Pos; + uint32_t const enum_spd = (dev->DSTS & DSTS_ENUMSPD_Msk) >> DSTS_ENUMSPD_Pos; return (enum_spd == DCD_HIGH_SPEED) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL; } @@ -283,8 +268,8 @@ static void set_speed(uint8_t rhport, tusb_speed_t speed) dwc2_device_t * dev = DEVICE_BASE(rhport); // Clear and set speed bits - dev->DCFG &= ~(3 << USB_OTG_DCFG_DSPD_Pos); - dev->DCFG |= (bitvalue << USB_OTG_DCFG_DSPD_Pos); + dev->DCFG &= ~(3 << DCFG_DSPD_Pos); + dev->DCFG |= (bitvalue << DCFG_DSPD_Pos); } #if defined(USB_HS_PHYC) @@ -347,16 +332,16 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c // IN and OUT endpoint xfers are interrupt-driven, we just schedule them here. if(dir == TUSB_DIR_IN) { // A full IN transfer (multiple packets, possibly) triggers XFRC. - in_ep[epnum].DIEPTSIZ = (num_packets << USB_OTG_DIEPTSIZ_PKTCNT_Pos) | - ((total_bytes << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) & USB_OTG_DIEPTSIZ_XFRSIZ_Msk); + in_ep[epnum].DIEPTSIZ = (num_packets << DIEPTSIZ_PKTCNT_Pos) | + ((total_bytes << DIEPTSIZ_XFRSIZ_Pos) & DIEPTSIZ_XFRSIZ_Msk); - in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_EPENA | USB_OTG_DIEPCTL_CNAK; + in_ep[epnum].DIEPCTL |= DIEPCTL_EPENA | DIEPCTL_CNAK; // For ISO endpoint set correct odd/even bit for next frame. - if ((in_ep[epnum].DIEPCTL & USB_OTG_DIEPCTL_EPTYP) == USB_OTG_DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) + if ((in_ep[epnum].DIEPCTL & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) { // Take odd/even bit from frame counter. - uint32_t const odd_frame_now = (dev->DSTS & (1u << USB_OTG_DSTS_FNSOF_Pos)); - in_ep[epnum].DIEPCTL |= (odd_frame_now ? USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk : USB_OTG_DIEPCTL_SODDFRM_Msk); + uint32_t const odd_frame_now = (dev->DSTS & (1u << DSTS_FNSOF_Pos)); + in_ep[epnum].DIEPCTL |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk); } // Enable fifo empty interrupt only if there are something to put in the fifo. if(total_bytes != 0) { @@ -364,16 +349,16 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c } } else { // A full OUT transfer (multiple packets, possibly) triggers XFRC. - out_ep[epnum].DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT_Msk | USB_OTG_DOEPTSIZ_XFRSIZ); - out_ep[epnum].DOEPTSIZ |= (num_packets << USB_OTG_DOEPTSIZ_PKTCNT_Pos) | - ((total_bytes << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) & USB_OTG_DOEPTSIZ_XFRSIZ_Msk); + out_ep[epnum].DOEPTSIZ &= ~(DOEPTSIZ_PKTCNT_Msk | DOEPTSIZ_XFRSIZ); + out_ep[epnum].DOEPTSIZ |= (num_packets << DOEPTSIZ_PKTCNT_Pos) | + ((total_bytes << DOEPTSIZ_XFRSIZ_Pos) & DOEPTSIZ_XFRSIZ_Msk); - out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_CNAK; - if ((out_ep[epnum].DOEPCTL & USB_OTG_DOEPCTL_EPTYP) == USB_OTG_DOEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) + out_ep[epnum].DOEPCTL |= DOEPCTL_EPENA | DOEPCTL_CNAK; + if ((out_ep[epnum].DOEPCTL & DOEPCTL_EPTYP) == DOEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) { // Take odd/even bit from frame counter. - uint32_t const odd_frame_now = (dev->DSTS & (1u << USB_OTG_DSTS_FNSOF_Pos)); - out_ep[epnum].DOEPCTL |= (odd_frame_now ? USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk : USB_OTG_DOEPCTL_SODDFRM_Msk); + uint32_t const odd_frame_now = (dev->DSTS & (1u << DSTS_FNSOF_Pos)); + out_ep[epnum].DOEPCTL |= (odd_frame_now ? DOEPCTL_SD0PID_SEVNFRM_Msk : DOEPCTL_SODDFRM_Msk); } } } @@ -385,7 +370,6 @@ void dcd_init (uint8_t rhport) { // Programming model begins in the last section of the chapter on the USB // peripheral in each Reference Manual. - dwc2_core_t * usb_otg = GLOBAL_BASE(rhport); // No HNP/SRP (no OTG support), program timeout later. @@ -394,23 +378,23 @@ void dcd_init (uint8_t rhport) // On selected MCUs HS port1 can be used with external PHY via ULPI interface #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED // deactivate internal PHY - usb_otg->GCCFG &= ~USB_OTG_GCCFG_PWRDWN; + usb_otg->GCCFG &= ~GCCFG_PWRDWN; // Init The UTMI Interface - usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL); + usb_otg->GUSBCFG &= ~(GUSBCFG_TSDPS | GUSBCFG_ULPIFSLS | GUSBCFG_PHYSEL); // Select default internal VBUS Indicator and Drive for ULPI - usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); + usb_otg->GUSBCFG &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI); #else - usb_otg->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; + usb_otg->GUSBCFG |= GUSBCFG_PHYSEL; #endif #if defined(USB_HS_PHYC) // Highspeed with embedded UTMI PHYC // Select UTMI Interface - usb_otg->GUSBCFG &= ~USB_OTG_GUSBCFG_ULPI_UTMI_SEL; - usb_otg->GCCFG |= USB_OTG_GCCFG_PHYHSEN; + usb_otg->GUSBCFG &= ~GUSBCFG_ULPI_UTMI_SEL; + usb_otg->GCCFG |= GCCFG_PHYHSEN; // Enables control of a High Speed USB PHY USB_HS_PHYCInit(); @@ -418,17 +402,17 @@ void dcd_init (uint8_t rhport) } else { // Enable internal PHY - usb_otg->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; + usb_otg->GUSBCFG |= GUSBCFG_PHYSEL; } - // Reset core after selecting PHY + // Reset core after selecting PHYst // Wait AHB IDLE, reset then wait until it is cleared - while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U) {} - usb_otg->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; - while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST) {} + while ((usb_otg->GRSTCTL & GRSTCTL_AHBIDL) == 0U) {} + usb_otg->GRSTCTL |= GRSTCTL_CSRST; + while ((usb_otg->GRSTCTL & GRSTCTL_CSRST) == GRSTCTL_CSRST) {} // Restart PHY clock - *((volatile uint32_t *)(RHPORT_REGS_BASE + USB_OTG_PCGCCTL_BASE)) = 0; + *((volatile uint32_t *)(DWC2_REG_BASE + DWC2_PCGCCTL_BASE)) = 0; // Clear all interrupts usb_otg->GINTSTS |= usb_otg->GINTSTS; @@ -436,25 +420,25 @@ void dcd_init (uint8_t rhport) // Required as part of core initialization. // TODO: How should mode mismatch be handled? It will cause // the core to stop working/require reset. - usb_otg->GINTMSK |= USB_OTG_GINTMSK_OTGINT | USB_OTG_GINTMSK_MMISM; + usb_otg->GINTMSK |= GINTMSK_OTGINT | GINTMSK_MMISM; dwc2_device_t * dev = DEVICE_BASE(rhport); // If USB host misbehaves during status portion of control xfer // (non zero-length packet), send STALL back and discard. - dev->DCFG |= USB_OTG_DCFG_NZLSOHSK; + dev->DCFG |= DCFG_NZLSOHSK; set_speed(rhport, TUD_OPT_HIGH_SPEED ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL); // Enable internal USB transceiver, unless using HS core (port 1) with external PHY. - if (!(rhport == 1 && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED))) usb_otg->GCCFG |= USB_OTG_GCCFG_PWRDWN; + if (!(rhport == 1 && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED))) usb_otg->GCCFG |= GCCFG_PWRDWN; - usb_otg->GINTMSK |= USB_OTG_GINTMSK_USBRST | USB_OTG_GINTMSK_ENUMDNEM | - USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_WUIM | - USB_OTG_GINTMSK_RXFLVLM | (USE_SOF ? USB_OTG_GINTMSK_SOFM : 0); + usb_otg->GINTMSK |= GINTMSK_USBRST | GINTMSK_ENUMDNEM | + GINTMSK_USBSUSPM | GINTMSK_WUIM | + GINTMSK_RXFLVLM | (USE_SOF ? GINTMSK_SOFM : 0); // Enable global interrupt - usb_otg->GAHBCFG |= USB_OTG_GAHBCFG_GINT; + usb_otg->GAHBCFG |= GAHBCFG_GINT; dcd_connect(rhport); } @@ -474,7 +458,7 @@ void dcd_int_disable (uint8_t rhport) void dcd_set_address (uint8_t rhport, uint8_t dev_addr) { dwc2_device_t * dev = DEVICE_BASE(rhport); - dev->DCFG = (dev->DCFG & ~USB_OTG_DCFG_DAD_Msk) | (dev_addr << USB_OTG_DCFG_DAD_Pos); + dev->DCFG = (dev->DCFG & ~DCFG_DAD_Msk) | (dev_addr << DCFG_DAD_Pos); // Response with status after changing device address dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0); @@ -498,30 +482,30 @@ void dcd_remote_wakeup(uint8_t rhport) dwc2_device_t * dev = DEVICE_BASE(rhport); // set remote wakeup - dev->DCTL |= USB_OTG_DCTL_RWUSIG; + dev->DCTL |= DCTL_RWUSIG; // enable SOF to detect bus resume - usb_otg->GINTSTS = USB_OTG_GINTSTS_SOF; - usb_otg->GINTMSK |= USB_OTG_GINTMSK_SOFM; + usb_otg->GINTSTS = GINTSTS_SOF; + usb_otg->GINTMSK |= GINTMSK_SOFM; // Per specs: remote wakeup signal bit must be clear within 1-15ms remote_wakeup_delay(); - dev->DCTL &= ~USB_OTG_DCTL_RWUSIG; + dev->DCTL &= ~DCTL_RWUSIG; } void dcd_connect(uint8_t rhport) { (void) rhport; dwc2_device_t * dev = DEVICE_BASE(rhport); - dev->DCTL &= ~USB_OTG_DCTL_SDIS; + dev->DCTL &= ~DCTL_SDIS; } void dcd_disconnect(uint8_t rhport) { (void) rhport; dwc2_device_t * dev = DEVICE_BASE(rhport); - dev->DCTL |= USB_OTG_DCTL_SDIS; + dev->DCTL |= DCTL_SDIS; } @@ -563,12 +547,12 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) usb_otg->GRXFSIZ = sz; } - out_ep[epnum].DOEPCTL |= (1 << USB_OTG_DOEPCTL_USBAEP_Pos) | - (desc_edpt->bmAttributes.xfer << USB_OTG_DOEPCTL_EPTYP_Pos) | - (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_OTG_DOEPCTL_SD0PID_SEVNFRM : 0) | - (xfer->max_size << USB_OTG_DOEPCTL_MPSIZ_Pos); + out_ep[epnum].DOEPCTL |= (1 << DOEPCTL_USBAEP_Pos) | + (desc_edpt->bmAttributes.xfer << DOEPCTL_EPTYP_Pos) | + (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DOEPCTL_SD0PID_SEVNFRM : 0) | + (xfer->max_size << DOEPCTL_MPSIZ_Pos); - dev->DAINTMSK |= (1 << (USB_OTG_DAINTMSK_OEPM_Pos + epnum)); + dev->DAINTMSK |= (1 << (DAINTMSK_OEPM_Pos + epnum)); } else { @@ -602,15 +586,15 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) // DIEPTXF starts at FIFO #1. // Both TXFD and TXSA are in unit of 32-bit words. - usb_otg->DIEPTXF[epnum - 1] = (fifo_size << USB_OTG_DIEPTXF_INEPTXFD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx); + usb_otg->DIEPTXF[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx); - in_ep[epnum].DIEPCTL |= (1 << USB_OTG_DIEPCTL_USBAEP_Pos) | - (epnum << USB_OTG_DIEPCTL_TXFNUM_Pos) | - (desc_edpt->bmAttributes.xfer << USB_OTG_DIEPCTL_EPTYP_Pos) | - (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_OTG_DIEPCTL_SD0PID_SEVNFRM : 0) | - (xfer->max_size << USB_OTG_DIEPCTL_MPSIZ_Pos); + in_ep[epnum].DIEPCTL |= (1 << DIEPCTL_USBAEP_Pos) | + (epnum << DIEPCTL_TXFNUM_Pos) | + (desc_edpt->bmAttributes.xfer << DIEPCTL_EPTYP_Pos) | + (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DIEPCTL_SD0PID_SEVNFRM : 0) | + (xfer->max_size << DIEPCTL_MPSIZ_Pos); - dev->DAINTMSK |= (1 << (USB_OTG_DAINTMSK_IEPM_Pos + epnum)); + dev->DAINTMSK |= (1 << (DAINTMSK_IEPM_Pos + epnum)); } return true; @@ -627,7 +611,7 @@ void dcd_edpt_close_all (uint8_t rhport) dwc2_epin_t * in_ep = IN_EP_BASE(rhport); // Disable non-control interrupt - dev->DAINTMSK = (1 << USB_OTG_DAINTMSK_OEPM_Pos) | (1 << USB_OTG_DAINTMSK_IEPM_Pos); + dev->DAINTMSK = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos); for(uint8_t n = 1; n < EP_MAX; n++) { @@ -719,42 +703,42 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall) if(dir == TUSB_DIR_IN) { // Only disable currently enabled non-control endpoint - if ( (epnum == 0) || !(in_ep[epnum].DIEPCTL & USB_OTG_DIEPCTL_EPENA) ){ - in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SNAK | (stall ? USB_OTG_DIEPCTL_STALL : 0); + if ( (epnum == 0) || !(in_ep[epnum].DIEPCTL & DIEPCTL_EPENA) ){ + in_ep[epnum].DIEPCTL |= DIEPCTL_SNAK | (stall ? DIEPCTL_STALL : 0); } else { // Stop transmitting packets and NAK IN xfers. - in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SNAK; - while((in_ep[epnum].DIEPINT & USB_OTG_DIEPINT_INEPNE) == 0); + in_ep[epnum].DIEPCTL |= DIEPCTL_SNAK; + while((in_ep[epnum].DIEPINT & DIEPINT_INEPNE) == 0); // Disable the endpoint. - in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_EPDIS | (stall ? USB_OTG_DIEPCTL_STALL : 0); - while((in_ep[epnum].DIEPINT & USB_OTG_DIEPINT_EPDISD_Msk) == 0); - in_ep[epnum].DIEPINT = USB_OTG_DIEPINT_EPDISD; + in_ep[epnum].DIEPCTL |= DIEPCTL_EPDIS | (stall ? DIEPCTL_STALL : 0); + while((in_ep[epnum].DIEPINT & DIEPINT_EPDISD_Msk) == 0); + in_ep[epnum].DIEPINT = DIEPINT_EPDISD; } // Flush the FIFO, and wait until we have confirmed it cleared. - usb_otg->GRSTCTL |= (epnum << USB_OTG_GRSTCTL_TXFNUM_Pos); - usb_otg->GRSTCTL |= USB_OTG_GRSTCTL_TXFFLSH; - while((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH_Msk) != 0); + usb_otg->GRSTCTL |= (epnum << GRSTCTL_TXFNUM_Pos); + usb_otg->GRSTCTL |= GRSTCTL_TXFFLSH; + while((usb_otg->GRSTCTL & GRSTCTL_TXFFLSH_Msk) != 0); } else { // Only disable currently enabled non-control endpoint - if ( (epnum == 0) || !(out_ep[epnum].DOEPCTL & USB_OTG_DOEPCTL_EPENA) ){ - out_ep[epnum].DOEPCTL |= stall ? USB_OTG_DOEPCTL_STALL : 0; + if ( (epnum == 0) || !(out_ep[epnum].DOEPCTL & DOEPCTL_EPENA) ){ + out_ep[epnum].DOEPCTL |= stall ? DOEPCTL_STALL : 0; } else { // Asserting GONAK is required to STALL an OUT endpoint. // Simpler to use polling here, we don't use the "B"OUTNAKEFF interrupt // anyway, and it can't be cleared by user code. If this while loop never // finishes, we have bigger problems than just the stack. - dev->DCTL |= USB_OTG_DCTL_SGONAK; - while((usb_otg->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF_Msk) == 0); + dev->DCTL |= DCTL_SGONAK; + while((usb_otg->GINTSTS & GINTSTS_BOUTNAKEFF_Msk) == 0); // Ditto here- disable the endpoint. - out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_EPDIS | (stall ? USB_OTG_DOEPCTL_STALL : 0); - while((out_ep[epnum].DOEPINT & USB_OTG_DOEPINT_EPDISD_Msk) == 0); - out_ep[epnum].DOEPINT = USB_OTG_DOEPINT_EPDISD; + out_ep[epnum].DOEPCTL |= DOEPCTL_EPDIS | (stall ? DOEPCTL_STALL : 0); + while((out_ep[epnum].DOEPINT & DOEPINT_EPDISD_Msk) == 0); + out_ep[epnum].DOEPINT = DOEPINT_EPDISD; // Allow other OUT endpoints to keep receiving. - dev->DCTL |= USB_OTG_DCTL_CGONAK; + dev->DCTL |= DCTL_CGONAK; } } } @@ -776,8 +760,8 @@ void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr) if (dir == TUSB_DIR_IN) { - uint16_t const fifo_size = (usb_otg->DIEPTXF[epnum - 1] & USB_OTG_DIEPTXF_INEPTXFD_Msk) >> USB_OTG_DIEPTXF_INEPTXFD_Pos; - uint16_t const fifo_start = (usb_otg->DIEPTXF[epnum - 1] & USB_OTG_DIEPTXF_INEPTXSA_Msk) >> USB_OTG_DIEPTXF_INEPTXSA_Pos; + uint16_t const fifo_size = (usb_otg->DIEPTXF[epnum - 1] & DIEPTXF_INEPTXFD_Msk) >> DIEPTXF_INEPTXFD_Pos; + uint16_t const fifo_start = (usb_otg->DIEPTXF[epnum - 1] & DIEPTXF_INEPTXSA_Msk) >> DIEPTXF_INEPTXSA_Pos; // For now only the last opened endpoint can be closed without fuss. TU_ASSERT(fifo_start == EP_FIFO_SIZE/4 - _allocated_fifo_words_tx,); _allocated_fifo_words_tx -= fifo_size; @@ -805,11 +789,11 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) // Clear stall and reset data toggle if(dir == TUSB_DIR_IN) { - in_ep[epnum].DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; - in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; + in_ep[epnum].DIEPCTL &= ~DIEPCTL_STALL; + in_ep[epnum].DIEPCTL |= DIEPCTL_SD0PID_SEVNFRM; } else { - out_ep[epnum].DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; - out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; + out_ep[epnum].DOEPCTL &= ~DOEPCTL_STALL; + out_ep[epnum].DOEPCTL |= DOEPCTL_SD0PID_SEVNFRM; } } @@ -882,9 +866,9 @@ static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep) { // Pop control word off FIFO uint32_t ctl_word = usb_otg->GRXSTSP; - uint8_t pktsts = (ctl_word & USB_OTG_GRXSTSP_PKTSTS_Msk) >> USB_OTG_GRXSTSP_PKTSTS_Pos; - uint8_t epnum = (ctl_word & USB_OTG_GRXSTSP_EPNUM_Msk) >> USB_OTG_GRXSTSP_EPNUM_Pos; - uint16_t bcnt = (ctl_word & USB_OTG_GRXSTSP_BCNT_Msk) >> USB_OTG_GRXSTSP_BCNT_Pos; + uint8_t pktsts = (ctl_word & GRXSTSP_PKTSTS_Msk) >> GRXSTSP_PKTSTS_Pos; + uint8_t epnum = (ctl_word & GRXSTSP_EPNUM_Msk) >> GRXSTSP_EPNUM_Pos; + uint16_t bcnt = (ctl_word & GRXSTSP_BCNT_Msk) >> GRXSTSP_BCNT_Pos; switch(pktsts) { case 0x01: // Global OUT NAK (Interrupt) @@ -911,7 +895,7 @@ static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep) { // Truncate transfer length in case of short packet if(bcnt < xfer->max_size) { - xfer->total_len -= (out_ep[epnum].DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ_Msk) >> USB_OTG_DOEPTSIZ_XFRSIZ_Pos; + xfer->total_len -= (out_ep[epnum].DOEPTSIZ & DOEPTSIZ_XFRSIZ_Msk) >> DOEPTSIZ_XFRSIZ_Pos; if(epnum == 0) { xfer->total_len -= ep0_pending[TUSB_DIR_OUT]; ep0_pending[TUSB_DIR_OUT] = 0; @@ -924,7 +908,7 @@ static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep) { break; case 0x04: // Setup packet done (Interrupt) - out_ep[epnum].DOEPTSIZ |= (3 << USB_OTG_DOEPTSIZ_STUPCNT_Pos); + out_ep[epnum].DOEPTSIZ |= (3 << DOEPTSIZ_STUPCNT_Pos); break; case 0x06: // Setup packet recvd @@ -946,16 +930,16 @@ static void handle_epout_ints(uint8_t rhport, dwc2_device_t * dev, dwc2_epout_t for(uint8_t n = 0; n < EP_MAX; n++) { xfer_ctl_t * xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT); - if(dev->DAINT & (1 << (USB_OTG_DAINT_OEPINT_Pos + n))) { + if(dev->DAINT & (1 << (DAINT_OEPINT_Pos + n))) { // SETUP packet Setup Phase done. - if(out_ep[n].DOEPINT & USB_OTG_DOEPINT_STUP) { - out_ep[n].DOEPINT = USB_OTG_DOEPINT_STUP; + if(out_ep[n].DOEPINT & DOEPINT_STUP) { + out_ep[n].DOEPINT = DOEPINT_STUP; dcd_event_setup_received(rhport, (uint8_t*) &_setup_packet[0], true); } // OUT XFER complete - if(out_ep[n].DOEPINT & USB_OTG_DOEPINT_XFRC) { - out_ep[n].DOEPINT = USB_OTG_DOEPINT_XFRC; + if(out_ep[n].DOEPINT & DOEPINT_XFRC) { + out_ep[n].DOEPINT = DOEPINT_XFRC; // EP0 can only handle one packet if((n == 0) && ep0_pending[TUSB_DIR_OUT]) { @@ -976,12 +960,12 @@ static void handle_epin_ints(uint8_t rhport, dwc2_device_t * dev, dwc2_epin_t * { xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_IN); - if ( dev->DAINT & (1 << (USB_OTG_DAINT_IEPINT_Pos + n)) ) + if ( dev->DAINT & (1 << (DAINT_IEPINT_Pos + n)) ) { // IN XFER complete (entire xfer). - if ( in_ep[n].DIEPINT & USB_OTG_DIEPINT_XFRC ) + if ( in_ep[n].DIEPINT & DIEPINT_XFRC ) { - in_ep[n].DIEPINT = USB_OTG_DIEPINT_XFRC; + in_ep[n].DIEPINT = DIEPINT_XFRC; // EP0 can only handle one packet if((n == 0) && ep0_pending[TUSB_DIR_IN]) { @@ -993,26 +977,26 @@ static void handle_epin_ints(uint8_t rhport, dwc2_device_t * dev, dwc2_epin_t * } // XFER FIFO empty - if ( (in_ep[n].DIEPINT & USB_OTG_DIEPINT_TXFE) && (dev->DIEPEMPMSK & (1 << n)) ) + if ( (in_ep[n].DIEPINT & DIEPINT_TXFE) && (dev->DIEPEMPMSK & (1 << n)) ) { // DIEPINT's TXFE bit is read-only, software cannot clear it. // It will only be cleared by hardware when written bytes is more than // - 64 bytes or // - Half of TX FIFO size (configured by DIEPTXF) - uint16_t remaining_packets = (in_ep[n].DIEPTSIZ & USB_OTG_DIEPTSIZ_PKTCNT_Msk) >> USB_OTG_DIEPTSIZ_PKTCNT_Pos; + uint16_t remaining_packets = (in_ep[n].DIEPTSIZ & DIEPTSIZ_PKTCNT_Msk) >> DIEPTSIZ_PKTCNT_Pos; // Process every single packet (only whole packets can be written to fifo) for(uint16_t i = 0; i < remaining_packets; i++) { - uint16_t const remaining_bytes = (in_ep[n].DIEPTSIZ & USB_OTG_DIEPTSIZ_XFRSIZ_Msk) >> USB_OTG_DIEPTSIZ_XFRSIZ_Pos; + uint16_t const remaining_bytes = (in_ep[n].DIEPTSIZ & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos; // Packet can not be larger than ep max size uint16_t const packet_size = tu_min16(remaining_bytes, xfer->max_size); // It's only possible to write full packets into FIFO. Therefore DTXFSTS register of current // EP has to be checked if the buffer can take another WHOLE packet - if(packet_size > ((in_ep[n].DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV_Msk) << 2)) break; + if(packet_size > ((in_ep[n].DTXFSTS & DTXFSTS_INEPTFSAV_Msk) << 2)) break; // Push packet to Tx-FIFO if (xfer->ff) @@ -1030,7 +1014,7 @@ static void handle_epin_ints(uint8_t rhport, dwc2_device_t * dev, dwc2_epin_t * } // Turn off TXFE if all bytes are written. - if (((in_ep[n].DIEPTSIZ & USB_OTG_DIEPTSIZ_XFRSIZ_Msk) >> USB_OTG_DIEPTSIZ_XFRSIZ_Pos) == 0) + if (((in_ep[n].DIEPTSIZ & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos) == 0) { dev->DIEPEMPMSK &= ~(1 << n); } @@ -1048,18 +1032,18 @@ void dcd_int_handler(uint8_t rhport) uint32_t const int_status = usb_otg->GINTSTS & usb_otg->GINTMSK; - if(int_status & USB_OTG_GINTSTS_USBRST) + if(int_status & GINTSTS_USBRST) { // USBRST is start of reset. - usb_otg->GINTSTS = USB_OTG_GINTSTS_USBRST; + usb_otg->GINTSTS = GINTSTS_USBRST; bus_reset(rhport); } - if(int_status & USB_OTG_GINTSTS_ENUMDNE) + if(int_status & GINTSTS_ENUMDNE) { // ENUMDNE is the end of reset where speed of the link is detected - usb_otg->GINTSTS = USB_OTG_GINTSTS_ENUMDNE; + usb_otg->GINTSTS = GINTSTS_ENUMDNE; tusb_speed_t const speed = get_speed(rhport); @@ -1067,27 +1051,27 @@ void dcd_int_handler(uint8_t rhport) dcd_event_bus_reset(rhport, speed, true); } - if(int_status & USB_OTG_GINTSTS_USBSUSP) + if(int_status & GINTSTS_USBSUSP) { - usb_otg->GINTSTS = USB_OTG_GINTSTS_USBSUSP; + usb_otg->GINTSTS = GINTSTS_USBSUSP; dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); } - if(int_status & USB_OTG_GINTSTS_WKUINT) + if(int_status & GINTSTS_WKUINT) { - usb_otg->GINTSTS = USB_OTG_GINTSTS_WKUINT; + usb_otg->GINTSTS = GINTSTS_WKUINT; dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true); } - // TODO check USB_OTG_GINTSTS_DISCINT for disconnect detection - // if(int_status & USB_OTG_GINTSTS_DISCINT) + // TODO check GINTSTS_DISCINT for disconnect detection + // if(int_status & GINTSTS_DISCINT) - if(int_status & USB_OTG_GINTSTS_OTGINT) + if(int_status & GINTSTS_OTGINT) { // OTG INT bit is read-only uint32_t const otg_int = usb_otg->GOTGINT; - if (otg_int & USB_OTG_GOTGINT_SEDET) + if (otg_int & GOTGINT_SEDET) { dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true); } @@ -1095,29 +1079,29 @@ void dcd_int_handler(uint8_t rhport) usb_otg->GOTGINT = otg_int; } - if(int_status & USB_OTG_GINTSTS_SOF) + if(int_status & GINTSTS_SOF) { - usb_otg->GINTSTS = USB_OTG_GINTSTS_SOF; + usb_otg->GINTSTS = GINTSTS_SOF; // Disable SOF interrupt since currently only used for remote wakeup detection - usb_otg->GINTMSK &= ~USB_OTG_GINTMSK_SOFM; + usb_otg->GINTMSK &= ~GINTMSK_SOFM; dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true); } // RxFIFO non-empty interrupt handling. - if(int_status & USB_OTG_GINTSTS_RXFLVL) + if(int_status & GINTSTS_RXFLVL) { // RXFLVL bit is read-only // Mask out RXFLVL while reading data from FIFO - usb_otg->GINTMSK &= ~USB_OTG_GINTMSK_RXFLVLM; + usb_otg->GINTMSK &= ~GINTMSK_RXFLVLM; // Loop until all available packets were handled do { handle_rxflvl_ints(rhport, out_ep); - } while(usb_otg->GINTSTS & USB_OTG_GINTSTS_RXFLVL); + } while(usb_otg->GINTSTS & GINTSTS_RXFLVL); // Manage RX FIFO size if (_out_ep_closed) @@ -1128,25 +1112,25 @@ void dcd_int_handler(uint8_t rhport) _out_ep_closed = false; } - usb_otg->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; + usb_otg->GINTMSK |= GINTMSK_RXFLVLM; } // OUT endpoint interrupt handling. - if(int_status & USB_OTG_GINTSTS_OEPINT) + if(int_status & GINTSTS_OEPINT) { // OEPINT is read-only handle_epout_ints(rhport, dev, out_ep); } // IN endpoint interrupt handling. - if(int_status & USB_OTG_GINTSTS_IEPINT) + if(int_status & GINTSTS_IEPINT) { // IEPINT bit read-only handle_epin_ints(rhport, dev, in_ep); } // // Check for Incomplete isochronous IN transfer - // if(int_status & USB_OTG_GINTSTS_IISOIXFR) { + // if(int_status & GINTSTS_IISOIXFR) { // printf(" IISOIXFR!\r\n"); //// TU_LOG2(" IISOIXFR!\r\n"); // } diff --git a/src/portable/synopsys/dwc2/dwc2_gd32.h b/src/portable/synopsys/dwc2/dwc2_gd32.h index 5abbd225f..3ace4d484 100644 --- a/src/portable/synopsys/dwc2/dwc2_gd32.h +++ b/src/portable/synopsys/dwc2/dwc2_gd32.h @@ -32,9 +32,10 @@ #define __NOP() __asm volatile ("nop") // These numbers are the same for the whole GD32VF103 family. -#define OTG_FS_IRQn 86 -#define EP_MAX_FS 4 -#define EP_FIFO_SIZE_FS 1280 +#define RHPORT_IRQn 86 +#define EP_MAX 4 +#define EP_FIFO_SIZE 1280 +#define DWC2_REG_BASE 0x50000000UL // The GD32VF103 is a RISC-V MCU, which implements the ECLIC Core-Local // Interrupt Controller by Nuclei. It is nearly API compatible to the diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h index efed6d14a..3a5e1a9ac 100644 --- a/src/portable/synopsys/dwc2/dwc2_stm32.h +++ b/src/portable/synopsys/dwc2/dwc2_stm32.h @@ -69,4 +69,19 @@ #error "Unsupported MCUs" #endif +// On STM32 we associate Port0 to OTG_FS, and Port1 to OTG_HS +#if TUD_OPT_RHPORT == 0 + #define EP_MAX EP_MAX_FS + #define EP_FIFO_SIZE EP_FIFO_SIZE_FS + #define DWC2_REG_BASE USB_OTG_FS_PERIPH_BASE + #define RHPORT_IRQn OTG_FS_IRQn + +#else + #define EP_MAX EP_MAX_HS + #define EP_FIFO_SIZE EP_FIFO_SIZE_HS + #define DWC2_REG_BASE USB_OTG_HS_PERIPH_BASE + #define RHPORT_IRQn OTG_HS_IRQn + +#endif + #endif /* DWC2_STM32_H_ */ diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index 8f48c71eb..5f3b4a420 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -39,14 +39,14 @@ typedef struct { -__IO uint32_t USB_HS_PHYC_PLL; /*!< This register is used to control the PLL of the HS PHY. 000h */ +__IO uint32_t HS_PHYC_PLL; /*!< This register is used to control the PLL of the HS PHY. 000h */ __IO uint32_t Reserved04; /*!< Reserved 004h */ __IO uint32_t Reserved08; /*!< Reserved 008h */ -__IO uint32_t USB_HS_PHYC_TUNE; /*!< This register is used to control the tuning interface of the High Speed PHY. 00Ch */ +__IO uint32_t HS_PHYC_TUNE; /*!< This register is used to control the tuning interface of the High Speed PHY. 00Ch */ __IO uint32_t Reserved10; /*!< Reserved 010h */ __IO uint32_t Reserved14; /*!< Reserved 014h */ -__IO uint32_t USB_HS_PHYC_LDO; /*!< This register is used to control the regulator (LDO). 018h */ -} USB_HS_PHYC_GlobalTypeDef; +__IO uint32_t HS_PHYC_LDO; /*!< This register is used to control the regulator (LDO). 018h */ +} HS_PHYC_GlobalTypeDef; #endif // Core @@ -156,7 +156,10 @@ typedef struct } dwc2_epout_t; -/*!< USB registers base address */ +//--------------------------------------------------------------------+ +// Register Base Address +//--------------------------------------------------------------------+ + #define DWC2_GLOBAL_BASE 0x00000000UL #define DWC2_DEVICE_BASE 0x00000800UL #define DWC2_IN_ENDPOINT_BASE 0x00000900UL @@ -170,1299 +173,1438 @@ typedef struct #define DWC2_FIFO_BASE 0x00001000UL #define DWC2_FIFO_SIZE 0x00001000UL -#if 0 -/******************************************************************************/ -/* */ -/* USB_OTG */ -/* */ -/******************************************************************************/ -/******************** Bit definition for USB_OTG_GOTGCTL register ***********/ -#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U) -#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */ -#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */ -#define USB_OTG_GOTGCTL_SRQ_Pos (1U) -#define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */ -#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */ -#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U) -#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */ -#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */ -#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U) -#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */ -#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */ -#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U) -#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */ -#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */ -#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U) -#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */ -#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */ -#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) -#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ -#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ -#define USB_OTG_GOTGCTL_DBCT_Pos (17U) -#define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ -#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ -#define USB_OTG_GOTGCTL_ASVLD_Pos (18U) -#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ -#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ -#define USB_OTG_GOTGCTL_BSVLD_Pos (19U) -#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */ -#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */ - -/******************** Bit definition for USB_OTG_HCFG register ********************/ - -#define USB_OTG_HCFG_FSLSPCS_Pos (0U) -#define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */ -#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */ -#define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */ -#define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */ -#define USB_OTG_HCFG_FSLSS_Pos (2U) -#define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */ -#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */ - -/******************** Bit definition for USB_OTG_DCFG register ********************/ - -#define USB_OTG_DCFG_DSPD_Pos (0U) -#define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */ -#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */ -#define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */ -#define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */ -#define USB_OTG_DCFG_NZLSOHSK_Pos (2U) -#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */ -#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */ - -#define USB_OTG_DCFG_DAD_Pos (4U) -#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */ -#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ -#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */ -#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */ -#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */ -#define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */ -#define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */ -#define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */ -#define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */ - -#define USB_OTG_DCFG_PFIVL_Pos (11U) -#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */ -#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ -#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ -#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ - -#define USB_OTG_DCFG_PERSCHIVL_Pos (24U) -#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ -#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ -#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */ -#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */ - -/******************** Bit definition for USB_OTG_PCGCR register ********************/ -#define USB_OTG_PCGCR_STPPCLK_Pos (0U) -#define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */ -#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */ -#define USB_OTG_PCGCR_GATEHCLK_Pos (1U) -#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */ -#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */ -#define USB_OTG_PCGCR_PHYSUSP_Pos (4U) -#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */ -#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */ - -/******************** Bit definition for USB_OTG_GOTGINT register ********************/ -#define USB_OTG_GOTGINT_SEDET_Pos (2U) -#define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */ -#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */ -#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U) -#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */ -#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */ -#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U) -#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */ -#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */ -#define USB_OTG_GOTGINT_HNGDET_Pos (17U) -#define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */ -#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */ -#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U) -#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */ -#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */ -#define USB_OTG_GOTGINT_DBCDNE_Pos (19U) -#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */ -#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */ - -/******************** Bit definition for USB_OTG_DCTL register ********************/ -#define USB_OTG_DCTL_RWUSIG_Pos (0U) -#define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */ -#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */ -#define USB_OTG_DCTL_SDIS_Pos (1U) -#define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */ -#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */ -#define USB_OTG_DCTL_GINSTS_Pos (2U) -#define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */ -#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */ -#define USB_OTG_DCTL_GONSTS_Pos (3U) -#define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */ -#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */ - -#define USB_OTG_DCTL_TCTL_Pos (4U) -#define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */ -#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */ -#define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */ -#define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */ -#define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */ -#define USB_OTG_DCTL_SGINAK_Pos (7U) -#define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */ -#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */ -#define USB_OTG_DCTL_CGINAK_Pos (8U) -#define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */ -#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */ -#define USB_OTG_DCTL_SGONAK_Pos (9U) -#define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */ -#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */ -#define USB_OTG_DCTL_CGONAK_Pos (10U) -#define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */ -#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */ -#define USB_OTG_DCTL_POPRGDNE_Pos (11U) -#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ -#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ - -/******************** Bit definition for USB_OTG_HFIR register ********************/ -#define USB_OTG_HFIR_FRIVL_Pos (0U) -#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ - -/******************** Bit definition for USB_OTG_HFNUM register ********************/ -#define USB_OTG_HFNUM_FRNUM_Pos (0U) -#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */ -#define USB_OTG_HFNUM_FTREM_Pos (16U) -#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */ - -/******************** Bit definition for USB_OTG_DSTS register ********************/ -#define USB_OTG_DSTS_SUSPSTS_Pos (0U) -#define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */ -#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */ - -#define USB_OTG_DSTS_ENUMSPD_Pos (1U) -#define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */ -#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */ -#define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */ -#define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */ -#define USB_OTG_DSTS_EERR_Pos (3U) -#define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */ -#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */ -#define USB_OTG_DSTS_FNSOF_Pos (8U) -#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ -#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ - -/******************** Bit definition for USB_OTG_GAHBCFG register ********************/ -#define USB_OTG_GAHBCFG_GINT_Pos (0U) -#define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ -#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ -#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) -#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ -#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ -#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */ -#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */ -#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */ -#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */ -#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */ -#define USB_OTG_GAHBCFG_DMAEN_Pos (5U) -#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */ -#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */ -#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U) -#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */ -#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */ -#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U) -#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */ -#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */ - -/******************** Bit definition for USB_OTG_GUSBCFG register ********************/ - -#define USB_OTG_GUSBCFG_TOCAL_Pos (0U) -#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */ -#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */ -#define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */ -#define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */ -#define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */ -#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U) -#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */ -#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */ -#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U) -#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */ -#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */ -#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U) -#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */ -#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */ -#define USB_OTG_GUSBCFG_TRDT_Pos (10U) -#define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */ -#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */ -#define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */ -#define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ -#define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ -#define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ -#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) -#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ -#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) -#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ -#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ -#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U) -#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */ -#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */ -#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U) -#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */ -#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */ -#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U) -#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */ -#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */ -#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U) -#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */ -#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */ -#define USB_OTG_GUSBCFG_TSDPS_Pos (22U) -#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */ -#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */ -#define USB_OTG_GUSBCFG_PCCI_Pos (23U) -#define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */ -#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */ -#define USB_OTG_GUSBCFG_PTCI_Pos (24U) -#define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */ -#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */ -#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U) -#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */ -#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */ -#define USB_OTG_GUSBCFG_FHMOD_Pos (29U) -#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */ -#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */ -#define USB_OTG_GUSBCFG_FDMOD_Pos (30U) -#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */ -#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */ -#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U) -#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */ - -/******************** Bit definition for USB_OTG_GRSTCTL register ********************/ -#define USB_OTG_GRSTCTL_CSRST_Pos (0U) -#define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ -#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ -#define USB_OTG_GRSTCTL_HSRST_Pos (1U) -#define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ -#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ -#define USB_OTG_GRSTCTL_FCRST_Pos (2U) -#define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ -#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ -#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U) -#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */ -#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */ -#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U) -#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */ -#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */ - - -#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U) -#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */ -#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */ -#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */ -#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */ -#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */ -#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */ -#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */ -#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U) -#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */ -#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */ -#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U) -#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */ -#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */ - -/******************** Bit definition for USB_OTG_DIEPMSK register ********************/ -#define USB_OTG_DIEPMSK_XFRCM_Pos (0U) -#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */ -#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */ -#define USB_OTG_DIEPMSK_EPDM_Pos (1U) -#define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ -#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ -#define USB_OTG_DIEPMSK_TOM_Pos (3U) -#define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ -#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ -#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U) -#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */ -#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ -#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U) -#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */ -#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ -#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U) -#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */ -#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ -#define USB_OTG_DIEPMSK_TXFURM_Pos (8U) -#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */ -#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */ -#define USB_OTG_DIEPMSK_BIM_Pos (9U) -#define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ -#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ - -/******************** Bit definition for USB_OTG_HPTXSTS register ********************/ -#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) -#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */ -#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U) -#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */ -#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */ -#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */ -#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */ -#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */ -#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */ -#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */ -#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */ -#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */ -#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */ - -#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U) -#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */ -#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */ -#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */ -#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */ -#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */ -#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */ -#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */ -#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */ -#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */ -#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for USB_OTG_HAINT register ********************/ -#define USB_OTG_HAINT_HAINT_Pos (0U) -#define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */ - -/******************** Bit definition for USB_OTG_DOEPMSK register ********************/ -#define USB_OTG_DOEPMSK_XFRCM_Pos (0U) -#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */ -#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */ -#define USB_OTG_DOEPMSK_EPDM_Pos (1U) -#define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ -#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ -#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U) -#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ -#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< OUT transaction AHB Error interrupt mask */ -#define USB_OTG_DOEPMSK_STUPM_Pos (3U) -#define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ -#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ -#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) -#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ -#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ -#define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U) -#define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */ -#define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */ -#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) -#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ -#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ -#define USB_OTG_DOEPMSK_OPEM_Pos (8U) -#define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ -#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ -#define USB_OTG_DOEPMSK_BOIM_Pos (9U) -#define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ -#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ -#define USB_OTG_DOEPMSK_BERRM_Pos (12U) -#define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ -#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ -#define USB_OTG_DOEPMSK_NAKM_Pos (13U) -#define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */ -#define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk /*!< OUT Packet NAK interrupt mask */ -#define USB_OTG_DOEPMSK_NYETM_Pos (14U) -#define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */ -#define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk /*!< NYET interrupt mask */ -/******************** Bit definition for USB_OTG_GINTSTS register ********************/ -#define USB_OTG_GINTSTS_CMOD_Pos (0U) -#define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */ -#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */ -#define USB_OTG_GINTSTS_MMIS_Pos (1U) -#define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */ -#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */ -#define USB_OTG_GINTSTS_OTGINT_Pos (2U) -#define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */ -#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */ -#define USB_OTG_GINTSTS_SOF_Pos (3U) -#define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */ -#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */ -#define USB_OTG_GINTSTS_RXFLVL_Pos (4U) -#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */ -#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */ -#define USB_OTG_GINTSTS_NPTXFE_Pos (5U) -#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */ -#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */ -#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) -#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ -#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ -#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) -#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ -#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ -#define USB_OTG_GINTSTS_ESUSP_Pos (10U) -#define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ -#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ -#define USB_OTG_GINTSTS_USBSUSP_Pos (11U) -#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */ -#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */ -#define USB_OTG_GINTSTS_USBRST_Pos (12U) -#define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */ -#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */ -#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U) -#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */ -#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */ -#define USB_OTG_GINTSTS_ISOODRP_Pos (14U) -#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */ -#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */ -#define USB_OTG_GINTSTS_EOPF_Pos (15U) -#define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */ -#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */ -#define USB_OTG_GINTSTS_IEPINT_Pos (18U) -#define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */ -#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */ -#define USB_OTG_GINTSTS_OEPINT_Pos (19U) -#define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */ -#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */ -#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U) -#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */ -#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */ -#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U) -#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */ -#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */ -#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) -#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ -#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ -#define USB_OTG_GINTSTS_HPRTINT_Pos (24U) -#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ -#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ -#define USB_OTG_GINTSTS_HCINT_Pos (25U) -#define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */ -#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */ -#define USB_OTG_GINTSTS_PTXFE_Pos (26U) -#define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */ -#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */ -#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U) -#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */ -#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */ -#define USB_OTG_GINTSTS_DISCINT_Pos (29U) -#define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */ -#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */ -#define USB_OTG_GINTSTS_SRQINT_Pos (30U) -#define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ -#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ -#define USB_OTG_GINTSTS_WKUINT_Pos (31U) -#define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ - -/******************** Bit definition for USB_OTG_GINTMSK register ********************/ -#define USB_OTG_GINTMSK_MMISM_Pos (1U) -#define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */ -#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */ -#define USB_OTG_GINTMSK_OTGINT_Pos (2U) -#define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */ -#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */ -#define USB_OTG_GINTMSK_SOFM_Pos (3U) -#define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */ -#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */ -#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U) -#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */ -#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */ -#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U) -#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */ -#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */ -#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U) -#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */ -#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */ -#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U) -#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */ -#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */ -#define USB_OTG_GINTMSK_ESUSPM_Pos (10U) -#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */ -#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */ -#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U) -#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */ -#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */ -#define USB_OTG_GINTMSK_USBRST_Pos (12U) -#define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */ -#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */ -#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U) -#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */ -#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */ -#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U) -#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */ -#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */ -#define USB_OTG_GINTMSK_EOPFM_Pos (15U) -#define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */ -#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */ -#define USB_OTG_GINTMSK_EPMISM_Pos (17U) -#define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */ -#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */ -#define USB_OTG_GINTMSK_IEPINT_Pos (18U) -#define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */ -#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */ -#define USB_OTG_GINTMSK_OEPINT_Pos (19U) -#define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */ -#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */ -#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) -#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ -#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ -#define USB_OTG_GINTMSK_FSUSPM_Pos (22U) -#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ -#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ -#define USB_OTG_GINTMSK_PRTIM_Pos (24U) -#define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ -#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ -#define USB_OTG_GINTMSK_HCIM_Pos (25U) -#define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */ -#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */ -#define USB_OTG_GINTMSK_PTXFEM_Pos (26U) -#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */ -#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */ -#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U) -#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */ -#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */ -#define USB_OTG_GINTMSK_DISCINT_Pos (29U) -#define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */ -#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */ -#define USB_OTG_GINTMSK_SRQIM_Pos (30U) -#define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */ -#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */ -#define USB_OTG_GINTMSK_WUIM_Pos (31U) -#define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */ -#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */ - -/******************** Bit definition for USB_OTG_DAINT register ********************/ -#define USB_OTG_DAINT_IEPINT_Pos (0U) -#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */ -#define USB_OTG_DAINT_OEPINT_Pos (16U) -#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */ - -/******************** Bit definition for USB_OTG_HAINTMSK register ********************/ -#define USB_OTG_HAINTMSK_HAINTM_Pos (0U) -#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ - -/******************** Bit definition for USB_OTG_GRXSTSP register ********************/ -#define USB_OTG_GRXSTSP_EPNUM_Pos (0U) -#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ -#define USB_OTG_GRXSTSP_BCNT_Pos (4U) -#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ -#define USB_OTG_GRXSTSP_DPID_Pos (15U) -#define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ -#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) -#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ - -/******************** Bit definition for USB_OTG_DAINTMSK register ********************/ -#define USB_OTG_DAINTMSK_IEPM_Pos (0U) -#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */ -#define USB_OTG_DAINTMSK_OEPM_Pos (16U) -#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */ - -/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/ -#define USB_OTG_GRXFSIZ_RXFD_Pos (0U) -#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */ - -/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/ -#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U) -#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */ +//--------------------------------------------------------------------+ +// Register Bit Definitions +//--------------------------------------------------------------------+ + +/******************** Bit definition for GOTGCTL register ********************/ +#define GOTGCTL_SRQSCS_Pos (0U) +#define GOTGCTL_SRQSCS_Msk (0x1UL << GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */ +#define GOTGCTL_SRQSCS GOTGCTL_SRQSCS_Msk /*!< Session request success */ +#define GOTGCTL_SRQ_Pos (1U) +#define GOTGCTL_SRQ_Msk (0x1UL << GOTGCTL_SRQ_Pos) /*!< 0x00000002 */ +#define GOTGCTL_SRQ GOTGCTL_SRQ_Msk /*!< Session request */ +#define GOTGCTL_VBVALOEN_Pos (2U) +#define GOTGCTL_VBVALOEN_Msk (0x1UL << GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */ +#define GOTGCTL_VBVALOEN GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */ +#define GOTGCTL_VBVALOVAL_Pos (3U) +#define GOTGCTL_VBVALOVAL_Msk (0x1UL << GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */ +#define GOTGCTL_VBVALOVAL GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */ +#define GOTGCTL_AVALOEN_Pos (4U) +#define GOTGCTL_AVALOEN_Msk (0x1UL << GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */ +#define GOTGCTL_AVALOEN GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */ +#define GOTGCTL_AVALOVAL_Pos (5U) +#define GOTGCTL_AVALOVAL_Msk (0x1UL << GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */ +#define GOTGCTL_AVALOVAL GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */ +#define GOTGCTL_BVALOEN_Pos (6U) +#define GOTGCTL_BVALOEN_Msk (0x1UL << GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */ +#define GOTGCTL_BVALOEN GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */ +#define GOTGCTL_BVALOVAL_Pos (7U) +#define GOTGCTL_BVALOVAL_Msk (0x1UL << GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */ +#define GOTGCTL_BVALOVAL GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */ +#define GOTGCTL_HNGSCS_Pos (8U) +#define GOTGCTL_HNGSCS_Msk (0x1UL << GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */ +#define GOTGCTL_HNGSCS GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */ +#define GOTGCTL_HNPRQ_Pos (9U) +#define GOTGCTL_HNPRQ_Msk (0x1UL << GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */ +#define GOTGCTL_HNPRQ GOTGCTL_HNPRQ_Msk /*!< HNP request */ +#define GOTGCTL_HSHNPEN_Pos (10U) +#define GOTGCTL_HSHNPEN_Msk (0x1UL << GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */ +#define GOTGCTL_HSHNPEN GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */ +#define GOTGCTL_DHNPEN_Pos (11U) +#define GOTGCTL_DHNPEN_Msk (0x1UL << GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */ +#define GOTGCTL_DHNPEN GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */ +#define GOTGCTL_EHEN_Pos (12U) +#define GOTGCTL_EHEN_Msk (0x1UL << GOTGCTL_EHEN_Pos) /*!< 0x00001000 */ +#define GOTGCTL_EHEN GOTGCTL_EHEN_Msk /*!< Embedded host enable */ +#define GOTGCTL_CIDSTS_Pos (16U) +#define GOTGCTL_CIDSTS_Msk (0x1UL << GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ +#define GOTGCTL_CIDSTS GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ +#define GOTGCTL_DBCT_Pos (17U) +#define GOTGCTL_DBCT_Msk (0x1UL << GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ +#define GOTGCTL_DBCT GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ +#define GOTGCTL_ASVLD_Pos (18U) +#define GOTGCTL_ASVLD_Msk (0x1UL << GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ +#define GOTGCTL_ASVLD GOTGCTL_ASVLD_Msk /*!< A-session valid */ +#define GOTGCTL_BSESVLD_Pos (19U) +#define GOTGCTL_BSESVLD_Msk (0x1UL << GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */ +#define GOTGCTL_BSESVLD GOTGCTL_BSESVLD_Msk /*!< B-session valid */ +#define GOTGCTL_OTGVER_Pos (20U) +#define GOTGCTL_OTGVER_Msk (0x1UL << GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ +#define GOTGCTL_OTGVER GOTGCTL_OTGVER_Msk /*!< OTG version */ + +/******************** Bit definition for HCFG register ********************/ +#define HCFG_FSLSPCS_Pos (0U) +#define HCFG_FSLSPCS_Msk (0x3UL << HCFG_FSLSPCS_Pos) /*!< 0x00000003 */ +#define HCFG_FSLSPCS HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */ +#define HCFG_FSLSPCS_0 (0x1UL << HCFG_FSLSPCS_Pos) /*!< 0x00000001 */ +#define HCFG_FSLSPCS_1 (0x2UL << HCFG_FSLSPCS_Pos) /*!< 0x00000002 */ +#define HCFG_FSLSS_Pos (2U) +#define HCFG_FSLSS_Msk (0x1UL << HCFG_FSLSS_Pos) /*!< 0x00000004 */ +#define HCFG_FSLSS HCFG_FSLSS_Msk /*!< FS- and LS-only support */ + +/******************** Bit definition for DCFG register ********************/ +#define DCFG_DSPD_Pos (0U) +#define DCFG_DSPD_Msk (0x3UL << DCFG_DSPD_Pos) /*!< 0x00000003 */ +#define DCFG_DSPD DCFG_DSPD_Msk /*!< Device speed */ +#define DCFG_DSPD_0 (0x1UL << DCFG_DSPD_Pos) /*!< 0x00000001 */ +#define DCFG_DSPD_1 (0x2UL << DCFG_DSPD_Pos) /*!< 0x00000002 */ +#define DCFG_NZLSOHSK_Pos (2U) +#define DCFG_NZLSOHSK_Msk (0x1UL << DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */ +#define DCFG_NZLSOHSK DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */ + +#define DCFG_DAD_Pos (4U) +#define DCFG_DAD_Msk (0x7FUL << DCFG_DAD_Pos) /*!< 0x000007F0 */ +#define DCFG_DAD DCFG_DAD_Msk /*!< Device address */ +#define DCFG_DAD_0 (0x01UL << DCFG_DAD_Pos) /*!< 0x00000010 */ +#define DCFG_DAD_1 (0x02UL << DCFG_DAD_Pos) /*!< 0x00000020 */ +#define DCFG_DAD_2 (0x04UL << DCFG_DAD_Pos) /*!< 0x00000040 */ +#define DCFG_DAD_3 (0x08UL << DCFG_DAD_Pos) /*!< 0x00000080 */ +#define DCFG_DAD_4 (0x10UL << DCFG_DAD_Pos) /*!< 0x00000100 */ +#define DCFG_DAD_5 (0x20UL << DCFG_DAD_Pos) /*!< 0x00000200 */ +#define DCFG_DAD_6 (0x40UL << DCFG_DAD_Pos) /*!< 0x00000400 */ + +#define DCFG_PFIVL_Pos (11U) +#define DCFG_PFIVL_Msk (0x3UL << DCFG_PFIVL_Pos) /*!< 0x00001800 */ +#define DCFG_PFIVL DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ +#define DCFG_PFIVL_0 (0x1UL << DCFG_PFIVL_Pos) /*!< 0x00000800 */ +#define DCFG_PFIVL_1 (0x2UL << DCFG_PFIVL_Pos) /*!< 0x00001000 */ + +#define DCFG_PERSCHIVL_Pos (24U) +#define DCFG_PERSCHIVL_Msk (0x3UL << DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ +#define DCFG_PERSCHIVL DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ +#define DCFG_PERSCHIVL_0 (0x1UL << DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */ +#define DCFG_PERSCHIVL_1 (0x2UL << DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */ + +/******************** Bit definition for PCGCR register ********************/ +#define PCGCR_STPPCLK_Pos (0U) +#define PCGCR_STPPCLK_Msk (0x1UL << PCGCR_STPPCLK_Pos) /*!< 0x00000001 */ +#define PCGCR_STPPCLK PCGCR_STPPCLK_Msk /*!< Stop PHY clock */ +#define PCGCR_GATEHCLK_Pos (1U) +#define PCGCR_GATEHCLK_Msk (0x1UL << PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */ +#define PCGCR_GATEHCLK PCGCR_GATEHCLK_Msk /*!< Gate HCLK */ +#define PCGCR_PHYSUSP_Pos (4U) +#define PCGCR_PHYSUSP_Msk (0x1UL << PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */ +#define PCGCR_PHYSUSP PCGCR_PHYSUSP_Msk /*!< PHY suspended */ + +/******************** Bit definition for GOTGINT register ********************/ +#define GOTGINT_SEDET_Pos (2U) +#define GOTGINT_SEDET_Msk (0x1UL << GOTGINT_SEDET_Pos) /*!< 0x00000004 */ +#define GOTGINT_SEDET GOTGINT_SEDET_Msk /*!< Session end detected */ +#define GOTGINT_SRSSCHG_Pos (8U) +#define GOTGINT_SRSSCHG_Msk (0x1UL << GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */ +#define GOTGINT_SRSSCHG GOTGINT_SRSSCHG_Msk /*!< Session request success status change */ +#define GOTGINT_HNSSCHG_Pos (9U) +#define GOTGINT_HNSSCHG_Msk (0x1UL << GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */ +#define GOTGINT_HNSSCHG GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */ +#define GOTGINT_HNGDET_Pos (17U) +#define GOTGINT_HNGDET_Msk (0x1UL << GOTGINT_HNGDET_Pos) /*!< 0x00020000 */ +#define GOTGINT_HNGDET GOTGINT_HNGDET_Msk /*!< Host negotiation detected */ +#define GOTGINT_ADTOCHG_Pos (18U) +#define GOTGINT_ADTOCHG_Msk (0x1UL << GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */ +#define GOTGINT_ADTOCHG GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */ +#define GOTGINT_DBCDNE_Pos (19U) +#define GOTGINT_DBCDNE_Msk (0x1UL << GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */ +#define GOTGINT_DBCDNE GOTGINT_DBCDNE_Msk /*!< Debounce done */ +#define GOTGINT_IDCHNG_Pos (20U) +#define GOTGINT_IDCHNG_Msk (0x1UL << GOTGINT_IDCHNG_Pos) /*!< 0x00100000 */ +#define GOTGINT_IDCHNG GOTGINT_IDCHNG_Msk /*!< Change in ID pin input value */ + +/******************** Bit definition for DCTL register ********************/ +#define DCTL_RWUSIG_Pos (0U) +#define DCTL_RWUSIG_Msk (0x1UL << DCTL_RWUSIG_Pos) /*!< 0x00000001 */ +#define DCTL_RWUSIG DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */ +#define DCTL_SDIS_Pos (1U) +#define DCTL_SDIS_Msk (0x1UL << DCTL_SDIS_Pos) /*!< 0x00000002 */ +#define DCTL_SDIS DCTL_SDIS_Msk /*!< Soft disconnect */ +#define DCTL_GINSTS_Pos (2U) +#define DCTL_GINSTS_Msk (0x1UL << DCTL_GINSTS_Pos) /*!< 0x00000004 */ +#define DCTL_GINSTS DCTL_GINSTS_Msk /*!< Global IN NAK status */ +#define DCTL_GONSTS_Pos (3U) +#define DCTL_GONSTS_Msk (0x1UL << DCTL_GONSTS_Pos) /*!< 0x00000008 */ +#define DCTL_GONSTS DCTL_GONSTS_Msk /*!< Global OUT NAK status */ + +#define DCTL_TCTL_Pos (4U) +#define DCTL_TCTL_Msk (0x7UL << DCTL_TCTL_Pos) /*!< 0x00000070 */ +#define DCTL_TCTL DCTL_TCTL_Msk /*!< Test control */ +#define DCTL_TCTL_0 (0x1UL << DCTL_TCTL_Pos) /*!< 0x00000010 */ +#define DCTL_TCTL_1 (0x2UL << DCTL_TCTL_Pos) /*!< 0x00000020 */ +#define DCTL_TCTL_2 (0x4UL << DCTL_TCTL_Pos) /*!< 0x00000040 */ +#define DCTL_SGINAK_Pos (7U) +#define DCTL_SGINAK_Msk (0x1UL << DCTL_SGINAK_Pos) /*!< 0x00000080 */ +#define DCTL_SGINAK DCTL_SGINAK_Msk /*!< Set global IN NAK */ +#define DCTL_CGINAK_Pos (8U) +#define DCTL_CGINAK_Msk (0x1UL << DCTL_CGINAK_Pos) /*!< 0x00000100 */ +#define DCTL_CGINAK DCTL_CGINAK_Msk /*!< Clear global IN NAK */ +#define DCTL_SGONAK_Pos (9U) +#define DCTL_SGONAK_Msk (0x1UL << DCTL_SGONAK_Pos) /*!< 0x00000200 */ +#define DCTL_SGONAK DCTL_SGONAK_Msk /*!< Set global OUT NAK */ +#define DCTL_CGONAK_Pos (10U) +#define DCTL_CGONAK_Msk (0x1UL << DCTL_CGONAK_Pos) /*!< 0x00000400 */ +#define DCTL_CGONAK DCTL_CGONAK_Msk /*!< Clear global OUT NAK */ +#define DCTL_POPRGDNE_Pos (11U) +#define DCTL_POPRGDNE_Msk (0x1UL << DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ +#define DCTL_POPRGDNE DCTL_POPRGDNE_Msk /*!< Power-on programming done */ + +/******************** Bit definition for HFIR register ********************/ +#define HFIR_FRIVL_Pos (0U) +#define HFIR_FRIVL_Msk (0xFFFFUL << HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ +#define HFIR_FRIVL HFIR_FRIVL_Msk /*!< Frame interval */ + +/******************** Bit definition for HFNUM register ********************/ +#define HFNUM_FRNUM_Pos (0U) +#define HFNUM_FRNUM_Msk (0xFFFFUL << HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */ +#define HFNUM_FRNUM HFNUM_FRNUM_Msk /*!< Frame number */ +#define HFNUM_FTREM_Pos (16U) +#define HFNUM_FTREM_Msk (0xFFFFUL << HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */ +#define HFNUM_FTREM HFNUM_FTREM_Msk /*!< Frame time remaining */ + +/******************** Bit definition for DSTS register ********************/ +#define DSTS_SUSPSTS_Pos (0U) +#define DSTS_SUSPSTS_Msk (0x1UL << DSTS_SUSPSTS_Pos) /*!< 0x00000001 */ +#define DSTS_SUSPSTS DSTS_SUSPSTS_Msk /*!< Suspend status */ + +#define DSTS_ENUMSPD_Pos (1U) +#define DSTS_ENUMSPD_Msk (0x3UL << DSTS_ENUMSPD_Pos) /*!< 0x00000006 */ +#define DSTS_ENUMSPD DSTS_ENUMSPD_Msk /*!< Enumerated speed */ +#define DSTS_ENUMSPD_0 (0x1UL << DSTS_ENUMSPD_Pos) /*!< 0x00000002 */ +#define DSTS_ENUMSPD_1 (0x2UL << DSTS_ENUMSPD_Pos) /*!< 0x00000004 */ +#define DSTS_EERR_Pos (3U) +#define DSTS_EERR_Msk (0x1UL << DSTS_EERR_Pos) /*!< 0x00000008 */ +#define DSTS_EERR DSTS_EERR_Msk /*!< Erratic error */ +#define DSTS_FNSOF_Pos (8U) +#define DSTS_FNSOF_Msk (0x3FFFUL << DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ +#define DSTS_FNSOF DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ + +/******************** Bit definition for GAHBCFG register ********************/ +#define GAHBCFG_GINT_Pos (0U) +#define GAHBCFG_GINT_Msk (0x1UL << GAHBCFG_GINT_Pos) /*!< 0x00000001 */ +#define GAHBCFG_GINT GAHBCFG_GINT_Msk /*!< Global interrupt mask */ +#define GAHBCFG_HBSTLEN_Pos (1U) +#define GAHBCFG_HBSTLEN_Msk (0xFUL << GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ +#define GAHBCFG_HBSTLEN GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ +#define GAHBCFG_HBSTLEN_0 (0x0UL << GAHBCFG_HBSTLEN_Pos) /*!< Single */ +#define GAHBCFG_HBSTLEN_1 (0x1UL << GAHBCFG_HBSTLEN_Pos) /*!< INCR */ +#define GAHBCFG_HBSTLEN_2 (0x3UL << GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */ +#define GAHBCFG_HBSTLEN_3 (0x5UL << GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */ +#define GAHBCFG_HBSTLEN_4 (0x7UL << GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */ +#define GAHBCFG_DMAEN_Pos (5U) +#define GAHBCFG_DMAEN_Msk (0x1UL << GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */ +#define GAHBCFG_DMAEN GAHBCFG_DMAEN_Msk /*!< DMA enable */ +#define GAHBCFG_TXFELVL_Pos (7U) +#define GAHBCFG_TXFELVL_Msk (0x1UL << GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */ +#define GAHBCFG_TXFELVL GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */ +#define GAHBCFG_PTXFELVL_Pos (8U) +#define GAHBCFG_PTXFELVL_Msk (0x1UL << GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */ +#define GAHBCFG_PTXFELVL GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */ + +/******************** Bit definition for GUSBCFG register ********************/ +#define GUSBCFG_TOCAL_Pos (0U) +#define GUSBCFG_TOCAL_Msk (0x7UL << GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */ +#define GUSBCFG_TOCAL GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */ +#define GUSBCFG_TOCAL_0 (0x1UL << GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */ +#define GUSBCFG_TOCAL_1 (0x2UL << GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */ +#define GUSBCFG_TOCAL_2 (0x4UL << GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */ +#define GUSBCFG_PHYIF_Pos (3U) +#define GUSBCFG_PHYIF_Msk (0x1UL << GUSBCFG_PHYIF_Pos) /*!< 0x00000008 */ +#define GUSBCFG_PHYIF GUSBCFG_PHYIF_Msk /*!< PHY Interface (PHYIf) */ +#define GUSBCFG_ULPI_UTMI_SEL_Pos (4U) +#define GUSBCFG_ULPI_UTMI_SEL_Msk (0x1UL << GUSBCFG_ULPI_UTMI_SEL_Pos) /*!< 0x00000010 */ +#define GUSBCFG_ULPI_UTMI_SEL GUSBCFG_ULPI_UTMI_SEL_Msk /*!< ULPI or UTMI+ Select (ULPI_UTMI_Sel) */ +#define GUSBCFG_PHYSEL_Pos (6U) +#define GUSBCFG_PHYSEL_Msk (0x1UL << GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */ +#define GUSBCFG_PHYSEL GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */ +#define GUSBCFG_SRPCAP_Pos (8U) +#define GUSBCFG_SRPCAP_Msk (0x1UL << GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */ +#define GUSBCFG_SRPCAP GUSBCFG_SRPCAP_Msk /*!< SRP-capable */ +#define GUSBCFG_HNPCAP_Pos (9U) +#define GUSBCFG_HNPCAP_Msk (0x1UL << GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */ +#define GUSBCFG_HNPCAP GUSBCFG_HNPCAP_Msk /*!< HNP-capable */ +#define GUSBCFG_TRDT_Pos (10U) +#define GUSBCFG_TRDT_Msk (0xFUL << GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */ +#define GUSBCFG_TRDT GUSBCFG_TRDT_Msk /*!< USB turnaround time */ +#define GUSBCFG_TRDT_0 (0x1UL << GUSBCFG_TRDT_Pos) /*!< 0x00000400 */ +#define GUSBCFG_TRDT_1 (0x2UL << GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ +#define GUSBCFG_TRDT_2 (0x4UL << GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ +#define GUSBCFG_TRDT_3 (0x8UL << GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ +#define GUSBCFG_PHYLPCS_Pos (15U) +#define GUSBCFG_PHYLPCS_Msk (0x1UL << GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ +#define GUSBCFG_PHYLPCS GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ +#define GUSBCFG_ULPIFSLS_Pos (17U) +#define GUSBCFG_ULPIFSLS_Msk (0x1UL << GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ +#define GUSBCFG_ULPIFSLS GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ +#define GUSBCFG_ULPIAR_Pos (18U) +#define GUSBCFG_ULPIAR_Msk (0x1UL << GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */ +#define GUSBCFG_ULPIAR GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */ +#define GUSBCFG_ULPICSM_Pos (19U) +#define GUSBCFG_ULPICSM_Msk (0x1UL << GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */ +#define GUSBCFG_ULPICSM GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */ +#define GUSBCFG_ULPIEVBUSD_Pos (20U) +#define GUSBCFG_ULPIEVBUSD_Msk (0x1UL << GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */ +#define GUSBCFG_ULPIEVBUSD GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */ +#define GUSBCFG_ULPIEVBUSI_Pos (21U) +#define GUSBCFG_ULPIEVBUSI_Msk (0x1UL << GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */ +#define GUSBCFG_ULPIEVBUSI GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */ +#define GUSBCFG_TSDPS_Pos (22U) +#define GUSBCFG_TSDPS_Msk (0x1UL << GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */ +#define GUSBCFG_TSDPS GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */ +#define GUSBCFG_PCCI_Pos (23U) +#define GUSBCFG_PCCI_Msk (0x1UL << GUSBCFG_PCCI_Pos) /*!< 0x00800000 */ +#define GUSBCFG_PCCI GUSBCFG_PCCI_Msk /*!< Indicator complement */ +#define GUSBCFG_PTCI_Pos (24U) +#define GUSBCFG_PTCI_Msk (0x1UL << GUSBCFG_PTCI_Pos) /*!< 0x01000000 */ +#define GUSBCFG_PTCI GUSBCFG_PTCI_Msk /*!< Indicator pass through */ +#define GUSBCFG_ULPIIPD_Pos (25U) +#define GUSBCFG_ULPIIPD_Msk (0x1UL << GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */ +#define GUSBCFG_ULPIIPD GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */ +#define GUSBCFG_FHMOD_Pos (29U) +#define GUSBCFG_FHMOD_Msk (0x1UL << GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */ +#define GUSBCFG_FHMOD GUSBCFG_FHMOD_Msk /*!< Forced host mode */ +#define GUSBCFG_FDMOD_Pos (30U) +#define GUSBCFG_FDMOD_Msk (0x1UL << GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */ +#define GUSBCFG_FDMOD GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */ +#define GUSBCFG_CTXPKT_Pos (31U) +#define GUSBCFG_CTXPKT_Msk (0x1UL << GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */ +#define GUSBCFG_CTXPKT GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */ + +/******************** Bit definition for GRSTCTL register ********************/ +#define GRSTCTL_CSRST_Pos (0U) +#define GRSTCTL_CSRST_Msk (0x1UL << GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ +#define GRSTCTL_CSRST GRSTCTL_CSRST_Msk /*!< Core soft reset */ +#define GRSTCTL_HSRST_Pos (1U) +#define GRSTCTL_HSRST_Msk (0x1UL << GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ +#define GRSTCTL_HSRST GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ +#define GRSTCTL_FCRST_Pos (2U) +#define GRSTCTL_FCRST_Msk (0x1UL << GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ +#define GRSTCTL_FCRST GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ +#define GRSTCTL_RXFFLSH_Pos (4U) +#define GRSTCTL_RXFFLSH_Msk (0x1UL << GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */ +#define GRSTCTL_RXFFLSH GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */ +#define GRSTCTL_TXFFLSH_Pos (5U) +#define GRSTCTL_TXFFLSH_Msk (0x1UL << GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */ +#define GRSTCTL_TXFFLSH GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */ +#define GRSTCTL_TXFNUM_Pos (6U) +#define GRSTCTL_TXFNUM_Msk (0x1FUL << GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */ +#define GRSTCTL_TXFNUM GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */ +#define GRSTCTL_TXFNUM_0 (0x01UL << GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */ +#define GRSTCTL_TXFNUM_1 (0x02UL << GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */ +#define GRSTCTL_TXFNUM_2 (0x04UL << GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */ +#define GRSTCTL_TXFNUM_3 (0x08UL << GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */ +#define GRSTCTL_TXFNUM_4 (0x10UL << GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */ +#define GRSTCTL_DMAREQ_Pos (30U) +#define GRSTCTL_DMAREQ_Msk (0x1UL << GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */ +#define GRSTCTL_DMAREQ GRSTCTL_DMAREQ_Msk /*!< DMA request signal */ +#define GRSTCTL_AHBIDL_Pos (31U) +#define GRSTCTL_AHBIDL_Msk (0x1UL << GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */ +#define GRSTCTL_AHBIDL GRSTCTL_AHBIDL_Msk /*!< AHB master idle */ + +/******************** Bit definition for DIEPMSK register ********************/ +#define DIEPMSK_XFRCM_Pos (0U) +#define DIEPMSK_XFRCM_Msk (0x1UL << DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */ +#define DIEPMSK_XFRCM DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */ +#define DIEPMSK_EPDM_Pos (1U) +#define DIEPMSK_EPDM_Msk (0x1UL << DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ +#define DIEPMSK_EPDM DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define DIEPMSK_TOM_Pos (3U) +#define DIEPMSK_TOM_Msk (0x1UL << DIEPMSK_TOM_Pos) /*!< 0x00000008 */ +#define DIEPMSK_TOM DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ +#define DIEPMSK_ITTXFEMSK_Pos (4U) +#define DIEPMSK_ITTXFEMSK_Msk (0x1UL << DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */ +#define DIEPMSK_ITTXFEMSK DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ +#define DIEPMSK_INEPNMM_Pos (5U) +#define DIEPMSK_INEPNMM_Msk (0x1UL << DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */ +#define DIEPMSK_INEPNMM DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ +#define DIEPMSK_INEPNEM_Pos (6U) +#define DIEPMSK_INEPNEM_Msk (0x1UL << DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */ +#define DIEPMSK_INEPNEM DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ +#define DIEPMSK_TXFURM_Pos (8U) +#define DIEPMSK_TXFURM_Msk (0x1UL << DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */ +#define DIEPMSK_TXFURM DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */ +#define DIEPMSK_BIM_Pos (9U) +#define DIEPMSK_BIM_Msk (0x1UL << DIEPMSK_BIM_Pos) /*!< 0x00000200 */ +#define DIEPMSK_BIM DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ + +/******************** Bit definition for HPTXSTS register ********************/ +#define HPTXSTS_PTXFSAVL_Pos (0U) +#define HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */ +#define HPTXSTS_PTXFSAVL HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */ +#define HPTXSTS_PTXQSAV_Pos (16U) +#define HPTXSTS_PTXQSAV_Msk (0xFFUL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */ +#define HPTXSTS_PTXQSAV HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */ +#define HPTXSTS_PTXQSAV_0 (0x01UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */ +#define HPTXSTS_PTXQSAV_1 (0x02UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */ +#define HPTXSTS_PTXQSAV_2 (0x04UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */ +#define HPTXSTS_PTXQSAV_3 (0x08UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */ +#define HPTXSTS_PTXQSAV_4 (0x10UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */ +#define HPTXSTS_PTXQSAV_5 (0x20UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */ +#define HPTXSTS_PTXQSAV_6 (0x40UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */ +#define HPTXSTS_PTXQSAV_7 (0x80UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */ + +#define HPTXSTS_PTXQTOP_Pos (24U) +#define HPTXSTS_PTXQTOP_Msk (0xFFUL << HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */ +#define HPTXSTS_PTXQTOP HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */ +#define HPTXSTS_PTXQTOP_0 (0x01UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */ +#define HPTXSTS_PTXQTOP_1 (0x02UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */ +#define HPTXSTS_PTXQTOP_2 (0x04UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */ +#define HPTXSTS_PTXQTOP_3 (0x08UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */ +#define HPTXSTS_PTXQTOP_4 (0x10UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */ +#define HPTXSTS_PTXQTOP_5 (0x20UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */ +#define HPTXSTS_PTXQTOP_6 (0x40UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */ +#define HPTXSTS_PTXQTOP_7 (0x80UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for HAINT register ********************/ +#define HAINT_HAINT_Pos (0U) +#define HAINT_HAINT_Msk (0xFFFFUL << HAINT_HAINT_Pos) /*!< 0x0000FFFF */ +#define HAINT_HAINT HAINT_HAINT_Msk /*!< Channel interrupts */ + +/******************** Bit definition for DOEPMSK register ********************/ +#define DOEPMSK_XFRCM_Pos (0U) +#define DOEPMSK_XFRCM_Msk (0x1UL << DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */ +#define DOEPMSK_XFRCM DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */ +#define DOEPMSK_EPDM_Pos (1U) +#define DOEPMSK_EPDM_Msk (0x1UL << DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ +#define DOEPMSK_EPDM DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define DOEPMSK_AHBERRM_Pos (2U) +#define DOEPMSK_AHBERRM_Msk (0x1UL << DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define DOEPMSK_AHBERRM DOEPMSK_AHBERRM_Msk /*!< OUT transaction AHB Error interrupt mask */ +#define DOEPMSK_STUPM_Pos (3U) +#define DOEPMSK_STUPM_Msk (0x1UL << DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ +#define DOEPMSK_STUPM DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ +#define DOEPMSK_OTEPDM_Pos (4U) +#define DOEPMSK_OTEPDM_Msk (0x1UL << DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ +#define DOEPMSK_OTEPDM DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ +#define DOEPMSK_OTEPSPRM_Pos (5U) +#define DOEPMSK_OTEPSPRM_Msk (0x1UL << DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */ +#define DOEPMSK_OTEPSPRM DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */ +#define DOEPMSK_B2BSTUP_Pos (6U) +#define DOEPMSK_B2BSTUP_Msk (0x1UL << DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ +#define DOEPMSK_B2BSTUP DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ +#define DOEPMSK_OPEM_Pos (8U) +#define DOEPMSK_OPEM_Msk (0x1UL << DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ +#define DOEPMSK_OPEM DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ +#define DOEPMSK_BOIM_Pos (9U) +#define DOEPMSK_BOIM_Msk (0x1UL << DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ +#define DOEPMSK_BOIM DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ +#define DOEPMSK_BERRM_Pos (12U) +#define DOEPMSK_BERRM_Msk (0x1UL << DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ +#define DOEPMSK_BERRM DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ +#define DOEPMSK_NAKM_Pos (13U) +#define DOEPMSK_NAKM_Msk (0x1UL << DOEPMSK_NAKM_Pos) /*!< 0x00002000 */ +#define DOEPMSK_NAKM DOEPMSK_NAKM_Msk /*!< OUT Packet NAK interrupt mask */ +#define DOEPMSK_NYETM_Pos (14U) +#define DOEPMSK_NYETM_Msk (0x1UL << DOEPMSK_NYETM_Pos) /*!< 0x00004000 */ +#define DOEPMSK_NYETM DOEPMSK_NYETM_Msk /*!< NYET interrupt mask */ + +/******************** Bit definition for GINTSTS register ********************/ +#define GINTSTS_CMOD_Pos (0U) +#define GINTSTS_CMOD_Msk (0x1UL << GINTSTS_CMOD_Pos) /*!< 0x00000001 */ +#define GINTSTS_CMOD GINTSTS_CMOD_Msk /*!< Current mode of operation */ +#define GINTSTS_MMIS_Pos (1U) +#define GINTSTS_MMIS_Msk (0x1UL << GINTSTS_MMIS_Pos) /*!< 0x00000002 */ +#define GINTSTS_MMIS GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */ +#define GINTSTS_OTGINT_Pos (2U) +#define GINTSTS_OTGINT_Msk (0x1UL << GINTSTS_OTGINT_Pos) /*!< 0x00000004 */ +#define GINTSTS_OTGINT GINTSTS_OTGINT_Msk /*!< OTG interrupt */ +#define GINTSTS_SOF_Pos (3U) +#define GINTSTS_SOF_Msk (0x1UL << GINTSTS_SOF_Pos) /*!< 0x00000008 */ +#define GINTSTS_SOF GINTSTS_SOF_Msk /*!< Start of frame */ +#define GINTSTS_RXFLVL_Pos (4U) +#define GINTSTS_RXFLVL_Msk (0x1UL << GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */ +#define GINTSTS_RXFLVL GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */ +#define GINTSTS_NPTXFE_Pos (5U) +#define GINTSTS_NPTXFE_Msk (0x1UL << GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */ +#define GINTSTS_NPTXFE GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */ +#define GINTSTS_GINAKEFF_Pos (6U) +#define GINTSTS_GINAKEFF_Msk (0x1UL << GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ +#define GINTSTS_GINAKEFF GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ +#define GINTSTS_BOUTNAKEFF_Pos (7U) +#define GINTSTS_BOUTNAKEFF_Msk (0x1UL << GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ +#define GINTSTS_BOUTNAKEFF GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ +#define GINTSTS_ESUSP_Pos (10U) +#define GINTSTS_ESUSP_Msk (0x1UL << GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ +#define GINTSTS_ESUSP GINTSTS_ESUSP_Msk /*!< Early suspend */ +#define GINTSTS_USBSUSP_Pos (11U) +#define GINTSTS_USBSUSP_Msk (0x1UL << GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */ +#define GINTSTS_USBSUSP GINTSTS_USBSUSP_Msk /*!< USB suspend */ +#define GINTSTS_USBRST_Pos (12U) +#define GINTSTS_USBRST_Msk (0x1UL << GINTSTS_USBRST_Pos) /*!< 0x00001000 */ +#define GINTSTS_USBRST GINTSTS_USBRST_Msk /*!< USB reset */ +#define GINTSTS_ENUMDNE_Pos (13U) +#define GINTSTS_ENUMDNE_Msk (0x1UL << GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */ +#define GINTSTS_ENUMDNE GINTSTS_ENUMDNE_Msk /*!< Enumeration done */ +#define GINTSTS_ISOODRP_Pos (14U) +#define GINTSTS_ISOODRP_Msk (0x1UL << GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */ +#define GINTSTS_ISOODRP GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */ +#define GINTSTS_EOPF_Pos (15U) +#define GINTSTS_EOPF_Msk (0x1UL << GINTSTS_EOPF_Pos) /*!< 0x00008000 */ +#define GINTSTS_EOPF GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */ +#define GINTSTS_IEPINT_Pos (18U) +#define GINTSTS_IEPINT_Msk (0x1UL << GINTSTS_IEPINT_Pos) /*!< 0x00040000 */ +#define GINTSTS_IEPINT GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */ +#define GINTSTS_OEPINT_Pos (19U) +#define GINTSTS_OEPINT_Msk (0x1UL << GINTSTS_OEPINT_Pos) /*!< 0x00080000 */ +#define GINTSTS_OEPINT GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */ +#define GINTSTS_IISOIXFR_Pos (20U) +#define GINTSTS_IISOIXFR_Msk (0x1UL << GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */ +#define GINTSTS_IISOIXFR GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */ +#define GINTSTS_PXFR_INCOMPISOOUT_Pos (21U) +#define GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */ +#define GINTSTS_PXFR_INCOMPISOOUT GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */ +#define GINTSTS_DATAFSUSP_Pos (22U) +#define GINTSTS_DATAFSUSP_Msk (0x1UL << GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ +#define GINTSTS_DATAFSUSP GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ +#define GINTSTS_RSTDET_Pos (23U) +#define GINTSTS_RSTDET_Msk (0x1UL << GINTSTS_RSTDET_Pos) /*!< 0x00800000 */ +#define GINTSTS_RSTDET GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */ +#define GINTSTS_HPRTINT_Pos (24U) +#define GINTSTS_HPRTINT_Msk (0x1UL << GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ +#define GINTSTS_HPRTINT GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ +#define GINTSTS_HCINT_Pos (25U) +#define GINTSTS_HCINT_Msk (0x1UL << GINTSTS_HCINT_Pos) /*!< 0x02000000 */ +#define GINTSTS_HCINT GINTSTS_HCINT_Msk /*!< Host channels interrupt */ +#define GINTSTS_PTXFE_Pos (26U) +#define GINTSTS_PTXFE_Msk (0x1UL << GINTSTS_PTXFE_Pos) /*!< 0x04000000 */ +#define GINTSTS_PTXFE GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */ +#define GINTSTS_LPMINT_Pos (27U) +#define GINTSTS_LPMINT_Msk (0x1UL << GINTSTS_LPMINT_Pos) /*!< 0x08000000 */ +#define GINTSTS_LPMINT GINTSTS_LPMINT_Msk /*!< LPM interrupt */ +#define GINTSTS_CIDSCHG_Pos (28U) +#define GINTSTS_CIDSCHG_Msk (0x1UL << GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */ +#define GINTSTS_CIDSCHG GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */ +#define GINTSTS_DISCINT_Pos (29U) +#define GINTSTS_DISCINT_Msk (0x1UL << GINTSTS_DISCINT_Pos) /*!< 0x20000000 */ +#define GINTSTS_DISCINT GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */ +#define GINTSTS_SRQINT_Pos (30U) +#define GINTSTS_SRQINT_Msk (0x1UL << GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ +#define GINTSTS_SRQINT GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ +#define GINTSTS_WKUINT_Pos (31U) +#define GINTSTS_WKUINT_Msk (0x1UL << GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ +#define GINTSTS_WKUINT GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ + +/******************** Bit definition for GINTMSK register ********************/ +#define GINTMSK_MMISM_Pos (1U) +#define GINTMSK_MMISM_Msk (0x1UL << GINTMSK_MMISM_Pos) /*!< 0x00000002 */ +#define GINTMSK_MMISM GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */ +#define GINTMSK_OTGINT_Pos (2U) +#define GINTMSK_OTGINT_Msk (0x1UL << GINTMSK_OTGINT_Pos) /*!< 0x00000004 */ +#define GINTMSK_OTGINT GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */ +#define GINTMSK_SOFM_Pos (3U) +#define GINTMSK_SOFM_Msk (0x1UL << GINTMSK_SOFM_Pos) /*!< 0x00000008 */ +#define GINTMSK_SOFM GINTMSK_SOFM_Msk /*!< Start of frame mask */ +#define GINTMSK_RXFLVLM_Pos (4U) +#define GINTMSK_RXFLVLM_Msk (0x1UL << GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */ +#define GINTMSK_RXFLVLM GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */ +#define GINTMSK_NPTXFEM_Pos (5U) +#define GINTMSK_NPTXFEM_Msk (0x1UL << GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */ +#define GINTMSK_NPTXFEM GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */ +#define GINTMSK_GINAKEFFM_Pos (6U) +#define GINTMSK_GINAKEFFM_Msk (0x1UL << GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */ +#define GINTMSK_GINAKEFFM GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */ +#define GINTMSK_GONAKEFFM_Pos (7U) +#define GINTMSK_GONAKEFFM_Msk (0x1UL << GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */ +#define GINTMSK_GONAKEFFM GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */ +#define GINTMSK_ESUSPM_Pos (10U) +#define GINTMSK_ESUSPM_Msk (0x1UL << GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */ +#define GINTMSK_ESUSPM GINTMSK_ESUSPM_Msk /*!< Early suspend mask */ +#define GINTMSK_USBSUSPM_Pos (11U) +#define GINTMSK_USBSUSPM_Msk (0x1UL << GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */ +#define GINTMSK_USBSUSPM GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */ +#define GINTMSK_USBRST_Pos (12U) +#define GINTMSK_USBRST_Msk (0x1UL << GINTMSK_USBRST_Pos) /*!< 0x00001000 */ +#define GINTMSK_USBRST GINTMSK_USBRST_Msk /*!< USB reset mask */ +#define GINTMSK_ENUMDNEM_Pos (13U) +#define GINTMSK_ENUMDNEM_Msk (0x1UL << GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */ +#define GINTMSK_ENUMDNEM GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */ +#define GINTMSK_ISOODRPM_Pos (14U) +#define GINTMSK_ISOODRPM_Msk (0x1UL << GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */ +#define GINTMSK_ISOODRPM GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */ +#define GINTMSK_EOPFM_Pos (15U) +#define GINTMSK_EOPFM_Msk (0x1UL << GINTMSK_EOPFM_Pos) /*!< 0x00008000 */ +#define GINTMSK_EOPFM GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */ +#define GINTMSK_EPMISM_Pos (17U) +#define GINTMSK_EPMISM_Msk (0x1UL << GINTMSK_EPMISM_Pos) /*!< 0x00020000 */ +#define GINTMSK_EPMISM GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */ +#define GINTMSK_IEPINT_Pos (18U) +#define GINTMSK_IEPINT_Msk (0x1UL << GINTMSK_IEPINT_Pos) /*!< 0x00040000 */ +#define GINTMSK_IEPINT GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */ +#define GINTMSK_OEPINT_Pos (19U) +#define GINTMSK_OEPINT_Msk (0x1UL << GINTMSK_OEPINT_Pos) /*!< 0x00080000 */ +#define GINTMSK_OEPINT GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */ +#define GINTMSK_IISOIXFRM_Pos (20U) +#define GINTMSK_IISOIXFRM_Msk (0x1UL << GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ +#define GINTMSK_IISOIXFRM GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ +#define GINTMSK_PXFRM_IISOOXFRM_Pos (21U) +#define GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ +#define GINTMSK_PXFRM_IISOOXFRM GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ +#define GINTMSK_FSUSPM_Pos (22U) +#define GINTMSK_FSUSPM_Msk (0x1UL << GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ +#define GINTMSK_FSUSPM GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ +#define GINTMSK_RSTDEM_Pos (23U) +#define GINTMSK_RSTDEM_Msk (0x1UL << GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */ +#define GINTMSK_RSTDEM GINTMSK_RSTDEM_Msk /*!< Reset detected interrupt mask */ +#define GINTMSK_PRTIM_Pos (24U) +#define GINTMSK_PRTIM_Msk (0x1UL << GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ +#define GINTMSK_PRTIM GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ +#define GINTMSK_HCIM_Pos (25U) +#define GINTMSK_HCIM_Msk (0x1UL << GINTMSK_HCIM_Pos) /*!< 0x02000000 */ +#define GINTMSK_HCIM GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */ +#define GINTMSK_PTXFEM_Pos (26U) +#define GINTMSK_PTXFEM_Msk (0x1UL << GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */ +#define GINTMSK_PTXFEM GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */ +#define GINTMSK_LPMINTM_Pos (27U) +#define GINTMSK_LPMINTM_Msk (0x1UL << GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */ +#define GINTMSK_LPMINTM GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */ +#define GINTMSK_CIDSCHGM_Pos (28U) +#define GINTMSK_CIDSCHGM_Msk (0x1UL << GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */ +#define GINTMSK_CIDSCHGM GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */ +#define GINTMSK_DISCINT_Pos (29U) +#define GINTMSK_DISCINT_Msk (0x1UL << GINTMSK_DISCINT_Pos) /*!< 0x20000000 */ +#define GINTMSK_DISCINT GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */ +#define GINTMSK_SRQIM_Pos (30U) +#define GINTMSK_SRQIM_Msk (0x1UL << GINTMSK_SRQIM_Pos) /*!< 0x40000000 */ +#define GINTMSK_SRQIM GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */ +#define GINTMSK_WUIM_Pos (31U) +#define GINTMSK_WUIM_Msk (0x1UL << GINTMSK_WUIM_Pos) /*!< 0x80000000 */ +#define GINTMSK_WUIM GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */ + +/******************** Bit definition for DAINT register ********************/ +#define DAINT_IEPINT_Pos (0U) +#define DAINT_IEPINT_Msk (0xFFFFUL << DAINT_IEPINT_Pos) /*!< 0x0000FFFF */ +#define DAINT_IEPINT DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */ +#define DAINT_OEPINT_Pos (16U) +#define DAINT_OEPINT_Msk (0xFFFFUL << DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */ +#define DAINT_OEPINT DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */ + +/******************** Bit definition for HAINTMSK register ********************/ +#define HAINTMSK_HAINTM_Pos (0U) +#define HAINTMSK_HAINTM_Msk (0xFFFFUL << HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ +#define HAINTMSK_HAINTM HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ + +/******************** Bit definition for GRXSTSP register ********************/ +#define GRXSTSP_EPNUM_Pos (0U) +#define GRXSTSP_EPNUM_Msk (0xFUL << GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ +#define GRXSTSP_EPNUM GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ +#define GRXSTSP_BCNT_Pos (4U) +#define GRXSTSP_BCNT_Msk (0x7FFUL << GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ +#define GRXSTSP_BCNT GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ +#define GRXSTSP_DPID_Pos (15U) +#define GRXSTSP_DPID_Msk (0x3UL << GRXSTSP_DPID_Pos) /*!< 0x00018000 */ +#define GRXSTSP_DPID GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ +#define GRXSTSP_PKTSTS_Pos (17U) +#define GRXSTSP_PKTSTS_Msk (0xFUL << GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ +#define GRXSTSP_PKTSTS GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ + +/******************** Bit definition for DAINTMSK register ********************/ +#define DAINTMSK_IEPM_Pos (0U) +#define DAINTMSK_IEPM_Msk (0xFFFFUL << DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */ +#define DAINTMSK_IEPM DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */ +#define DAINTMSK_OEPM_Pos (16U) +#define DAINTMSK_OEPM_Msk (0xFFFFUL << DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */ +#define DAINTMSK_OEPM DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */ /******************** Bit definition for OTG register ********************/ -#define USB_OTG_NPTXFSA_Pos (0U) -#define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */ -#define USB_OTG_NPTXFD_Pos (16U) -#define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */ -#define USB_OTG_TX0FSA_Pos (0U) -#define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */ -#define USB_OTG_TX0FD_Pos (16U) -#define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */ - -/******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/ -#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U) -#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */ -#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */ - -/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/ -#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U) -#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */ - -#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U) -#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */ -#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */ -#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */ -#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */ -#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */ -#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */ -#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */ -#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */ -#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */ -#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */ - -#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U) -#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */ -#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */ -#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */ -#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */ -#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */ -#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */ -#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */ -#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */ -#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */ - -/******************** Bit definition for USB_OTG_DTHRCTL register ********************/ -#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U) -#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */ -#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */ -#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U) -#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */ -#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */ - -#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U) -#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */ -#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */ -#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */ -#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */ -#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */ -#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */ -#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */ -#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */ -#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */ -#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */ -#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */ -#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U) -#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */ -#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */ - -#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U) -#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */ -#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */ -#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */ -#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */ -#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */ -#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */ -#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */ -#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */ -#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */ -#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */ -#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */ -#define USB_OTG_DTHRCTL_ARPEN_Pos (27U) -#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */ -#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */ - -/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/ -#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U) -#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */ - -/******************** Bit definition for USB_OTG_DEACHINT register ********************/ -#define USB_OTG_DEACHINT_IEP1INT_Pos (1U) -#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */ -#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */ -#define USB_OTG_DEACHINT_OEP1INT_Pos (17U) -#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */ -#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */ - -/******************** Bit definition for USB_OTG_GCCFG register ********************/ -#define USB_OTG_GCCFG_PWRDWN_Pos (16U) -#define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */ -#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */ -#define USB_OTG_GCCFG_VBUSASEN_Pos (18U) -#define USB_OTG_GCCFG_VBUSASEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */ -#define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk /*!< Enable the VBUS sensing device */ -#define USB_OTG_GCCFG_VBUSBSEN_Pos (19U) -#define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */ -#define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk /*!< Enable the VBUS sensing device */ -#define USB_OTG_GCCFG_SOFOUTEN_Pos (20U) -#define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */ -#define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk /*!< SOF output enable */ - -/******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/ -#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U) -#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */ -#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */ -#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U) -#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */ -#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */ - -/******************** Bit definition for USB_OTG_CID register ********************/ -#define USB_OTG_CID_PRODUCT_ID_Pos (0U) -#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */ -#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */ - -/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ -#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) -#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */ -#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */ -#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U) -#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */ -#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */ -#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U) -#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */ -#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ -#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U) -#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */ -#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ -#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U) -#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */ -#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ -#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U) -#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */ -#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ -#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U) -#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */ -#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */ -#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U) -#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */ -#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */ -#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U) -#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */ -#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */ - -/******************** Bit definition for USB_OTG_HPRT register ********************/ -#define USB_OTG_HPRT_PCSTS_Pos (0U) -#define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */ -#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */ -#define USB_OTG_HPRT_PCDET_Pos (1U) -#define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */ -#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */ -#define USB_OTG_HPRT_PENA_Pos (2U) -#define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */ -#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */ -#define USB_OTG_HPRT_PENCHNG_Pos (3U) -#define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */ -#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */ -#define USB_OTG_HPRT_POCA_Pos (4U) -#define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */ -#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */ -#define USB_OTG_HPRT_POCCHNG_Pos (5U) -#define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */ -#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */ -#define USB_OTG_HPRT_PRES_Pos (6U) -#define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */ -#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */ -#define USB_OTG_HPRT_PSUSP_Pos (7U) -#define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */ -#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */ -#define USB_OTG_HPRT_PRST_Pos (8U) -#define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ -#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ - -#define USB_OTG_HPRT_PLSTS_Pos (10U) -#define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ -#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ -#define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */ -#define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */ -#define USB_OTG_HPRT_PPWR_Pos (12U) -#define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ -#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ - -#define USB_OTG_HPRT_PTCTL_Pos (13U) -#define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ -#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ -#define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */ -#define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ -#define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ -#define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ - -#define USB_OTG_HPRT_PSPD_Pos (17U) -#define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ -#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ -#define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */ -#define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */ - -/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/ -#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U) -#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */ -#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */ -#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U) -#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */ -#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */ -#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U) -#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */ -#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */ -#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U) -#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */ -#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ -#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U) -#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */ -#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ -#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U) -#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */ -#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ -#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U) -#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */ -#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */ -#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U) -#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */ -#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */ -#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U) -#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */ -#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */ -#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U) -#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */ -#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */ -#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U) -#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */ -#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */ - -/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/ -#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) -#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ -#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) -#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ - -/******************** Bit definition for USB_OTG_DIEPCTL register ********************/ -#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) -#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */ -#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */ -#define USB_OTG_DIEPCTL_USBAEP_Pos (15U) -#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */ -#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */ -#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U) -#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */ -#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */ -#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U) -#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ -#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */ - -#define USB_OTG_DIEPCTL_EPTYP_Pos (18U) -#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ -#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */ -#define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */ -#define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */ -#define USB_OTG_DIEPCTL_STALL_Pos (21U) -#define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */ -#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */ - -#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U) -#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */ -#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */ -#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */ -#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */ -#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */ -#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */ -#define USB_OTG_DIEPCTL_CNAK_Pos (26U) -#define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */ -#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */ -#define USB_OTG_DIEPCTL_SNAK_Pos (27U) -#define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */ -#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ -#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) -#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ -#define USB_OTG_DIEPCTL_EPDIS_Pos (30U) -#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ -#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ -#define USB_OTG_DIEPCTL_EPENA_Pos (31U) -#define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */ -#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */ - -/******************** Bit definition for USB_OTG_HCCHAR register ********************/ -#define USB_OTG_HCCHAR_MPSIZ_Pos (0U) -#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ -#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ - -#define USB_OTG_HCCHAR_EPNUM_Pos (11U) -#define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ -#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ -#define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */ -#define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */ -#define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */ -#define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */ -#define USB_OTG_HCCHAR_EPDIR_Pos (15U) -#define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */ -#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */ -#define USB_OTG_HCCHAR_LSDEV_Pos (17U) -#define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ -#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ - -#define USB_OTG_HCCHAR_EPTYP_Pos (18U) -#define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ -#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ -#define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ -#define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ - -#define USB_OTG_HCCHAR_MC_Pos (20U) -#define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ -#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ -#define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ -#define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ - -#define USB_OTG_HCCHAR_DAD_Pos (22U) -#define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ -#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ -#define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */ -#define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */ -#define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */ -#define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */ -#define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */ -#define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */ -#define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */ -#define USB_OTG_HCCHAR_ODDFRM_Pos (29U) -#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */ -#define USB_OTG_HCCHAR_CHDIS_Pos (30U) -#define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */ -#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */ -#define USB_OTG_HCCHAR_CHENA_Pos (31U) -#define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */ -#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */ - -/******************** Bit definition for USB_OTG_HCSPLT register ********************/ - -#define USB_OTG_HCSPLT_PRTADDR_Pos (0U) -#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */ -#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */ -#define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */ -#define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */ -#define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */ -#define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */ -#define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */ -#define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */ -#define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */ - -#define USB_OTG_HCSPLT_HUBADDR_Pos (7U) -#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */ -#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */ -#define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */ -#define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */ -#define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */ -#define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */ -#define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */ -#define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */ -#define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */ - -#define USB_OTG_HCSPLT_XACTPOS_Pos (14U) -#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */ -#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */ -#define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */ -#define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */ -#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U) -#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */ -#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */ -#define USB_OTG_HCSPLT_SPLITEN_Pos (31U) -#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */ -#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */ - -/******************** Bit definition for USB_OTG_HCINT register ********************/ -#define USB_OTG_HCINT_XFRC_Pos (0U) -#define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */ -#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */ -#define USB_OTG_HCINT_CHH_Pos (1U) -#define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */ -#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */ -#define USB_OTG_HCINT_AHBERR_Pos (2U) -#define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */ -#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */ -#define USB_OTG_HCINT_STALL_Pos (3U) -#define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */ -#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */ -#define USB_OTG_HCINT_NAK_Pos (4U) -#define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */ -#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */ -#define USB_OTG_HCINT_ACK_Pos (5U) -#define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */ -#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */ -#define USB_OTG_HCINT_NYET_Pos (6U) -#define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */ -#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */ -#define USB_OTG_HCINT_TXERR_Pos (7U) -#define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */ -#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */ -#define USB_OTG_HCINT_BBERR_Pos (8U) -#define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */ -#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */ -#define USB_OTG_HCINT_FRMOR_Pos (9U) -#define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */ -#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */ -#define USB_OTG_HCINT_DTERR_Pos (10U) -#define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */ -#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */ - -/******************** Bit definition for USB_OTG_DIEPINT register ********************/ -#define USB_OTG_DIEPINT_XFRC_Pos (0U) -#define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */ -#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */ -#define USB_OTG_DIEPINT_EPDISD_Pos (1U) -#define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */ -#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ -#define USB_OTG_DIEPINT_AHBERR_Pos (2U) -#define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */ -#define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an IN transaction */ -#define USB_OTG_DIEPINT_TOC_Pos (3U) -#define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */ -#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */ -#define USB_OTG_DIEPINT_ITTXFE_Pos (4U) -#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ -#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ -#define USB_OTG_DIEPINT_INEPNM_Pos (5U) -#define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000004 */ -#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ -#define USB_OTG_DIEPINT_INEPNE_Pos (6U) -#define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ -#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ -#define USB_OTG_DIEPINT_TXFE_Pos (7U) -#define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */ -#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */ -#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U) -#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */ -#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */ -#define USB_OTG_DIEPINT_BNA_Pos (9U) -#define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */ -#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */ -#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U) -#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */ -#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */ -#define USB_OTG_DIEPINT_BERR_Pos (12U) -#define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */ -#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */ -#define USB_OTG_DIEPINT_NAK_Pos (13U) -#define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */ -#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */ - -/******************** Bit definition for USB_OTG_HCINTMSK register ********************/ -#define USB_OTG_HCINTMSK_XFRCM_Pos (0U) -#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */ -#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */ -#define USB_OTG_HCINTMSK_CHHM_Pos (1U) -#define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ -#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ -#define USB_OTG_HCINTMSK_AHBERR_Pos (2U) -#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ -#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ -#define USB_OTG_HCINTMSK_STALLM_Pos (3U) -#define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ -#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ -#define USB_OTG_HCINTMSK_NAKM_Pos (4U) -#define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */ -#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */ -#define USB_OTG_HCINTMSK_ACKM_Pos (5U) -#define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */ -#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */ -#define USB_OTG_HCINTMSK_NYET_Pos (6U) -#define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */ -#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */ -#define USB_OTG_HCINTMSK_TXERRM_Pos (7U) -#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */ -#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */ -#define USB_OTG_HCINTMSK_BBERRM_Pos (8U) -#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */ -#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */ -#define USB_OTG_HCINTMSK_FRMORM_Pos (9U) -#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */ -#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */ -#define USB_OTG_HCINTMSK_DTERRM_Pos (10U) -#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */ -#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */ - -/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/ - -#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U) -#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ -#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */ -#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) -#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ -#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) -#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ -/******************** Bit definition for USB_OTG_HCTSIZ register ********************/ -#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) -#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ -#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */ -#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) -#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ -#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_HCTSIZ_DOPING_Pos (31U) -#define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ -#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ -#define USB_OTG_HCTSIZ_DPID_Pos (29U) -#define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ -#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ -#define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ -#define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ - -/******************** Bit definition for USB_OTG_DIEPDMA register ********************/ -#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) -#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */ -#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */ - -/******************** Bit definition for USB_OTG_HCDMA register ********************/ -#define USB_OTG_HCDMA_DMAADDR_Pos (0U) -#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */ -#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */ - -/******************** Bit definition for USB_OTG_DTXFSTS register ********************/ -#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U) -#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */ - -/******************** Bit definition for USB_OTG_DIEPTXF register ********************/ -#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U) -#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */ -#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U) -#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */ - -/******************** Bit definition for USB_OTG_DOEPCTL register ********************/ - -#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U) -#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */ -#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*! Date: Mon, 25 Oct 2021 00:11:17 +0700 Subject: minor rename --- src/portable/synopsys/dwc2/dcd_dwc2.c | 124 +++++++++++++++++----------------- 1 file changed, 62 insertions(+), 62 deletions(-) diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 5811afa5a..0be587cb2 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -83,7 +83,7 @@ xfer_ctl_t xfer_status[EP_MAX][2]; // EP0 transfers are limited to 1 packet - larger sizes has to be split static uint16_t ep0_pending[2]; // Index determines direction as tusb_dir_t type -// TX FIFO RAM allocation so far in words - RX FIFO size is readily available from usb_otg->GRXFSIZ +// TX FIFO RAM allocation so far in words - RX FIFO size is readily available from core->GRXFSIZ static uint16_t _allocated_fifo_words_tx; // TX FIFO size in words (IN EPs) static bool _out_ep_closed; // Flag to check if RX FIFO size needs an update (reduce its size) @@ -97,7 +97,7 @@ static void update_grxfsiz(uint8_t rhport) { (void) rhport; - dwc2_core_t * usb_otg = GLOBAL_BASE(rhport); + dwc2_core_t * core = GLOBAL_BASE(rhport); // Determine largest EP size for RX FIFO uint16_t max_epsize = 0; @@ -107,7 +107,7 @@ static void update_grxfsiz(uint8_t rhport) } // Update size of RX FIFO - usb_otg->GRXFSIZ = calc_rx_ff_size(max_epsize); + core->GRXFSIZ = calc_rx_ff_size(max_epsize); } // Setup the control endpoint 0. @@ -115,7 +115,7 @@ static void bus_reset(uint8_t rhport) { (void) rhport; - dwc2_core_t * usb_otg = GLOBAL_BASE(rhport); + dwc2_core_t * core = GLOBAL_BASE(rhport); dwc2_device_t * dev = DEVICE_BASE(rhport); dwc2_epout_t * out_ep = OUT_EP_BASE(rhport); dwc2_epin_t * in_ep = IN_EP_BASE(rhport); @@ -186,12 +186,12 @@ static void bus_reset(uint8_t rhport) // are enabled at least "2 x (Largest-EPsize/4) + 1" are recommended. Maybe provide a macro for application to // overwrite this. - usb_otg->GRXFSIZ = calc_rx_ff_size(TUD_OPT_HIGH_SPEED ? 512 : 64); + core->GRXFSIZ = calc_rx_ff_size(TUD_OPT_HIGH_SPEED ? 512 : 64); _allocated_fifo_words_tx = 16; // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word ) - usb_otg->DIEPTXF0_HNPTXFSIZ = (16 << TX0FD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx); + core->DIEPTXF0_HNPTXFSIZ = (16 << TX0FD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx); // Fixed control EP0 size to 64 bytes in_ep[0].DIEPCTL &= ~(0x03 << DIEPCTL_MPSIZ_Pos); @@ -199,19 +199,19 @@ static void bus_reset(uint8_t rhport) out_ep[0].DOEPTSIZ |= (3 << DOEPTSIZ_STUPCNT_Pos); - usb_otg->GINTMSK |= GINTMSK_OEPINT | GINTMSK_IEPINT; + core->GINTMSK |= GINTMSK_OEPINT | GINTMSK_IEPINT; } // Set turn-around timeout according to link speed extern uint32_t SystemCoreClock; -static void set_turnaround(dwc2_core_t * usb_otg, tusb_speed_t speed) +static void set_turnaround(dwc2_core_t * core, tusb_speed_t speed) { - usb_otg->GUSBCFG &= ~GUSBCFG_TRDT; + core->GUSBCFG &= ~GUSBCFG_TRDT; if ( speed == TUSB_SPEED_HIGH ) { // Use fixed 0x09 for Highspeed - usb_otg->GUSBCFG |= (0x09 << GUSBCFG_TRDT_Pos); + core->GUSBCFG |= (0x09 << GUSBCFG_TRDT_Pos); } else { @@ -240,7 +240,7 @@ static void set_turnaround(dwc2_core_t * usb_otg, tusb_speed_t speed) turnaround = 0xFU; // Fullspeed depends on MCU clocks, but we will use 0x06 for 32+ Mhz - usb_otg->GUSBCFG |= (turnaround << GUSBCFG_TRDT_Pos); + core->GUSBCFG |= (turnaround << GUSBCFG_TRDT_Pos); } } @@ -370,7 +370,7 @@ void dcd_init (uint8_t rhport) { // Programming model begins in the last section of the chapter on the USB // peripheral in each Reference Manual. - dwc2_core_t * usb_otg = GLOBAL_BASE(rhport); + dwc2_core_t * core = GLOBAL_BASE(rhport); // No HNP/SRP (no OTG support), program timeout later. if ( rhport == 1 ) @@ -378,23 +378,23 @@ void dcd_init (uint8_t rhport) // On selected MCUs HS port1 can be used with external PHY via ULPI interface #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED // deactivate internal PHY - usb_otg->GCCFG &= ~GCCFG_PWRDWN; + core->GCCFG &= ~GCCFG_PWRDWN; // Init The UTMI Interface - usb_otg->GUSBCFG &= ~(GUSBCFG_TSDPS | GUSBCFG_ULPIFSLS | GUSBCFG_PHYSEL); + core->GUSBCFG &= ~(GUSBCFG_TSDPS | GUSBCFG_ULPIFSLS | GUSBCFG_PHYSEL); // Select default internal VBUS Indicator and Drive for ULPI - usb_otg->GUSBCFG &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI); + core->GUSBCFG &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI); #else - usb_otg->GUSBCFG |= GUSBCFG_PHYSEL; + core->GUSBCFG |= GUSBCFG_PHYSEL; #endif #if defined(USB_HS_PHYC) // Highspeed with embedded UTMI PHYC // Select UTMI Interface - usb_otg->GUSBCFG &= ~GUSBCFG_ULPI_UTMI_SEL; - usb_otg->GCCFG |= GCCFG_PHYHSEN; + core->GUSBCFG &= ~GUSBCFG_ULPI_UTMI_SEL; + core->GCCFG |= GCCFG_PHYHSEN; // Enables control of a High Speed USB PHY USB_HS_PHYCInit(); @@ -402,25 +402,25 @@ void dcd_init (uint8_t rhport) } else { // Enable internal PHY - usb_otg->GUSBCFG |= GUSBCFG_PHYSEL; + core->GUSBCFG |= GUSBCFG_PHYSEL; } // Reset core after selecting PHYst // Wait AHB IDLE, reset then wait until it is cleared - while ((usb_otg->GRSTCTL & GRSTCTL_AHBIDL) == 0U) {} - usb_otg->GRSTCTL |= GRSTCTL_CSRST; - while ((usb_otg->GRSTCTL & GRSTCTL_CSRST) == GRSTCTL_CSRST) {} + while ((core->GRSTCTL & GRSTCTL_AHBIDL) == 0U) {} + core->GRSTCTL |= GRSTCTL_CSRST; + while ((core->GRSTCTL & GRSTCTL_CSRST) == GRSTCTL_CSRST) {} // Restart PHY clock *((volatile uint32_t *)(DWC2_REG_BASE + DWC2_PCGCCTL_BASE)) = 0; // Clear all interrupts - usb_otg->GINTSTS |= usb_otg->GINTSTS; + core->GINTSTS |= core->GINTSTS; // Required as part of core initialization. // TODO: How should mode mismatch be handled? It will cause // the core to stop working/require reset. - usb_otg->GINTMSK |= GINTMSK_OTGINT | GINTMSK_MMISM; + core->GINTMSK |= GINTMSK_OTGINT | GINTMSK_MMISM; dwc2_device_t * dev = DEVICE_BASE(rhport); @@ -431,14 +431,14 @@ void dcd_init (uint8_t rhport) set_speed(rhport, TUD_OPT_HIGH_SPEED ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL); // Enable internal USB transceiver, unless using HS core (port 1) with external PHY. - if (!(rhport == 1 && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED))) usb_otg->GCCFG |= GCCFG_PWRDWN; + if (!(rhport == 1 && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED))) core->GCCFG |= GCCFG_PWRDWN; - usb_otg->GINTMSK |= GINTMSK_USBRST | GINTMSK_ENUMDNEM | - GINTMSK_USBSUSPM | GINTMSK_WUIM | - GINTMSK_RXFLVLM | (USE_SOF ? GINTMSK_SOFM : 0); + core->GINTMSK |= GINTMSK_USBRST | GINTMSK_ENUMDNEM | + GINTMSK_USBSUSPM | GINTMSK_WUIM | + GINTMSK_RXFLVLM | (USE_SOF ? GINTMSK_SOFM : 0); // Enable global interrupt - usb_otg->GAHBCFG |= GAHBCFG_GINT; + core->GAHBCFG |= GAHBCFG_GINT; dcd_connect(rhport); } @@ -478,15 +478,15 @@ void dcd_remote_wakeup(uint8_t rhport) { (void) rhport; - dwc2_core_t * usb_otg = GLOBAL_BASE(rhport); + dwc2_core_t * core = GLOBAL_BASE(rhport); dwc2_device_t * dev = DEVICE_BASE(rhport); // set remote wakeup dev->DCTL |= DCTL_RWUSIG; // enable SOF to detect bus resume - usb_otg->GINTSTS = GINTSTS_SOF; - usb_otg->GINTMSK |= GINTMSK_SOFM; + core->GINTSTS = GINTSTS_SOF; + core->GINTMSK |= GINTMSK_SOFM; // Per specs: remote wakeup signal bit must be clear within 1-15ms remote_wakeup_delay(); @@ -517,7 +517,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) { (void) rhport; - dwc2_core_t * usb_otg = GLOBAL_BASE(rhport); + dwc2_core_t * core = GLOBAL_BASE(rhport); dwc2_device_t * dev = DEVICE_BASE(rhport); dwc2_epout_t * out_ep = OUT_EP_BASE(rhport); dwc2_epin_t * in_ep = IN_EP_BASE(rhport); @@ -539,12 +539,12 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) uint16_t const sz = calc_rx_ff_size(4*fifo_size); // If size_rx needs to be extended check if possible and if so enlarge it - if (usb_otg->GRXFSIZ < sz) + if (core->GRXFSIZ < sz) { TU_ASSERT(sz + _allocated_fifo_words_tx <= EP_FIFO_SIZE/4); // Enlarge RX FIFO - usb_otg->GRXFSIZ = sz; + core->GRXFSIZ = sz; } out_ep[epnum].DOEPCTL |= (1 << DOEPCTL_USBAEP_Pos) | @@ -578,7 +578,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n". // Check if free space is available - TU_ASSERT(_allocated_fifo_words_tx + fifo_size + usb_otg->GRXFSIZ <= EP_FIFO_SIZE/4); + TU_ASSERT(_allocated_fifo_words_tx + fifo_size + core->GRXFSIZ <= EP_FIFO_SIZE/4); _allocated_fifo_words_tx += fifo_size; @@ -586,7 +586,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) // DIEPTXF starts at FIFO #1. // Both TXFD and TXSA are in unit of 32-bit words. - usb_otg->DIEPTXF[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx); + core->DIEPTXF[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx); in_ep[epnum].DIEPCTL |= (1 << DIEPCTL_USBAEP_Pos) | (epnum << DIEPCTL_TXFNUM_Pos) | @@ -605,7 +605,7 @@ void dcd_edpt_close_all (uint8_t rhport) { (void) rhport; -// dwc2_core_t * usb_otg = GLOBAL_BASE(rhport); +// dwc2_core_t * core = GLOBAL_BASE(rhport); dwc2_device_t * dev = DEVICE_BASE(rhport); dwc2_epout_t * out_ep = OUT_EP_BASE(rhport); dwc2_epin_t * in_ep = IN_EP_BASE(rhport); @@ -693,7 +693,7 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall) { (void) rhport; - dwc2_core_t * usb_otg = GLOBAL_BASE(rhport); + dwc2_core_t * core = GLOBAL_BASE(rhport); dwc2_device_t * dev = DEVICE_BASE(rhport); dwc2_epout_t * out_ep = OUT_EP_BASE(rhport); dwc2_epin_t * in_ep = IN_EP_BASE(rhport); @@ -717,9 +717,9 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall) } // Flush the FIFO, and wait until we have confirmed it cleared. - usb_otg->GRSTCTL |= (epnum << GRSTCTL_TXFNUM_Pos); - usb_otg->GRSTCTL |= GRSTCTL_TXFFLSH; - while((usb_otg->GRSTCTL & GRSTCTL_TXFFLSH_Msk) != 0); + core->GRSTCTL |= (epnum << GRSTCTL_TXFNUM_Pos); + core->GRSTCTL |= GRSTCTL_TXFFLSH; + while((core->GRSTCTL & GRSTCTL_TXFFLSH_Msk) != 0); } else { // Only disable currently enabled non-control endpoint if ( (epnum == 0) || !(out_ep[epnum].DOEPCTL & DOEPCTL_EPENA) ){ @@ -730,7 +730,7 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall) // anyway, and it can't be cleared by user code. If this while loop never // finishes, we have bigger problems than just the stack. dev->DCTL |= DCTL_SGONAK; - while((usb_otg->GINTSTS & GINTSTS_BOUTNAKEFF_Msk) == 0); + while((core->GINTSTS & GINTSTS_BOUTNAKEFF_Msk) == 0); // Ditto here- disable the endpoint. out_ep[epnum].DOEPCTL |= DOEPCTL_EPDIS | (stall ? DOEPCTL_STALL : 0); @@ -748,7 +748,7 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall) */ void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr) { - dwc2_core_t * usb_otg = GLOBAL_BASE(rhport); + dwc2_core_t * core = GLOBAL_BASE(rhport); uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); @@ -760,8 +760,8 @@ void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr) if (dir == TUSB_DIR_IN) { - uint16_t const fifo_size = (usb_otg->DIEPTXF[epnum - 1] & DIEPTXF_INEPTXFD_Msk) >> DIEPTXF_INEPTXFD_Pos; - uint16_t const fifo_start = (usb_otg->DIEPTXF[epnum - 1] & DIEPTXF_INEPTXSA_Msk) >> DIEPTXF_INEPTXSA_Pos; + uint16_t const fifo_size = (core->DIEPTXF[epnum - 1] & DIEPTXF_INEPTXFD_Msk) >> DIEPTXF_INEPTXFD_Pos; + uint16_t const fifo_start = (core->DIEPTXF[epnum - 1] & DIEPTXF_INEPTXSA_Msk) >> DIEPTXF_INEPTXSA_Pos; // For now only the last opened endpoint can be closed without fuss. TU_ASSERT(fifo_start == EP_FIFO_SIZE/4 - _allocated_fifo_words_tx,); _allocated_fifo_words_tx -= fifo_size; @@ -861,11 +861,11 @@ static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t * src, u } static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep) { - dwc2_core_t * usb_otg = GLOBAL_BASE(rhport); + dwc2_core_t * core = GLOBAL_BASE(rhport); usb_fifo_t rx_fifo = FIFO_BASE(rhport, 0); // Pop control word off FIFO - uint32_t ctl_word = usb_otg->GRXSTSP; + uint32_t ctl_word = core->GRXSTSP; uint8_t pktsts = (ctl_word & GRXSTSP_PKTSTS_Msk) >> GRXSTSP_PKTSTS_Pos; uint8_t epnum = (ctl_word & GRXSTSP_EPNUM_Msk) >> GRXSTSP_EPNUM_Pos; uint16_t bcnt = (ctl_word & GRXSTSP_BCNT_Msk) >> GRXSTSP_BCNT_Pos; @@ -1025,17 +1025,17 @@ static void handle_epin_ints(uint8_t rhport, dwc2_device_t * dev, dwc2_epin_t * void dcd_int_handler(uint8_t rhport) { - dwc2_core_t * usb_otg = GLOBAL_BASE(rhport); + dwc2_core_t * core = GLOBAL_BASE(rhport); dwc2_device_t * dev = DEVICE_BASE(rhport); dwc2_epout_t * out_ep = OUT_EP_BASE(rhport); dwc2_epin_t * in_ep = IN_EP_BASE(rhport); - uint32_t const int_status = usb_otg->GINTSTS & usb_otg->GINTMSK; + uint32_t const int_status = core->GINTSTS & core->GINTMSK; if(int_status & GINTSTS_USBRST) { // USBRST is start of reset. - usb_otg->GINTSTS = GINTSTS_USBRST; + core->GINTSTS = GINTSTS_USBRST; bus_reset(rhport); } @@ -1043,23 +1043,23 @@ void dcd_int_handler(uint8_t rhport) { // ENUMDNE is the end of reset where speed of the link is detected - usb_otg->GINTSTS = GINTSTS_ENUMDNE; + core->GINTSTS = GINTSTS_ENUMDNE; tusb_speed_t const speed = get_speed(rhport); - set_turnaround(usb_otg, speed); + set_turnaround(core, speed); dcd_event_bus_reset(rhport, speed, true); } if(int_status & GINTSTS_USBSUSP) { - usb_otg->GINTSTS = GINTSTS_USBSUSP; + core->GINTSTS = GINTSTS_USBSUSP; dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); } if(int_status & GINTSTS_WKUINT) { - usb_otg->GINTSTS = GINTSTS_WKUINT; + core->GINTSTS = GINTSTS_WKUINT; dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true); } @@ -1069,22 +1069,22 @@ void dcd_int_handler(uint8_t rhport) if(int_status & GINTSTS_OTGINT) { // OTG INT bit is read-only - uint32_t const otg_int = usb_otg->GOTGINT; + uint32_t const otg_int = core->GOTGINT; if (otg_int & GOTGINT_SEDET) { dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true); } - usb_otg->GOTGINT = otg_int; + core->GOTGINT = otg_int; } if(int_status & GINTSTS_SOF) { - usb_otg->GINTSTS = GINTSTS_SOF; + core->GINTSTS = GINTSTS_SOF; // Disable SOF interrupt since currently only used for remote wakeup detection - usb_otg->GINTMSK &= ~GINTMSK_SOFM; + core->GINTMSK &= ~GINTMSK_SOFM; dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true); } @@ -1095,13 +1095,13 @@ void dcd_int_handler(uint8_t rhport) // RXFLVL bit is read-only // Mask out RXFLVL while reading data from FIFO - usb_otg->GINTMSK &= ~GINTMSK_RXFLVLM; + core->GINTMSK &= ~GINTMSK_RXFLVLM; // Loop until all available packets were handled do { handle_rxflvl_ints(rhport, out_ep); - } while(usb_otg->GINTSTS & GINTSTS_RXFLVL); + } while(core->GINTSTS & GINTSTS_RXFLVL); // Manage RX FIFO size if (_out_ep_closed) @@ -1112,7 +1112,7 @@ void dcd_int_handler(uint8_t rhport) _out_ep_closed = false; } - usb_otg->GINTMSK |= GINTMSK_RXFLVLM; + core->GINTMSK |= GINTMSK_RXFLVLM; } // OUT endpoint interrupt handling. -- cgit v1.3.1 From 4ab931a36167f579f556bd3fed4946cf78865646 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 25 Oct 2021 00:16:11 +0700 Subject: more clean up --- src/portable/synopsys/dwc2/dcd_dwc2.c | 102 ++++++++++++++++------------------ 1 file changed, 49 insertions(+), 53 deletions(-) diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 0be587cb2..aae6e7004 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -44,18 +44,14 @@ #include "device/dcd.h" -// Since TinyUSB doesn't use SOF for now, and this interrupt too often (1ms interval) -// We disable SOF for now until needed later on -#define USE_SOF 0 - //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ -#define GLOBAL_BASE(_port) ((dwc2_core_t*) DWC2_REG_BASE) -#define DEVICE_BASE(_port) ((dwc2_device_t*) (DWC2_REG_BASE + DWC2_DEVICE_BASE)) -#define IN_EP_BASE(_port) ((dwc2_epin_t*) (DWC2_REG_BASE + DWC2_IN_ENDPOINT_BASE)) -#define OUT_EP_BASE(_port) ((dwc2_epout_t*) (DWC2_REG_BASE + DWC2_OUT_ENDPOINT_BASE)) +#define CORE_REG(_port) ((dwc2_core_t*) DWC2_REG_BASE) +#define DEVICE_REG(_port) ((dwc2_device_t*) (DWC2_REG_BASE + DWC2_DEVICE_BASE)) +#define EPIN_REG(_port) ((dwc2_epin_t*) (DWC2_REG_BASE + DWC2_IN_ENDPOINT_BASE)) +#define EPOUT_REG(_port) ((dwc2_epout_t*) (DWC2_REG_BASE + DWC2_OUT_ENDPOINT_BASE)) #define FIFO_BASE(_port, _x) ((volatile uint32_t*) (DWC2_REG_BASE + DWC2_FIFO_BASE + (_x) * DWC2_FIFO_SIZE)) enum @@ -97,7 +93,7 @@ static void update_grxfsiz(uint8_t rhport) { (void) rhport; - dwc2_core_t * core = GLOBAL_BASE(rhport); + dwc2_core_t * core = CORE_REG(rhport); // Determine largest EP size for RX FIFO uint16_t max_epsize = 0; @@ -115,10 +111,10 @@ static void bus_reset(uint8_t rhport) { (void) rhport; - dwc2_core_t * core = GLOBAL_BASE(rhport); - dwc2_device_t * dev = DEVICE_BASE(rhport); - dwc2_epout_t * out_ep = OUT_EP_BASE(rhport); - dwc2_epin_t * in_ep = IN_EP_BASE(rhport); + dwc2_core_t * core = CORE_REG(rhport); + dwc2_device_t * dev = DEVICE_REG(rhport); + dwc2_epout_t * out_ep = EPOUT_REG(rhport); + dwc2_epin_t * in_ep = EPIN_REG(rhport); tu_memclr(xfer_status, sizeof(xfer_status)); _out_ep_closed = false; @@ -133,8 +129,8 @@ static void bus_reset(uint8_t rhport) // 2. Un-mask interrupt bits dev->DAINTMSK = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos); - dev->DOEPMSK = DOEPMSK_STUPM | DOEPMSK_XFRCM; - dev->DIEPMSK = DIEPMSK_TOM | DIEPMSK_XFRCM; + dev->DOEPMSK = DOEPMSK_STUPM | DOEPMSK_XFRCM; + dev->DIEPMSK = DIEPMSK_TOM | DIEPMSK_XFRCM; // "USB Data FIFOs" section in reference manual // Peripheral FIFO architecture @@ -247,7 +243,7 @@ static void set_turnaround(dwc2_core_t * core, tusb_speed_t speed) static tusb_speed_t get_speed(uint8_t rhport) { (void) rhport; - dwc2_device_t * dev = DEVICE_BASE(rhport); + dwc2_device_t * dev = DEVICE_REG(rhport); uint32_t const enum_spd = (dev->DSTS & DSTS_ENUMSPD_Msk) >> DSTS_ENUMSPD_Pos; return (enum_spd == DCD_HIGH_SPEED) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL; } @@ -265,7 +261,7 @@ static void set_speed(uint8_t rhport, tusb_speed_t speed) bitvalue = DCD_FULL_SPEED; } - dwc2_device_t * dev = DEVICE_BASE(rhport); + dwc2_device_t * dev = DEVICE_REG(rhport); // Clear and set speed bits dev->DCFG &= ~(3 << DCFG_DSPD_Pos); @@ -317,9 +313,9 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c { (void) rhport; - dwc2_device_t * dev = DEVICE_BASE(rhport); - dwc2_epout_t * out_ep = OUT_EP_BASE(rhport); - dwc2_epin_t * in_ep = IN_EP_BASE(rhport); + dwc2_device_t * dev = DEVICE_REG(rhport); + dwc2_epout_t * out_ep = EPOUT_REG(rhport); + dwc2_epin_t * in_ep = EPIN_REG(rhport); // EP0 is limited to one packet each xfer // We use multiple transaction of xfer->max_size length to get a whole transfer done @@ -336,6 +332,7 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c ((total_bytes << DIEPTSIZ_XFRSIZ_Pos) & DIEPTSIZ_XFRSIZ_Msk); in_ep[epnum].DIEPCTL |= DIEPCTL_EPENA | DIEPCTL_CNAK; + // For ISO endpoint set correct odd/even bit for next frame. if ((in_ep[epnum].DIEPCTL & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) { @@ -370,7 +367,7 @@ void dcd_init (uint8_t rhport) { // Programming model begins in the last section of the chapter on the USB // peripheral in each Reference Manual. - dwc2_core_t * core = GLOBAL_BASE(rhport); + dwc2_core_t * core = CORE_REG(rhport); // No HNP/SRP (no OTG support), program timeout later. if ( rhport == 1 ) @@ -422,7 +419,7 @@ void dcd_init (uint8_t rhport) // the core to stop working/require reset. core->GINTMSK |= GINTMSK_OTGINT | GINTMSK_MMISM; - dwc2_device_t * dev = DEVICE_BASE(rhport); + dwc2_device_t * dev = DEVICE_REG(rhport); // If USB host misbehaves during status portion of control xfer // (non zero-length packet), send STALL back and discard. @@ -433,9 +430,8 @@ void dcd_init (uint8_t rhport) // Enable internal USB transceiver, unless using HS core (port 1) with external PHY. if (!(rhport == 1 && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED))) core->GCCFG |= GCCFG_PWRDWN; - core->GINTMSK |= GINTMSK_USBRST | GINTMSK_ENUMDNEM | - GINTMSK_USBSUSPM | GINTMSK_WUIM | - GINTMSK_RXFLVLM | (USE_SOF ? GINTMSK_SOFM : 0); + core->GINTMSK |= GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_USBSUSPM | + GINTMSK_WUIM | GINTMSK_RXFLVLM; // Enable global interrupt core->GAHBCFG |= GAHBCFG_GINT; @@ -457,7 +453,7 @@ void dcd_int_disable (uint8_t rhport) void dcd_set_address (uint8_t rhport, uint8_t dev_addr) { - dwc2_device_t * dev = DEVICE_BASE(rhport); + dwc2_device_t * dev = DEVICE_REG(rhport); dev->DCFG = (dev->DCFG & ~DCFG_DAD_Msk) | (dev_addr << DCFG_DAD_Pos); // Response with status after changing device address @@ -478,8 +474,8 @@ void dcd_remote_wakeup(uint8_t rhport) { (void) rhport; - dwc2_core_t * core = GLOBAL_BASE(rhport); - dwc2_device_t * dev = DEVICE_BASE(rhport); + dwc2_core_t * core = CORE_REG(rhport); + dwc2_device_t * dev = DEVICE_REG(rhport); // set remote wakeup dev->DCTL |= DCTL_RWUSIG; @@ -497,14 +493,14 @@ void dcd_remote_wakeup(uint8_t rhport) void dcd_connect(uint8_t rhport) { (void) rhport; - dwc2_device_t * dev = DEVICE_BASE(rhport); + dwc2_device_t * dev = DEVICE_REG(rhport); dev->DCTL &= ~DCTL_SDIS; } void dcd_disconnect(uint8_t rhport) { (void) rhport; - dwc2_device_t * dev = DEVICE_BASE(rhport); + dwc2_device_t * dev = DEVICE_REG(rhport); dev->DCTL |= DCTL_SDIS; } @@ -517,10 +513,10 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) { (void) rhport; - dwc2_core_t * core = GLOBAL_BASE(rhport); - dwc2_device_t * dev = DEVICE_BASE(rhport); - dwc2_epout_t * out_ep = OUT_EP_BASE(rhport); - dwc2_epin_t * in_ep = IN_EP_BASE(rhport); + dwc2_core_t * core = CORE_REG(rhport); + dwc2_device_t * dev = DEVICE_REG(rhport); + dwc2_epout_t * out_ep = EPOUT_REG(rhport); + dwc2_epin_t * in_ep = EPIN_REG(rhport); uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress); uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress); @@ -605,10 +601,10 @@ void dcd_edpt_close_all (uint8_t rhport) { (void) rhport; -// dwc2_core_t * core = GLOBAL_BASE(rhport); - dwc2_device_t * dev = DEVICE_BASE(rhport); - dwc2_epout_t * out_ep = OUT_EP_BASE(rhport); - dwc2_epin_t * in_ep = IN_EP_BASE(rhport); +// dwc2_core_t * core = CORE_REG(rhport); + dwc2_device_t * dev = DEVICE_REG(rhport); + dwc2_epout_t * out_ep = EPOUT_REG(rhport); + dwc2_epin_t * in_ep = EPIN_REG(rhport); // Disable non-control interrupt dev->DAINTMSK = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos); @@ -693,10 +689,10 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall) { (void) rhport; - dwc2_core_t * core = GLOBAL_BASE(rhport); - dwc2_device_t * dev = DEVICE_BASE(rhport); - dwc2_epout_t * out_ep = OUT_EP_BASE(rhport); - dwc2_epin_t * in_ep = IN_EP_BASE(rhport); + dwc2_core_t * core = CORE_REG(rhport); + dwc2_device_t * dev = DEVICE_REG(rhport); + dwc2_epout_t * out_ep = EPOUT_REG(rhport); + dwc2_epin_t * in_ep = EPIN_REG(rhport); uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); @@ -748,7 +744,7 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall) */ void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr) { - dwc2_core_t * core = GLOBAL_BASE(rhport); + dwc2_core_t * core = CORE_REG(rhport); uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); @@ -781,8 +777,8 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) { (void) rhport; - dwc2_epout_t * out_ep = OUT_EP_BASE(rhport); - dwc2_epin_t * in_ep = IN_EP_BASE(rhport); + dwc2_epout_t * out_ep = EPOUT_REG(rhport); + dwc2_epin_t * in_ep = EPIN_REG(rhport); uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); @@ -861,14 +857,14 @@ static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t * src, u } static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep) { - dwc2_core_t * core = GLOBAL_BASE(rhport); + dwc2_core_t * core = CORE_REG(rhport); usb_fifo_t rx_fifo = FIFO_BASE(rhport, 0); // Pop control word off FIFO uint32_t ctl_word = core->GRXSTSP; - uint8_t pktsts = (ctl_word & GRXSTSP_PKTSTS_Msk) >> GRXSTSP_PKTSTS_Pos; - uint8_t epnum = (ctl_word & GRXSTSP_EPNUM_Msk) >> GRXSTSP_EPNUM_Pos; - uint16_t bcnt = (ctl_word & GRXSTSP_BCNT_Msk) >> GRXSTSP_BCNT_Pos; + uint8_t pktsts = (ctl_word & GRXSTSP_PKTSTS_Msk) >> GRXSTSP_PKTSTS_Pos; + uint8_t epnum = (ctl_word & GRXSTSP_EPNUM_Msk) >> GRXSTSP_EPNUM_Pos; + uint16_t bcnt = (ctl_word & GRXSTSP_BCNT_Msk) >> GRXSTSP_BCNT_Pos; switch(pktsts) { case 0x01: // Global OUT NAK (Interrupt) @@ -1025,10 +1021,10 @@ static void handle_epin_ints(uint8_t rhport, dwc2_device_t * dev, dwc2_epin_t * void dcd_int_handler(uint8_t rhport) { - dwc2_core_t * core = GLOBAL_BASE(rhport); - dwc2_device_t * dev = DEVICE_BASE(rhport); - dwc2_epout_t * out_ep = OUT_EP_BASE(rhport); - dwc2_epin_t * in_ep = IN_EP_BASE(rhport); + dwc2_core_t * core = CORE_REG(rhport); + dwc2_device_t * dev = DEVICE_REG(rhport); + dwc2_epout_t * out_ep = EPOUT_REG(rhport); + dwc2_epin_t * in_ep = EPIN_REG(rhport); uint32_t const int_status = core->GINTSTS & core->GINTMSK; -- cgit v1.3.1 From 61c80840c30db790560076fef9808cccc3fdf361 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 25 Oct 2021 00:39:37 +0700 Subject: update dwc int enable/disable --- src/portable/synopsys/dwc2/dcd_dwc2.c | 17 +++++++---------- src/portable/synopsys/dwc2/dwc2_gd32.h | 22 +++++++++++++++++----- src/portable/synopsys/dwc2/dwc2_stm32.h | 14 ++++++++++++++ 3 files changed, 38 insertions(+), 15 deletions(-) diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index aae6e7004..367fc7b56 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -32,6 +32,7 @@ #if TUSB_OPT_DEVICE_ENABLED && (defined(DCD_ATTR_DWC2_STM32) || TU_CHECK_MCU(GD32VF103)) +#include "device/dcd.h" #include "dwc2_type.h" #if defined(DCD_ATTR_DWC2_STM32) @@ -42,17 +43,15 @@ #error "Unsupported MCUs" #endif -#include "device/dcd.h" - //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ -#define CORE_REG(_port) ((dwc2_core_t*) DWC2_REG_BASE) +#define CORE_REG(_port) ((dwc2_core_t*) DWC2_REG_BASE) #define DEVICE_REG(_port) ((dwc2_device_t*) (DWC2_REG_BASE + DWC2_DEVICE_BASE)) -#define EPIN_REG(_port) ((dwc2_epin_t*) (DWC2_REG_BASE + DWC2_IN_ENDPOINT_BASE)) -#define EPOUT_REG(_port) ((dwc2_epout_t*) (DWC2_REG_BASE + DWC2_OUT_ENDPOINT_BASE)) -#define FIFO_BASE(_port, _x) ((volatile uint32_t*) (DWC2_REG_BASE + DWC2_FIFO_BASE + (_x) * DWC2_FIFO_SIZE)) +#define EPIN_REG(_port) ((dwc2_epin_t*) (DWC2_REG_BASE + DWC2_IN_ENDPOINT_BASE)) +#define EPOUT_REG(_port) ((dwc2_epout_t*) (DWC2_REG_BASE + DWC2_OUT_ENDPOINT_BASE)) +#define FIFO_BASE(_port, _x) ((volatile uint32_t*) (DWC2_REG_BASE + DWC2_FIFO_BASE + (_x) * DWC2_FIFO_SIZE)) enum { @@ -441,14 +440,12 @@ void dcd_init (uint8_t rhport) void dcd_int_enable (uint8_t rhport) { - (void) rhport; - NVIC_EnableIRQ(RHPORT_IRQn); + dcd_dwc2_int_enable(rhport); } void dcd_int_disable (uint8_t rhport) { - (void) rhport; - NVIC_DisableIRQ(RHPORT_IRQn); + dcd_dwc2_int_disable(rhport); } void dcd_set_address (uint8_t rhport, uint8_t dev_addr) diff --git a/src/portable/synopsys/dwc2/dwc2_gd32.h b/src/portable/synopsys/dwc2/dwc2_gd32.h index 3ace4d484..8fe390fd8 100644 --- a/src/portable/synopsys/dwc2/dwc2_gd32.h +++ b/src/portable/synopsys/dwc2/dwc2_gd32.h @@ -32,26 +32,38 @@ #define __NOP() __asm volatile ("nop") // These numbers are the same for the whole GD32VF103 family. -#define RHPORT_IRQn 86 +#define DWC2_REG_BASE 0x50000000UL #define EP_MAX 4 #define EP_FIFO_SIZE 1280 -#define DWC2_REG_BASE 0x50000000UL +#define RHPORT_IRQn 86 // The GD32VF103 is a RISC-V MCU, which implements the ECLIC Core-Local // Interrupt Controller by Nuclei. It is nearly API compatible to the // NVIC used by ARM MCUs. #define ECLIC_INTERRUPT_ENABLE_BASE 0xD2001001UL -#define NVIC_EnableIRQ __eclic_enable_interrupt -#define NVIC_DisableIRQ __eclic_disable_interrupt - +TU_ATTR_ALWAYS_INLINE static inline void __eclic_enable_interrupt (uint32_t irq) { *(volatile uint8_t*)(ECLIC_INTERRUPT_ENABLE_BASE + (irq * 4)) = 1; } +TU_ATTR_ALWAYS_INLINE static inline void __eclic_disable_interrupt (uint32_t irq){ *(volatile uint8_t*)(ECLIC_INTERRUPT_ENABLE_BASE + (irq * 4)) = 0; } +TU_ATTR_ALWAYS_INLINE +static inline void dcd_dwc2_int_enable(uint8_t rhport) +{ + (void) rhport; + __eclic_enable_interrupt(RHPORT_IRQn); +} + +TU_ATTR_ALWAYS_INLINE +static inline void dcd_dwc2_int_disable (uint8_t rhport) +{ + (void) rhport; + __eclic_disable_interrupt(RHPORT_IRQn); +} #endif /* DWC2_GD32_H_ */ diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h index 3a5e1a9ac..d99e5502a 100644 --- a/src/portable/synopsys/dwc2/dwc2_stm32.h +++ b/src/portable/synopsys/dwc2/dwc2_stm32.h @@ -84,4 +84,18 @@ #endif +TU_ATTR_ALWAYS_INLINE +static inline void dcd_dwc2_int_enable(uint8_t rhport) +{ + (void) rhport; + NVIC_EnableIRQ(RHPORT_IRQn); +} + +TU_ATTR_ALWAYS_INLINE +static inline void dcd_dwc2_int_disable (uint8_t rhport) +{ + (void) rhport; + NVIC_DisableIRQ(RHPORT_IRQn); +} + #endif /* DWC2_STM32_H_ */ -- cgit v1.3.1 From a0202df920889b57f79560760f6a38632e52c364 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 25 Oct 2021 13:49:59 +0700 Subject: add TU_ARGS_APPLY(), TU_CHECK_MCU() now could check list of mcus --- src/common/tusb_common.h | 31 ------------------------------- src/common/tusb_compiler.h | 40 ++++++++++++++++++++++++++++++++++++++++ src/tusb_option.h | 9 ++++++++- 3 files changed, 48 insertions(+), 32 deletions(-) diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h index fc92654b7..bf9641622 100644 --- a/src/common/tusb_common.h +++ b/src/common/tusb_common.h @@ -235,37 +235,6 @@ TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write16 (void* mem, ui #endif -/*------------------------------------------------------------------*/ -/* Count number of arguments of __VA_ARGS__ - * - reference https://groups.google.com/forum/#!topic/comp.std.c/d-6Mj5Lko_s - * - _GET_NTH_ARG() takes args >= N (64) but only expand to Nth one (64th) - * - _RSEQ_N() is reverse sequential to N to add padding to have - * Nth position is the same as the number of arguments - * - ##__VA_ARGS__ is used to deal with 0 paramerter (swallows comma) - *------------------------------------------------------------------*/ -#ifndef TU_ARGS_NUM - -#define TU_ARGS_NUM(...) _TU_NARG(_0, ##__VA_ARGS__,_RSEQ_N()) - -#define _TU_NARG(...) _GET_NTH_ARG(__VA_ARGS__) -#define _GET_NTH_ARG( \ - _1, _2, _3, _4, _5, _6, _7, _8, _9,_10, \ - _11,_12,_13,_14,_15,_16,_17,_18,_19,_20, \ - _21,_22,_23,_24,_25,_26,_27,_28,_29,_30, \ - _31,_32,_33,_34,_35,_36,_37,_38,_39,_40, \ - _41,_42,_43,_44,_45,_46,_47,_48,_49,_50, \ - _51,_52,_53,_54,_55,_56,_57,_58,_59,_60, \ - _61,_62,_63,N,...) N -#define _RSEQ_N() \ - 62,61,60, \ - 59,58,57,56,55,54,53,52,51,50, \ - 49,48,47,46,45,44,43,42,41,40, \ - 39,38,37,36,35,34,33,32,31,30, \ - 29,28,27,26,25,24,23,22,21,20, \ - 19,18,17,16,15,14,13,12,11,10, \ - 9,8,7,6,5,4,3,2,1,0 -#endif - // To be removed //------------- Binary constant -------------// #if defined(__GNUC__) && !defined(__CC_ARM) diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h index 3e85939b0..b0999b5d9 100644 --- a/src/common/tusb_compiler.h +++ b/src/common/tusb_compiler.h @@ -67,6 +67,46 @@ #define TU_LITTLE_ENDIAN (0x12u) #define TU_BIG_ENDIAN (0x21u) +/*------------------------------------------------------------------*/ +/* Count number of arguments of __VA_ARGS__ + * - reference https://groups.google.com/forum/#!topic/comp.std.c/d-6Mj5Lko_s + * - _GET_NTH_ARG() takes args >= N (64) but only expand to Nth one (64th) + * - _RSEQ_N() is reverse sequential to N to add padding to have + * Nth position is the same as the number of arguments + * - ##__VA_ARGS__ is used to deal with 0 paramerter (swallows comma) + *------------------------------------------------------------------*/ +#define TU_ARGS_NUM(...) _TU_NARG(_0, ##__VA_ARGS__,_RSEQ_N()) + +#define _TU_NARG(...) _GET_NTH_ARG(__VA_ARGS__) +#define _GET_NTH_ARG( \ + _1, _2, _3, _4, _5, _6, _7, _8, _9,_10, \ + _11,_12,_13,_14,_15,_16,_17,_18,_19,_20, \ + _21,_22,_23,_24,_25,_26,_27,_28,_29,_30, \ + _31,_32,_33,_34,_35,_36,_37,_38,_39,_40, \ + _41,_42,_43,_44,_45,_46,_47,_48,_49,_50, \ + _51,_52,_53,_54,_55,_56,_57,_58,_59,_60, \ + _61,_62,_63,N,...) N +#define _RSEQ_N() \ + 62,61,60, \ + 59,58,57,56,55,54,53,52,51,50, \ + 49,48,47,46,45,44,43,42,41,40, \ + 39,38,37,36,35,34,33,32,31,30, \ + 29,28,27,26,25,24,23,22,21,20, \ + 19,18,17,16,15,14,13,12,11,10, \ + 9,8,7,6,5,4,3,2,1,0 + +// Apply an macro X to each of the arguments with an separated of choice +#define TU_ARGS_APPLY(_X, _s, ...) TU_XSTRCAT(_TU_ARGS_APPLY_, TU_ARGS_NUM(__VA_ARGS__))(_X, _s, __VA_ARGS__) + +#define _TU_ARGS_APPLY_1(_X, _s, _a1) _X(_a1) +#define _TU_ARGS_APPLY_2(_X, _s, _a1, _a2) _X(_a1) _s _X(_a2) +#define _TU_ARGS_APPLY_3(_X, _s, _a1, _a2, _a3) _X(_a1) _s _TU_ARGS_APPLY_2(_X, _s, _a2, _a3) +#define _TU_ARGS_APPLY_4(_X, _s, _a1, _a2, _a3, _a4) _X(_a1) _s _TU_ARGS_APPLY_3(_X, _s, _a2, _a3, _a4) +#define _TU_ARGS_APPLY_5(_X, _s, _a1, _a2, _a3, _a4, _a5) _X(_a1) _s _TU_ARGS_APPLY_4(_X, _s, _a2, _a3, _a4, _a5) +#define _TU_ARGS_APPLY_6(_X, _s, _a1, _a2, _a3, _a4, _a5, _a6) _X(_a1) _s _TU_ARGS_APPLY_5(_X, _s, _a2, _a3, _a4, _a5, _a6) +#define _TU_ARGS_APPLY_7(_X, _s, _a1, _a2, _a3, _a4, _a5, _a6, _a7) _X(_a1) _s _TU_ARGS_APPLY_6(_X, _s, _a2, _a3, _a4, _a5, _a6, _a7) +#define _TU_ARGS_APPLY_8(_X, _s, _a1, _a2, _a3, _a4, _a5, _a6, _a7, _a8) _X(_a1) _s _TU_ARGS_APPLY_7(_X, _s, _a2, _a3, _a4, _a5, _a6, _a7, _a8) + //--------------------------------------------------------------------+ // Compiler porting with Attribute and Endian //--------------------------------------------------------------------+ diff --git a/src/tusb_option.h b/src/tusb_option.h index e49fc0119..89d83472b 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -27,6 +27,8 @@ #ifndef _TUSB_OPTION_H_ #define _TUSB_OPTION_H_ +#include "common/tusb_compiler.h" + #define TUSB_VERSION_MAJOR 0 #define TUSB_VERSION_MINOR 12 #define TUSB_VERSION_REVISION 0 @@ -36,7 +38,6 @@ // Supported MCUs // CFG_TUSB_MCU must be defined to one of following value //--------------------------------------------------------------------+ -#define TU_CHECK_MCU(_m) (CFG_TUSB_MCU == OPT_MCU_##_m) #define OPT_MCU_NONE 0 @@ -126,6 +127,12 @@ // GigaDevice #define OPT_MCU_GD32VF103 1600 ///< GigaDevice GD32VF103 + +// Helper to check if configured MCU is one of listed +// Apply _TU_CHECK_MCU with || as separator to list of input +#define _TU_CHECK_MCU(_m) (CFG_TUSB_MCU == OPT_MCU_##_m) +#define TU_CHECK_MCU(...) TU_ARGS_APPLY(_TU_CHECK_MCU, ||, __VA_ARGS__) + //--------------------------------------------------------------------+ // Supported OS //--------------------------------------------------------------------+ -- cgit v1.3.1 From 9f014b059a2411d23a1a24e9154c89d87739eaaf Mon Sep 17 00:00:00 2001 From: Tod Kurt Date: Mon, 25 Oct 2021 00:07:59 -0700 Subject: properly handle Program Change and Channel Aftertouch messages --- src/class/midi/midi_device.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/class/midi/midi_device.c b/src/class/midi/midi_device.c index edec57846..b08b362f9 100644 --- a/src/class/midi/midi_device.c +++ b/src/class/midi/midi_device.c @@ -279,6 +279,12 @@ uint32_t tud_midi_n_stream_write(uint8_t itf, uint8_t cable_num, uint8_t const* stream->buffer[0] = (cable_num << 4) | msg; stream->total = 4; } + else if ( msg == 0xC || msg == 0xD) + { + // Channel Voice Messages, two-byte variants (Program Change and Channel Pressure) + stream->buffer[0] = (cable_num << 4) | msg; + stream->total = 3; + } else if ( msg == 0xf ) { // System message -- cgit v1.3.1 From 4ccf60954d184c0530daf800090bd7103aacee86 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 25 Oct 2021 15:51:41 +0700 Subject: moving esp32s2 to dwc2, abstract dwc2_set_turnaround() --- .../device/cdc_msc_freertos/src/CMakeLists.txt | 2 +- hw/bsp/gd32vf103/family.mk | 3 +- src/device/dcd_attr.h | 16 ++-- src/portable/synopsys/dwc2/dcd_dwc2.c | 98 ++++++---------------- src/portable/synopsys/dwc2/dwc2_esp32.h | 82 ++++++++++++++++++ src/portable/synopsys/dwc2/dwc2_gd32.h | 37 ++++++-- src/portable/synopsys/dwc2/dwc2_stm32.h | 83 +++++++++++++++--- src/tusb_option.h | 2 +- 8 files changed, 222 insertions(+), 101 deletions(-) create mode 100644 src/portable/synopsys/dwc2/dwc2_esp32.h diff --git a/examples/device/cdc_msc_freertos/src/CMakeLists.txt b/examples/device/cdc_msc_freertos/src/CMakeLists.txt index 07fc4df89..93ae0686a 100644 --- a/examples/device/cdc_msc_freertos/src/CMakeLists.txt +++ b/examples/device/cdc_msc_freertos/src/CMakeLists.txt @@ -27,5 +27,5 @@ target_sources(${COMPONENT_TARGET} PUBLIC "${TOP}/src/class/net/ncm_device.c" "${TOP}/src/class/usbtmc/usbtmc_device.c" "${TOP}/src/class/vendor/vendor_device.c" - "${TOP}/src/portable/espressif/esp32sx/dcd_esp32sx.c" + "${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c" ) diff --git a/hw/bsp/gd32vf103/family.mk b/hw/bsp/gd32vf103/family.mk index 4de23ac17..49bacdf1b 100644 --- a/hw/bsp/gd32vf103/family.mk +++ b/hw/bsp/gd32vf103/family.mk @@ -28,8 +28,7 @@ CFLAGS += \ -mstrict-align \ -nostdlib -nostartfiles \ -DCFG_TUSB_MCU=OPT_MCU_GD32VF103 \ - -DDOWNLOAD_MODE=DOWNLOAD_MODE_FLASHXIP \ - -DGD32VF103 + -DDOWNLOAD_MODE=DOWNLOAD_MODE_FLASHXIP # mcu driver cause following warnings CFLAGS += -Wno-error=unused-parameter diff --git a/src/device/dcd_attr.h b/src/device/dcd_attr.h index 3690985c6..ddec481a8 100644 --- a/src/device/dcd_attr.h +++ b/src/device/dcd_attr.h @@ -36,13 +36,13 @@ // - PORT_HIGHSPEED: mask to indicate which port support highspeed mode, bit0 for port0 and so on. //------------- NXP -------------// -#if TU_CHECK_MCU(LPC11UXX) || TU_CHECK_MCU(LPC13XX) || TU_CHECK_MCU(LPC15XX) +#if TU_CHECK_MCU(LPC11UXX, LPC13XX, LPC15XX) #define DCD_ATTR_ENDPOINT_MAX 5 -#elif TU_CHECK_MCU(LPC175X_6X) || TU_CHECK_MCU(LPC177X_8X) || TU_CHECK_MCU(LPC40XX) +#elif TU_CHECK_MCU(LPC175X_6X, LPC177X_8X, LPC40XX) #define DCD_ATTR_ENDPOINT_MAX 16 -#elif TU_CHECK_MCU(LPC18XX) || TU_CHECK_MCU(LPC43XX) +#elif TU_CHECK_MCU(LPC18XX, LPC43XX) // TODO USB0 has 6, USB1 has 4 #define DCD_ATTR_ENDPOINT_MAX 6 @@ -60,7 +60,7 @@ #elif TU_CHECK_MCU(MIMXRT10XX) #define DCD_ATTR_ENDPOINT_MAX 8 -#elif TU_CHECK_MCU(MKL25ZXX) || TU_CHECK_MCU(K32L2BXX) +#elif TU_CHECK_MCU(MKL25ZXX, K32L2BXX) #define DCD_ATTR_ENDPOINT_MAX 16 #elif TU_CHECK_MCU(MM32F327X) @@ -72,8 +72,8 @@ #define DCD_ATTR_ENDPOINT_MAX 9 //------------- Microchip -------------// -#elif TU_CHECK_MCU(SAMD21) || TU_CHECK_MCU(SAMD51) || TU_CHECK_MCU(SAME5X) || \ - TU_CHECK_MCU(SAMD11) || TU_CHECK_MCU(SAML21) || TU_CHECK_MCU(SAML22) +#elif TU_CHECK_MCU(SAMD21, SAMD51, SAME5X) || \ + TU_CHECK_MCU(SAMD11, SAML21, SAML22) #define DCD_ATTR_ENDPOINT_MAX 8 #elif TU_CHECK_MCU(SAMG) @@ -119,7 +119,7 @@ #define DCD_ATTR_ENDPOINT_MAX 9 #define DCD_ATTR_DWC2_STM32 -#elif TU_CHECK_MCU(STM32L0) || TU_CHECK_MCU(STM32L1) +#elif TU_CHECK_MCU(STM32L0, STM32L1) #define DCD_ATTR_ENDPOINT_MAX 8 #elif TU_CHECK_MCU(STM32L4) @@ -157,7 +157,7 @@ #define DCD_ATTR_ENDPOINT_MAX 12 //------------- Espressif -------------// -#elif TU_CHECK_MCU(ESP32S2) || TU_CHECK_MCU(ESP32S3) +#elif TU_CHECK_MCU(ESP32S2, ESP32S3) #define DCD_ATTR_ENDPOINT_MAX 6 //------------- Dialog -------------// diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 367fc7b56..c3773fb8b 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -30,13 +30,16 @@ #include "tusb_option.h" #include "device/dcd_attr.h" -#if TUSB_OPT_DEVICE_ENABLED && (defined(DCD_ATTR_DWC2_STM32) || TU_CHECK_MCU(GD32VF103)) +#if TUSB_OPT_DEVICE_ENABLED && \ + ( defined(DCD_ATTR_DWC2_STM32) || TU_CHECK_MCU(ESP32S2, ESP32S3, GD32VF103) ) #include "device/dcd.h" #include "dwc2_type.h" #if defined(DCD_ATTR_DWC2_STM32) #include "dwc2_stm32.h" +#elif TU_CHECK_MCU(ESP32S2, ESP32S3) + #include "dwc2_esp32.h" #elif TU_CHECK_MCU(GD32VF103) #include "dwc2_gd32.h" #else @@ -72,7 +75,7 @@ typedef struct { typedef volatile uint32_t * usb_fifo_t; -xfer_ctl_t xfer_status[EP_MAX][2]; +xfer_ctl_t xfer_status[DWC2_EP_MAX][2]; #define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir] // EP0 transfers are limited to 1 packet - larger sizes has to be split @@ -85,7 +88,7 @@ static bool _out_ep_closed; // Flag to check if RX FIFO si // Calculate the RX FIFO size according to recommendations from reference manual static inline uint16_t calc_rx_ff_size(uint16_t ep_size) { - return 15 + 2*(ep_size/4) + 2*EP_MAX; + return 15 + 2*(ep_size/4) + 2*DWC2_EP_MAX; } static void update_grxfsiz(uint8_t rhport) @@ -96,7 +99,7 @@ static void update_grxfsiz(uint8_t rhport) // Determine largest EP size for RX FIFO uint16_t max_epsize = 0; - for (uint8_t epnum = 0; epnum < EP_MAX; epnum++) + for (uint8_t epnum = 0; epnum < DWC2_EP_MAX; epnum++) { max_epsize = tu_max16(max_epsize, xfer_status[epnum][TUSB_DIR_OUT].max_size); } @@ -122,7 +125,7 @@ static void bus_reset(uint8_t rhport) dev->DCFG &= ~DCFG_DAD_Msk; // 1. NAK for all OUT endpoints - for(uint8_t n = 0; n < EP_MAX; n++) { + for(uint8_t n = 0; n < DWC2_EP_MAX; n++) { out_ep[n].DOEPCTL |= DOEPCTL_SNAK; } @@ -171,11 +174,11 @@ static void bus_reset(uint8_t rhport) // - 2 for each used OUT endpoint // // Therefore GRXFSIZ = 13 + 1 + 1 + 2 x (Largest-EPsize/4) + 2 x EPOUTnum - // - FullSpeed (64 Bytes ): GRXFSIZ = 15 + 2 x 16 + 2 x EP_MAX = 47 + 2 x EP_MAX - // - Highspeed (512 bytes): GRXFSIZ = 15 + 2 x 128 + 2 x EP_MAX = 271 + 2 x EP_MAX + // - FullSpeed (64 Bytes ): GRXFSIZ = 15 + 2 x 16 + 2 x DWC2_EP_MAX = 47 + 2 x DWC2_EP_MAX + // - Highspeed (512 bytes): GRXFSIZ = 15 + 2 x 128 + 2 x DWC2_EP_MAX = 271 + 2 x DWC2_EP_MAX // // NOTE: Largest-EPsize & EPOUTnum is actual used endpoints in configuration. Since DCD has no knowledge - // of the overall picture yet. We will use the worst scenario: largest possible + EP_MAX + // of the overall picture yet. We will use the worst scenario: largest possible + DWC2_EP_MAX // // For Isochronous, largest EP size can be 1023/1024 for FS/HS respectively. In addition if multiple ISO // are enabled at least "2 x (Largest-EPsize/4) + 1" are recommended. Maybe provide a macro for application to @@ -186,7 +189,7 @@ static void bus_reset(uint8_t rhport) _allocated_fifo_words_tx = 16; // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word ) - core->DIEPTXF0_HNPTXFSIZ = (16 << TX0FD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx); + core->DIEPTXF0_HNPTXFSIZ = (16 << TX0FD_Pos) | (DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx); // Fixed control EP0 size to 64 bytes in_ep[0].DIEPCTL &= ~(0x03 << DIEPCTL_MPSIZ_Pos); @@ -197,47 +200,6 @@ static void bus_reset(uint8_t rhport) core->GINTMSK |= GINTMSK_OEPINT | GINTMSK_IEPINT; } -// Set turn-around timeout according to link speed -extern uint32_t SystemCoreClock; -static void set_turnaround(dwc2_core_t * core, tusb_speed_t speed) -{ - core->GUSBCFG &= ~GUSBCFG_TRDT; - - if ( speed == TUSB_SPEED_HIGH ) - { - // Use fixed 0x09 for Highspeed - core->GUSBCFG |= (0x09 << GUSBCFG_TRDT_Pos); - } - else - { - // Turnaround timeout depends on the MCU clock - uint32_t turnaround; - - if ( SystemCoreClock >= 32000000U ) - turnaround = 0x6U; - else if ( SystemCoreClock >= 27500000U ) - turnaround = 0x7U; - else if ( SystemCoreClock >= 24000000U ) - turnaround = 0x8U; - else if ( SystemCoreClock >= 21800000U ) - turnaround = 0x9U; - else if ( SystemCoreClock >= 20000000U ) - turnaround = 0xAU; - else if ( SystemCoreClock >= 18500000U ) - turnaround = 0xBU; - else if ( SystemCoreClock >= 17200000U ) - turnaround = 0xCU; - else if ( SystemCoreClock >= 16000000U ) - turnaround = 0xDU; - else if ( SystemCoreClock >= 15000000U ) - turnaround = 0xEU; - else - turnaround = 0xFU; - - // Fullspeed depends on MCU clocks, but we will use 0x06 for 32+ Mhz - core->GUSBCFG |= (turnaround << GUSBCFG_TRDT_Pos); - } -} static tusb_speed_t get_speed(uint8_t rhport) { @@ -368,6 +330,8 @@ void dcd_init (uint8_t rhport) // peripheral in each Reference Manual. dwc2_core_t * core = CORE_REG(rhport); + // check GSNPSID + // No HNP/SRP (no OTG support), program timeout later. if ( rhport == 1 ) { @@ -422,7 +386,7 @@ void dcd_init (uint8_t rhport) // If USB host misbehaves during status portion of control xfer // (non zero-length packet), send STALL back and discard. - dev->DCFG |= DCFG_NZLSOHSK; + dev->DCFG |= DCFG_NZLSOHSK; set_speed(rhport, TUD_OPT_HIGH_SPEED ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL); @@ -457,16 +421,6 @@ void dcd_set_address (uint8_t rhport, uint8_t dev_addr) dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0); } -static void remote_wakeup_delay(void) -{ - // try to delay for 1 ms - uint32_t count = SystemCoreClock / 1000; - while ( count-- ) - { - __NOP(); - } -} - void dcd_remote_wakeup(uint8_t rhport) { (void) rhport; @@ -482,7 +436,7 @@ void dcd_remote_wakeup(uint8_t rhport) core->GINTMSK |= GINTMSK_SOFM; // Per specs: remote wakeup signal bit must be clear within 1-15ms - remote_wakeup_delay(); + dwc2_remote_wakeup_delay(); dev->DCTL &= ~DCTL_RWUSIG; } @@ -518,7 +472,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress); uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress); - TU_ASSERT(epnum < EP_MAX); + TU_ASSERT(epnum < DWC2_EP_MAX); xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir); xfer->max_size = tu_edpt_packet_size(desc_edpt); @@ -534,7 +488,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) // If size_rx needs to be extended check if possible and if so enlarge it if (core->GRXFSIZ < sz) { - TU_ASSERT(sz + _allocated_fifo_words_tx <= EP_FIFO_SIZE/4); + TU_ASSERT(sz + _allocated_fifo_words_tx <= DWC2_EP_FIFO_SIZE/4); // Enlarge RX FIFO core->GRXFSIZ = sz; @@ -571,15 +525,15 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n". // Check if free space is available - TU_ASSERT(_allocated_fifo_words_tx + fifo_size + core->GRXFSIZ <= EP_FIFO_SIZE/4); + TU_ASSERT(_allocated_fifo_words_tx + fifo_size + core->GRXFSIZ <= DWC2_EP_FIFO_SIZE/4); _allocated_fifo_words_tx += fifo_size; - TU_LOG(2, " Allocated %u bytes at offset %u", fifo_size*4, EP_FIFO_SIZE-_allocated_fifo_words_tx*4); + TU_LOG(2, " Allocated %u bytes at offset %u", fifo_size*4, DWC2_EP_FIFO_SIZE-_allocated_fifo_words_tx*4); // DIEPTXF starts at FIFO #1. // Both TXFD and TXSA are in unit of 32-bit words. - core->DIEPTXF[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx); + core->DIEPTXF[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | (DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx); in_ep[epnum].DIEPCTL |= (1 << DIEPCTL_USBAEP_Pos) | (epnum << DIEPCTL_TXFNUM_Pos) | @@ -606,7 +560,7 @@ void dcd_edpt_close_all (uint8_t rhport) // Disable non-control interrupt dev->DAINTMSK = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos); - for(uint8_t n = 1; n < EP_MAX; n++) + for(uint8_t n = 1; n < DWC2_EP_MAX; n++) { // disable OUT endpoint out_ep[n].DOEPCTL = 0; @@ -756,7 +710,7 @@ void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr) uint16_t const fifo_size = (core->DIEPTXF[epnum - 1] & DIEPTXF_INEPTXFD_Msk) >> DIEPTXF_INEPTXFD_Pos; uint16_t const fifo_start = (core->DIEPTXF[epnum - 1] & DIEPTXF_INEPTXSA_Msk) >> DIEPTXF_INEPTXSA_Pos; // For now only the last opened endpoint can be closed without fuss. - TU_ASSERT(fifo_start == EP_FIFO_SIZE/4 - _allocated_fifo_words_tx,); + TU_ASSERT(fifo_start == DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx,); _allocated_fifo_words_tx -= fifo_size; } else @@ -920,7 +874,7 @@ static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep) { static void handle_epout_ints(uint8_t rhport, dwc2_device_t * dev, dwc2_epout_t * out_ep) { // DAINT for a given EP clears when DOEPINTx is cleared. // OEPINT will be cleared when DAINT's out bits are cleared. - for(uint8_t n = 0; n < EP_MAX; n++) { + for(uint8_t n = 0; n < DWC2_EP_MAX; n++) { xfer_ctl_t * xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT); if(dev->DAINT & (1 << (DAINT_OEPINT_Pos + n))) { @@ -949,7 +903,7 @@ static void handle_epout_ints(uint8_t rhport, dwc2_device_t * dev, dwc2_epout_t static void handle_epin_ints(uint8_t rhport, dwc2_device_t * dev, dwc2_epin_t * in_ep) { // DAINT for a given EP clears when DIEPINTx is cleared. // IEPINT will be cleared when DAINT's out bits are cleared. - for ( uint8_t n = 0; n < EP_MAX; n++ ) + for ( uint8_t n = 0; n < DWC2_EP_MAX; n++ ) { xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_IN); @@ -1040,7 +994,7 @@ void dcd_int_handler(uint8_t rhport) tusb_speed_t const speed = get_speed(rhport); - set_turnaround(core, speed); + dwc2_set_turnaround(core, speed); dcd_event_bus_reset(rhport, speed, true); } diff --git a/src/portable/synopsys/dwc2/dwc2_esp32.h b/src/portable/synopsys/dwc2/dwc2_esp32.h new file mode 100644 index 000000000..5e544673d --- /dev/null +++ b/src/portable/synopsys/dwc2/dwc2_esp32.h @@ -0,0 +1,82 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + + +#ifndef _DWC2_ESP32_H_ +#define _DWC2_ESP32_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "esp_intr_alloc.h" +#include "soc/periph_defs.h" +//#include "soc/usb_periph.h" + +#define DWC2_REG_BASE 0x60080000UL +#define DWC2_EP_MAX 5 // USB_OUT_EP_NUM +#define DWC2_EP_FIFO_SIZE 1024 + +// #define EP_FIFO_NUM 5 + +static intr_handle_t usb_ih; + +static void dcd_int_handler_wrap(void* arg) +{ + (void) arg; + dcd_int_handler(0); +} + +static inline void dcd_dwc2_int_enable (uint8_t rhport) +{ + (void) rhport; + esp_intr_alloc(ETS_USB_INTR_SOURCE, ESP_INTR_FLAG_LOWMED, dcd_int_handler_wrap, NULL, &usb_ih); +} + +static inline void dcd_dwc2_int_disable (uint8_t rhport) +{ + (void) rhport; + esp_intr_free(usb_ih); +} + +static inline void dwc2_remote_wakeup_delay(void) +{ + vTaskDelay(pdMS_TO_TICKS(1)); +} + +static inline void dwc2_set_turnaround(dwc2_core_t * core, tusb_speed_t speed) +{ + (void) core; + (void) speed; + + // keep the reset value +} + +#ifdef __cplusplus +} +#endif + +#endif /* _DWC2_ESP32_H_ */ diff --git a/src/portable/synopsys/dwc2/dwc2_gd32.h b/src/portable/synopsys/dwc2/dwc2_gd32.h index 8fe390fd8..1ad066720 100644 --- a/src/portable/synopsys/dwc2/dwc2_gd32.h +++ b/src/portable/synopsys/dwc2/dwc2_gd32.h @@ -28,14 +28,18 @@ #ifndef DWC2_GD32_H_ #define DWC2_GD32_H_ -// for remote wakeup delay -#define __NOP() __asm volatile ("nop") +#ifdef __cplusplus + extern "C" { +#endif + // These numbers are the same for the whole GD32VF103 family. -#define DWC2_REG_BASE 0x50000000UL -#define EP_MAX 4 -#define EP_FIFO_SIZE 1280 -#define RHPORT_IRQn 86 +#define DWC2_REG_BASE 0x50000000UL +#define DWC2_EP_MAX 4 +#define DWC2_EP_FIFO_SIZE 1280 +#define RHPORT_IRQn 86 + +extern uint32_t SystemCoreClock; // The GD32VF103 is a RISC-V MCU, which implements the ECLIC Core-Local // Interrupt Controller by Nuclei. It is nearly API compatible to the @@ -66,4 +70,25 @@ static inline void dcd_dwc2_int_disable (uint8_t rhport) __eclic_disable_interrupt(RHPORT_IRQn); } +TU_ATTR_ALWAYS_INLINE +static inline void dwc2_remote_wakeup_delay(void) +{ + // try to delay for 1 ms + uint32_t count = SystemCoreClock / 1000; + while ( count-- ) __asm volatile ("nop"); +} + +static inline void dwc2_set_turnaround(dwc2_core_t * core, tusb_speed_t speed) +{ + (void) core; + (void) speed; + + // keep the reset value +} + + +#ifdef __cplusplus +} +#endif + #endif /* DWC2_GD32_H_ */ diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h index d99e5502a..2a6d58e9a 100644 --- a/src/portable/synopsys/dwc2/dwc2_stm32.h +++ b/src/portable/synopsys/dwc2/dwc2_stm32.h @@ -24,8 +24,12 @@ * This file is part of the TinyUSB stack. */ -#ifndef _TUSB_DWC2_STM32_H_ -#define _TUSB_DWC2_STM32_H_ +#ifndef _DWC2_STM32_H_ +#define _DWC2_STM32_H_ + +#ifdef __cplusplus + extern "C" { +#endif // EP_MAX : Max number of bi-directional endpoints including EP0 // EP_FIFO_SIZE : Size of dedicated USB SRAM @@ -71,19 +75,21 @@ // On STM32 we associate Port0 to OTG_FS, and Port1 to OTG_HS #if TUD_OPT_RHPORT == 0 - #define EP_MAX EP_MAX_FS - #define EP_FIFO_SIZE EP_FIFO_SIZE_FS - #define DWC2_REG_BASE USB_OTG_FS_PERIPH_BASE - #define RHPORT_IRQn OTG_FS_IRQn + #define DWC2_REG_BASE USB_OTG_FS_PERIPH_BASE + #define DWC2_EP_MAX EP_MAX_FS + #define DWC2_EP_FIFO_SIZE EP_FIFO_SIZE_FS + #define RHPORT_IRQn OTG_FS_IRQn #else - #define EP_MAX EP_MAX_HS - #define EP_FIFO_SIZE EP_FIFO_SIZE_HS - #define DWC2_REG_BASE USB_OTG_HS_PERIPH_BASE - #define RHPORT_IRQn OTG_HS_IRQn + #define DWC2_REG_BASE USB_OTG_HS_PERIPH_BASE + #define DWC2_EP_MAX EP_MAX_HS + #define DWC2_EP_FIFO_SIZE EP_FIFO_SIZE_HS + #define RHPORT_IRQn OTG_HS_IRQn #endif +extern uint32_t SystemCoreClock; + TU_ATTR_ALWAYS_INLINE static inline void dcd_dwc2_int_enable(uint8_t rhport) { @@ -98,4 +104,59 @@ static inline void dcd_dwc2_int_disable (uint8_t rhport) NVIC_DisableIRQ(RHPORT_IRQn); } -#endif /* DWC2_STM32_H_ */ +TU_ATTR_ALWAYS_INLINE +static inline void dwc2_remote_wakeup_delay(void) +{ + // try to delay for 1 ms + uint32_t count = SystemCoreClock / 1000; + while ( count-- ) __NOP(); +} + +// Set turn-around timeout according to link speed +static inline void dwc2_set_turnaround(dwc2_core_t * core, tusb_speed_t speed) +{ + core->GUSBCFG &= ~GUSBCFG_TRDT; + + if ( speed == TUSB_SPEED_HIGH ) + { + // Use fixed 0x09 for Highspeed + core->GUSBCFG |= (0x09 << GUSBCFG_TRDT_Pos); + } + else + { + // Turnaround timeout depends on the MCU clock + uint32_t turnaround; + + if ( SystemCoreClock >= 32000000U ) + turnaround = 0x6U; + else if ( SystemCoreClock >= 27500000U ) + turnaround = 0x7U; + else if ( SystemCoreClock >= 24000000U ) + turnaround = 0x8U; + else if ( SystemCoreClock >= 21800000U ) + turnaround = 0x9U; + else if ( SystemCoreClock >= 20000000U ) + turnaround = 0xAU; + else if ( SystemCoreClock >= 18500000U ) + turnaround = 0xBU; + else if ( SystemCoreClock >= 17200000U ) + turnaround = 0xCU; + else if ( SystemCoreClock >= 16000000U ) + turnaround = 0xDU; + else if ( SystemCoreClock >= 15000000U ) + turnaround = 0xEU; + else + turnaround = 0xFU; + + // Fullspeed depends on MCU clocks, but we will use 0x06 for 32+ Mhz + core->GUSBCFG |= (turnaround << GUSBCFG_TRDT_Pos); + } +} + + + +#ifdef __cplusplus +} +#endif + +#endif /* _DWC2_STM32_H_ */ diff --git a/src/tusb_option.h b/src/tusb_option.h index 89d83472b..d707c44c7 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -131,7 +131,7 @@ // Helper to check if configured MCU is one of listed // Apply _TU_CHECK_MCU with || as separator to list of input #define _TU_CHECK_MCU(_m) (CFG_TUSB_MCU == OPT_MCU_##_m) -#define TU_CHECK_MCU(...) TU_ARGS_APPLY(_TU_CHECK_MCU, ||, __VA_ARGS__) +#define TU_CHECK_MCU(...) (TU_ARGS_APPLY(_TU_CHECK_MCU, ||, __VA_ARGS__)) //--------------------------------------------------------------------+ // Supported OS -- cgit v1.3.1 From 85e18b9172b266f26ace35c825a9da0f3a32db0b Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 25 Oct 2021 15:58:12 +0700 Subject: house keeping --- src/portable/synopsys/dwc2/dcd_dwc2.c | 112 +++++++++++++++++++++------------- 1 file changed, 70 insertions(+), 42 deletions(-) diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index c3773fb8b..fca5321f7 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -73,8 +73,6 @@ typedef struct { uint8_t interval; } xfer_ctl_t; -typedef volatile uint32_t * usb_fifo_t; - xfer_ctl_t xfer_status[DWC2_EP_MAX][2]; #define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir] @@ -586,7 +584,8 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t xfer->total_len = total_bytes; // EP0 can only handle one packet - if(epnum == 0) { + if(epnum == 0) + { ep0_pending[dir] = total_bytes; // Schedule the first transaction for EP0 transfer edpt_schedule_packets(rhport, epnum, dir, 1, ep0_pending[dir]); @@ -597,9 +596,7 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t uint16_t const short_packet_size = total_bytes % xfer->max_size; // Zero-size packet is special case. - if(short_packet_size > 0 || (total_bytes == 0)) { - num_packets++; - } + if ( short_packet_size > 0 || (total_bytes == 0) ) num_packets++; // Schedule packets to be sent within interrupt edpt_schedule_packets(rhport, epnum, dir, num_packets, total_bytes); @@ -628,7 +625,7 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16 uint16_t const short_packet_size = total_bytes % xfer->max_size; // Zero-size packet is special case. - if(short_packet_size > 0 || (total_bytes == 0)) num_packets++; + if ( short_packet_size > 0 || (total_bytes == 0) ) num_packets++; // Schedule packets to be sent within interrupt edpt_schedule_packets(rhport, epnum, dir, num_packets, total_bytes); @@ -648,40 +645,51 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall) uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); - if(dir == TUSB_DIR_IN) { + if ( dir == TUSB_DIR_IN ) + { // Only disable currently enabled non-control endpoint - if ( (epnum == 0) || !(in_ep[epnum].DIEPCTL & DIEPCTL_EPENA) ){ + if ( (epnum == 0) || !(in_ep[epnum].DIEPCTL & DIEPCTL_EPENA) ) + { in_ep[epnum].DIEPCTL |= DIEPCTL_SNAK | (stall ? DIEPCTL_STALL : 0); - } else { + } + else + { // Stop transmitting packets and NAK IN xfers. in_ep[epnum].DIEPCTL |= DIEPCTL_SNAK; - while((in_ep[epnum].DIEPINT & DIEPINT_INEPNE) == 0); + while ( (in_ep[epnum].DIEPINT & DIEPINT_INEPNE) == 0 ) {} // Disable the endpoint. in_ep[epnum].DIEPCTL |= DIEPCTL_EPDIS | (stall ? DIEPCTL_STALL : 0); - while((in_ep[epnum].DIEPINT & DIEPINT_EPDISD_Msk) == 0); + while ( (in_ep[epnum].DIEPINT & DIEPINT_EPDISD_Msk) == 0 ) {} + in_ep[epnum].DIEPINT = DIEPINT_EPDISD; } // Flush the FIFO, and wait until we have confirmed it cleared. core->GRSTCTL |= (epnum << GRSTCTL_TXFNUM_Pos); core->GRSTCTL |= GRSTCTL_TXFFLSH; - while((core->GRSTCTL & GRSTCTL_TXFFLSH_Msk) != 0); - } else { + while ( (core->GRSTCTL & GRSTCTL_TXFFLSH_Msk) != 0 ) {} + } + else + { // Only disable currently enabled non-control endpoint - if ( (epnum == 0) || !(out_ep[epnum].DOEPCTL & DOEPCTL_EPENA) ){ + if ( (epnum == 0) || !(out_ep[epnum].DOEPCTL & DOEPCTL_EPENA) ) + { out_ep[epnum].DOEPCTL |= stall ? DOEPCTL_STALL : 0; - } else { + } + else + { // Asserting GONAK is required to STALL an OUT endpoint. // Simpler to use polling here, we don't use the "B"OUTNAKEFF interrupt // anyway, and it can't be cleared by user code. If this while loop never // finishes, we have bigger problems than just the stack. dev->DCTL |= DCTL_SGONAK; - while((core->GINTSTS & GINTSTS_BOUTNAKEFF_Msk) == 0); + while ( (core->GINTSTS & GINTSTS_BOUTNAKEFF_Msk) == 0 ) {} // Ditto here- disable the endpoint. out_ep[epnum].DOEPCTL |= DOEPCTL_EPDIS | (stall ? DOEPCTL_STALL : 0); - while((out_ep[epnum].DOEPINT & DOEPINT_EPDISD_Msk) == 0); + while ( (out_ep[epnum].DOEPINT & DOEPINT_EPDISD_Msk) == 0 ) {} + out_ep[epnum].DOEPINT = DOEPINT_EPDISD; // Allow other OUT endpoints to keep receiving. @@ -735,10 +743,13 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) uint8_t const dir = tu_edpt_dir(ep_addr); // Clear stall and reset data toggle - if(dir == TUSB_DIR_IN) { + if ( dir == TUSB_DIR_IN ) + { in_ep[epnum].DIEPCTL &= ~DIEPCTL_STALL; in_ep[epnum].DIEPCTL |= DIEPCTL_SD0PID_SEVNFRM; - } else { + } + else + { out_ep[epnum].DOEPCTL &= ~DOEPCTL_STALL; out_ep[epnum].DOEPCTL |= DOEPCTL_SD0PID_SEVNFRM; } @@ -751,11 +762,12 @@ static void read_fifo_packet(uint8_t rhport, uint8_t * dst, uint16_t len) { (void) rhport; - usb_fifo_t rx_fifo = FIFO_BASE(rhport, 0); + volatile uint32_t * rx_fifo = FIFO_BASE(rhport, 0); // Reading full available 32 bit words from fifo uint16_t full_words = len >> 2; - for(uint16_t i = 0; i < full_words; i++) { + for ( uint16_t i = 0; i < full_words; i++ ) + { uint32_t tmp = *rx_fifo; dst[0] = tmp & 0x000000FF; dst[1] = (tmp & 0x0000FF00) >> 8; @@ -766,13 +778,16 @@ static void read_fifo_packet(uint8_t rhport, uint8_t * dst, uint16_t len) // Read the remaining 1-3 bytes from fifo uint8_t bytes_rem = len & 0x03; - if(bytes_rem != 0) { + if ( bytes_rem != 0 ) + { uint32_t tmp = *rx_fifo; dst[0] = tmp & 0x000000FF; - if(bytes_rem > 1) { + if ( bytes_rem > 1 ) + { dst[1] = (tmp & 0x0000FF00) >> 8; } - if(bytes_rem > 2) { + if ( bytes_rem > 2 ) + { dst[2] = (tmp & 0x00FF0000) >> 16; } } @@ -783,24 +798,28 @@ static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t * src, u { (void) rhport; - usb_fifo_t tx_fifo = FIFO_BASE(rhport, fifo_num); + volatile uint32_t * tx_fifo = FIFO_BASE(rhport, fifo_num); // Pushing full available 32 bit words to fifo uint16_t full_words = len >> 2; - for(uint16_t i = 0; i < full_words; i++){ + for ( uint16_t i = 0; i < full_words; i++ ) + { *tx_fifo = (src[3] << 24) | (src[2] << 16) | (src[1] << 8) | src[0]; src += 4; } // Write the remaining 1-3 bytes into fifo uint8_t bytes_rem = len & 0x03; - if(bytes_rem){ + if ( bytes_rem ) + { uint32_t tmp_word = 0; tmp_word |= src[0]; - if(bytes_rem > 1){ + if ( bytes_rem > 1 ) + { tmp_word |= src[1] << 8; } - if(bytes_rem > 2){ + if ( bytes_rem > 2 ) + { tmp_word |= src[2] << 16; } *tx_fifo = tmp_word; @@ -809,7 +828,7 @@ static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t * src, u static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep) { dwc2_core_t * core = CORE_REG(rhport); - usb_fifo_t rx_fifo = FIFO_BASE(rhport, 0); + volatile uint32_t * rx_fifo = FIFO_BASE(rhport, 0); // Pop control word off FIFO uint32_t ctl_word = core->GRXSTSP; @@ -817,7 +836,8 @@ static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep) { uint8_t epnum = (ctl_word & GRXSTSP_EPNUM_Msk) >> GRXSTSP_EPNUM_Pos; uint16_t bcnt = (ctl_word & GRXSTSP_BCNT_Msk) >> GRXSTSP_BCNT_Pos; - switch(pktsts) { + switch(pktsts) + { case 0x01: // Global OUT NAK (Interrupt) break; @@ -871,28 +891,36 @@ static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep) { } } -static void handle_epout_ints(uint8_t rhport, dwc2_device_t * dev, dwc2_epout_t * out_ep) { +static void handle_epout_ints (uint8_t rhport, dwc2_device_t *dev, dwc2_epout_t *out_ep) +{ // DAINT for a given EP clears when DOEPINTx is cleared. // OEPINT will be cleared when DAINT's out bits are cleared. - for(uint8_t n = 0; n < DWC2_EP_MAX; n++) { - xfer_ctl_t * xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT); + for ( uint8_t n = 0; n < DWC2_EP_MAX; n++ ) + { + xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT); - if(dev->DAINT & (1 << (DAINT_OEPINT_Pos + n))) { + if ( dev->DAINT & (1 << (DAINT_OEPINT_Pos + n)) ) + { // SETUP packet Setup Phase done. - if(out_ep[n].DOEPINT & DOEPINT_STUP) { - out_ep[n].DOEPINT = DOEPINT_STUP; + if ( out_ep[n].DOEPINT & DOEPINT_STUP ) + { + out_ep[n].DOEPINT = DOEPINT_STUP; dcd_event_setup_received(rhport, (uint8_t*) &_setup_packet[0], true); } // OUT XFER complete - if(out_ep[n].DOEPINT & DOEPINT_XFRC) { + if ( out_ep[n].DOEPINT & DOEPINT_XFRC ) + { out_ep[n].DOEPINT = DOEPINT_XFRC; // EP0 can only handle one packet - if((n == 0) && ep0_pending[TUSB_DIR_OUT]) { + if ( (n == 0) && ep0_pending[TUSB_DIR_OUT] ) + { // Schedule another packet to be received. edpt_schedule_packets(rhport, n, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]); - } else { + } + else + { dcd_event_xfer_complete(rhport, n, xfer->total_len, XFER_RESULT_SUCCESS, true); } } @@ -948,7 +976,7 @@ static void handle_epin_ints(uint8_t rhport, dwc2_device_t * dev, dwc2_epin_t * // Push packet to Tx-FIFO if (xfer->ff) { - usb_fifo_t tx_fifo = FIFO_BASE(rhport, n); + volatile uint32_t * tx_fifo = FIFO_BASE(rhport, n); tu_fifo_read_n_const_addr_full_words(xfer->ff, (void *)(uintptr_t) tx_fifo, packet_size); } else -- cgit v1.3.1 From dbd31895bc234ff6d76d3fe736dc613890ab7acb Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 25 Oct 2021 17:04:03 +0700 Subject: change usage of TU_CHECK_MCU() to prevent macro conflict --- .../audio_4_channel_mic/src/usb_descriptors.c | 12 ++-- examples/device/audio_test/src/usb_descriptors.c | 2 +- examples/device/cdc_msc_freertos/src/main.c | 6 +- examples/device/cdc_msc_freertos/src/tusb_config.h | 2 +- examples/device/hid_composite_freertos/src/main.c | 6 +- .../hid_composite_freertos/src/tusb_config.h | 2 +- .../device/video_capture/src/usb_descriptors.c | 4 +- src/class/msc/msc_device.c | 2 +- src/common/tusb_compiler.h | 2 +- src/device/dcd_attr.h | 73 +++++++++++----------- src/host/hcd_attr.h | 46 +++++++------- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 11 ++-- src/portable/synopsys/dwc2/dcd_dwc2.c | 6 +- src/tusb_option.h | 2 +- 14 files changed, 85 insertions(+), 91 deletions(-) diff --git a/examples/device/audio_4_channel_mic/src/usb_descriptors.c b/examples/device/audio_4_channel_mic/src/usb_descriptors.c index b6a5bd5c2..93ae2ea47 100644 --- a/examples/device/audio_4_channel_mic/src/usb_descriptors.c +++ b/examples/device/audio_4_channel_mic/src/usb_descriptors.c @@ -81,12 +81,12 @@ enum #define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + CFG_TUD_AUDIO * TUD_AUDIO_MIC_FOUR_CH_DESC_LEN) -#if TU_CHECK_MCU(LPC175X_6X) || TU_CHECK_MCU(LPC177X_8X) || TU_CHECK_MCU(LPC40XX) +#if TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC40XX) // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ... #define EPNUM_AUDIO 0x03 -#elif TU_CHECK_MCU(NRF5X) +#elif TU_CHECK_MCU(OPT_MCU_NRF5X) // nRF5x ISO can only be endpoint 8 #define EPNUM_AUDIO 0x08 @@ -96,11 +96,11 @@ enum uint8_t const desc_configuration[] = { - // Interface count, string index, total length, attribute, power in mA - TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100), + // Interface count, string index, total length, attribute, power in mA + TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100), - // Interface number, string index, EP Out & EP In address, EP size - TUD_AUDIO_MIC_FOUR_CH_DESCRIPTOR(/*_itfnum*/ ITF_NUM_AUDIO_CONTROL, /*_stridx*/ 0, /*_nBytesPerSample*/ CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX, /*_nBitsUsedPerSample*/ CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX*8, /*_epin*/ 0x80 | EPNUM_AUDIO, /*_epsize*/ CFG_TUD_AUDIO_EP_SZ_IN) + // Interface number, string index, EP Out & EP In address, EP size + TUD_AUDIO_MIC_FOUR_CH_DESCRIPTOR(/*_itfnum*/ ITF_NUM_AUDIO_CONTROL, /*_stridx*/ 0, /*_nBytesPerSample*/ CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX, /*_nBitsUsedPerSample*/ CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX*8, /*_epin*/ 0x80 | EPNUM_AUDIO, /*_epsize*/ CFG_TUD_AUDIO_EP_SZ_IN) }; // Invoked when received GET CONFIGURATION DESCRIPTOR diff --git a/examples/device/audio_test/src/usb_descriptors.c b/examples/device/audio_test/src/usb_descriptors.c index 348f5eede..09b2a2d45 100644 --- a/examples/device/audio_test/src/usb_descriptors.c +++ b/examples/device/audio_test/src/usb_descriptors.c @@ -86,7 +86,7 @@ enum // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ... #define EPNUM_AUDIO 0x03 -#elif TU_CHECK_MCU(NRF5X) +#elif TU_CHECK_MCU(OPT_MCU_NRF5X) // nRF5x ISO can only be endpoint 8 #define EPNUM_AUDIO 0x08 diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c index 65b7fda3b..2d3426f1d 100644 --- a/examples/device/cdc_msc_freertos/src/main.c +++ b/examples/device/cdc_msc_freertos/src/main.c @@ -30,7 +30,7 @@ #include "bsp/board.h" #include "tusb.h" -#if TU_CHECK_MCU(ESP32S2) || TU_CHECK_MCU(ESP32S3) +#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) // ESP-IDF need "freertos/" prefix in include path. // CFG_TUSB_OS_INC_PATH should be defined accordingly. #include "freertos/FreeRTOS.h" @@ -105,14 +105,14 @@ int main(void) (void) xTaskCreateStatic( cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, cdc_stack, &cdc_taskdef); // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3 -#if !( TU_CHECK_MCU(ESP32S2) || TU_CHECK_MCU(ESP32S3) ) +#if !TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) vTaskStartScheduler(); #endif return 0; } -#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3 +#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) void app_main(void) { main(); diff --git a/examples/device/cdc_msc_freertos/src/tusb_config.h b/examples/device/cdc_msc_freertos/src/tusb_config.h index d4bbdee48..55e84c62d 100644 --- a/examples/device/cdc_msc_freertos/src/tusb_config.h +++ b/examples/device/cdc_msc_freertos/src/tusb_config.h @@ -68,7 +68,7 @@ #define CFG_TUSB_OS OPT_OS_FREERTOS // Espressif IDF requires "freertos/" prefix in include path -#if TU_CHECK_MCU(ESP32S2) || TU_CHECK_MCU(ESP32S3) +#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) #define CFG_TUSB_OS_INC_PATH freertos/ #endif diff --git a/examples/device/hid_composite_freertos/src/main.c b/examples/device/hid_composite_freertos/src/main.c index b25c71f64..336f5d426 100644 --- a/examples/device/hid_composite_freertos/src/main.c +++ b/examples/device/hid_composite_freertos/src/main.c @@ -31,7 +31,7 @@ #include "tusb.h" #include "usb_descriptors.h" -#if TU_CHECK_MCU(ESP32S2) || TU_CHECK_MCU(ESP32S3) +#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) // ESP-IDF need "freertos/" prefix in include path. // CFG_TUSB_OS_INC_PATH should be defined accordingly. #include "freertos/FreeRTOS.h" @@ -105,14 +105,14 @@ int main(void) (void) xTaskCreateStatic( hid_task, "hid", HID_STACK_SZIE, NULL, configMAX_PRIORITIES-2, hid_stack, &hid_taskdef); // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3 -#if !( TU_CHECK_MCU(ESP32S2) || TU_CHECK_MCU(ESP32S3) ) +#if !TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) vTaskStartScheduler(); #endif return 0; } -#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3 +#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) void app_main(void) { main(); diff --git a/examples/device/hid_composite_freertos/src/tusb_config.h b/examples/device/hid_composite_freertos/src/tusb_config.h index b061dce3f..062f32ac3 100644 --- a/examples/device/hid_composite_freertos/src/tusb_config.h +++ b/examples/device/hid_composite_freertos/src/tusb_config.h @@ -68,7 +68,7 @@ #define CFG_TUSB_OS OPT_OS_FREERTOS // Espressif IDF requires "freertos/" prefix in include path -#if TU_CHECK_MCU(ESP32S2) || TU_CHECK_MCU(ESP32S3) +#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) #define CFG_TUSB_OS_INC_PATH freertos/ #endif diff --git a/examples/device/video_capture/src/usb_descriptors.c b/examples/device/video_capture/src/usb_descriptors.c index 404ffe070..da8ec8e89 100644 --- a/examples/device/video_capture/src/usb_descriptors.c +++ b/examples/device/video_capture/src/usb_descriptors.c @@ -77,12 +77,12 @@ uint8_t const * tud_descriptor_device_cb(void) #define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + TUD_VIDEO_CAPTURE_DESC_LEN) -#if TU_CHECK_MCU(LPC175X_6X) || TU_CHECK_MCU(LPC177X_8X) || TU_CHECK_MCU(LPC40XX) +#if TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC40XX) // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In, 5 Bulk etc ... #define EPNUM_VIDEO_IN 0x83 -#elif TU_CHECK_MCU(NRF5X) +#elif TU_CHECK_MCU(OPT_MCU_NRF5X) // nRF5x ISO can only be endpoint 8 #define EPNUM_VIDEO_IN 0x88 diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c index 81522be46..dd490dd68 100644 --- a/src/class/msc/msc_device.c +++ b/src/class/msc/msc_device.c @@ -617,7 +617,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t } } - #if TU_CHECK_MCU(CXD56) + #if TU_CHECK_MCU(OPT_MCU_CXD56) // WORKAROUND: cxd56 has its own nuttx usb stack which does not forward Set/ClearFeature(Endpoint) to DCD. // There is no way for us to know when EP is un-stall, therefore we will unconditionally un-stall here and // hope everything will work diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h index b0999b5d9..d3284c62a 100644 --- a/src/common/tusb_compiler.h +++ b/src/common/tusb_compiler.h @@ -69,7 +69,7 @@ /*------------------------------------------------------------------*/ /* Count number of arguments of __VA_ARGS__ - * - reference https://groups.google.com/forum/#!topic/comp.std.c/d-6Mj5Lko_s + * - reference https://stackoverflow.com/questions/2124339/c-preprocessor-va-args-number-of-arguments * - _GET_NTH_ARG() takes args >= N (64) but only expand to Nth one (64th) * - _RSEQ_N() is reverse sequential to N to add padding to have * Nth position is the same as the number of arguments diff --git a/src/device/dcd_attr.h b/src/device/dcd_attr.h index ddec481a8..54627eaa0 100644 --- a/src/device/dcd_attr.h +++ b/src/device/dcd_attr.h @@ -36,59 +36,59 @@ // - PORT_HIGHSPEED: mask to indicate which port support highspeed mode, bit0 for port0 and so on. //------------- NXP -------------// -#if TU_CHECK_MCU(LPC11UXX, LPC13XX, LPC15XX) +#if TU_CHECK_MCU(OPT_MCU_LPC11UXX, OPT_MCU_LPC13XX, OPT_MCU_LPC15XX) #define DCD_ATTR_ENDPOINT_MAX 5 -#elif TU_CHECK_MCU(LPC175X_6X, LPC177X_8X, LPC40XX) +#elif TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC40XX) #define DCD_ATTR_ENDPOINT_MAX 16 -#elif TU_CHECK_MCU(LPC18XX, LPC43XX) +#elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX) // TODO USB0 has 6, USB1 has 4 #define DCD_ATTR_ENDPOINT_MAX 6 -#elif TU_CHECK_MCU(LPC51UXX) +#elif TU_CHECK_MCU(OPT_MCU_LPC51UXX) #define DCD_ATTR_ENDPOINT_MAX 5 -#elif TU_CHECK_MCU(LPC54XXX) +#elif TU_CHECK_MCU(OPT_MCU_LPC54XXX) // TODO USB0 has 5, USB1 has 6 #define DCD_ATTR_ENDPOINT_MAX 6 -#elif TU_CHECK_MCU(LPC55XX) +#elif TU_CHECK_MCU(OPT_MCU_LPC55XX) // TODO USB0 has 5, USB1 has 6 #define DCD_ATTR_ENDPOINT_MAX 6 -#elif TU_CHECK_MCU(MIMXRT10XX) +#elif TU_CHECK_MCU(OPT_MCU_MIMXRT10XX) #define DCD_ATTR_ENDPOINT_MAX 8 -#elif TU_CHECK_MCU(MKL25ZXX, K32L2BXX) +#elif TU_CHECK_MCU(OPT_MCU_MKL25ZXX, OPT_MCU_K32L2BXX) #define DCD_ATTR_ENDPOINT_MAX 16 -#elif TU_CHECK_MCU(MM32F327X) +#elif TU_CHECK_MCU(OPT_MCU_MM32F327X) #define DCD_ATTR_ENDPOINT_MAX 16 //------------- Nordic -------------// -#elif TU_CHECK_MCU(NRF5X) +#elif TU_CHECK_MCU(OPT_MCU_NRF5X) // 8 CBI + 1 ISO #define DCD_ATTR_ENDPOINT_MAX 9 //------------- Microchip -------------// -#elif TU_CHECK_MCU(SAMD21, SAMD51, SAME5X) || \ - TU_CHECK_MCU(SAMD11, SAML21, SAML22) +#elif TU_CHECK_MCU(OPT_MCU_SAMD21, OPT_MCU_SAMD51, OPT_MCU_SAME5X) || \ + TU_CHECK_MCU(OPT_MCU_SAMD11, OPT_MCU_SAML21, OPT_MCU_SAML22) #define DCD_ATTR_ENDPOINT_MAX 8 -#elif TU_CHECK_MCU(SAMG) +#elif TU_CHECK_MCU(OPT_MCU_SAMG) #define DCD_ATTR_ENDPOINT_MAX 6 #define DCD_ATTR_ENDPOINT_EXCLUSIVE_NUMBER -#elif TU_CHECK_MCU(SAMX7X) +#elif TU_CHECK_MCU(OPT_MCU_SAMX7X) #define DCD_ATTR_ENDPOINT_MAX 10 #define DCD_ATTR_ENDPOINT_EXCLUSIVE_NUMBER //------------- ST -------------// -#elif TU_CHECK_MCU(STM32F0) +#elif TU_CHECK_MCU(OPT_MCU_STM32F0) #define DCD_ATTR_ENDPOINT_MAX 8 -#elif TU_CHECK_MCU(STM32F1) +#elif TU_CHECK_MCU(OPT_MCU_STM32F1) #if defined (STM32F105x8) || defined (STM32F105xB) || defined (STM32F105xC) || \ defined (STM32F107xB) || defined (STM32F107xC) #define DCD_ATTR_ENDPOINT_MAX 4 @@ -97,32 +97,32 @@ #define DCD_ATTR_ENDPOINT_MAX 8 #endif -#elif TU_CHECK_MCU(STM32F2) +#elif TU_CHECK_MCU(OPT_MCU_STM32F2) // FS has 4 ep, HS has 5 ep #define DCD_ATTR_ENDPOINT_MAX 6 #define DCD_ATTR_DWC2_STM32 -#elif TU_CHECK_MCU(STM32F3) +#elif TU_CHECK_MCU(OPT_MCU_STM32F3) #define DCD_ATTR_ENDPOINT_MAX 8 -#elif TU_CHECK_MCU(STM32F4) +#elif TU_CHECK_MCU(OPT_MCU_STM32F4) // For most mcu, FS has 4, HS has 6. TODO 446/469/479 HS has 9 #define DCD_ATTR_ENDPOINT_MAX 6 #define DCD_ATTR_DWC2_STM32 -#elif TU_CHECK_MCU(STM32F7) +#elif TU_CHECK_MCU(OPT_MCU_STM32F7) // FS has 6, HS has 9 #define DCD_ATTR_ENDPOINT_MAX 9 #define DCD_ATTR_DWC2_STM32 -#elif TU_CHECK_MCU(STM32H7) +#elif TU_CHECK_MCU(OPT_MCU_STM32H7) #define DCD_ATTR_ENDPOINT_MAX 9 #define DCD_ATTR_DWC2_STM32 -#elif TU_CHECK_MCU(STM32L0, STM32L1) +#elif TU_CHECK_MCU(OPT_MCU_STM32L0, OPT_MCU_STM32L1) #define DCD_ATTR_ENDPOINT_MAX 8 -#elif TU_CHECK_MCU(STM32L4) +#elif TU_CHECK_MCU(OPT_MCU_STM32L4) #if defined (STM32L475xx) || defined (STM32L476xx) || \ defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || \ defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || \ @@ -134,53 +134,50 @@ #endif //------------- Sony -------------// -#elif TU_CHECK_MCU(CXD56) +#elif TU_CHECK_MCU(OPT_MCU_CXD56) #define DCD_ATTR_ENDPOINT_MAX 7 #define DCD_ATTR_ENDPOINT_EXCLUSIVE_NUMBER //------------- TI -------------// -#elif TU_CHECK_MCU(MSP430x5xx) +#elif TU_CHECK_MCU(OPT_MCU_MSP430x5xx) #define DCD_ATTR_ENDPOINT_MAX 8 //------------- ValentyUSB -------------// -#elif TU_CHECK_MCU(VALENTYUSB_EPTRI) +#elif TU_CHECK_MCU(OPT_MCU_VALENTYUSB_EPTRI) #define DCD_ATTR_ENDPOINT_MAX 16 //------------- Nuvoton -------------// -#elif TU_CHECK_MCU(NUC121) || TU_CHECK_MCU(NUC126) +#elif TU_CHECK_MCU(OPT_MCU_NUC121, OPT_MCU_NUC126) #define DCD_ATTR_ENDPOINT_MAX 8 -#elif TU_CHECK_MCU(NUC120) +#elif TU_CHECK_MCU(OPT_MCU_NUC120) #define DCD_ATTR_ENDPOINT_MAX 6 -#elif TU_CHECK_MCU(NUC505) +#elif TU_CHECK_MCU(OPT_MCU_NUC505) #define DCD_ATTR_ENDPOINT_MAX 12 //------------- Espressif -------------// -#elif TU_CHECK_MCU(ESP32S2, ESP32S3) +#elif TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) #define DCD_ATTR_ENDPOINT_MAX 6 //------------- Dialog -------------// -#elif TU_CHECK_MCU(DA1469X) +#elif TU_CHECK_MCU(OPT_MCU_DA1469X) #define DCD_ATTR_ENDPOINT_MAX 4 //------------- Raspberry Pi -------------// -#elif TU_CHECK_MCU(RP2040) +#elif TU_CHECK_MCU(OPT_MCU_RP2040) #define DCD_ATTR_ENDPOINT_MAX 16 //------------- Silabs -------------// -#elif TU_CHECK_MCU(EFM32GG) || TU_CHECK_MCU(EFM32GG11) || TU_CHECK_MCU(EFM32GG12) +#elif TU_CHECK_MCU(OPT_MCU_EFM32GG, OPT_MCU_EFM32GG11, OPT_MCU_EFM32GG12) #define DCD_ATTR_ENDPOINT_MAX 7 //------------- Renesas -------------// -#elif TU_CHECK_MCU(RX63X) || TU_CHECK_MCU(RX65X) || TU_CHECK_MCU(RX72N) +#elif TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) #define DCD_ATTR_ENDPOINT_MAX 10 -//#elif TU_CHECK_MCU(MM32F327X) -// #define DCD_ATTR_ENDPOINT_MAX not known yet - //------------- GigaDevice -------------// -#elif TU_CHECK_MCU(GD32VF103) +#elif TU_CHECK_MCU(OPT_MCU_GD32VF103) #define DCD_ATTR_ENDPOINT_MAX 4 #else diff --git a/src/host/hcd_attr.h b/src/host/hcd_attr.h index 729fc407b..a9bc242d7 100644 --- a/src/host/hcd_attr.h +++ b/src/host/hcd_attr.h @@ -34,64 +34,64 @@ // - PORT_HIGHSPEED: mask to indicate which port support highspeed mode, bit0 for port0 and so on. //------------- NXP -------------// -#if TU_CHECK_MCU(LPC175X_6X) || TU_CHECK_MCU(LPC177X_8X) || TU_CHECK_MCU(LPC40XX) +#if TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC40XX) #define HCD_ATTR_OHCI -#elif TU_CHECK_MCU(LPC18XX) || TU_CHECK_MCU(LPC43XX) +#elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX) #define HCD_ATTR_EHCI_TRANSDIMENSION -#elif TU_CHECK_MCU(LPC54XXX) +#elif TU_CHECK_MCU(OPT_MCU_LPC54XXX) // #define HCD_ATTR_EHCI_NXP_PTD -#elif TU_CHECK_MCU(LPC55XX) +#elif TU_CHECK_MCU(OPT_MCU_LPC55XX) // #define HCD_ATTR_EHCI_NXP_PTD -#elif TU_CHECK_MCU(MIMXRT10XX) +#elif TU_CHECK_MCU(OPT_MCU_MIMXRT10XX) #define HCD_ATTR_EHCI_TRANSDIMENSION -#elif TU_CHECK_MCU(MKL25ZXX) +#elif TU_CHECK_MCU(OPT_MCU_MKL25ZXX) //------------- Microchip -------------// -#elif TU_CHECK_MCU(SAMD21) || TU_CHECK_MCU(SAMD51) || TU_CHECK_MCU(SAME5X) || \ - TU_CHECK_MCU(SAMD11) || TU_CHECK_MCU(SAML21) || TU_CHECK_MCU(SAML22) +#elif TU_CHECK_MCU(OPT_MCU_SAMD21, OPT_MCU_SAMD51, OPT_MCU_SAME5X) || \ + TU_CHECK_MCU(OPT_MCU_SAMD11, OPT_MCU_SAML21, OPT_MCU_SAML22) -#elif TU_CHECK_MCU(SAMG) +#elif TU_CHECK_MCU(OPT_MCU_SAMG) -#elif TU_CHECK_MCU(SAMX7X) +#elif TU_CHECK_MCU(OPT_MCU_SAMX7X) //------------- ST -------------// -#elif TU_CHECK_MCU(STM32F0) || TU_CHECK_MCU(STM32F1) || TU_CHECK_MCU(STM32F3) || \ - TU_CHECK_MCU(STM32L0) || TU_CHECK_MCU(STM32L1) || TU_CHECK_MCU(STM32L4) +#elif TU_CHECK_MCU(OPT_MCU_STM32F0, OPT_MCU_STM32F1, OPT_MCU_STM32F3) || \ + TU_CHECK_MCU(OPT_MCU_STM32L0, OPT_MCU_STM32L1, OPT_MCU_STM32L4) -#elif TU_CHECK_MCU(STM32F2) || TU_CHECK_MCU(STM32F4) || TU_CHECK_MCU(STM32F3) +#elif TU_CHECK_MCU(OPT_MCU_STM32F2, OPT_MCU_STM32F3, OPT_MCU_STM32F4) -#elif TU_CHECK_MCU(STM32F7) +#elif TU_CHECK_MCU(OPT_MCU_STM32F7) -#elif TU_CHECK_MCU(STM32H7) +#elif TU_CHECK_MCU(OPT_MCU_STM32H7) //------------- Sony -------------// -#elif TU_CHECK_MCU(CXD56) +#elif TU_CHECK_MCU(OPT_MCU_CXD56) //------------- Nuvoton -------------// -#elif TU_CHECK_MCU(NUC505) +#elif TU_CHECK_MCU(OPT_MCU_NUC505) //------------- Espressif -------------// -#elif TU_CHECK_MCU(ESP32S2) || TU_CHECK_MCU(ESP32S3) +#elif TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) //------------- Raspberry Pi -------------// -#elif TU_CHECK_MCU(RP2040) +#elif TU_CHECK_MCU(OPT_MCU_RP2040) //------------- Silabs -------------// -#elif TU_CHECK_MCU(EFM32GG) || TU_CHECK_MCU(EFM32GG11) || TU_CHECK_MCU(EFM32GG12) +#elif TU_CHECK_MCU(OPT_MCU_EFM32GG, OPT_MCU_EFM32GG11, OPT_MCU_EFM32GG12) //------------- Renesas -------------// -#elif TU_CHECK_MCU(RX63X) || TU_CHECK_MCU(RX65X) || TU_CHECK_MCU(RX72N) +#elif TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) -//#elif TU_CHECK_MCU(MM32F327X) +//#elif TU_CHECK_MCU(OPT_MCU_MM32F327X) // #define DCD_ATTR_ENDPOINT_MAX not known yet //------------- GigaDevice -------------// -#elif TU_CHECK_MCU(GD32VF103) +#elif TU_CHECK_MCU(OPT_MCU_GD32VF103) #else // #warning "DCD_ATTR_ENDPOINT_MAX is not defined for this MCU, default to 8" diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index ca6564d46..933f352a2 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -109,13 +109,10 @@ #define STM32F1_FSDEV #endif -#if (TUSB_OPT_DEVICE_ENABLED) && ( \ - (CFG_TUSB_MCU == OPT_MCU_STM32F0 ) || \ - (CFG_TUSB_MCU == OPT_MCU_STM32F1 && defined(STM32F1_FSDEV)) || \ - (CFG_TUSB_MCU == OPT_MCU_STM32F3 ) || \ - (CFG_TUSB_MCU == OPT_MCU_STM32L0 ) || \ - (CFG_TUSB_MCU == OPT_MCU_STM32L1 ) \ - ) +#if TUSB_OPT_DEVICE_ENABLED && \ + ( TU_CHECK_MCU(OPT_MCU_STM32F0, OPT_MCU_STM32F3, OPT_MCU_STM32L0, OPT_MCU_STM32L1) || \ + (TU_CHECK_MCU(OPT_MCU_STM32F1) && defined(STM32F1_FSDEV)) \ + ) // In order to reduce the dependance on HAL, we undefine this. // Some definitions are copied to our private include file. diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index fca5321f7..7ae10652c 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -31,16 +31,16 @@ #include "device/dcd_attr.h" #if TUSB_OPT_DEVICE_ENABLED && \ - ( defined(DCD_ATTR_DWC2_STM32) || TU_CHECK_MCU(ESP32S2, ESP32S3, GD32VF103) ) + ( defined(DCD_ATTR_DWC2_STM32) || TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3, OPT_MCU_GD32VF103) ) #include "device/dcd.h" #include "dwc2_type.h" #if defined(DCD_ATTR_DWC2_STM32) #include "dwc2_stm32.h" -#elif TU_CHECK_MCU(ESP32S2, ESP32S3) +#elif TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) #include "dwc2_esp32.h" -#elif TU_CHECK_MCU(GD32VF103) +#elif TU_CHECK_MCU(OPT_MCU_GD32VF103) #include "dwc2_gd32.h" #else #error "Unsupported MCUs" diff --git a/src/tusb_option.h b/src/tusb_option.h index d707c44c7..509ff4a3c 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -130,7 +130,7 @@ // Helper to check if configured MCU is one of listed // Apply _TU_CHECK_MCU with || as separator to list of input -#define _TU_CHECK_MCU(_m) (CFG_TUSB_MCU == OPT_MCU_##_m) +#define _TU_CHECK_MCU(_m) (CFG_TUSB_MCU == _m) #define TU_CHECK_MCU(...) (TU_ARGS_APPLY(_TU_CHECK_MCU, ||, __VA_ARGS__)) //--------------------------------------------------------------------+ -- cgit v1.3.1 From 7d0d6f85f2aa9ff228ec76387a3d2d0ebf2580bb Mon Sep 17 00:00:00 2001 From: suda-morris <362953310@qq.com> Date: Mon, 25 Oct 2021 21:53:14 +0800 Subject: update dcd_esp32sx with correct include list --- src/portable/espressif/esp32sx/dcd_esp32sx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/portable/espressif/esp32sx/dcd_esp32sx.c b/src/portable/espressif/esp32sx/dcd_esp32sx.c index c27fc2922..a9c311324 100644 --- a/src/portable/espressif/esp32sx/dcd_esp32sx.c +++ b/src/portable/espressif/esp32sx/dcd_esp32sx.c @@ -31,7 +31,6 @@ #if (((CFG_TUSB_MCU == OPT_MCU_ESP32S2) || (CFG_TUSB_MCU == OPT_MCU_ESP32S3)) && TUSB_OPT_DEVICE_ENABLED) // Espressif -#include "driver/periph_ctrl.h" #include "freertos/xtensa_api.h" #include "esp_intr_alloc.h" #include "esp_log.h" @@ -39,6 +38,7 @@ #include "soc/dport_reg.h" #include "soc/gpio_sig_map.h" #include "soc/usb_periph.h" +#include "soc/periph_defs.h" // for interrupt source #include "device/dcd.h" -- cgit v1.3.1 From 460052c8a0b21d715a8206149f8106de0c5c38aa Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 25 Oct 2021 21:20:58 +0700 Subject: spacing --- src/portable/synopsys/dwc2/dwc2_gd32.h | 2 - src/portable/synopsys/dwc2/dwc2_type.h | 1979 ++++++++++++++++---------------- 2 files changed, 983 insertions(+), 998 deletions(-) diff --git a/src/portable/synopsys/dwc2/dwc2_gd32.h b/src/portable/synopsys/dwc2/dwc2_gd32.h index 1ad066720..db1fb89fd 100644 --- a/src/portable/synopsys/dwc2/dwc2_gd32.h +++ b/src/portable/synopsys/dwc2/dwc2_gd32.h @@ -32,8 +32,6 @@ extern "C" { #endif - -// These numbers are the same for the whole GD32VF103 family. #define DWC2_REG_BASE 0x50000000UL #define DWC2_EP_MAX 4 #define DWC2_EP_FIFO_SIZE 1280 diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index 5f3b4a420..8d12e21ce 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -23,136 +23,124 @@ extern "C" { #endif -#ifdef __cplusplus - #define __I volatile -#else - #define __I volatile const -#endif -#define __O volatile -#define __IO volatile -#define __IM volatile const -#define __OM volatile -#define __IOM volatile - #if 0 // HS PHY typedef struct { - -__IO uint32_t HS_PHYC_PLL; /*!< This register is used to control the PLL of the HS PHY. 000h */ -__IO uint32_t Reserved04; /*!< Reserved 004h */ -__IO uint32_t Reserved08; /*!< Reserved 008h */ -__IO uint32_t HS_PHYC_TUNE; /*!< This register is used to control the tuning interface of the High Speed PHY. 00Ch */ -__IO uint32_t Reserved10; /*!< Reserved 010h */ -__IO uint32_t Reserved14; /*!< Reserved 014h */ -__IO uint32_t HS_PHYC_LDO; /*!< This register is used to control the regulator (LDO). 018h */ + volatile uint32_t HS_PHYC_PLL; /*!< This register is used to control the PLL of the HS PHY. 000h */ + volatile uint32_t Reserved04; /*!< Reserved 004h */ + volatile uint32_t Reserved08; /*!< Reserved 008h */ + volatile uint32_t HS_PHYC_TUNE; /*!< This register is used to control the tuning interface of the High Speed PHY. 00Ch */ + volatile uint32_t Reserved10; /*!< Reserved 010h */ + volatile uint32_t Reserved14; /*!< Reserved 014h */ + volatile uint32_t HS_PHYC_LDO; /*!< This register is used to control the regulator (LDO). 018h */ } HS_PHYC_GlobalTypeDef; #endif // Core typedef struct { - __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ - __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ - __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ - __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ - __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ - __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ - __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ - __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ - __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ - __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ - __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */ - __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ - uint32_t Reserved30[2]; /*!< Reserved 030h */ - __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */ - __IO uint32_t CID; /*!< User ID Register 03Ch */ - __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/ - __IO uint32_t GHWCFG1; /* User HW config1 044h*/ - __IO uint32_t GHWCFG2; /* User HW config2 048h*/ - __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */ - uint32_t Reserved6; /*!< Reserved 050h */ - __IO uint32_t GLPMCFG; /*!< LPM Register 054h */ - __IO uint32_t GPWRDN; /*!< Power Down Register 058h */ - __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */ - __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */ - uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */ - __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */ - __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO 104h-13Ch */ + volatile uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ + volatile uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ + volatile uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ + volatile uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ + volatile uint32_t GRSTCTL; /*!< Core Reset Register 010h */ + volatile uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ + volatile uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ + volatile uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ + volatile uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ + volatile uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ + volatile uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */ + volatile uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ + uint32_t Reserved30[2]; /*!< Reserved 030h */ + volatile uint32_t GCCFG; /*!< General Purpose IO Register 038h */ + volatile uint32_t CID; /*!< User ID Register 03Ch */ + volatile uint32_t GSNPSID; /* USB_OTG core ID 040h*/ + volatile uint32_t GHWCFG1; /* User HW config1 044h*/ + volatile uint32_t GHWCFG2; /* User HW config2 048h*/ + volatile uint32_t GHWCFG3; /*!< User HW config3 04Ch */ + uint32_t Reserved6; /*!< Reserved 050h */ + volatile uint32_t GLPMCFG; /*!< LPM Register 054h */ + volatile uint32_t GPWRDN; /*!< Power Down Register 058h */ + volatile uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */ + volatile uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */ + uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */ + volatile uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */ + volatile uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO 104h-13Ch */ } dwc2_core_t; // Host typedef struct { - __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ - __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ - __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */ - uint32_t Reserved40C; /*!< Reserved 40Ch */ - __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */ - __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */ - __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ + volatile uint32_t HCFG; /*!< Host Configuration Register 400h */ + volatile uint32_t HFIR; /*!< Host Frame Interval Register 404h */ + volatile uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */ + uint32_t Reserved40C; /*!< Reserved 40Ch */ + volatile uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */ + volatile uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */ + volatile uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ } dwc2_host_t; // Host Channel typedef struct { - __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */ - __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */ - __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */ - __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */ - __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */ - __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */ - uint32_t Reserved[2]; /*!< Reserved */ + volatile uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */ + volatile uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */ + volatile uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */ + volatile uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */ + volatile uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */ + volatile uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */ + uint32_t Reserved[2]; /*!< Reserved */ } dwc2_channel_t; // Device typedef struct { - __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ - __IO uint32_t DCTL; /*!< dev Control Register 804h */ - __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */ - uint32_t Reserved0C; /*!< Reserved 80Ch */ - __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ - __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ - __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ - __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ - uint32_t Reserved20; /*!< Reserved 820h */ - uint32_t Reserved9; /*!< Reserved 824h */ - __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ - __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ - __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ - __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ - __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ - __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ - uint32_t Reserved40; /*!< dedicated EP mask 840h */ - __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ - uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ - __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ + volatile uint32_t DCFG; /*!< dev Configuration Register 800h */ + volatile uint32_t DCTL; /*!< dev Control Register 804h */ + volatile uint32_t DSTS; /*!< dev Status Register (RO) 808h */ + uint32_t Reserved0C; /*!< Reserved 80Ch */ + volatile uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ + volatile uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ + volatile uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ + volatile uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ + uint32_t Reserved20; /*!< Reserved 820h */ + uint32_t Reserved9; /*!< Reserved 824h */ + volatile uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ + volatile uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ + volatile uint32_t DTHRCTL; /*!< dev threshold 830h */ + volatile uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ + volatile uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ + volatile uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask 840h */ + volatile uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ + uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ + volatile uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ } dwc2_device_t; // Endpoint IN typedef struct { - __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ - uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ - __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ - uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ - __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ - __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ - __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ - uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ + volatile uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ + volatile uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ + volatile uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ + volatile uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ + volatile uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ + uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ } dwc2_epin_t; // Endpoint OUT typedef struct { - __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ - uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ - __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ - uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ - __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ - __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ - uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ + volatile uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ + volatile uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ + volatile uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ + volatile uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ + uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ } dwc2_epout_t; @@ -179,1411 +167,1410 @@ typedef struct /******************** Bit definition for GOTGCTL register ********************/ #define GOTGCTL_SRQSCS_Pos (0U) -#define GOTGCTL_SRQSCS_Msk (0x1UL << GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */ -#define GOTGCTL_SRQSCS GOTGCTL_SRQSCS_Msk /*!< Session request success */ +#define GOTGCTL_SRQSCS_Msk (0x1UL << GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */ +#define GOTGCTL_SRQSCS GOTGCTL_SRQSCS_Msk /*!< Session request success */ #define GOTGCTL_SRQ_Pos (1U) -#define GOTGCTL_SRQ_Msk (0x1UL << GOTGCTL_SRQ_Pos) /*!< 0x00000002 */ -#define GOTGCTL_SRQ GOTGCTL_SRQ_Msk /*!< Session request */ +#define GOTGCTL_SRQ_Msk (0x1UL << GOTGCTL_SRQ_Pos) /*!< 0x00000002 */ +#define GOTGCTL_SRQ GOTGCTL_SRQ_Msk /*!< Session request */ #define GOTGCTL_VBVALOEN_Pos (2U) -#define GOTGCTL_VBVALOEN_Msk (0x1UL << GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */ -#define GOTGCTL_VBVALOEN GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */ +#define GOTGCTL_VBVALOEN_Msk (0x1UL << GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */ +#define GOTGCTL_VBVALOEN GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */ #define GOTGCTL_VBVALOVAL_Pos (3U) -#define GOTGCTL_VBVALOVAL_Msk (0x1UL << GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */ -#define GOTGCTL_VBVALOVAL GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */ +#define GOTGCTL_VBVALOVAL_Msk (0x1UL << GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */ +#define GOTGCTL_VBVALOVAL GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */ #define GOTGCTL_AVALOEN_Pos (4U) -#define GOTGCTL_AVALOEN_Msk (0x1UL << GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */ -#define GOTGCTL_AVALOEN GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */ +#define GOTGCTL_AVALOEN_Msk (0x1UL << GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */ +#define GOTGCTL_AVALOEN GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */ #define GOTGCTL_AVALOVAL_Pos (5U) -#define GOTGCTL_AVALOVAL_Msk (0x1UL << GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */ -#define GOTGCTL_AVALOVAL GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */ +#define GOTGCTL_AVALOVAL_Msk (0x1UL << GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */ +#define GOTGCTL_AVALOVAL GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */ #define GOTGCTL_BVALOEN_Pos (6U) -#define GOTGCTL_BVALOEN_Msk (0x1UL << GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */ -#define GOTGCTL_BVALOEN GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */ +#define GOTGCTL_BVALOEN_Msk (0x1UL << GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */ +#define GOTGCTL_BVALOEN GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */ #define GOTGCTL_BVALOVAL_Pos (7U) -#define GOTGCTL_BVALOVAL_Msk (0x1UL << GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */ -#define GOTGCTL_BVALOVAL GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */ +#define GOTGCTL_BVALOVAL_Msk (0x1UL << GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */ +#define GOTGCTL_BVALOVAL GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */ #define GOTGCTL_HNGSCS_Pos (8U) -#define GOTGCTL_HNGSCS_Msk (0x1UL << GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */ -#define GOTGCTL_HNGSCS GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */ +#define GOTGCTL_HNGSCS_Msk (0x1UL << GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */ +#define GOTGCTL_HNGSCS GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */ #define GOTGCTL_HNPRQ_Pos (9U) -#define GOTGCTL_HNPRQ_Msk (0x1UL << GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */ -#define GOTGCTL_HNPRQ GOTGCTL_HNPRQ_Msk /*!< HNP request */ +#define GOTGCTL_HNPRQ_Msk (0x1UL << GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */ +#define GOTGCTL_HNPRQ GOTGCTL_HNPRQ_Msk /*!< HNP request */ #define GOTGCTL_HSHNPEN_Pos (10U) -#define GOTGCTL_HSHNPEN_Msk (0x1UL << GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */ -#define GOTGCTL_HSHNPEN GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */ +#define GOTGCTL_HSHNPEN_Msk (0x1UL << GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */ +#define GOTGCTL_HSHNPEN GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */ #define GOTGCTL_DHNPEN_Pos (11U) -#define GOTGCTL_DHNPEN_Msk (0x1UL << GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */ -#define GOTGCTL_DHNPEN GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */ +#define GOTGCTL_DHNPEN_Msk (0x1UL << GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */ +#define GOTGCTL_DHNPEN GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */ #define GOTGCTL_EHEN_Pos (12U) -#define GOTGCTL_EHEN_Msk (0x1UL << GOTGCTL_EHEN_Pos) /*!< 0x00001000 */ -#define GOTGCTL_EHEN GOTGCTL_EHEN_Msk /*!< Embedded host enable */ +#define GOTGCTL_EHEN_Msk (0x1UL << GOTGCTL_EHEN_Pos) /*!< 0x00001000 */ +#define GOTGCTL_EHEN GOTGCTL_EHEN_Msk /*!< Embedded host enable */ #define GOTGCTL_CIDSTS_Pos (16U) -#define GOTGCTL_CIDSTS_Msk (0x1UL << GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ -#define GOTGCTL_CIDSTS GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ +#define GOTGCTL_CIDSTS_Msk (0x1UL << GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ +#define GOTGCTL_CIDSTS GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ #define GOTGCTL_DBCT_Pos (17U) -#define GOTGCTL_DBCT_Msk (0x1UL << GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ -#define GOTGCTL_DBCT GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ +#define GOTGCTL_DBCT_Msk (0x1UL << GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ +#define GOTGCTL_DBCT GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ #define GOTGCTL_ASVLD_Pos (18U) -#define GOTGCTL_ASVLD_Msk (0x1UL << GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ -#define GOTGCTL_ASVLD GOTGCTL_ASVLD_Msk /*!< A-session valid */ +#define GOTGCTL_ASVLD_Msk (0x1UL << GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ +#define GOTGCTL_ASVLD GOTGCTL_ASVLD_Msk /*!< A-session valid */ #define GOTGCTL_BSESVLD_Pos (19U) -#define GOTGCTL_BSESVLD_Msk (0x1UL << GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */ -#define GOTGCTL_BSESVLD GOTGCTL_BSESVLD_Msk /*!< B-session valid */ +#define GOTGCTL_BSESVLD_Msk (0x1UL << GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */ +#define GOTGCTL_BSESVLD GOTGCTL_BSESVLD_Msk /*!< B-session valid */ #define GOTGCTL_OTGVER_Pos (20U) -#define GOTGCTL_OTGVER_Msk (0x1UL << GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ -#define GOTGCTL_OTGVER GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define GOTGCTL_OTGVER_Msk (0x1UL << GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ +#define GOTGCTL_OTGVER GOTGCTL_OTGVER_Msk /*!< OTG version */ /******************** Bit definition for HCFG register ********************/ #define HCFG_FSLSPCS_Pos (0U) -#define HCFG_FSLSPCS_Msk (0x3UL << HCFG_FSLSPCS_Pos) /*!< 0x00000003 */ -#define HCFG_FSLSPCS HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */ -#define HCFG_FSLSPCS_0 (0x1UL << HCFG_FSLSPCS_Pos) /*!< 0x00000001 */ -#define HCFG_FSLSPCS_1 (0x2UL << HCFG_FSLSPCS_Pos) /*!< 0x00000002 */ +#define HCFG_FSLSPCS_Msk (0x3UL << HCFG_FSLSPCS_Pos) /*!< 0x00000003 */ +#define HCFG_FSLSPCS HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */ +#define HCFG_FSLSPCS_0 (0x1UL << HCFG_FSLSPCS_Pos) /*!< 0x00000001 */ +#define HCFG_FSLSPCS_1 (0x2UL << HCFG_FSLSPCS_Pos) /*!< 0x00000002 */ #define HCFG_FSLSS_Pos (2U) -#define HCFG_FSLSS_Msk (0x1UL << HCFG_FSLSS_Pos) /*!< 0x00000004 */ -#define HCFG_FSLSS HCFG_FSLSS_Msk /*!< FS- and LS-only support */ +#define HCFG_FSLSS_Msk (0x1UL << HCFG_FSLSS_Pos) /*!< 0x00000004 */ +#define HCFG_FSLSS HCFG_FSLSS_Msk /*!< FS- and LS-only support */ /******************** Bit definition for DCFG register ********************/ #define DCFG_DSPD_Pos (0U) -#define DCFG_DSPD_Msk (0x3UL << DCFG_DSPD_Pos) /*!< 0x00000003 */ -#define DCFG_DSPD DCFG_DSPD_Msk /*!< Device speed */ -#define DCFG_DSPD_0 (0x1UL << DCFG_DSPD_Pos) /*!< 0x00000001 */ -#define DCFG_DSPD_1 (0x2UL << DCFG_DSPD_Pos) /*!< 0x00000002 */ +#define DCFG_DSPD_Msk (0x3UL << DCFG_DSPD_Pos) /*!< 0x00000003 */ +#define DCFG_DSPD DCFG_DSPD_Msk /*!< Device speed */ +#define DCFG_DSPD_0 (0x1UL << DCFG_DSPD_Pos) /*!< 0x00000001 */ +#define DCFG_DSPD_1 (0x2UL << DCFG_DSPD_Pos) /*!< 0x00000002 */ #define DCFG_NZLSOHSK_Pos (2U) -#define DCFG_NZLSOHSK_Msk (0x1UL << DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */ -#define DCFG_NZLSOHSK DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */ +#define DCFG_NZLSOHSK_Msk (0x1UL << DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */ +#define DCFG_NZLSOHSK DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */ #define DCFG_DAD_Pos (4U) -#define DCFG_DAD_Msk (0x7FUL << DCFG_DAD_Pos) /*!< 0x000007F0 */ -#define DCFG_DAD DCFG_DAD_Msk /*!< Device address */ -#define DCFG_DAD_0 (0x01UL << DCFG_DAD_Pos) /*!< 0x00000010 */ -#define DCFG_DAD_1 (0x02UL << DCFG_DAD_Pos) /*!< 0x00000020 */ -#define DCFG_DAD_2 (0x04UL << DCFG_DAD_Pos) /*!< 0x00000040 */ -#define DCFG_DAD_3 (0x08UL << DCFG_DAD_Pos) /*!< 0x00000080 */ -#define DCFG_DAD_4 (0x10UL << DCFG_DAD_Pos) /*!< 0x00000100 */ -#define DCFG_DAD_5 (0x20UL << DCFG_DAD_Pos) /*!< 0x00000200 */ -#define DCFG_DAD_6 (0x40UL << DCFG_DAD_Pos) /*!< 0x00000400 */ +#define DCFG_DAD_Msk (0x7FUL << DCFG_DAD_Pos) /*!< 0x000007F0 */ +#define DCFG_DAD DCFG_DAD_Msk /*!< Device address */ +#define DCFG_DAD_0 (0x01UL << DCFG_DAD_Pos) /*!< 0x00000010 */ +#define DCFG_DAD_1 (0x02UL << DCFG_DAD_Pos) /*!< 0x00000020 */ +#define DCFG_DAD_2 (0x04UL << DCFG_DAD_Pos) /*!< 0x00000040 */ +#define DCFG_DAD_3 (0x08UL << DCFG_DAD_Pos) /*!< 0x00000080 */ +#define DCFG_DAD_4 (0x10UL << DCFG_DAD_Pos) /*!< 0x00000100 */ +#define DCFG_DAD_5 (0x20UL << DCFG_DAD_Pos) /*!< 0x00000200 */ +#define DCFG_DAD_6 (0x40UL << DCFG_DAD_Pos) /*!< 0x00000400 */ #define DCFG_PFIVL_Pos (11U) -#define DCFG_PFIVL_Msk (0x3UL << DCFG_PFIVL_Pos) /*!< 0x00001800 */ -#define DCFG_PFIVL DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ -#define DCFG_PFIVL_0 (0x1UL << DCFG_PFIVL_Pos) /*!< 0x00000800 */ -#define DCFG_PFIVL_1 (0x2UL << DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define DCFG_PFIVL_Msk (0x3UL << DCFG_PFIVL_Pos) /*!< 0x00001800 */ +#define DCFG_PFIVL DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ +#define DCFG_PFIVL_0 (0x1UL << DCFG_PFIVL_Pos) /*!< 0x00000800 */ +#define DCFG_PFIVL_1 (0x2UL << DCFG_PFIVL_Pos) /*!< 0x00001000 */ #define DCFG_PERSCHIVL_Pos (24U) -#define DCFG_PERSCHIVL_Msk (0x3UL << DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ -#define DCFG_PERSCHIVL DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ -#define DCFG_PERSCHIVL_0 (0x1UL << DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */ -#define DCFG_PERSCHIVL_1 (0x2UL << DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */ +#define DCFG_PERSCHIVL_Msk (0x3UL << DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ +#define DCFG_PERSCHIVL DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ +#define DCFG_PERSCHIVL_0 (0x1UL << DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */ +#define DCFG_PERSCHIVL_1 (0x2UL << DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */ /******************** Bit definition for PCGCR register ********************/ #define PCGCR_STPPCLK_Pos (0U) -#define PCGCR_STPPCLK_Msk (0x1UL << PCGCR_STPPCLK_Pos) /*!< 0x00000001 */ -#define PCGCR_STPPCLK PCGCR_STPPCLK_Msk /*!< Stop PHY clock */ +#define PCGCR_STPPCLK_Msk (0x1UL << PCGCR_STPPCLK_Pos) /*!< 0x00000001 */ +#define PCGCR_STPPCLK PCGCR_STPPCLK_Msk /*!< Stop PHY clock */ #define PCGCR_GATEHCLK_Pos (1U) -#define PCGCR_GATEHCLK_Msk (0x1UL << PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */ -#define PCGCR_GATEHCLK PCGCR_GATEHCLK_Msk /*!< Gate HCLK */ +#define PCGCR_GATEHCLK_Msk (0x1UL << PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */ +#define PCGCR_GATEHCLK PCGCR_GATEHCLK_Msk /*!< Gate HCLK */ #define PCGCR_PHYSUSP_Pos (4U) -#define PCGCR_PHYSUSP_Msk (0x1UL << PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */ -#define PCGCR_PHYSUSP PCGCR_PHYSUSP_Msk /*!< PHY suspended */ +#define PCGCR_PHYSUSP_Msk (0x1UL << PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */ +#define PCGCR_PHYSUSP PCGCR_PHYSUSP_Msk /*!< PHY suspended */ /******************** Bit definition for GOTGINT register ********************/ #define GOTGINT_SEDET_Pos (2U) -#define GOTGINT_SEDET_Msk (0x1UL << GOTGINT_SEDET_Pos) /*!< 0x00000004 */ -#define GOTGINT_SEDET GOTGINT_SEDET_Msk /*!< Session end detected */ +#define GOTGINT_SEDET_Msk (0x1UL << GOTGINT_SEDET_Pos) /*!< 0x00000004 */ +#define GOTGINT_SEDET GOTGINT_SEDET_Msk /*!< Session end detected */ #define GOTGINT_SRSSCHG_Pos (8U) -#define GOTGINT_SRSSCHG_Msk (0x1UL << GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */ -#define GOTGINT_SRSSCHG GOTGINT_SRSSCHG_Msk /*!< Session request success status change */ +#define GOTGINT_SRSSCHG_Msk (0x1UL << GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */ +#define GOTGINT_SRSSCHG GOTGINT_SRSSCHG_Msk /*!< Session request success status change */ #define GOTGINT_HNSSCHG_Pos (9U) -#define GOTGINT_HNSSCHG_Msk (0x1UL << GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */ -#define GOTGINT_HNSSCHG GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */ +#define GOTGINT_HNSSCHG_Msk (0x1UL << GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */ +#define GOTGINT_HNSSCHG GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */ #define GOTGINT_HNGDET_Pos (17U) -#define GOTGINT_HNGDET_Msk (0x1UL << GOTGINT_HNGDET_Pos) /*!< 0x00020000 */ -#define GOTGINT_HNGDET GOTGINT_HNGDET_Msk /*!< Host negotiation detected */ +#define GOTGINT_HNGDET_Msk (0x1UL << GOTGINT_HNGDET_Pos) /*!< 0x00020000 */ +#define GOTGINT_HNGDET GOTGINT_HNGDET_Msk /*!< Host negotiation detected */ #define GOTGINT_ADTOCHG_Pos (18U) -#define GOTGINT_ADTOCHG_Msk (0x1UL << GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */ -#define GOTGINT_ADTOCHG GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */ +#define GOTGINT_ADTOCHG_Msk (0x1UL << GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */ +#define GOTGINT_ADTOCHG GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */ #define GOTGINT_DBCDNE_Pos (19U) -#define GOTGINT_DBCDNE_Msk (0x1UL << GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */ -#define GOTGINT_DBCDNE GOTGINT_DBCDNE_Msk /*!< Debounce done */ +#define GOTGINT_DBCDNE_Msk (0x1UL << GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */ +#define GOTGINT_DBCDNE GOTGINT_DBCDNE_Msk /*!< Debounce done */ #define GOTGINT_IDCHNG_Pos (20U) -#define GOTGINT_IDCHNG_Msk (0x1UL << GOTGINT_IDCHNG_Pos) /*!< 0x00100000 */ -#define GOTGINT_IDCHNG GOTGINT_IDCHNG_Msk /*!< Change in ID pin input value */ +#define GOTGINT_IDCHNG_Msk (0x1UL << GOTGINT_IDCHNG_Pos) /*!< 0x00100000 */ +#define GOTGINT_IDCHNG GOTGINT_IDCHNG_Msk /*!< Change in ID pin input value */ /******************** Bit definition for DCTL register ********************/ #define DCTL_RWUSIG_Pos (0U) -#define DCTL_RWUSIG_Msk (0x1UL << DCTL_RWUSIG_Pos) /*!< 0x00000001 */ -#define DCTL_RWUSIG DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */ +#define DCTL_RWUSIG_Msk (0x1UL << DCTL_RWUSIG_Pos) /*!< 0x00000001 */ +#define DCTL_RWUSIG DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */ #define DCTL_SDIS_Pos (1U) -#define DCTL_SDIS_Msk (0x1UL << DCTL_SDIS_Pos) /*!< 0x00000002 */ -#define DCTL_SDIS DCTL_SDIS_Msk /*!< Soft disconnect */ +#define DCTL_SDIS_Msk (0x1UL << DCTL_SDIS_Pos) /*!< 0x00000002 */ +#define DCTL_SDIS DCTL_SDIS_Msk /*!< Soft disconnect */ #define DCTL_GINSTS_Pos (2U) -#define DCTL_GINSTS_Msk (0x1UL << DCTL_GINSTS_Pos) /*!< 0x00000004 */ -#define DCTL_GINSTS DCTL_GINSTS_Msk /*!< Global IN NAK status */ +#define DCTL_GINSTS_Msk (0x1UL << DCTL_GINSTS_Pos) /*!< 0x00000004 */ +#define DCTL_GINSTS DCTL_GINSTS_Msk /*!< Global IN NAK status */ #define DCTL_GONSTS_Pos (3U) -#define DCTL_GONSTS_Msk (0x1UL << DCTL_GONSTS_Pos) /*!< 0x00000008 */ -#define DCTL_GONSTS DCTL_GONSTS_Msk /*!< Global OUT NAK status */ +#define DCTL_GONSTS_Msk (0x1UL << DCTL_GONSTS_Pos) /*!< 0x00000008 */ +#define DCTL_GONSTS DCTL_GONSTS_Msk /*!< Global OUT NAK status */ #define DCTL_TCTL_Pos (4U) -#define DCTL_TCTL_Msk (0x7UL << DCTL_TCTL_Pos) /*!< 0x00000070 */ -#define DCTL_TCTL DCTL_TCTL_Msk /*!< Test control */ -#define DCTL_TCTL_0 (0x1UL << DCTL_TCTL_Pos) /*!< 0x00000010 */ -#define DCTL_TCTL_1 (0x2UL << DCTL_TCTL_Pos) /*!< 0x00000020 */ -#define DCTL_TCTL_2 (0x4UL << DCTL_TCTL_Pos) /*!< 0x00000040 */ +#define DCTL_TCTL_Msk (0x7UL << DCTL_TCTL_Pos) /*!< 0x00000070 */ +#define DCTL_TCTL DCTL_TCTL_Msk /*!< Test control */ +#define DCTL_TCTL_0 (0x1UL << DCTL_TCTL_Pos) /*!< 0x00000010 */ +#define DCTL_TCTL_1 (0x2UL << DCTL_TCTL_Pos) /*!< 0x00000020 */ +#define DCTL_TCTL_2 (0x4UL << DCTL_TCTL_Pos) /*!< 0x00000040 */ #define DCTL_SGINAK_Pos (7U) -#define DCTL_SGINAK_Msk (0x1UL << DCTL_SGINAK_Pos) /*!< 0x00000080 */ -#define DCTL_SGINAK DCTL_SGINAK_Msk /*!< Set global IN NAK */ +#define DCTL_SGINAK_Msk (0x1UL << DCTL_SGINAK_Pos) /*!< 0x00000080 */ +#define DCTL_SGINAK DCTL_SGINAK_Msk /*!< Set global IN NAK */ #define DCTL_CGINAK_Pos (8U) -#define DCTL_CGINAK_Msk (0x1UL << DCTL_CGINAK_Pos) /*!< 0x00000100 */ -#define DCTL_CGINAK DCTL_CGINAK_Msk /*!< Clear global IN NAK */ +#define DCTL_CGINAK_Msk (0x1UL << DCTL_CGINAK_Pos) /*!< 0x00000100 */ +#define DCTL_CGINAK DCTL_CGINAK_Msk /*!< Clear global IN NAK */ #define DCTL_SGONAK_Pos (9U) -#define DCTL_SGONAK_Msk (0x1UL << DCTL_SGONAK_Pos) /*!< 0x00000200 */ -#define DCTL_SGONAK DCTL_SGONAK_Msk /*!< Set global OUT NAK */ +#define DCTL_SGONAK_Msk (0x1UL << DCTL_SGONAK_Pos) /*!< 0x00000200 */ +#define DCTL_SGONAK DCTL_SGONAK_Msk /*!< Set global OUT NAK */ #define DCTL_CGONAK_Pos (10U) -#define DCTL_CGONAK_Msk (0x1UL << DCTL_CGONAK_Pos) /*!< 0x00000400 */ -#define DCTL_CGONAK DCTL_CGONAK_Msk /*!< Clear global OUT NAK */ +#define DCTL_CGONAK_Msk (0x1UL << DCTL_CGONAK_Pos) /*!< 0x00000400 */ +#define DCTL_CGONAK DCTL_CGONAK_Msk /*!< Clear global OUT NAK */ #define DCTL_POPRGDNE_Pos (11U) -#define DCTL_POPRGDNE_Msk (0x1UL << DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ -#define DCTL_POPRGDNE DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define DCTL_POPRGDNE_Msk (0x1UL << DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ +#define DCTL_POPRGDNE DCTL_POPRGDNE_Msk /*!< Power-on programming done */ /******************** Bit definition for HFIR register ********************/ #define HFIR_FRIVL_Pos (0U) -#define HFIR_FRIVL_Msk (0xFFFFUL << HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ -#define HFIR_FRIVL HFIR_FRIVL_Msk /*!< Frame interval */ +#define HFIR_FRIVL_Msk (0xFFFFUL << HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ +#define HFIR_FRIVL HFIR_FRIVL_Msk /*!< Frame interval */ /******************** Bit definition for HFNUM register ********************/ #define HFNUM_FRNUM_Pos (0U) -#define HFNUM_FRNUM_Msk (0xFFFFUL << HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */ -#define HFNUM_FRNUM HFNUM_FRNUM_Msk /*!< Frame number */ +#define HFNUM_FRNUM_Msk (0xFFFFUL << HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */ +#define HFNUM_FRNUM HFNUM_FRNUM_Msk /*!< Frame number */ #define HFNUM_FTREM_Pos (16U) -#define HFNUM_FTREM_Msk (0xFFFFUL << HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */ -#define HFNUM_FTREM HFNUM_FTREM_Msk /*!< Frame time remaining */ +#define HFNUM_FTREM_Msk (0xFFFFUL << HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */ +#define HFNUM_FTREM HFNUM_FTREM_Msk /*!< Frame time remaining */ /******************** Bit definition for DSTS register ********************/ #define DSTS_SUSPSTS_Pos (0U) -#define DSTS_SUSPSTS_Msk (0x1UL << DSTS_SUSPSTS_Pos) /*!< 0x00000001 */ -#define DSTS_SUSPSTS DSTS_SUSPSTS_Msk /*!< Suspend status */ +#define DSTS_SUSPSTS_Msk (0x1UL << DSTS_SUSPSTS_Pos) /*!< 0x00000001 */ +#define DSTS_SUSPSTS DSTS_SUSPSTS_Msk /*!< Suspend status */ #define DSTS_ENUMSPD_Pos (1U) -#define DSTS_ENUMSPD_Msk (0x3UL << DSTS_ENUMSPD_Pos) /*!< 0x00000006 */ -#define DSTS_ENUMSPD DSTS_ENUMSPD_Msk /*!< Enumerated speed */ -#define DSTS_ENUMSPD_0 (0x1UL << DSTS_ENUMSPD_Pos) /*!< 0x00000002 */ -#define DSTS_ENUMSPD_1 (0x2UL << DSTS_ENUMSPD_Pos) /*!< 0x00000004 */ +#define DSTS_ENUMSPD_Msk (0x3UL << DSTS_ENUMSPD_Pos) /*!< 0x00000006 */ +#define DSTS_ENUMSPD DSTS_ENUMSPD_Msk /*!< Enumerated speed */ +#define DSTS_ENUMSPD_0 (0x1UL << DSTS_ENUMSPD_Pos) /*!< 0x00000002 */ +#define DSTS_ENUMSPD_1 (0x2UL << DSTS_ENUMSPD_Pos) /*!< 0x00000004 */ #define DSTS_EERR_Pos (3U) -#define DSTS_EERR_Msk (0x1UL << DSTS_EERR_Pos) /*!< 0x00000008 */ -#define DSTS_EERR DSTS_EERR_Msk /*!< Erratic error */ +#define DSTS_EERR_Msk (0x1UL << DSTS_EERR_Pos) /*!< 0x00000008 */ +#define DSTS_EERR DSTS_EERR_Msk /*!< Erratic error */ #define DSTS_FNSOF_Pos (8U) -#define DSTS_FNSOF_Msk (0x3FFFUL << DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ -#define DSTS_FNSOF DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ +#define DSTS_FNSOF_Msk (0x3FFFUL << DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ +#define DSTS_FNSOF DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ /******************** Bit definition for GAHBCFG register ********************/ #define GAHBCFG_GINT_Pos (0U) -#define GAHBCFG_GINT_Msk (0x1UL << GAHBCFG_GINT_Pos) /*!< 0x00000001 */ -#define GAHBCFG_GINT GAHBCFG_GINT_Msk /*!< Global interrupt mask */ +#define GAHBCFG_GINT_Msk (0x1UL << GAHBCFG_GINT_Pos) /*!< 0x00000001 */ +#define GAHBCFG_GINT GAHBCFG_GINT_Msk /*!< Global interrupt mask */ #define GAHBCFG_HBSTLEN_Pos (1U) -#define GAHBCFG_HBSTLEN_Msk (0xFUL << GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ -#define GAHBCFG_HBSTLEN GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ -#define GAHBCFG_HBSTLEN_0 (0x0UL << GAHBCFG_HBSTLEN_Pos) /*!< Single */ -#define GAHBCFG_HBSTLEN_1 (0x1UL << GAHBCFG_HBSTLEN_Pos) /*!< INCR */ -#define GAHBCFG_HBSTLEN_2 (0x3UL << GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */ -#define GAHBCFG_HBSTLEN_3 (0x5UL << GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */ -#define GAHBCFG_HBSTLEN_4 (0x7UL << GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */ +#define GAHBCFG_HBSTLEN_Msk (0xFUL << GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ +#define GAHBCFG_HBSTLEN GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ +#define GAHBCFG_HBSTLEN_0 (0x0UL << GAHBCFG_HBSTLEN_Pos) /*!< Single */ +#define GAHBCFG_HBSTLEN_1 (0x1UL << GAHBCFG_HBSTLEN_Pos) /*!< INCR */ +#define GAHBCFG_HBSTLEN_2 (0x3UL << GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */ +#define GAHBCFG_HBSTLEN_3 (0x5UL << GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */ +#define GAHBCFG_HBSTLEN_4 (0x7UL << GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */ #define GAHBCFG_DMAEN_Pos (5U) -#define GAHBCFG_DMAEN_Msk (0x1UL << GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */ -#define GAHBCFG_DMAEN GAHBCFG_DMAEN_Msk /*!< DMA enable */ +#define GAHBCFG_DMAEN_Msk (0x1UL << GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */ +#define GAHBCFG_DMAEN GAHBCFG_DMAEN_Msk /*!< DMA enable */ #define GAHBCFG_TXFELVL_Pos (7U) -#define GAHBCFG_TXFELVL_Msk (0x1UL << GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */ -#define GAHBCFG_TXFELVL GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */ +#define GAHBCFG_TXFELVL_Msk (0x1UL << GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */ +#define GAHBCFG_TXFELVL GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */ #define GAHBCFG_PTXFELVL_Pos (8U) -#define GAHBCFG_PTXFELVL_Msk (0x1UL << GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */ -#define GAHBCFG_PTXFELVL GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */ +#define GAHBCFG_PTXFELVL_Msk (0x1UL << GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */ +#define GAHBCFG_PTXFELVL GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */ /******************** Bit definition for GUSBCFG register ********************/ #define GUSBCFG_TOCAL_Pos (0U) -#define GUSBCFG_TOCAL_Msk (0x7UL << GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */ -#define GUSBCFG_TOCAL GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */ -#define GUSBCFG_TOCAL_0 (0x1UL << GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */ -#define GUSBCFG_TOCAL_1 (0x2UL << GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */ -#define GUSBCFG_TOCAL_2 (0x4UL << GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */ +#define GUSBCFG_TOCAL_Msk (0x7UL << GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */ +#define GUSBCFG_TOCAL GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */ +#define GUSBCFG_TOCAL_0 (0x1UL << GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */ +#define GUSBCFG_TOCAL_1 (0x2UL << GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */ +#define GUSBCFG_TOCAL_2 (0x4UL << GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */ #define GUSBCFG_PHYIF_Pos (3U) -#define GUSBCFG_PHYIF_Msk (0x1UL << GUSBCFG_PHYIF_Pos) /*!< 0x00000008 */ -#define GUSBCFG_PHYIF GUSBCFG_PHYIF_Msk /*!< PHY Interface (PHYIf) */ +#define GUSBCFG_PHYIF_Msk (0x1UL << GUSBCFG_PHYIF_Pos) /*!< 0x00000008 */ +#define GUSBCFG_PHYIF GUSBCFG_PHYIF_Msk /*!< PHY Interface (PHYIf) */ #define GUSBCFG_ULPI_UTMI_SEL_Pos (4U) -#define GUSBCFG_ULPI_UTMI_SEL_Msk (0x1UL << GUSBCFG_ULPI_UTMI_SEL_Pos) /*!< 0x00000010 */ -#define GUSBCFG_ULPI_UTMI_SEL GUSBCFG_ULPI_UTMI_SEL_Msk /*!< ULPI or UTMI+ Select (ULPI_UTMI_Sel) */ +#define GUSBCFG_ULPI_UTMI_SEL_Msk (0x1UL << GUSBCFG_ULPI_UTMI_SEL_Pos) /*!< 0x00000010 */ +#define GUSBCFG_ULPI_UTMI_SEL GUSBCFG_ULPI_UTMI_SEL_Msk /*!< ULPI or UTMI+ Select (ULPI_UTMI_Sel) */ #define GUSBCFG_PHYSEL_Pos (6U) -#define GUSBCFG_PHYSEL_Msk (0x1UL << GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */ -#define GUSBCFG_PHYSEL GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */ +#define GUSBCFG_PHYSEL_Msk (0x1UL << GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */ +#define GUSBCFG_PHYSEL GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */ #define GUSBCFG_SRPCAP_Pos (8U) -#define GUSBCFG_SRPCAP_Msk (0x1UL << GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */ -#define GUSBCFG_SRPCAP GUSBCFG_SRPCAP_Msk /*!< SRP-capable */ +#define GUSBCFG_SRPCAP_Msk (0x1UL << GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */ +#define GUSBCFG_SRPCAP GUSBCFG_SRPCAP_Msk /*!< SRP-capable */ #define GUSBCFG_HNPCAP_Pos (9U) -#define GUSBCFG_HNPCAP_Msk (0x1UL << GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */ -#define GUSBCFG_HNPCAP GUSBCFG_HNPCAP_Msk /*!< HNP-capable */ +#define GUSBCFG_HNPCAP_Msk (0x1UL << GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */ +#define GUSBCFG_HNPCAP GUSBCFG_HNPCAP_Msk /*!< HNP-capable */ #define GUSBCFG_TRDT_Pos (10U) -#define GUSBCFG_TRDT_Msk (0xFUL << GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */ -#define GUSBCFG_TRDT GUSBCFG_TRDT_Msk /*!< USB turnaround time */ -#define GUSBCFG_TRDT_0 (0x1UL << GUSBCFG_TRDT_Pos) /*!< 0x00000400 */ -#define GUSBCFG_TRDT_1 (0x2UL << GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ -#define GUSBCFG_TRDT_2 (0x4UL << GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ -#define GUSBCFG_TRDT_3 (0x8UL << GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ +#define GUSBCFG_TRDT_Msk (0xFUL << GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */ +#define GUSBCFG_TRDT GUSBCFG_TRDT_Msk /*!< USB turnaround time */ +#define GUSBCFG_TRDT_0 (0x1UL << GUSBCFG_TRDT_Pos) /*!< 0x00000400 */ +#define GUSBCFG_TRDT_1 (0x2UL << GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ +#define GUSBCFG_TRDT_2 (0x4UL << GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ +#define GUSBCFG_TRDT_3 (0x8UL << GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ #define GUSBCFG_PHYLPCS_Pos (15U) -#define GUSBCFG_PHYLPCS_Msk (0x1UL << GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ -#define GUSBCFG_PHYLPCS GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ +#define GUSBCFG_PHYLPCS_Msk (0x1UL << GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ +#define GUSBCFG_PHYLPCS GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ #define GUSBCFG_ULPIFSLS_Pos (17U) -#define GUSBCFG_ULPIFSLS_Msk (0x1UL << GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ -#define GUSBCFG_ULPIFSLS GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ +#define GUSBCFG_ULPIFSLS_Msk (0x1UL << GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ +#define GUSBCFG_ULPIFSLS GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ #define GUSBCFG_ULPIAR_Pos (18U) -#define GUSBCFG_ULPIAR_Msk (0x1UL << GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */ -#define GUSBCFG_ULPIAR GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */ +#define GUSBCFG_ULPIAR_Msk (0x1UL << GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */ +#define GUSBCFG_ULPIAR GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */ #define GUSBCFG_ULPICSM_Pos (19U) -#define GUSBCFG_ULPICSM_Msk (0x1UL << GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */ -#define GUSBCFG_ULPICSM GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */ +#define GUSBCFG_ULPICSM_Msk (0x1UL << GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */ +#define GUSBCFG_ULPICSM GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */ #define GUSBCFG_ULPIEVBUSD_Pos (20U) -#define GUSBCFG_ULPIEVBUSD_Msk (0x1UL << GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */ -#define GUSBCFG_ULPIEVBUSD GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */ +#define GUSBCFG_ULPIEVBUSD_Msk (0x1UL << GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */ +#define GUSBCFG_ULPIEVBUSD GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */ #define GUSBCFG_ULPIEVBUSI_Pos (21U) -#define GUSBCFG_ULPIEVBUSI_Msk (0x1UL << GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */ -#define GUSBCFG_ULPIEVBUSI GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */ +#define GUSBCFG_ULPIEVBUSI_Msk (0x1UL << GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */ +#define GUSBCFG_ULPIEVBUSI GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */ #define GUSBCFG_TSDPS_Pos (22U) -#define GUSBCFG_TSDPS_Msk (0x1UL << GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */ -#define GUSBCFG_TSDPS GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */ +#define GUSBCFG_TSDPS_Msk (0x1UL << GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */ +#define GUSBCFG_TSDPS GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */ #define GUSBCFG_PCCI_Pos (23U) -#define GUSBCFG_PCCI_Msk (0x1UL << GUSBCFG_PCCI_Pos) /*!< 0x00800000 */ -#define GUSBCFG_PCCI GUSBCFG_PCCI_Msk /*!< Indicator complement */ +#define GUSBCFG_PCCI_Msk (0x1UL << GUSBCFG_PCCI_Pos) /*!< 0x00800000 */ +#define GUSBCFG_PCCI GUSBCFG_PCCI_Msk /*!< Indicator complement */ #define GUSBCFG_PTCI_Pos (24U) -#define GUSBCFG_PTCI_Msk (0x1UL << GUSBCFG_PTCI_Pos) /*!< 0x01000000 */ -#define GUSBCFG_PTCI GUSBCFG_PTCI_Msk /*!< Indicator pass through */ +#define GUSBCFG_PTCI_Msk (0x1UL << GUSBCFG_PTCI_Pos) /*!< 0x01000000 */ +#define GUSBCFG_PTCI GUSBCFG_PTCI_Msk /*!< Indicator pass through */ #define GUSBCFG_ULPIIPD_Pos (25U) -#define GUSBCFG_ULPIIPD_Msk (0x1UL << GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */ -#define GUSBCFG_ULPIIPD GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */ +#define GUSBCFG_ULPIIPD_Msk (0x1UL << GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */ +#define GUSBCFG_ULPIIPD GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */ #define GUSBCFG_FHMOD_Pos (29U) -#define GUSBCFG_FHMOD_Msk (0x1UL << GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */ -#define GUSBCFG_FHMOD GUSBCFG_FHMOD_Msk /*!< Forced host mode */ +#define GUSBCFG_FHMOD_Msk (0x1UL << GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */ +#define GUSBCFG_FHMOD GUSBCFG_FHMOD_Msk /*!< Forced host mode */ #define GUSBCFG_FDMOD_Pos (30U) -#define GUSBCFG_FDMOD_Msk (0x1UL << GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */ -#define GUSBCFG_FDMOD GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */ +#define GUSBCFG_FDMOD_Msk (0x1UL << GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */ +#define GUSBCFG_FDMOD GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */ #define GUSBCFG_CTXPKT_Pos (31U) -#define GUSBCFG_CTXPKT_Msk (0x1UL << GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */ -#define GUSBCFG_CTXPKT GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */ +#define GUSBCFG_CTXPKT_Msk (0x1UL << GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */ +#define GUSBCFG_CTXPKT GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */ /******************** Bit definition for GRSTCTL register ********************/ #define GRSTCTL_CSRST_Pos (0U) -#define GRSTCTL_CSRST_Msk (0x1UL << GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ -#define GRSTCTL_CSRST GRSTCTL_CSRST_Msk /*!< Core soft reset */ +#define GRSTCTL_CSRST_Msk (0x1UL << GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ +#define GRSTCTL_CSRST GRSTCTL_CSRST_Msk /*!< Core soft reset */ #define GRSTCTL_HSRST_Pos (1U) -#define GRSTCTL_HSRST_Msk (0x1UL << GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ -#define GRSTCTL_HSRST GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ +#define GRSTCTL_HSRST_Msk (0x1UL << GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ +#define GRSTCTL_HSRST GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ #define GRSTCTL_FCRST_Pos (2U) -#define GRSTCTL_FCRST_Msk (0x1UL << GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ -#define GRSTCTL_FCRST GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ +#define GRSTCTL_FCRST_Msk (0x1UL << GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ +#define GRSTCTL_FCRST GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ #define GRSTCTL_RXFFLSH_Pos (4U) -#define GRSTCTL_RXFFLSH_Msk (0x1UL << GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */ -#define GRSTCTL_RXFFLSH GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */ +#define GRSTCTL_RXFFLSH_Msk (0x1UL << GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */ +#define GRSTCTL_RXFFLSH GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */ #define GRSTCTL_TXFFLSH_Pos (5U) -#define GRSTCTL_TXFFLSH_Msk (0x1UL << GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */ -#define GRSTCTL_TXFFLSH GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */ +#define GRSTCTL_TXFFLSH_Msk (0x1UL << GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */ +#define GRSTCTL_TXFFLSH GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */ #define GRSTCTL_TXFNUM_Pos (6U) -#define GRSTCTL_TXFNUM_Msk (0x1FUL << GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */ -#define GRSTCTL_TXFNUM GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */ -#define GRSTCTL_TXFNUM_0 (0x01UL << GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */ -#define GRSTCTL_TXFNUM_1 (0x02UL << GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */ -#define GRSTCTL_TXFNUM_2 (0x04UL << GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */ -#define GRSTCTL_TXFNUM_3 (0x08UL << GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */ -#define GRSTCTL_TXFNUM_4 (0x10UL << GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */ +#define GRSTCTL_TXFNUM_Msk (0x1FUL << GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */ +#define GRSTCTL_TXFNUM GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */ +#define GRSTCTL_TXFNUM_0 (0x01UL << GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */ +#define GRSTCTL_TXFNUM_1 (0x02UL << GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */ +#define GRSTCTL_TXFNUM_2 (0x04UL << GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */ +#define GRSTCTL_TXFNUM_3 (0x08UL << GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */ +#define GRSTCTL_TXFNUM_4 (0x10UL << GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */ #define GRSTCTL_DMAREQ_Pos (30U) -#define GRSTCTL_DMAREQ_Msk (0x1UL << GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */ -#define GRSTCTL_DMAREQ GRSTCTL_DMAREQ_Msk /*!< DMA request signal */ +#define GRSTCTL_DMAREQ_Msk (0x1UL << GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */ +#define GRSTCTL_DMAREQ GRSTCTL_DMAREQ_Msk /*!< DMA request signal */ #define GRSTCTL_AHBIDL_Pos (31U) -#define GRSTCTL_AHBIDL_Msk (0x1UL << GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */ -#define GRSTCTL_AHBIDL GRSTCTL_AHBIDL_Msk /*!< AHB master idle */ +#define GRSTCTL_AHBIDL_Msk (0x1UL << GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */ +#define GRSTCTL_AHBIDL GRSTCTL_AHBIDL_Msk /*!< AHB master idle */ /******************** Bit definition for DIEPMSK register ********************/ #define DIEPMSK_XFRCM_Pos (0U) -#define DIEPMSK_XFRCM_Msk (0x1UL << DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */ -#define DIEPMSK_XFRCM DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */ +#define DIEPMSK_XFRCM_Msk (0x1UL << DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */ +#define DIEPMSK_XFRCM DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */ #define DIEPMSK_EPDM_Pos (1U) -#define DIEPMSK_EPDM_Msk (0x1UL << DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ -#define DIEPMSK_EPDM DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define DIEPMSK_EPDM_Msk (0x1UL << DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ +#define DIEPMSK_EPDM DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ #define DIEPMSK_TOM_Pos (3U) -#define DIEPMSK_TOM_Msk (0x1UL << DIEPMSK_TOM_Pos) /*!< 0x00000008 */ -#define DIEPMSK_TOM DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ +#define DIEPMSK_TOM_Msk (0x1UL << DIEPMSK_TOM_Pos) /*!< 0x00000008 */ +#define DIEPMSK_TOM DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ #define DIEPMSK_ITTXFEMSK_Pos (4U) -#define DIEPMSK_ITTXFEMSK_Msk (0x1UL << DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */ -#define DIEPMSK_ITTXFEMSK DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ +#define DIEPMSK_ITTXFEMSK_Msk (0x1UL << DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */ +#define DIEPMSK_ITTXFEMSK DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ #define DIEPMSK_INEPNMM_Pos (5U) -#define DIEPMSK_INEPNMM_Msk (0x1UL << DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */ -#define DIEPMSK_INEPNMM DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ +#define DIEPMSK_INEPNMM_Msk (0x1UL << DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */ +#define DIEPMSK_INEPNMM DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ #define DIEPMSK_INEPNEM_Pos (6U) -#define DIEPMSK_INEPNEM_Msk (0x1UL << DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */ -#define DIEPMSK_INEPNEM DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ +#define DIEPMSK_INEPNEM_Msk (0x1UL << DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */ +#define DIEPMSK_INEPNEM DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ #define DIEPMSK_TXFURM_Pos (8U) -#define DIEPMSK_TXFURM_Msk (0x1UL << DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */ -#define DIEPMSK_TXFURM DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */ +#define DIEPMSK_TXFURM_Msk (0x1UL << DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */ +#define DIEPMSK_TXFURM DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */ #define DIEPMSK_BIM_Pos (9U) -#define DIEPMSK_BIM_Msk (0x1UL << DIEPMSK_BIM_Pos) /*!< 0x00000200 */ -#define DIEPMSK_BIM DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ +#define DIEPMSK_BIM_Msk (0x1UL << DIEPMSK_BIM_Pos) /*!< 0x00000200 */ +#define DIEPMSK_BIM DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ /******************** Bit definition for HPTXSTS register ********************/ #define HPTXSTS_PTXFSAVL_Pos (0U) -#define HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */ -#define HPTXSTS_PTXFSAVL HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */ +#define HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */ +#define HPTXSTS_PTXFSAVL HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */ #define HPTXSTS_PTXQSAV_Pos (16U) -#define HPTXSTS_PTXQSAV_Msk (0xFFUL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */ -#define HPTXSTS_PTXQSAV HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */ -#define HPTXSTS_PTXQSAV_0 (0x01UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */ -#define HPTXSTS_PTXQSAV_1 (0x02UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */ -#define HPTXSTS_PTXQSAV_2 (0x04UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */ -#define HPTXSTS_PTXQSAV_3 (0x08UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */ -#define HPTXSTS_PTXQSAV_4 (0x10UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */ -#define HPTXSTS_PTXQSAV_5 (0x20UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */ -#define HPTXSTS_PTXQSAV_6 (0x40UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */ -#define HPTXSTS_PTXQSAV_7 (0x80UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */ +#define HPTXSTS_PTXQSAV_Msk (0xFFUL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */ +#define HPTXSTS_PTXQSAV HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */ +#define HPTXSTS_PTXQSAV_0 (0x01UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */ +#define HPTXSTS_PTXQSAV_1 (0x02UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */ +#define HPTXSTS_PTXQSAV_2 (0x04UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */ +#define HPTXSTS_PTXQSAV_3 (0x08UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */ +#define HPTXSTS_PTXQSAV_4 (0x10UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */ +#define HPTXSTS_PTXQSAV_5 (0x20UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */ +#define HPTXSTS_PTXQSAV_6 (0x40UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */ +#define HPTXSTS_PTXQSAV_7 (0x80UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */ #define HPTXSTS_PTXQTOP_Pos (24U) -#define HPTXSTS_PTXQTOP_Msk (0xFFUL << HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */ -#define HPTXSTS_PTXQTOP HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */ -#define HPTXSTS_PTXQTOP_0 (0x01UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */ -#define HPTXSTS_PTXQTOP_1 (0x02UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */ -#define HPTXSTS_PTXQTOP_2 (0x04UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */ -#define HPTXSTS_PTXQTOP_3 (0x08UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */ -#define HPTXSTS_PTXQTOP_4 (0x10UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */ -#define HPTXSTS_PTXQTOP_5 (0x20UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */ -#define HPTXSTS_PTXQTOP_6 (0x40UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */ -#define HPTXSTS_PTXQTOP_7 (0x80UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */ +#define HPTXSTS_PTXQTOP_Msk (0xFFUL << HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */ +#define HPTXSTS_PTXQTOP HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */ +#define HPTXSTS_PTXQTOP_0 (0x01UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */ +#define HPTXSTS_PTXQTOP_1 (0x02UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */ +#define HPTXSTS_PTXQTOP_2 (0x04UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */ +#define HPTXSTS_PTXQTOP_3 (0x08UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */ +#define HPTXSTS_PTXQTOP_4 (0x10UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */ +#define HPTXSTS_PTXQTOP_5 (0x20UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */ +#define HPTXSTS_PTXQTOP_6 (0x40UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */ +#define HPTXSTS_PTXQTOP_7 (0x80UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */ /******************** Bit definition for HAINT register ********************/ #define HAINT_HAINT_Pos (0U) -#define HAINT_HAINT_Msk (0xFFFFUL << HAINT_HAINT_Pos) /*!< 0x0000FFFF */ -#define HAINT_HAINT HAINT_HAINT_Msk /*!< Channel interrupts */ +#define HAINT_HAINT_Msk (0xFFFFUL << HAINT_HAINT_Pos) /*!< 0x0000FFFF */ +#define HAINT_HAINT HAINT_HAINT_Msk /*!< Channel interrupts */ /******************** Bit definition for DOEPMSK register ********************/ #define DOEPMSK_XFRCM_Pos (0U) -#define DOEPMSK_XFRCM_Msk (0x1UL << DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */ -#define DOEPMSK_XFRCM DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */ +#define DOEPMSK_XFRCM_Msk (0x1UL << DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */ +#define DOEPMSK_XFRCM DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */ #define DOEPMSK_EPDM_Pos (1U) -#define DOEPMSK_EPDM_Msk (0x1UL << DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ -#define DOEPMSK_EPDM DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define DOEPMSK_EPDM_Msk (0x1UL << DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ +#define DOEPMSK_EPDM DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ #define DOEPMSK_AHBERRM_Pos (2U) -#define DOEPMSK_AHBERRM_Msk (0x1UL << DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ -#define DOEPMSK_AHBERRM DOEPMSK_AHBERRM_Msk /*!< OUT transaction AHB Error interrupt mask */ +#define DOEPMSK_AHBERRM_Msk (0x1UL << DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define DOEPMSK_AHBERRM DOEPMSK_AHBERRM_Msk /*!< OUT transaction AHB Error interrupt mask */ #define DOEPMSK_STUPM_Pos (3U) -#define DOEPMSK_STUPM_Msk (0x1UL << DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ -#define DOEPMSK_STUPM DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ +#define DOEPMSK_STUPM_Msk (0x1UL << DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ +#define DOEPMSK_STUPM DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ #define DOEPMSK_OTEPDM_Pos (4U) -#define DOEPMSK_OTEPDM_Msk (0x1UL << DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ -#define DOEPMSK_OTEPDM DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ +#define DOEPMSK_OTEPDM_Msk (0x1UL << DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ +#define DOEPMSK_OTEPDM DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ #define DOEPMSK_OTEPSPRM_Pos (5U) -#define DOEPMSK_OTEPSPRM_Msk (0x1UL << DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */ -#define DOEPMSK_OTEPSPRM DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */ +#define DOEPMSK_OTEPSPRM_Msk (0x1UL << DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */ +#define DOEPMSK_OTEPSPRM DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */ #define DOEPMSK_B2BSTUP_Pos (6U) -#define DOEPMSK_B2BSTUP_Msk (0x1UL << DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ -#define DOEPMSK_B2BSTUP DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ +#define DOEPMSK_B2BSTUP_Msk (0x1UL << DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ +#define DOEPMSK_B2BSTUP DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ #define DOEPMSK_OPEM_Pos (8U) -#define DOEPMSK_OPEM_Msk (0x1UL << DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ -#define DOEPMSK_OPEM DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ +#define DOEPMSK_OPEM_Msk (0x1UL << DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ +#define DOEPMSK_OPEM DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ #define DOEPMSK_BOIM_Pos (9U) -#define DOEPMSK_BOIM_Msk (0x1UL << DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ -#define DOEPMSK_BOIM DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ +#define DOEPMSK_BOIM_Msk (0x1UL << DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ +#define DOEPMSK_BOIM DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ #define DOEPMSK_BERRM_Pos (12U) -#define DOEPMSK_BERRM_Msk (0x1UL << DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ -#define DOEPMSK_BERRM DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ +#define DOEPMSK_BERRM_Msk (0x1UL << DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ +#define DOEPMSK_BERRM DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ #define DOEPMSK_NAKM_Pos (13U) -#define DOEPMSK_NAKM_Msk (0x1UL << DOEPMSK_NAKM_Pos) /*!< 0x00002000 */ -#define DOEPMSK_NAKM DOEPMSK_NAKM_Msk /*!< OUT Packet NAK interrupt mask */ +#define DOEPMSK_NAKM_Msk (0x1UL << DOEPMSK_NAKM_Pos) /*!< 0x00002000 */ +#define DOEPMSK_NAKM DOEPMSK_NAKM_Msk /*!< OUT Packet NAK interrupt mask */ #define DOEPMSK_NYETM_Pos (14U) -#define DOEPMSK_NYETM_Msk (0x1UL << DOEPMSK_NYETM_Pos) /*!< 0x00004000 */ -#define DOEPMSK_NYETM DOEPMSK_NYETM_Msk /*!< NYET interrupt mask */ +#define DOEPMSK_NYETM_Msk (0x1UL << DOEPMSK_NYETM_Pos) /*!< 0x00004000 */ +#define DOEPMSK_NYETM DOEPMSK_NYETM_Msk /*!< NYET interrupt mask */ /******************** Bit definition for GINTSTS register ********************/ #define GINTSTS_CMOD_Pos (0U) -#define GINTSTS_CMOD_Msk (0x1UL << GINTSTS_CMOD_Pos) /*!< 0x00000001 */ -#define GINTSTS_CMOD GINTSTS_CMOD_Msk /*!< Current mode of operation */ +#define GINTSTS_CMOD_Msk (0x1UL << GINTSTS_CMOD_Pos) /*!< 0x00000001 */ +#define GINTSTS_CMOD GINTSTS_CMOD_Msk /*!< Current mode of operation */ #define GINTSTS_MMIS_Pos (1U) -#define GINTSTS_MMIS_Msk (0x1UL << GINTSTS_MMIS_Pos) /*!< 0x00000002 */ -#define GINTSTS_MMIS GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */ +#define GINTSTS_MMIS_Msk (0x1UL << GINTSTS_MMIS_Pos) /*!< 0x00000002 */ +#define GINTSTS_MMIS GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */ #define GINTSTS_OTGINT_Pos (2U) -#define GINTSTS_OTGINT_Msk (0x1UL << GINTSTS_OTGINT_Pos) /*!< 0x00000004 */ -#define GINTSTS_OTGINT GINTSTS_OTGINT_Msk /*!< OTG interrupt */ +#define GINTSTS_OTGINT_Msk (0x1UL << GINTSTS_OTGINT_Pos) /*!< 0x00000004 */ +#define GINTSTS_OTGINT GINTSTS_OTGINT_Msk /*!< OTG interrupt */ #define GINTSTS_SOF_Pos (3U) -#define GINTSTS_SOF_Msk (0x1UL << GINTSTS_SOF_Pos) /*!< 0x00000008 */ -#define GINTSTS_SOF GINTSTS_SOF_Msk /*!< Start of frame */ +#define GINTSTS_SOF_Msk (0x1UL << GINTSTS_SOF_Pos) /*!< 0x00000008 */ +#define GINTSTS_SOF GINTSTS_SOF_Msk /*!< Start of frame */ #define GINTSTS_RXFLVL_Pos (4U) -#define GINTSTS_RXFLVL_Msk (0x1UL << GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */ -#define GINTSTS_RXFLVL GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */ +#define GINTSTS_RXFLVL_Msk (0x1UL << GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */ +#define GINTSTS_RXFLVL GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */ #define GINTSTS_NPTXFE_Pos (5U) -#define GINTSTS_NPTXFE_Msk (0x1UL << GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */ -#define GINTSTS_NPTXFE GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */ +#define GINTSTS_NPTXFE_Msk (0x1UL << GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */ +#define GINTSTS_NPTXFE GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */ #define GINTSTS_GINAKEFF_Pos (6U) -#define GINTSTS_GINAKEFF_Msk (0x1UL << GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ -#define GINTSTS_GINAKEFF GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ +#define GINTSTS_GINAKEFF_Msk (0x1UL << GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ +#define GINTSTS_GINAKEFF GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ #define GINTSTS_BOUTNAKEFF_Pos (7U) -#define GINTSTS_BOUTNAKEFF_Msk (0x1UL << GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ -#define GINTSTS_BOUTNAKEFF GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ +#define GINTSTS_BOUTNAKEFF_Msk (0x1UL << GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ +#define GINTSTS_BOUTNAKEFF GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ #define GINTSTS_ESUSP_Pos (10U) -#define GINTSTS_ESUSP_Msk (0x1UL << GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ -#define GINTSTS_ESUSP GINTSTS_ESUSP_Msk /*!< Early suspend */ +#define GINTSTS_ESUSP_Msk (0x1UL << GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ +#define GINTSTS_ESUSP GINTSTS_ESUSP_Msk /*!< Early suspend */ #define GINTSTS_USBSUSP_Pos (11U) -#define GINTSTS_USBSUSP_Msk (0x1UL << GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */ -#define GINTSTS_USBSUSP GINTSTS_USBSUSP_Msk /*!< USB suspend */ +#define GINTSTS_USBSUSP_Msk (0x1UL << GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */ +#define GINTSTS_USBSUSP GINTSTS_USBSUSP_Msk /*!< USB suspend */ #define GINTSTS_USBRST_Pos (12U) -#define GINTSTS_USBRST_Msk (0x1UL << GINTSTS_USBRST_Pos) /*!< 0x00001000 */ -#define GINTSTS_USBRST GINTSTS_USBRST_Msk /*!< USB reset */ +#define GINTSTS_USBRST_Msk (0x1UL << GINTSTS_USBRST_Pos) /*!< 0x00001000 */ +#define GINTSTS_USBRST GINTSTS_USBRST_Msk /*!< USB reset */ #define GINTSTS_ENUMDNE_Pos (13U) -#define GINTSTS_ENUMDNE_Msk (0x1UL << GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */ -#define GINTSTS_ENUMDNE GINTSTS_ENUMDNE_Msk /*!< Enumeration done */ +#define GINTSTS_ENUMDNE_Msk (0x1UL << GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */ +#define GINTSTS_ENUMDNE GINTSTS_ENUMDNE_Msk /*!< Enumeration done */ #define GINTSTS_ISOODRP_Pos (14U) -#define GINTSTS_ISOODRP_Msk (0x1UL << GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */ -#define GINTSTS_ISOODRP GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */ +#define GINTSTS_ISOODRP_Msk (0x1UL << GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */ +#define GINTSTS_ISOODRP GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */ #define GINTSTS_EOPF_Pos (15U) -#define GINTSTS_EOPF_Msk (0x1UL << GINTSTS_EOPF_Pos) /*!< 0x00008000 */ -#define GINTSTS_EOPF GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */ +#define GINTSTS_EOPF_Msk (0x1UL << GINTSTS_EOPF_Pos) /*!< 0x00008000 */ +#define GINTSTS_EOPF GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */ #define GINTSTS_IEPINT_Pos (18U) -#define GINTSTS_IEPINT_Msk (0x1UL << GINTSTS_IEPINT_Pos) /*!< 0x00040000 */ -#define GINTSTS_IEPINT GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */ +#define GINTSTS_IEPINT_Msk (0x1UL << GINTSTS_IEPINT_Pos) /*!< 0x00040000 */ +#define GINTSTS_IEPINT GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */ #define GINTSTS_OEPINT_Pos (19U) -#define GINTSTS_OEPINT_Msk (0x1UL << GINTSTS_OEPINT_Pos) /*!< 0x00080000 */ -#define GINTSTS_OEPINT GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */ +#define GINTSTS_OEPINT_Msk (0x1UL << GINTSTS_OEPINT_Pos) /*!< 0x00080000 */ +#define GINTSTS_OEPINT GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */ #define GINTSTS_IISOIXFR_Pos (20U) -#define GINTSTS_IISOIXFR_Msk (0x1UL << GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */ -#define GINTSTS_IISOIXFR GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */ +#define GINTSTS_IISOIXFR_Msk (0x1UL << GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */ +#define GINTSTS_IISOIXFR GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */ #define GINTSTS_PXFR_INCOMPISOOUT_Pos (21U) #define GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */ -#define GINTSTS_PXFR_INCOMPISOOUT GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */ +#define GINTSTS_PXFR_INCOMPISOOUT GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */ #define GINTSTS_DATAFSUSP_Pos (22U) -#define GINTSTS_DATAFSUSP_Msk (0x1UL << GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ -#define GINTSTS_DATAFSUSP GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ +#define GINTSTS_DATAFSUSP_Msk (0x1UL << GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ +#define GINTSTS_DATAFSUSP GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ #define GINTSTS_RSTDET_Pos (23U) -#define GINTSTS_RSTDET_Msk (0x1UL << GINTSTS_RSTDET_Pos) /*!< 0x00800000 */ -#define GINTSTS_RSTDET GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */ +#define GINTSTS_RSTDET_Msk (0x1UL << GINTSTS_RSTDET_Pos) /*!< 0x00800000 */ +#define GINTSTS_RSTDET GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */ #define GINTSTS_HPRTINT_Pos (24U) -#define GINTSTS_HPRTINT_Msk (0x1UL << GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ -#define GINTSTS_HPRTINT GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ +#define GINTSTS_HPRTINT_Msk (0x1UL << GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ +#define GINTSTS_HPRTINT GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ #define GINTSTS_HCINT_Pos (25U) -#define GINTSTS_HCINT_Msk (0x1UL << GINTSTS_HCINT_Pos) /*!< 0x02000000 */ -#define GINTSTS_HCINT GINTSTS_HCINT_Msk /*!< Host channels interrupt */ +#define GINTSTS_HCINT_Msk (0x1UL << GINTSTS_HCINT_Pos) /*!< 0x02000000 */ +#define GINTSTS_HCINT GINTSTS_HCINT_Msk /*!< Host channels interrupt */ #define GINTSTS_PTXFE_Pos (26U) -#define GINTSTS_PTXFE_Msk (0x1UL << GINTSTS_PTXFE_Pos) /*!< 0x04000000 */ -#define GINTSTS_PTXFE GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */ +#define GINTSTS_PTXFE_Msk (0x1UL << GINTSTS_PTXFE_Pos) /*!< 0x04000000 */ +#define GINTSTS_PTXFE GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */ #define GINTSTS_LPMINT_Pos (27U) -#define GINTSTS_LPMINT_Msk (0x1UL << GINTSTS_LPMINT_Pos) /*!< 0x08000000 */ -#define GINTSTS_LPMINT GINTSTS_LPMINT_Msk /*!< LPM interrupt */ +#define GINTSTS_LPMINT_Msk (0x1UL << GINTSTS_LPMINT_Pos) /*!< 0x08000000 */ +#define GINTSTS_LPMINT GINTSTS_LPMINT_Msk /*!< LPM interrupt */ #define GINTSTS_CIDSCHG_Pos (28U) -#define GINTSTS_CIDSCHG_Msk (0x1UL << GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */ -#define GINTSTS_CIDSCHG GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */ +#define GINTSTS_CIDSCHG_Msk (0x1UL << GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */ +#define GINTSTS_CIDSCHG GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */ #define GINTSTS_DISCINT_Pos (29U) -#define GINTSTS_DISCINT_Msk (0x1UL << GINTSTS_DISCINT_Pos) /*!< 0x20000000 */ -#define GINTSTS_DISCINT GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */ +#define GINTSTS_DISCINT_Msk (0x1UL << GINTSTS_DISCINT_Pos) /*!< 0x20000000 */ +#define GINTSTS_DISCINT GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */ #define GINTSTS_SRQINT_Pos (30U) -#define GINTSTS_SRQINT_Msk (0x1UL << GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ -#define GINTSTS_SRQINT GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ +#define GINTSTS_SRQINT_Msk (0x1UL << GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ +#define GINTSTS_SRQINT GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ #define GINTSTS_WKUINT_Pos (31U) -#define GINTSTS_WKUINT_Msk (0x1UL << GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ -#define GINTSTS_WKUINT GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ +#define GINTSTS_WKUINT_Msk (0x1UL << GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ +#define GINTSTS_WKUINT GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ /******************** Bit definition for GINTMSK register ********************/ #define GINTMSK_MMISM_Pos (1U) -#define GINTMSK_MMISM_Msk (0x1UL << GINTMSK_MMISM_Pos) /*!< 0x00000002 */ -#define GINTMSK_MMISM GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */ +#define GINTMSK_MMISM_Msk (0x1UL << GINTMSK_MMISM_Pos) /*!< 0x00000002 */ +#define GINTMSK_MMISM GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */ #define GINTMSK_OTGINT_Pos (2U) -#define GINTMSK_OTGINT_Msk (0x1UL << GINTMSK_OTGINT_Pos) /*!< 0x00000004 */ -#define GINTMSK_OTGINT GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */ +#define GINTMSK_OTGINT_Msk (0x1UL << GINTMSK_OTGINT_Pos) /*!< 0x00000004 */ +#define GINTMSK_OTGINT GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */ #define GINTMSK_SOFM_Pos (3U) -#define GINTMSK_SOFM_Msk (0x1UL << GINTMSK_SOFM_Pos) /*!< 0x00000008 */ -#define GINTMSK_SOFM GINTMSK_SOFM_Msk /*!< Start of frame mask */ +#define GINTMSK_SOFM_Msk (0x1UL << GINTMSK_SOFM_Pos) /*!< 0x00000008 */ +#define GINTMSK_SOFM GINTMSK_SOFM_Msk /*!< Start of frame mask */ #define GINTMSK_RXFLVLM_Pos (4U) -#define GINTMSK_RXFLVLM_Msk (0x1UL << GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */ -#define GINTMSK_RXFLVLM GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */ +#define GINTMSK_RXFLVLM_Msk (0x1UL << GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */ +#define GINTMSK_RXFLVLM GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */ #define GINTMSK_NPTXFEM_Pos (5U) -#define GINTMSK_NPTXFEM_Msk (0x1UL << GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */ -#define GINTMSK_NPTXFEM GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */ +#define GINTMSK_NPTXFEM_Msk (0x1UL << GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */ +#define GINTMSK_NPTXFEM GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */ #define GINTMSK_GINAKEFFM_Pos (6U) -#define GINTMSK_GINAKEFFM_Msk (0x1UL << GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */ -#define GINTMSK_GINAKEFFM GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */ +#define GINTMSK_GINAKEFFM_Msk (0x1UL << GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */ +#define GINTMSK_GINAKEFFM GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */ #define GINTMSK_GONAKEFFM_Pos (7U) -#define GINTMSK_GONAKEFFM_Msk (0x1UL << GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */ -#define GINTMSK_GONAKEFFM GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */ +#define GINTMSK_GONAKEFFM_Msk (0x1UL << GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */ +#define GINTMSK_GONAKEFFM GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */ #define GINTMSK_ESUSPM_Pos (10U) -#define GINTMSK_ESUSPM_Msk (0x1UL << GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */ -#define GINTMSK_ESUSPM GINTMSK_ESUSPM_Msk /*!< Early suspend mask */ +#define GINTMSK_ESUSPM_Msk (0x1UL << GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */ +#define GINTMSK_ESUSPM GINTMSK_ESUSPM_Msk /*!< Early suspend mask */ #define GINTMSK_USBSUSPM_Pos (11U) -#define GINTMSK_USBSUSPM_Msk (0x1UL << GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */ -#define GINTMSK_USBSUSPM GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */ +#define GINTMSK_USBSUSPM_Msk (0x1UL << GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */ +#define GINTMSK_USBSUSPM GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */ #define GINTMSK_USBRST_Pos (12U) -#define GINTMSK_USBRST_Msk (0x1UL << GINTMSK_USBRST_Pos) /*!< 0x00001000 */ -#define GINTMSK_USBRST GINTMSK_USBRST_Msk /*!< USB reset mask */ +#define GINTMSK_USBRST_Msk (0x1UL << GINTMSK_USBRST_Pos) /*!< 0x00001000 */ +#define GINTMSK_USBRST GINTMSK_USBRST_Msk /*!< USB reset mask */ #define GINTMSK_ENUMDNEM_Pos (13U) -#define GINTMSK_ENUMDNEM_Msk (0x1UL << GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */ -#define GINTMSK_ENUMDNEM GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */ +#define GINTMSK_ENUMDNEM_Msk (0x1UL << GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */ +#define GINTMSK_ENUMDNEM GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */ #define GINTMSK_ISOODRPM_Pos (14U) -#define GINTMSK_ISOODRPM_Msk (0x1UL << GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */ -#define GINTMSK_ISOODRPM GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */ +#define GINTMSK_ISOODRPM_Msk (0x1UL << GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */ +#define GINTMSK_ISOODRPM GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */ #define GINTMSK_EOPFM_Pos (15U) -#define GINTMSK_EOPFM_Msk (0x1UL << GINTMSK_EOPFM_Pos) /*!< 0x00008000 */ -#define GINTMSK_EOPFM GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */ +#define GINTMSK_EOPFM_Msk (0x1UL << GINTMSK_EOPFM_Pos) /*!< 0x00008000 */ +#define GINTMSK_EOPFM GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */ #define GINTMSK_EPMISM_Pos (17U) -#define GINTMSK_EPMISM_Msk (0x1UL << GINTMSK_EPMISM_Pos) /*!< 0x00020000 */ -#define GINTMSK_EPMISM GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */ +#define GINTMSK_EPMISM_Msk (0x1UL << GINTMSK_EPMISM_Pos) /*!< 0x00020000 */ +#define GINTMSK_EPMISM GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */ #define GINTMSK_IEPINT_Pos (18U) -#define GINTMSK_IEPINT_Msk (0x1UL << GINTMSK_IEPINT_Pos) /*!< 0x00040000 */ -#define GINTMSK_IEPINT GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */ +#define GINTMSK_IEPINT_Msk (0x1UL << GINTMSK_IEPINT_Pos) /*!< 0x00040000 */ +#define GINTMSK_IEPINT GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */ #define GINTMSK_OEPINT_Pos (19U) -#define GINTMSK_OEPINT_Msk (0x1UL << GINTMSK_OEPINT_Pos) /*!< 0x00080000 */ -#define GINTMSK_OEPINT GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */ +#define GINTMSK_OEPINT_Msk (0x1UL << GINTMSK_OEPINT_Pos) /*!< 0x00080000 */ +#define GINTMSK_OEPINT GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */ #define GINTMSK_IISOIXFRM_Pos (20U) -#define GINTMSK_IISOIXFRM_Msk (0x1UL << GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ -#define GINTMSK_IISOIXFRM GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ +#define GINTMSK_IISOIXFRM_Msk (0x1UL << GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ +#define GINTMSK_IISOIXFRM GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ #define GINTMSK_PXFRM_IISOOXFRM_Pos (21U) -#define GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ -#define GINTMSK_PXFRM_IISOOXFRM GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ +#define GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ +#define GINTMSK_PXFRM_IISOOXFRM GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ #define GINTMSK_FSUSPM_Pos (22U) -#define GINTMSK_FSUSPM_Msk (0x1UL << GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ -#define GINTMSK_FSUSPM GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ +#define GINTMSK_FSUSPM_Msk (0x1UL << GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ +#define GINTMSK_FSUSPM GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ #define GINTMSK_RSTDEM_Pos (23U) -#define GINTMSK_RSTDEM_Msk (0x1UL << GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */ -#define GINTMSK_RSTDEM GINTMSK_RSTDEM_Msk /*!< Reset detected interrupt mask */ +#define GINTMSK_RSTDEM_Msk (0x1UL << GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */ +#define GINTMSK_RSTDEM GINTMSK_RSTDEM_Msk /*!< Reset detected interrupt mask */ #define GINTMSK_PRTIM_Pos (24U) -#define GINTMSK_PRTIM_Msk (0x1UL << GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ -#define GINTMSK_PRTIM GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ +#define GINTMSK_PRTIM_Msk (0x1UL << GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ +#define GINTMSK_PRTIM GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ #define GINTMSK_HCIM_Pos (25U) -#define GINTMSK_HCIM_Msk (0x1UL << GINTMSK_HCIM_Pos) /*!< 0x02000000 */ -#define GINTMSK_HCIM GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */ +#define GINTMSK_HCIM_Msk (0x1UL << GINTMSK_HCIM_Pos) /*!< 0x02000000 */ +#define GINTMSK_HCIM GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */ #define GINTMSK_PTXFEM_Pos (26U) -#define GINTMSK_PTXFEM_Msk (0x1UL << GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */ -#define GINTMSK_PTXFEM GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */ +#define GINTMSK_PTXFEM_Msk (0x1UL << GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */ +#define GINTMSK_PTXFEM GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */ #define GINTMSK_LPMINTM_Pos (27U) -#define GINTMSK_LPMINTM_Msk (0x1UL << GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */ -#define GINTMSK_LPMINTM GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */ +#define GINTMSK_LPMINTM_Msk (0x1UL << GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */ +#define GINTMSK_LPMINTM GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */ #define GINTMSK_CIDSCHGM_Pos (28U) -#define GINTMSK_CIDSCHGM_Msk (0x1UL << GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */ -#define GINTMSK_CIDSCHGM GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */ +#define GINTMSK_CIDSCHGM_Msk (0x1UL << GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */ +#define GINTMSK_CIDSCHGM GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */ #define GINTMSK_DISCINT_Pos (29U) -#define GINTMSK_DISCINT_Msk (0x1UL << GINTMSK_DISCINT_Pos) /*!< 0x20000000 */ -#define GINTMSK_DISCINT GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */ +#define GINTMSK_DISCINT_Msk (0x1UL << GINTMSK_DISCINT_Pos) /*!< 0x20000000 */ +#define GINTMSK_DISCINT GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */ #define GINTMSK_SRQIM_Pos (30U) -#define GINTMSK_SRQIM_Msk (0x1UL << GINTMSK_SRQIM_Pos) /*!< 0x40000000 */ -#define GINTMSK_SRQIM GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */ +#define GINTMSK_SRQIM_Msk (0x1UL << GINTMSK_SRQIM_Pos) /*!< 0x40000000 */ +#define GINTMSK_SRQIM GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */ #define GINTMSK_WUIM_Pos (31U) -#define GINTMSK_WUIM_Msk (0x1UL << GINTMSK_WUIM_Pos) /*!< 0x80000000 */ -#define GINTMSK_WUIM GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */ +#define GINTMSK_WUIM_Msk (0x1UL << GINTMSK_WUIM_Pos) /*!< 0x80000000 */ +#define GINTMSK_WUIM GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */ /******************** Bit definition for DAINT register ********************/ #define DAINT_IEPINT_Pos (0U) -#define DAINT_IEPINT_Msk (0xFFFFUL << DAINT_IEPINT_Pos) /*!< 0x0000FFFF */ -#define DAINT_IEPINT DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */ +#define DAINT_IEPINT_Msk (0xFFFFUL << DAINT_IEPINT_Pos) /*!< 0x0000FFFF */ +#define DAINT_IEPINT DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */ #define DAINT_OEPINT_Pos (16U) -#define DAINT_OEPINT_Msk (0xFFFFUL << DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */ -#define DAINT_OEPINT DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */ +#define DAINT_OEPINT_Msk (0xFFFFUL << DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */ +#define DAINT_OEPINT DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */ /******************** Bit definition for HAINTMSK register ********************/ #define HAINTMSK_HAINTM_Pos (0U) -#define HAINTMSK_HAINTM_Msk (0xFFFFUL << HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ -#define HAINTMSK_HAINTM HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ +#define HAINTMSK_HAINTM_Msk (0xFFFFUL << HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ +#define HAINTMSK_HAINTM HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ /******************** Bit definition for GRXSTSP register ********************/ #define GRXSTSP_EPNUM_Pos (0U) -#define GRXSTSP_EPNUM_Msk (0xFUL << GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ -#define GRXSTSP_EPNUM GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ +#define GRXSTSP_EPNUM_Msk (0xFUL << GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ +#define GRXSTSP_EPNUM GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ #define GRXSTSP_BCNT_Pos (4U) -#define GRXSTSP_BCNT_Msk (0x7FFUL << GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ -#define GRXSTSP_BCNT GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ +#define GRXSTSP_BCNT_Msk (0x7FFUL << GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ +#define GRXSTSP_BCNT GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ #define GRXSTSP_DPID_Pos (15U) -#define GRXSTSP_DPID_Msk (0x3UL << GRXSTSP_DPID_Pos) /*!< 0x00018000 */ -#define GRXSTSP_DPID GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ +#define GRXSTSP_DPID_Msk (0x3UL << GRXSTSP_DPID_Pos) /*!< 0x00018000 */ +#define GRXSTSP_DPID GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ #define GRXSTSP_PKTSTS_Pos (17U) -#define GRXSTSP_PKTSTS_Msk (0xFUL << GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ -#define GRXSTSP_PKTSTS GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ +#define GRXSTSP_PKTSTS_Msk (0xFUL << GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ +#define GRXSTSP_PKTSTS GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ /******************** Bit definition for DAINTMSK register ********************/ #define DAINTMSK_IEPM_Pos (0U) -#define DAINTMSK_IEPM_Msk (0xFFFFUL << DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */ -#define DAINTMSK_IEPM DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */ +#define DAINTMSK_IEPM_Msk (0xFFFFUL << DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */ +#define DAINTMSK_IEPM DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */ #define DAINTMSK_OEPM_Pos (16U) -#define DAINTMSK_OEPM_Msk (0xFFFFUL << DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */ -#define DAINTMSK_OEPM DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */ +#define DAINTMSK_OEPM_Msk (0xFFFFUL << DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */ +#define DAINTMSK_OEPM DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */ /******************** Bit definition for OTG register ********************/ - #define CHNUM_Pos (0U) -#define CHNUM_Msk (0xFUL << CHNUM_Pos) /*!< 0x0000000F */ -#define CHNUM CHNUM_Msk /*!< Channel number */ -#define CHNUM_0 (0x1UL << CHNUM_Pos) /*!< 0x00000001 */ -#define CHNUM_1 (0x2UL << CHNUM_Pos) /*!< 0x00000002 */ -#define CHNUM_2 (0x4UL << CHNUM_Pos) /*!< 0x00000004 */ -#define CHNUM_3 (0x8UL << CHNUM_Pos) /*!< 0x00000008 */ +#define CHNUM_Msk (0xFUL << CHNUM_Pos) /*!< 0x0000000F */ +#define CHNUM CHNUM_Msk /*!< Channel number */ +#define CHNUM_0 (0x1UL << CHNUM_Pos) /*!< 0x00000001 */ +#define CHNUM_1 (0x2UL << CHNUM_Pos) /*!< 0x00000002 */ +#define CHNUM_2 (0x4UL << CHNUM_Pos) /*!< 0x00000004 */ +#define CHNUM_3 (0x8UL << CHNUM_Pos) /*!< 0x00000008 */ #define BCNT_Pos (4U) -#define BCNT_Msk (0x7FFUL << BCNT_Pos) /*!< 0x00007FF0 */ -#define BCNT BCNT_Msk /*!< Byte count */ +#define BCNT_Msk (0x7FFUL << BCNT_Pos) /*!< 0x00007FF0 */ +#define BCNT BCNT_Msk /*!< Byte count */ #define DPID_Pos (15U) -#define DPID_Msk (0x3UL << DPID_Pos) /*!< 0x00018000 */ -#define DPID DPID_Msk /*!< Data PID */ -#define DPID_0 (0x1UL << DPID_Pos) /*!< 0x00008000 */ -#define DPID_1 (0x2UL << DPID_Pos) /*!< 0x00010000 */ +#define DPID_Msk (0x3UL << DPID_Pos) /*!< 0x00018000 */ +#define DPID DPID_Msk /*!< Data PID */ +#define DPID_0 (0x1UL << DPID_Pos) /*!< 0x00008000 */ +#define DPID_1 (0x2UL << DPID_Pos) /*!< 0x00010000 */ #define PKTSTS_Pos (17U) -#define PKTSTS_Msk (0xFUL << PKTSTS_Pos) /*!< 0x001E0000 */ -#define PKTSTS PKTSTS_Msk /*!< Packet status */ -#define PKTSTS_0 (0x1UL << PKTSTS_Pos) /*!< 0x00020000 */ -#define PKTSTS_1 (0x2UL << PKTSTS_Pos) /*!< 0x00040000 */ -#define PKTSTS_2 (0x4UL << PKTSTS_Pos) /*!< 0x00080000 */ -#define PKTSTS_3 (0x8UL << PKTSTS_Pos) /*!< 0x00100000 */ +#define PKTSTS_Msk (0xFUL << PKTSTS_Pos) /*!< 0x001E0000 */ +#define PKTSTS PKTSTS_Msk /*!< Packet status */ +#define PKTSTS_0 (0x1UL << PKTSTS_Pos) /*!< 0x00020000 */ +#define PKTSTS_1 (0x2UL << PKTSTS_Pos) /*!< 0x00040000 */ +#define PKTSTS_2 (0x4UL << PKTSTS_Pos) /*!< 0x00080000 */ +#define PKTSTS_3 (0x8UL << PKTSTS_Pos) /*!< 0x00100000 */ #define EPNUM_Pos (0U) -#define EPNUM_Msk (0xFUL << EPNUM_Pos) /*!< 0x0000000F */ -#define EPNUM EPNUM_Msk /*!< Endpoint number */ -#define EPNUM_0 (0x1UL << EPNUM_Pos) /*!< 0x00000001 */ -#define EPNUM_1 (0x2UL << EPNUM_Pos) /*!< 0x00000002 */ -#define EPNUM_2 (0x4UL << EPNUM_Pos) /*!< 0x00000004 */ -#define EPNUM_3 (0x8UL << EPNUM_Pos) /*!< 0x00000008 */ +#define EPNUM_Msk (0xFUL << EPNUM_Pos) /*!< 0x0000000F */ +#define EPNUM EPNUM_Msk /*!< Endpoint number */ +#define EPNUM_0 (0x1UL << EPNUM_Pos) /*!< 0x00000001 */ +#define EPNUM_1 (0x2UL << EPNUM_Pos) /*!< 0x00000002 */ +#define EPNUM_2 (0x4UL << EPNUM_Pos) /*!< 0x00000004 */ +#define EPNUM_3 (0x8UL << EPNUM_Pos) /*!< 0x00000008 */ #define FRMNUM_Pos (21U) -#define FRMNUM_Msk (0xFUL << FRMNUM_Pos) /*!< 0x01E00000 */ -#define FRMNUM FRMNUM_Msk /*!< Frame number */ -#define FRMNUM_0 (0x1UL << FRMNUM_Pos) /*!< 0x00200000 */ -#define FRMNUM_1 (0x2UL << FRMNUM_Pos) /*!< 0x00400000 */ -#define FRMNUM_2 (0x4UL << FRMNUM_Pos) /*!< 0x00800000 */ -#define FRMNUM_3 (0x8UL << FRMNUM_Pos) /*!< 0x01000000 */ +#define FRMNUM_Msk (0xFUL << FRMNUM_Pos) /*!< 0x01E00000 */ +#define FRMNUM FRMNUM_Msk /*!< Frame number */ +#define FRMNUM_0 (0x1UL << FRMNUM_Pos) /*!< 0x00200000 */ +#define FRMNUM_1 (0x2UL << FRMNUM_Pos) /*!< 0x00400000 */ +#define FRMNUM_2 (0x4UL << FRMNUM_Pos) /*!< 0x00800000 */ +#define FRMNUM_3 (0x8UL << FRMNUM_Pos) /*!< 0x01000000 */ /******************** Bit definition for GRXFSIZ register ********************/ #define GRXFSIZ_RXFD_Pos (0U) -#define GRXFSIZ_RXFD_Msk (0xFFFFUL << GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */ -#define GRXFSIZ_RXFD GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */ +#define GRXFSIZ_RXFD_Msk (0xFFFFUL << GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */ +#define GRXFSIZ_RXFD GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */ /******************** Bit definition for DVBUSDIS register ********************/ #define DVBUSDIS_VBUSDT_Pos (0U) -#define DVBUSDIS_VBUSDT_Msk (0xFFFFUL << DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */ -#define DVBUSDIS_VBUSDT DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */ +#define DVBUSDIS_VBUSDT_Msk (0xFFFFUL << DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */ +#define DVBUSDIS_VBUSDT DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */ /******************** Bit definition for OTG register ********************/ #define NPTXFSA_Pos (0U) -#define NPTXFSA_Msk (0xFFFFUL << NPTXFSA_Pos) /*!< 0x0000FFFF */ -#define NPTXFSA NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */ +#define NPTXFSA_Msk (0xFFFFUL << NPTXFSA_Pos) /*!< 0x0000FFFF */ +#define NPTXFSA NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */ #define NPTXFD_Pos (16U) -#define NPTXFD_Msk (0xFFFFUL << NPTXFD_Pos) /*!< 0xFFFF0000 */ -#define NPTXFD NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */ +#define NPTXFD_Msk (0xFFFFUL << NPTXFD_Pos) /*!< 0xFFFF0000 */ +#define NPTXFD NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */ #define TX0FSA_Pos (0U) -#define TX0FSA_Msk (0xFFFFUL << TX0FSA_Pos) /*!< 0x0000FFFF */ -#define TX0FSA TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */ +#define TX0FSA_Msk (0xFFFFUL << TX0FSA_Pos) /*!< 0x0000FFFF */ +#define TX0FSA TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */ #define TX0FD_Pos (16U) -#define TX0FD_Msk (0xFFFFUL << TX0FD_Pos) /*!< 0xFFFF0000 */ -#define TX0FD TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */ +#define TX0FD_Msk (0xFFFFUL << TX0FD_Pos) /*!< 0xFFFF0000 */ +#define TX0FD TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */ /******************** Bit definition for DVBUSPULSE register ********************/ #define DVBUSPULSE_DVBUSP_Pos (0U) -#define DVBUSPULSE_DVBUSP_Msk (0xFFFUL << DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */ -#define DVBUSPULSE_DVBUSP DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */ +#define DVBUSPULSE_DVBUSP_Msk (0xFFFUL << DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */ +#define DVBUSPULSE_DVBUSP DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */ /******************** Bit definition for GNPTXSTS register ********************/ #define GNPTXSTS_NPTXFSAV_Pos (0U) -#define GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */ -#define GNPTXSTS_NPTXFSAV GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */ +#define GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */ +#define GNPTXSTS_NPTXFSAV GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */ #define GNPTXSTS_NPTQXSAV_Pos (16U) -#define GNPTXSTS_NPTQXSAV_Msk (0xFFUL << GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */ -#define GNPTXSTS_NPTQXSAV GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */ -#define GNPTXSTS_NPTQXSAV_0 (0x01UL << GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */ -#define GNPTXSTS_NPTQXSAV_1 (0x02UL << GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */ -#define GNPTXSTS_NPTQXSAV_2 (0x04UL << GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */ -#define GNPTXSTS_NPTQXSAV_3 (0x08UL << GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */ -#define GNPTXSTS_NPTQXSAV_4 (0x10UL << GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */ -#define GNPTXSTS_NPTQXSAV_5 (0x20UL << GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */ -#define GNPTXSTS_NPTQXSAV_6 (0x40UL << GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */ -#define GNPTXSTS_NPTQXSAV_7 (0x80UL << GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */ +#define GNPTXSTS_NPTQXSAV_Msk (0xFFUL << GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */ +#define GNPTXSTS_NPTQXSAV GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */ +#define GNPTXSTS_NPTQXSAV_0 (0x01UL << GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */ +#define GNPTXSTS_NPTQXSAV_1 (0x02UL << GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */ +#define GNPTXSTS_NPTQXSAV_2 (0x04UL << GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */ +#define GNPTXSTS_NPTQXSAV_3 (0x08UL << GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */ +#define GNPTXSTS_NPTQXSAV_4 (0x10UL << GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */ +#define GNPTXSTS_NPTQXSAV_5 (0x20UL << GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */ +#define GNPTXSTS_NPTQXSAV_6 (0x40UL << GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */ +#define GNPTXSTS_NPTQXSAV_7 (0x80UL << GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */ #define GNPTXSTS_NPTXQTOP_Pos (24U) -#define GNPTXSTS_NPTXQTOP_Msk (0x7FUL << GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */ -#define GNPTXSTS_NPTXQTOP GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */ -#define GNPTXSTS_NPTXQTOP_0 (0x01UL << GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */ -#define GNPTXSTS_NPTXQTOP_1 (0x02UL << GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */ -#define GNPTXSTS_NPTXQTOP_2 (0x04UL << GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */ -#define GNPTXSTS_NPTXQTOP_3 (0x08UL << GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */ -#define GNPTXSTS_NPTXQTOP_4 (0x10UL << GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */ -#define GNPTXSTS_NPTXQTOP_5 (0x20UL << GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */ -#define GNPTXSTS_NPTXQTOP_6 (0x40UL << GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */ +#define GNPTXSTS_NPTXQTOP_Msk (0x7FUL << GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */ +#define GNPTXSTS_NPTXQTOP GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */ +#define GNPTXSTS_NPTXQTOP_0 (0x01UL << GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */ +#define GNPTXSTS_NPTXQTOP_1 (0x02UL << GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */ +#define GNPTXSTS_NPTXQTOP_2 (0x04UL << GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */ +#define GNPTXSTS_NPTXQTOP_3 (0x08UL << GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */ +#define GNPTXSTS_NPTXQTOP_4 (0x10UL << GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */ +#define GNPTXSTS_NPTXQTOP_5 (0x20UL << GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */ +#define GNPTXSTS_NPTXQTOP_6 (0x40UL << GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */ /******************** Bit definition for DTHRCTL register ********************/ #define DTHRCTL_NONISOTHREN_Pos (0U) -#define DTHRCTL_NONISOTHREN_Msk (0x1UL << DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */ -#define DTHRCTL_NONISOTHREN DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */ +#define DTHRCTL_NONISOTHREN_Msk (0x1UL << DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */ +#define DTHRCTL_NONISOTHREN DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */ #define DTHRCTL_ISOTHREN_Pos (1U) -#define DTHRCTL_ISOTHREN_Msk (0x1UL << DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */ -#define DTHRCTL_ISOTHREN DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */ +#define DTHRCTL_ISOTHREN_Msk (0x1UL << DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */ +#define DTHRCTL_ISOTHREN DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */ #define DTHRCTL_TXTHRLEN_Pos (2U) -#define DTHRCTL_TXTHRLEN_Msk (0x1FFUL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */ -#define DTHRCTL_TXTHRLEN DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */ -#define DTHRCTL_TXTHRLEN_0 (0x001UL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */ -#define DTHRCTL_TXTHRLEN_1 (0x002UL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */ -#define DTHRCTL_TXTHRLEN_2 (0x004UL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */ -#define DTHRCTL_TXTHRLEN_3 (0x008UL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */ -#define DTHRCTL_TXTHRLEN_4 (0x010UL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */ -#define DTHRCTL_TXTHRLEN_5 (0x020UL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */ -#define DTHRCTL_TXTHRLEN_6 (0x040UL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */ -#define DTHRCTL_TXTHRLEN_7 (0x080UL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */ -#define DTHRCTL_TXTHRLEN_8 (0x100UL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */ +#define DTHRCTL_TXTHRLEN_Msk (0x1FFUL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */ +#define DTHRCTL_TXTHRLEN DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */ +#define DTHRCTL_TXTHRLEN_0 (0x001UL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */ +#define DTHRCTL_TXTHRLEN_1 (0x002UL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */ +#define DTHRCTL_TXTHRLEN_2 (0x004UL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */ +#define DTHRCTL_TXTHRLEN_3 (0x008UL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */ +#define DTHRCTL_TXTHRLEN_4 (0x010UL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */ +#define DTHRCTL_TXTHRLEN_5 (0x020UL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */ +#define DTHRCTL_TXTHRLEN_6 (0x040UL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */ +#define DTHRCTL_TXTHRLEN_7 (0x080UL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */ +#define DTHRCTL_TXTHRLEN_8 (0x100UL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */ #define DTHRCTL_RXTHREN_Pos (16U) -#define DTHRCTL_RXTHREN_Msk (0x1UL << DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */ -#define DTHRCTL_RXTHREN DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */ +#define DTHRCTL_RXTHREN_Msk (0x1UL << DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */ +#define DTHRCTL_RXTHREN DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */ #define DTHRCTL_RXTHRLEN_Pos (17U) -#define DTHRCTL_RXTHRLEN_Msk (0x1FFUL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */ -#define DTHRCTL_RXTHRLEN DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */ -#define DTHRCTL_RXTHRLEN_0 (0x001UL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */ -#define DTHRCTL_RXTHRLEN_1 (0x002UL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */ -#define DTHRCTL_RXTHRLEN_2 (0x004UL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */ -#define DTHRCTL_RXTHRLEN_3 (0x008UL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */ -#define DTHRCTL_RXTHRLEN_4 (0x010UL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */ -#define DTHRCTL_RXTHRLEN_5 (0x020UL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */ -#define DTHRCTL_RXTHRLEN_6 (0x040UL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */ -#define DTHRCTL_RXTHRLEN_7 (0x080UL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */ -#define DTHRCTL_RXTHRLEN_8 (0x100UL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */ +#define DTHRCTL_RXTHRLEN_Msk (0x1FFUL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */ +#define DTHRCTL_RXTHRLEN DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */ +#define DTHRCTL_RXTHRLEN_0 (0x001UL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */ +#define DTHRCTL_RXTHRLEN_1 (0x002UL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */ +#define DTHRCTL_RXTHRLEN_2 (0x004UL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */ +#define DTHRCTL_RXTHRLEN_3 (0x008UL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */ +#define DTHRCTL_RXTHRLEN_4 (0x010UL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */ +#define DTHRCTL_RXTHRLEN_5 (0x020UL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */ +#define DTHRCTL_RXTHRLEN_6 (0x040UL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */ +#define DTHRCTL_RXTHRLEN_7 (0x080UL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */ +#define DTHRCTL_RXTHRLEN_8 (0x100UL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */ #define DTHRCTL_ARPEN_Pos (27U) -#define DTHRCTL_ARPEN_Msk (0x1UL << DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */ -#define DTHRCTL_ARPEN DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */ +#define DTHRCTL_ARPEN_Msk (0x1UL << DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */ +#define DTHRCTL_ARPEN DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */ /******************** Bit definition for DIEPEMPMSK register ********************/ #define DIEPEMPMSK_INEPTXFEM_Pos (0U) -#define DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */ -#define DIEPEMPMSK_INEPTXFEM DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */ +#define DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */ +#define DIEPEMPMSK_INEPTXFEM DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */ /******************** Bit definition for DEACHINT register ********************/ #define DEACHINT_IEP1INT_Pos (1U) -#define DEACHINT_IEP1INT_Msk (0x1UL << DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */ -#define DEACHINT_IEP1INT DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */ +#define DEACHINT_IEP1INT_Msk (0x1UL << DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */ +#define DEACHINT_IEP1INT DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */ #define DEACHINT_OEP1INT_Pos (17U) -#define DEACHINT_OEP1INT_Msk (0x1UL << DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */ -#define DEACHINT_OEP1INT DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */ +#define DEACHINT_OEP1INT_Msk (0x1UL << DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */ +#define DEACHINT_OEP1INT DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */ /******************** Bit definition for GCCFG register ********************/ #define GCCFG_DCDET_Pos (0U) -#define GCCFG_DCDET_Msk (0x1UL << GCCFG_DCDET_Pos) /*!< 0x00000001 */ -#define GCCFG_DCDET GCCFG_DCDET_Msk /*!< Data contact detection (DCD) status */ +#define GCCFG_DCDET_Msk (0x1UL << GCCFG_DCDET_Pos) /*!< 0x00000001 */ +#define GCCFG_DCDET GCCFG_DCDET_Msk /*!< Data contact detection (DCD) status */ #define GCCFG_PDET_Pos (1U) -#define GCCFG_PDET_Msk (0x1UL << GCCFG_PDET_Pos) /*!< 0x00000002 */ -#define GCCFG_PDET GCCFG_PDET_Msk /*!< Primary detection (PD) status */ +#define GCCFG_PDET_Msk (0x1UL << GCCFG_PDET_Pos) /*!< 0x00000002 */ +#define GCCFG_PDET GCCFG_PDET_Msk /*!< Primary detection (PD) status */ #define GCCFG_SDET_Pos (2U) -#define GCCFG_SDET_Msk (0x1UL << GCCFG_SDET_Pos) /*!< 0x00000004 */ -#define GCCFG_SDET GCCFG_SDET_Msk /*!< Secondary detection (SD) status */ +#define GCCFG_SDET_Msk (0x1UL << GCCFG_SDET_Pos) /*!< 0x00000004 */ +#define GCCFG_SDET GCCFG_SDET_Msk /*!< Secondary detection (SD) status */ #define GCCFG_PS2DET_Pos (3U) -#define GCCFG_PS2DET_Msk (0x1UL << GCCFG_PS2DET_Pos) /*!< 0x00000008 */ -#define GCCFG_PS2DET GCCFG_PS2DET_Msk /*!< DM pull-up detection status */ +#define GCCFG_PS2DET_Msk (0x1UL << GCCFG_PS2DET_Pos) /*!< 0x00000008 */ +#define GCCFG_PS2DET GCCFG_PS2DET_Msk /*!< DM pull-up detection status */ #define GCCFG_PWRDWN_Pos (16U) -#define GCCFG_PWRDWN_Msk (0x1UL << GCCFG_PWRDWN_Pos) /*!< 0x00010000 */ -#define GCCFG_PWRDWN GCCFG_PWRDWN_Msk /*!< Power down */ +#define GCCFG_PWRDWN_Msk (0x1UL << GCCFG_PWRDWN_Pos) /*!< 0x00010000 */ +#define GCCFG_PWRDWN GCCFG_PWRDWN_Msk /*!< Power down */ #define GCCFG_BCDEN_Pos (17U) -#define GCCFG_BCDEN_Msk (0x1UL << GCCFG_BCDEN_Pos) /*!< 0x00020000 */ -#define GCCFG_BCDEN GCCFG_BCDEN_Msk /*!< Battery charging detector (BCD) enable */ +#define GCCFG_BCDEN_Msk (0x1UL << GCCFG_BCDEN_Pos) /*!< 0x00020000 */ +#define GCCFG_BCDEN GCCFG_BCDEN_Msk /*!< Battery charging detector (BCD) enable */ #define GCCFG_DCDEN_Pos (18U) -#define GCCFG_DCDEN_Msk (0x1UL << GCCFG_DCDEN_Pos) /*!< 0x00040000 */ -#define GCCFG_DCDEN GCCFG_DCDEN_Msk /*!< Data contact detection (DCD) mode enable*/ +#define GCCFG_DCDEN_Msk (0x1UL << GCCFG_DCDEN_Pos) /*!< 0x00040000 */ +#define GCCFG_DCDEN GCCFG_DCDEN_Msk /*!< Data contact detection (DCD) mode enable*/ #define GCCFG_PDEN_Pos (19U) -#define GCCFG_PDEN_Msk (0x1UL << GCCFG_PDEN_Pos) /*!< 0x00080000 */ -#define GCCFG_PDEN GCCFG_PDEN_Msk /*!< Primary detection (PD) mode enable*/ +#define GCCFG_PDEN_Msk (0x1UL << GCCFG_PDEN_Pos) /*!< 0x00080000 */ +#define GCCFG_PDEN GCCFG_PDEN_Msk /*!< Primary detection (PD) mode enable*/ #define GCCFG_SDEN_Pos (20U) -#define GCCFG_SDEN_Msk (0x1UL << GCCFG_SDEN_Pos) /*!< 0x00100000 */ -#define GCCFG_SDEN GCCFG_SDEN_Msk /*!< Secondary detection (SD) mode enable */ +#define GCCFG_SDEN_Msk (0x1UL << GCCFG_SDEN_Pos) /*!< 0x00100000 */ +#define GCCFG_SDEN GCCFG_SDEN_Msk /*!< Secondary detection (SD) mode enable */ #define GCCFG_VBDEN_Pos (21U) -#define GCCFG_VBDEN_Msk (0x1UL << GCCFG_VBDEN_Pos) /*!< 0x00200000 */ -#define GCCFG_VBDEN GCCFG_VBDEN_Msk /*!< VBUS mode enable */ +#define GCCFG_VBDEN_Msk (0x1UL << GCCFG_VBDEN_Pos) /*!< 0x00200000 */ +#define GCCFG_VBDEN GCCFG_VBDEN_Msk /*!< VBUS mode enable */ #define GCCFG_OTGIDEN_Pos (22U) -#define GCCFG_OTGIDEN_Msk (0x1UL << GCCFG_OTGIDEN_Pos) /*!< 0x00400000 */ -#define GCCFG_OTGIDEN GCCFG_OTGIDEN_Msk /*!< OTG Id enable */ +#define GCCFG_OTGIDEN_Msk (0x1UL << GCCFG_OTGIDEN_Pos) /*!< 0x00400000 */ +#define GCCFG_OTGIDEN GCCFG_OTGIDEN_Msk /*!< OTG Id enable */ #define GCCFG_PHYHSEN_Pos (23U) -#define GCCFG_PHYHSEN_Msk (0x1UL << GCCFG_PHYHSEN_Pos) /*!< 0x00800000 */ -#define GCCFG_PHYHSEN GCCFG_PHYHSEN_Msk /*!< HS PHY enable */ +#define GCCFG_PHYHSEN_Msk (0x1UL << GCCFG_PHYHSEN_Pos) /*!< 0x00800000 */ +#define GCCFG_PHYHSEN GCCFG_PHYHSEN_Msk /*!< HS PHY enable */ /******************** Bit definition for DEACHINTMSK register ********************/ #define DEACHINTMSK_IEP1INTM_Pos (1U) -#define DEACHINTMSK_IEP1INTM_Msk (0x1UL << DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */ -#define DEACHINTMSK_IEP1INTM DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */ +#define DEACHINTMSK_IEP1INTM_Msk (0x1UL << DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */ +#define DEACHINTMSK_IEP1INTM DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */ #define DEACHINTMSK_OEP1INTM_Pos (17U) -#define DEACHINTMSK_OEP1INTM_Msk (0x1UL << DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */ -#define DEACHINTMSK_OEP1INTM DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */ +#define DEACHINTMSK_OEP1INTM_Msk (0x1UL << DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */ +#define DEACHINTMSK_OEP1INTM DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */ /******************** Bit definition for CID register ********************/ #define CID_PRODUCT_ID_Pos (0U) -#define CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */ -#define CID_PRODUCT_ID CID_PRODUCT_ID_Msk /*!< Product ID field */ +#define CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */ +#define CID_PRODUCT_ID CID_PRODUCT_ID_Msk /*!< Product ID field */ /******************** Bit definition for GLPMCFG register ********************/ #define GLPMCFG_LPMEN_Pos (0U) -#define GLPMCFG_LPMEN_Msk (0x1UL << GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ -#define GLPMCFG_LPMEN GLPMCFG_LPMEN_Msk /*!< LPM support enable */ +#define GLPMCFG_LPMEN_Msk (0x1UL << GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ +#define GLPMCFG_LPMEN GLPMCFG_LPMEN_Msk /*!< LPM support enable */ #define GLPMCFG_LPMACK_Pos (1U) -#define GLPMCFG_LPMACK_Msk (0x1UL << GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ -#define GLPMCFG_LPMACK GLPMCFG_LPMACK_Msk /*!< LPM Token acknowledge enable */ +#define GLPMCFG_LPMACK_Msk (0x1UL << GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ +#define GLPMCFG_LPMACK GLPMCFG_LPMACK_Msk /*!< LPM Token acknowledge enable */ #define GLPMCFG_BESL_Pos (2U) -#define GLPMCFG_BESL_Msk (0xFUL << GLPMCFG_BESL_Pos) /*!< 0x0000003C */ -#define GLPMCFG_BESL GLPMCFG_BESL_Msk /*!< BESL value received with last ACKed LPM Token */ +#define GLPMCFG_BESL_Msk (0xFUL << GLPMCFG_BESL_Pos) /*!< 0x0000003C */ +#define GLPMCFG_BESL GLPMCFG_BESL_Msk /*!< BESL value received with last ACKed LPM Token */ #define GLPMCFG_REMWAKE_Pos (6U) -#define GLPMCFG_REMWAKE_Msk (0x1UL << GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ -#define GLPMCFG_REMWAKE GLPMCFG_REMWAKE_Msk /*!< bRemoteWake value received with last ACKed LPM Token */ +#define GLPMCFG_REMWAKE_Msk (0x1UL << GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ +#define GLPMCFG_REMWAKE GLPMCFG_REMWAKE_Msk /*!< bRemoteWake value received with last ACKed LPM Token */ #define GLPMCFG_L1SSEN_Pos (7U) -#define GLPMCFG_L1SSEN_Msk (0x1UL << GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ -#define GLPMCFG_L1SSEN GLPMCFG_L1SSEN_Msk /*!< L1 shallow sleep enable */ +#define GLPMCFG_L1SSEN_Msk (0x1UL << GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ +#define GLPMCFG_L1SSEN GLPMCFG_L1SSEN_Msk /*!< L1 shallow sleep enable */ #define GLPMCFG_BESLTHRS_Pos (8U) -#define GLPMCFG_BESLTHRS_Msk (0xFUL << GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ -#define GLPMCFG_BESLTHRS GLPMCFG_BESLTHRS_Msk /*!< BESL threshold */ +#define GLPMCFG_BESLTHRS_Msk (0xFUL << GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ +#define GLPMCFG_BESLTHRS GLPMCFG_BESLTHRS_Msk /*!< BESL threshold */ #define GLPMCFG_L1DSEN_Pos (12U) -#define GLPMCFG_L1DSEN_Msk (0x1UL << GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ -#define GLPMCFG_L1DSEN GLPMCFG_L1DSEN_Msk /*!< L1 deep sleep enable */ +#define GLPMCFG_L1DSEN_Msk (0x1UL << GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ +#define GLPMCFG_L1DSEN GLPMCFG_L1DSEN_Msk /*!< L1 deep sleep enable */ #define GLPMCFG_LPMRSP_Pos (13U) -#define GLPMCFG_LPMRSP_Msk (0x3UL << GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ -#define GLPMCFG_LPMRSP GLPMCFG_LPMRSP_Msk /*!< LPM response */ +#define GLPMCFG_LPMRSP_Msk (0x3UL << GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ +#define GLPMCFG_LPMRSP GLPMCFG_LPMRSP_Msk /*!< LPM response */ #define GLPMCFG_SLPSTS_Pos (15U) -#define GLPMCFG_SLPSTS_Msk (0x1UL << GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ -#define GLPMCFG_SLPSTS GLPMCFG_SLPSTS_Msk /*!< Port sleep status */ +#define GLPMCFG_SLPSTS_Msk (0x1UL << GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ +#define GLPMCFG_SLPSTS GLPMCFG_SLPSTS_Msk /*!< Port sleep status */ #define GLPMCFG_L1RSMOK_Pos (16U) -#define GLPMCFG_L1RSMOK_Msk (0x1UL << GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */ -#define GLPMCFG_L1RSMOK GLPMCFG_L1RSMOK_Msk /*!< Sleep State Resume OK */ +#define GLPMCFG_L1RSMOK_Msk (0x1UL << GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */ +#define GLPMCFG_L1RSMOK GLPMCFG_L1RSMOK_Msk /*!< Sleep State Resume OK */ #define GLPMCFG_LPMCHIDX_Pos (17U) -#define GLPMCFG_LPMCHIDX_Msk (0xFUL << GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ -#define GLPMCFG_LPMCHIDX GLPMCFG_LPMCHIDX_Msk /*!< LPM Channel Index */ +#define GLPMCFG_LPMCHIDX_Msk (0xFUL << GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ +#define GLPMCFG_LPMCHIDX GLPMCFG_LPMCHIDX_Msk /*!< LPM Channel Index */ #define GLPMCFG_LPMRCNT_Pos (21U) -#define GLPMCFG_LPMRCNT_Msk (0x7UL << GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ -#define GLPMCFG_LPMRCNT GLPMCFG_LPMRCNT_Msk /*!< LPM retry count */ +#define GLPMCFG_LPMRCNT_Msk (0x7UL << GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ +#define GLPMCFG_LPMRCNT GLPMCFG_LPMRCNT_Msk /*!< LPM retry count */ #define GLPMCFG_SNDLPM_Pos (24U) -#define GLPMCFG_SNDLPM_Msk (0x1UL << GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ -#define GLPMCFG_SNDLPM GLPMCFG_SNDLPM_Msk /*!< Send LPM transaction */ +#define GLPMCFG_SNDLPM_Msk (0x1UL << GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ +#define GLPMCFG_SNDLPM GLPMCFG_SNDLPM_Msk /*!< Send LPM transaction */ #define GLPMCFG_LPMRCNTSTS_Pos (25U) -#define GLPMCFG_LPMRCNTSTS_Msk (0x7UL << GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ -#define GLPMCFG_LPMRCNTSTS GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status */ +#define GLPMCFG_LPMRCNTSTS_Msk (0x7UL << GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ +#define GLPMCFG_LPMRCNTSTS GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status */ #define GLPMCFG_ENBESL_Pos (28U) -#define GLPMCFG_ENBESL_Msk (0x1UL << GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ -#define GLPMCFG_ENBESL GLPMCFG_ENBESL_Msk /*!< Enable best effort service latency */ +#define GLPMCFG_ENBESL_Msk (0x1UL << GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ +#define GLPMCFG_ENBESL GLPMCFG_ENBESL_Msk /*!< Enable best effort service latency */ /******************** Bit definition for DIEPEACHMSK1 register ********************/ #define DIEPEACHMSK1_XFRCM_Pos (0U) -#define DIEPEACHMSK1_XFRCM_Msk (0x1UL << DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */ -#define DIEPEACHMSK1_XFRCM DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */ +#define DIEPEACHMSK1_XFRCM_Msk (0x1UL << DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */ +#define DIEPEACHMSK1_XFRCM DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */ #define DIEPEACHMSK1_EPDM_Pos (1U) -#define DIEPEACHMSK1_EPDM_Msk (0x1UL << DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */ -#define DIEPEACHMSK1_EPDM DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define DIEPEACHMSK1_EPDM_Msk (0x1UL << DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */ +#define DIEPEACHMSK1_EPDM DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */ #define DIEPEACHMSK1_TOM_Pos (3U) -#define DIEPEACHMSK1_TOM_Msk (0x1UL << DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */ -#define DIEPEACHMSK1_TOM DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ +#define DIEPEACHMSK1_TOM_Msk (0x1UL << DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */ +#define DIEPEACHMSK1_TOM DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ #define DIEPEACHMSK1_ITTXFEMSK_Pos (4U) -#define DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */ -#define DIEPEACHMSK1_ITTXFEMSK DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ +#define DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */ +#define DIEPEACHMSK1_ITTXFEMSK DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ #define DIEPEACHMSK1_INEPNMM_Pos (5U) -#define DIEPEACHMSK1_INEPNMM_Msk (0x1UL << DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */ -#define DIEPEACHMSK1_INEPNMM DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ +#define DIEPEACHMSK1_INEPNMM_Msk (0x1UL << DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */ +#define DIEPEACHMSK1_INEPNMM DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ #define DIEPEACHMSK1_INEPNEM_Pos (6U) -#define DIEPEACHMSK1_INEPNEM_Msk (0x1UL << DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */ -#define DIEPEACHMSK1_INEPNEM DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ +#define DIEPEACHMSK1_INEPNEM_Msk (0x1UL << DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */ +#define DIEPEACHMSK1_INEPNEM DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ #define DIEPEACHMSK1_TXFURM_Pos (8U) -#define DIEPEACHMSK1_TXFURM_Msk (0x1UL << DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */ -#define DIEPEACHMSK1_TXFURM DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */ +#define DIEPEACHMSK1_TXFURM_Msk (0x1UL << DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */ +#define DIEPEACHMSK1_TXFURM DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */ #define DIEPEACHMSK1_BIM_Pos (9U) -#define DIEPEACHMSK1_BIM_Msk (0x1UL << DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */ -#define DIEPEACHMSK1_BIM DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */ +#define DIEPEACHMSK1_BIM_Msk (0x1UL << DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */ +#define DIEPEACHMSK1_BIM DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */ #define DIEPEACHMSK1_NAKM_Pos (13U) -#define DIEPEACHMSK1_NAKM_Msk (0x1UL << DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */ -#define DIEPEACHMSK1_NAKM DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */ +#define DIEPEACHMSK1_NAKM_Msk (0x1UL << DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */ +#define DIEPEACHMSK1_NAKM DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */ /******************** Bit definition for HPRT register ********************/ #define HPRT_PCSTS_Pos (0U) -#define HPRT_PCSTS_Msk (0x1UL << HPRT_PCSTS_Pos) /*!< 0x00000001 */ -#define HPRT_PCSTS HPRT_PCSTS_Msk /*!< Port connect status */ +#define HPRT_PCSTS_Msk (0x1UL << HPRT_PCSTS_Pos) /*!< 0x00000001 */ +#define HPRT_PCSTS HPRT_PCSTS_Msk /*!< Port connect status */ #define HPRT_PCDET_Pos (1U) -#define HPRT_PCDET_Msk (0x1UL << HPRT_PCDET_Pos) /*!< 0x00000002 */ -#define HPRT_PCDET HPRT_PCDET_Msk /*!< Port connect detected */ +#define HPRT_PCDET_Msk (0x1UL << HPRT_PCDET_Pos) /*!< 0x00000002 */ +#define HPRT_PCDET HPRT_PCDET_Msk /*!< Port connect detected */ #define HPRT_PENA_Pos (2U) -#define HPRT_PENA_Msk (0x1UL << HPRT_PENA_Pos) /*!< 0x00000004 */ -#define HPRT_PENA HPRT_PENA_Msk /*!< Port enable */ +#define HPRT_PENA_Msk (0x1UL << HPRT_PENA_Pos) /*!< 0x00000004 */ +#define HPRT_PENA HPRT_PENA_Msk /*!< Port enable */ #define HPRT_PENCHNG_Pos (3U) -#define HPRT_PENCHNG_Msk (0x1UL << HPRT_PENCHNG_Pos) /*!< 0x00000008 */ -#define HPRT_PENCHNG HPRT_PENCHNG_Msk /*!< Port enable/disable change */ +#define HPRT_PENCHNG_Msk (0x1UL << HPRT_PENCHNG_Pos) /*!< 0x00000008 */ +#define HPRT_PENCHNG HPRT_PENCHNG_Msk /*!< Port enable/disable change */ #define HPRT_POCA_Pos (4U) -#define HPRT_POCA_Msk (0x1UL << HPRT_POCA_Pos) /*!< 0x00000010 */ -#define HPRT_POCA HPRT_POCA_Msk /*!< Port overcurrent active */ +#define HPRT_POCA_Msk (0x1UL << HPRT_POCA_Pos) /*!< 0x00000010 */ +#define HPRT_POCA HPRT_POCA_Msk /*!< Port overcurrent active */ #define HPRT_POCCHNG_Pos (5U) -#define HPRT_POCCHNG_Msk (0x1UL << HPRT_POCCHNG_Pos) /*!< 0x00000020 */ -#define HPRT_POCCHNG HPRT_POCCHNG_Msk /*!< Port overcurrent change */ +#define HPRT_POCCHNG_Msk (0x1UL << HPRT_POCCHNG_Pos) /*!< 0x00000020 */ +#define HPRT_POCCHNG HPRT_POCCHNG_Msk /*!< Port overcurrent change */ #define HPRT_PRES_Pos (6U) -#define HPRT_PRES_Msk (0x1UL << HPRT_PRES_Pos) /*!< 0x00000040 */ -#define HPRT_PRES HPRT_PRES_Msk /*!< Port resume */ +#define HPRT_PRES_Msk (0x1UL << HPRT_PRES_Pos) /*!< 0x00000040 */ +#define HPRT_PRES HPRT_PRES_Msk /*!< Port resume */ #define HPRT_PSUSP_Pos (7U) -#define HPRT_PSUSP_Msk (0x1UL << HPRT_PSUSP_Pos) /*!< 0x00000080 */ -#define HPRT_PSUSP HPRT_PSUSP_Msk /*!< Port suspend */ +#define HPRT_PSUSP_Msk (0x1UL << HPRT_PSUSP_Pos) /*!< 0x00000080 */ +#define HPRT_PSUSP HPRT_PSUSP_Msk /*!< Port suspend */ #define HPRT_PRST_Pos (8U) -#define HPRT_PRST_Msk (0x1UL << HPRT_PRST_Pos) /*!< 0x00000100 */ -#define HPRT_PRST HPRT_PRST_Msk /*!< Port reset */ +#define HPRT_PRST_Msk (0x1UL << HPRT_PRST_Pos) /*!< 0x00000100 */ +#define HPRT_PRST HPRT_PRST_Msk /*!< Port reset */ #define HPRT_PLSTS_Pos (10U) -#define HPRT_PLSTS_Msk (0x3UL << HPRT_PLSTS_Pos) /*!< 0x00000C00 */ -#define HPRT_PLSTS HPRT_PLSTS_Msk /*!< Port line status */ -#define HPRT_PLSTS_0 (0x1UL << HPRT_PLSTS_Pos) /*!< 0x00000400 */ -#define HPRT_PLSTS_1 (0x2UL << HPRT_PLSTS_Pos) /*!< 0x00000800 */ +#define HPRT_PLSTS_Msk (0x3UL << HPRT_PLSTS_Pos) /*!< 0x00000C00 */ +#define HPRT_PLSTS HPRT_PLSTS_Msk /*!< Port line status */ +#define HPRT_PLSTS_0 (0x1UL << HPRT_PLSTS_Pos) /*!< 0x00000400 */ +#define HPRT_PLSTS_1 (0x2UL << HPRT_PLSTS_Pos) /*!< 0x00000800 */ #define HPRT_PPWR_Pos (12U) -#define HPRT_PPWR_Msk (0x1UL << HPRT_PPWR_Pos) /*!< 0x00001000 */ -#define HPRT_PPWR HPRT_PPWR_Msk /*!< Port power */ +#define HPRT_PPWR_Msk (0x1UL << HPRT_PPWR_Pos) /*!< 0x00001000 */ +#define HPRT_PPWR HPRT_PPWR_Msk /*!< Port power */ #define HPRT_PTCTL_Pos (13U) -#define HPRT_PTCTL_Msk (0xFUL << HPRT_PTCTL_Pos) /*!< 0x0001E000 */ -#define HPRT_PTCTL HPRT_PTCTL_Msk /*!< Port test control */ -#define HPRT_PTCTL_0 (0x1UL << HPRT_PTCTL_Pos) /*!< 0x00002000 */ -#define HPRT_PTCTL_1 (0x2UL << HPRT_PTCTL_Pos) /*!< 0x00004000 */ -#define HPRT_PTCTL_2 (0x4UL << HPRT_PTCTL_Pos) /*!< 0x00008000 */ -#define HPRT_PTCTL_3 (0x8UL << HPRT_PTCTL_Pos) /*!< 0x00010000 */ +#define HPRT_PTCTL_Msk (0xFUL << HPRT_PTCTL_Pos) /*!< 0x0001E000 */ +#define HPRT_PTCTL HPRT_PTCTL_Msk /*!< Port test control */ +#define HPRT_PTCTL_0 (0x1UL << HPRT_PTCTL_Pos) /*!< 0x00002000 */ +#define HPRT_PTCTL_1 (0x2UL << HPRT_PTCTL_Pos) /*!< 0x00004000 */ +#define HPRT_PTCTL_2 (0x4UL << HPRT_PTCTL_Pos) /*!< 0x00008000 */ +#define HPRT_PTCTL_3 (0x8UL << HPRT_PTCTL_Pos) /*!< 0x00010000 */ #define HPRT_PSPD_Pos (17U) -#define HPRT_PSPD_Msk (0x3UL << HPRT_PSPD_Pos) /*!< 0x00060000 */ -#define HPRT_PSPD HPRT_PSPD_Msk /*!< Port speed */ -#define HPRT_PSPD_0 (0x1UL << HPRT_PSPD_Pos) /*!< 0x00020000 */ -#define HPRT_PSPD_1 (0x2UL << HPRT_PSPD_Pos) /*!< 0x00040000 */ +#define HPRT_PSPD_Msk (0x3UL << HPRT_PSPD_Pos) /*!< 0x00060000 */ +#define HPRT_PSPD HPRT_PSPD_Msk /*!< Port speed */ +#define HPRT_PSPD_0 (0x1UL << HPRT_PSPD_Pos) /*!< 0x00020000 */ +#define HPRT_PSPD_1 (0x2UL << HPRT_PSPD_Pos) /*!< 0x00040000 */ /******************** Bit definition for DOEPEACHMSK1 register ********************/ #define DOEPEACHMSK1_XFRCM_Pos (0U) -#define DOEPEACHMSK1_XFRCM_Msk (0x1UL << DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */ -#define DOEPEACHMSK1_XFRCM DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */ +#define DOEPEACHMSK1_XFRCM_Msk (0x1UL << DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */ +#define DOEPEACHMSK1_XFRCM DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */ #define DOEPEACHMSK1_EPDM_Pos (1U) -#define DOEPEACHMSK1_EPDM_Msk (0x1UL << DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */ -#define DOEPEACHMSK1_EPDM DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define DOEPEACHMSK1_EPDM_Msk (0x1UL << DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */ +#define DOEPEACHMSK1_EPDM DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */ #define DOEPEACHMSK1_TOM_Pos (3U) -#define DOEPEACHMSK1_TOM_Msk (0x1UL << DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */ -#define DOEPEACHMSK1_TOM DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */ +#define DOEPEACHMSK1_TOM_Msk (0x1UL << DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */ +#define DOEPEACHMSK1_TOM DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */ #define DOEPEACHMSK1_ITTXFEMSK_Pos (4U) -#define DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */ -#define DOEPEACHMSK1_ITTXFEMSK DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ +#define DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */ +#define DOEPEACHMSK1_ITTXFEMSK DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ #define DOEPEACHMSK1_INEPNMM_Pos (5U) -#define DOEPEACHMSK1_INEPNMM_Msk (0x1UL << DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */ -#define DOEPEACHMSK1_INEPNMM DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ +#define DOEPEACHMSK1_INEPNMM_Msk (0x1UL << DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */ +#define DOEPEACHMSK1_INEPNMM DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ #define DOEPEACHMSK1_INEPNEM_Pos (6U) -#define DOEPEACHMSK1_INEPNEM_Msk (0x1UL << DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */ -#define DOEPEACHMSK1_INEPNEM DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ +#define DOEPEACHMSK1_INEPNEM_Msk (0x1UL << DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */ +#define DOEPEACHMSK1_INEPNEM DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ #define DOEPEACHMSK1_TXFURM_Pos (8U) -#define DOEPEACHMSK1_TXFURM_Msk (0x1UL << DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */ -#define DOEPEACHMSK1_TXFURM DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */ +#define DOEPEACHMSK1_TXFURM_Msk (0x1UL << DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */ +#define DOEPEACHMSK1_TXFURM DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */ #define DOEPEACHMSK1_BIM_Pos (9U) -#define DOEPEACHMSK1_BIM_Msk (0x1UL << DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */ -#define DOEPEACHMSK1_BIM DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */ +#define DOEPEACHMSK1_BIM_Msk (0x1UL << DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */ +#define DOEPEACHMSK1_BIM DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */ #define DOEPEACHMSK1_BERRM_Pos (12U) -#define DOEPEACHMSK1_BERRM_Msk (0x1UL << DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */ -#define DOEPEACHMSK1_BERRM DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */ +#define DOEPEACHMSK1_BERRM_Msk (0x1UL << DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */ +#define DOEPEACHMSK1_BERRM DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */ #define DOEPEACHMSK1_NAKM_Pos (13U) -#define DOEPEACHMSK1_NAKM_Msk (0x1UL << DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */ -#define DOEPEACHMSK1_NAKM DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */ +#define DOEPEACHMSK1_NAKM_Msk (0x1UL << DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */ +#define DOEPEACHMSK1_NAKM DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */ #define DOEPEACHMSK1_NYETM_Pos (14U) -#define DOEPEACHMSK1_NYETM_Msk (0x1UL << DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */ -#define DOEPEACHMSK1_NYETM DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */ +#define DOEPEACHMSK1_NYETM_Msk (0x1UL << DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */ +#define DOEPEACHMSK1_NYETM DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */ /******************** Bit definition for HPTXFSIZ register ********************/ #define HPTXFSIZ_PTXSA_Pos (0U) -#define HPTXFSIZ_PTXSA_Msk (0xFFFFUL << HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ -#define HPTXFSIZ_PTXSA HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ +#define HPTXFSIZ_PTXSA_Msk (0xFFFFUL << HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ +#define HPTXFSIZ_PTXSA HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ #define HPTXFSIZ_PTXFD_Pos (16U) -#define HPTXFSIZ_PTXFD_Msk (0xFFFFUL << HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ -#define HPTXFSIZ_PTXFD HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ +#define HPTXFSIZ_PTXFD_Msk (0xFFFFUL << HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ +#define HPTXFSIZ_PTXFD HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ /******************** Bit definition for DIEPCTL register ********************/ #define DIEPCTL_MPSIZ_Pos (0U) -#define DIEPCTL_MPSIZ_Msk (0x7FFUL << DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */ -#define DIEPCTL_MPSIZ DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */ +#define DIEPCTL_MPSIZ_Msk (0x7FFUL << DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */ +#define DIEPCTL_MPSIZ DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */ #define DIEPCTL_USBAEP_Pos (15U) -#define DIEPCTL_USBAEP_Msk (0x1UL << DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */ -#define DIEPCTL_USBAEP DIEPCTL_USBAEP_Msk /*!< USB active endpoint */ +#define DIEPCTL_USBAEP_Msk (0x1UL << DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */ +#define DIEPCTL_USBAEP DIEPCTL_USBAEP_Msk /*!< USB active endpoint */ #define DIEPCTL_EONUM_DPID_Pos (16U) -#define DIEPCTL_EONUM_DPID_Msk (0x1UL << DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */ -#define DIEPCTL_EONUM_DPID DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */ +#define DIEPCTL_EONUM_DPID_Msk (0x1UL << DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */ +#define DIEPCTL_EONUM_DPID DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */ #define DIEPCTL_NAKSTS_Pos (17U) -#define DIEPCTL_NAKSTS_Msk (0x1UL << DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ -#define DIEPCTL_NAKSTS DIEPCTL_NAKSTS_Msk /*!< NAK status */ +#define DIEPCTL_NAKSTS_Msk (0x1UL << DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ +#define DIEPCTL_NAKSTS DIEPCTL_NAKSTS_Msk /*!< NAK status */ #define DIEPCTL_EPTYP_Pos (18U) -#define DIEPCTL_EPTYP_Msk (0x3UL << DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ -#define DIEPCTL_EPTYP DIEPCTL_EPTYP_Msk /*!< Endpoint type */ -#define DIEPCTL_EPTYP_0 (0x1UL << DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */ -#define DIEPCTL_EPTYP_1 (0x2UL << DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */ +#define DIEPCTL_EPTYP_Msk (0x3UL << DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ +#define DIEPCTL_EPTYP DIEPCTL_EPTYP_Msk /*!< Endpoint type */ +#define DIEPCTL_EPTYP_0 (0x1UL << DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */ +#define DIEPCTL_EPTYP_1 (0x2UL << DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */ #define DIEPCTL_STALL_Pos (21U) -#define DIEPCTL_STALL_Msk (0x1UL << DIEPCTL_STALL_Pos) /*!< 0x00200000 */ -#define DIEPCTL_STALL DIEPCTL_STALL_Msk /*!< STALL handshake */ +#define DIEPCTL_STALL_Msk (0x1UL << DIEPCTL_STALL_Pos) /*!< 0x00200000 */ +#define DIEPCTL_STALL DIEPCTL_STALL_Msk /*!< STALL handshake */ #define DIEPCTL_TXFNUM_Pos (22U) -#define DIEPCTL_TXFNUM_Msk (0xFUL << DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */ -#define DIEPCTL_TXFNUM DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */ -#define DIEPCTL_TXFNUM_0 (0x1UL << DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */ -#define DIEPCTL_TXFNUM_1 (0x2UL << DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */ -#define DIEPCTL_TXFNUM_2 (0x4UL << DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */ -#define DIEPCTL_TXFNUM_3 (0x8UL << DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */ +#define DIEPCTL_TXFNUM_Msk (0xFUL << DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */ +#define DIEPCTL_TXFNUM DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */ +#define DIEPCTL_TXFNUM_0 (0x1UL << DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */ +#define DIEPCTL_TXFNUM_1 (0x2UL << DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */ +#define DIEPCTL_TXFNUM_2 (0x4UL << DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */ +#define DIEPCTL_TXFNUM_3 (0x8UL << DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */ #define DIEPCTL_CNAK_Pos (26U) -#define DIEPCTL_CNAK_Msk (0x1UL << DIEPCTL_CNAK_Pos) /*!< 0x04000000 */ -#define DIEPCTL_CNAK DIEPCTL_CNAK_Msk /*!< Clear NAK */ +#define DIEPCTL_CNAK_Msk (0x1UL << DIEPCTL_CNAK_Pos) /*!< 0x04000000 */ +#define DIEPCTL_CNAK DIEPCTL_CNAK_Msk /*!< Clear NAK */ #define DIEPCTL_SNAK_Pos (27U) -#define DIEPCTL_SNAK_Msk (0x1UL << DIEPCTL_SNAK_Pos) /*!< 0x08000000 */ -#define DIEPCTL_SNAK DIEPCTL_SNAK_Msk /*!< Set NAK */ +#define DIEPCTL_SNAK_Msk (0x1UL << DIEPCTL_SNAK_Pos) /*!< 0x08000000 */ +#define DIEPCTL_SNAK DIEPCTL_SNAK_Msk /*!< Set NAK */ #define DIEPCTL_SD0PID_SEVNFRM_Pos (28U) -#define DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define DIEPCTL_SD0PID_SEVNFRM DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ +#define DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ +#define DIEPCTL_SD0PID_SEVNFRM DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ #define DIEPCTL_SODDFRM_Pos (29U) -#define DIEPCTL_SODDFRM_Msk (0x1UL << DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define DIEPCTL_SODDFRM DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ +#define DIEPCTL_SODDFRM_Msk (0x1UL << DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ +#define DIEPCTL_SODDFRM DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ #define DIEPCTL_EPDIS_Pos (30U) -#define DIEPCTL_EPDIS_Msk (0x1UL << DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ -#define DIEPCTL_EPDIS DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ +#define DIEPCTL_EPDIS_Msk (0x1UL << DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ +#define DIEPCTL_EPDIS DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ #define DIEPCTL_EPENA_Pos (31U) -#define DIEPCTL_EPENA_Msk (0x1UL << DIEPCTL_EPENA_Pos) /*!< 0x80000000 */ -#define DIEPCTL_EPENA DIEPCTL_EPENA_Msk /*!< Endpoint enable */ +#define DIEPCTL_EPENA_Msk (0x1UL << DIEPCTL_EPENA_Pos) /*!< 0x80000000 */ +#define DIEPCTL_EPENA DIEPCTL_EPENA_Msk /*!< Endpoint enable */ /******************** Bit definition for HCCHAR register ********************/ #define HCCHAR_MPSIZ_Pos (0U) -#define HCCHAR_MPSIZ_Msk (0x7FFUL << HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ -#define HCCHAR_MPSIZ HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ +#define HCCHAR_MPSIZ_Msk (0x7FFUL << HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ +#define HCCHAR_MPSIZ HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ #define HCCHAR_EPNUM_Pos (11U) -#define HCCHAR_EPNUM_Msk (0xFUL << HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ -#define HCCHAR_EPNUM HCCHAR_EPNUM_Msk /*!< Endpoint number */ -#define HCCHAR_EPNUM_0 (0x1UL << HCCHAR_EPNUM_Pos) /*!< 0x00000800 */ -#define HCCHAR_EPNUM_1 (0x2UL << HCCHAR_EPNUM_Pos) /*!< 0x00001000 */ -#define HCCHAR_EPNUM_2 (0x4UL << HCCHAR_EPNUM_Pos) /*!< 0x00002000 */ -#define HCCHAR_EPNUM_3 (0x8UL << HCCHAR_EPNUM_Pos) /*!< 0x00004000 */ +#define HCCHAR_EPNUM_Msk (0xFUL << HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ +#define HCCHAR_EPNUM HCCHAR_EPNUM_Msk /*!< Endpoint number */ +#define HCCHAR_EPNUM_0 (0x1UL << HCCHAR_EPNUM_Pos) /*!< 0x00000800 */ +#define HCCHAR_EPNUM_1 (0x2UL << HCCHAR_EPNUM_Pos) /*!< 0x00001000 */ +#define HCCHAR_EPNUM_2 (0x4UL << HCCHAR_EPNUM_Pos) /*!< 0x00002000 */ +#define HCCHAR_EPNUM_3 (0x8UL << HCCHAR_EPNUM_Pos) /*!< 0x00004000 */ #define HCCHAR_EPDIR_Pos (15U) -#define HCCHAR_EPDIR_Msk (0x1UL << HCCHAR_EPDIR_Pos) /*!< 0x00008000 */ -#define HCCHAR_EPDIR HCCHAR_EPDIR_Msk /*!< Endpoint direction */ +#define HCCHAR_EPDIR_Msk (0x1UL << HCCHAR_EPDIR_Pos) /*!< 0x00008000 */ +#define HCCHAR_EPDIR HCCHAR_EPDIR_Msk /*!< Endpoint direction */ #define HCCHAR_LSDEV_Pos (17U) -#define HCCHAR_LSDEV_Msk (0x1UL << HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ -#define HCCHAR_LSDEV HCCHAR_LSDEV_Msk /*!< Low-speed device */ +#define HCCHAR_LSDEV_Msk (0x1UL << HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ +#define HCCHAR_LSDEV HCCHAR_LSDEV_Msk /*!< Low-speed device */ #define HCCHAR_EPTYP_Pos (18U) -#define HCCHAR_EPTYP_Msk (0x3UL << HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ -#define HCCHAR_EPTYP HCCHAR_EPTYP_Msk /*!< Endpoint type */ -#define HCCHAR_EPTYP_0 (0x1UL << HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ -#define HCCHAR_EPTYP_1 (0x2UL << HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ +#define HCCHAR_EPTYP_Msk (0x3UL << HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ +#define HCCHAR_EPTYP HCCHAR_EPTYP_Msk /*!< Endpoint type */ +#define HCCHAR_EPTYP_0 (0x1UL << HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ +#define HCCHAR_EPTYP_1 (0x2UL << HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ #define HCCHAR_MC_Pos (20U) -#define HCCHAR_MC_Msk (0x3UL << HCCHAR_MC_Pos) /*!< 0x00300000 */ -#define HCCHAR_MC HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ -#define HCCHAR_MC_0 (0x1UL << HCCHAR_MC_Pos) /*!< 0x00100000 */ -#define HCCHAR_MC_1 (0x2UL << HCCHAR_MC_Pos) /*!< 0x00200000 */ +#define HCCHAR_MC_Msk (0x3UL << HCCHAR_MC_Pos) /*!< 0x00300000 */ +#define HCCHAR_MC HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ +#define HCCHAR_MC_0 (0x1UL << HCCHAR_MC_Pos) /*!< 0x00100000 */ +#define HCCHAR_MC_1 (0x2UL << HCCHAR_MC_Pos) /*!< 0x00200000 */ #define HCCHAR_DAD_Pos (22U) -#define HCCHAR_DAD_Msk (0x7FUL << HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ -#define HCCHAR_DAD HCCHAR_DAD_Msk /*!< Device address */ -#define HCCHAR_DAD_0 (0x01UL << HCCHAR_DAD_Pos) /*!< 0x00400000 */ -#define HCCHAR_DAD_1 (0x02UL << HCCHAR_DAD_Pos) /*!< 0x00800000 */ -#define HCCHAR_DAD_2 (0x04UL << HCCHAR_DAD_Pos) /*!< 0x01000000 */ -#define HCCHAR_DAD_3 (0x08UL << HCCHAR_DAD_Pos) /*!< 0x02000000 */ -#define HCCHAR_DAD_4 (0x10UL << HCCHAR_DAD_Pos) /*!< 0x04000000 */ -#define HCCHAR_DAD_5 (0x20UL << HCCHAR_DAD_Pos) /*!< 0x08000000 */ -#define HCCHAR_DAD_6 (0x40UL << HCCHAR_DAD_Pos) /*!< 0x10000000 */ +#define HCCHAR_DAD_Msk (0x7FUL << HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ +#define HCCHAR_DAD HCCHAR_DAD_Msk /*!< Device address */ +#define HCCHAR_DAD_0 (0x01UL << HCCHAR_DAD_Pos) /*!< 0x00400000 */ +#define HCCHAR_DAD_1 (0x02UL << HCCHAR_DAD_Pos) /*!< 0x00800000 */ +#define HCCHAR_DAD_2 (0x04UL << HCCHAR_DAD_Pos) /*!< 0x01000000 */ +#define HCCHAR_DAD_3 (0x08UL << HCCHAR_DAD_Pos) /*!< 0x02000000 */ +#define HCCHAR_DAD_4 (0x10UL << HCCHAR_DAD_Pos) /*!< 0x04000000 */ +#define HCCHAR_DAD_5 (0x20UL << HCCHAR_DAD_Pos) /*!< 0x08000000 */ +#define HCCHAR_DAD_6 (0x40UL << HCCHAR_DAD_Pos) /*!< 0x10000000 */ #define HCCHAR_ODDFRM_Pos (29U) -#define HCCHAR_ODDFRM_Msk (0x1UL << HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */ -#define HCCHAR_ODDFRM HCCHAR_ODDFRM_Msk /*!< Odd frame */ +#define HCCHAR_ODDFRM_Msk (0x1UL << HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */ +#define HCCHAR_ODDFRM HCCHAR_ODDFRM_Msk /*!< Odd frame */ #define HCCHAR_CHDIS_Pos (30U) -#define HCCHAR_CHDIS_Msk (0x1UL << HCCHAR_CHDIS_Pos) /*!< 0x40000000 */ -#define HCCHAR_CHDIS HCCHAR_CHDIS_Msk /*!< Channel disable */ +#define HCCHAR_CHDIS_Msk (0x1UL << HCCHAR_CHDIS_Pos) /*!< 0x40000000 */ +#define HCCHAR_CHDIS HCCHAR_CHDIS_Msk /*!< Channel disable */ #define HCCHAR_CHENA_Pos (31U) -#define HCCHAR_CHENA_Msk (0x1UL << HCCHAR_CHENA_Pos) /*!< 0x80000000 */ -#define HCCHAR_CHENA HCCHAR_CHENA_Msk /*!< Channel enable */ +#define HCCHAR_CHENA_Msk (0x1UL << HCCHAR_CHENA_Pos) /*!< 0x80000000 */ +#define HCCHAR_CHENA HCCHAR_CHENA_Msk /*!< Channel enable */ /******************** Bit definition for HCSPLT register ********************/ #define HCSPLT_PRTADDR_Pos (0U) -#define HCSPLT_PRTADDR_Msk (0x7FUL << HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */ -#define HCSPLT_PRTADDR HCSPLT_PRTADDR_Msk /*!< Port address */ -#define HCSPLT_PRTADDR_0 (0x01UL << HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */ -#define HCSPLT_PRTADDR_1 (0x02UL << HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */ -#define HCSPLT_PRTADDR_2 (0x04UL << HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */ -#define HCSPLT_PRTADDR_3 (0x08UL << HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */ -#define HCSPLT_PRTADDR_4 (0x10UL << HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */ -#define HCSPLT_PRTADDR_5 (0x20UL << HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */ -#define HCSPLT_PRTADDR_6 (0x40UL << HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */ +#define HCSPLT_PRTADDR_Msk (0x7FUL << HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */ +#define HCSPLT_PRTADDR HCSPLT_PRTADDR_Msk /*!< Port address */ +#define HCSPLT_PRTADDR_0 (0x01UL << HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */ +#define HCSPLT_PRTADDR_1 (0x02UL << HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */ +#define HCSPLT_PRTADDR_2 (0x04UL << HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */ +#define HCSPLT_PRTADDR_3 (0x08UL << HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */ +#define HCSPLT_PRTADDR_4 (0x10UL << HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */ +#define HCSPLT_PRTADDR_5 (0x20UL << HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */ +#define HCSPLT_PRTADDR_6 (0x40UL << HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */ #define HCSPLT_HUBADDR_Pos (7U) -#define HCSPLT_HUBADDR_Msk (0x7FUL << HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */ -#define HCSPLT_HUBADDR HCSPLT_HUBADDR_Msk /*!< Hub address */ -#define HCSPLT_HUBADDR_0 (0x01UL << HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */ -#define HCSPLT_HUBADDR_1 (0x02UL << HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */ -#define HCSPLT_HUBADDR_2 (0x04UL << HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */ -#define HCSPLT_HUBADDR_3 (0x08UL << HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */ -#define HCSPLT_HUBADDR_4 (0x10UL << HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */ -#define HCSPLT_HUBADDR_5 (0x20UL << HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */ -#define HCSPLT_HUBADDR_6 (0x40UL << HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */ +#define HCSPLT_HUBADDR_Msk (0x7FUL << HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */ +#define HCSPLT_HUBADDR HCSPLT_HUBADDR_Msk /*!< Hub address */ +#define HCSPLT_HUBADDR_0 (0x01UL << HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */ +#define HCSPLT_HUBADDR_1 (0x02UL << HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */ +#define HCSPLT_HUBADDR_2 (0x04UL << HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */ +#define HCSPLT_HUBADDR_3 (0x08UL << HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */ +#define HCSPLT_HUBADDR_4 (0x10UL << HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */ +#define HCSPLT_HUBADDR_5 (0x20UL << HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */ +#define HCSPLT_HUBADDR_6 (0x40UL << HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */ #define HCSPLT_XACTPOS_Pos (14U) -#define HCSPLT_XACTPOS_Msk (0x3UL << HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */ -#define HCSPLT_XACTPOS HCSPLT_XACTPOS_Msk /*!< XACTPOS */ -#define HCSPLT_XACTPOS_0 (0x1UL << HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */ -#define HCSPLT_XACTPOS_1 (0x2UL << HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */ +#define HCSPLT_XACTPOS_Msk (0x3UL << HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */ +#define HCSPLT_XACTPOS HCSPLT_XACTPOS_Msk /*!< XACTPOS */ +#define HCSPLT_XACTPOS_0 (0x1UL << HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */ +#define HCSPLT_XACTPOS_1 (0x2UL << HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */ #define HCSPLT_COMPLSPLT_Pos (16U) -#define HCSPLT_COMPLSPLT_Msk (0x1UL << HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */ -#define HCSPLT_COMPLSPLT HCSPLT_COMPLSPLT_Msk /*!< Do complete split */ +#define HCSPLT_COMPLSPLT_Msk (0x1UL << HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */ +#define HCSPLT_COMPLSPLT HCSPLT_COMPLSPLT_Msk /*!< Do complete split */ #define HCSPLT_SPLITEN_Pos (31U) -#define HCSPLT_SPLITEN_Msk (0x1UL << HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */ -#define HCSPLT_SPLITEN HCSPLT_SPLITEN_Msk /*!< Split enable */ +#define HCSPLT_SPLITEN_Msk (0x1UL << HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */ +#define HCSPLT_SPLITEN HCSPLT_SPLITEN_Msk /*!< Split enable */ /******************** Bit definition for HCINT register ********************/ #define HCINT_XFRC_Pos (0U) -#define HCINT_XFRC_Msk (0x1UL << HCINT_XFRC_Pos) /*!< 0x00000001 */ -#define HCINT_XFRC HCINT_XFRC_Msk /*!< Transfer completed */ +#define HCINT_XFRC_Msk (0x1UL << HCINT_XFRC_Pos) /*!< 0x00000001 */ +#define HCINT_XFRC HCINT_XFRC_Msk /*!< Transfer completed */ #define HCINT_CHH_Pos (1U) -#define HCINT_CHH_Msk (0x1UL << HCINT_CHH_Pos) /*!< 0x00000002 */ -#define HCINT_CHH HCINT_CHH_Msk /*!< Channel halted */ +#define HCINT_CHH_Msk (0x1UL << HCINT_CHH_Pos) /*!< 0x00000002 */ +#define HCINT_CHH HCINT_CHH_Msk /*!< Channel halted */ #define HCINT_AHBERR_Pos (2U) -#define HCINT_AHBERR_Msk (0x1UL << HCINT_AHBERR_Pos) /*!< 0x00000004 */ -#define HCINT_AHBERR HCINT_AHBERR_Msk /*!< AHB error */ +#define HCINT_AHBERR_Msk (0x1UL << HCINT_AHBERR_Pos) /*!< 0x00000004 */ +#define HCINT_AHBERR HCINT_AHBERR_Msk /*!< AHB error */ #define HCINT_STALL_Pos (3U) -#define HCINT_STALL_Msk (0x1UL << HCINT_STALL_Pos) /*!< 0x00000008 */ -#define HCINT_STALL HCINT_STALL_Msk /*!< STALL response received interrupt */ +#define HCINT_STALL_Msk (0x1UL << HCINT_STALL_Pos) /*!< 0x00000008 */ +#define HCINT_STALL HCINT_STALL_Msk /*!< STALL response received interrupt */ #define HCINT_NAK_Pos (4U) -#define HCINT_NAK_Msk (0x1UL << HCINT_NAK_Pos) /*!< 0x00000010 */ -#define HCINT_NAK HCINT_NAK_Msk /*!< NAK response received interrupt */ +#define HCINT_NAK_Msk (0x1UL << HCINT_NAK_Pos) /*!< 0x00000010 */ +#define HCINT_NAK HCINT_NAK_Msk /*!< NAK response received interrupt */ #define HCINT_ACK_Pos (5U) -#define HCINT_ACK_Msk (0x1UL << HCINT_ACK_Pos) /*!< 0x00000020 */ -#define HCINT_ACK HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */ +#define HCINT_ACK_Msk (0x1UL << HCINT_ACK_Pos) /*!< 0x00000020 */ +#define HCINT_ACK HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */ #define HCINT_NYET_Pos (6U) -#define HCINT_NYET_Msk (0x1UL << HCINT_NYET_Pos) /*!< 0x00000040 */ -#define HCINT_NYET HCINT_NYET_Msk /*!< Response received interrupt */ +#define HCINT_NYET_Msk (0x1UL << HCINT_NYET_Pos) /*!< 0x00000040 */ +#define HCINT_NYET HCINT_NYET_Msk /*!< Response received interrupt */ #define HCINT_TXERR_Pos (7U) -#define HCINT_TXERR_Msk (0x1UL << HCINT_TXERR_Pos) /*!< 0x00000080 */ -#define HCINT_TXERR HCINT_TXERR_Msk /*!< Transaction error */ +#define HCINT_TXERR_Msk (0x1UL << HCINT_TXERR_Pos) /*!< 0x00000080 */ +#define HCINT_TXERR HCINT_TXERR_Msk /*!< Transaction error */ #define HCINT_BBERR_Pos (8U) -#define HCINT_BBERR_Msk (0x1UL << HCINT_BBERR_Pos) /*!< 0x00000100 */ -#define HCINT_BBERR HCINT_BBERR_Msk /*!< Babble error */ +#define HCINT_BBERR_Msk (0x1UL << HCINT_BBERR_Pos) /*!< 0x00000100 */ +#define HCINT_BBERR HCINT_BBERR_Msk /*!< Babble error */ #define HCINT_FRMOR_Pos (9U) -#define HCINT_FRMOR_Msk (0x1UL << HCINT_FRMOR_Pos) /*!< 0x00000200 */ -#define HCINT_FRMOR HCINT_FRMOR_Msk /*!< Frame overrun */ +#define HCINT_FRMOR_Msk (0x1UL << HCINT_FRMOR_Pos) /*!< 0x00000200 */ +#define HCINT_FRMOR HCINT_FRMOR_Msk /*!< Frame overrun */ #define HCINT_DTERR_Pos (10U) -#define HCINT_DTERR_Msk (0x1UL << HCINT_DTERR_Pos) /*!< 0x00000400 */ -#define HCINT_DTERR HCINT_DTERR_Msk /*!< Data toggle error */ +#define HCINT_DTERR_Msk (0x1UL << HCINT_DTERR_Pos) /*!< 0x00000400 */ +#define HCINT_DTERR HCINT_DTERR_Msk /*!< Data toggle error */ /******************** Bit definition for DIEPINT register ********************/ #define DIEPINT_XFRC_Pos (0U) -#define DIEPINT_XFRC_Msk (0x1UL << DIEPINT_XFRC_Pos) /*!< 0x00000001 */ -#define DIEPINT_XFRC DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */ +#define DIEPINT_XFRC_Msk (0x1UL << DIEPINT_XFRC_Pos) /*!< 0x00000001 */ +#define DIEPINT_XFRC DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */ #define DIEPINT_EPDISD_Pos (1U) -#define DIEPINT_EPDISD_Msk (0x1UL << DIEPINT_EPDISD_Pos) /*!< 0x00000002 */ -#define DIEPINT_EPDISD DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ +#define DIEPINT_EPDISD_Msk (0x1UL << DIEPINT_EPDISD_Pos) /*!< 0x00000002 */ +#define DIEPINT_EPDISD DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ #define DIEPINT_AHBERR_Pos (2U) -#define DIEPINT_AHBERR_Msk (0x1UL << DIEPINT_AHBERR_Pos) /*!< 0x00000004 */ -#define DIEPINT_AHBERR DIEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an IN transaction */ +#define DIEPINT_AHBERR_Msk (0x1UL << DIEPINT_AHBERR_Pos) /*!< 0x00000004 */ +#define DIEPINT_AHBERR DIEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an IN transaction */ #define DIEPINT_TOC_Pos (3U) -#define DIEPINT_TOC_Msk (0x1UL << DIEPINT_TOC_Pos) /*!< 0x00000008 */ -#define DIEPINT_TOC DIEPINT_TOC_Msk /*!< Timeout condition */ +#define DIEPINT_TOC_Msk (0x1UL << DIEPINT_TOC_Pos) /*!< 0x00000008 */ +#define DIEPINT_TOC DIEPINT_TOC_Msk /*!< Timeout condition */ #define DIEPINT_ITTXFE_Pos (4U) -#define DIEPINT_ITTXFE_Msk (0x1UL << DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ -#define DIEPINT_ITTXFE DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ +#define DIEPINT_ITTXFE_Msk (0x1UL << DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ +#define DIEPINT_ITTXFE DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ #define DIEPINT_INEPNM_Pos (5U) -#define DIEPINT_INEPNM_Msk (0x1UL << DIEPINT_INEPNM_Pos) /*!< 0x00000020 */ -#define DIEPINT_INEPNM DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ +#define DIEPINT_INEPNM_Msk (0x1UL << DIEPINT_INEPNM_Pos) /*!< 0x00000020 */ +#define DIEPINT_INEPNM DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ #define DIEPINT_INEPNE_Pos (6U) -#define DIEPINT_INEPNE_Msk (0x1UL << DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ -#define DIEPINT_INEPNE DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ +#define DIEPINT_INEPNE_Msk (0x1UL << DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ +#define DIEPINT_INEPNE DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ #define DIEPINT_TXFE_Pos (7U) -#define DIEPINT_TXFE_Msk (0x1UL << DIEPINT_TXFE_Pos) /*!< 0x00000080 */ -#define DIEPINT_TXFE DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */ +#define DIEPINT_TXFE_Msk (0x1UL << DIEPINT_TXFE_Pos) /*!< 0x00000080 */ +#define DIEPINT_TXFE DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */ #define DIEPINT_TXFIFOUDRN_Pos (8U) -#define DIEPINT_TXFIFOUDRN_Msk (0x1UL << DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */ -#define DIEPINT_TXFIFOUDRN DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */ +#define DIEPINT_TXFIFOUDRN_Msk (0x1UL << DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */ +#define DIEPINT_TXFIFOUDRN DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */ #define DIEPINT_BNA_Pos (9U) -#define DIEPINT_BNA_Msk (0x1UL << DIEPINT_BNA_Pos) /*!< 0x00000200 */ -#define DIEPINT_BNA DIEPINT_BNA_Msk /*!< Buffer not available interrupt */ +#define DIEPINT_BNA_Msk (0x1UL << DIEPINT_BNA_Pos) /*!< 0x00000200 */ +#define DIEPINT_BNA DIEPINT_BNA_Msk /*!< Buffer not available interrupt */ #define DIEPINT_PKTDRPSTS_Pos (11U) -#define DIEPINT_PKTDRPSTS_Msk (0x1UL << DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */ -#define DIEPINT_PKTDRPSTS DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */ +#define DIEPINT_PKTDRPSTS_Msk (0x1UL << DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */ +#define DIEPINT_PKTDRPSTS DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */ #define DIEPINT_BERR_Pos (12U) -#define DIEPINT_BERR_Msk (0x1UL << DIEPINT_BERR_Pos) /*!< 0x00001000 */ -#define DIEPINT_BERR DIEPINT_BERR_Msk /*!< Babble error interrupt */ +#define DIEPINT_BERR_Msk (0x1UL << DIEPINT_BERR_Pos) /*!< 0x00001000 */ +#define DIEPINT_BERR DIEPINT_BERR_Msk /*!< Babble error interrupt */ #define DIEPINT_NAK_Pos (13U) -#define DIEPINT_NAK_Msk (0x1UL << DIEPINT_NAK_Pos) /*!< 0x00002000 */ -#define DIEPINT_NAK DIEPINT_NAK_Msk /*!< NAK interrupt */ +#define DIEPINT_NAK_Msk (0x1UL << DIEPINT_NAK_Pos) /*!< 0x00002000 */ +#define DIEPINT_NAK DIEPINT_NAK_Msk /*!< NAK interrupt */ /******************** Bit definition for HCINTMSK register ********************/ #define HCINTMSK_XFRCM_Pos (0U) -#define HCINTMSK_XFRCM_Msk (0x1UL << HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */ -#define HCINTMSK_XFRCM HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */ +#define HCINTMSK_XFRCM_Msk (0x1UL << HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */ +#define HCINTMSK_XFRCM HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */ #define HCINTMSK_CHHM_Pos (1U) -#define HCINTMSK_CHHM_Msk (0x1UL << HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ -#define HCINTMSK_CHHM HCINTMSK_CHHM_Msk /*!< Channel halted mask */ +#define HCINTMSK_CHHM_Msk (0x1UL << HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ +#define HCINTMSK_CHHM HCINTMSK_CHHM_Msk /*!< Channel halted mask */ #define HCINTMSK_AHBERR_Pos (2U) -#define HCINTMSK_AHBERR_Msk (0x1UL << HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ -#define HCINTMSK_AHBERR HCINTMSK_AHBERR_Msk /*!< AHB error */ +#define HCINTMSK_AHBERR_Msk (0x1UL << HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ +#define HCINTMSK_AHBERR HCINTMSK_AHBERR_Msk /*!< AHB error */ #define HCINTMSK_STALLM_Pos (3U) -#define HCINTMSK_STALLM_Msk (0x1UL << HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ -#define HCINTMSK_STALLM HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ +#define HCINTMSK_STALLM_Msk (0x1UL << HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ +#define HCINTMSK_STALLM HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ #define HCINTMSK_NAKM_Pos (4U) -#define HCINTMSK_NAKM_Msk (0x1UL << HCINTMSK_NAKM_Pos) /*!< 0x00000010 */ -#define HCINTMSK_NAKM HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */ +#define HCINTMSK_NAKM_Msk (0x1UL << HCINTMSK_NAKM_Pos) /*!< 0x00000010 */ +#define HCINTMSK_NAKM HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */ #define HCINTMSK_ACKM_Pos (5U) -#define HCINTMSK_ACKM_Msk (0x1UL << HCINTMSK_ACKM_Pos) /*!< 0x00000020 */ -#define HCINTMSK_ACKM HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */ +#define HCINTMSK_ACKM_Msk (0x1UL << HCINTMSK_ACKM_Pos) /*!< 0x00000020 */ +#define HCINTMSK_ACKM HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */ #define HCINTMSK_NYET_Pos (6U) -#define HCINTMSK_NYET_Msk (0x1UL << HCINTMSK_NYET_Pos) /*!< 0x00000040 */ -#define HCINTMSK_NYET HCINTMSK_NYET_Msk /*!< response received interrupt mask */ +#define HCINTMSK_NYET_Msk (0x1UL << HCINTMSK_NYET_Pos) /*!< 0x00000040 */ +#define HCINTMSK_NYET HCINTMSK_NYET_Msk /*!< response received interrupt mask */ #define HCINTMSK_TXERRM_Pos (7U) -#define HCINTMSK_TXERRM_Msk (0x1UL << HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */ -#define HCINTMSK_TXERRM HCINTMSK_TXERRM_Msk /*!< Transaction error mask */ +#define HCINTMSK_TXERRM_Msk (0x1UL << HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */ +#define HCINTMSK_TXERRM HCINTMSK_TXERRM_Msk /*!< Transaction error mask */ #define HCINTMSK_BBERRM_Pos (8U) -#define HCINTMSK_BBERRM_Msk (0x1UL << HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */ -#define HCINTMSK_BBERRM HCINTMSK_BBERRM_Msk /*!< Babble error mask */ +#define HCINTMSK_BBERRM_Msk (0x1UL << HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */ +#define HCINTMSK_BBERRM HCINTMSK_BBERRM_Msk /*!< Babble error mask */ #define HCINTMSK_FRMORM_Pos (9U) -#define HCINTMSK_FRMORM_Msk (0x1UL << HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */ -#define HCINTMSK_FRMORM HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */ +#define HCINTMSK_FRMORM_Msk (0x1UL << HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */ +#define HCINTMSK_FRMORM HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */ #define HCINTMSK_DTERRM_Pos (10U) -#define HCINTMSK_DTERRM_Msk (0x1UL << HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */ -#define HCINTMSK_DTERRM HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */ +#define HCINTMSK_DTERRM_Msk (0x1UL << HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */ +#define HCINTMSK_DTERRM HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */ /******************** Bit definition for DIEPTSIZ register ********************/ #define DIEPTSIZ_XFRSIZ_Pos (0U) -#define DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ -#define DIEPTSIZ_XFRSIZ DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */ +#define DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ +#define DIEPTSIZ_XFRSIZ DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */ #define DIEPTSIZ_PKTCNT_Pos (19U) -#define DIEPTSIZ_PKTCNT_Msk (0x3FFUL << DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ -#define DIEPTSIZ_PKTCNT DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ +#define DIEPTSIZ_PKTCNT_Msk (0x3FFUL << DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ +#define DIEPTSIZ_PKTCNT DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ #define DIEPTSIZ_MULCNT_Pos (29U) -#define DIEPTSIZ_MULCNT_Msk (0x3UL << DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ -#define DIEPTSIZ_MULCNT DIEPTSIZ_MULCNT_Msk /*!< Packet count */ -/******************** Bit definition for HCTSIZ register ********************/ +#define DIEPTSIZ_MULCNT_Msk (0x3UL << DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ +#define DIEPTSIZ_MULCNT DIEPTSIZ_MULCNT_Msk /*!< Packet count */ + /******************** Bit definition for HCTSIZ register ********************/ #define HCTSIZ_XFRSIZ_Pos (0U) -#define HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ -#define HCTSIZ_XFRSIZ HCTSIZ_XFRSIZ_Msk /*!< Transfer size */ +#define HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ +#define HCTSIZ_XFRSIZ HCTSIZ_XFRSIZ_Msk /*!< Transfer size */ #define HCTSIZ_PKTCNT_Pos (19U) -#define HCTSIZ_PKTCNT_Msk (0x3FFUL << HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ -#define HCTSIZ_PKTCNT HCTSIZ_PKTCNT_Msk /*!< Packet count */ +#define HCTSIZ_PKTCNT_Msk (0x3FFUL << HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ +#define HCTSIZ_PKTCNT HCTSIZ_PKTCNT_Msk /*!< Packet count */ #define HCTSIZ_DOPING_Pos (31U) -#define HCTSIZ_DOPING_Msk (0x1UL << HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ -#define HCTSIZ_DOPING HCTSIZ_DOPING_Msk /*!< Do PING */ +#define HCTSIZ_DOPING_Msk (0x1UL << HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ +#define HCTSIZ_DOPING HCTSIZ_DOPING_Msk /*!< Do PING */ #define HCTSIZ_DPID_Pos (29U) -#define HCTSIZ_DPID_Msk (0x3UL << HCTSIZ_DPID_Pos) /*!< 0x60000000 */ -#define HCTSIZ_DPID HCTSIZ_DPID_Msk /*!< Data PID */ -#define HCTSIZ_DPID_0 (0x1UL << HCTSIZ_DPID_Pos) /*!< 0x20000000 */ -#define HCTSIZ_DPID_1 (0x2UL << HCTSIZ_DPID_Pos) /*!< 0x40000000 */ +#define HCTSIZ_DPID_Msk (0x3UL << HCTSIZ_DPID_Pos) /*!< 0x60000000 */ +#define HCTSIZ_DPID HCTSIZ_DPID_Msk /*!< Data PID */ +#define HCTSIZ_DPID_0 (0x1UL << HCTSIZ_DPID_Pos) /*!< 0x20000000 */ +#define HCTSIZ_DPID_1 (0x2UL << HCTSIZ_DPID_Pos) /*!< 0x40000000 */ /******************** Bit definition for DIEPDMA register ********************/ #define DIEPDMA_DMAADDR_Pos (0U) -#define DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */ -#define DIEPDMA_DMAADDR DIEPDMA_DMAADDR_Msk /*!< DMA address */ +#define DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */ +#define DIEPDMA_DMAADDR DIEPDMA_DMAADDR_Msk /*!< DMA address */ /******************** Bit definition for HCDMA register ********************/ #define HCDMA_DMAADDR_Pos (0U) -#define HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */ -#define HCDMA_DMAADDR HCDMA_DMAADDR_Msk /*!< DMA address */ +#define HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */ +#define HCDMA_DMAADDR HCDMA_DMAADDR_Msk /*!< DMA address */ -/******************** Bit definition for DTXFSTS register ********************/ + /******************** Bit definition for DTXFSTS register ********************/ #define DTXFSTS_INEPTFSAV_Pos (0U) -#define DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */ -#define DTXFSTS_INEPTFSAV DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */ +#define DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */ +#define DTXFSTS_INEPTFSAV DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */ -/******************** Bit definition for DIEPTXF register ********************/ + /******************** Bit definition for DIEPTXF register ********************/ #define DIEPTXF_INEPTXSA_Pos (0U) -#define DIEPTXF_INEPTXSA_Msk (0xFFFFUL << DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */ -#define DIEPTXF_INEPTXSA DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */ +#define DIEPTXF_INEPTXSA_Msk (0xFFFFUL << DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */ +#define DIEPTXF_INEPTXSA DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */ #define DIEPTXF_INEPTXFD_Pos (16U) -#define DIEPTXF_INEPTXFD_Msk (0xFFFFUL << DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */ -#define DIEPTXF_INEPTXFD DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */ +#define DIEPTXF_INEPTXFD_Msk (0xFFFFUL << DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */ +#define DIEPTXF_INEPTXFD DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */ /******************** Bit definition for DOEPCTL register ********************/ #define DOEPCTL_MPSIZ_Pos (0U) -#define DOEPCTL_MPSIZ_Msk (0x7FFUL << DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */ -#define DOEPCTL_MPSIZ DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*! Date: Tue, 26 Oct 2021 00:55:24 +0700 Subject: update dwc2_type --- src/portable/synopsys/dwc2/dcd_dwc2.c | 175 +-- src/portable/synopsys/dwc2/dwc2_stm32.h | 6 +- src/portable/synopsys/dwc2/dwc2_type.h | 2032 ++++++++++++++++--------------- 3 files changed, 1120 insertions(+), 1093 deletions(-) diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 7ae10652c..b98bd0055 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -30,6 +30,7 @@ #include "tusb_option.h" #include "device/dcd_attr.h" + #if TUSB_OPT_DEVICE_ENABLED && \ ( defined(DCD_ATTR_DWC2_STM32) || TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3, OPT_MCU_GD32VF103) ) @@ -51,7 +52,7 @@ //--------------------------------------------------------------------+ #define CORE_REG(_port) ((dwc2_core_t*) DWC2_REG_BASE) -#define DEVICE_REG(_port) ((dwc2_device_t*) (DWC2_REG_BASE + DWC2_DEVICE_BASE)) +#define DEVICE_REG(_port) CORE_REG(_port) //((dwc2_core_t*) (DWC2_REG_BASE + DWC2_DEVICE_BASE)) #define EPIN_REG(_port) ((dwc2_epin_t*) (DWC2_REG_BASE + DWC2_IN_ENDPOINT_BASE)) #define EPOUT_REG(_port) ((dwc2_epout_t*) (DWC2_REG_BASE + DWC2_OUT_ENDPOINT_BASE)) #define FIFO_BASE(_port, _x) ((volatile uint32_t*) (DWC2_REG_BASE + DWC2_FIFO_BASE + (_x) * DWC2_FIFO_SIZE)) @@ -63,6 +64,10 @@ enum DCD_FULL_SPEED = 3, // Full speed with internal PHY }; +// PHYSEL, ULPISEL +// UTMI internal HS PHY +// ULPI external HS PHY + static TU_ATTR_ALIGNED(4) uint32_t _setup_packet[2]; typedef struct { @@ -103,7 +108,7 @@ static void update_grxfsiz(uint8_t rhport) } // Update size of RX FIFO - core->GRXFSIZ = calc_rx_ff_size(max_epsize); + core->grxfsiz = calc_rx_ff_size(max_epsize); } // Setup the control endpoint 0. @@ -112,7 +117,7 @@ static void bus_reset(uint8_t rhport) (void) rhport; dwc2_core_t * core = CORE_REG(rhport); - dwc2_device_t * dev = DEVICE_REG(rhport); + dwc2_core_t * dev = DEVICE_REG(rhport); dwc2_epout_t * out_ep = EPOUT_REG(rhport); dwc2_epin_t * in_ep = EPIN_REG(rhport); @@ -120,7 +125,7 @@ static void bus_reset(uint8_t rhport) _out_ep_closed = false; // clear device address - dev->DCFG &= ~DCFG_DAD_Msk; + dev->dcfg &= ~DCFG_DAD_Msk; // 1. NAK for all OUT endpoints for(uint8_t n = 0; n < DWC2_EP_MAX; n++) { @@ -128,9 +133,9 @@ static void bus_reset(uint8_t rhport) } // 2. Un-mask interrupt bits - dev->DAINTMSK = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos); - dev->DOEPMSK = DOEPMSK_STUPM | DOEPMSK_XFRCM; - dev->DIEPMSK = DIEPMSK_TOM | DIEPMSK_XFRCM; + dev->daintmsk = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos); + dev->doepmsk = DOEPMSK_STUPM | DOEPMSK_XFRCM; + dev->diepmsk = DIEPMSK_TOM | DIEPMSK_XFRCM; // "USB Data FIFOs" section in reference manual // Peripheral FIFO architecture @@ -182,12 +187,12 @@ static void bus_reset(uint8_t rhport) // are enabled at least "2 x (Largest-EPsize/4) + 1" are recommended. Maybe provide a macro for application to // overwrite this. - core->GRXFSIZ = calc_rx_ff_size(TUD_OPT_HIGH_SPEED ? 512 : 64); + core->grxfsiz = calc_rx_ff_size(TUD_OPT_HIGH_SPEED ? 512 : 64); _allocated_fifo_words_tx = 16; // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word ) - core->DIEPTXF0_HNPTXFSIZ = (16 << TX0FD_Pos) | (DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx); + core->dieptxf0 = (16 << TX0FD_Pos) | (DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx); // Fixed control EP0 size to 64 bytes in_ep[0].DIEPCTL &= ~(0x03 << DIEPCTL_MPSIZ_Pos); @@ -195,15 +200,15 @@ static void bus_reset(uint8_t rhport) out_ep[0].DOEPTSIZ |= (3 << DOEPTSIZ_STUPCNT_Pos); - core->GINTMSK |= GINTMSK_OEPINT | GINTMSK_IEPINT; + core->gintmsk |= GINTMSK_OEPINT | GINTMSK_IEPINT; } static tusb_speed_t get_speed(uint8_t rhport) { (void) rhport; - dwc2_device_t * dev = DEVICE_REG(rhport); - uint32_t const enum_spd = (dev->DSTS & DSTS_ENUMSPD_Msk) >> DSTS_ENUMSPD_Pos; + dwc2_core_t * dev = DEVICE_REG(rhport); + uint32_t const enum_spd = (dev->dsts & DSTS_ENUMSPD_Msk) >> DSTS_ENUMSPD_Pos; return (enum_spd == DCD_HIGH_SPEED) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL; } @@ -220,11 +225,11 @@ static void set_speed(uint8_t rhport, tusb_speed_t speed) bitvalue = DCD_FULL_SPEED; } - dwc2_device_t * dev = DEVICE_REG(rhport); + dwc2_core_t * dev = DEVICE_REG(rhport); // Clear and set speed bits - dev->DCFG &= ~(3 << DCFG_DSPD_Pos); - dev->DCFG |= (bitvalue << DCFG_DSPD_Pos); + dev->dcfg &= ~(3 << DCFG_DSPD_Pos); + dev->dcfg |= (bitvalue << DCFG_DSPD_Pos); } #if defined(USB_HS_PHYC) @@ -272,7 +277,7 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c { (void) rhport; - dwc2_device_t * dev = DEVICE_REG(rhport); + dwc2_core_t * dev = DEVICE_REG(rhport); dwc2_epout_t * out_ep = EPOUT_REG(rhport); dwc2_epin_t * in_ep = EPIN_REG(rhport); @@ -296,12 +301,12 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c if ((in_ep[epnum].DIEPCTL & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) { // Take odd/even bit from frame counter. - uint32_t const odd_frame_now = (dev->DSTS & (1u << DSTS_FNSOF_Pos)); + uint32_t const odd_frame_now = (dev->dsts & (1u << DSTS_FNSOF_Pos)); in_ep[epnum].DIEPCTL |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk); } // Enable fifo empty interrupt only if there are something to put in the fifo. if(total_bytes != 0) { - dev->DIEPEMPMSK |= (1 << epnum); + dev->diepempmsk |= (1 << epnum); } } else { // A full OUT transfer (multiple packets, possibly) triggers XFRC. @@ -313,7 +318,7 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c if ((out_ep[epnum].DOEPCTL & DOEPCTL_EPTYP) == DOEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) { // Take odd/even bit from frame counter. - uint32_t const odd_frame_now = (dev->DSTS & (1u << DSTS_FNSOF_Pos)); + uint32_t const odd_frame_now = (dev->dsts & (1u << DSTS_FNSOF_Pos)); out_ep[epnum].DOEPCTL |= (odd_frame_now ? DOEPCTL_SD0PID_SEVNFRM_Msk : DOEPCTL_SODDFRM_Msk); } } @@ -336,23 +341,23 @@ void dcd_init (uint8_t rhport) // On selected MCUs HS port1 can be used with external PHY via ULPI interface #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED // deactivate internal PHY - core->GCCFG &= ~GCCFG_PWRDWN; + core->gccfg &= ~GCCFG_PWRDWN; // Init The UTMI Interface - core->GUSBCFG &= ~(GUSBCFG_TSDPS | GUSBCFG_ULPIFSLS | GUSBCFG_PHYSEL); + core->gusbcfg &= ~(GUSBCFG_TSDPS | GUSBCFG_ULPIFSLS | GUSBCFG_PHYSEL); // Select default internal VBUS Indicator and Drive for ULPI - core->GUSBCFG &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI); + core->gusbcfg &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI); #else - core->GUSBCFG |= GUSBCFG_PHYSEL; + core->gusbcfg |= GUSBCFG_PHYSEL; #endif #if defined(USB_HS_PHYC) // Highspeed with embedded UTMI PHYC // Select UTMI Interface - core->GUSBCFG &= ~GUSBCFG_ULPI_UTMI_SEL; - core->GCCFG |= GCCFG_PHYHSEN; + core->gusbcfg &= ~GUSBCFG_ULPI_UTMI_SEL; + core->gccfg |= GCCFG_PHYHSEN; // Enables control of a High Speed USB PHY USB_HS_PHYCInit(); @@ -360,42 +365,42 @@ void dcd_init (uint8_t rhport) } else { // Enable internal PHY - core->GUSBCFG |= GUSBCFG_PHYSEL; + core->gusbcfg |= GUSBCFG_PHYSEL; } // Reset core after selecting PHYst // Wait AHB IDLE, reset then wait until it is cleared - while ((core->GRSTCTL & GRSTCTL_AHBIDL) == 0U) {} - core->GRSTCTL |= GRSTCTL_CSRST; - while ((core->GRSTCTL & GRSTCTL_CSRST) == GRSTCTL_CSRST) {} + while ((core->grstctl & GRSTCTL_AHBIDL) == 0U) {} + core->grstctl |= GRSTCTL_CSRST; + while ((core->grstctl & GRSTCTL_CSRST) == GRSTCTL_CSRST) {} // Restart PHY clock *((volatile uint32_t *)(DWC2_REG_BASE + DWC2_PCGCCTL_BASE)) = 0; // Clear all interrupts - core->GINTSTS |= core->GINTSTS; + core->gintsts |= core->gintsts; // Required as part of core initialization. // TODO: How should mode mismatch be handled? It will cause // the core to stop working/require reset. - core->GINTMSK |= GINTMSK_OTGINT | GINTMSK_MMISM; + core->gintmsk |= GINTMSK_OTGINT | GINTMSK_MMISM; - dwc2_device_t * dev = DEVICE_REG(rhport); + dwc2_core_t * dev = DEVICE_REG(rhport); // If USB host misbehaves during status portion of control xfer // (non zero-length packet), send STALL back and discard. - dev->DCFG |= DCFG_NZLSOHSK; + dev->dcfg |= DCFG_NZLSOHSK; set_speed(rhport, TUD_OPT_HIGH_SPEED ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL); // Enable internal USB transceiver, unless using HS core (port 1) with external PHY. - if (!(rhport == 1 && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED))) core->GCCFG |= GCCFG_PWRDWN; + if (!(rhport == 1 && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED))) core->gccfg |= GCCFG_PWRDWN; - core->GINTMSK |= GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_USBSUSPM | + core->gintmsk |= GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_USBSUSPM | GINTMSK_WUIM | GINTMSK_RXFLVLM; // Enable global interrupt - core->GAHBCFG |= GAHBCFG_GINT; + core->gahbcfg |= GAHBCFG_GINT; dcd_connect(rhport); } @@ -412,8 +417,8 @@ void dcd_int_disable (uint8_t rhport) void dcd_set_address (uint8_t rhport, uint8_t dev_addr) { - dwc2_device_t * dev = DEVICE_REG(rhport); - dev->DCFG = (dev->DCFG & ~DCFG_DAD_Msk) | (dev_addr << DCFG_DAD_Pos); + dwc2_core_t * dev = DEVICE_REG(rhport); + dev->dcfg = (dev->dcfg & ~DCFG_DAD_Msk) | (dev_addr << DCFG_DAD_Pos); // Response with status after changing device address dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0); @@ -424,33 +429,33 @@ void dcd_remote_wakeup(uint8_t rhport) (void) rhport; dwc2_core_t * core = CORE_REG(rhport); - dwc2_device_t * dev = DEVICE_REG(rhport); + dwc2_core_t * dev = DEVICE_REG(rhport); // set remote wakeup - dev->DCTL |= DCTL_RWUSIG; + dev->dctl |= DCTL_RWUSIG; // enable SOF to detect bus resume - core->GINTSTS = GINTSTS_SOF; - core->GINTMSK |= GINTMSK_SOFM; + core->gintsts = GINTSTS_SOF; + core->gintmsk |= GINTMSK_SOFM; // Per specs: remote wakeup signal bit must be clear within 1-15ms dwc2_remote_wakeup_delay(); - dev->DCTL &= ~DCTL_RWUSIG; + dev->dctl &= ~DCTL_RWUSIG; } void dcd_connect(uint8_t rhport) { (void) rhport; - dwc2_device_t * dev = DEVICE_REG(rhport); - dev->DCTL &= ~DCTL_SDIS; + dwc2_core_t * dev = DEVICE_REG(rhport); + dev->dctl &= ~DCTL_SDIS; } void dcd_disconnect(uint8_t rhport) { (void) rhport; - dwc2_device_t * dev = DEVICE_REG(rhport); - dev->DCTL |= DCTL_SDIS; + dwc2_core_t * dev = DEVICE_REG(rhport); + dev->dctl |= DCTL_SDIS; } @@ -463,7 +468,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) (void) rhport; dwc2_core_t * core = CORE_REG(rhport); - dwc2_device_t * dev = DEVICE_REG(rhport); + dwc2_core_t * dev = DEVICE_REG(rhport); dwc2_epout_t * out_ep = EPOUT_REG(rhport); dwc2_epin_t * in_ep = EPIN_REG(rhport); @@ -484,12 +489,12 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) uint16_t const sz = calc_rx_ff_size(4*fifo_size); // If size_rx needs to be extended check if possible and if so enlarge it - if (core->GRXFSIZ < sz) + if (core->grxfsiz < sz) { TU_ASSERT(sz + _allocated_fifo_words_tx <= DWC2_EP_FIFO_SIZE/4); // Enlarge RX FIFO - core->GRXFSIZ = sz; + core->grxfsiz = sz; } out_ep[epnum].DOEPCTL |= (1 << DOEPCTL_USBAEP_Pos) | @@ -497,7 +502,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DOEPCTL_SD0PID_SEVNFRM : 0) | (xfer->max_size << DOEPCTL_MPSIZ_Pos); - dev->DAINTMSK |= (1 << (DAINTMSK_OEPM_Pos + epnum)); + dev->daintmsk |= (1 << (DAINTMSK_OEPM_Pos + epnum)); } else { @@ -523,7 +528,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n". // Check if free space is available - TU_ASSERT(_allocated_fifo_words_tx + fifo_size + core->GRXFSIZ <= DWC2_EP_FIFO_SIZE/4); + TU_ASSERT(_allocated_fifo_words_tx + fifo_size + core->grxfsiz <= DWC2_EP_FIFO_SIZE/4); _allocated_fifo_words_tx += fifo_size; @@ -531,7 +536,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) // DIEPTXF starts at FIFO #1. // Both TXFD and TXSA are in unit of 32-bit words. - core->DIEPTXF[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | (DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx); + core->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | (DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx); in_ep[epnum].DIEPCTL |= (1 << DIEPCTL_USBAEP_Pos) | (epnum << DIEPCTL_TXFNUM_Pos) | @@ -539,7 +544,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DIEPCTL_SD0PID_SEVNFRM : 0) | (xfer->max_size << DIEPCTL_MPSIZ_Pos); - dev->DAINTMSK |= (1 << (DAINTMSK_IEPM_Pos + epnum)); + dev->daintmsk |= (1 << (DAINTMSK_IEPM_Pos + epnum)); } return true; @@ -551,12 +556,12 @@ void dcd_edpt_close_all (uint8_t rhport) (void) rhport; // dwc2_core_t * core = CORE_REG(rhport); - dwc2_device_t * dev = DEVICE_REG(rhport); + dwc2_core_t * dev = DEVICE_REG(rhport); dwc2_epout_t * out_ep = EPOUT_REG(rhport); dwc2_epin_t * in_ep = EPIN_REG(rhport); // Disable non-control interrupt - dev->DAINTMSK = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos); + dev->daintmsk = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos); for(uint8_t n = 1; n < DWC2_EP_MAX; n++) { @@ -638,7 +643,7 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall) (void) rhport; dwc2_core_t * core = CORE_REG(rhport); - dwc2_device_t * dev = DEVICE_REG(rhport); + dwc2_core_t * dev = DEVICE_REG(rhport); dwc2_epout_t * out_ep = EPOUT_REG(rhport); dwc2_epin_t * in_ep = EPIN_REG(rhport); @@ -666,9 +671,9 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall) } // Flush the FIFO, and wait until we have confirmed it cleared. - core->GRSTCTL |= (epnum << GRSTCTL_TXFNUM_Pos); - core->GRSTCTL |= GRSTCTL_TXFFLSH; - while ( (core->GRSTCTL & GRSTCTL_TXFFLSH_Msk) != 0 ) {} + core->grstctl |= (epnum << GRSTCTL_TXFNUM_Pos); + core->grstctl |= GRSTCTL_TXFFLSH; + while ( (core->grstctl & GRSTCTL_TXFFLSH_Msk) != 0 ) {} } else { @@ -683,8 +688,8 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall) // Simpler to use polling here, we don't use the "B"OUTNAKEFF interrupt // anyway, and it can't be cleared by user code. If this while loop never // finishes, we have bigger problems than just the stack. - dev->DCTL |= DCTL_SGONAK; - while ( (core->GINTSTS & GINTSTS_BOUTNAKEFF_Msk) == 0 ) {} + dev->dctl |= DCTL_SGONAK; + while ( (core->gintsts & GINTSTS_BOUTNAKEFF_Msk) == 0 ) {} // Ditto here- disable the endpoint. out_ep[epnum].DOEPCTL |= DOEPCTL_EPDIS | (stall ? DOEPCTL_STALL : 0); @@ -693,7 +698,7 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall) out_ep[epnum].DOEPINT = DOEPINT_EPDISD; // Allow other OUT endpoints to keep receiving. - dev->DCTL |= DCTL_CGONAK; + dev->dctl |= DCTL_CGONAK; } } } @@ -715,8 +720,8 @@ void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr) if (dir == TUSB_DIR_IN) { - uint16_t const fifo_size = (core->DIEPTXF[epnum - 1] & DIEPTXF_INEPTXFD_Msk) >> DIEPTXF_INEPTXFD_Pos; - uint16_t const fifo_start = (core->DIEPTXF[epnum - 1] & DIEPTXF_INEPTXSA_Msk) >> DIEPTXF_INEPTXSA_Pos; + uint16_t const fifo_size = (core->dieptxf[epnum - 1] & DIEPTXF_INEPTXFD_Msk) >> DIEPTXF_INEPTXFD_Pos; + uint16_t const fifo_start = (core->dieptxf[epnum - 1] & DIEPTXF_INEPTXSA_Msk) >> DIEPTXF_INEPTXSA_Pos; // For now only the last opened endpoint can be closed without fuss. TU_ASSERT(fifo_start == DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx,); _allocated_fifo_words_tx -= fifo_size; @@ -831,7 +836,7 @@ static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep) { volatile uint32_t * rx_fifo = FIFO_BASE(rhport, 0); // Pop control word off FIFO - uint32_t ctl_word = core->GRXSTSP; + uint32_t ctl_word = core->grxstsp; uint8_t pktsts = (ctl_word & GRXSTSP_PKTSTS_Msk) >> GRXSTSP_PKTSTS_Pos; uint8_t epnum = (ctl_word & GRXSTSP_EPNUM_Msk) >> GRXSTSP_EPNUM_Pos; uint16_t bcnt = (ctl_word & GRXSTSP_BCNT_Msk) >> GRXSTSP_BCNT_Pos; @@ -891,7 +896,7 @@ static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep) { } } -static void handle_epout_ints (uint8_t rhport, dwc2_device_t *dev, dwc2_epout_t *out_ep) +static void handle_epout_ints (uint8_t rhport, dwc2_core_t *dev, dwc2_epout_t *out_ep) { // DAINT for a given EP clears when DOEPINTx is cleared. // OEPINT will be cleared when DAINT's out bits are cleared. @@ -899,7 +904,7 @@ static void handle_epout_ints (uint8_t rhport, dwc2_device_t *dev, dwc2_epout_t { xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT); - if ( dev->DAINT & (1 << (DAINT_OEPINT_Pos + n)) ) + if ( dev->daint & (1 << (DAINT_OEPINT_Pos + n)) ) { // SETUP packet Setup Phase done. if ( out_ep[n].DOEPINT & DOEPINT_STUP ) @@ -928,14 +933,14 @@ static void handle_epout_ints (uint8_t rhport, dwc2_device_t *dev, dwc2_epout_t } } -static void handle_epin_ints(uint8_t rhport, dwc2_device_t * dev, dwc2_epin_t * in_ep) { +static void handle_epin_ints(uint8_t rhport, dwc2_core_t * dev, dwc2_epin_t * in_ep) { // DAINT for a given EP clears when DIEPINTx is cleared. // IEPINT will be cleared when DAINT's out bits are cleared. for ( uint8_t n = 0; n < DWC2_EP_MAX; n++ ) { xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_IN); - if ( dev->DAINT & (1 << (DAINT_IEPINT_Pos + n)) ) + if ( dev->daint & (1 << (DAINT_IEPINT_Pos + n)) ) { // IN XFER complete (entire xfer). if ( in_ep[n].DIEPINT & DIEPINT_XFRC ) @@ -952,7 +957,7 @@ static void handle_epin_ints(uint8_t rhport, dwc2_device_t * dev, dwc2_epin_t * } // XFER FIFO empty - if ( (in_ep[n].DIEPINT & DIEPINT_TXFE) && (dev->DIEPEMPMSK & (1 << n)) ) + if ( (in_ep[n].DIEPINT & DIEPINT_TXFE) && (dev->diepempmsk & (1 << n)) ) { // DIEPINT's TXFE bit is read-only, software cannot clear it. // It will only be cleared by hardware when written bytes is more than @@ -991,7 +996,7 @@ static void handle_epin_ints(uint8_t rhport, dwc2_device_t * dev, dwc2_epin_t * // Turn off TXFE if all bytes are written. if (((in_ep[n].DIEPTSIZ & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos) == 0) { - dev->DIEPEMPMSK &= ~(1 << n); + dev->diepempmsk &= ~(1 << n); } } } @@ -1001,16 +1006,16 @@ static void handle_epin_ints(uint8_t rhport, dwc2_device_t * dev, dwc2_epin_t * void dcd_int_handler(uint8_t rhport) { dwc2_core_t * core = CORE_REG(rhport); - dwc2_device_t * dev = DEVICE_REG(rhport); + dwc2_core_t * dev = DEVICE_REG(rhport); dwc2_epout_t * out_ep = EPOUT_REG(rhport); dwc2_epin_t * in_ep = EPIN_REG(rhport); - uint32_t const int_status = core->GINTSTS & core->GINTMSK; + uint32_t const int_status = core->gintsts & core->gintmsk; if(int_status & GINTSTS_USBRST) { // USBRST is start of reset. - core->GINTSTS = GINTSTS_USBRST; + core->gintsts = GINTSTS_USBRST; bus_reset(rhport); } @@ -1018,7 +1023,7 @@ void dcd_int_handler(uint8_t rhport) { // ENUMDNE is the end of reset where speed of the link is detected - core->GINTSTS = GINTSTS_ENUMDNE; + core->gintsts = GINTSTS_ENUMDNE; tusb_speed_t const speed = get_speed(rhport); @@ -1028,13 +1033,13 @@ void dcd_int_handler(uint8_t rhport) if(int_status & GINTSTS_USBSUSP) { - core->GINTSTS = GINTSTS_USBSUSP; + core->gintsts = GINTSTS_USBSUSP; dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); } if(int_status & GINTSTS_WKUINT) { - core->GINTSTS = GINTSTS_WKUINT; + core->gintsts = GINTSTS_WKUINT; dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true); } @@ -1044,22 +1049,22 @@ void dcd_int_handler(uint8_t rhport) if(int_status & GINTSTS_OTGINT) { // OTG INT bit is read-only - uint32_t const otg_int = core->GOTGINT; + uint32_t const otg_int = core->gotgint; if (otg_int & GOTGINT_SEDET) { dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true); } - core->GOTGINT = otg_int; + core->gotgint = otg_int; } if(int_status & GINTSTS_SOF) { - core->GINTSTS = GINTSTS_SOF; + core->gotgint = GINTSTS_SOF; // Disable SOF interrupt since currently only used for remote wakeup detection - core->GINTMSK &= ~GINTMSK_SOFM; + core->gintmsk &= ~GINTMSK_SOFM; dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true); } @@ -1070,13 +1075,13 @@ void dcd_int_handler(uint8_t rhport) // RXFLVL bit is read-only // Mask out RXFLVL while reading data from FIFO - core->GINTMSK &= ~GINTMSK_RXFLVLM; + core->gintmsk &= ~GINTMSK_RXFLVLM; // Loop until all available packets were handled do { handle_rxflvl_ints(rhport, out_ep); - } while(core->GINTSTS & GINTSTS_RXFLVL); + } while(core->gotgint & GINTSTS_RXFLVL); // Manage RX FIFO size if (_out_ep_closed) @@ -1087,7 +1092,7 @@ void dcd_int_handler(uint8_t rhport) _out_ep_closed = false; } - core->GINTMSK |= GINTMSK_RXFLVLM; + core->gintmsk |= GINTMSK_RXFLVLM; } // OUT endpoint interrupt handling. diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h index 2a6d58e9a..d2ad8abb7 100644 --- a/src/portable/synopsys/dwc2/dwc2_stm32.h +++ b/src/portable/synopsys/dwc2/dwc2_stm32.h @@ -115,12 +115,12 @@ static inline void dwc2_remote_wakeup_delay(void) // Set turn-around timeout according to link speed static inline void dwc2_set_turnaround(dwc2_core_t * core, tusb_speed_t speed) { - core->GUSBCFG &= ~GUSBCFG_TRDT; + core->gusbcfg &= ~GUSBCFG_TRDT; if ( speed == TUSB_SPEED_HIGH ) { // Use fixed 0x09 for Highspeed - core->GUSBCFG |= (0x09 << GUSBCFG_TRDT_Pos); + core->gusbcfg |= (0x09 << GUSBCFG_TRDT_Pos); } else { @@ -149,7 +149,7 @@ static inline void dwc2_set_turnaround(dwc2_core_t * core, tusb_speed_t speed) turnaround = 0xFU; // Fullspeed depends on MCU clocks, but we will use 0x06 for 32+ Mhz - core->GUSBCFG |= (turnaround << GUSBCFG_TRDT_Pos); + core->gusbcfg |= (turnaround << GUSBCFG_TRDT_Pos); } } diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index 8d12e21ce..b83ac67f9 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -27,120 +27,142 @@ // HS PHY typedef struct { - volatile uint32_t HS_PHYC_PLL; /*!< This register is used to control the PLL of the HS PHY. 000h */ - volatile uint32_t Reserved04; /*!< Reserved 004h */ - volatile uint32_t Reserved08; /*!< Reserved 008h */ - volatile uint32_t HS_PHYC_TUNE; /*!< This register is used to control the tuning interface of the High Speed PHY. 00Ch */ - volatile uint32_t Reserved10; /*!< Reserved 010h */ - volatile uint32_t Reserved14; /*!< Reserved 014h */ - volatile uint32_t HS_PHYC_LDO; /*!< This register is used to control the regulator (LDO). 018h */ + volatile uint32_t HS_PHYC_PLL; // This register is used to control the PLL of the HS PHY. 000h */ + volatile uint32_t Reserved04; // Reserved 004h */ + volatile uint32_t Reserved08; // Reserved 008h */ + volatile uint32_t HS_PHYC_TUNE; // This register is used to control the tuning interface of the High Speed PHY. 00Ch */ + volatile uint32_t Reserved10; // Reserved 010h */ + volatile uint32_t Reserved14; // Reserved 014h */ + volatile uint32_t HS_PHYC_LDO; // This register is used to control the regulator (LDO). 018h */ } HS_PHYC_GlobalTypeDef; #endif -// Core -typedef struct -{ - volatile uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ - volatile uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ - volatile uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ - volatile uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ - volatile uint32_t GRSTCTL; /*!< Core Reset Register 010h */ - volatile uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ - volatile uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ - volatile uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ - volatile uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ - volatile uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ - volatile uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */ - volatile uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ - uint32_t Reserved30[2]; /*!< Reserved 030h */ - volatile uint32_t GCCFG; /*!< General Purpose IO Register 038h */ - volatile uint32_t CID; /*!< User ID Register 03Ch */ - volatile uint32_t GSNPSID; /* USB_OTG core ID 040h*/ - volatile uint32_t GHWCFG1; /* User HW config1 044h*/ - volatile uint32_t GHWCFG2; /* User HW config2 048h*/ - volatile uint32_t GHWCFG3; /*!< User HW config3 04Ch */ - uint32_t Reserved6; /*!< Reserved 050h */ - volatile uint32_t GLPMCFG; /*!< LPM Register 054h */ - volatile uint32_t GPWRDN; /*!< Power Down Register 058h */ - volatile uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */ - volatile uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */ - uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */ - volatile uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */ - volatile uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO 104h-13Ch */ -} dwc2_core_t; - -// Host -typedef struct -{ - volatile uint32_t HCFG; /*!< Host Configuration Register 400h */ - volatile uint32_t HFIR; /*!< Host Frame Interval Register 404h */ - volatile uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */ - uint32_t Reserved40C; /*!< Reserved 40Ch */ - volatile uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */ - volatile uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */ - volatile uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ -} dwc2_host_t; - // Host Channel typedef struct { - volatile uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */ - volatile uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */ - volatile uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */ - volatile uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */ - volatile uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */ - volatile uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */ - uint32_t Reserved[2]; /*!< Reserved */ + volatile uint32_t hcchar; // 500 + 20n Host Channel Characteristics Register + volatile uint32_t hcsplt; // 504 + 20n Host Channel Split Control Register + volatile uint32_t hcint; // 508 + 20n Host Channel Interrupt Register + volatile uint32_t hcintmsk; // 50C + 20n Host Channel Interrupt Mask Register + volatile uint32_t hctsiz; // 510 + 20n Host Channel Transfer Size Register + volatile uint32_t hcdma; // 514 + 20n Host Channel DMA Address Register + uint32_t reserved518; // 518 + 20n + volatile uint32_t hcdmab; // 51C + 20n Host Channel DMA Address Register } dwc2_channel_t; -// Device typedef struct { - volatile uint32_t DCFG; /*!< dev Configuration Register 800h */ - volatile uint32_t DCTL; /*!< dev Control Register 804h */ - volatile uint32_t DSTS; /*!< dev Status Register (RO) 808h */ - uint32_t Reserved0C; /*!< Reserved 80Ch */ - volatile uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ - volatile uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ - volatile uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ - volatile uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ - uint32_t Reserved20; /*!< Reserved 820h */ - uint32_t Reserved9; /*!< Reserved 824h */ - volatile uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ - volatile uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ - volatile uint32_t DTHRCTL; /*!< dev threshold 830h */ - volatile uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ - volatile uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ - volatile uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ - uint32_t Reserved40; /*!< dedicated EP mask 840h */ - volatile uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ - uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ - volatile uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ -} dwc2_device_t; + //------------- Core Global -------------// + volatile uint32_t gotgctl; // 000 OTG Control and Status Register + volatile uint32_t gotgint; // 004 OTG Interrupt Register + volatile uint32_t gahbcfg; // 008 AHB Configuration Register + volatile uint32_t gusbcfg; // 00c USB Configuration Register + volatile uint32_t grstctl; // 010 Reset Register + volatile uint32_t gintsts; // 014 Interrupt Register + volatile uint32_t gintmsk; // 018 Interrupt Mask Register + volatile uint32_t grxstsr; // 01c Receive Status Debug Read Register + volatile uint32_t grxstsp; // 020 Receive Status Read/Pop Register + volatile uint32_t grxfsiz; // 024 Receive FIFO Size Register +union { + volatile uint32_t dieptxf0; // 028 EP0 Tx FIFO Size Register + volatile uint32_t gnptxfsiz; // 028 Non-periodic Transmit FIFO Size Register +}; + volatile uint32_t gnptxsts; // 02c Non-periodic Transmit FIFO/Queue Status Register + volatile uint32_t gi2cctl; // 030 I2C Address Register + volatile uint32_t gpvndctl; // 034 PHY Vendor Control Register +union { + volatile uint32_t ggpio; // 038 General Purpose IO Register + volatile uint32_t gccfg; // 038 STM32 General Core Configuration +}; + volatile uint32_t guid; // 03C User ID Register + volatile uint32_t gsnpsid; // 040 Synopsys ID Register + volatile uint32_t ghwcfg1; // 044 User Hardware Configuration 1 Register + volatile uint32_t ghwcfg2; // 048 User Hardware Configuration 2 Register + volatile uint32_t ghwcfg3; // 04C User Hardware Configuration 3 Register + volatile uint32_t ghwcfg4; // 050 User Hardware Configuration 4 Register + volatile uint32_t glpmcfg; // 054 Core LPM Configuration Register + volatile uint32_t gpwrdn; // 058 Power Down Register + volatile uint32_t gdfifocfg; // 05C DFIFO Software Configuration Register + volatile uint32_t gadpctl; // 060 ADP Timer, Control and Status Register + + uint32_t reserved64[39]; // 064..0FF + volatile uint32_t hptxfsiz; // 100 Host Periodic Tx FIFO Size Register + volatile uint32_t dieptxf[15]; // 104..13C Device Periodic Transmit FIFO Size Register + uint32_t reserved140[176]; // 140..3FC + + //------------- Host -------------// + volatile uint32_t hcfg; // 400 Host Configuration Register + volatile uint32_t hfir; // 404 Host Frame Interval Register + volatile uint32_t hfnum; // 408 Host Frame Number / Frame Remaining + uint32_t reserved40c; // 40C + volatile uint32_t hptxsts; // 410 Host Periodic TX FIFO / Queue Status + volatile uint32_t haint; // 414 Host All Channels Interrupt Register + volatile uint32_t haintmsk; // 418 Host All Channels Interrupt Mask + volatile uint32_t hflbaddr; // 41C Host Frame List Base Address Register + uint32_t reserved420[8]; // 420..43C + volatile uint32_t hprt; // 440 Host Port Control and Status + uint32_t reserved444[47]; // 444..4FC + + //------------- Host Channel -------------// + dwc2_channel_t channel[16]; // 500..6FC Host Channels 0-15 + + uint32_t reserved700[64]; // 700..7FC + + //------------- Device -------------// + volatile uint32_t dcfg; // 800 Device Configuration Register + volatile uint32_t dctl; // 804 Device Control Register + volatile uint32_t dsts; // 808 Device Status Register (RO) + uint32_t reserved80c; // 80C + volatile uint32_t diepmsk; // 810 Device IN Endpoint Interrupt Mask + volatile uint32_t doepmsk; // 814 Device OUT Endpoint Interrupt Mask + volatile uint32_t daint; // 818 Device All Endpoints Interrupt + volatile uint32_t daintmsk; // 81C Device All Endpoints Interrupt Mask + volatile uint32_t dtknqr1; // 820 Device IN token sequence learning queue read register1 + volatile uint32_t dtknqr2; // 824 Device IN token sequence learning queue read register2 + volatile uint32_t dvbusdis; // 828 Device VBUS Discharge Time Register + volatile uint32_t dvbuspulse; // 82C Device VBUS Pulsing Time Register + volatile uint32_t dthrctl; // 830 Device threshold Control + volatile uint32_t diepempmsk; // 834 Device IN Endpoint FIFO Empty Interrupt Mask + + volatile uint32_t deachint; // 838 Device Each Endpoint Interrupt + volatile uint32_t deachmsk; // 83C Device Each Endpoint Interrupt msk + volatile uint32_t diepeachmsk[16]; // 840..87C Device Each IN Endpoint mask + volatile uint32_t doepeachmsk[16]; // 880..8BC Device Each OUT Endpoint mask + uint32_t reserved8c0[16]; // 8C0..8FC + + //------------- Device IN Endpoint -------------// + + + //------------- Device OUT Endpoint -------------// +} dwc2_core_t; + +TU_VERIFY_STATIC(offsetof(dwc2_core_t, hcfg ) == 0x0400, "incorrect size"); +TU_VERIFY_STATIC(offsetof(dwc2_core_t, channel) == 0x0500, "incorrect size"); +TU_VERIFY_STATIC(offsetof(dwc2_core_t, dcfg ) == 0x0800, "incorrect size"); // Endpoint IN typedef struct { - volatile uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ - uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ - volatile uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ - uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ - volatile uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ - volatile uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ - volatile uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ - uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ + volatile uint32_t DIEPCTL; // dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; // Reserved 900h + (ep_num * 20h) + 04h */ + volatile uint32_t DIEPINT; // dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; // Reserved 900h + (ep_num * 20h) + 0Ch */ + volatile uint32_t DIEPTSIZ; // IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ + volatile uint32_t DIEPDMA; // IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ + volatile uint32_t DTXFSTS; // IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ + uint32_t Reserved18; // Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ } dwc2_epin_t; // Endpoint OUT typedef struct { - volatile uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ - uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ - volatile uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ - uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ - volatile uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ - volatile uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ - uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ + volatile uint32_t DOEPCTL; // dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; // Reserved B00h + (ep_num * 20h) + 04h */ + volatile uint32_t DOEPINT; // dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; // Reserved B00h + (ep_num * 20h) + 0Ch */ + volatile uint32_t DOEPTSIZ; // dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ + volatile uint32_t DOEPDMA; // dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ + uint32_t Reserved18[2]; // Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ } dwc2_epout_t; @@ -167,1427 +189,1427 @@ typedef struct /******************** Bit definition for GOTGCTL register ********************/ #define GOTGCTL_SRQSCS_Pos (0U) -#define GOTGCTL_SRQSCS_Msk (0x1UL << GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */ -#define GOTGCTL_SRQSCS GOTGCTL_SRQSCS_Msk /*!< Session request success */ +#define GOTGCTL_SRQSCS_Msk (0x1UL << GOTGCTL_SRQSCS_Pos) // 0x00000001 */ +#define GOTGCTL_SRQSCS GOTGCTL_SRQSCS_Msk // Session request success */ #define GOTGCTL_SRQ_Pos (1U) -#define GOTGCTL_SRQ_Msk (0x1UL << GOTGCTL_SRQ_Pos) /*!< 0x00000002 */ -#define GOTGCTL_SRQ GOTGCTL_SRQ_Msk /*!< Session request */ +#define GOTGCTL_SRQ_Msk (0x1UL << GOTGCTL_SRQ_Pos) // 0x00000002 */ +#define GOTGCTL_SRQ GOTGCTL_SRQ_Msk // Session request */ #define GOTGCTL_VBVALOEN_Pos (2U) -#define GOTGCTL_VBVALOEN_Msk (0x1UL << GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */ -#define GOTGCTL_VBVALOEN GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */ +#define GOTGCTL_VBVALOEN_Msk (0x1UL << GOTGCTL_VBVALOEN_Pos) // 0x00000004 */ +#define GOTGCTL_VBVALOEN GOTGCTL_VBVALOEN_Msk // VBUS valid override enable */ #define GOTGCTL_VBVALOVAL_Pos (3U) -#define GOTGCTL_VBVALOVAL_Msk (0x1UL << GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */ -#define GOTGCTL_VBVALOVAL GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */ +#define GOTGCTL_VBVALOVAL_Msk (0x1UL << GOTGCTL_VBVALOVAL_Pos) // 0x00000008 */ +#define GOTGCTL_VBVALOVAL GOTGCTL_VBVALOVAL_Msk // VBUS valid override value */ #define GOTGCTL_AVALOEN_Pos (4U) -#define GOTGCTL_AVALOEN_Msk (0x1UL << GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */ -#define GOTGCTL_AVALOEN GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */ +#define GOTGCTL_AVALOEN_Msk (0x1UL << GOTGCTL_AVALOEN_Pos) // 0x00000010 */ +#define GOTGCTL_AVALOEN GOTGCTL_AVALOEN_Msk // A-peripheral session valid override enable */ #define GOTGCTL_AVALOVAL_Pos (5U) -#define GOTGCTL_AVALOVAL_Msk (0x1UL << GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */ -#define GOTGCTL_AVALOVAL GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */ +#define GOTGCTL_AVALOVAL_Msk (0x1UL << GOTGCTL_AVALOVAL_Pos) // 0x00000020 */ +#define GOTGCTL_AVALOVAL GOTGCTL_AVALOVAL_Msk // A-peripheral session valid override value */ #define GOTGCTL_BVALOEN_Pos (6U) -#define GOTGCTL_BVALOEN_Msk (0x1UL << GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */ -#define GOTGCTL_BVALOEN GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */ +#define GOTGCTL_BVALOEN_Msk (0x1UL << GOTGCTL_BVALOEN_Pos) // 0x00000040 */ +#define GOTGCTL_BVALOEN GOTGCTL_BVALOEN_Msk // B-peripheral session valid override enable */ #define GOTGCTL_BVALOVAL_Pos (7U) -#define GOTGCTL_BVALOVAL_Msk (0x1UL << GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */ -#define GOTGCTL_BVALOVAL GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */ +#define GOTGCTL_BVALOVAL_Msk (0x1UL << GOTGCTL_BVALOVAL_Pos) // 0x00000080 */ +#define GOTGCTL_BVALOVAL GOTGCTL_BVALOVAL_Msk // B-peripheral session valid override value */ #define GOTGCTL_HNGSCS_Pos (8U) -#define GOTGCTL_HNGSCS_Msk (0x1UL << GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */ -#define GOTGCTL_HNGSCS GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */ +#define GOTGCTL_HNGSCS_Msk (0x1UL << GOTGCTL_HNGSCS_Pos) // 0x00000100 */ +#define GOTGCTL_HNGSCS GOTGCTL_HNGSCS_Msk // Host set HNP enable */ #define GOTGCTL_HNPRQ_Pos (9U) -#define GOTGCTL_HNPRQ_Msk (0x1UL << GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */ -#define GOTGCTL_HNPRQ GOTGCTL_HNPRQ_Msk /*!< HNP request */ +#define GOTGCTL_HNPRQ_Msk (0x1UL << GOTGCTL_HNPRQ_Pos) // 0x00000200 */ +#define GOTGCTL_HNPRQ GOTGCTL_HNPRQ_Msk // HNP request */ #define GOTGCTL_HSHNPEN_Pos (10U) -#define GOTGCTL_HSHNPEN_Msk (0x1UL << GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */ -#define GOTGCTL_HSHNPEN GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */ +#define GOTGCTL_HSHNPEN_Msk (0x1UL << GOTGCTL_HSHNPEN_Pos) // 0x00000400 */ +#define GOTGCTL_HSHNPEN GOTGCTL_HSHNPEN_Msk // Host set HNP enable */ #define GOTGCTL_DHNPEN_Pos (11U) -#define GOTGCTL_DHNPEN_Msk (0x1UL << GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */ -#define GOTGCTL_DHNPEN GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */ +#define GOTGCTL_DHNPEN_Msk (0x1UL << GOTGCTL_DHNPEN_Pos) // 0x00000800 */ +#define GOTGCTL_DHNPEN GOTGCTL_DHNPEN_Msk // Device HNP enabled */ #define GOTGCTL_EHEN_Pos (12U) -#define GOTGCTL_EHEN_Msk (0x1UL << GOTGCTL_EHEN_Pos) /*!< 0x00001000 */ -#define GOTGCTL_EHEN GOTGCTL_EHEN_Msk /*!< Embedded host enable */ +#define GOTGCTL_EHEN_Msk (0x1UL << GOTGCTL_EHEN_Pos) // 0x00001000 */ +#define GOTGCTL_EHEN GOTGCTL_EHEN_Msk // Embedded host enable */ #define GOTGCTL_CIDSTS_Pos (16U) -#define GOTGCTL_CIDSTS_Msk (0x1UL << GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ -#define GOTGCTL_CIDSTS GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ +#define GOTGCTL_CIDSTS_Msk (0x1UL << GOTGCTL_CIDSTS_Pos) // 0x00010000 */ +#define GOTGCTL_CIDSTS GOTGCTL_CIDSTS_Msk // Connector ID status */ #define GOTGCTL_DBCT_Pos (17U) -#define GOTGCTL_DBCT_Msk (0x1UL << GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ -#define GOTGCTL_DBCT GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ +#define GOTGCTL_DBCT_Msk (0x1UL << GOTGCTL_DBCT_Pos) // 0x00020000 */ +#define GOTGCTL_DBCT GOTGCTL_DBCT_Msk // Long/short debounce time */ #define GOTGCTL_ASVLD_Pos (18U) -#define GOTGCTL_ASVLD_Msk (0x1UL << GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ -#define GOTGCTL_ASVLD GOTGCTL_ASVLD_Msk /*!< A-session valid */ +#define GOTGCTL_ASVLD_Msk (0x1UL << GOTGCTL_ASVLD_Pos) // 0x00040000 */ +#define GOTGCTL_ASVLD GOTGCTL_ASVLD_Msk // A-session valid */ #define GOTGCTL_BSESVLD_Pos (19U) -#define GOTGCTL_BSESVLD_Msk (0x1UL << GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */ -#define GOTGCTL_BSESVLD GOTGCTL_BSESVLD_Msk /*!< B-session valid */ +#define GOTGCTL_BSESVLD_Msk (0x1UL << GOTGCTL_BSESVLD_Pos) // 0x00080000 */ +#define GOTGCTL_BSESVLD GOTGCTL_BSESVLD_Msk // B-session valid */ #define GOTGCTL_OTGVER_Pos (20U) -#define GOTGCTL_OTGVER_Msk (0x1UL << GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ -#define GOTGCTL_OTGVER GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define GOTGCTL_OTGVER_Msk (0x1UL << GOTGCTL_OTGVER_Pos) // 0x00100000 */ +#define GOTGCTL_OTGVER GOTGCTL_OTGVER_Msk // OTG version */ /******************** Bit definition for HCFG register ********************/ #define HCFG_FSLSPCS_Pos (0U) -#define HCFG_FSLSPCS_Msk (0x3UL << HCFG_FSLSPCS_Pos) /*!< 0x00000003 */ -#define HCFG_FSLSPCS HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */ -#define HCFG_FSLSPCS_0 (0x1UL << HCFG_FSLSPCS_Pos) /*!< 0x00000001 */ -#define HCFG_FSLSPCS_1 (0x2UL << HCFG_FSLSPCS_Pos) /*!< 0x00000002 */ +#define HCFG_FSLSPCS_Msk (0x3UL << HCFG_FSLSPCS_Pos) // 0x00000003 */ +#define HCFG_FSLSPCS HCFG_FSLSPCS_Msk // FS/LS PHY clock select */ +#define HCFG_FSLSPCS_0 (0x1UL << HCFG_FSLSPCS_Pos) // 0x00000001 */ +#define HCFG_FSLSPCS_1 (0x2UL << HCFG_FSLSPCS_Pos) // 0x00000002 */ #define HCFG_FSLSS_Pos (2U) -#define HCFG_FSLSS_Msk (0x1UL << HCFG_FSLSS_Pos) /*!< 0x00000004 */ -#define HCFG_FSLSS HCFG_FSLSS_Msk /*!< FS- and LS-only support */ +#define HCFG_FSLSS_Msk (0x1UL << HCFG_FSLSS_Pos) // 0x00000004 */ +#define HCFG_FSLSS HCFG_FSLSS_Msk // FS- and LS-only support */ /******************** Bit definition for DCFG register ********************/ #define DCFG_DSPD_Pos (0U) -#define DCFG_DSPD_Msk (0x3UL << DCFG_DSPD_Pos) /*!< 0x00000003 */ -#define DCFG_DSPD DCFG_DSPD_Msk /*!< Device speed */ -#define DCFG_DSPD_0 (0x1UL << DCFG_DSPD_Pos) /*!< 0x00000001 */ -#define DCFG_DSPD_1 (0x2UL << DCFG_DSPD_Pos) /*!< 0x00000002 */ +#define DCFG_DSPD_Msk (0x3UL << DCFG_DSPD_Pos) // 0x00000003 */ +#define DCFG_DSPD DCFG_DSPD_Msk // Device speed */ +#define DCFG_DSPD_0 (0x1UL << DCFG_DSPD_Pos) // 0x00000001 */ +#define DCFG_DSPD_1 (0x2UL << DCFG_DSPD_Pos) // 0x00000002 */ #define DCFG_NZLSOHSK_Pos (2U) -#define DCFG_NZLSOHSK_Msk (0x1UL << DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */ -#define DCFG_NZLSOHSK DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */ +#define DCFG_NZLSOHSK_Msk (0x1UL << DCFG_NZLSOHSK_Pos) // 0x00000004 */ +#define DCFG_NZLSOHSK DCFG_NZLSOHSK_Msk // Nonzero-length status OUT handshake */ #define DCFG_DAD_Pos (4U) -#define DCFG_DAD_Msk (0x7FUL << DCFG_DAD_Pos) /*!< 0x000007F0 */ -#define DCFG_DAD DCFG_DAD_Msk /*!< Device address */ -#define DCFG_DAD_0 (0x01UL << DCFG_DAD_Pos) /*!< 0x00000010 */ -#define DCFG_DAD_1 (0x02UL << DCFG_DAD_Pos) /*!< 0x00000020 */ -#define DCFG_DAD_2 (0x04UL << DCFG_DAD_Pos) /*!< 0x00000040 */ -#define DCFG_DAD_3 (0x08UL << DCFG_DAD_Pos) /*!< 0x00000080 */ -#define DCFG_DAD_4 (0x10UL << DCFG_DAD_Pos) /*!< 0x00000100 */ -#define DCFG_DAD_5 (0x20UL << DCFG_DAD_Pos) /*!< 0x00000200 */ -#define DCFG_DAD_6 (0x40UL << DCFG_DAD_Pos) /*!< 0x00000400 */ +#define DCFG_DAD_Msk (0x7FUL << DCFG_DAD_Pos) // 0x000007F0 */ +#define DCFG_DAD DCFG_DAD_Msk // Device address */ +#define DCFG_DAD_0 (0x01UL << DCFG_DAD_Pos) // 0x00000010 */ +#define DCFG_DAD_1 (0x02UL << DCFG_DAD_Pos) // 0x00000020 */ +#define DCFG_DAD_2 (0x04UL << DCFG_DAD_Pos) // 0x00000040 */ +#define DCFG_DAD_3 (0x08UL << DCFG_DAD_Pos) // 0x00000080 */ +#define DCFG_DAD_4 (0x10UL << DCFG_DAD_Pos) // 0x00000100 */ +#define DCFG_DAD_5 (0x20UL << DCFG_DAD_Pos) // 0x00000200 */ +#define DCFG_DAD_6 (0x40UL << DCFG_DAD_Pos) // 0x00000400 */ #define DCFG_PFIVL_Pos (11U) -#define DCFG_PFIVL_Msk (0x3UL << DCFG_PFIVL_Pos) /*!< 0x00001800 */ -#define DCFG_PFIVL DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ -#define DCFG_PFIVL_0 (0x1UL << DCFG_PFIVL_Pos) /*!< 0x00000800 */ -#define DCFG_PFIVL_1 (0x2UL << DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define DCFG_PFIVL_Msk (0x3UL << DCFG_PFIVL_Pos) // 0x00001800 */ +#define DCFG_PFIVL DCFG_PFIVL_Msk // Periodic (micro)frame interval */ +#define DCFG_PFIVL_0 (0x1UL << DCFG_PFIVL_Pos) // 0x00000800 */ +#define DCFG_PFIVL_1 (0x2UL << DCFG_PFIVL_Pos) // 0x00001000 */ #define DCFG_PERSCHIVL_Pos (24U) -#define DCFG_PERSCHIVL_Msk (0x3UL << DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ -#define DCFG_PERSCHIVL DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ -#define DCFG_PERSCHIVL_0 (0x1UL << DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */ -#define DCFG_PERSCHIVL_1 (0x2UL << DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */ +#define DCFG_PERSCHIVL_Msk (0x3UL << DCFG_PERSCHIVL_Pos) // 0x03000000 */ +#define DCFG_PERSCHIVL DCFG_PERSCHIVL_Msk // Periodic scheduling interval */ +#define DCFG_PERSCHIVL_0 (0x1UL << DCFG_PERSCHIVL_Pos) // 0x01000000 */ +#define DCFG_PERSCHIVL_1 (0x2UL << DCFG_PERSCHIVL_Pos) // 0x02000000 */ /******************** Bit definition for PCGCR register ********************/ #define PCGCR_STPPCLK_Pos (0U) -#define PCGCR_STPPCLK_Msk (0x1UL << PCGCR_STPPCLK_Pos) /*!< 0x00000001 */ -#define PCGCR_STPPCLK PCGCR_STPPCLK_Msk /*!< Stop PHY clock */ +#define PCGCR_STPPCLK_Msk (0x1UL << PCGCR_STPPCLK_Pos) // 0x00000001 */ +#define PCGCR_STPPCLK PCGCR_STPPCLK_Msk // Stop PHY clock */ #define PCGCR_GATEHCLK_Pos (1U) -#define PCGCR_GATEHCLK_Msk (0x1UL << PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */ -#define PCGCR_GATEHCLK PCGCR_GATEHCLK_Msk /*!< Gate HCLK */ +#define PCGCR_GATEHCLK_Msk (0x1UL << PCGCR_GATEHCLK_Pos) // 0x00000002 */ +#define PCGCR_GATEHCLK PCGCR_GATEHCLK_Msk // Gate HCLK */ #define PCGCR_PHYSUSP_Pos (4U) -#define PCGCR_PHYSUSP_Msk (0x1UL << PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */ -#define PCGCR_PHYSUSP PCGCR_PHYSUSP_Msk /*!< PHY suspended */ +#define PCGCR_PHYSUSP_Msk (0x1UL << PCGCR_PHYSUSP_Pos) // 0x00000010 */ +#define PCGCR_PHYSUSP PCGCR_PHYSUSP_Msk // PHY suspended */ /******************** Bit definition for GOTGINT register ********************/ #define GOTGINT_SEDET_Pos (2U) -#define GOTGINT_SEDET_Msk (0x1UL << GOTGINT_SEDET_Pos) /*!< 0x00000004 */ -#define GOTGINT_SEDET GOTGINT_SEDET_Msk /*!< Session end detected */ +#define GOTGINT_SEDET_Msk (0x1UL << GOTGINT_SEDET_Pos) // 0x00000004 */ +#define GOTGINT_SEDET GOTGINT_SEDET_Msk // Session end detected */ #define GOTGINT_SRSSCHG_Pos (8U) -#define GOTGINT_SRSSCHG_Msk (0x1UL << GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */ -#define GOTGINT_SRSSCHG GOTGINT_SRSSCHG_Msk /*!< Session request success status change */ +#define GOTGINT_SRSSCHG_Msk (0x1UL << GOTGINT_SRSSCHG_Pos) // 0x00000100 */ +#define GOTGINT_SRSSCHG GOTGINT_SRSSCHG_Msk // Session request success status change */ #define GOTGINT_HNSSCHG_Pos (9U) -#define GOTGINT_HNSSCHG_Msk (0x1UL << GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */ -#define GOTGINT_HNSSCHG GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */ +#define GOTGINT_HNSSCHG_Msk (0x1UL << GOTGINT_HNSSCHG_Pos) // 0x00000200 */ +#define GOTGINT_HNSSCHG GOTGINT_HNSSCHG_Msk // Host negotiation success status change */ #define GOTGINT_HNGDET_Pos (17U) -#define GOTGINT_HNGDET_Msk (0x1UL << GOTGINT_HNGDET_Pos) /*!< 0x00020000 */ -#define GOTGINT_HNGDET GOTGINT_HNGDET_Msk /*!< Host negotiation detected */ +#define GOTGINT_HNGDET_Msk (0x1UL << GOTGINT_HNGDET_Pos) // 0x00020000 */ +#define GOTGINT_HNGDET GOTGINT_HNGDET_Msk // Host negotiation detected */ #define GOTGINT_ADTOCHG_Pos (18U) -#define GOTGINT_ADTOCHG_Msk (0x1UL << GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */ -#define GOTGINT_ADTOCHG GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */ +#define GOTGINT_ADTOCHG_Msk (0x1UL << GOTGINT_ADTOCHG_Pos) // 0x00040000 */ +#define GOTGINT_ADTOCHG GOTGINT_ADTOCHG_Msk // A-device timeout change */ #define GOTGINT_DBCDNE_Pos (19U) -#define GOTGINT_DBCDNE_Msk (0x1UL << GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */ -#define GOTGINT_DBCDNE GOTGINT_DBCDNE_Msk /*!< Debounce done */ +#define GOTGINT_DBCDNE_Msk (0x1UL << GOTGINT_DBCDNE_Pos) // 0x00080000 */ +#define GOTGINT_DBCDNE GOTGINT_DBCDNE_Msk // Debounce done */ #define GOTGINT_IDCHNG_Pos (20U) -#define GOTGINT_IDCHNG_Msk (0x1UL << GOTGINT_IDCHNG_Pos) /*!< 0x00100000 */ -#define GOTGINT_IDCHNG GOTGINT_IDCHNG_Msk /*!< Change in ID pin input value */ +#define GOTGINT_IDCHNG_Msk (0x1UL << GOTGINT_IDCHNG_Pos) // 0x00100000 */ +#define GOTGINT_IDCHNG GOTGINT_IDCHNG_Msk // Change in ID pin input value */ /******************** Bit definition for DCTL register ********************/ #define DCTL_RWUSIG_Pos (0U) -#define DCTL_RWUSIG_Msk (0x1UL << DCTL_RWUSIG_Pos) /*!< 0x00000001 */ -#define DCTL_RWUSIG DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */ +#define DCTL_RWUSIG_Msk (0x1UL << DCTL_RWUSIG_Pos) // 0x00000001 */ +#define DCTL_RWUSIG DCTL_RWUSIG_Msk // Remote wakeup signaling */ #define DCTL_SDIS_Pos (1U) -#define DCTL_SDIS_Msk (0x1UL << DCTL_SDIS_Pos) /*!< 0x00000002 */ -#define DCTL_SDIS DCTL_SDIS_Msk /*!< Soft disconnect */ +#define DCTL_SDIS_Msk (0x1UL << DCTL_SDIS_Pos) // 0x00000002 */ +#define DCTL_SDIS DCTL_SDIS_Msk // Soft disconnect */ #define DCTL_GINSTS_Pos (2U) -#define DCTL_GINSTS_Msk (0x1UL << DCTL_GINSTS_Pos) /*!< 0x00000004 */ -#define DCTL_GINSTS DCTL_GINSTS_Msk /*!< Global IN NAK status */ +#define DCTL_GINSTS_Msk (0x1UL << DCTL_GINSTS_Pos) // 0x00000004 */ +#define DCTL_GINSTS DCTL_GINSTS_Msk // Global IN NAK status */ #define DCTL_GONSTS_Pos (3U) -#define DCTL_GONSTS_Msk (0x1UL << DCTL_GONSTS_Pos) /*!< 0x00000008 */ -#define DCTL_GONSTS DCTL_GONSTS_Msk /*!< Global OUT NAK status */ +#define DCTL_GONSTS_Msk (0x1UL << DCTL_GONSTS_Pos) // 0x00000008 */ +#define DCTL_GONSTS DCTL_GONSTS_Msk // Global OUT NAK status */ #define DCTL_TCTL_Pos (4U) -#define DCTL_TCTL_Msk (0x7UL << DCTL_TCTL_Pos) /*!< 0x00000070 */ -#define DCTL_TCTL DCTL_TCTL_Msk /*!< Test control */ -#define DCTL_TCTL_0 (0x1UL << DCTL_TCTL_Pos) /*!< 0x00000010 */ -#define DCTL_TCTL_1 (0x2UL << DCTL_TCTL_Pos) /*!< 0x00000020 */ -#define DCTL_TCTL_2 (0x4UL << DCTL_TCTL_Pos) /*!< 0x00000040 */ +#define DCTL_TCTL_Msk (0x7UL << DCTL_TCTL_Pos) // 0x00000070 */ +#define DCTL_TCTL DCTL_TCTL_Msk // Test control */ +#define DCTL_TCTL_0 (0x1UL << DCTL_TCTL_Pos) // 0x00000010 */ +#define DCTL_TCTL_1 (0x2UL << DCTL_TCTL_Pos) // 0x00000020 */ +#define DCTL_TCTL_2 (0x4UL << DCTL_TCTL_Pos) // 0x00000040 */ #define DCTL_SGINAK_Pos (7U) -#define DCTL_SGINAK_Msk (0x1UL << DCTL_SGINAK_Pos) /*!< 0x00000080 */ -#define DCTL_SGINAK DCTL_SGINAK_Msk /*!< Set global IN NAK */ +#define DCTL_SGINAK_Msk (0x1UL << DCTL_SGINAK_Pos) // 0x00000080 */ +#define DCTL_SGINAK DCTL_SGINAK_Msk // Set global IN NAK */ #define DCTL_CGINAK_Pos (8U) -#define DCTL_CGINAK_Msk (0x1UL << DCTL_CGINAK_Pos) /*!< 0x00000100 */ -#define DCTL_CGINAK DCTL_CGINAK_Msk /*!< Clear global IN NAK */ +#define DCTL_CGINAK_Msk (0x1UL << DCTL_CGINAK_Pos) // 0x00000100 */ +#define DCTL_CGINAK DCTL_CGINAK_Msk // Clear global IN NAK */ #define DCTL_SGONAK_Pos (9U) -#define DCTL_SGONAK_Msk (0x1UL << DCTL_SGONAK_Pos) /*!< 0x00000200 */ -#define DCTL_SGONAK DCTL_SGONAK_Msk /*!< Set global OUT NAK */ +#define DCTL_SGONAK_Msk (0x1UL << DCTL_SGONAK_Pos) // 0x00000200 */ +#define DCTL_SGONAK DCTL_SGONAK_Msk // Set global OUT NAK */ #define DCTL_CGONAK_Pos (10U) -#define DCTL_CGONAK_Msk (0x1UL << DCTL_CGONAK_Pos) /*!< 0x00000400 */ -#define DCTL_CGONAK DCTL_CGONAK_Msk /*!< Clear global OUT NAK */ +#define DCTL_CGONAK_Msk (0x1UL << DCTL_CGONAK_Pos) // 0x00000400 */ +#define DCTL_CGONAK DCTL_CGONAK_Msk // Clear global OUT NAK */ #define DCTL_POPRGDNE_Pos (11U) -#define DCTL_POPRGDNE_Msk (0x1UL << DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ -#define DCTL_POPRGDNE DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define DCTL_POPRGDNE_Msk (0x1UL << DCTL_POPRGDNE_Pos) // 0x00000800 */ +#define DCTL_POPRGDNE DCTL_POPRGDNE_Msk // Power-on programming done */ /******************** Bit definition for HFIR register ********************/ #define HFIR_FRIVL_Pos (0U) -#define HFIR_FRIVL_Msk (0xFFFFUL << HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ -#define HFIR_FRIVL HFIR_FRIVL_Msk /*!< Frame interval */ +#define HFIR_FRIVL_Msk (0xFFFFUL << HFIR_FRIVL_Pos) // 0x0000FFFF */ +#define HFIR_FRIVL HFIR_FRIVL_Msk // Frame interval */ /******************** Bit definition for HFNUM register ********************/ #define HFNUM_FRNUM_Pos (0U) -#define HFNUM_FRNUM_Msk (0xFFFFUL << HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */ -#define HFNUM_FRNUM HFNUM_FRNUM_Msk /*!< Frame number */ +#define HFNUM_FRNUM_Msk (0xFFFFUL << HFNUM_FRNUM_Pos) // 0x0000FFFF */ +#define HFNUM_FRNUM HFNUM_FRNUM_Msk // Frame number */ #define HFNUM_FTREM_Pos (16U) -#define HFNUM_FTREM_Msk (0xFFFFUL << HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */ -#define HFNUM_FTREM HFNUM_FTREM_Msk /*!< Frame time remaining */ +#define HFNUM_FTREM_Msk (0xFFFFUL << HFNUM_FTREM_Pos) // 0xFFFF0000 */ +#define HFNUM_FTREM HFNUM_FTREM_Msk // Frame time remaining */ /******************** Bit definition for DSTS register ********************/ #define DSTS_SUSPSTS_Pos (0U) -#define DSTS_SUSPSTS_Msk (0x1UL << DSTS_SUSPSTS_Pos) /*!< 0x00000001 */ -#define DSTS_SUSPSTS DSTS_SUSPSTS_Msk /*!< Suspend status */ +#define DSTS_SUSPSTS_Msk (0x1UL << DSTS_SUSPSTS_Pos) // 0x00000001 */ +#define DSTS_SUSPSTS DSTS_SUSPSTS_Msk // Suspend status */ #define DSTS_ENUMSPD_Pos (1U) -#define DSTS_ENUMSPD_Msk (0x3UL << DSTS_ENUMSPD_Pos) /*!< 0x00000006 */ -#define DSTS_ENUMSPD DSTS_ENUMSPD_Msk /*!< Enumerated speed */ -#define DSTS_ENUMSPD_0 (0x1UL << DSTS_ENUMSPD_Pos) /*!< 0x00000002 */ -#define DSTS_ENUMSPD_1 (0x2UL << DSTS_ENUMSPD_Pos) /*!< 0x00000004 */ +#define DSTS_ENUMSPD_Msk (0x3UL << DSTS_ENUMSPD_Pos) // 0x00000006 */ +#define DSTS_ENUMSPD DSTS_ENUMSPD_Msk // Enumerated speed */ +#define DSTS_ENUMSPD_0 (0x1UL << DSTS_ENUMSPD_Pos) // 0x00000002 */ +#define DSTS_ENUMSPD_1 (0x2UL << DSTS_ENUMSPD_Pos) // 0x00000004 */ #define DSTS_EERR_Pos (3U) -#define DSTS_EERR_Msk (0x1UL << DSTS_EERR_Pos) /*!< 0x00000008 */ -#define DSTS_EERR DSTS_EERR_Msk /*!< Erratic error */ +#define DSTS_EERR_Msk (0x1UL << DSTS_EERR_Pos) // 0x00000008 */ +#define DSTS_EERR DSTS_EERR_Msk // Erratic error */ #define DSTS_FNSOF_Pos (8U) -#define DSTS_FNSOF_Msk (0x3FFFUL << DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ -#define DSTS_FNSOF DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ +#define DSTS_FNSOF_Msk (0x3FFFUL << DSTS_FNSOF_Pos) // 0x003FFF00 */ +#define DSTS_FNSOF DSTS_FNSOF_Msk // Frame number of the received SOF */ /******************** Bit definition for GAHBCFG register ********************/ #define GAHBCFG_GINT_Pos (0U) -#define GAHBCFG_GINT_Msk (0x1UL << GAHBCFG_GINT_Pos) /*!< 0x00000001 */ -#define GAHBCFG_GINT GAHBCFG_GINT_Msk /*!< Global interrupt mask */ +#define GAHBCFG_GINT_Msk (0x1UL << GAHBCFG_GINT_Pos) // 0x00000001 */ +#define GAHBCFG_GINT GAHBCFG_GINT_Msk // Global interrupt mask */ #define GAHBCFG_HBSTLEN_Pos (1U) -#define GAHBCFG_HBSTLEN_Msk (0xFUL << GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ -#define GAHBCFG_HBSTLEN GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ -#define GAHBCFG_HBSTLEN_0 (0x0UL << GAHBCFG_HBSTLEN_Pos) /*!< Single */ -#define GAHBCFG_HBSTLEN_1 (0x1UL << GAHBCFG_HBSTLEN_Pos) /*!< INCR */ -#define GAHBCFG_HBSTLEN_2 (0x3UL << GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */ -#define GAHBCFG_HBSTLEN_3 (0x5UL << GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */ -#define GAHBCFG_HBSTLEN_4 (0x7UL << GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */ +#define GAHBCFG_HBSTLEN_Msk (0xFUL << GAHBCFG_HBSTLEN_Pos) // 0x0000001E */ +#define GAHBCFG_HBSTLEN GAHBCFG_HBSTLEN_Msk // Burst length/type */ +#define GAHBCFG_HBSTLEN_0 (0x0UL << GAHBCFG_HBSTLEN_Pos) // Single */ +#define GAHBCFG_HBSTLEN_1 (0x1UL << GAHBCFG_HBSTLEN_Pos) // INCR */ +#define GAHBCFG_HBSTLEN_2 (0x3UL << GAHBCFG_HBSTLEN_Pos) // INCR4 */ +#define GAHBCFG_HBSTLEN_3 (0x5UL << GAHBCFG_HBSTLEN_Pos) // INCR8 */ +#define GAHBCFG_HBSTLEN_4 (0x7UL << GAHBCFG_HBSTLEN_Pos) // INCR16 */ #define GAHBCFG_DMAEN_Pos (5U) -#define GAHBCFG_DMAEN_Msk (0x1UL << GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */ -#define GAHBCFG_DMAEN GAHBCFG_DMAEN_Msk /*!< DMA enable */ +#define GAHBCFG_DMAEN_Msk (0x1UL << GAHBCFG_DMAEN_Pos) // 0x00000020 */ +#define GAHBCFG_DMAEN GAHBCFG_DMAEN_Msk // DMA enable */ #define GAHBCFG_TXFELVL_Pos (7U) -#define GAHBCFG_TXFELVL_Msk (0x1UL << GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */ -#define GAHBCFG_TXFELVL GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */ +#define GAHBCFG_TXFELVL_Msk (0x1UL << GAHBCFG_TXFELVL_Pos) // 0x00000080 */ +#define GAHBCFG_TXFELVL GAHBCFG_TXFELVL_Msk // TxFIFO empty level */ #define GAHBCFG_PTXFELVL_Pos (8U) -#define GAHBCFG_PTXFELVL_Msk (0x1UL << GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */ -#define GAHBCFG_PTXFELVL GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */ +#define GAHBCFG_PTXFELVL_Msk (0x1UL << GAHBCFG_PTXFELVL_Pos) // 0x00000100 */ +#define GAHBCFG_PTXFELVL GAHBCFG_PTXFELVL_Msk // Periodic TxFIFO empty level */ /******************** Bit definition for GUSBCFG register ********************/ #define GUSBCFG_TOCAL_Pos (0U) -#define GUSBCFG_TOCAL_Msk (0x7UL << GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */ -#define GUSBCFG_TOCAL GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */ -#define GUSBCFG_TOCAL_0 (0x1UL << GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */ -#define GUSBCFG_TOCAL_1 (0x2UL << GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */ -#define GUSBCFG_TOCAL_2 (0x4UL << GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */ +#define GUSBCFG_TOCAL_Msk (0x7UL << GUSBCFG_TOCAL_Pos) // 0x00000007 */ +#define GUSBCFG_TOCAL GUSBCFG_TOCAL_Msk // FS timeout calibration */ +#define GUSBCFG_TOCAL_0 (0x1UL << GUSBCFG_TOCAL_Pos) // 0x00000001 */ +#define GUSBCFG_TOCAL_1 (0x2UL << GUSBCFG_TOCAL_Pos) // 0x00000002 */ +#define GUSBCFG_TOCAL_2 (0x4UL << GUSBCFG_TOCAL_Pos) // 0x00000004 */ #define GUSBCFG_PHYIF_Pos (3U) -#define GUSBCFG_PHYIF_Msk (0x1UL << GUSBCFG_PHYIF_Pos) /*!< 0x00000008 */ -#define GUSBCFG_PHYIF GUSBCFG_PHYIF_Msk /*!< PHY Interface (PHYIf) */ +#define GUSBCFG_PHYIF_Msk (0x1UL << GUSBCFG_PHYIF_Pos) // 0x00000008 */ +#define GUSBCFG_PHYIF GUSBCFG_PHYIF_Msk // PHY Interface (PHYIf) */ #define GUSBCFG_ULPI_UTMI_SEL_Pos (4U) -#define GUSBCFG_ULPI_UTMI_SEL_Msk (0x1UL << GUSBCFG_ULPI_UTMI_SEL_Pos) /*!< 0x00000010 */ -#define GUSBCFG_ULPI_UTMI_SEL GUSBCFG_ULPI_UTMI_SEL_Msk /*!< ULPI or UTMI+ Select (ULPI_UTMI_Sel) */ +#define GUSBCFG_ULPI_UTMI_SEL_Msk (0x1UL << GUSBCFG_ULPI_UTMI_SEL_Pos) // 0x00000010 */ +#define GUSBCFG_ULPI_UTMI_SEL GUSBCFG_ULPI_UTMI_SEL_Msk // ULPI or UTMI+ Select (ULPI_UTMI_Sel) */ #define GUSBCFG_PHYSEL_Pos (6U) -#define GUSBCFG_PHYSEL_Msk (0x1UL << GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */ -#define GUSBCFG_PHYSEL GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */ +#define GUSBCFG_PHYSEL_Msk (0x1UL << GUSBCFG_PHYSEL_Pos) // 0x00000040 */ +#define GUSBCFG_PHYSEL GUSBCFG_PHYSEL_Msk // USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */ #define GUSBCFG_SRPCAP_Pos (8U) -#define GUSBCFG_SRPCAP_Msk (0x1UL << GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */ -#define GUSBCFG_SRPCAP GUSBCFG_SRPCAP_Msk /*!< SRP-capable */ +#define GUSBCFG_SRPCAP_Msk (0x1UL << GUSBCFG_SRPCAP_Pos) // 0x00000100 */ +#define GUSBCFG_SRPCAP GUSBCFG_SRPCAP_Msk // SRP-capable */ #define GUSBCFG_HNPCAP_Pos (9U) -#define GUSBCFG_HNPCAP_Msk (0x1UL << GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */ -#define GUSBCFG_HNPCAP GUSBCFG_HNPCAP_Msk /*!< HNP-capable */ +#define GUSBCFG_HNPCAP_Msk (0x1UL << GUSBCFG_HNPCAP_Pos) // 0x00000200 */ +#define GUSBCFG_HNPCAP GUSBCFG_HNPCAP_Msk // HNP-capable */ #define GUSBCFG_TRDT_Pos (10U) -#define GUSBCFG_TRDT_Msk (0xFUL << GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */ -#define GUSBCFG_TRDT GUSBCFG_TRDT_Msk /*!< USB turnaround time */ -#define GUSBCFG_TRDT_0 (0x1UL << GUSBCFG_TRDT_Pos) /*!< 0x00000400 */ -#define GUSBCFG_TRDT_1 (0x2UL << GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ -#define GUSBCFG_TRDT_2 (0x4UL << GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ -#define GUSBCFG_TRDT_3 (0x8UL << GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ +#define GUSBCFG_TRDT_Msk (0xFUL << GUSBCFG_TRDT_Pos) // 0x00003C00 */ +#define GUSBCFG_TRDT GUSBCFG_TRDT_Msk // USB turnaround time */ +#define GUSBCFG_TRDT_0 (0x1UL << GUSBCFG_TRDT_Pos) // 0x00000400 */ +#define GUSBCFG_TRDT_1 (0x2UL << GUSBCFG_TRDT_Pos) // 0x00000800 */ +#define GUSBCFG_TRDT_2 (0x4UL << GUSBCFG_TRDT_Pos) // 0x00001000 */ +#define GUSBCFG_TRDT_3 (0x8UL << GUSBCFG_TRDT_Pos) // 0x00002000 */ #define GUSBCFG_PHYLPCS_Pos (15U) -#define GUSBCFG_PHYLPCS_Msk (0x1UL << GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ -#define GUSBCFG_PHYLPCS GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ +#define GUSBCFG_PHYLPCS_Msk (0x1UL << GUSBCFG_PHYLPCS_Pos) // 0x00008000 */ +#define GUSBCFG_PHYLPCS GUSBCFG_PHYLPCS_Msk // PHY Low-power clock select */ #define GUSBCFG_ULPIFSLS_Pos (17U) -#define GUSBCFG_ULPIFSLS_Msk (0x1UL << GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ -#define GUSBCFG_ULPIFSLS GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ +#define GUSBCFG_ULPIFSLS_Msk (0x1UL << GUSBCFG_ULPIFSLS_Pos) // 0x00020000 */ +#define GUSBCFG_ULPIFSLS GUSBCFG_ULPIFSLS_Msk // ULPI FS/LS select */ #define GUSBCFG_ULPIAR_Pos (18U) -#define GUSBCFG_ULPIAR_Msk (0x1UL << GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */ -#define GUSBCFG_ULPIAR GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */ +#define GUSBCFG_ULPIAR_Msk (0x1UL << GUSBCFG_ULPIAR_Pos) // 0x00040000 */ +#define GUSBCFG_ULPIAR GUSBCFG_ULPIAR_Msk // ULPI Auto-resume */ #define GUSBCFG_ULPICSM_Pos (19U) -#define GUSBCFG_ULPICSM_Msk (0x1UL << GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */ -#define GUSBCFG_ULPICSM GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */ +#define GUSBCFG_ULPICSM_Msk (0x1UL << GUSBCFG_ULPICSM_Pos) // 0x00080000 */ +#define GUSBCFG_ULPICSM GUSBCFG_ULPICSM_Msk // ULPI Clock SuspendM */ #define GUSBCFG_ULPIEVBUSD_Pos (20U) -#define GUSBCFG_ULPIEVBUSD_Msk (0x1UL << GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */ -#define GUSBCFG_ULPIEVBUSD GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */ +#define GUSBCFG_ULPIEVBUSD_Msk (0x1UL << GUSBCFG_ULPIEVBUSD_Pos) // 0x00100000 */ +#define GUSBCFG_ULPIEVBUSD GUSBCFG_ULPIEVBUSD_Msk // ULPI External VBUS Drive */ #define GUSBCFG_ULPIEVBUSI_Pos (21U) -#define GUSBCFG_ULPIEVBUSI_Msk (0x1UL << GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */ -#define GUSBCFG_ULPIEVBUSI GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */ +#define GUSBCFG_ULPIEVBUSI_Msk (0x1UL << GUSBCFG_ULPIEVBUSI_Pos) // 0x00200000 */ +#define GUSBCFG_ULPIEVBUSI GUSBCFG_ULPIEVBUSI_Msk // ULPI external VBUS indicator */ #define GUSBCFG_TSDPS_Pos (22U) -#define GUSBCFG_TSDPS_Msk (0x1UL << GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */ -#define GUSBCFG_TSDPS GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */ +#define GUSBCFG_TSDPS_Msk (0x1UL << GUSBCFG_TSDPS_Pos) // 0x00400000 */ +#define GUSBCFG_TSDPS GUSBCFG_TSDPS_Msk // TermSel DLine pulsing selection */ #define GUSBCFG_PCCI_Pos (23U) -#define GUSBCFG_PCCI_Msk (0x1UL << GUSBCFG_PCCI_Pos) /*!< 0x00800000 */ -#define GUSBCFG_PCCI GUSBCFG_PCCI_Msk /*!< Indicator complement */ +#define GUSBCFG_PCCI_Msk (0x1UL << GUSBCFG_PCCI_Pos) // 0x00800000 */ +#define GUSBCFG_PCCI GUSBCFG_PCCI_Msk // Indicator complement */ #define GUSBCFG_PTCI_Pos (24U) -#define GUSBCFG_PTCI_Msk (0x1UL << GUSBCFG_PTCI_Pos) /*!< 0x01000000 */ -#define GUSBCFG_PTCI GUSBCFG_PTCI_Msk /*!< Indicator pass through */ +#define GUSBCFG_PTCI_Msk (0x1UL << GUSBCFG_PTCI_Pos) // 0x01000000 */ +#define GUSBCFG_PTCI GUSBCFG_PTCI_Msk // Indicator pass through */ #define GUSBCFG_ULPIIPD_Pos (25U) -#define GUSBCFG_ULPIIPD_Msk (0x1UL << GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */ -#define GUSBCFG_ULPIIPD GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */ +#define GUSBCFG_ULPIIPD_Msk (0x1UL << GUSBCFG_ULPIIPD_Pos) // 0x02000000 */ +#define GUSBCFG_ULPIIPD GUSBCFG_ULPIIPD_Msk // ULPI interface protect disable */ #define GUSBCFG_FHMOD_Pos (29U) -#define GUSBCFG_FHMOD_Msk (0x1UL << GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */ -#define GUSBCFG_FHMOD GUSBCFG_FHMOD_Msk /*!< Forced host mode */ +#define GUSBCFG_FHMOD_Msk (0x1UL << GUSBCFG_FHMOD_Pos) // 0x20000000 */ +#define GUSBCFG_FHMOD GUSBCFG_FHMOD_Msk // Forced host mode */ #define GUSBCFG_FDMOD_Pos (30U) -#define GUSBCFG_FDMOD_Msk (0x1UL << GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */ -#define GUSBCFG_FDMOD GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */ +#define GUSBCFG_FDMOD_Msk (0x1UL << GUSBCFG_FDMOD_Pos) // 0x40000000 */ +#define GUSBCFG_FDMOD GUSBCFG_FDMOD_Msk // Forced peripheral mode */ #define GUSBCFG_CTXPKT_Pos (31U) -#define GUSBCFG_CTXPKT_Msk (0x1UL << GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */ -#define GUSBCFG_CTXPKT GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */ +#define GUSBCFG_CTXPKT_Msk (0x1UL << GUSBCFG_CTXPKT_Pos) // 0x80000000 */ +#define GUSBCFG_CTXPKT GUSBCFG_CTXPKT_Msk // Corrupt Tx packet */ /******************** Bit definition for GRSTCTL register ********************/ #define GRSTCTL_CSRST_Pos (0U) -#define GRSTCTL_CSRST_Msk (0x1UL << GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ -#define GRSTCTL_CSRST GRSTCTL_CSRST_Msk /*!< Core soft reset */ +#define GRSTCTL_CSRST_Msk (0x1UL << GRSTCTL_CSRST_Pos) // 0x00000001 */ +#define GRSTCTL_CSRST GRSTCTL_CSRST_Msk // Core soft reset */ #define GRSTCTL_HSRST_Pos (1U) -#define GRSTCTL_HSRST_Msk (0x1UL << GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ -#define GRSTCTL_HSRST GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ +#define GRSTCTL_HSRST_Msk (0x1UL << GRSTCTL_HSRST_Pos) // 0x00000002 */ +#define GRSTCTL_HSRST GRSTCTL_HSRST_Msk // HCLK soft reset */ #define GRSTCTL_FCRST_Pos (2U) -#define GRSTCTL_FCRST_Msk (0x1UL << GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ -#define GRSTCTL_FCRST GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ +#define GRSTCTL_FCRST_Msk (0x1UL << GRSTCTL_FCRST_Pos) // 0x00000004 */ +#define GRSTCTL_FCRST GRSTCTL_FCRST_Msk // Host frame counter reset */ #define GRSTCTL_RXFFLSH_Pos (4U) -#define GRSTCTL_RXFFLSH_Msk (0x1UL << GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */ -#define GRSTCTL_RXFFLSH GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */ +#define GRSTCTL_RXFFLSH_Msk (0x1UL << GRSTCTL_RXFFLSH_Pos) // 0x00000010 */ +#define GRSTCTL_RXFFLSH GRSTCTL_RXFFLSH_Msk // RxFIFO flush */ #define GRSTCTL_TXFFLSH_Pos (5U) -#define GRSTCTL_TXFFLSH_Msk (0x1UL << GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */ -#define GRSTCTL_TXFFLSH GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */ +#define GRSTCTL_TXFFLSH_Msk (0x1UL << GRSTCTL_TXFFLSH_Pos) // 0x00000020 */ +#define GRSTCTL_TXFFLSH GRSTCTL_TXFFLSH_Msk // TxFIFO flush */ #define GRSTCTL_TXFNUM_Pos (6U) -#define GRSTCTL_TXFNUM_Msk (0x1FUL << GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */ -#define GRSTCTL_TXFNUM GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */ -#define GRSTCTL_TXFNUM_0 (0x01UL << GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */ -#define GRSTCTL_TXFNUM_1 (0x02UL << GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */ -#define GRSTCTL_TXFNUM_2 (0x04UL << GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */ -#define GRSTCTL_TXFNUM_3 (0x08UL << GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */ -#define GRSTCTL_TXFNUM_4 (0x10UL << GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */ +#define GRSTCTL_TXFNUM_Msk (0x1FUL << GRSTCTL_TXFNUM_Pos) // 0x000007C0 */ +#define GRSTCTL_TXFNUM GRSTCTL_TXFNUM_Msk // TxFIFO number */ +#define GRSTCTL_TXFNUM_0 (0x01UL << GRSTCTL_TXFNUM_Pos) // 0x00000040 */ +#define GRSTCTL_TXFNUM_1 (0x02UL << GRSTCTL_TXFNUM_Pos) // 0x00000080 */ +#define GRSTCTL_TXFNUM_2 (0x04UL << GRSTCTL_TXFNUM_Pos) // 0x00000100 */ +#define GRSTCTL_TXFNUM_3 (0x08UL << GRSTCTL_TXFNUM_Pos) // 0x00000200 */ +#define GRSTCTL_TXFNUM_4 (0x10UL << GRSTCTL_TXFNUM_Pos) // 0x00000400 */ #define GRSTCTL_DMAREQ_Pos (30U) -#define GRSTCTL_DMAREQ_Msk (0x1UL << GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */ -#define GRSTCTL_DMAREQ GRSTCTL_DMAREQ_Msk /*!< DMA request signal */ +#define GRSTCTL_DMAREQ_Msk (0x1UL << GRSTCTL_DMAREQ_Pos) // 0x40000000 */ +#define GRSTCTL_DMAREQ GRSTCTL_DMAREQ_Msk // DMA request signal */ #define GRSTCTL_AHBIDL_Pos (31U) -#define GRSTCTL_AHBIDL_Msk (0x1UL << GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */ -#define GRSTCTL_AHBIDL GRSTCTL_AHBIDL_Msk /*!< AHB master idle */ +#define GRSTCTL_AHBIDL_Msk (0x1UL << GRSTCTL_AHBIDL_Pos) // 0x80000000 */ +#define GRSTCTL_AHBIDL GRSTCTL_AHBIDL_Msk // AHB master idle */ /******************** Bit definition for DIEPMSK register ********************/ #define DIEPMSK_XFRCM_Pos (0U) -#define DIEPMSK_XFRCM_Msk (0x1UL << DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */ -#define DIEPMSK_XFRCM DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */ +#define DIEPMSK_XFRCM_Msk (0x1UL << DIEPMSK_XFRCM_Pos) // 0x00000001 */ +#define DIEPMSK_XFRCM DIEPMSK_XFRCM_Msk // Transfer completed interrupt mask */ #define DIEPMSK_EPDM_Pos (1U) -#define DIEPMSK_EPDM_Msk (0x1UL << DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ -#define DIEPMSK_EPDM DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define DIEPMSK_EPDM_Msk (0x1UL << DIEPMSK_EPDM_Pos) // 0x00000002 */ +#define DIEPMSK_EPDM DIEPMSK_EPDM_Msk // Endpoint disabled interrupt mask */ #define DIEPMSK_TOM_Pos (3U) -#define DIEPMSK_TOM_Msk (0x1UL << DIEPMSK_TOM_Pos) /*!< 0x00000008 */ -#define DIEPMSK_TOM DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ +#define DIEPMSK_TOM_Msk (0x1UL << DIEPMSK_TOM_Pos) // 0x00000008 */ +#define DIEPMSK_TOM DIEPMSK_TOM_Msk // Timeout condition mask (nonisochronous endpoints) */ #define DIEPMSK_ITTXFEMSK_Pos (4U) -#define DIEPMSK_ITTXFEMSK_Msk (0x1UL << DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */ -#define DIEPMSK_ITTXFEMSK DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ +#define DIEPMSK_ITTXFEMSK_Msk (0x1UL << DIEPMSK_ITTXFEMSK_Pos) // 0x00000010 */ +#define DIEPMSK_ITTXFEMSK DIEPMSK_ITTXFEMSK_Msk // IN token received when TxFIFO empty mask */ #define DIEPMSK_INEPNMM_Pos (5U) -#define DIEPMSK_INEPNMM_Msk (0x1UL << DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */ -#define DIEPMSK_INEPNMM DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ +#define DIEPMSK_INEPNMM_Msk (0x1UL << DIEPMSK_INEPNMM_Pos) // 0x00000020 */ +#define DIEPMSK_INEPNMM DIEPMSK_INEPNMM_Msk // IN token received with EP mismatch mask */ #define DIEPMSK_INEPNEM_Pos (6U) -#define DIEPMSK_INEPNEM_Msk (0x1UL << DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */ -#define DIEPMSK_INEPNEM DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ +#define DIEPMSK_INEPNEM_Msk (0x1UL << DIEPMSK_INEPNEM_Pos) // 0x00000040 */ +#define DIEPMSK_INEPNEM DIEPMSK_INEPNEM_Msk // IN endpoint NAK effective mask */ #define DIEPMSK_TXFURM_Pos (8U) -#define DIEPMSK_TXFURM_Msk (0x1UL << DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */ -#define DIEPMSK_TXFURM DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */ +#define DIEPMSK_TXFURM_Msk (0x1UL << DIEPMSK_TXFURM_Pos) // 0x00000100 */ +#define DIEPMSK_TXFURM DIEPMSK_TXFURM_Msk // FIFO underrun mask */ #define DIEPMSK_BIM_Pos (9U) -#define DIEPMSK_BIM_Msk (0x1UL << DIEPMSK_BIM_Pos) /*!< 0x00000200 */ -#define DIEPMSK_BIM DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ +#define DIEPMSK_BIM_Msk (0x1UL << DIEPMSK_BIM_Pos) // 0x00000200 */ +#define DIEPMSK_BIM DIEPMSK_BIM_Msk // BNA interrupt mask */ /******************** Bit definition for HPTXSTS register ********************/ #define HPTXSTS_PTXFSAVL_Pos (0U) -#define HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */ -#define HPTXSTS_PTXFSAVL HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */ +#define HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << HPTXSTS_PTXFSAVL_Pos) // 0x0000FFFF */ +#define HPTXSTS_PTXFSAVL HPTXSTS_PTXFSAVL_Msk // Periodic transmit data FIFO space available */ #define HPTXSTS_PTXQSAV_Pos (16U) -#define HPTXSTS_PTXQSAV_Msk (0xFFUL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */ -#define HPTXSTS_PTXQSAV HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */ -#define HPTXSTS_PTXQSAV_0 (0x01UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */ -#define HPTXSTS_PTXQSAV_1 (0x02UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */ -#define HPTXSTS_PTXQSAV_2 (0x04UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */ -#define HPTXSTS_PTXQSAV_3 (0x08UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */ -#define HPTXSTS_PTXQSAV_4 (0x10UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */ -#define HPTXSTS_PTXQSAV_5 (0x20UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */ -#define HPTXSTS_PTXQSAV_6 (0x40UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */ -#define HPTXSTS_PTXQSAV_7 (0x80UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */ +#define HPTXSTS_PTXQSAV_Msk (0xFFUL << HPTXSTS_PTXQSAV_Pos) // 0x00FF0000 */ +#define HPTXSTS_PTXQSAV HPTXSTS_PTXQSAV_Msk // Periodic transmit request queue space available */ +#define HPTXSTS_PTXQSAV_0 (0x01UL << HPTXSTS_PTXQSAV_Pos) // 0x00010000 */ +#define HPTXSTS_PTXQSAV_1 (0x02UL << HPTXSTS_PTXQSAV_Pos) // 0x00020000 */ +#define HPTXSTS_PTXQSAV_2 (0x04UL << HPTXSTS_PTXQSAV_Pos) // 0x00040000 */ +#define HPTXSTS_PTXQSAV_3 (0x08UL << HPTXSTS_PTXQSAV_Pos) // 0x00080000 */ +#define HPTXSTS_PTXQSAV_4 (0x10UL << HPTXSTS_PTXQSAV_Pos) // 0x00100000 */ +#define HPTXSTS_PTXQSAV_5 (0x20UL << HPTXSTS_PTXQSAV_Pos) // 0x00200000 */ +#define HPTXSTS_PTXQSAV_6 (0x40UL << HPTXSTS_PTXQSAV_Pos) // 0x00400000 */ +#define HPTXSTS_PTXQSAV_7 (0x80UL << HPTXSTS_PTXQSAV_Pos) // 0x00800000 */ #define HPTXSTS_PTXQTOP_Pos (24U) -#define HPTXSTS_PTXQTOP_Msk (0xFFUL << HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */ -#define HPTXSTS_PTXQTOP HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */ -#define HPTXSTS_PTXQTOP_0 (0x01UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */ -#define HPTXSTS_PTXQTOP_1 (0x02UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */ -#define HPTXSTS_PTXQTOP_2 (0x04UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */ -#define HPTXSTS_PTXQTOP_3 (0x08UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */ -#define HPTXSTS_PTXQTOP_4 (0x10UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */ -#define HPTXSTS_PTXQTOP_5 (0x20UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */ -#define HPTXSTS_PTXQTOP_6 (0x40UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */ -#define HPTXSTS_PTXQTOP_7 (0x80UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */ +#define HPTXSTS_PTXQTOP_Msk (0xFFUL << HPTXSTS_PTXQTOP_Pos) // 0xFF000000 */ +#define HPTXSTS_PTXQTOP HPTXSTS_PTXQTOP_Msk // Top of the periodic transmit request queue */ +#define HPTXSTS_PTXQTOP_0 (0x01UL << HPTXSTS_PTXQTOP_Pos) // 0x01000000 */ +#define HPTXSTS_PTXQTOP_1 (0x02UL << HPTXSTS_PTXQTOP_Pos) // 0x02000000 */ +#define HPTXSTS_PTXQTOP_2 (0x04UL << HPTXSTS_PTXQTOP_Pos) // 0x04000000 */ +#define HPTXSTS_PTXQTOP_3 (0x08UL << HPTXSTS_PTXQTOP_Pos) // 0x08000000 */ +#define HPTXSTS_PTXQTOP_4 (0x10UL << HPTXSTS_PTXQTOP_Pos) // 0x10000000 */ +#define HPTXSTS_PTXQTOP_5 (0x20UL << HPTXSTS_PTXQTOP_Pos) // 0x20000000 */ +#define HPTXSTS_PTXQTOP_6 (0x40UL << HPTXSTS_PTXQTOP_Pos) // 0x40000000 */ +#define HPTXSTS_PTXQTOP_7 (0x80UL << HPTXSTS_PTXQTOP_Pos) // 0x80000000 */ /******************** Bit definition for HAINT register ********************/ #define HAINT_HAINT_Pos (0U) -#define HAINT_HAINT_Msk (0xFFFFUL << HAINT_HAINT_Pos) /*!< 0x0000FFFF */ -#define HAINT_HAINT HAINT_HAINT_Msk /*!< Channel interrupts */ +#define HAINT_HAINT_Msk (0xFFFFUL << HAINT_HAINT_Pos) // 0x0000FFFF */ +#define HAINT_HAINT HAINT_HAINT_Msk // Channel interrupts */ /******************** Bit definition for DOEPMSK register ********************/ #define DOEPMSK_XFRCM_Pos (0U) -#define DOEPMSK_XFRCM_Msk (0x1UL << DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */ -#define DOEPMSK_XFRCM DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */ +#define DOEPMSK_XFRCM_Msk (0x1UL << DOEPMSK_XFRCM_Pos) // 0x00000001 */ +#define DOEPMSK_XFRCM DOEPMSK_XFRCM_Msk // Transfer completed interrupt mask */ #define DOEPMSK_EPDM_Pos (1U) -#define DOEPMSK_EPDM_Msk (0x1UL << DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ -#define DOEPMSK_EPDM DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define DOEPMSK_EPDM_Msk (0x1UL << DOEPMSK_EPDM_Pos) // 0x00000002 */ +#define DOEPMSK_EPDM DOEPMSK_EPDM_Msk // Endpoint disabled interrupt mask */ #define DOEPMSK_AHBERRM_Pos (2U) -#define DOEPMSK_AHBERRM_Msk (0x1UL << DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ -#define DOEPMSK_AHBERRM DOEPMSK_AHBERRM_Msk /*!< OUT transaction AHB Error interrupt mask */ +#define DOEPMSK_AHBERRM_Msk (0x1UL << DOEPMSK_AHBERRM_Pos) // 0x00000004 */ +#define DOEPMSK_AHBERRM DOEPMSK_AHBERRM_Msk // OUT transaction AHB Error interrupt mask */ #define DOEPMSK_STUPM_Pos (3U) -#define DOEPMSK_STUPM_Msk (0x1UL << DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ -#define DOEPMSK_STUPM DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ +#define DOEPMSK_STUPM_Msk (0x1UL << DOEPMSK_STUPM_Pos) // 0x00000008 */ +#define DOEPMSK_STUPM DOEPMSK_STUPM_Msk // SETUP phase done mask */ #define DOEPMSK_OTEPDM_Pos (4U) -#define DOEPMSK_OTEPDM_Msk (0x1UL << DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ -#define DOEPMSK_OTEPDM DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ +#define DOEPMSK_OTEPDM_Msk (0x1UL << DOEPMSK_OTEPDM_Pos) // 0x00000010 */ +#define DOEPMSK_OTEPDM DOEPMSK_OTEPDM_Msk // OUT token received when endpoint disabled mask */ #define DOEPMSK_OTEPSPRM_Pos (5U) -#define DOEPMSK_OTEPSPRM_Msk (0x1UL << DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */ -#define DOEPMSK_OTEPSPRM DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */ +#define DOEPMSK_OTEPSPRM_Msk (0x1UL << DOEPMSK_OTEPSPRM_Pos) // 0x00000020 */ +#define DOEPMSK_OTEPSPRM DOEPMSK_OTEPSPRM_Msk // Status Phase Received mask */ #define DOEPMSK_B2BSTUP_Pos (6U) -#define DOEPMSK_B2BSTUP_Msk (0x1UL << DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ -#define DOEPMSK_B2BSTUP DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ +#define DOEPMSK_B2BSTUP_Msk (0x1UL << DOEPMSK_B2BSTUP_Pos) // 0x00000040 */ +#define DOEPMSK_B2BSTUP DOEPMSK_B2BSTUP_Msk // Back-to-back SETUP packets received mask */ #define DOEPMSK_OPEM_Pos (8U) -#define DOEPMSK_OPEM_Msk (0x1UL << DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ -#define DOEPMSK_OPEM DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ +#define DOEPMSK_OPEM_Msk (0x1UL << DOEPMSK_OPEM_Pos) // 0x00000100 */ +#define DOEPMSK_OPEM DOEPMSK_OPEM_Msk // OUT packet error mask */ #define DOEPMSK_BOIM_Pos (9U) -#define DOEPMSK_BOIM_Msk (0x1UL << DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ -#define DOEPMSK_BOIM DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ +#define DOEPMSK_BOIM_Msk (0x1UL << DOEPMSK_BOIM_Pos) // 0x00000200 */ +#define DOEPMSK_BOIM DOEPMSK_BOIM_Msk // BNA interrupt mask */ #define DOEPMSK_BERRM_Pos (12U) -#define DOEPMSK_BERRM_Msk (0x1UL << DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ -#define DOEPMSK_BERRM DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ +#define DOEPMSK_BERRM_Msk (0x1UL << DOEPMSK_BERRM_Pos) // 0x00001000 */ +#define DOEPMSK_BERRM DOEPMSK_BERRM_Msk // Babble error interrupt mask */ #define DOEPMSK_NAKM_Pos (13U) -#define DOEPMSK_NAKM_Msk (0x1UL << DOEPMSK_NAKM_Pos) /*!< 0x00002000 */ -#define DOEPMSK_NAKM DOEPMSK_NAKM_Msk /*!< OUT Packet NAK interrupt mask */ +#define DOEPMSK_NAKM_Msk (0x1UL << DOEPMSK_NAKM_Pos) // 0x00002000 */ +#define DOEPMSK_NAKM DOEPMSK_NAKM_Msk // OUT Packet NAK interrupt mask */ #define DOEPMSK_NYETM_Pos (14U) -#define DOEPMSK_NYETM_Msk (0x1UL << DOEPMSK_NYETM_Pos) /*!< 0x00004000 */ -#define DOEPMSK_NYETM DOEPMSK_NYETM_Msk /*!< NYET interrupt mask */ +#define DOEPMSK_NYETM_Msk (0x1UL << DOEPMSK_NYETM_Pos) // 0x00004000 */ +#define DOEPMSK_NYETM DOEPMSK_NYETM_Msk // NYET interrupt mask */ /******************** Bit definition for GINTSTS register ********************/ #define GINTSTS_CMOD_Pos (0U) -#define GINTSTS_CMOD_Msk (0x1UL << GINTSTS_CMOD_Pos) /*!< 0x00000001 */ -#define GINTSTS_CMOD GINTSTS_CMOD_Msk /*!< Current mode of operation */ +#define GINTSTS_CMOD_Msk (0x1UL << GINTSTS_CMOD_Pos) // 0x00000001 */ +#define GINTSTS_CMOD GINTSTS_CMOD_Msk // Current mode of operation */ #define GINTSTS_MMIS_Pos (1U) -#define GINTSTS_MMIS_Msk (0x1UL << GINTSTS_MMIS_Pos) /*!< 0x00000002 */ -#define GINTSTS_MMIS GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */ +#define GINTSTS_MMIS_Msk (0x1UL << GINTSTS_MMIS_Pos) // 0x00000002 */ +#define GINTSTS_MMIS GINTSTS_MMIS_Msk // Mode mismatch interrupt */ #define GINTSTS_OTGINT_Pos (2U) -#define GINTSTS_OTGINT_Msk (0x1UL << GINTSTS_OTGINT_Pos) /*!< 0x00000004 */ -#define GINTSTS_OTGINT GINTSTS_OTGINT_Msk /*!< OTG interrupt */ +#define GINTSTS_OTGINT_Msk (0x1UL << GINTSTS_OTGINT_Pos) // 0x00000004 */ +#define GINTSTS_OTGINT GINTSTS_OTGINT_Msk // OTG interrupt */ #define GINTSTS_SOF_Pos (3U) -#define GINTSTS_SOF_Msk (0x1UL << GINTSTS_SOF_Pos) /*!< 0x00000008 */ -#define GINTSTS_SOF GINTSTS_SOF_Msk /*!< Start of frame */ +#define GINTSTS_SOF_Msk (0x1UL << GINTSTS_SOF_Pos) // 0x00000008 */ +#define GINTSTS_SOF GINTSTS_SOF_Msk // Start of frame */ #define GINTSTS_RXFLVL_Pos (4U) -#define GINTSTS_RXFLVL_Msk (0x1UL << GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */ -#define GINTSTS_RXFLVL GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */ +#define GINTSTS_RXFLVL_Msk (0x1UL << GINTSTS_RXFLVL_Pos) // 0x00000010 */ +#define GINTSTS_RXFLVL GINTSTS_RXFLVL_Msk // RxFIFO nonempty */ #define GINTSTS_NPTXFE_Pos (5U) -#define GINTSTS_NPTXFE_Msk (0x1UL << GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */ -#define GINTSTS_NPTXFE GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */ +#define GINTSTS_NPTXFE_Msk (0x1UL << GINTSTS_NPTXFE_Pos) // 0x00000020 */ +#define GINTSTS_NPTXFE GINTSTS_NPTXFE_Msk // Nonperiodic TxFIFO empty */ #define GINTSTS_GINAKEFF_Pos (6U) -#define GINTSTS_GINAKEFF_Msk (0x1UL << GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ -#define GINTSTS_GINAKEFF GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ +#define GINTSTS_GINAKEFF_Msk (0x1UL << GINTSTS_GINAKEFF_Pos) // 0x00000040 */ +#define GINTSTS_GINAKEFF GINTSTS_GINAKEFF_Msk // Global IN nonperiodic NAK effective */ #define GINTSTS_BOUTNAKEFF_Pos (7U) -#define GINTSTS_BOUTNAKEFF_Msk (0x1UL << GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ -#define GINTSTS_BOUTNAKEFF GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ +#define GINTSTS_BOUTNAKEFF_Msk (0x1UL << GINTSTS_BOUTNAKEFF_Pos) // 0x00000080 */ +#define GINTSTS_BOUTNAKEFF GINTSTS_BOUTNAKEFF_Msk // Global OUT NAK effective */ #define GINTSTS_ESUSP_Pos (10U) -#define GINTSTS_ESUSP_Msk (0x1UL << GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ -#define GINTSTS_ESUSP GINTSTS_ESUSP_Msk /*!< Early suspend */ +#define GINTSTS_ESUSP_Msk (0x1UL << GINTSTS_ESUSP_Pos) // 0x00000400 */ +#define GINTSTS_ESUSP GINTSTS_ESUSP_Msk // Early suspend */ #define GINTSTS_USBSUSP_Pos (11U) -#define GINTSTS_USBSUSP_Msk (0x1UL << GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */ -#define GINTSTS_USBSUSP GINTSTS_USBSUSP_Msk /*!< USB suspend */ +#define GINTSTS_USBSUSP_Msk (0x1UL << GINTSTS_USBSUSP_Pos) // 0x00000800 */ +#define GINTSTS_USBSUSP GINTSTS_USBSUSP_Msk // USB suspend */ #define GINTSTS_USBRST_Pos (12U) -#define GINTSTS_USBRST_Msk (0x1UL << GINTSTS_USBRST_Pos) /*!< 0x00001000 */ -#define GINTSTS_USBRST GINTSTS_USBRST_Msk /*!< USB reset */ +#define GINTSTS_USBRST_Msk (0x1UL << GINTSTS_USBRST_Pos) // 0x00001000 */ +#define GINTSTS_USBRST GINTSTS_USBRST_Msk // USB reset */ #define GINTSTS_ENUMDNE_Pos (13U) -#define GINTSTS_ENUMDNE_Msk (0x1UL << GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */ -#define GINTSTS_ENUMDNE GINTSTS_ENUMDNE_Msk /*!< Enumeration done */ +#define GINTSTS_ENUMDNE_Msk (0x1UL << GINTSTS_ENUMDNE_Pos) // 0x00002000 */ +#define GINTSTS_ENUMDNE GINTSTS_ENUMDNE_Msk // Enumeration done */ #define GINTSTS_ISOODRP_Pos (14U) -#define GINTSTS_ISOODRP_Msk (0x1UL << GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */ -#define GINTSTS_ISOODRP GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */ +#define GINTSTS_ISOODRP_Msk (0x1UL << GINTSTS_ISOODRP_Pos) // 0x00004000 */ +#define GINTSTS_ISOODRP GINTSTS_ISOODRP_Msk // Isochronous OUT packet dropped interrupt */ #define GINTSTS_EOPF_Pos (15U) -#define GINTSTS_EOPF_Msk (0x1UL << GINTSTS_EOPF_Pos) /*!< 0x00008000 */ -#define GINTSTS_EOPF GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */ +#define GINTSTS_EOPF_Msk (0x1UL << GINTSTS_EOPF_Pos) // 0x00008000 */ +#define GINTSTS_EOPF GINTSTS_EOPF_Msk // End of periodic frame interrupt */ #define GINTSTS_IEPINT_Pos (18U) -#define GINTSTS_IEPINT_Msk (0x1UL << GINTSTS_IEPINT_Pos) /*!< 0x00040000 */ -#define GINTSTS_IEPINT GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */ +#define GINTSTS_IEPINT_Msk (0x1UL << GINTSTS_IEPINT_Pos) // 0x00040000 */ +#define GINTSTS_IEPINT GINTSTS_IEPINT_Msk // IN endpoint interrupt */ #define GINTSTS_OEPINT_Pos (19U) -#define GINTSTS_OEPINT_Msk (0x1UL << GINTSTS_OEPINT_Pos) /*!< 0x00080000 */ -#define GINTSTS_OEPINT GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */ +#define GINTSTS_OEPINT_Msk (0x1UL << GINTSTS_OEPINT_Pos) // 0x00080000 */ +#define GINTSTS_OEPINT GINTSTS_OEPINT_Msk // OUT endpoint interrupt */ #define GINTSTS_IISOIXFR_Pos (20U) -#define GINTSTS_IISOIXFR_Msk (0x1UL << GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */ -#define GINTSTS_IISOIXFR GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */ +#define GINTSTS_IISOIXFR_Msk (0x1UL << GINTSTS_IISOIXFR_Pos) // 0x00100000 */ +#define GINTSTS_IISOIXFR GINTSTS_IISOIXFR_Msk // Incomplete isochronous IN transfer */ #define GINTSTS_PXFR_INCOMPISOOUT_Pos (21U) -#define GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */ -#define GINTSTS_PXFR_INCOMPISOOUT GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */ +#define GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << GINTSTS_PXFR_INCOMPISOOUT_Pos) // 0x00200000 */ +#define GINTSTS_PXFR_INCOMPISOOUT GINTSTS_PXFR_INCOMPISOOUT_Msk // Incomplete periodic transfer */ #define GINTSTS_DATAFSUSP_Pos (22U) -#define GINTSTS_DATAFSUSP_Msk (0x1UL << GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ -#define GINTSTS_DATAFSUSP GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ +#define GINTSTS_DATAFSUSP_Msk (0x1UL << GINTSTS_DATAFSUSP_Pos) // 0x00400000 */ +#define GINTSTS_DATAFSUSP GINTSTS_DATAFSUSP_Msk // Data fetch suspended */ #define GINTSTS_RSTDET_Pos (23U) -#define GINTSTS_RSTDET_Msk (0x1UL << GINTSTS_RSTDET_Pos) /*!< 0x00800000 */ -#define GINTSTS_RSTDET GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */ +#define GINTSTS_RSTDET_Msk (0x1UL << GINTSTS_RSTDET_Pos) // 0x00800000 */ +#define GINTSTS_RSTDET GINTSTS_RSTDET_Msk // Reset detected interrupt */ #define GINTSTS_HPRTINT_Pos (24U) -#define GINTSTS_HPRTINT_Msk (0x1UL << GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ -#define GINTSTS_HPRTINT GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ +#define GINTSTS_HPRTINT_Msk (0x1UL << GINTSTS_HPRTINT_Pos) // 0x01000000 */ +#define GINTSTS_HPRTINT GINTSTS_HPRTINT_Msk // Host port interrupt */ #define GINTSTS_HCINT_Pos (25U) -#define GINTSTS_HCINT_Msk (0x1UL << GINTSTS_HCINT_Pos) /*!< 0x02000000 */ -#define GINTSTS_HCINT GINTSTS_HCINT_Msk /*!< Host channels interrupt */ +#define GINTSTS_HCINT_Msk (0x1UL << GINTSTS_HCINT_Pos) // 0x02000000 */ +#define GINTSTS_HCINT GINTSTS_HCINT_Msk // Host channels interrupt */ #define GINTSTS_PTXFE_Pos (26U) -#define GINTSTS_PTXFE_Msk (0x1UL << GINTSTS_PTXFE_Pos) /*!< 0x04000000 */ -#define GINTSTS_PTXFE GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */ +#define GINTSTS_PTXFE_Msk (0x1UL << GINTSTS_PTXFE_Pos) // 0x04000000 */ +#define GINTSTS_PTXFE GINTSTS_PTXFE_Msk // Periodic TxFIFO empty */ #define GINTSTS_LPMINT_Pos (27U) -#define GINTSTS_LPMINT_Msk (0x1UL << GINTSTS_LPMINT_Pos) /*!< 0x08000000 */ -#define GINTSTS_LPMINT GINTSTS_LPMINT_Msk /*!< LPM interrupt */ +#define GINTSTS_LPMINT_Msk (0x1UL << GINTSTS_LPMINT_Pos) // 0x08000000 */ +#define GINTSTS_LPMINT GINTSTS_LPMINT_Msk // LPM interrupt */ #define GINTSTS_CIDSCHG_Pos (28U) -#define GINTSTS_CIDSCHG_Msk (0x1UL << GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */ -#define GINTSTS_CIDSCHG GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */ +#define GINTSTS_CIDSCHG_Msk (0x1UL << GINTSTS_CIDSCHG_Pos) // 0x10000000 */ +#define GINTSTS_CIDSCHG GINTSTS_CIDSCHG_Msk // Connector ID status change */ #define GINTSTS_DISCINT_Pos (29U) -#define GINTSTS_DISCINT_Msk (0x1UL << GINTSTS_DISCINT_Pos) /*!< 0x20000000 */ -#define GINTSTS_DISCINT GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */ +#define GINTSTS_DISCINT_Msk (0x1UL << GINTSTS_DISCINT_Pos) // 0x20000000 */ +#define GINTSTS_DISCINT GINTSTS_DISCINT_Msk // Disconnect detected interrupt */ #define GINTSTS_SRQINT_Pos (30U) -#define GINTSTS_SRQINT_Msk (0x1UL << GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ -#define GINTSTS_SRQINT GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ +#define GINTSTS_SRQINT_Msk (0x1UL << GINTSTS_SRQINT_Pos) // 0x40000000 */ +#define GINTSTS_SRQINT GINTSTS_SRQINT_Msk // Session request/new session detected interrupt */ #define GINTSTS_WKUINT_Pos (31U) -#define GINTSTS_WKUINT_Msk (0x1UL << GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ -#define GINTSTS_WKUINT GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ +#define GINTSTS_WKUINT_Msk (0x1UL << GINTSTS_WKUINT_Pos) // 0x80000000 */ +#define GINTSTS_WKUINT GINTSTS_WKUINT_Msk // Resume/remote wakeup detected interrupt */ /******************** Bit definition for GINTMSK register ********************/ #define GINTMSK_MMISM_Pos (1U) -#define GINTMSK_MMISM_Msk (0x1UL << GINTMSK_MMISM_Pos) /*!< 0x00000002 */ -#define GINTMSK_MMISM GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */ +#define GINTMSK_MMISM_Msk (0x1UL << GINTMSK_MMISM_Pos) // 0x00000002 */ +#define GINTMSK_MMISM GINTMSK_MMISM_Msk // Mode mismatch interrupt mask */ #define GINTMSK_OTGINT_Pos (2U) -#define GINTMSK_OTGINT_Msk (0x1UL << GINTMSK_OTGINT_Pos) /*!< 0x00000004 */ -#define GINTMSK_OTGINT GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */ +#define GINTMSK_OTGINT_Msk (0x1UL << GINTMSK_OTGINT_Pos) // 0x00000004 */ +#define GINTMSK_OTGINT GINTMSK_OTGINT_Msk // OTG interrupt mask */ #define GINTMSK_SOFM_Pos (3U) -#define GINTMSK_SOFM_Msk (0x1UL << GINTMSK_SOFM_Pos) /*!< 0x00000008 */ -#define GINTMSK_SOFM GINTMSK_SOFM_Msk /*!< Start of frame mask */ +#define GINTMSK_SOFM_Msk (0x1UL << GINTMSK_SOFM_Pos) // 0x00000008 */ +#define GINTMSK_SOFM GINTMSK_SOFM_Msk // Start of frame mask */ #define GINTMSK_RXFLVLM_Pos (4U) -#define GINTMSK_RXFLVLM_Msk (0x1UL << GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */ -#define GINTMSK_RXFLVLM GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */ +#define GINTMSK_RXFLVLM_Msk (0x1UL << GINTMSK_RXFLVLM_Pos) // 0x00000010 */ +#define GINTMSK_RXFLVLM GINTMSK_RXFLVLM_Msk // Receive FIFO nonempty mask */ #define GINTMSK_NPTXFEM_Pos (5U) -#define GINTMSK_NPTXFEM_Msk (0x1UL << GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */ -#define GINTMSK_NPTXFEM GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */ +#define GINTMSK_NPTXFEM_Msk (0x1UL << GINTMSK_NPTXFEM_Pos) // 0x00000020 */ +#define GINTMSK_NPTXFEM GINTMSK_NPTXFEM_Msk // Nonperiodic TxFIFO empty mask */ #define GINTMSK_GINAKEFFM_Pos (6U) -#define GINTMSK_GINAKEFFM_Msk (0x1UL << GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */ -#define GINTMSK_GINAKEFFM GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */ +#define GINTMSK_GINAKEFFM_Msk (0x1UL << GINTMSK_GINAKEFFM_Pos) // 0x00000040 */ +#define GINTMSK_GINAKEFFM GINTMSK_GINAKEFFM_Msk // Global nonperiodic IN NAK effective mask */ #define GINTMSK_GONAKEFFM_Pos (7U) -#define GINTMSK_GONAKEFFM_Msk (0x1UL << GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */ -#define GINTMSK_GONAKEFFM GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */ +#define GINTMSK_GONAKEFFM_Msk (0x1UL << GINTMSK_GONAKEFFM_Pos) // 0x00000080 */ +#define GINTMSK_GONAKEFFM GINTMSK_GONAKEFFM_Msk // Global OUT NAK effective mask */ #define GINTMSK_ESUSPM_Pos (10U) -#define GINTMSK_ESUSPM_Msk (0x1UL << GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */ -#define GINTMSK_ESUSPM GINTMSK_ESUSPM_Msk /*!< Early suspend mask */ +#define GINTMSK_ESUSPM_Msk (0x1UL << GINTMSK_ESUSPM_Pos) // 0x00000400 */ +#define GINTMSK_ESUSPM GINTMSK_ESUSPM_Msk // Early suspend mask */ #define GINTMSK_USBSUSPM_Pos (11U) -#define GINTMSK_USBSUSPM_Msk (0x1UL << GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */ -#define GINTMSK_USBSUSPM GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */ +#define GINTMSK_USBSUSPM_Msk (0x1UL << GINTMSK_USBSUSPM_Pos) // 0x00000800 */ +#define GINTMSK_USBSUSPM GINTMSK_USBSUSPM_Msk // USB suspend mask */ #define GINTMSK_USBRST_Pos (12U) -#define GINTMSK_USBRST_Msk (0x1UL << GINTMSK_USBRST_Pos) /*!< 0x00001000 */ -#define GINTMSK_USBRST GINTMSK_USBRST_Msk /*!< USB reset mask */ +#define GINTMSK_USBRST_Msk (0x1UL << GINTMSK_USBRST_Pos) // 0x00001000 */ +#define GINTMSK_USBRST GINTMSK_USBRST_Msk // USB reset mask */ #define GINTMSK_ENUMDNEM_Pos (13U) -#define GINTMSK_ENUMDNEM_Msk (0x1UL << GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */ -#define GINTMSK_ENUMDNEM GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */ +#define GINTMSK_ENUMDNEM_Msk (0x1UL << GINTMSK_ENUMDNEM_Pos) // 0x00002000 */ +#define GINTMSK_ENUMDNEM GINTMSK_ENUMDNEM_Msk // Enumeration done mask */ #define GINTMSK_ISOODRPM_Pos (14U) -#define GINTMSK_ISOODRPM_Msk (0x1UL << GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */ -#define GINTMSK_ISOODRPM GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */ +#define GINTMSK_ISOODRPM_Msk (0x1UL << GINTMSK_ISOODRPM_Pos) // 0x00004000 */ +#define GINTMSK_ISOODRPM GINTMSK_ISOODRPM_Msk // Isochronous OUT packet dropped interrupt mask */ #define GINTMSK_EOPFM_Pos (15U) -#define GINTMSK_EOPFM_Msk (0x1UL << GINTMSK_EOPFM_Pos) /*!< 0x00008000 */ -#define GINTMSK_EOPFM GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */ +#define GINTMSK_EOPFM_Msk (0x1UL << GINTMSK_EOPFM_Pos) // 0x00008000 */ +#define GINTMSK_EOPFM GINTMSK_EOPFM_Msk // End of periodic frame interrupt mask */ #define GINTMSK_EPMISM_Pos (17U) -#define GINTMSK_EPMISM_Msk (0x1UL << GINTMSK_EPMISM_Pos) /*!< 0x00020000 */ -#define GINTMSK_EPMISM GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */ +#define GINTMSK_EPMISM_Msk (0x1UL << GINTMSK_EPMISM_Pos) // 0x00020000 */ +#define GINTMSK_EPMISM GINTMSK_EPMISM_Msk // Endpoint mismatch interrupt mask */ #define GINTMSK_IEPINT_Pos (18U) -#define GINTMSK_IEPINT_Msk (0x1UL << GINTMSK_IEPINT_Pos) /*!< 0x00040000 */ -#define GINTMSK_IEPINT GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */ +#define GINTMSK_IEPINT_Msk (0x1UL << GINTMSK_IEPINT_Pos) // 0x00040000 */ +#define GINTMSK_IEPINT GINTMSK_IEPINT_Msk // IN endpoints interrupt mask */ #define GINTMSK_OEPINT_Pos (19U) -#define GINTMSK_OEPINT_Msk (0x1UL << GINTMSK_OEPINT_Pos) /*!< 0x00080000 */ -#define GINTMSK_OEPINT GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */ +#define GINTMSK_OEPINT_Msk (0x1UL << GINTMSK_OEPINT_Pos) // 0x00080000 */ +#define GINTMSK_OEPINT GINTMSK_OEPINT_Msk // OUT endpoints interrupt mask */ #define GINTMSK_IISOIXFRM_Pos (20U) -#define GINTMSK_IISOIXFRM_Msk (0x1UL << GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ -#define GINTMSK_IISOIXFRM GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ +#define GINTMSK_IISOIXFRM_Msk (0x1UL << GINTMSK_IISOIXFRM_Pos) // 0x00100000 */ +#define GINTMSK_IISOIXFRM GINTMSK_IISOIXFRM_Msk // Incomplete isochronous IN transfer mask */ #define GINTMSK_PXFRM_IISOOXFRM_Pos (21U) -#define GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ -#define GINTMSK_PXFRM_IISOOXFRM GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ +#define GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << GINTMSK_PXFRM_IISOOXFRM_Pos) // 0x00200000 */ +#define GINTMSK_PXFRM_IISOOXFRM GINTMSK_PXFRM_IISOOXFRM_Msk // Incomplete periodic transfer mask */ #define GINTMSK_FSUSPM_Pos (22U) -#define GINTMSK_FSUSPM_Msk (0x1UL << GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ -#define GINTMSK_FSUSPM GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ +#define GINTMSK_FSUSPM_Msk (0x1UL << GINTMSK_FSUSPM_Pos) // 0x00400000 */ +#define GINTMSK_FSUSPM GINTMSK_FSUSPM_Msk // Data fetch suspended mask */ #define GINTMSK_RSTDEM_Pos (23U) -#define GINTMSK_RSTDEM_Msk (0x1UL << GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */ -#define GINTMSK_RSTDEM GINTMSK_RSTDEM_Msk /*!< Reset detected interrupt mask */ +#define GINTMSK_RSTDEM_Msk (0x1UL << GINTMSK_RSTDEM_Pos) // 0x00800000 */ +#define GINTMSK_RSTDEM GINTMSK_RSTDEM_Msk // Reset detected interrupt mask */ #define GINTMSK_PRTIM_Pos (24U) -#define GINTMSK_PRTIM_Msk (0x1UL << GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ -#define GINTMSK_PRTIM GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ +#define GINTMSK_PRTIM_Msk (0x1UL << GINTMSK_PRTIM_Pos) // 0x01000000 */ +#define GINTMSK_PRTIM GINTMSK_PRTIM_Msk // Host port interrupt mask */ #define GINTMSK_HCIM_Pos (25U) -#define GINTMSK_HCIM_Msk (0x1UL << GINTMSK_HCIM_Pos) /*!< 0x02000000 */ -#define GINTMSK_HCIM GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */ +#define GINTMSK_HCIM_Msk (0x1UL << GINTMSK_HCIM_Pos) // 0x02000000 */ +#define GINTMSK_HCIM GINTMSK_HCIM_Msk // Host channels interrupt mask */ #define GINTMSK_PTXFEM_Pos (26U) -#define GINTMSK_PTXFEM_Msk (0x1UL << GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */ -#define GINTMSK_PTXFEM GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */ +#define GINTMSK_PTXFEM_Msk (0x1UL << GINTMSK_PTXFEM_Pos) // 0x04000000 */ +#define GINTMSK_PTXFEM GINTMSK_PTXFEM_Msk // Periodic TxFIFO empty mask */ #define GINTMSK_LPMINTM_Pos (27U) -#define GINTMSK_LPMINTM_Msk (0x1UL << GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */ -#define GINTMSK_LPMINTM GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */ +#define GINTMSK_LPMINTM_Msk (0x1UL << GINTMSK_LPMINTM_Pos) // 0x08000000 */ +#define GINTMSK_LPMINTM GINTMSK_LPMINTM_Msk // LPM interrupt Mask */ #define GINTMSK_CIDSCHGM_Pos (28U) -#define GINTMSK_CIDSCHGM_Msk (0x1UL << GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */ -#define GINTMSK_CIDSCHGM GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */ +#define GINTMSK_CIDSCHGM_Msk (0x1UL << GINTMSK_CIDSCHGM_Pos) // 0x10000000 */ +#define GINTMSK_CIDSCHGM GINTMSK_CIDSCHGM_Msk // Connector ID status change mask */ #define GINTMSK_DISCINT_Pos (29U) -#define GINTMSK_DISCINT_Msk (0x1UL << GINTMSK_DISCINT_Pos) /*!< 0x20000000 */ -#define GINTMSK_DISCINT GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */ +#define GINTMSK_DISCINT_Msk (0x1UL << GINTMSK_DISCINT_Pos) // 0x20000000 */ +#define GINTMSK_DISCINT GINTMSK_DISCINT_Msk // Disconnect detected interrupt mask */ #define GINTMSK_SRQIM_Pos (30U) -#define GINTMSK_SRQIM_Msk (0x1UL << GINTMSK_SRQIM_Pos) /*!< 0x40000000 */ -#define GINTMSK_SRQIM GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */ +#define GINTMSK_SRQIM_Msk (0x1UL << GINTMSK_SRQIM_Pos) // 0x40000000 */ +#define GINTMSK_SRQIM GINTMSK_SRQIM_Msk // Session request/new session detected interrupt mask */ #define GINTMSK_WUIM_Pos (31U) -#define GINTMSK_WUIM_Msk (0x1UL << GINTMSK_WUIM_Pos) /*!< 0x80000000 */ -#define GINTMSK_WUIM GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */ +#define GINTMSK_WUIM_Msk (0x1UL << GINTMSK_WUIM_Pos) // 0x80000000 */ +#define GINTMSK_WUIM GINTMSK_WUIM_Msk // Resume/remote wakeup detected interrupt mask */ /******************** Bit definition for DAINT register ********************/ #define DAINT_IEPINT_Pos (0U) -#define DAINT_IEPINT_Msk (0xFFFFUL << DAINT_IEPINT_Pos) /*!< 0x0000FFFF */ -#define DAINT_IEPINT DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */ +#define DAINT_IEPINT_Msk (0xFFFFUL << DAINT_IEPINT_Pos) // 0x0000FFFF */ +#define DAINT_IEPINT DAINT_IEPINT_Msk // IN endpoint interrupt bits */ #define DAINT_OEPINT_Pos (16U) -#define DAINT_OEPINT_Msk (0xFFFFUL << DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */ -#define DAINT_OEPINT DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */ +#define DAINT_OEPINT_Msk (0xFFFFUL << DAINT_OEPINT_Pos) // 0xFFFF0000 */ +#define DAINT_OEPINT DAINT_OEPINT_Msk // OUT endpoint interrupt bits */ /******************** Bit definition for HAINTMSK register ********************/ #define HAINTMSK_HAINTM_Pos (0U) -#define HAINTMSK_HAINTM_Msk (0xFFFFUL << HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ -#define HAINTMSK_HAINTM HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ +#define HAINTMSK_HAINTM_Msk (0xFFFFUL << HAINTMSK_HAINTM_Pos) // 0x0000FFFF */ +#define HAINTMSK_HAINTM HAINTMSK_HAINTM_Msk // Channel interrupt mask */ /******************** Bit definition for GRXSTSP register ********************/ #define GRXSTSP_EPNUM_Pos (0U) -#define GRXSTSP_EPNUM_Msk (0xFUL << GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ -#define GRXSTSP_EPNUM GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ +#define GRXSTSP_EPNUM_Msk (0xFUL << GRXSTSP_EPNUM_Pos) // 0x0000000F */ +#define GRXSTSP_EPNUM GRXSTSP_EPNUM_Msk // IN EP interrupt mask bits */ #define GRXSTSP_BCNT_Pos (4U) -#define GRXSTSP_BCNT_Msk (0x7FFUL << GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ -#define GRXSTSP_BCNT GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ +#define GRXSTSP_BCNT_Msk (0x7FFUL << GRXSTSP_BCNT_Pos) // 0x00007FF0 */ +#define GRXSTSP_BCNT GRXSTSP_BCNT_Msk // OUT EP interrupt mask bits */ #define GRXSTSP_DPID_Pos (15U) -#define GRXSTSP_DPID_Msk (0x3UL << GRXSTSP_DPID_Pos) /*!< 0x00018000 */ -#define GRXSTSP_DPID GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ +#define GRXSTSP_DPID_Msk (0x3UL << GRXSTSP_DPID_Pos) // 0x00018000 */ +#define GRXSTSP_DPID GRXSTSP_DPID_Msk // OUT EP interrupt mask bits */ #define GRXSTSP_PKTSTS_Pos (17U) -#define GRXSTSP_PKTSTS_Msk (0xFUL << GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ -#define GRXSTSP_PKTSTS GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ +#define GRXSTSP_PKTSTS_Msk (0xFUL << GRXSTSP_PKTSTS_Pos) // 0x001E0000 */ +#define GRXSTSP_PKTSTS GRXSTSP_PKTSTS_Msk // OUT EP interrupt mask bits */ /******************** Bit definition for DAINTMSK register ********************/ #define DAINTMSK_IEPM_Pos (0U) -#define DAINTMSK_IEPM_Msk (0xFFFFUL << DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */ -#define DAINTMSK_IEPM DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */ +#define DAINTMSK_IEPM_Msk (0xFFFFUL << DAINTMSK_IEPM_Pos) // 0x0000FFFF */ +#define DAINTMSK_IEPM DAINTMSK_IEPM_Msk // IN EP interrupt mask bits */ #define DAINTMSK_OEPM_Pos (16U) -#define DAINTMSK_OEPM_Msk (0xFFFFUL << DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */ -#define DAINTMSK_OEPM DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */ +#define DAINTMSK_OEPM_Msk (0xFFFFUL << DAINTMSK_OEPM_Pos) // 0xFFFF0000 */ +#define DAINTMSK_OEPM DAINTMSK_OEPM_Msk // OUT EP interrupt mask bits */ /******************** Bit definition for OTG register ********************/ #define CHNUM_Pos (0U) -#define CHNUM_Msk (0xFUL << CHNUM_Pos) /*!< 0x0000000F */ -#define CHNUM CHNUM_Msk /*!< Channel number */ -#define CHNUM_0 (0x1UL << CHNUM_Pos) /*!< 0x00000001 */ -#define CHNUM_1 (0x2UL << CHNUM_Pos) /*!< 0x00000002 */ -#define CHNUM_2 (0x4UL << CHNUM_Pos) /*!< 0x00000004 */ -#define CHNUM_3 (0x8UL << CHNUM_Pos) /*!< 0x00000008 */ +#define CHNUM_Msk (0xFUL << CHNUM_Pos) // 0x0000000F */ +#define CHNUM CHNUM_Msk // Channel number */ +#define CHNUM_0 (0x1UL << CHNUM_Pos) // 0x00000001 */ +#define CHNUM_1 (0x2UL << CHNUM_Pos) // 0x00000002 */ +#define CHNUM_2 (0x4UL << CHNUM_Pos) // 0x00000004 */ +#define CHNUM_3 (0x8UL << CHNUM_Pos) // 0x00000008 */ #define BCNT_Pos (4U) -#define BCNT_Msk (0x7FFUL << BCNT_Pos) /*!< 0x00007FF0 */ -#define BCNT BCNT_Msk /*!< Byte count */ +#define BCNT_Msk (0x7FFUL << BCNT_Pos) // 0x00007FF0 */ +#define BCNT BCNT_Msk // Byte count */ #define DPID_Pos (15U) -#define DPID_Msk (0x3UL << DPID_Pos) /*!< 0x00018000 */ -#define DPID DPID_Msk /*!< Data PID */ -#define DPID_0 (0x1UL << DPID_Pos) /*!< 0x00008000 */ -#define DPID_1 (0x2UL << DPID_Pos) /*!< 0x00010000 */ +#define DPID_Msk (0x3UL << DPID_Pos) // 0x00018000 */ +#define DPID DPID_Msk // Data PID */ +#define DPID_0 (0x1UL << DPID_Pos) // 0x00008000 */ +#define DPID_1 (0x2UL << DPID_Pos) // 0x00010000 */ #define PKTSTS_Pos (17U) -#define PKTSTS_Msk (0xFUL << PKTSTS_Pos) /*!< 0x001E0000 */ -#define PKTSTS PKTSTS_Msk /*!< Packet status */ -#define PKTSTS_0 (0x1UL << PKTSTS_Pos) /*!< 0x00020000 */ -#define PKTSTS_1 (0x2UL << PKTSTS_Pos) /*!< 0x00040000 */ -#define PKTSTS_2 (0x4UL << PKTSTS_Pos) /*!< 0x00080000 */ -#define PKTSTS_3 (0x8UL << PKTSTS_Pos) /*!< 0x00100000 */ +#define PKTSTS_Msk (0xFUL << PKTSTS_Pos) // 0x001E0000 */ +#define PKTSTS PKTSTS_Msk // Packet status */ +#define PKTSTS_0 (0x1UL << PKTSTS_Pos) // 0x00020000 */ +#define PKTSTS_1 (0x2UL << PKTSTS_Pos) // 0x00040000 */ +#define PKTSTS_2 (0x4UL << PKTSTS_Pos) // 0x00080000 */ +#define PKTSTS_3 (0x8UL << PKTSTS_Pos) // 0x00100000 */ #define EPNUM_Pos (0U) -#define EPNUM_Msk (0xFUL << EPNUM_Pos) /*!< 0x0000000F */ -#define EPNUM EPNUM_Msk /*!< Endpoint number */ -#define EPNUM_0 (0x1UL << EPNUM_Pos) /*!< 0x00000001 */ -#define EPNUM_1 (0x2UL << EPNUM_Pos) /*!< 0x00000002 */ -#define EPNUM_2 (0x4UL << EPNUM_Pos) /*!< 0x00000004 */ -#define EPNUM_3 (0x8UL << EPNUM_Pos) /*!< 0x00000008 */ +#define EPNUM_Msk (0xFUL << EPNUM_Pos) // 0x0000000F */ +#define EPNUM EPNUM_Msk // Endpoint number */ +#define EPNUM_0 (0x1UL << EPNUM_Pos) // 0x00000001 */ +#define EPNUM_1 (0x2UL << EPNUM_Pos) // 0x00000002 */ +#define EPNUM_2 (0x4UL << EPNUM_Pos) // 0x00000004 */ +#define EPNUM_3 (0x8UL << EPNUM_Pos) // 0x00000008 */ #define FRMNUM_Pos (21U) -#define FRMNUM_Msk (0xFUL << FRMNUM_Pos) /*!< 0x01E00000 */ -#define FRMNUM FRMNUM_Msk /*!< Frame number */ -#define FRMNUM_0 (0x1UL << FRMNUM_Pos) /*!< 0x00200000 */ -#define FRMNUM_1 (0x2UL << FRMNUM_Pos) /*!< 0x00400000 */ -#define FRMNUM_2 (0x4UL << FRMNUM_Pos) /*!< 0x00800000 */ -#define FRMNUM_3 (0x8UL << FRMNUM_Pos) /*!< 0x01000000 */ +#define FRMNUM_Msk (0xFUL << FRMNUM_Pos) // 0x01E00000 */ +#define FRMNUM FRMNUM_Msk // Frame number */ +#define FRMNUM_0 (0x1UL << FRMNUM_Pos) // 0x00200000 */ +#define FRMNUM_1 (0x2UL << FRMNUM_Pos) // 0x00400000 */ +#define FRMNUM_2 (0x4UL << FRMNUM_Pos) // 0x00800000 */ +#define FRMNUM_3 (0x8UL << FRMNUM_Pos) // 0x01000000 */ /******************** Bit definition for GRXFSIZ register ********************/ #define GRXFSIZ_RXFD_Pos (0U) -#define GRXFSIZ_RXFD_Msk (0xFFFFUL << GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */ -#define GRXFSIZ_RXFD GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */ +#define GRXFSIZ_RXFD_Msk (0xFFFFUL << GRXFSIZ_RXFD_Pos) // 0x0000FFFF */ +#define GRXFSIZ_RXFD GRXFSIZ_RXFD_Msk // RxFIFO depth */ /******************** Bit definition for DVBUSDIS register ********************/ #define DVBUSDIS_VBUSDT_Pos (0U) -#define DVBUSDIS_VBUSDT_Msk (0xFFFFUL << DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */ -#define DVBUSDIS_VBUSDT DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */ +#define DVBUSDIS_VBUSDT_Msk (0xFFFFUL << DVBUSDIS_VBUSDT_Pos) // 0x0000FFFF */ +#define DVBUSDIS_VBUSDT DVBUSDIS_VBUSDT_Msk // Device VBUS discharge time */ /******************** Bit definition for OTG register ********************/ #define NPTXFSA_Pos (0U) -#define NPTXFSA_Msk (0xFFFFUL << NPTXFSA_Pos) /*!< 0x0000FFFF */ -#define NPTXFSA NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */ +#define NPTXFSA_Msk (0xFFFFUL << NPTXFSA_Pos) // 0x0000FFFF */ +#define NPTXFSA NPTXFSA_Msk // Nonperiodic transmit RAM start address */ #define NPTXFD_Pos (16U) -#define NPTXFD_Msk (0xFFFFUL << NPTXFD_Pos) /*!< 0xFFFF0000 */ -#define NPTXFD NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */ +#define NPTXFD_Msk (0xFFFFUL << NPTXFD_Pos) // 0xFFFF0000 */ +#define NPTXFD NPTXFD_Msk // Nonperiodic TxFIFO depth */ #define TX0FSA_Pos (0U) -#define TX0FSA_Msk (0xFFFFUL << TX0FSA_Pos) /*!< 0x0000FFFF */ -#define TX0FSA TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */ +#define TX0FSA_Msk (0xFFFFUL << TX0FSA_Pos) // 0x0000FFFF */ +#define TX0FSA TX0FSA_Msk // Endpoint 0 transmit RAM start address */ #define TX0FD_Pos (16U) -#define TX0FD_Msk (0xFFFFUL << TX0FD_Pos) /*!< 0xFFFF0000 */ -#define TX0FD TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */ +#define TX0FD_Msk (0xFFFFUL << TX0FD_Pos) // 0xFFFF0000 */ +#define TX0FD TX0FD_Msk // Endpoint 0 TxFIFO depth */ /******************** Bit definition for DVBUSPULSE register ********************/ #define DVBUSPULSE_DVBUSP_Pos (0U) -#define DVBUSPULSE_DVBUSP_Msk (0xFFFUL << DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */ -#define DVBUSPULSE_DVBUSP DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */ +#define DVBUSPULSE_DVBUSP_Msk (0xFFFUL << DVBUSPULSE_DVBUSP_Pos) // 0x00000FFF */ +#define DVBUSPULSE_DVBUSP DVBUSPULSE_DVBUSP_Msk // Device VBUS pulsing time */ /******************** Bit definition for GNPTXSTS register ********************/ #define GNPTXSTS_NPTXFSAV_Pos (0U) -#define GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */ -#define GNPTXSTS_NPTXFSAV GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */ +#define GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << GNPTXSTS_NPTXFSAV_Pos) // 0x0000FFFF */ +#define GNPTXSTS_NPTXFSAV GNPTXSTS_NPTXFSAV_Msk // Nonperiodic TxFIFO space available */ #define GNPTXSTS_NPTQXSAV_Pos (16U) -#define GNPTXSTS_NPTQXSAV_Msk (0xFFUL << GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */ -#define GNPTXSTS_NPTQXSAV GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */ -#define GNPTXSTS_NPTQXSAV_0 (0x01UL << GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */ -#define GNPTXSTS_NPTQXSAV_1 (0x02UL << GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */ -#define GNPTXSTS_NPTQXSAV_2 (0x04UL << GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */ -#define GNPTXSTS_NPTQXSAV_3 (0x08UL << GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */ -#define GNPTXSTS_NPTQXSAV_4 (0x10UL << GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */ -#define GNPTXSTS_NPTQXSAV_5 (0x20UL << GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */ -#define GNPTXSTS_NPTQXSAV_6 (0x40UL << GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */ -#define GNPTXSTS_NPTQXSAV_7 (0x80UL << GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */ +#define GNPTXSTS_NPTQXSAV_Msk (0xFFUL << GNPTXSTS_NPTQXSAV_Pos) // 0x00FF0000 */ +#define GNPTXSTS_NPTQXSAV GNPTXSTS_NPTQXSAV_Msk // Nonperiodic transmit request queue space available */ +#define GNPTXSTS_NPTQXSAV_0 (0x01UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00010000 */ +#define GNPTXSTS_NPTQXSAV_1 (0x02UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00020000 */ +#define GNPTXSTS_NPTQXSAV_2 (0x04UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00040000 */ +#define GNPTXSTS_NPTQXSAV_3 (0x08UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00080000 */ +#define GNPTXSTS_NPTQXSAV_4 (0x10UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00100000 */ +#define GNPTXSTS_NPTQXSAV_5 (0x20UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00200000 */ +#define GNPTXSTS_NPTQXSAV_6 (0x40UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00400000 */ +#define GNPTXSTS_NPTQXSAV_7 (0x80UL << GNPTXSTS_NPTQXSAV_Pos) // 0x00800000 */ #define GNPTXSTS_NPTXQTOP_Pos (24U) -#define GNPTXSTS_NPTXQTOP_Msk (0x7FUL << GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */ -#define GNPTXSTS_NPTXQTOP GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */ -#define GNPTXSTS_NPTXQTOP_0 (0x01UL << GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */ -#define GNPTXSTS_NPTXQTOP_1 (0x02UL << GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */ -#define GNPTXSTS_NPTXQTOP_2 (0x04UL << GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */ -#define GNPTXSTS_NPTXQTOP_3 (0x08UL << GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */ -#define GNPTXSTS_NPTXQTOP_4 (0x10UL << GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */ -#define GNPTXSTS_NPTXQTOP_5 (0x20UL << GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */ -#define GNPTXSTS_NPTXQTOP_6 (0x40UL << GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */ +#define GNPTXSTS_NPTXQTOP_Msk (0x7FUL << GNPTXSTS_NPTXQTOP_Pos) // 0x7F000000 */ +#define GNPTXSTS_NPTXQTOP GNPTXSTS_NPTXQTOP_Msk // Top of the nonperiodic transmit request queue */ +#define GNPTXSTS_NPTXQTOP_0 (0x01UL << GNPTXSTS_NPTXQTOP_Pos) // 0x01000000 */ +#define GNPTXSTS_NPTXQTOP_1 (0x02UL << GNPTXSTS_NPTXQTOP_Pos) // 0x02000000 */ +#define GNPTXSTS_NPTXQTOP_2 (0x04UL << GNPTXSTS_NPTXQTOP_Pos) // 0x04000000 */ +#define GNPTXSTS_NPTXQTOP_3 (0x08UL << GNPTXSTS_NPTXQTOP_Pos) // 0x08000000 */ +#define GNPTXSTS_NPTXQTOP_4 (0x10UL << GNPTXSTS_NPTXQTOP_Pos) // 0x10000000 */ +#define GNPTXSTS_NPTXQTOP_5 (0x20UL << GNPTXSTS_NPTXQTOP_Pos) // 0x20000000 */ +#define GNPTXSTS_NPTXQTOP_6 (0x40UL << GNPTXSTS_NPTXQTOP_Pos) // 0x40000000 */ /******************** Bit definition for DTHRCTL register ********************/ #define DTHRCTL_NONISOTHREN_Pos (0U) -#define DTHRCTL_NONISOTHREN_Msk (0x1UL << DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */ -#define DTHRCTL_NONISOTHREN DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */ +#define DTHRCTL_NONISOTHREN_Msk (0x1UL << DTHRCTL_NONISOTHREN_Pos) // 0x00000001 */ +#define DTHRCTL_NONISOTHREN DTHRCTL_NONISOTHREN_Msk // Nonisochronous IN endpoints threshold enable */ #define DTHRCTL_ISOTHREN_Pos (1U) -#define DTHRCTL_ISOTHREN_Msk (0x1UL << DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */ -#define DTHRCTL_ISOTHREN DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */ +#define DTHRCTL_ISOTHREN_Msk (0x1UL << DTHRCTL_ISOTHREN_Pos) // 0x00000002 */ +#define DTHRCTL_ISOTHREN DTHRCTL_ISOTHREN_Msk // ISO IN endpoint threshold enable */ #define DTHRCTL_TXTHRLEN_Pos (2U) -#define DTHRCTL_TXTHRLEN_Msk (0x1FFUL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */ -#define DTHRCTL_TXTHRLEN DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */ -#define DTHRCTL_TXTHRLEN_0 (0x001UL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */ -#define DTHRCTL_TXTHRLEN_1 (0x002UL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */ -#define DTHRCTL_TXTHRLEN_2 (0x004UL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */ -#define DTHRCTL_TXTHRLEN_3 (0x008UL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */ -#define DTHRCTL_TXTHRLEN_4 (0x010UL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */ -#define DTHRCTL_TXTHRLEN_5 (0x020UL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */ -#define DTHRCTL_TXTHRLEN_6 (0x040UL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */ -#define DTHRCTL_TXTHRLEN_7 (0x080UL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */ -#define DTHRCTL_TXTHRLEN_8 (0x100UL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */ +#define DTHRCTL_TXTHRLEN_Msk (0x1FFUL << DTHRCTL_TXTHRLEN_Pos) // 0x000007FC */ +#define DTHRCTL_TXTHRLEN DTHRCTL_TXTHRLEN_Msk // Transmit threshold length */ +#define DTHRCTL_TXTHRLEN_0 (0x001UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000004 */ +#define DTHRCTL_TXTHRLEN_1 (0x002UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000008 */ +#define DTHRCTL_TXTHRLEN_2 (0x004UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000010 */ +#define DTHRCTL_TXTHRLEN_3 (0x008UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000020 */ +#define DTHRCTL_TXTHRLEN_4 (0x010UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000040 */ +#define DTHRCTL_TXTHRLEN_5 (0x020UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000080 */ +#define DTHRCTL_TXTHRLEN_6 (0x040UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000100 */ +#define DTHRCTL_TXTHRLEN_7 (0x080UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000200 */ +#define DTHRCTL_TXTHRLEN_8 (0x100UL << DTHRCTL_TXTHRLEN_Pos) // 0x00000400 */ #define DTHRCTL_RXTHREN_Pos (16U) -#define DTHRCTL_RXTHREN_Msk (0x1UL << DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */ -#define DTHRCTL_RXTHREN DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */ +#define DTHRCTL_RXTHREN_Msk (0x1UL << DTHRCTL_RXTHREN_Pos) // 0x00010000 */ +#define DTHRCTL_RXTHREN DTHRCTL_RXTHREN_Msk // Receive threshold enable */ #define DTHRCTL_RXTHRLEN_Pos (17U) -#define DTHRCTL_RXTHRLEN_Msk (0x1FFUL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */ -#define DTHRCTL_RXTHRLEN DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */ -#define DTHRCTL_RXTHRLEN_0 (0x001UL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */ -#define DTHRCTL_RXTHRLEN_1 (0x002UL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */ -#define DTHRCTL_RXTHRLEN_2 (0x004UL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */ -#define DTHRCTL_RXTHRLEN_3 (0x008UL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */ -#define DTHRCTL_RXTHRLEN_4 (0x010UL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */ -#define DTHRCTL_RXTHRLEN_5 (0x020UL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */ -#define DTHRCTL_RXTHRLEN_6 (0x040UL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */ -#define DTHRCTL_RXTHRLEN_7 (0x080UL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */ -#define DTHRCTL_RXTHRLEN_8 (0x100UL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */ +#define DTHRCTL_RXTHRLEN_Msk (0x1FFUL << DTHRCTL_RXTHRLEN_Pos) // 0x03FE0000 */ +#define DTHRCTL_RXTHRLEN DTHRCTL_RXTHRLEN_Msk // Receive threshold length */ +#define DTHRCTL_RXTHRLEN_0 (0x001UL << DTHRCTL_RXTHRLEN_Pos) // 0x00020000 */ +#define DTHRCTL_RXTHRLEN_1 (0x002UL << DTHRCTL_RXTHRLEN_Pos) // 0x00040000 */ +#define DTHRCTL_RXTHRLEN_2 (0x004UL << DTHRCTL_RXTHRLEN_Pos) // 0x00080000 */ +#define DTHRCTL_RXTHRLEN_3 (0x008UL << DTHRCTL_RXTHRLEN_Pos) // 0x00100000 */ +#define DTHRCTL_RXTHRLEN_4 (0x010UL << DTHRCTL_RXTHRLEN_Pos) // 0x00200000 */ +#define DTHRCTL_RXTHRLEN_5 (0x020UL << DTHRCTL_RXTHRLEN_Pos) // 0x00400000 */ +#define DTHRCTL_RXTHRLEN_6 (0x040UL << DTHRCTL_RXTHRLEN_Pos) // 0x00800000 */ +#define DTHRCTL_RXTHRLEN_7 (0x080UL << DTHRCTL_RXTHRLEN_Pos) // 0x01000000 */ +#define DTHRCTL_RXTHRLEN_8 (0x100UL << DTHRCTL_RXTHRLEN_Pos) // 0x02000000 */ #define DTHRCTL_ARPEN_Pos (27U) -#define DTHRCTL_ARPEN_Msk (0x1UL << DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */ -#define DTHRCTL_ARPEN DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */ +#define DTHRCTL_ARPEN_Msk (0x1UL << DTHRCTL_ARPEN_Pos) // 0x08000000 */ +#define DTHRCTL_ARPEN DTHRCTL_ARPEN_Msk // Arbiter parking enable */ /******************** Bit definition for DIEPEMPMSK register ********************/ #define DIEPEMPMSK_INEPTXFEM_Pos (0U) -#define DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */ -#define DIEPEMPMSK_INEPTXFEM DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */ +#define DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << DIEPEMPMSK_INEPTXFEM_Pos) // 0x0000FFFF */ +#define DIEPEMPMSK_INEPTXFEM DIEPEMPMSK_INEPTXFEM_Msk // IN EP Tx FIFO empty interrupt mask bits */ /******************** Bit definition for DEACHINT register ********************/ #define DEACHINT_IEP1INT_Pos (1U) -#define DEACHINT_IEP1INT_Msk (0x1UL << DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */ -#define DEACHINT_IEP1INT DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */ +#define DEACHINT_IEP1INT_Msk (0x1UL << DEACHINT_IEP1INT_Pos) // 0x00000002 */ +#define DEACHINT_IEP1INT DEACHINT_IEP1INT_Msk // IN endpoint 1interrupt bit */ #define DEACHINT_OEP1INT_Pos (17U) -#define DEACHINT_OEP1INT_Msk (0x1UL << DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */ -#define DEACHINT_OEP1INT DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */ +#define DEACHINT_OEP1INT_Msk (0x1UL << DEACHINT_OEP1INT_Pos) // 0x00020000 */ +#define DEACHINT_OEP1INT DEACHINT_OEP1INT_Msk // OUT endpoint 1 interrupt bit */ /******************** Bit definition for GCCFG register ********************/ #define GCCFG_DCDET_Pos (0U) -#define GCCFG_DCDET_Msk (0x1UL << GCCFG_DCDET_Pos) /*!< 0x00000001 */ -#define GCCFG_DCDET GCCFG_DCDET_Msk /*!< Data contact detection (DCD) status */ +#define GCCFG_DCDET_Msk (0x1UL << GCCFG_DCDET_Pos) // 0x00000001 */ +#define GCCFG_DCDET GCCFG_DCDET_Msk // Data contact detection (DCD) status */ #define GCCFG_PDET_Pos (1U) -#define GCCFG_PDET_Msk (0x1UL << GCCFG_PDET_Pos) /*!< 0x00000002 */ -#define GCCFG_PDET GCCFG_PDET_Msk /*!< Primary detection (PD) status */ +#define GCCFG_PDET_Msk (0x1UL << GCCFG_PDET_Pos) // 0x00000002 */ +#define GCCFG_PDET GCCFG_PDET_Msk // Primary detection (PD) status */ #define GCCFG_SDET_Pos (2U) -#define GCCFG_SDET_Msk (0x1UL << GCCFG_SDET_Pos) /*!< 0x00000004 */ -#define GCCFG_SDET GCCFG_SDET_Msk /*!< Secondary detection (SD) status */ +#define GCCFG_SDET_Msk (0x1UL << GCCFG_SDET_Pos) // 0x00000004 */ +#define GCCFG_SDET GCCFG_SDET_Msk // Secondary detection (SD) status */ #define GCCFG_PS2DET_Pos (3U) -#define GCCFG_PS2DET_Msk (0x1UL << GCCFG_PS2DET_Pos) /*!< 0x00000008 */ -#define GCCFG_PS2DET GCCFG_PS2DET_Msk /*!< DM pull-up detection status */ +#define GCCFG_PS2DET_Msk (0x1UL << GCCFG_PS2DET_Pos) // 0x00000008 */ +#define GCCFG_PS2DET GCCFG_PS2DET_Msk // DM pull-up detection status */ #define GCCFG_PWRDWN_Pos (16U) -#define GCCFG_PWRDWN_Msk (0x1UL << GCCFG_PWRDWN_Pos) /*!< 0x00010000 */ -#define GCCFG_PWRDWN GCCFG_PWRDWN_Msk /*!< Power down */ +#define GCCFG_PWRDWN_Msk (0x1UL << GCCFG_PWRDWN_Pos) // 0x00010000 */ +#define GCCFG_PWRDWN GCCFG_PWRDWN_Msk // Power down */ #define GCCFG_BCDEN_Pos (17U) -#define GCCFG_BCDEN_Msk (0x1UL << GCCFG_BCDEN_Pos) /*!< 0x00020000 */ -#define GCCFG_BCDEN GCCFG_BCDEN_Msk /*!< Battery charging detector (BCD) enable */ +#define GCCFG_BCDEN_Msk (0x1UL << GCCFG_BCDEN_Pos) // 0x00020000 */ +#define GCCFG_BCDEN GCCFG_BCDEN_Msk // Battery charging detector (BCD) enable */ #define GCCFG_DCDEN_Pos (18U) -#define GCCFG_DCDEN_Msk (0x1UL << GCCFG_DCDEN_Pos) /*!< 0x00040000 */ -#define GCCFG_DCDEN GCCFG_DCDEN_Msk /*!< Data contact detection (DCD) mode enable*/ +#define GCCFG_DCDEN_Msk (0x1UL << GCCFG_DCDEN_Pos) // 0x00040000 */ +#define GCCFG_DCDEN GCCFG_DCDEN_Msk // Data contact detection (DCD) mode enable*/ #define GCCFG_PDEN_Pos (19U) -#define GCCFG_PDEN_Msk (0x1UL << GCCFG_PDEN_Pos) /*!< 0x00080000 */ -#define GCCFG_PDEN GCCFG_PDEN_Msk /*!< Primary detection (PD) mode enable*/ +#define GCCFG_PDEN_Msk (0x1UL << GCCFG_PDEN_Pos) // 0x00080000 */ +#define GCCFG_PDEN GCCFG_PDEN_Msk // Primary detection (PD) mode enable*/ #define GCCFG_SDEN_Pos (20U) -#define GCCFG_SDEN_Msk (0x1UL << GCCFG_SDEN_Pos) /*!< 0x00100000 */ -#define GCCFG_SDEN GCCFG_SDEN_Msk /*!< Secondary detection (SD) mode enable */ +#define GCCFG_SDEN_Msk (0x1UL << GCCFG_SDEN_Pos) // 0x00100000 */ +#define GCCFG_SDEN GCCFG_SDEN_Msk // Secondary detection (SD) mode enable */ #define GCCFG_VBDEN_Pos (21U) -#define GCCFG_VBDEN_Msk (0x1UL << GCCFG_VBDEN_Pos) /*!< 0x00200000 */ -#define GCCFG_VBDEN GCCFG_VBDEN_Msk /*!< VBUS mode enable */ +#define GCCFG_VBDEN_Msk (0x1UL << GCCFG_VBDEN_Pos) // 0x00200000 */ +#define GCCFG_VBDEN GCCFG_VBDEN_Msk // VBUS mode enable */ #define GCCFG_OTGIDEN_Pos (22U) -#define GCCFG_OTGIDEN_Msk (0x1UL << GCCFG_OTGIDEN_Pos) /*!< 0x00400000 */ -#define GCCFG_OTGIDEN GCCFG_OTGIDEN_Msk /*!< OTG Id enable */ +#define GCCFG_OTGIDEN_Msk (0x1UL << GCCFG_OTGIDEN_Pos) // 0x00400000 */ +#define GCCFG_OTGIDEN GCCFG_OTGIDEN_Msk // OTG Id enable */ #define GCCFG_PHYHSEN_Pos (23U) -#define GCCFG_PHYHSEN_Msk (0x1UL << GCCFG_PHYHSEN_Pos) /*!< 0x00800000 */ -#define GCCFG_PHYHSEN GCCFG_PHYHSEN_Msk /*!< HS PHY enable */ +#define GCCFG_PHYHSEN_Msk (0x1UL << GCCFG_PHYHSEN_Pos) // 0x00800000 */ +#define GCCFG_PHYHSEN GCCFG_PHYHSEN_Msk // HS PHY enable */ /******************** Bit definition for DEACHINTMSK register ********************/ #define DEACHINTMSK_IEP1INTM_Pos (1U) -#define DEACHINTMSK_IEP1INTM_Msk (0x1UL << DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */ -#define DEACHINTMSK_IEP1INTM DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */ +#define DEACHINTMSK_IEP1INTM_Msk (0x1UL << DEACHINTMSK_IEP1INTM_Pos) // 0x00000002 */ +#define DEACHINTMSK_IEP1INTM DEACHINTMSK_IEP1INTM_Msk // IN Endpoint 1 interrupt mask bit */ #define DEACHINTMSK_OEP1INTM_Pos (17U) -#define DEACHINTMSK_OEP1INTM_Msk (0x1UL << DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */ -#define DEACHINTMSK_OEP1INTM DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */ +#define DEACHINTMSK_OEP1INTM_Msk (0x1UL << DEACHINTMSK_OEP1INTM_Pos) // 0x00020000 */ +#define DEACHINTMSK_OEP1INTM DEACHINTMSK_OEP1INTM_Msk // OUT Endpoint 1 interrupt mask bit */ /******************** Bit definition for CID register ********************/ #define CID_PRODUCT_ID_Pos (0U) -#define CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */ -#define CID_PRODUCT_ID CID_PRODUCT_ID_Msk /*!< Product ID field */ +#define CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << CID_PRODUCT_ID_Pos) // 0xFFFFFFFF */ +#define CID_PRODUCT_ID CID_PRODUCT_ID_Msk // Product ID field */ /******************** Bit definition for GLPMCFG register ********************/ #define GLPMCFG_LPMEN_Pos (0U) -#define GLPMCFG_LPMEN_Msk (0x1UL << GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ -#define GLPMCFG_LPMEN GLPMCFG_LPMEN_Msk /*!< LPM support enable */ +#define GLPMCFG_LPMEN_Msk (0x1UL << GLPMCFG_LPMEN_Pos) // 0x00000001 */ +#define GLPMCFG_LPMEN GLPMCFG_LPMEN_Msk // LPM support enable */ #define GLPMCFG_LPMACK_Pos (1U) -#define GLPMCFG_LPMACK_Msk (0x1UL << GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ -#define GLPMCFG_LPMACK GLPMCFG_LPMACK_Msk /*!< LPM Token acknowledge enable */ +#define GLPMCFG_LPMACK_Msk (0x1UL << GLPMCFG_LPMACK_Pos) // 0x00000002 */ +#define GLPMCFG_LPMACK GLPMCFG_LPMACK_Msk // LPM Token acknowledge enable */ #define GLPMCFG_BESL_Pos (2U) -#define GLPMCFG_BESL_Msk (0xFUL << GLPMCFG_BESL_Pos) /*!< 0x0000003C */ -#define GLPMCFG_BESL GLPMCFG_BESL_Msk /*!< BESL value received with last ACKed LPM Token */ +#define GLPMCFG_BESL_Msk (0xFUL << GLPMCFG_BESL_Pos) // 0x0000003C */ +#define GLPMCFG_BESL GLPMCFG_BESL_Msk // BESL value received with last ACKed LPM Token */ #define GLPMCFG_REMWAKE_Pos (6U) -#define GLPMCFG_REMWAKE_Msk (0x1UL << GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ -#define GLPMCFG_REMWAKE GLPMCFG_REMWAKE_Msk /*!< bRemoteWake value received with last ACKed LPM Token */ +#define GLPMCFG_REMWAKE_Msk (0x1UL << GLPMCFG_REMWAKE_Pos) // 0x00000040 */ +#define GLPMCFG_REMWAKE GLPMCFG_REMWAKE_Msk // bRemoteWake value received with last ACKed LPM Token */ #define GLPMCFG_L1SSEN_Pos (7U) -#define GLPMCFG_L1SSEN_Msk (0x1UL << GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ -#define GLPMCFG_L1SSEN GLPMCFG_L1SSEN_Msk /*!< L1 shallow sleep enable */ +#define GLPMCFG_L1SSEN_Msk (0x1UL << GLPMCFG_L1SSEN_Pos) // 0x00000080 */ +#define GLPMCFG_L1SSEN GLPMCFG_L1SSEN_Msk // L1 shallow sleep enable */ #define GLPMCFG_BESLTHRS_Pos (8U) -#define GLPMCFG_BESLTHRS_Msk (0xFUL << GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ -#define GLPMCFG_BESLTHRS GLPMCFG_BESLTHRS_Msk /*!< BESL threshold */ +#define GLPMCFG_BESLTHRS_Msk (0xFUL << GLPMCFG_BESLTHRS_Pos) // 0x00000F00 */ +#define GLPMCFG_BESLTHRS GLPMCFG_BESLTHRS_Msk // BESL threshold */ #define GLPMCFG_L1DSEN_Pos (12U) -#define GLPMCFG_L1DSEN_Msk (0x1UL << GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ -#define GLPMCFG_L1DSEN GLPMCFG_L1DSEN_Msk /*!< L1 deep sleep enable */ +#define GLPMCFG_L1DSEN_Msk (0x1UL << GLPMCFG_L1DSEN_Pos) // 0x00001000 */ +#define GLPMCFG_L1DSEN GLPMCFG_L1DSEN_Msk // L1 deep sleep enable */ #define GLPMCFG_LPMRSP_Pos (13U) -#define GLPMCFG_LPMRSP_Msk (0x3UL << GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ -#define GLPMCFG_LPMRSP GLPMCFG_LPMRSP_Msk /*!< LPM response */ +#define GLPMCFG_LPMRSP_Msk (0x3UL << GLPMCFG_LPMRSP_Pos) // 0x00006000 */ +#define GLPMCFG_LPMRSP GLPMCFG_LPMRSP_Msk // LPM response */ #define GLPMCFG_SLPSTS_Pos (15U) -#define GLPMCFG_SLPSTS_Msk (0x1UL << GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ -#define GLPMCFG_SLPSTS GLPMCFG_SLPSTS_Msk /*!< Port sleep status */ +#define GLPMCFG_SLPSTS_Msk (0x1UL << GLPMCFG_SLPSTS_Pos) // 0x00008000 */ +#define GLPMCFG_SLPSTS GLPMCFG_SLPSTS_Msk // Port sleep status */ #define GLPMCFG_L1RSMOK_Pos (16U) -#define GLPMCFG_L1RSMOK_Msk (0x1UL << GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */ -#define GLPMCFG_L1RSMOK GLPMCFG_L1RSMOK_Msk /*!< Sleep State Resume OK */ +#define GLPMCFG_L1RSMOK_Msk (0x1UL << GLPMCFG_L1RSMOK_Pos) // 0x00010000 */ +#define GLPMCFG_L1RSMOK GLPMCFG_L1RSMOK_Msk // Sleep State Resume OK */ #define GLPMCFG_LPMCHIDX_Pos (17U) -#define GLPMCFG_LPMCHIDX_Msk (0xFUL << GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ -#define GLPMCFG_LPMCHIDX GLPMCFG_LPMCHIDX_Msk /*!< LPM Channel Index */ +#define GLPMCFG_LPMCHIDX_Msk (0xFUL << GLPMCFG_LPMCHIDX_Pos) // 0x001E0000 */ +#define GLPMCFG_LPMCHIDX GLPMCFG_LPMCHIDX_Msk // LPM Channel Index */ #define GLPMCFG_LPMRCNT_Pos (21U) -#define GLPMCFG_LPMRCNT_Msk (0x7UL << GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ -#define GLPMCFG_LPMRCNT GLPMCFG_LPMRCNT_Msk /*!< LPM retry count */ +#define GLPMCFG_LPMRCNT_Msk (0x7UL << GLPMCFG_LPMRCNT_Pos) // 0x00E00000 */ +#define GLPMCFG_LPMRCNT GLPMCFG_LPMRCNT_Msk // LPM retry count */ #define GLPMCFG_SNDLPM_Pos (24U) -#define GLPMCFG_SNDLPM_Msk (0x1UL << GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ -#define GLPMCFG_SNDLPM GLPMCFG_SNDLPM_Msk /*!< Send LPM transaction */ +#define GLPMCFG_SNDLPM_Msk (0x1UL << GLPMCFG_SNDLPM_Pos) // 0x01000000 */ +#define GLPMCFG_SNDLPM GLPMCFG_SNDLPM_Msk // Send LPM transaction */ #define GLPMCFG_LPMRCNTSTS_Pos (25U) -#define GLPMCFG_LPMRCNTSTS_Msk (0x7UL << GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ -#define GLPMCFG_LPMRCNTSTS GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status */ +#define GLPMCFG_LPMRCNTSTS_Msk (0x7UL << GLPMCFG_LPMRCNTSTS_Pos) // 0x0E000000 */ +#define GLPMCFG_LPMRCNTSTS GLPMCFG_LPMRCNTSTS_Msk // LPM retry count status */ #define GLPMCFG_ENBESL_Pos (28U) -#define GLPMCFG_ENBESL_Msk (0x1UL << GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ -#define GLPMCFG_ENBESL GLPMCFG_ENBESL_Msk /*!< Enable best effort service latency */ +#define GLPMCFG_ENBESL_Msk (0x1UL << GLPMCFG_ENBESL_Pos) // 0x10000000 */ +#define GLPMCFG_ENBESL GLPMCFG_ENBESL_Msk // Enable best effort service latency */ /******************** Bit definition for DIEPEACHMSK1 register ********************/ #define DIEPEACHMSK1_XFRCM_Pos (0U) -#define DIEPEACHMSK1_XFRCM_Msk (0x1UL << DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */ -#define DIEPEACHMSK1_XFRCM DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */ +#define DIEPEACHMSK1_XFRCM_Msk (0x1UL << DIEPEACHMSK1_XFRCM_Pos) // 0x00000001 */ +#define DIEPEACHMSK1_XFRCM DIEPEACHMSK1_XFRCM_Msk // Transfer completed interrupt mask */ #define DIEPEACHMSK1_EPDM_Pos (1U) -#define DIEPEACHMSK1_EPDM_Msk (0x1UL << DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */ -#define DIEPEACHMSK1_EPDM DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define DIEPEACHMSK1_EPDM_Msk (0x1UL << DIEPEACHMSK1_EPDM_Pos) // 0x00000002 */ +#define DIEPEACHMSK1_EPDM DIEPEACHMSK1_EPDM_Msk // Endpoint disabled interrupt mask */ #define DIEPEACHMSK1_TOM_Pos (3U) -#define DIEPEACHMSK1_TOM_Msk (0x1UL << DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */ -#define DIEPEACHMSK1_TOM DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ +#define DIEPEACHMSK1_TOM_Msk (0x1UL << DIEPEACHMSK1_TOM_Pos) // 0x00000008 */ +#define DIEPEACHMSK1_TOM DIEPEACHMSK1_TOM_Msk // Timeout condition mask (nonisochronous endpoints) */ #define DIEPEACHMSK1_ITTXFEMSK_Pos (4U) -#define DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */ -#define DIEPEACHMSK1_ITTXFEMSK DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ +#define DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << DIEPEACHMSK1_ITTXFEMSK_Pos) // 0x00000010 */ +#define DIEPEACHMSK1_ITTXFEMSK DIEPEACHMSK1_ITTXFEMSK_Msk // IN token received when TxFIFO empty mask */ #define DIEPEACHMSK1_INEPNMM_Pos (5U) -#define DIEPEACHMSK1_INEPNMM_Msk (0x1UL << DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */ -#define DIEPEACHMSK1_INEPNMM DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ +#define DIEPEACHMSK1_INEPNMM_Msk (0x1UL << DIEPEACHMSK1_INEPNMM_Pos) // 0x00000020 */ +#define DIEPEACHMSK1_INEPNMM DIEPEACHMSK1_INEPNMM_Msk // IN token received with EP mismatch mask */ #define DIEPEACHMSK1_INEPNEM_Pos (6U) -#define DIEPEACHMSK1_INEPNEM_Msk (0x1UL << DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */ -#define DIEPEACHMSK1_INEPNEM DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ +#define DIEPEACHMSK1_INEPNEM_Msk (0x1UL << DIEPEACHMSK1_INEPNEM_Pos) // 0x00000040 */ +#define DIEPEACHMSK1_INEPNEM DIEPEACHMSK1_INEPNEM_Msk // IN endpoint NAK effective mask */ #define DIEPEACHMSK1_TXFURM_Pos (8U) -#define DIEPEACHMSK1_TXFURM_Msk (0x1UL << DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */ -#define DIEPEACHMSK1_TXFURM DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */ +#define DIEPEACHMSK1_TXFURM_Msk (0x1UL << DIEPEACHMSK1_TXFURM_Pos) // 0x00000100 */ +#define DIEPEACHMSK1_TXFURM DIEPEACHMSK1_TXFURM_Msk // FIFO underrun mask */ #define DIEPEACHMSK1_BIM_Pos (9U) -#define DIEPEACHMSK1_BIM_Msk (0x1UL << DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */ -#define DIEPEACHMSK1_BIM DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */ +#define DIEPEACHMSK1_BIM_Msk (0x1UL << DIEPEACHMSK1_BIM_Pos) // 0x00000200 */ +#define DIEPEACHMSK1_BIM DIEPEACHMSK1_BIM_Msk // BNA interrupt mask */ #define DIEPEACHMSK1_NAKM_Pos (13U) -#define DIEPEACHMSK1_NAKM_Msk (0x1UL << DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */ -#define DIEPEACHMSK1_NAKM DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */ +#define DIEPEACHMSK1_NAKM_Msk (0x1UL << DIEPEACHMSK1_NAKM_Pos) // 0x00002000 */ +#define DIEPEACHMSK1_NAKM DIEPEACHMSK1_NAKM_Msk // NAK interrupt mask */ /******************** Bit definition for HPRT register ********************/ #define HPRT_PCSTS_Pos (0U) -#define HPRT_PCSTS_Msk (0x1UL << HPRT_PCSTS_Pos) /*!< 0x00000001 */ -#define HPRT_PCSTS HPRT_PCSTS_Msk /*!< Port connect status */ +#define HPRT_PCSTS_Msk (0x1UL << HPRT_PCSTS_Pos) // 0x00000001 */ +#define HPRT_PCSTS HPRT_PCSTS_Msk // Port connect status */ #define HPRT_PCDET_Pos (1U) -#define HPRT_PCDET_Msk (0x1UL << HPRT_PCDET_Pos) /*!< 0x00000002 */ -#define HPRT_PCDET HPRT_PCDET_Msk /*!< Port connect detected */ +#define HPRT_PCDET_Msk (0x1UL << HPRT_PCDET_Pos) // 0x00000002 */ +#define HPRT_PCDET HPRT_PCDET_Msk // Port connect detected */ #define HPRT_PENA_Pos (2U) -#define HPRT_PENA_Msk (0x1UL << HPRT_PENA_Pos) /*!< 0x00000004 */ -#define HPRT_PENA HPRT_PENA_Msk /*!< Port enable */ +#define HPRT_PENA_Msk (0x1UL << HPRT_PENA_Pos) // 0x00000004 */ +#define HPRT_PENA HPRT_PENA_Msk // Port enable */ #define HPRT_PENCHNG_Pos (3U) -#define HPRT_PENCHNG_Msk (0x1UL << HPRT_PENCHNG_Pos) /*!< 0x00000008 */ -#define HPRT_PENCHNG HPRT_PENCHNG_Msk /*!< Port enable/disable change */ +#define HPRT_PENCHNG_Msk (0x1UL << HPRT_PENCHNG_Pos) // 0x00000008 */ +#define HPRT_PENCHNG HPRT_PENCHNG_Msk // Port enable/disable change */ #define HPRT_POCA_Pos (4U) -#define HPRT_POCA_Msk (0x1UL << HPRT_POCA_Pos) /*!< 0x00000010 */ -#define HPRT_POCA HPRT_POCA_Msk /*!< Port overcurrent active */ +#define HPRT_POCA_Msk (0x1UL << HPRT_POCA_Pos) // 0x00000010 */ +#define HPRT_POCA HPRT_POCA_Msk // Port overcurrent active */ #define HPRT_POCCHNG_Pos (5U) -#define HPRT_POCCHNG_Msk (0x1UL << HPRT_POCCHNG_Pos) /*!< 0x00000020 */ -#define HPRT_POCCHNG HPRT_POCCHNG_Msk /*!< Port overcurrent change */ +#define HPRT_POCCHNG_Msk (0x1UL << HPRT_POCCHNG_Pos) // 0x00000020 */ +#define HPRT_POCCHNG HPRT_POCCHNG_Msk // Port overcurrent change */ #define HPRT_PRES_Pos (6U) -#define HPRT_PRES_Msk (0x1UL << HPRT_PRES_Pos) /*!< 0x00000040 */ -#define HPRT_PRES HPRT_PRES_Msk /*!< Port resume */ +#define HPRT_PRES_Msk (0x1UL << HPRT_PRES_Pos) // 0x00000040 */ +#define HPRT_PRES HPRT_PRES_Msk // Port resume */ #define HPRT_PSUSP_Pos (7U) -#define HPRT_PSUSP_Msk (0x1UL << HPRT_PSUSP_Pos) /*!< 0x00000080 */ -#define HPRT_PSUSP HPRT_PSUSP_Msk /*!< Port suspend */ +#define HPRT_PSUSP_Msk (0x1UL << HPRT_PSUSP_Pos) // 0x00000080 */ +#define HPRT_PSUSP HPRT_PSUSP_Msk // Port suspend */ #define HPRT_PRST_Pos (8U) -#define HPRT_PRST_Msk (0x1UL << HPRT_PRST_Pos) /*!< 0x00000100 */ -#define HPRT_PRST HPRT_PRST_Msk /*!< Port reset */ +#define HPRT_PRST_Msk (0x1UL << HPRT_PRST_Pos) // 0x00000100 */ +#define HPRT_PRST HPRT_PRST_Msk // Port reset */ #define HPRT_PLSTS_Pos (10U) -#define HPRT_PLSTS_Msk (0x3UL << HPRT_PLSTS_Pos) /*!< 0x00000C00 */ -#define HPRT_PLSTS HPRT_PLSTS_Msk /*!< Port line status */ -#define HPRT_PLSTS_0 (0x1UL << HPRT_PLSTS_Pos) /*!< 0x00000400 */ -#define HPRT_PLSTS_1 (0x2UL << HPRT_PLSTS_Pos) /*!< 0x00000800 */ +#define HPRT_PLSTS_Msk (0x3UL << HPRT_PLSTS_Pos) // 0x00000C00 */ +#define HPRT_PLSTS HPRT_PLSTS_Msk // Port line status */ +#define HPRT_PLSTS_0 (0x1UL << HPRT_PLSTS_Pos) // 0x00000400 */ +#define HPRT_PLSTS_1 (0x2UL << HPRT_PLSTS_Pos) // 0x00000800 */ #define HPRT_PPWR_Pos (12U) -#define HPRT_PPWR_Msk (0x1UL << HPRT_PPWR_Pos) /*!< 0x00001000 */ -#define HPRT_PPWR HPRT_PPWR_Msk /*!< Port power */ +#define HPRT_PPWR_Msk (0x1UL << HPRT_PPWR_Pos) // 0x00001000 */ +#define HPRT_PPWR HPRT_PPWR_Msk // Port power */ #define HPRT_PTCTL_Pos (13U) -#define HPRT_PTCTL_Msk (0xFUL << HPRT_PTCTL_Pos) /*!< 0x0001E000 */ -#define HPRT_PTCTL HPRT_PTCTL_Msk /*!< Port test control */ -#define HPRT_PTCTL_0 (0x1UL << HPRT_PTCTL_Pos) /*!< 0x00002000 */ -#define HPRT_PTCTL_1 (0x2UL << HPRT_PTCTL_Pos) /*!< 0x00004000 */ -#define HPRT_PTCTL_2 (0x4UL << HPRT_PTCTL_Pos) /*!< 0x00008000 */ -#define HPRT_PTCTL_3 (0x8UL << HPRT_PTCTL_Pos) /*!< 0x00010000 */ +#define HPRT_PTCTL_Msk (0xFUL << HPRT_PTCTL_Pos) // 0x0001E000 */ +#define HPRT_PTCTL HPRT_PTCTL_Msk // Port test control */ +#define HPRT_PTCTL_0 (0x1UL << HPRT_PTCTL_Pos) // 0x00002000 */ +#define HPRT_PTCTL_1 (0x2UL << HPRT_PTCTL_Pos) // 0x00004000 */ +#define HPRT_PTCTL_2 (0x4UL << HPRT_PTCTL_Pos) // 0x00008000 */ +#define HPRT_PTCTL_3 (0x8UL << HPRT_PTCTL_Pos) // 0x00010000 */ #define HPRT_PSPD_Pos (17U) -#define HPRT_PSPD_Msk (0x3UL << HPRT_PSPD_Pos) /*!< 0x00060000 */ -#define HPRT_PSPD HPRT_PSPD_Msk /*!< Port speed */ -#define HPRT_PSPD_0 (0x1UL << HPRT_PSPD_Pos) /*!< 0x00020000 */ -#define HPRT_PSPD_1 (0x2UL << HPRT_PSPD_Pos) /*!< 0x00040000 */ +#define HPRT_PSPD_Msk (0x3UL << HPRT_PSPD_Pos) // 0x00060000 */ +#define HPRT_PSPD HPRT_PSPD_Msk // Port speed */ +#define HPRT_PSPD_0 (0x1UL << HPRT_PSPD_Pos) // 0x00020000 */ +#define HPRT_PSPD_1 (0x2UL << HPRT_PSPD_Pos) // 0x00040000 */ /******************** Bit definition for DOEPEACHMSK1 register ********************/ #define DOEPEACHMSK1_XFRCM_Pos (0U) -#define DOEPEACHMSK1_XFRCM_Msk (0x1UL << DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */ -#define DOEPEACHMSK1_XFRCM DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */ +#define DOEPEACHMSK1_XFRCM_Msk (0x1UL << DOEPEACHMSK1_XFRCM_Pos) // 0x00000001 */ +#define DOEPEACHMSK1_XFRCM DOEPEACHMSK1_XFRCM_Msk // Transfer completed interrupt mask */ #define DOEPEACHMSK1_EPDM_Pos (1U) -#define DOEPEACHMSK1_EPDM_Msk (0x1UL << DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */ -#define DOEPEACHMSK1_EPDM DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define DOEPEACHMSK1_EPDM_Msk (0x1UL << DOEPEACHMSK1_EPDM_Pos) // 0x00000002 */ +#define DOEPEACHMSK1_EPDM DOEPEACHMSK1_EPDM_Msk // Endpoint disabled interrupt mask */ #define DOEPEACHMSK1_TOM_Pos (3U) -#define DOEPEACHMSK1_TOM_Msk (0x1UL << DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */ -#define DOEPEACHMSK1_TOM DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */ +#define DOEPEACHMSK1_TOM_Msk (0x1UL << DOEPEACHMSK1_TOM_Pos) // 0x00000008 */ +#define DOEPEACHMSK1_TOM DOEPEACHMSK1_TOM_Msk // Timeout condition mask */ #define DOEPEACHMSK1_ITTXFEMSK_Pos (4U) -#define DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */ -#define DOEPEACHMSK1_ITTXFEMSK DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ +#define DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << DOEPEACHMSK1_ITTXFEMSK_Pos) // 0x00000010 */ +#define DOEPEACHMSK1_ITTXFEMSK DOEPEACHMSK1_ITTXFEMSK_Msk // IN token received when TxFIFO empty mask */ #define DOEPEACHMSK1_INEPNMM_Pos (5U) -#define DOEPEACHMSK1_INEPNMM_Msk (0x1UL << DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */ -#define DOEPEACHMSK1_INEPNMM DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ +#define DOEPEACHMSK1_INEPNMM_Msk (0x1UL << DOEPEACHMSK1_INEPNMM_Pos) // 0x00000020 */ +#define DOEPEACHMSK1_INEPNMM DOEPEACHMSK1_INEPNMM_Msk // IN token received with EP mismatch mask */ #define DOEPEACHMSK1_INEPNEM_Pos (6U) -#define DOEPEACHMSK1_INEPNEM_Msk (0x1UL << DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */ -#define DOEPEACHMSK1_INEPNEM DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ +#define DOEPEACHMSK1_INEPNEM_Msk (0x1UL << DOEPEACHMSK1_INEPNEM_Pos) // 0x00000040 */ +#define DOEPEACHMSK1_INEPNEM DOEPEACHMSK1_INEPNEM_Msk // IN endpoint NAK effective mask */ #define DOEPEACHMSK1_TXFURM_Pos (8U) -#define DOEPEACHMSK1_TXFURM_Msk (0x1UL << DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */ -#define DOEPEACHMSK1_TXFURM DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */ +#define DOEPEACHMSK1_TXFURM_Msk (0x1UL << DOEPEACHMSK1_TXFURM_Pos) // 0x00000100 */ +#define DOEPEACHMSK1_TXFURM DOEPEACHMSK1_TXFURM_Msk // OUT packet error mask */ #define DOEPEACHMSK1_BIM_Pos (9U) -#define DOEPEACHMSK1_BIM_Msk (0x1UL << DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */ -#define DOEPEACHMSK1_BIM DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */ +#define DOEPEACHMSK1_BIM_Msk (0x1UL << DOEPEACHMSK1_BIM_Pos) // 0x00000200 */ +#define DOEPEACHMSK1_BIM DOEPEACHMSK1_BIM_Msk // BNA interrupt mask */ #define DOEPEACHMSK1_BERRM_Pos (12U) -#define DOEPEACHMSK1_BERRM_Msk (0x1UL << DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */ -#define DOEPEACHMSK1_BERRM DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */ +#define DOEPEACHMSK1_BERRM_Msk (0x1UL << DOEPEACHMSK1_BERRM_Pos) // 0x00001000 */ +#define DOEPEACHMSK1_BERRM DOEPEACHMSK1_BERRM_Msk // Bubble error interrupt mask */ #define DOEPEACHMSK1_NAKM_Pos (13U) -#define DOEPEACHMSK1_NAKM_Msk (0x1UL << DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */ -#define DOEPEACHMSK1_NAKM DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */ +#define DOEPEACHMSK1_NAKM_Msk (0x1UL << DOEPEACHMSK1_NAKM_Pos) // 0x00002000 */ +#define DOEPEACHMSK1_NAKM DOEPEACHMSK1_NAKM_Msk // NAK interrupt mask */ #define DOEPEACHMSK1_NYETM_Pos (14U) -#define DOEPEACHMSK1_NYETM_Msk (0x1UL << DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */ -#define DOEPEACHMSK1_NYETM DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */ +#define DOEPEACHMSK1_NYETM_Msk (0x1UL << DOEPEACHMSK1_NYETM_Pos) // 0x00004000 */ +#define DOEPEACHMSK1_NYETM DOEPEACHMSK1_NYETM_Msk // NYET interrupt mask */ /******************** Bit definition for HPTXFSIZ register ********************/ #define HPTXFSIZ_PTXSA_Pos (0U) -#define HPTXFSIZ_PTXSA_Msk (0xFFFFUL << HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ -#define HPTXFSIZ_PTXSA HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ +#define HPTXFSIZ_PTXSA_Msk (0xFFFFUL << HPTXFSIZ_PTXSA_Pos) // 0x0000FFFF */ +#define HPTXFSIZ_PTXSA HPTXFSIZ_PTXSA_Msk // Host periodic TxFIFO start address */ #define HPTXFSIZ_PTXFD_Pos (16U) -#define HPTXFSIZ_PTXFD_Msk (0xFFFFUL << HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ -#define HPTXFSIZ_PTXFD HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ +#define HPTXFSIZ_PTXFD_Msk (0xFFFFUL << HPTXFSIZ_PTXFD_Pos) // 0xFFFF0000 */ +#define HPTXFSIZ_PTXFD HPTXFSIZ_PTXFD_Msk // Host periodic TxFIFO depth */ /******************** Bit definition for DIEPCTL register ********************/ #define DIEPCTL_MPSIZ_Pos (0U) -#define DIEPCTL_MPSIZ_Msk (0x7FFUL << DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */ -#define DIEPCTL_MPSIZ DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */ +#define DIEPCTL_MPSIZ_Msk (0x7FFUL << DIEPCTL_MPSIZ_Pos) // 0x000007FF */ +#define DIEPCTL_MPSIZ DIEPCTL_MPSIZ_Msk // Maximum packet size */ #define DIEPCTL_USBAEP_Pos (15U) -#define DIEPCTL_USBAEP_Msk (0x1UL << DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */ -#define DIEPCTL_USBAEP DIEPCTL_USBAEP_Msk /*!< USB active endpoint */ +#define DIEPCTL_USBAEP_Msk (0x1UL << DIEPCTL_USBAEP_Pos) // 0x00008000 */ +#define DIEPCTL_USBAEP DIEPCTL_USBAEP_Msk // USB active endpoint */ #define DIEPCTL_EONUM_DPID_Pos (16U) -#define DIEPCTL_EONUM_DPID_Msk (0x1UL << DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */ -#define DIEPCTL_EONUM_DPID DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */ +#define DIEPCTL_EONUM_DPID_Msk (0x1UL << DIEPCTL_EONUM_DPID_Pos) // 0x00010000 */ +#define DIEPCTL_EONUM_DPID DIEPCTL_EONUM_DPID_Msk // Even/odd frame */ #define DIEPCTL_NAKSTS_Pos (17U) -#define DIEPCTL_NAKSTS_Msk (0x1UL << DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ -#define DIEPCTL_NAKSTS DIEPCTL_NAKSTS_Msk /*!< NAK status */ +#define DIEPCTL_NAKSTS_Msk (0x1UL << DIEPCTL_NAKSTS_Pos) // 0x00020000 */ +#define DIEPCTL_NAKSTS DIEPCTL_NAKSTS_Msk // NAK status */ #define DIEPCTL_EPTYP_Pos (18U) -#define DIEPCTL_EPTYP_Msk (0x3UL << DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ -#define DIEPCTL_EPTYP DIEPCTL_EPTYP_Msk /*!< Endpoint type */ -#define DIEPCTL_EPTYP_0 (0x1UL << DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */ -#define DIEPCTL_EPTYP_1 (0x2UL << DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */ +#define DIEPCTL_EPTYP_Msk (0x3UL << DIEPCTL_EPTYP_Pos) // 0x000C0000 */ +#define DIEPCTL_EPTYP DIEPCTL_EPTYP_Msk // Endpoint type */ +#define DIEPCTL_EPTYP_0 (0x1UL << DIEPCTL_EPTYP_Pos) // 0x00040000 */ +#define DIEPCTL_EPTYP_1 (0x2UL << DIEPCTL_EPTYP_Pos) // 0x00080000 */ #define DIEPCTL_STALL_Pos (21U) -#define DIEPCTL_STALL_Msk (0x1UL << DIEPCTL_STALL_Pos) /*!< 0x00200000 */ -#define DIEPCTL_STALL DIEPCTL_STALL_Msk /*!< STALL handshake */ +#define DIEPCTL_STALL_Msk (0x1UL << DIEPCTL_STALL_Pos) // 0x00200000 */ +#define DIEPCTL_STALL DIEPCTL_STALL_Msk // STALL handshake */ #define DIEPCTL_TXFNUM_Pos (22U) -#define DIEPCTL_TXFNUM_Msk (0xFUL << DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */ -#define DIEPCTL_TXFNUM DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */ -#define DIEPCTL_TXFNUM_0 (0x1UL << DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */ -#define DIEPCTL_TXFNUM_1 (0x2UL << DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */ -#define DIEPCTL_TXFNUM_2 (0x4UL << DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */ -#define DIEPCTL_TXFNUM_3 (0x8UL << DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */ +#define DIEPCTL_TXFNUM_Msk (0xFUL << DIEPCTL_TXFNUM_Pos) // 0x03C00000 */ +#define DIEPCTL_TXFNUM DIEPCTL_TXFNUM_Msk // TxFIFO number */ +#define DIEPCTL_TXFNUM_0 (0x1UL << DIEPCTL_TXFNUM_Pos) // 0x00400000 */ +#define DIEPCTL_TXFNUM_1 (0x2UL << DIEPCTL_TXFNUM_Pos) // 0x00800000 */ +#define DIEPCTL_TXFNUM_2 (0x4UL << DIEPCTL_TXFNUM_Pos) // 0x01000000 */ +#define DIEPCTL_TXFNUM_3 (0x8UL << DIEPCTL_TXFNUM_Pos) // 0x02000000 */ #define DIEPCTL_CNAK_Pos (26U) -#define DIEPCTL_CNAK_Msk (0x1UL << DIEPCTL_CNAK_Pos) /*!< 0x04000000 */ -#define DIEPCTL_CNAK DIEPCTL_CNAK_Msk /*!< Clear NAK */ +#define DIEPCTL_CNAK_Msk (0x1UL << DIEPCTL_CNAK_Pos) // 0x04000000 */ +#define DIEPCTL_CNAK DIEPCTL_CNAK_Msk // Clear NAK */ #define DIEPCTL_SNAK_Pos (27U) -#define DIEPCTL_SNAK_Msk (0x1UL << DIEPCTL_SNAK_Pos) /*!< 0x08000000 */ -#define DIEPCTL_SNAK DIEPCTL_SNAK_Msk /*!< Set NAK */ +#define DIEPCTL_SNAK_Msk (0x1UL << DIEPCTL_SNAK_Pos) // 0x08000000 */ +#define DIEPCTL_SNAK DIEPCTL_SNAK_Msk // Set NAK */ #define DIEPCTL_SD0PID_SEVNFRM_Pos (28U) -#define DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define DIEPCTL_SD0PID_SEVNFRM DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ +#define DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << DIEPCTL_SD0PID_SEVNFRM_Pos) // 0x10000000 */ +#define DIEPCTL_SD0PID_SEVNFRM DIEPCTL_SD0PID_SEVNFRM_Msk // Set DATA0 PID */ #define DIEPCTL_SODDFRM_Pos (29U) -#define DIEPCTL_SODDFRM_Msk (0x1UL << DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define DIEPCTL_SODDFRM DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ +#define DIEPCTL_SODDFRM_Msk (0x1UL << DIEPCTL_SODDFRM_Pos) // 0x20000000 */ +#define DIEPCTL_SODDFRM DIEPCTL_SODDFRM_Msk // Set odd frame */ #define DIEPCTL_EPDIS_Pos (30U) -#define DIEPCTL_EPDIS_Msk (0x1UL << DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ -#define DIEPCTL_EPDIS DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ +#define DIEPCTL_EPDIS_Msk (0x1UL << DIEPCTL_EPDIS_Pos) // 0x40000000 */ +#define DIEPCTL_EPDIS DIEPCTL_EPDIS_Msk // Endpoint disable */ #define DIEPCTL_EPENA_Pos (31U) -#define DIEPCTL_EPENA_Msk (0x1UL << DIEPCTL_EPENA_Pos) /*!< 0x80000000 */ -#define DIEPCTL_EPENA DIEPCTL_EPENA_Msk /*!< Endpoint enable */ +#define DIEPCTL_EPENA_Msk (0x1UL << DIEPCTL_EPENA_Pos) // 0x80000000 */ +#define DIEPCTL_EPENA DIEPCTL_EPENA_Msk // Endpoint enable */ /******************** Bit definition for HCCHAR register ********************/ #define HCCHAR_MPSIZ_Pos (0U) -#define HCCHAR_MPSIZ_Msk (0x7FFUL << HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ -#define HCCHAR_MPSIZ HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ +#define HCCHAR_MPSIZ_Msk (0x7FFUL << HCCHAR_MPSIZ_Pos) // 0x000007FF */ +#define HCCHAR_MPSIZ HCCHAR_MPSIZ_Msk // Maximum packet size */ #define HCCHAR_EPNUM_Pos (11U) -#define HCCHAR_EPNUM_Msk (0xFUL << HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ -#define HCCHAR_EPNUM HCCHAR_EPNUM_Msk /*!< Endpoint number */ -#define HCCHAR_EPNUM_0 (0x1UL << HCCHAR_EPNUM_Pos) /*!< 0x00000800 */ -#define HCCHAR_EPNUM_1 (0x2UL << HCCHAR_EPNUM_Pos) /*!< 0x00001000 */ -#define HCCHAR_EPNUM_2 (0x4UL << HCCHAR_EPNUM_Pos) /*!< 0x00002000 */ -#define HCCHAR_EPNUM_3 (0x8UL << HCCHAR_EPNUM_Pos) /*!< 0x00004000 */ +#define HCCHAR_EPNUM_Msk (0xFUL << HCCHAR_EPNUM_Pos) // 0x00007800 */ +#define HCCHAR_EPNUM HCCHAR_EPNUM_Msk // Endpoint number */ +#define HCCHAR_EPNUM_0 (0x1UL << HCCHAR_EPNUM_Pos) // 0x00000800 */ +#define HCCHAR_EPNUM_1 (0x2UL << HCCHAR_EPNUM_Pos) // 0x00001000 */ +#define HCCHAR_EPNUM_2 (0x4UL << HCCHAR_EPNUM_Pos) // 0x00002000 */ +#define HCCHAR_EPNUM_3 (0x8UL << HCCHAR_EPNUM_Pos) // 0x00004000 */ #define HCCHAR_EPDIR_Pos (15U) -#define HCCHAR_EPDIR_Msk (0x1UL << HCCHAR_EPDIR_Pos) /*!< 0x00008000 */ -#define HCCHAR_EPDIR HCCHAR_EPDIR_Msk /*!< Endpoint direction */ +#define HCCHAR_EPDIR_Msk (0x1UL << HCCHAR_EPDIR_Pos) // 0x00008000 */ +#define HCCHAR_EPDIR HCCHAR_EPDIR_Msk // Endpoint direction */ #define HCCHAR_LSDEV_Pos (17U) -#define HCCHAR_LSDEV_Msk (0x1UL << HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ -#define HCCHAR_LSDEV HCCHAR_LSDEV_Msk /*!< Low-speed device */ +#define HCCHAR_LSDEV_Msk (0x1UL << HCCHAR_LSDEV_Pos) // 0x00020000 */ +#define HCCHAR_LSDEV HCCHAR_LSDEV_Msk // Low-speed device */ #define HCCHAR_EPTYP_Pos (18U) -#define HCCHAR_EPTYP_Msk (0x3UL << HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ -#define HCCHAR_EPTYP HCCHAR_EPTYP_Msk /*!< Endpoint type */ -#define HCCHAR_EPTYP_0 (0x1UL << HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ -#define HCCHAR_EPTYP_1 (0x2UL << HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ +#define HCCHAR_EPTYP_Msk (0x3UL << HCCHAR_EPTYP_Pos) // 0x000C0000 */ +#define HCCHAR_EPTYP HCCHAR_EPTYP_Msk // Endpoint type */ +#define HCCHAR_EPTYP_0 (0x1UL << HCCHAR_EPTYP_Pos) // 0x00040000 */ +#define HCCHAR_EPTYP_1 (0x2UL << HCCHAR_EPTYP_Pos) // 0x00080000 */ #define HCCHAR_MC_Pos (20U) -#define HCCHAR_MC_Msk (0x3UL << HCCHAR_MC_Pos) /*!< 0x00300000 */ -#define HCCHAR_MC HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ -#define HCCHAR_MC_0 (0x1UL << HCCHAR_MC_Pos) /*!< 0x00100000 */ -#define HCCHAR_MC_1 (0x2UL << HCCHAR_MC_Pos) /*!< 0x00200000 */ +#define HCCHAR_MC_Msk (0x3UL << HCCHAR_MC_Pos) // 0x00300000 */ +#define HCCHAR_MC HCCHAR_MC_Msk // Multi Count (MC) / Error Count (EC) */ +#define HCCHAR_MC_0 (0x1UL << HCCHAR_MC_Pos) // 0x00100000 */ +#define HCCHAR_MC_1 (0x2UL << HCCHAR_MC_Pos) // 0x00200000 */ #define HCCHAR_DAD_Pos (22U) -#define HCCHAR_DAD_Msk (0x7FUL << HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ -#define HCCHAR_DAD HCCHAR_DAD_Msk /*!< Device address */ -#define HCCHAR_DAD_0 (0x01UL << HCCHAR_DAD_Pos) /*!< 0x00400000 */ -#define HCCHAR_DAD_1 (0x02UL << HCCHAR_DAD_Pos) /*!< 0x00800000 */ -#define HCCHAR_DAD_2 (0x04UL << HCCHAR_DAD_Pos) /*!< 0x01000000 */ -#define HCCHAR_DAD_3 (0x08UL << HCCHAR_DAD_Pos) /*!< 0x02000000 */ -#define HCCHAR_DAD_4 (0x10UL << HCCHAR_DAD_Pos) /*!< 0x04000000 */ -#define HCCHAR_DAD_5 (0x20UL << HCCHAR_DAD_Pos) /*!< 0x08000000 */ -#define HCCHAR_DAD_6 (0x40UL << HCCHAR_DAD_Pos) /*!< 0x10000000 */ +#define HCCHAR_DAD_Msk (0x7FUL << HCCHAR_DAD_Pos) // 0x1FC00000 */ +#define HCCHAR_DAD HCCHAR_DAD_Msk // Device address */ +#define HCCHAR_DAD_0 (0x01UL << HCCHAR_DAD_Pos) // 0x00400000 */ +#define HCCHAR_DAD_1 (0x02UL << HCCHAR_DAD_Pos) // 0x00800000 */ +#define HCCHAR_DAD_2 (0x04UL << HCCHAR_DAD_Pos) // 0x01000000 */ +#define HCCHAR_DAD_3 (0x08UL << HCCHAR_DAD_Pos) // 0x02000000 */ +#define HCCHAR_DAD_4 (0x10UL << HCCHAR_DAD_Pos) // 0x04000000 */ +#define HCCHAR_DAD_5 (0x20UL << HCCHAR_DAD_Pos) // 0x08000000 */ +#define HCCHAR_DAD_6 (0x40UL << HCCHAR_DAD_Pos) // 0x10000000 */ #define HCCHAR_ODDFRM_Pos (29U) -#define HCCHAR_ODDFRM_Msk (0x1UL << HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */ -#define HCCHAR_ODDFRM HCCHAR_ODDFRM_Msk /*!< Odd frame */ +#define HCCHAR_ODDFRM_Msk (0x1UL << HCCHAR_ODDFRM_Pos) // 0x20000000 */ +#define HCCHAR_ODDFRM HCCHAR_ODDFRM_Msk // Odd frame */ #define HCCHAR_CHDIS_Pos (30U) -#define HCCHAR_CHDIS_Msk (0x1UL << HCCHAR_CHDIS_Pos) /*!< 0x40000000 */ -#define HCCHAR_CHDIS HCCHAR_CHDIS_Msk /*!< Channel disable */ +#define HCCHAR_CHDIS_Msk (0x1UL << HCCHAR_CHDIS_Pos) // 0x40000000 */ +#define HCCHAR_CHDIS HCCHAR_CHDIS_Msk // Channel disable */ #define HCCHAR_CHENA_Pos (31U) -#define HCCHAR_CHENA_Msk (0x1UL << HCCHAR_CHENA_Pos) /*!< 0x80000000 */ -#define HCCHAR_CHENA HCCHAR_CHENA_Msk /*!< Channel enable */ +#define HCCHAR_CHENA_Msk (0x1UL << HCCHAR_CHENA_Pos) // 0x80000000 */ +#define HCCHAR_CHENA HCCHAR_CHENA_Msk // Channel enable */ /******************** Bit definition for HCSPLT register ********************/ #define HCSPLT_PRTADDR_Pos (0U) -#define HCSPLT_PRTADDR_Msk (0x7FUL << HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */ -#define HCSPLT_PRTADDR HCSPLT_PRTADDR_Msk /*!< Port address */ -#define HCSPLT_PRTADDR_0 (0x01UL << HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */ -#define HCSPLT_PRTADDR_1 (0x02UL << HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */ -#define HCSPLT_PRTADDR_2 (0x04UL << HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */ -#define HCSPLT_PRTADDR_3 (0x08UL << HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */ -#define HCSPLT_PRTADDR_4 (0x10UL << HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */ -#define HCSPLT_PRTADDR_5 (0x20UL << HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */ -#define HCSPLT_PRTADDR_6 (0x40UL << HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */ +#define HCSPLT_PRTADDR_Msk (0x7FUL << HCSPLT_PRTADDR_Pos) // 0x0000007F */ +#define HCSPLT_PRTADDR HCSPLT_PRTADDR_Msk // Port address */ +#define HCSPLT_PRTADDR_0 (0x01UL << HCSPLT_PRTADDR_Pos) // 0x00000001 */ +#define HCSPLT_PRTADDR_1 (0x02UL << HCSPLT_PRTADDR_Pos) // 0x00000002 */ +#define HCSPLT_PRTADDR_2 (0x04UL << HCSPLT_PRTADDR_Pos) // 0x00000004 */ +#define HCSPLT_PRTADDR_3 (0x08UL << HCSPLT_PRTADDR_Pos) // 0x00000008 */ +#define HCSPLT_PRTADDR_4 (0x10UL << HCSPLT_PRTADDR_Pos) // 0x00000010 */ +#define HCSPLT_PRTADDR_5 (0x20UL << HCSPLT_PRTADDR_Pos) // 0x00000020 */ +#define HCSPLT_PRTADDR_6 (0x40UL << HCSPLT_PRTADDR_Pos) // 0x00000040 */ #define HCSPLT_HUBADDR_Pos (7U) -#define HCSPLT_HUBADDR_Msk (0x7FUL << HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */ -#define HCSPLT_HUBADDR HCSPLT_HUBADDR_Msk /*!< Hub address */ -#define HCSPLT_HUBADDR_0 (0x01UL << HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */ -#define HCSPLT_HUBADDR_1 (0x02UL << HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */ -#define HCSPLT_HUBADDR_2 (0x04UL << HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */ -#define HCSPLT_HUBADDR_3 (0x08UL << HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */ -#define HCSPLT_HUBADDR_4 (0x10UL << HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */ -#define HCSPLT_HUBADDR_5 (0x20UL << HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */ -#define HCSPLT_HUBADDR_6 (0x40UL << HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */ +#define HCSPLT_HUBADDR_Msk (0x7FUL << HCSPLT_HUBADDR_Pos) // 0x00003F80 */ +#define HCSPLT_HUBADDR HCSPLT_HUBADDR_Msk // Hub address */ +#define HCSPLT_HUBADDR_0 (0x01UL << HCSPLT_HUBADDR_Pos) // 0x00000080 */ +#define HCSPLT_HUBADDR_1 (0x02UL << HCSPLT_HUBADDR_Pos) // 0x00000100 */ +#define HCSPLT_HUBADDR_2 (0x04UL << HCSPLT_HUBADDR_Pos) // 0x00000200 */ +#define HCSPLT_HUBADDR_3 (0x08UL << HCSPLT_HUBADDR_Pos) // 0x00000400 */ +#define HCSPLT_HUBADDR_4 (0x10UL << HCSPLT_HUBADDR_Pos) // 0x00000800 */ +#define HCSPLT_HUBADDR_5 (0x20UL << HCSPLT_HUBADDR_Pos) // 0x00001000 */ +#define HCSPLT_HUBADDR_6 (0x40UL << HCSPLT_HUBADDR_Pos) // 0x00002000 */ #define HCSPLT_XACTPOS_Pos (14U) -#define HCSPLT_XACTPOS_Msk (0x3UL << HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */ -#define HCSPLT_XACTPOS HCSPLT_XACTPOS_Msk /*!< XACTPOS */ -#define HCSPLT_XACTPOS_0 (0x1UL << HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */ -#define HCSPLT_XACTPOS_1 (0x2UL << HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */ +#define HCSPLT_XACTPOS_Msk (0x3UL << HCSPLT_XACTPOS_Pos) // 0x0000C000 */ +#define HCSPLT_XACTPOS HCSPLT_XACTPOS_Msk // XACTPOS */ +#define HCSPLT_XACTPOS_0 (0x1UL << HCSPLT_XACTPOS_Pos) // 0x00004000 */ +#define HCSPLT_XACTPOS_1 (0x2UL << HCSPLT_XACTPOS_Pos) // 0x00008000 */ #define HCSPLT_COMPLSPLT_Pos (16U) -#define HCSPLT_COMPLSPLT_Msk (0x1UL << HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */ -#define HCSPLT_COMPLSPLT HCSPLT_COMPLSPLT_Msk /*!< Do complete split */ +#define HCSPLT_COMPLSPLT_Msk (0x1UL << HCSPLT_COMPLSPLT_Pos) // 0x00010000 */ +#define HCSPLT_COMPLSPLT HCSPLT_COMPLSPLT_Msk // Do complete split */ #define HCSPLT_SPLITEN_Pos (31U) -#define HCSPLT_SPLITEN_Msk (0x1UL << HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */ -#define HCSPLT_SPLITEN HCSPLT_SPLITEN_Msk /*!< Split enable */ +#define HCSPLT_SPLITEN_Msk (0x1UL << HCSPLT_SPLITEN_Pos) // 0x80000000 */ +#define HCSPLT_SPLITEN HCSPLT_SPLITEN_Msk // Split enable */ /******************** Bit definition for HCINT register ********************/ #define HCINT_XFRC_Pos (0U) -#define HCINT_XFRC_Msk (0x1UL << HCINT_XFRC_Pos) /*!< 0x00000001 */ -#define HCINT_XFRC HCINT_XFRC_Msk /*!< Transfer completed */ +#define HCINT_XFRC_Msk (0x1UL << HCINT_XFRC_Pos) // 0x00000001 */ +#define HCINT_XFRC HCINT_XFRC_Msk // Transfer completed */ #define HCINT_CHH_Pos (1U) -#define HCINT_CHH_Msk (0x1UL << HCINT_CHH_Pos) /*!< 0x00000002 */ -#define HCINT_CHH HCINT_CHH_Msk /*!< Channel halted */ +#define HCINT_CHH_Msk (0x1UL << HCINT_CHH_Pos) // 0x00000002 */ +#define HCINT_CHH HCINT_CHH_Msk // Channel halted */ #define HCINT_AHBERR_Pos (2U) -#define HCINT_AHBERR_Msk (0x1UL << HCINT_AHBERR_Pos) /*!< 0x00000004 */ -#define HCINT_AHBERR HCINT_AHBERR_Msk /*!< AHB error */ +#define HCINT_AHBERR_Msk (0x1UL << HCINT_AHBERR_Pos) // 0x00000004 */ +#define HCINT_AHBERR HCINT_AHBERR_Msk // AHB error */ #define HCINT_STALL_Pos (3U) -#define HCINT_STALL_Msk (0x1UL << HCINT_STALL_Pos) /*!< 0x00000008 */ -#define HCINT_STALL HCINT_STALL_Msk /*!< STALL response received interrupt */ +#define HCINT_STALL_Msk (0x1UL << HCINT_STALL_Pos) // 0x00000008 */ +#define HCINT_STALL HCINT_STALL_Msk // STALL response received interrupt */ #define HCINT_NAK_Pos (4U) -#define HCINT_NAK_Msk (0x1UL << HCINT_NAK_Pos) /*!< 0x00000010 */ -#define HCINT_NAK HCINT_NAK_Msk /*!< NAK response received interrupt */ +#define HCINT_NAK_Msk (0x1UL << HCINT_NAK_Pos) // 0x00000010 */ +#define HCINT_NAK HCINT_NAK_Msk // NAK response received interrupt */ #define HCINT_ACK_Pos (5U) -#define HCINT_ACK_Msk (0x1UL << HCINT_ACK_Pos) /*!< 0x00000020 */ -#define HCINT_ACK HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */ +#define HCINT_ACK_Msk (0x1UL << HCINT_ACK_Pos) // 0x00000020 */ +#define HCINT_ACK HCINT_ACK_Msk // ACK response received/transmitted interrupt */ #define HCINT_NYET_Pos (6U) -#define HCINT_NYET_Msk (0x1UL << HCINT_NYET_Pos) /*!< 0x00000040 */ -#define HCINT_NYET HCINT_NYET_Msk /*!< Response received interrupt */ +#define HCINT_NYET_Msk (0x1UL << HCINT_NYET_Pos) // 0x00000040 */ +#define HCINT_NYET HCINT_NYET_Msk // Response received interrupt */ #define HCINT_TXERR_Pos (7U) -#define HCINT_TXERR_Msk (0x1UL << HCINT_TXERR_Pos) /*!< 0x00000080 */ -#define HCINT_TXERR HCINT_TXERR_Msk /*!< Transaction error */ +#define HCINT_TXERR_Msk (0x1UL << HCINT_TXERR_Pos) // 0x00000080 */ +#define HCINT_TXERR HCINT_TXERR_Msk // Transaction error */ #define HCINT_BBERR_Pos (8U) -#define HCINT_BBERR_Msk (0x1UL << HCINT_BBERR_Pos) /*!< 0x00000100 */ -#define HCINT_BBERR HCINT_BBERR_Msk /*!< Babble error */ +#define HCINT_BBERR_Msk (0x1UL << HCINT_BBERR_Pos) // 0x00000100 */ +#define HCINT_BBERR HCINT_BBERR_Msk // Babble error */ #define HCINT_FRMOR_Pos (9U) -#define HCINT_FRMOR_Msk (0x1UL << HCINT_FRMOR_Pos) /*!< 0x00000200 */ -#define HCINT_FRMOR HCINT_FRMOR_Msk /*!< Frame overrun */ +#define HCINT_FRMOR_Msk (0x1UL << HCINT_FRMOR_Pos) // 0x00000200 */ +#define HCINT_FRMOR HCINT_FRMOR_Msk // Frame overrun */ #define HCINT_DTERR_Pos (10U) -#define HCINT_DTERR_Msk (0x1UL << HCINT_DTERR_Pos) /*!< 0x00000400 */ -#define HCINT_DTERR HCINT_DTERR_Msk /*!< Data toggle error */ +#define HCINT_DTERR_Msk (0x1UL << HCINT_DTERR_Pos) // 0x00000400 */ +#define HCINT_DTERR HCINT_DTERR_Msk // Data toggle error */ /******************** Bit definition for DIEPINT register ********************/ #define DIEPINT_XFRC_Pos (0U) -#define DIEPINT_XFRC_Msk (0x1UL << DIEPINT_XFRC_Pos) /*!< 0x00000001 */ -#define DIEPINT_XFRC DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */ +#define DIEPINT_XFRC_Msk (0x1UL << DIEPINT_XFRC_Pos) // 0x00000001 */ +#define DIEPINT_XFRC DIEPINT_XFRC_Msk // Transfer completed interrupt */ #define DIEPINT_EPDISD_Pos (1U) -#define DIEPINT_EPDISD_Msk (0x1UL << DIEPINT_EPDISD_Pos) /*!< 0x00000002 */ -#define DIEPINT_EPDISD DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ +#define DIEPINT_EPDISD_Msk (0x1UL << DIEPINT_EPDISD_Pos) // 0x00000002 */ +#define DIEPINT_EPDISD DIEPINT_EPDISD_Msk // Endpoint disabled interrupt */ #define DIEPINT_AHBERR_Pos (2U) -#define DIEPINT_AHBERR_Msk (0x1UL << DIEPINT_AHBERR_Pos) /*!< 0x00000004 */ -#define DIEPINT_AHBERR DIEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an IN transaction */ +#define DIEPINT_AHBERR_Msk (0x1UL << DIEPINT_AHBERR_Pos) // 0x00000004 */ +#define DIEPINT_AHBERR DIEPINT_AHBERR_Msk // AHB Error (AHBErr) during an IN transaction */ #define DIEPINT_TOC_Pos (3U) -#define DIEPINT_TOC_Msk (0x1UL << DIEPINT_TOC_Pos) /*!< 0x00000008 */ -#define DIEPINT_TOC DIEPINT_TOC_Msk /*!< Timeout condition */ +#define DIEPINT_TOC_Msk (0x1UL << DIEPINT_TOC_Pos) // 0x00000008 */ +#define DIEPINT_TOC DIEPINT_TOC_Msk // Timeout condition */ #define DIEPINT_ITTXFE_Pos (4U) -#define DIEPINT_ITTXFE_Msk (0x1UL << DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ -#define DIEPINT_ITTXFE DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ +#define DIEPINT_ITTXFE_Msk (0x1UL << DIEPINT_ITTXFE_Pos) // 0x00000010 */ +#define DIEPINT_ITTXFE DIEPINT_ITTXFE_Msk // IN token received when TxFIFO is empty */ #define DIEPINT_INEPNM_Pos (5U) -#define DIEPINT_INEPNM_Msk (0x1UL << DIEPINT_INEPNM_Pos) /*!< 0x00000020 */ -#define DIEPINT_INEPNM DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ +#define DIEPINT_INEPNM_Msk (0x1UL << DIEPINT_INEPNM_Pos) // 0x00000020 */ +#define DIEPINT_INEPNM DIEPINT_INEPNM_Msk // IN token received with EP mismatch */ #define DIEPINT_INEPNE_Pos (6U) -#define DIEPINT_INEPNE_Msk (0x1UL << DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ -#define DIEPINT_INEPNE DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ +#define DIEPINT_INEPNE_Msk (0x1UL << DIEPINT_INEPNE_Pos) // 0x00000040 */ +#define DIEPINT_INEPNE DIEPINT_INEPNE_Msk // IN endpoint NAK effective */ #define DIEPINT_TXFE_Pos (7U) -#define DIEPINT_TXFE_Msk (0x1UL << DIEPINT_TXFE_Pos) /*!< 0x00000080 */ -#define DIEPINT_TXFE DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */ +#define DIEPINT_TXFE_Msk (0x1UL << DIEPINT_TXFE_Pos) // 0x00000080 */ +#define DIEPINT_TXFE DIEPINT_TXFE_Msk // Transmit FIFO empty */ #define DIEPINT_TXFIFOUDRN_Pos (8U) -#define DIEPINT_TXFIFOUDRN_Msk (0x1UL << DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */ -#define DIEPINT_TXFIFOUDRN DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */ +#define DIEPINT_TXFIFOUDRN_Msk (0x1UL << DIEPINT_TXFIFOUDRN_Pos) // 0x00000100 */ +#define DIEPINT_TXFIFOUDRN DIEPINT_TXFIFOUDRN_Msk // Transmit Fifo Underrun */ #define DIEPINT_BNA_Pos (9U) -#define DIEPINT_BNA_Msk (0x1UL << DIEPINT_BNA_Pos) /*!< 0x00000200 */ -#define DIEPINT_BNA DIEPINT_BNA_Msk /*!< Buffer not available interrupt */ +#define DIEPINT_BNA_Msk (0x1UL << DIEPINT_BNA_Pos) // 0x00000200 */ +#define DIEPINT_BNA DIEPINT_BNA_Msk // Buffer not available interrupt */ #define DIEPINT_PKTDRPSTS_Pos (11U) -#define DIEPINT_PKTDRPSTS_Msk (0x1UL << DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */ -#define DIEPINT_PKTDRPSTS DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */ +#define DIEPINT_PKTDRPSTS_Msk (0x1UL << DIEPINT_PKTDRPSTS_Pos) // 0x00000800 */ +#define DIEPINT_PKTDRPSTS DIEPINT_PKTDRPSTS_Msk // Packet dropped status */ #define DIEPINT_BERR_Pos (12U) -#define DIEPINT_BERR_Msk (0x1UL << DIEPINT_BERR_Pos) /*!< 0x00001000 */ -#define DIEPINT_BERR DIEPINT_BERR_Msk /*!< Babble error interrupt */ +#define DIEPINT_BERR_Msk (0x1UL << DIEPINT_BERR_Pos) // 0x00001000 */ +#define DIEPINT_BERR DIEPINT_BERR_Msk // Babble error interrupt */ #define DIEPINT_NAK_Pos (13U) -#define DIEPINT_NAK_Msk (0x1UL << DIEPINT_NAK_Pos) /*!< 0x00002000 */ -#define DIEPINT_NAK DIEPINT_NAK_Msk /*!< NAK interrupt */ +#define DIEPINT_NAK_Msk (0x1UL << DIEPINT_NAK_Pos) // 0x00002000 */ +#define DIEPINT_NAK DIEPINT_NAK_Msk // NAK interrupt */ /******************** Bit definition for HCINTMSK register ********************/ #define HCINTMSK_XFRCM_Pos (0U) -#define HCINTMSK_XFRCM_Msk (0x1UL << HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */ -#define HCINTMSK_XFRCM HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */ +#define HCINTMSK_XFRCM_Msk (0x1UL << HCINTMSK_XFRCM_Pos) // 0x00000001 */ +#define HCINTMSK_XFRCM HCINTMSK_XFRCM_Msk // Transfer completed mask */ #define HCINTMSK_CHHM_Pos (1U) -#define HCINTMSK_CHHM_Msk (0x1UL << HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ -#define HCINTMSK_CHHM HCINTMSK_CHHM_Msk /*!< Channel halted mask */ +#define HCINTMSK_CHHM_Msk (0x1UL << HCINTMSK_CHHM_Pos) // 0x00000002 */ +#define HCINTMSK_CHHM HCINTMSK_CHHM_Msk // Channel halted mask */ #define HCINTMSK_AHBERR_Pos (2U) -#define HCINTMSK_AHBERR_Msk (0x1UL << HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ -#define HCINTMSK_AHBERR HCINTMSK_AHBERR_Msk /*!< AHB error */ +#define HCINTMSK_AHBERR_Msk (0x1UL << HCINTMSK_AHBERR_Pos) // 0x00000004 */ +#define HCINTMSK_AHBERR HCINTMSK_AHBERR_Msk // AHB error */ #define HCINTMSK_STALLM_Pos (3U) -#define HCINTMSK_STALLM_Msk (0x1UL << HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ -#define HCINTMSK_STALLM HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ +#define HCINTMSK_STALLM_Msk (0x1UL << HCINTMSK_STALLM_Pos) // 0x00000008 */ +#define HCINTMSK_STALLM HCINTMSK_STALLM_Msk // STALL response received interrupt mask */ #define HCINTMSK_NAKM_Pos (4U) -#define HCINTMSK_NAKM_Msk (0x1UL << HCINTMSK_NAKM_Pos) /*!< 0x00000010 */ -#define HCINTMSK_NAKM HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */ +#define HCINTMSK_NAKM_Msk (0x1UL << HCINTMSK_NAKM_Pos) // 0x00000010 */ +#define HCINTMSK_NAKM HCINTMSK_NAKM_Msk // NAK response received interrupt mask */ #define HCINTMSK_ACKM_Pos (5U) -#define HCINTMSK_ACKM_Msk (0x1UL << HCINTMSK_ACKM_Pos) /*!< 0x00000020 */ -#define HCINTMSK_ACKM HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */ +#define HCINTMSK_ACKM_Msk (0x1UL << HCINTMSK_ACKM_Pos) // 0x00000020 */ +#define HCINTMSK_ACKM HCINTMSK_ACKM_Msk // ACK response received/transmitted interrupt mask */ #define HCINTMSK_NYET_Pos (6U) -#define HCINTMSK_NYET_Msk (0x1UL << HCINTMSK_NYET_Pos) /*!< 0x00000040 */ -#define HCINTMSK_NYET HCINTMSK_NYET_Msk /*!< response received interrupt mask */ +#define HCINTMSK_NYET_Msk (0x1UL << HCINTMSK_NYET_Pos) // 0x00000040 */ +#define HCINTMSK_NYET HCINTMSK_NYET_Msk // response received interrupt mask */ #define HCINTMSK_TXERRM_Pos (7U) -#define HCINTMSK_TXERRM_Msk (0x1UL << HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */ -#define HCINTMSK_TXERRM HCINTMSK_TXERRM_Msk /*!< Transaction error mask */ +#define HCINTMSK_TXERRM_Msk (0x1UL << HCINTMSK_TXERRM_Pos) // 0x00000080 */ +#define HCINTMSK_TXERRM HCINTMSK_TXERRM_Msk // Transaction error mask */ #define HCINTMSK_BBERRM_Pos (8U) -#define HCINTMSK_BBERRM_Msk (0x1UL << HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */ -#define HCINTMSK_BBERRM HCINTMSK_BBERRM_Msk /*!< Babble error mask */ +#define HCINTMSK_BBERRM_Msk (0x1UL << HCINTMSK_BBERRM_Pos) // 0x00000100 */ +#define HCINTMSK_BBERRM HCINTMSK_BBERRM_Msk // Babble error mask */ #define HCINTMSK_FRMORM_Pos (9U) -#define HCINTMSK_FRMORM_Msk (0x1UL << HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */ -#define HCINTMSK_FRMORM HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */ +#define HCINTMSK_FRMORM_Msk (0x1UL << HCINTMSK_FRMORM_Pos) // 0x00000200 */ +#define HCINTMSK_FRMORM HCINTMSK_FRMORM_Msk // Frame overrun mask */ #define HCINTMSK_DTERRM_Pos (10U) -#define HCINTMSK_DTERRM_Msk (0x1UL << HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */ -#define HCINTMSK_DTERRM HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */ +#define HCINTMSK_DTERRM_Msk (0x1UL << HCINTMSK_DTERRM_Pos) // 0x00000400 */ +#define HCINTMSK_DTERRM HCINTMSK_DTERRM_Msk // Data toggle error mask */ /******************** Bit definition for DIEPTSIZ register ********************/ #define DIEPTSIZ_XFRSIZ_Pos (0U) -#define DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ -#define DIEPTSIZ_XFRSIZ DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */ +#define DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << DIEPTSIZ_XFRSIZ_Pos) // 0x0007FFFF */ +#define DIEPTSIZ_XFRSIZ DIEPTSIZ_XFRSIZ_Msk // Transfer size */ #define DIEPTSIZ_PKTCNT_Pos (19U) -#define DIEPTSIZ_PKTCNT_Msk (0x3FFUL << DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ -#define DIEPTSIZ_PKTCNT DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ +#define DIEPTSIZ_PKTCNT_Msk (0x3FFUL << DIEPTSIZ_PKTCNT_Pos) // 0x1FF80000 */ +#define DIEPTSIZ_PKTCNT DIEPTSIZ_PKTCNT_Msk // Packet count */ #define DIEPTSIZ_MULCNT_Pos (29U) -#define DIEPTSIZ_MULCNT_Msk (0x3UL << DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ -#define DIEPTSIZ_MULCNT DIEPTSIZ_MULCNT_Msk /*!< Packet count */ +#define DIEPTSIZ_MULCNT_Msk (0x3UL << DIEPTSIZ_MULCNT_Pos) // 0x60000000 */ +#define DIEPTSIZ_MULCNT DIEPTSIZ_MULCNT_Msk // Packet count */ /******************** Bit definition for HCTSIZ register ********************/ #define HCTSIZ_XFRSIZ_Pos (0U) -#define HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ -#define HCTSIZ_XFRSIZ HCTSIZ_XFRSIZ_Msk /*!< Transfer size */ +#define HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << HCTSIZ_XFRSIZ_Pos) // 0x0007FFFF */ +#define HCTSIZ_XFRSIZ HCTSIZ_XFRSIZ_Msk // Transfer size */ #define HCTSIZ_PKTCNT_Pos (19U) -#define HCTSIZ_PKTCNT_Msk (0x3FFUL << HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ -#define HCTSIZ_PKTCNT HCTSIZ_PKTCNT_Msk /*!< Packet count */ +#define HCTSIZ_PKTCNT_Msk (0x3FFUL << HCTSIZ_PKTCNT_Pos) // 0x1FF80000 */ +#define HCTSIZ_PKTCNT HCTSIZ_PKTCNT_Msk // Packet count */ #define HCTSIZ_DOPING_Pos (31U) -#define HCTSIZ_DOPING_Msk (0x1UL << HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ -#define HCTSIZ_DOPING HCTSIZ_DOPING_Msk /*!< Do PING */ +#define HCTSIZ_DOPING_Msk (0x1UL << HCTSIZ_DOPING_Pos) // 0x80000000 */ +#define HCTSIZ_DOPING HCTSIZ_DOPING_Msk // Do PING */ #define HCTSIZ_DPID_Pos (29U) -#define HCTSIZ_DPID_Msk (0x3UL << HCTSIZ_DPID_Pos) /*!< 0x60000000 */ -#define HCTSIZ_DPID HCTSIZ_DPID_Msk /*!< Data PID */ -#define HCTSIZ_DPID_0 (0x1UL << HCTSIZ_DPID_Pos) /*!< 0x20000000 */ -#define HCTSIZ_DPID_1 (0x2UL << HCTSIZ_DPID_Pos) /*!< 0x40000000 */ +#define HCTSIZ_DPID_Msk (0x3UL << HCTSIZ_DPID_Pos) // 0x60000000 */ +#define HCTSIZ_DPID HCTSIZ_DPID_Msk // Data PID */ +#define HCTSIZ_DPID_0 (0x1UL << HCTSIZ_DPID_Pos) // 0x20000000 */ +#define HCTSIZ_DPID_1 (0x2UL << HCTSIZ_DPID_Pos) // 0x40000000 */ /******************** Bit definition for DIEPDMA register ********************/ #define DIEPDMA_DMAADDR_Pos (0U) -#define DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */ -#define DIEPDMA_DMAADDR DIEPDMA_DMAADDR_Msk /*!< DMA address */ +#define DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << DIEPDMA_DMAADDR_Pos) // 0xFFFFFFFF */ +#define DIEPDMA_DMAADDR DIEPDMA_DMAADDR_Msk // DMA address */ /******************** Bit definition for HCDMA register ********************/ #define HCDMA_DMAADDR_Pos (0U) -#define HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */ -#define HCDMA_DMAADDR HCDMA_DMAADDR_Msk /*!< DMA address */ +#define HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << HCDMA_DMAADDR_Pos) // 0xFFFFFFFF */ +#define HCDMA_DMAADDR HCDMA_DMAADDR_Msk // DMA address */ /******************** Bit definition for DTXFSTS register ********************/ #define DTXFSTS_INEPTFSAV_Pos (0U) -#define DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */ -#define DTXFSTS_INEPTFSAV DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */ +#define DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << DTXFSTS_INEPTFSAV_Pos) // 0x0000FFFF */ +#define DTXFSTS_INEPTFSAV DTXFSTS_INEPTFSAV_Msk // IN endpoint TxFIFO space available */ /******************** Bit definition for DIEPTXF register ********************/ #define DIEPTXF_INEPTXSA_Pos (0U) -#define DIEPTXF_INEPTXSA_Msk (0xFFFFUL << DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */ -#define DIEPTXF_INEPTXSA DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */ +#define DIEPTXF_INEPTXSA_Msk (0xFFFFUL << DIEPTXF_INEPTXSA_Pos) // 0x0000FFFF */ +#define DIEPTXF_INEPTXSA DIEPTXF_INEPTXSA_Msk // IN endpoint FIFOx transmit RAM start address */ #define DIEPTXF_INEPTXFD_Pos (16U) -#define DIEPTXF_INEPTXFD_Msk (0xFFFFUL << DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */ -#define DIEPTXF_INEPTXFD DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */ +#define DIEPTXF_INEPTXFD_Msk (0xFFFFUL << DIEPTXF_INEPTXFD_Pos) // 0xFFFF0000 */ +#define DIEPTXF_INEPTXFD DIEPTXF_INEPTXFD_Msk // IN endpoint TxFIFO depth */ /******************** Bit definition for DOEPCTL register ********************/ #define DOEPCTL_MPSIZ_Pos (0U) -#define DOEPCTL_MPSIZ_Msk (0x7FFUL << DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */ -#define DOEPCTL_MPSIZ DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*! Date: Tue, 26 Oct 2021 11:11:46 +0700 Subject: more rename --- src/portable/synopsys/dwc2/dcd_dwc2.c | 189 +++++++++++++++----------------- src/portable/synopsys/dwc2/dwc2_esp32.h | 2 +- src/portable/synopsys/dwc2/dwc2_gd32.h | 2 +- src/portable/synopsys/dwc2/dwc2_stm32.h | 2 +- src/portable/synopsys/dwc2/dwc2_type.h | 8 +- 5 files changed, 97 insertions(+), 106 deletions(-) diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index b98bd0055..c0bf655f4 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -51,8 +51,7 @@ // MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ -#define CORE_REG(_port) ((dwc2_core_t*) DWC2_REG_BASE) -#define DEVICE_REG(_port) CORE_REG(_port) //((dwc2_core_t*) (DWC2_REG_BASE + DWC2_DEVICE_BASE)) +#define DWC2_REG(_port) ((dwc2_regs_t*) DWC2_REG_BASE) #define EPIN_REG(_port) ((dwc2_epin_t*) (DWC2_REG_BASE + DWC2_IN_ENDPOINT_BASE)) #define EPOUT_REG(_port) ((dwc2_epout_t*) (DWC2_REG_BASE + DWC2_OUT_ENDPOINT_BASE)) #define FIFO_BASE(_port, _x) ((volatile uint32_t*) (DWC2_REG_BASE + DWC2_FIFO_BASE + (_x) * DWC2_FIFO_SIZE)) @@ -98,7 +97,7 @@ static void update_grxfsiz(uint8_t rhport) { (void) rhport; - dwc2_core_t * core = CORE_REG(rhport); + dwc2_regs_t * core = DWC2_REG(rhport); // Determine largest EP size for RX FIFO uint16_t max_epsize = 0; @@ -116,8 +115,7 @@ static void bus_reset(uint8_t rhport) { (void) rhport; - dwc2_core_t * core = CORE_REG(rhport); - dwc2_core_t * dev = DEVICE_REG(rhport); + dwc2_regs_t * dwc2 = DWC2_REG(rhport); dwc2_epout_t * out_ep = EPOUT_REG(rhport); dwc2_epin_t * in_ep = EPIN_REG(rhport); @@ -125,7 +123,7 @@ static void bus_reset(uint8_t rhport) _out_ep_closed = false; // clear device address - dev->dcfg &= ~DCFG_DAD_Msk; + dwc2->dcfg &= ~DCFG_DAD_Msk; // 1. NAK for all OUT endpoints for(uint8_t n = 0; n < DWC2_EP_MAX; n++) { @@ -133,9 +131,9 @@ static void bus_reset(uint8_t rhport) } // 2. Un-mask interrupt bits - dev->daintmsk = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos); - dev->doepmsk = DOEPMSK_STUPM | DOEPMSK_XFRCM; - dev->diepmsk = DIEPMSK_TOM | DIEPMSK_XFRCM; + dwc2->daintmsk = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos); + dwc2->doepmsk = DOEPMSK_STUPM | DOEPMSK_XFRCM; + dwc2->diepmsk = DIEPMSK_TOM | DIEPMSK_XFRCM; // "USB Data FIFOs" section in reference manual // Peripheral FIFO architecture @@ -187,12 +185,12 @@ static void bus_reset(uint8_t rhport) // are enabled at least "2 x (Largest-EPsize/4) + 1" are recommended. Maybe provide a macro for application to // overwrite this. - core->grxfsiz = calc_rx_ff_size(TUD_OPT_HIGH_SPEED ? 512 : 64); + dwc2->grxfsiz = calc_rx_ff_size(TUD_OPT_HIGH_SPEED ? 512 : 64); _allocated_fifo_words_tx = 16; // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word ) - core->dieptxf0 = (16 << TX0FD_Pos) | (DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx); + dwc2->dieptxf0 = (16 << TX0FD_Pos) | (DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx); // Fixed control EP0 size to 64 bytes in_ep[0].DIEPCTL &= ~(0x03 << DIEPCTL_MPSIZ_Pos); @@ -200,15 +198,15 @@ static void bus_reset(uint8_t rhport) out_ep[0].DOEPTSIZ |= (3 << DOEPTSIZ_STUPCNT_Pos); - core->gintmsk |= GINTMSK_OEPINT | GINTMSK_IEPINT; + dwc2->gintmsk |= GINTMSK_OEPINT | GINTMSK_IEPINT; } static tusb_speed_t get_speed(uint8_t rhport) { (void) rhport; - dwc2_core_t * dev = DEVICE_REG(rhport); - uint32_t const enum_spd = (dev->dsts & DSTS_ENUMSPD_Msk) >> DSTS_ENUMSPD_Pos; + dwc2_regs_t * dwc2 = DWC2_REG(rhport); + uint32_t const enum_spd = (dwc2->dsts & DSTS_ENUMSPD_Msk) >> DSTS_ENUMSPD_Pos; return (enum_spd == DCD_HIGH_SPEED) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL; } @@ -225,11 +223,11 @@ static void set_speed(uint8_t rhport, tusb_speed_t speed) bitvalue = DCD_FULL_SPEED; } - dwc2_core_t * dev = DEVICE_REG(rhport); + dwc2_regs_t * dwc2 = DWC2_REG(rhport); // Clear and set speed bits - dev->dcfg &= ~(3 << DCFG_DSPD_Pos); - dev->dcfg |= (bitvalue << DCFG_DSPD_Pos); + dwc2->dcfg &= ~(3 << DCFG_DSPD_Pos); + dwc2->dcfg |= (bitvalue << DCFG_DSPD_Pos); } #if defined(USB_HS_PHYC) @@ -277,7 +275,7 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c { (void) rhport; - dwc2_core_t * dev = DEVICE_REG(rhport); + dwc2_regs_t * dwc2 = DWC2_REG(rhport); dwc2_epout_t * out_ep = EPOUT_REG(rhport); dwc2_epin_t * in_ep = EPIN_REG(rhport); @@ -301,12 +299,12 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c if ((in_ep[epnum].DIEPCTL & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) { // Take odd/even bit from frame counter. - uint32_t const odd_frame_now = (dev->dsts & (1u << DSTS_FNSOF_Pos)); + uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos)); in_ep[epnum].DIEPCTL |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk); } // Enable fifo empty interrupt only if there are something to put in the fifo. if(total_bytes != 0) { - dev->diepempmsk |= (1 << epnum); + dwc2->diepempmsk |= (1 << epnum); } } else { // A full OUT transfer (multiple packets, possibly) triggers XFRC. @@ -318,7 +316,7 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c if ((out_ep[epnum].DOEPCTL & DOEPCTL_EPTYP) == DOEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) { // Take odd/even bit from frame counter. - uint32_t const odd_frame_now = (dev->dsts & (1u << DSTS_FNSOF_Pos)); + uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos)); out_ep[epnum].DOEPCTL |= (odd_frame_now ? DOEPCTL_SD0PID_SEVNFRM_Msk : DOEPCTL_SODDFRM_Msk); } } @@ -331,7 +329,7 @@ void dcd_init (uint8_t rhport) { // Programming model begins in the last section of the chapter on the USB // peripheral in each Reference Manual. - dwc2_core_t * core = CORE_REG(rhport); + dwc2_regs_t * dwc2 = DWC2_REG(rhport); // check GSNPSID @@ -341,23 +339,23 @@ void dcd_init (uint8_t rhport) // On selected MCUs HS port1 can be used with external PHY via ULPI interface #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED // deactivate internal PHY - core->gccfg &= ~GCCFG_PWRDWN; + dwc2->gccfg &= ~GCCFG_PWRDWN; // Init The UTMI Interface - core->gusbcfg &= ~(GUSBCFG_TSDPS | GUSBCFG_ULPIFSLS | GUSBCFG_PHYSEL); + dwc2->gusbcfg &= ~(GUSBCFG_TSDPS | GUSBCFG_ULPIFSLS | GUSBCFG_PHYSEL); // Select default internal VBUS Indicator and Drive for ULPI - core->gusbcfg &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI); + dwc2->gusbcfg &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI); #else - core->gusbcfg |= GUSBCFG_PHYSEL; + dwc2->gusbcfg |= GUSBCFG_PHYSEL; #endif #if defined(USB_HS_PHYC) // Highspeed with embedded UTMI PHYC // Select UTMI Interface - core->gusbcfg &= ~GUSBCFG_ULPI_UTMI_SEL; - core->gccfg |= GCCFG_PHYHSEN; + dwc2->gusbcfg &= ~GUSBCFG_ULPI_UTMI_SEL; + dwc2->gccfg |= GCCFG_PHYHSEN; // Enables control of a High Speed USB PHY USB_HS_PHYCInit(); @@ -365,42 +363,40 @@ void dcd_init (uint8_t rhport) } else { // Enable internal PHY - core->gusbcfg |= GUSBCFG_PHYSEL; + dwc2->gusbcfg |= GUSBCFG_PHYSEL; } // Reset core after selecting PHYst // Wait AHB IDLE, reset then wait until it is cleared - while ((core->grstctl & GRSTCTL_AHBIDL) == 0U) {} - core->grstctl |= GRSTCTL_CSRST; - while ((core->grstctl & GRSTCTL_CSRST) == GRSTCTL_CSRST) {} + while ((dwc2->grstctl & GRSTCTL_AHBIDL) == 0U) {} + dwc2->grstctl |= GRSTCTL_CSRST; + while ((dwc2->grstctl & GRSTCTL_CSRST) == GRSTCTL_CSRST) {} // Restart PHY clock *((volatile uint32_t *)(DWC2_REG_BASE + DWC2_PCGCCTL_BASE)) = 0; // Clear all interrupts - core->gintsts |= core->gintsts; + dwc2->gintsts |= dwc2->gintsts; // Required as part of core initialization. // TODO: How should mode mismatch be handled? It will cause // the core to stop working/require reset. - core->gintmsk |= GINTMSK_OTGINT | GINTMSK_MMISM; - - dwc2_core_t * dev = DEVICE_REG(rhport); + dwc2->gintmsk |= GINTMSK_OTGINT | GINTMSK_MMISM; // If USB host misbehaves during status portion of control xfer // (non zero-length packet), send STALL back and discard. - dev->dcfg |= DCFG_NZLSOHSK; + dwc2->dcfg |= DCFG_NZLSOHSK; set_speed(rhport, TUD_OPT_HIGH_SPEED ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL); // Enable internal USB transceiver, unless using HS core (port 1) with external PHY. - if (!(rhport == 1 && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED))) core->gccfg |= GCCFG_PWRDWN; + if (!(rhport == 1 && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED))) dwc2->gccfg |= GCCFG_PWRDWN; - core->gintmsk |= GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_USBSUSPM | + dwc2->gintmsk |= GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_USBSUSPM | GINTMSK_WUIM | GINTMSK_RXFLVLM; // Enable global interrupt - core->gahbcfg |= GAHBCFG_GINT; + dwc2->gahbcfg |= GAHBCFG_GINT; dcd_connect(rhport); } @@ -417,8 +413,8 @@ void dcd_int_disable (uint8_t rhport) void dcd_set_address (uint8_t rhport, uint8_t dev_addr) { - dwc2_core_t * dev = DEVICE_REG(rhport); - dev->dcfg = (dev->dcfg & ~DCFG_DAD_Msk) | (dev_addr << DCFG_DAD_Pos); + dwc2_regs_t * dwc2 = DWC2_REG(rhport); + dwc2->dcfg = (dwc2->dcfg & ~DCFG_DAD_Msk) | (dev_addr << DCFG_DAD_Pos); // Response with status after changing device address dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0); @@ -428,34 +424,33 @@ void dcd_remote_wakeup(uint8_t rhport) { (void) rhport; - dwc2_core_t * core = CORE_REG(rhport); - dwc2_core_t * dev = DEVICE_REG(rhport); + dwc2_regs_t* dwc2 = DWC2_REG(rhport); // set remote wakeup - dev->dctl |= DCTL_RWUSIG; + dwc2->dctl |= DCTL_RWUSIG; // enable SOF to detect bus resume - core->gintsts = GINTSTS_SOF; - core->gintmsk |= GINTMSK_SOFM; + dwc2->gintsts = GINTSTS_SOF; + dwc2->gintmsk |= GINTMSK_SOFM; // Per specs: remote wakeup signal bit must be clear within 1-15ms dwc2_remote_wakeup_delay(); - dev->dctl &= ~DCTL_RWUSIG; + dwc2->dctl &= ~DCTL_RWUSIG; } void dcd_connect(uint8_t rhport) { (void) rhport; - dwc2_core_t * dev = DEVICE_REG(rhport); - dev->dctl &= ~DCTL_SDIS; + dwc2_regs_t * dwc2 = DWC2_REG(rhport); + dwc2->dctl &= ~DCTL_SDIS; } void dcd_disconnect(uint8_t rhport) { (void) rhport; - dwc2_core_t * dev = DEVICE_REG(rhport); - dev->dctl |= DCTL_SDIS; + dwc2_regs_t * dwc2 = DWC2_REG(rhport); + dwc2->dctl |= DCTL_SDIS; } @@ -467,8 +462,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) { (void) rhport; - dwc2_core_t * core = CORE_REG(rhport); - dwc2_core_t * dev = DEVICE_REG(rhport); + dwc2_regs_t * dwc2 = DWC2_REG(rhport); dwc2_epout_t * out_ep = EPOUT_REG(rhport); dwc2_epin_t * in_ep = EPIN_REG(rhport); @@ -489,12 +483,12 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) uint16_t const sz = calc_rx_ff_size(4*fifo_size); // If size_rx needs to be extended check if possible and if so enlarge it - if (core->grxfsiz < sz) + if (dwc2->grxfsiz < sz) { TU_ASSERT(sz + _allocated_fifo_words_tx <= DWC2_EP_FIFO_SIZE/4); // Enlarge RX FIFO - core->grxfsiz = sz; + dwc2->grxfsiz = sz; } out_ep[epnum].DOEPCTL |= (1 << DOEPCTL_USBAEP_Pos) | @@ -502,7 +496,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DOEPCTL_SD0PID_SEVNFRM : 0) | (xfer->max_size << DOEPCTL_MPSIZ_Pos); - dev->daintmsk |= (1 << (DAINTMSK_OEPM_Pos + epnum)); + dwc2->daintmsk |= (1 << (DAINTMSK_OEPM_Pos + epnum)); } else { @@ -528,7 +522,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n". // Check if free space is available - TU_ASSERT(_allocated_fifo_words_tx + fifo_size + core->grxfsiz <= DWC2_EP_FIFO_SIZE/4); + TU_ASSERT(_allocated_fifo_words_tx + fifo_size + dwc2->grxfsiz <= DWC2_EP_FIFO_SIZE/4); _allocated_fifo_words_tx += fifo_size; @@ -536,7 +530,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) // DIEPTXF starts at FIFO #1. // Both TXFD and TXSA are in unit of 32-bit words. - core->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | (DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx); + dwc2->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | (DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx); in_ep[epnum].DIEPCTL |= (1 << DIEPCTL_USBAEP_Pos) | (epnum << DIEPCTL_TXFNUM_Pos) | @@ -544,7 +538,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DIEPCTL_SD0PID_SEVNFRM : 0) | (xfer->max_size << DIEPCTL_MPSIZ_Pos); - dev->daintmsk |= (1 << (DAINTMSK_IEPM_Pos + epnum)); + dwc2->daintmsk |= (1 << (DAINTMSK_IEPM_Pos + epnum)); } return true; @@ -555,13 +549,12 @@ void dcd_edpt_close_all (uint8_t rhport) { (void) rhport; -// dwc2_core_t * core = CORE_REG(rhport); - dwc2_core_t * dev = DEVICE_REG(rhport); + dwc2_regs_t * dwc2 = DWC2_REG(rhport); dwc2_epout_t * out_ep = EPOUT_REG(rhport); dwc2_epin_t * in_ep = EPIN_REG(rhport); // Disable non-control interrupt - dev->daintmsk = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos); + dwc2->daintmsk = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos); for(uint8_t n = 1; n < DWC2_EP_MAX; n++) { @@ -642,8 +635,7 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall) { (void) rhport; - dwc2_core_t * core = CORE_REG(rhport); - dwc2_core_t * dev = DEVICE_REG(rhport); + dwc2_regs_t * dwc2 = DWC2_REG(rhport); dwc2_epout_t * out_ep = EPOUT_REG(rhport); dwc2_epin_t * in_ep = EPIN_REG(rhport); @@ -671,9 +663,9 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall) } // Flush the FIFO, and wait until we have confirmed it cleared. - core->grstctl |= (epnum << GRSTCTL_TXFNUM_Pos); - core->grstctl |= GRSTCTL_TXFFLSH; - while ( (core->grstctl & GRSTCTL_TXFFLSH_Msk) != 0 ) {} + dwc2->grstctl |= (epnum << GRSTCTL_TXFNUM_Pos); + dwc2->grstctl |= GRSTCTL_TXFFLSH; + while ( (dwc2->grstctl & GRSTCTL_TXFFLSH_Msk) != 0 ) {} } else { @@ -688,8 +680,8 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall) // Simpler to use polling here, we don't use the "B"OUTNAKEFF interrupt // anyway, and it can't be cleared by user code. If this while loop never // finishes, we have bigger problems than just the stack. - dev->dctl |= DCTL_SGONAK; - while ( (core->gintsts & GINTSTS_BOUTNAKEFF_Msk) == 0 ) {} + dwc2->dctl |= DCTL_SGONAK; + while ( (dwc2->gintsts & GINTSTS_BOUTNAKEFF_Msk) == 0 ) {} // Ditto here- disable the endpoint. out_ep[epnum].DOEPCTL |= DOEPCTL_EPDIS | (stall ? DOEPCTL_STALL : 0); @@ -698,7 +690,7 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall) out_ep[epnum].DOEPINT = DOEPINT_EPDISD; // Allow other OUT endpoints to keep receiving. - dev->dctl |= DCTL_CGONAK; + dwc2->dctl |= DCTL_CGONAK; } } } @@ -708,7 +700,7 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall) */ void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr) { - dwc2_core_t * core = CORE_REG(rhport); + dwc2_regs_t * dwc2 = DWC2_REG(rhport); uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); @@ -720,8 +712,8 @@ void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr) if (dir == TUSB_DIR_IN) { - uint16_t const fifo_size = (core->dieptxf[epnum - 1] & DIEPTXF_INEPTXFD_Msk) >> DIEPTXF_INEPTXFD_Pos; - uint16_t const fifo_start = (core->dieptxf[epnum - 1] & DIEPTXF_INEPTXSA_Msk) >> DIEPTXF_INEPTXSA_Pos; + uint16_t const fifo_size = (dwc2->dieptxf[epnum - 1] & DIEPTXF_INEPTXFD_Msk) >> DIEPTXF_INEPTXFD_Pos; + uint16_t const fifo_start = (dwc2->dieptxf[epnum - 1] & DIEPTXF_INEPTXSA_Msk) >> DIEPTXF_INEPTXSA_Pos; // For now only the last opened endpoint can be closed without fuss. TU_ASSERT(fifo_start == DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx,); _allocated_fifo_words_tx -= fifo_size; @@ -832,11 +824,11 @@ static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t * src, u } static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep) { - dwc2_core_t * core = CORE_REG(rhport); + dwc2_regs_t * dwc2 = DWC2_REG(rhport); volatile uint32_t * rx_fifo = FIFO_BASE(rhport, 0); // Pop control word off FIFO - uint32_t ctl_word = core->grxstsp; + uint32_t ctl_word = dwc2->grxstsp; uint8_t pktsts = (ctl_word & GRXSTSP_PKTSTS_Msk) >> GRXSTSP_PKTSTS_Pos; uint8_t epnum = (ctl_word & GRXSTSP_EPNUM_Msk) >> GRXSTSP_EPNUM_Pos; uint16_t bcnt = (ctl_word & GRXSTSP_BCNT_Msk) >> GRXSTSP_BCNT_Pos; @@ -896,7 +888,7 @@ static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep) { } } -static void handle_epout_ints (uint8_t rhport, dwc2_core_t *dev, dwc2_epout_t *out_ep) +static void handle_epout_ints (uint8_t rhport, dwc2_regs_t *dwc2, dwc2_epout_t *out_ep) { // DAINT for a given EP clears when DOEPINTx is cleared. // OEPINT will be cleared when DAINT's out bits are cleared. @@ -904,7 +896,7 @@ static void handle_epout_ints (uint8_t rhport, dwc2_core_t *dev, dwc2_epout_t *o { xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT); - if ( dev->daint & (1 << (DAINT_OEPINT_Pos + n)) ) + if ( dwc2->daint & (1 << (DAINT_OEPINT_Pos + n)) ) { // SETUP packet Setup Phase done. if ( out_ep[n].DOEPINT & DOEPINT_STUP ) @@ -933,14 +925,14 @@ static void handle_epout_ints (uint8_t rhport, dwc2_core_t *dev, dwc2_epout_t *o } } -static void handle_epin_ints(uint8_t rhport, dwc2_core_t * dev, dwc2_epin_t * in_ep) { +static void handle_epin_ints(uint8_t rhport, dwc2_regs_t * dwc2, dwc2_epin_t * in_ep) { // DAINT for a given EP clears when DIEPINTx is cleared. // IEPINT will be cleared when DAINT's out bits are cleared. for ( uint8_t n = 0; n < DWC2_EP_MAX; n++ ) { xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_IN); - if ( dev->daint & (1 << (DAINT_IEPINT_Pos + n)) ) + if ( dwc2->daint & (1 << (DAINT_IEPINT_Pos + n)) ) { // IN XFER complete (entire xfer). if ( in_ep[n].DIEPINT & DIEPINT_XFRC ) @@ -957,7 +949,7 @@ static void handle_epin_ints(uint8_t rhport, dwc2_core_t * dev, dwc2_epin_t * in } // XFER FIFO empty - if ( (in_ep[n].DIEPINT & DIEPINT_TXFE) && (dev->diepempmsk & (1 << n)) ) + if ( (in_ep[n].DIEPINT & DIEPINT_TXFE) && (dwc2->diepempmsk & (1 << n)) ) { // DIEPINT's TXFE bit is read-only, software cannot clear it. // It will only be cleared by hardware when written bytes is more than @@ -996,7 +988,7 @@ static void handle_epin_ints(uint8_t rhport, dwc2_core_t * dev, dwc2_epin_t * in // Turn off TXFE if all bytes are written. if (((in_ep[n].DIEPTSIZ & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos) == 0) { - dev->diepempmsk &= ~(1 << n); + dwc2->diepempmsk &= ~(1 << n); } } } @@ -1005,17 +997,16 @@ static void handle_epin_ints(uint8_t rhport, dwc2_core_t * dev, dwc2_epin_t * in void dcd_int_handler(uint8_t rhport) { - dwc2_core_t * core = CORE_REG(rhport); - dwc2_core_t * dev = DEVICE_REG(rhport); + dwc2_regs_t * dwc2 = DWC2_REG(rhport); dwc2_epout_t * out_ep = EPOUT_REG(rhport); dwc2_epin_t * in_ep = EPIN_REG(rhport); - uint32_t const int_status = core->gintsts & core->gintmsk; + uint32_t const int_status = dwc2->gintsts & dwc2->gintmsk; if(int_status & GINTSTS_USBRST) { // USBRST is start of reset. - core->gintsts = GINTSTS_USBRST; + dwc2->gintsts = GINTSTS_USBRST; bus_reset(rhport); } @@ -1023,23 +1014,23 @@ void dcd_int_handler(uint8_t rhport) { // ENUMDNE is the end of reset where speed of the link is detected - core->gintsts = GINTSTS_ENUMDNE; + dwc2->gintsts = GINTSTS_ENUMDNE; tusb_speed_t const speed = get_speed(rhport); - dwc2_set_turnaround(core, speed); + dwc2_set_turnaround(dwc2, speed); dcd_event_bus_reset(rhport, speed, true); } if(int_status & GINTSTS_USBSUSP) { - core->gintsts = GINTSTS_USBSUSP; + dwc2->gintsts = GINTSTS_USBSUSP; dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); } if(int_status & GINTSTS_WKUINT) { - core->gintsts = GINTSTS_WKUINT; + dwc2->gintsts = GINTSTS_WKUINT; dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true); } @@ -1049,22 +1040,22 @@ void dcd_int_handler(uint8_t rhport) if(int_status & GINTSTS_OTGINT) { // OTG INT bit is read-only - uint32_t const otg_int = core->gotgint; + uint32_t const otg_int = dwc2->gotgint; if (otg_int & GOTGINT_SEDET) { dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true); } - core->gotgint = otg_int; + dwc2->gotgint = otg_int; } if(int_status & GINTSTS_SOF) { - core->gotgint = GINTSTS_SOF; + dwc2->gotgint = GINTSTS_SOF; // Disable SOF interrupt since currently only used for remote wakeup detection - core->gintmsk &= ~GINTMSK_SOFM; + dwc2->gintmsk &= ~GINTMSK_SOFM; dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true); } @@ -1075,13 +1066,13 @@ void dcd_int_handler(uint8_t rhport) // RXFLVL bit is read-only // Mask out RXFLVL while reading data from FIFO - core->gintmsk &= ~GINTMSK_RXFLVLM; + dwc2->gintmsk &= ~GINTMSK_RXFLVLM; // Loop until all available packets were handled do { handle_rxflvl_ints(rhport, out_ep); - } while(core->gotgint & GINTSTS_RXFLVL); + } while(dwc2->gotgint & GINTSTS_RXFLVL); // Manage RX FIFO size if (_out_ep_closed) @@ -1092,21 +1083,21 @@ void dcd_int_handler(uint8_t rhport) _out_ep_closed = false; } - core->gintmsk |= GINTMSK_RXFLVLM; + dwc2->gintmsk |= GINTMSK_RXFLVLM; } // OUT endpoint interrupt handling. if(int_status & GINTSTS_OEPINT) { // OEPINT is read-only - handle_epout_ints(rhport, dev, out_ep); + handle_epout_ints(rhport, dwc2, out_ep); } // IN endpoint interrupt handling. if(int_status & GINTSTS_IEPINT) { // IEPINT bit read-only - handle_epin_ints(rhport, dev, in_ep); + handle_epin_ints(rhport, dwc2, in_ep); } // // Check for Incomplete isochronous IN transfer diff --git a/src/portable/synopsys/dwc2/dwc2_esp32.h b/src/portable/synopsys/dwc2/dwc2_esp32.h index 5e544673d..d73ec0504 100644 --- a/src/portable/synopsys/dwc2/dwc2_esp32.h +++ b/src/portable/synopsys/dwc2/dwc2_esp32.h @@ -67,7 +67,7 @@ static inline void dwc2_remote_wakeup_delay(void) vTaskDelay(pdMS_TO_TICKS(1)); } -static inline void dwc2_set_turnaround(dwc2_core_t * core, tusb_speed_t speed) +static inline void dwc2_set_turnaround(dwc2_regs_t * core, tusb_speed_t speed) { (void) core; (void) speed; diff --git a/src/portable/synopsys/dwc2/dwc2_gd32.h b/src/portable/synopsys/dwc2/dwc2_gd32.h index db1fb89fd..f0c7cfb38 100644 --- a/src/portable/synopsys/dwc2/dwc2_gd32.h +++ b/src/portable/synopsys/dwc2/dwc2_gd32.h @@ -76,7 +76,7 @@ static inline void dwc2_remote_wakeup_delay(void) while ( count-- ) __asm volatile ("nop"); } -static inline void dwc2_set_turnaround(dwc2_core_t * core, tusb_speed_t speed) +static inline void dwc2_set_turnaround(dwc2_regs_t * core, tusb_speed_t speed) { (void) core; (void) speed; diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h index d2ad8abb7..5a0071563 100644 --- a/src/portable/synopsys/dwc2/dwc2_stm32.h +++ b/src/portable/synopsys/dwc2/dwc2_stm32.h @@ -113,7 +113,7 @@ static inline void dwc2_remote_wakeup_delay(void) } // Set turn-around timeout according to link speed -static inline void dwc2_set_turnaround(dwc2_core_t * core, tusb_speed_t speed) +static inline void dwc2_set_turnaround(dwc2_regs_t * core, tusb_speed_t speed) { core->gusbcfg &= ~GUSBCFG_TRDT; diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index b83ac67f9..23d724366 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -134,11 +134,11 @@ union { //------------- Device OUT Endpoint -------------// -} dwc2_core_t; +} dwc2_regs_t; -TU_VERIFY_STATIC(offsetof(dwc2_core_t, hcfg ) == 0x0400, "incorrect size"); -TU_VERIFY_STATIC(offsetof(dwc2_core_t, channel) == 0x0500, "incorrect size"); -TU_VERIFY_STATIC(offsetof(dwc2_core_t, dcfg ) == 0x0800, "incorrect size"); +TU_VERIFY_STATIC(offsetof(dwc2_regs_t, hcfg ) == 0x0400, "incorrect size"); +TU_VERIFY_STATIC(offsetof(dwc2_regs_t, channel) == 0x0500, "incorrect size"); +TU_VERIFY_STATIC(offsetof(dwc2_regs_t, dcfg ) == 0x0800, "incorrect size"); // Endpoint IN typedef struct -- cgit v1.3.1 From 3755814f570b8803fad63b727f1f194aeca9e796 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 26 Oct 2021 11:49:59 +0700 Subject: add epin, epout to dwc2 regs --- src/portable/synopsys/dwc2/dcd_dwc2.c | 101 ++++++++++++++++---------------- src/portable/synopsys/dwc2/dwc2_esp32.h | 4 +- src/portable/synopsys/dwc2/dwc2_gd32.h | 4 +- src/portable/synopsys/dwc2/dwc2_stm32.h | 4 +- src/portable/synopsys/dwc2/dwc2_type.h | 83 +++++++++++++------------- 5 files changed, 98 insertions(+), 98 deletions(-) diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index c0bf655f4..468ce520f 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -31,6 +31,7 @@ #include "device/dcd_attr.h" + #if TUSB_OPT_DEVICE_ENABLED && \ ( defined(DCD_ATTR_DWC2_STM32) || TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3, OPT_MCU_GD32VF103) ) @@ -52,8 +53,8 @@ //--------------------------------------------------------------------+ #define DWC2_REG(_port) ((dwc2_regs_t*) DWC2_REG_BASE) -#define EPIN_REG(_port) ((dwc2_epin_t*) (DWC2_REG_BASE + DWC2_IN_ENDPOINT_BASE)) -#define EPOUT_REG(_port) ((dwc2_epout_t*) (DWC2_REG_BASE + DWC2_OUT_ENDPOINT_BASE)) +#define EPIN_REG(_port) (DWC2_REG(_port)->epin) +#define EPOUT_REG(_port) (DWC2_REG(_port)->epout) #define FIFO_BASE(_port, _x) ((volatile uint32_t*) (DWC2_REG_BASE + DWC2_FIFO_BASE + (_x) * DWC2_FIFO_SIZE)) enum @@ -127,7 +128,7 @@ static void bus_reset(uint8_t rhport) // 1. NAK for all OUT endpoints for(uint8_t n = 0; n < DWC2_EP_MAX; n++) { - out_ep[n].DOEPCTL |= DOEPCTL_SNAK; + out_ep[n].doepctl |= DOEPCTL_SNAK; } // 2. Un-mask interrupt bits @@ -193,10 +194,10 @@ static void bus_reset(uint8_t rhport) dwc2->dieptxf0 = (16 << TX0FD_Pos) | (DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx); // Fixed control EP0 size to 64 bytes - in_ep[0].DIEPCTL &= ~(0x03 << DIEPCTL_MPSIZ_Pos); + in_ep[0].diepctl &= ~(0x03 << DIEPCTL_MPSIZ_Pos); xfer_status[0][TUSB_DIR_OUT].max_size = xfer_status[0][TUSB_DIR_IN].max_size = 64; - out_ep[0].DOEPTSIZ |= (3 << DOEPTSIZ_STUPCNT_Pos); + out_ep[0].doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos); dwc2->gintmsk |= GINTMSK_OEPINT | GINTMSK_IEPINT; } @@ -290,17 +291,17 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c // IN and OUT endpoint xfers are interrupt-driven, we just schedule them here. if(dir == TUSB_DIR_IN) { // A full IN transfer (multiple packets, possibly) triggers XFRC. - in_ep[epnum].DIEPTSIZ = (num_packets << DIEPTSIZ_PKTCNT_Pos) | + in_ep[epnum].dieptsiz = (num_packets << DIEPTSIZ_PKTCNT_Pos) | ((total_bytes << DIEPTSIZ_XFRSIZ_Pos) & DIEPTSIZ_XFRSIZ_Msk); - in_ep[epnum].DIEPCTL |= DIEPCTL_EPENA | DIEPCTL_CNAK; + in_ep[epnum].diepctl |= DIEPCTL_EPENA | DIEPCTL_CNAK; // For ISO endpoint set correct odd/even bit for next frame. - if ((in_ep[epnum].DIEPCTL & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) + if ((in_ep[epnum].diepctl & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) { // Take odd/even bit from frame counter. uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos)); - in_ep[epnum].DIEPCTL |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk); + in_ep[epnum].diepctl |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk); } // Enable fifo empty interrupt only if there are something to put in the fifo. if(total_bytes != 0) { @@ -308,16 +309,16 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c } } else { // A full OUT transfer (multiple packets, possibly) triggers XFRC. - out_ep[epnum].DOEPTSIZ &= ~(DOEPTSIZ_PKTCNT_Msk | DOEPTSIZ_XFRSIZ); - out_ep[epnum].DOEPTSIZ |= (num_packets << DOEPTSIZ_PKTCNT_Pos) | + out_ep[epnum].doeptsiz &= ~(DOEPTSIZ_PKTCNT_Msk | DOEPTSIZ_XFRSIZ); + out_ep[epnum].doeptsiz |= (num_packets << DOEPTSIZ_PKTCNT_Pos) | ((total_bytes << DOEPTSIZ_XFRSIZ_Pos) & DOEPTSIZ_XFRSIZ_Msk); - out_ep[epnum].DOEPCTL |= DOEPCTL_EPENA | DOEPCTL_CNAK; - if ((out_ep[epnum].DOEPCTL & DOEPCTL_EPTYP) == DOEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) + out_ep[epnum].doepctl |= DOEPCTL_EPENA | DOEPCTL_CNAK; + if ((out_ep[epnum].doepctl & DOEPCTL_EPTYP) == DOEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) { // Take odd/even bit from frame counter. uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos)); - out_ep[epnum].DOEPCTL |= (odd_frame_now ? DOEPCTL_SD0PID_SEVNFRM_Msk : DOEPCTL_SODDFRM_Msk); + out_ep[epnum].doepctl |= (odd_frame_now ? DOEPCTL_SD0PID_SEVNFRM_Msk : DOEPCTL_SODDFRM_Msk); } } } @@ -403,12 +404,12 @@ void dcd_init (uint8_t rhport) void dcd_int_enable (uint8_t rhport) { - dcd_dwc2_int_enable(rhport); + dwc2_dcd_int_enable(rhport); } void dcd_int_disable (uint8_t rhport) { - dcd_dwc2_int_disable(rhport); + dwc2_dcd_int_disable(rhport); } void dcd_set_address (uint8_t rhport, uint8_t dev_addr) @@ -491,7 +492,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) dwc2->grxfsiz = sz; } - out_ep[epnum].DOEPCTL |= (1 << DOEPCTL_USBAEP_Pos) | + out_ep[epnum].doepctl |= (1 << DOEPCTL_USBAEP_Pos) | (desc_edpt->bmAttributes.xfer << DOEPCTL_EPTYP_Pos) | (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DOEPCTL_SD0PID_SEVNFRM : 0) | (xfer->max_size << DOEPCTL_MPSIZ_Pos); @@ -532,7 +533,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) // Both TXFD and TXSA are in unit of 32-bit words. dwc2->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | (DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx); - in_ep[epnum].DIEPCTL |= (1 << DIEPCTL_USBAEP_Pos) | + in_ep[epnum].diepctl |= (1 << DIEPCTL_USBAEP_Pos) | (epnum << DIEPCTL_TXFNUM_Pos) | (desc_edpt->bmAttributes.xfer << DIEPCTL_EPTYP_Pos) | (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DIEPCTL_SD0PID_SEVNFRM : 0) | @@ -559,11 +560,11 @@ void dcd_edpt_close_all (uint8_t rhport) for(uint8_t n = 1; n < DWC2_EP_MAX; n++) { // disable OUT endpoint - out_ep[n].DOEPCTL = 0; + out_ep[n].doepctl = 0; xfer_status[n][TUSB_DIR_OUT].max_size = 0; // disable IN endpoint - in_ep[n].DIEPCTL = 0; + in_ep[n].diepctl = 0; xfer_status[n][TUSB_DIR_IN].max_size = 0; } @@ -645,21 +646,21 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall) if ( dir == TUSB_DIR_IN ) { // Only disable currently enabled non-control endpoint - if ( (epnum == 0) || !(in_ep[epnum].DIEPCTL & DIEPCTL_EPENA) ) + if ( (epnum == 0) || !(in_ep[epnum].diepctl & DIEPCTL_EPENA) ) { - in_ep[epnum].DIEPCTL |= DIEPCTL_SNAK | (stall ? DIEPCTL_STALL : 0); + in_ep[epnum].diepctl |= DIEPCTL_SNAK | (stall ? DIEPCTL_STALL : 0); } else { // Stop transmitting packets and NAK IN xfers. - in_ep[epnum].DIEPCTL |= DIEPCTL_SNAK; - while ( (in_ep[epnum].DIEPINT & DIEPINT_INEPNE) == 0 ) {} + in_ep[epnum].diepctl |= DIEPCTL_SNAK; + while ( (in_ep[epnum].diepint & DIEPINT_INEPNE) == 0 ) {} // Disable the endpoint. - in_ep[epnum].DIEPCTL |= DIEPCTL_EPDIS | (stall ? DIEPCTL_STALL : 0); - while ( (in_ep[epnum].DIEPINT & DIEPINT_EPDISD_Msk) == 0 ) {} + in_ep[epnum].diepctl |= DIEPCTL_EPDIS | (stall ? DIEPCTL_STALL : 0); + while ( (in_ep[epnum].diepint & DIEPINT_EPDISD_Msk) == 0 ) {} - in_ep[epnum].DIEPINT = DIEPINT_EPDISD; + in_ep[epnum].diepint = DIEPINT_EPDISD; } // Flush the FIFO, and wait until we have confirmed it cleared. @@ -670,9 +671,9 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall) else { // Only disable currently enabled non-control endpoint - if ( (epnum == 0) || !(out_ep[epnum].DOEPCTL & DOEPCTL_EPENA) ) + if ( (epnum == 0) || !(out_ep[epnum].doepctl & DOEPCTL_EPENA) ) { - out_ep[epnum].DOEPCTL |= stall ? DOEPCTL_STALL : 0; + out_ep[epnum].doepctl |= stall ? DOEPCTL_STALL : 0; } else { @@ -684,10 +685,10 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall) while ( (dwc2->gintsts & GINTSTS_BOUTNAKEFF_Msk) == 0 ) {} // Ditto here- disable the endpoint. - out_ep[epnum].DOEPCTL |= DOEPCTL_EPDIS | (stall ? DOEPCTL_STALL : 0); - while ( (out_ep[epnum].DOEPINT & DOEPINT_EPDISD_Msk) == 0 ) {} + out_ep[epnum].doepctl |= DOEPCTL_EPDIS | (stall ? DOEPCTL_STALL : 0); + while ( (out_ep[epnum].doepint & DOEPINT_EPDISD_Msk) == 0 ) {} - out_ep[epnum].DOEPINT = DOEPINT_EPDISD; + out_ep[epnum].doepint = DOEPINT_EPDISD; // Allow other OUT endpoints to keep receiving. dwc2->dctl |= DCTL_CGONAK; @@ -742,13 +743,13 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) // Clear stall and reset data toggle if ( dir == TUSB_DIR_IN ) { - in_ep[epnum].DIEPCTL &= ~DIEPCTL_STALL; - in_ep[epnum].DIEPCTL |= DIEPCTL_SD0PID_SEVNFRM; + in_ep[epnum].diepctl &= ~DIEPCTL_STALL; + in_ep[epnum].diepctl |= DIEPCTL_SD0PID_SEVNFRM; } else { - out_ep[epnum].DOEPCTL &= ~DOEPCTL_STALL; - out_ep[epnum].DOEPCTL |= DOEPCTL_SD0PID_SEVNFRM; + out_ep[epnum].doepctl &= ~DOEPCTL_STALL; + out_ep[epnum].doepctl |= DOEPCTL_SD0PID_SEVNFRM; } } @@ -859,7 +860,7 @@ static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep) { // Truncate transfer length in case of short packet if(bcnt < xfer->max_size) { - xfer->total_len -= (out_ep[epnum].DOEPTSIZ & DOEPTSIZ_XFRSIZ_Msk) >> DOEPTSIZ_XFRSIZ_Pos; + xfer->total_len -= (out_ep[epnum].doeptsiz & DOEPTSIZ_XFRSIZ_Msk) >> DOEPTSIZ_XFRSIZ_Pos; if(epnum == 0) { xfer->total_len -= ep0_pending[TUSB_DIR_OUT]; ep0_pending[TUSB_DIR_OUT] = 0; @@ -872,7 +873,7 @@ static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep) { break; case 0x04: // Setup packet done (Interrupt) - out_ep[epnum].DOEPTSIZ |= (3 << DOEPTSIZ_STUPCNT_Pos); + out_ep[epnum].doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos); break; case 0x06: // Setup packet recvd @@ -899,16 +900,16 @@ static void handle_epout_ints (uint8_t rhport, dwc2_regs_t *dwc2, dwc2_epout_t * if ( dwc2->daint & (1 << (DAINT_OEPINT_Pos + n)) ) { // SETUP packet Setup Phase done. - if ( out_ep[n].DOEPINT & DOEPINT_STUP ) + if ( out_ep[n].doepint & DOEPINT_STUP ) { - out_ep[n].DOEPINT = DOEPINT_STUP; + out_ep[n].doepint = DOEPINT_STUP; dcd_event_setup_received(rhport, (uint8_t*) &_setup_packet[0], true); } // OUT XFER complete - if ( out_ep[n].DOEPINT & DOEPINT_XFRC ) + if ( out_ep[n].doepint & DOEPINT_XFRC ) { - out_ep[n].DOEPINT = DOEPINT_XFRC; + out_ep[n].doepint = DOEPINT_XFRC; // EP0 can only handle one packet if ( (n == 0) && ep0_pending[TUSB_DIR_OUT] ) @@ -935,9 +936,9 @@ static void handle_epin_ints(uint8_t rhport, dwc2_regs_t * dwc2, dwc2_epin_t * i if ( dwc2->daint & (1 << (DAINT_IEPINT_Pos + n)) ) { // IN XFER complete (entire xfer). - if ( in_ep[n].DIEPINT & DIEPINT_XFRC ) + if ( in_ep[n].diepint & DIEPINT_XFRC ) { - in_ep[n].DIEPINT = DIEPINT_XFRC; + in_ep[n].diepint = DIEPINT_XFRC; // EP0 can only handle one packet if((n == 0) && ep0_pending[TUSB_DIR_IN]) { @@ -949,26 +950,26 @@ static void handle_epin_ints(uint8_t rhport, dwc2_regs_t * dwc2, dwc2_epin_t * i } // XFER FIFO empty - if ( (in_ep[n].DIEPINT & DIEPINT_TXFE) && (dwc2->diepempmsk & (1 << n)) ) + if ( (in_ep[n].diepint & DIEPINT_TXFE) && (dwc2->diepempmsk & (1 << n)) ) { - // DIEPINT's TXFE bit is read-only, software cannot clear it. + // diepint's TXFE bit is read-only, software cannot clear it. // It will only be cleared by hardware when written bytes is more than // - 64 bytes or // - Half of TX FIFO size (configured by DIEPTXF) - uint16_t remaining_packets = (in_ep[n].DIEPTSIZ & DIEPTSIZ_PKTCNT_Msk) >> DIEPTSIZ_PKTCNT_Pos; + uint16_t remaining_packets = (in_ep[n].dieptsiz & DIEPTSIZ_PKTCNT_Msk) >> DIEPTSIZ_PKTCNT_Pos; // Process every single packet (only whole packets can be written to fifo) for(uint16_t i = 0; i < remaining_packets; i++) { - uint16_t const remaining_bytes = (in_ep[n].DIEPTSIZ & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos; + uint16_t const remaining_bytes = (in_ep[n].dieptsiz & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos; // Packet can not be larger than ep max size uint16_t const packet_size = tu_min16(remaining_bytes, xfer->max_size); // It's only possible to write full packets into FIFO. Therefore DTXFSTS register of current // EP has to be checked if the buffer can take another WHOLE packet - if(packet_size > ((in_ep[n].DTXFSTS & DTXFSTS_INEPTFSAV_Msk) << 2)) break; + if(packet_size > ((in_ep[n].dtxfsts & DTXFSTS_INEPTFSAV_Msk) << 2)) break; // Push packet to Tx-FIFO if (xfer->ff) @@ -986,7 +987,7 @@ static void handle_epin_ints(uint8_t rhport, dwc2_regs_t * dwc2, dwc2_epin_t * i } // Turn off TXFE if all bytes are written. - if (((in_ep[n].DIEPTSIZ & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos) == 0) + if (((in_ep[n].dieptsiz & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos) == 0) { dwc2->diepempmsk &= ~(1 << n); } diff --git a/src/portable/synopsys/dwc2/dwc2_esp32.h b/src/portable/synopsys/dwc2/dwc2_esp32.h index d73ec0504..b8a040041 100644 --- a/src/portable/synopsys/dwc2/dwc2_esp32.h +++ b/src/portable/synopsys/dwc2/dwc2_esp32.h @@ -50,13 +50,13 @@ static void dcd_int_handler_wrap(void* arg) dcd_int_handler(0); } -static inline void dcd_dwc2_int_enable (uint8_t rhport) +static inline void dwc2_dcd_int_enable (uint8_t rhport) { (void) rhport; esp_intr_alloc(ETS_USB_INTR_SOURCE, ESP_INTR_FLAG_LOWMED, dcd_int_handler_wrap, NULL, &usb_ih); } -static inline void dcd_dwc2_int_disable (uint8_t rhport) +static inline void dwc2_dcd_int_disable (uint8_t rhport) { (void) rhport; esp_intr_free(usb_ih); diff --git a/src/portable/synopsys/dwc2/dwc2_gd32.h b/src/portable/synopsys/dwc2/dwc2_gd32.h index f0c7cfb38..de3ccb3b0 100644 --- a/src/portable/synopsys/dwc2/dwc2_gd32.h +++ b/src/portable/synopsys/dwc2/dwc2_gd32.h @@ -55,14 +55,14 @@ static inline void __eclic_disable_interrupt (uint32_t irq){ } TU_ATTR_ALWAYS_INLINE -static inline void dcd_dwc2_int_enable(uint8_t rhport) +static inline void dwc2_dcd_int_enable(uint8_t rhport) { (void) rhport; __eclic_enable_interrupt(RHPORT_IRQn); } TU_ATTR_ALWAYS_INLINE -static inline void dcd_dwc2_int_disable (uint8_t rhport) +static inline void dwc2_dcd_int_disable (uint8_t rhport) { (void) rhport; __eclic_disable_interrupt(RHPORT_IRQn); diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h index 5a0071563..236936d66 100644 --- a/src/portable/synopsys/dwc2/dwc2_stm32.h +++ b/src/portable/synopsys/dwc2/dwc2_stm32.h @@ -91,14 +91,14 @@ extern uint32_t SystemCoreClock; TU_ATTR_ALWAYS_INLINE -static inline void dcd_dwc2_int_enable(uint8_t rhport) +static inline void dwc2_dcd_int_enable(uint8_t rhport) { (void) rhport; NVIC_EnableIRQ(RHPORT_IRQn); } TU_ATTR_ALWAYS_INLINE -static inline void dcd_dwc2_int_disable (uint8_t rhport) +static inline void dwc2_dcd_int_disable (uint8_t rhport) { (void) rhport; NVIC_DisableIRQ(RHPORT_IRQn); diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index 23d724366..8f011d642 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -40,16 +40,41 @@ typedef struct // Host Channel typedef struct { - volatile uint32_t hcchar; // 500 + 20n Host Channel Characteristics Register - volatile uint32_t hcsplt; // 504 + 20n Host Channel Split Control Register - volatile uint32_t hcint; // 508 + 20n Host Channel Interrupt Register - volatile uint32_t hcintmsk; // 50C + 20n Host Channel Interrupt Mask Register - volatile uint32_t hctsiz; // 510 + 20n Host Channel Transfer Size Register - volatile uint32_t hcdma; // 514 + 20n Host Channel DMA Address Register - uint32_t reserved518; // 518 + 20n - volatile uint32_t hcdmab; // 51C + 20n Host Channel DMA Address Register + volatile uint32_t hcchar; // 500 + 20*ch Host Channel Characteristics Register + volatile uint32_t hcsplt; // 504 + 20*ch Host Channel Split Control Register + volatile uint32_t hcint; // 508 + 20*ch Host Channel Interrupt Register + volatile uint32_t hcintmsk; // 50C + 20*ch Host Channel Interrupt Mask Register + volatile uint32_t hctsiz; // 510 + 20*ch Host Channel Transfer Size Register + volatile uint32_t hcdma; // 514 + 20*ch Host Channel DMA Address Register + uint32_t reserved518; // 518 + 20*ch + volatile uint32_t hcdmab; // 51C + 20*ch Host Channel DMA Address Register } dwc2_channel_t; +// Endpoint IN +typedef struct +{ + volatile uint32_t diepctl; // 900 + 20*ep Device IN Endpoint Control + uint32_t reserved04; // 904 + volatile uint32_t diepint; // 908 + 20*ep Device IN Endpoint Interrupt + uint32_t reserved0c; // 90C + volatile uint32_t dieptsiz; // 910 + 20*ep Device IN Endpoint Transfer Size + volatile uint32_t diepdma; // 914 + 20*ep Device IN Endpoint DMA Address + volatile uint32_t dtxfsts; // 918 + 20*ep Device IN Endpoint Tx FIFO Status + uint32_t reserved1c; // 91C +} dwc2_epin_t; + +// Endpoint OUT +typedef struct +{ + volatile uint32_t doepctl; // B00 + 20*ep Device OUT Endpoint Control + uint32_t reserved04; // B04 + volatile uint32_t doepint; // B08 + 20*ep Device OUT Endpoint Interrupt + uint32_t reserved0c; // B0C + volatile uint32_t doeptsiz; // B10 + 20*ep Device OUT Endpoint Transfer Size + volatile uint32_t doepdma; // B14 + 20*ep Device OUT Endpoint DMA Address + uint32_t reserved18[2]; // B18..B1C +} dwc2_epout_t; + typedef struct { //------------- Core Global -------------// @@ -123,48 +148,22 @@ union { volatile uint32_t dvbuspulse; // 82C Device VBUS Pulsing Time Register volatile uint32_t dthrctl; // 830 Device threshold Control volatile uint32_t diepempmsk; // 834 Device IN Endpoint FIFO Empty Interrupt Mask - volatile uint32_t deachint; // 838 Device Each Endpoint Interrupt volatile uint32_t deachmsk; // 83C Device Each Endpoint Interrupt msk volatile uint32_t diepeachmsk[16]; // 840..87C Device Each IN Endpoint mask volatile uint32_t doepeachmsk[16]; // 880..8BC Device Each OUT Endpoint mask uint32_t reserved8c0[16]; // 8C0..8FC - //------------- Device IN Endpoint -------------// - - - //------------- Device OUT Endpoint -------------// + //------------- Device Endpoint -------------// + dwc2_epin_t epin[16]; // 900..AFC IN Endpoints + dwc2_epout_t epout[16]; // B00..CFC OUT Endpoints } dwc2_regs_t; -TU_VERIFY_STATIC(offsetof(dwc2_regs_t, hcfg ) == 0x0400, "incorrect size"); -TU_VERIFY_STATIC(offsetof(dwc2_regs_t, channel) == 0x0500, "incorrect size"); -TU_VERIFY_STATIC(offsetof(dwc2_regs_t, dcfg ) == 0x0800, "incorrect size"); - -// Endpoint IN -typedef struct -{ - volatile uint32_t DIEPCTL; // dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ - uint32_t Reserved04; // Reserved 900h + (ep_num * 20h) + 04h */ - volatile uint32_t DIEPINT; // dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ - uint32_t Reserved0C; // Reserved 900h + (ep_num * 20h) + 0Ch */ - volatile uint32_t DIEPTSIZ; // IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ - volatile uint32_t DIEPDMA; // IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ - volatile uint32_t DTXFSTS; // IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ - uint32_t Reserved18; // Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ -} dwc2_epin_t; - -// Endpoint OUT -typedef struct -{ - volatile uint32_t DOEPCTL; // dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ - uint32_t Reserved04; // Reserved B00h + (ep_num * 20h) + 04h */ - volatile uint32_t DOEPINT; // dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ - uint32_t Reserved0C; // Reserved B00h + (ep_num * 20h) + 0Ch */ - volatile uint32_t DOEPTSIZ; // dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ - volatile uint32_t DOEPDMA; // dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ - uint32_t Reserved18[2]; // Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ -} dwc2_epout_t; - +TU_VERIFY_STATIC(offsetof(dwc2_regs_t, hcfg ) == 0x400, "incorrect size"); +TU_VERIFY_STATIC(offsetof(dwc2_regs_t, channel) == 0x500, "incorrect size"); +TU_VERIFY_STATIC(offsetof(dwc2_regs_t, dcfg ) == 0x800, "incorrect size"); +TU_VERIFY_STATIC(offsetof(dwc2_regs_t, epin ) == 0x900, "incorrect size"); +TU_VERIFY_STATIC(offsetof(dwc2_regs_t, epout ) == 0xB00, "incorrect size"); //--------------------------------------------------------------------+ // Register Base Address -- cgit v1.3.1 From 5e1a0318004d95c6663e494ade76a0581594391e Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 26 Oct 2021 12:22:07 +0700 Subject: complete dwc2 regs struct --- src/portable/synopsys/dwc2/dcd_dwc2.c | 16 ++-- src/portable/synopsys/dwc2/dwc2_type.h | 140 ++++++++++++++++++--------------- 2 files changed, 82 insertions(+), 74 deletions(-) diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 468ce520f..718773a00 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -30,8 +30,6 @@ #include "tusb_option.h" #include "device/dcd_attr.h" - - #if TUSB_OPT_DEVICE_ENABLED && \ ( defined(DCD_ATTR_DWC2_STM32) || TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3, OPT_MCU_GD32VF103) ) @@ -84,7 +82,7 @@ xfer_ctl_t xfer_status[DWC2_EP_MAX][2]; // EP0 transfers are limited to 1 packet - larger sizes has to be split static uint16_t ep0_pending[2]; // Index determines direction as tusb_dir_t type -// TX FIFO RAM allocation so far in words - RX FIFO size is readily available from core->GRXFSIZ +// TX FIFO RAM allocation so far in words - RX FIFO size is readily available from dwc2->grxfsiz static uint16_t _allocated_fifo_words_tx; // TX FIFO size in words (IN EPs) static bool _out_ep_closed; // Flag to check if RX FIFO size needs an update (reduce its size) @@ -98,7 +96,7 @@ static void update_grxfsiz(uint8_t rhport) { (void) rhport; - dwc2_regs_t * core = DWC2_REG(rhport); + dwc2_regs_t * dwc2 = DWC2_REG(rhport); // Determine largest EP size for RX FIFO uint16_t max_epsize = 0; @@ -108,7 +106,7 @@ static void update_grxfsiz(uint8_t rhport) } // Update size of RX FIFO - core->grxfsiz = calc_rx_ff_size(max_epsize); + dwc2->grxfsiz = calc_rx_ff_size(max_epsize); } // Setup the control endpoint 0. @@ -340,7 +338,7 @@ void dcd_init (uint8_t rhport) // On selected MCUs HS port1 can be used with external PHY via ULPI interface #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED // deactivate internal PHY - dwc2->gccfg &= ~GCCFG_PWRDWN; + dwc2->stm32_gccfg &= ~GCCFG_PWRDWN; // Init The UTMI Interface dwc2->gusbcfg &= ~(GUSBCFG_TSDPS | GUSBCFG_ULPIFSLS | GUSBCFG_PHYSEL); @@ -356,7 +354,7 @@ void dcd_init (uint8_t rhport) // Select UTMI Interface dwc2->gusbcfg &= ~GUSBCFG_ULPI_UTMI_SEL; - dwc2->gccfg |= GCCFG_PHYHSEN; + dwc2->stm32_gccfg |= GCCFG_PHYHSEN; // Enables control of a High Speed USB PHY USB_HS_PHYCInit(); @@ -374,7 +372,7 @@ void dcd_init (uint8_t rhport) while ((dwc2->grstctl & GRSTCTL_CSRST) == GRSTCTL_CSRST) {} // Restart PHY clock - *((volatile uint32_t *)(DWC2_REG_BASE + DWC2_PCGCCTL_BASE)) = 0; + dwc2->pcgctrl = 0; // Clear all interrupts dwc2->gintsts |= dwc2->gintsts; @@ -391,7 +389,7 @@ void dcd_init (uint8_t rhport) set_speed(rhport, TUD_OPT_HIGH_SPEED ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL); // Enable internal USB transceiver, unless using HS core (port 1) with external PHY. - if (!(rhport == 1 && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED))) dwc2->gccfg |= GCCFG_PWRDWN; + if (!(rhport == 1 && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED))) dwc2->stm32_gccfg |= GCCFG_PWRDWN; dwc2->gintmsk |= GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_USBSUSPM | GINTMSK_WUIM | GINTMSK_RXFLVLM; diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index 8f011d642..95d043b86 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -78,42 +78,42 @@ typedef struct typedef struct { //------------- Core Global -------------// - volatile uint32_t gotgctl; // 000 OTG Control and Status Register - volatile uint32_t gotgint; // 004 OTG Interrupt Register - volatile uint32_t gahbcfg; // 008 AHB Configuration Register - volatile uint32_t gusbcfg; // 00c USB Configuration Register - volatile uint32_t grstctl; // 010 Reset Register - volatile uint32_t gintsts; // 014 Interrupt Register - volatile uint32_t gintmsk; // 018 Interrupt Mask Register - volatile uint32_t grxstsr; // 01c Receive Status Debug Read Register - volatile uint32_t grxstsp; // 020 Receive Status Read/Pop Register - volatile uint32_t grxfsiz; // 024 Receive FIFO Size Register + volatile uint32_t gotgctl; // 000 OTG Control and Status Register + volatile uint32_t gotgint; // 004 OTG Interrupt Register + volatile uint32_t gahbcfg; // 008 AHB Configuration Register + volatile uint32_t gusbcfg; // 00c USB Configuration Register + volatile uint32_t grstctl; // 010 Reset Register + volatile uint32_t gintsts; // 014 Interrupt Register + volatile uint32_t gintmsk; // 018 Interrupt Mask Register + volatile uint32_t grxstsr; // 01c Receive Status Debug Read Register + volatile uint32_t grxstsp; // 020 Receive Status Read/Pop Register + volatile uint32_t grxfsiz; // 024 Receive FIFO Size Register union { - volatile uint32_t dieptxf0; // 028 EP0 Tx FIFO Size Register - volatile uint32_t gnptxfsiz; // 028 Non-periodic Transmit FIFO Size Register + volatile uint32_t dieptxf0; // 028 EP0 Tx FIFO Size Register + volatile uint32_t gnptxfsiz; // 028 Non-periodic Transmit FIFO Size Register }; - volatile uint32_t gnptxsts; // 02c Non-periodic Transmit FIFO/Queue Status Register - volatile uint32_t gi2cctl; // 030 I2C Address Register - volatile uint32_t gpvndctl; // 034 PHY Vendor Control Register + volatile uint32_t gnptxsts; // 02c Non-periodic Transmit FIFO/Queue Status Register + volatile uint32_t gi2cctl; // 030 I2C Address Register + volatile uint32_t gpvndctl; // 034 PHY Vendor Control Register union { - volatile uint32_t ggpio; // 038 General Purpose IO Register - volatile uint32_t gccfg; // 038 STM32 General Core Configuration + volatile uint32_t ggpio; // 038 General Purpose IO Register + volatile uint32_t stm32_gccfg; // 038 STM32 General Core Configuration }; - volatile uint32_t guid; // 03C User ID Register - volatile uint32_t gsnpsid; // 040 Synopsys ID Register - volatile uint32_t ghwcfg1; // 044 User Hardware Configuration 1 Register - volatile uint32_t ghwcfg2; // 048 User Hardware Configuration 2 Register - volatile uint32_t ghwcfg3; // 04C User Hardware Configuration 3 Register - volatile uint32_t ghwcfg4; // 050 User Hardware Configuration 4 Register - volatile uint32_t glpmcfg; // 054 Core LPM Configuration Register - volatile uint32_t gpwrdn; // 058 Power Down Register - volatile uint32_t gdfifocfg; // 05C DFIFO Software Configuration Register - volatile uint32_t gadpctl; // 060 ADP Timer, Control and Status Register - - uint32_t reserved64[39]; // 064..0FF - volatile uint32_t hptxfsiz; // 100 Host Periodic Tx FIFO Size Register - volatile uint32_t dieptxf[15]; // 104..13C Device Periodic Transmit FIFO Size Register - uint32_t reserved140[176]; // 140..3FC + volatile uint32_t guid; // 03C User ID Register + volatile uint32_t gsnpsid; // 040 Synopsys ID Register + volatile uint32_t ghwcfg1; // 044 User Hardware Configuration 1 Register + volatile uint32_t ghwcfg2; // 048 User Hardware Configuration 2 Register + volatile uint32_t ghwcfg3; // 04C User Hardware Configuration 3 Register + volatile uint32_t ghwcfg4; // 050 User Hardware Configuration 4 Register + volatile uint32_t glpmcfg; // 054 Core LPM Configuration Register + volatile uint32_t gpwrdn; // 058 Power Down Register + volatile uint32_t gdfifocfg; // 05C DFIFO Software Configuration Register + volatile uint32_t gadpctl; // 060 ADP Timer, Control and Status Register + + uint32_t reserved64[39]; // 064..0FF + volatile uint32_t hptxfsiz; // 100 Host Periodic Tx FIFO Size Register + volatile uint32_t dieptxf[15]; // 104..13C Device Periodic Transmit FIFO Size Register + uint32_t reserved140[176]; // 140..3FF //------------- Host -------------// volatile uint32_t hcfg; // 400 Host Configuration Register @@ -124,46 +124,56 @@ union { volatile uint32_t haint; // 414 Host All Channels Interrupt Register volatile uint32_t haintmsk; // 418 Host All Channels Interrupt Mask volatile uint32_t hflbaddr; // 41C Host Frame List Base Address Register - uint32_t reserved420[8]; // 420..43C + uint32_t reserved420[8]; // 420..43F volatile uint32_t hprt; // 440 Host Port Control and Status - uint32_t reserved444[47]; // 444..4FC + uint32_t reserved444[47]; // 444..4FF //------------- Host Channel -------------// - dwc2_channel_t channel[16]; // 500..6FC Host Channels 0-15 - - uint32_t reserved700[64]; // 700..7FC - - //------------- Device -------------// - volatile uint32_t dcfg; // 800 Device Configuration Register - volatile uint32_t dctl; // 804 Device Control Register - volatile uint32_t dsts; // 808 Device Status Register (RO) - uint32_t reserved80c; // 80C - volatile uint32_t diepmsk; // 810 Device IN Endpoint Interrupt Mask - volatile uint32_t doepmsk; // 814 Device OUT Endpoint Interrupt Mask - volatile uint32_t daint; // 818 Device All Endpoints Interrupt - volatile uint32_t daintmsk; // 81C Device All Endpoints Interrupt Mask - volatile uint32_t dtknqr1; // 820 Device IN token sequence learning queue read register1 - volatile uint32_t dtknqr2; // 824 Device IN token sequence learning queue read register2 - volatile uint32_t dvbusdis; // 828 Device VBUS Discharge Time Register - volatile uint32_t dvbuspulse; // 82C Device VBUS Pulsing Time Register - volatile uint32_t dthrctl; // 830 Device threshold Control - volatile uint32_t diepempmsk; // 834 Device IN Endpoint FIFO Empty Interrupt Mask - volatile uint32_t deachint; // 838 Device Each Endpoint Interrupt - volatile uint32_t deachmsk; // 83C Device Each Endpoint Interrupt msk - volatile uint32_t diepeachmsk[16]; // 840..87C Device Each IN Endpoint mask - volatile uint32_t doepeachmsk[16]; // 880..8BC Device Each OUT Endpoint mask - uint32_t reserved8c0[16]; // 8C0..8FC + dwc2_channel_t channel[16]; // 500..6FF Host Channels 0-15 + uint32_t reserved700[64]; // 700..7FF + + //------------- Device -------------// + volatile uint32_t dcfg; // 800 Device Configuration Register + volatile uint32_t dctl; // 804 Device Control Register + volatile uint32_t dsts; // 808 Device Status Register (RO) + uint32_t reserved80c; // 80C + volatile uint32_t diepmsk; // 810 Device IN Endpoint Interrupt Mask + volatile uint32_t doepmsk; // 814 Device OUT Endpoint Interrupt Mask + volatile uint32_t daint; // 818 Device All Endpoints Interrupt + volatile uint32_t daintmsk; // 81C Device All Endpoints Interrupt Mask + volatile uint32_t dtknqr1; // 820 Device IN token sequence learning queue read register1 + volatile uint32_t dtknqr2; // 824 Device IN token sequence learning queue read register2 + volatile uint32_t dvbusdis; // 828 Device VBUS Discharge Time Register + volatile uint32_t dvbuspulse; // 82C Device VBUS Pulsing Time Register + volatile uint32_t dthrctl; // 830 Device threshold Control + volatile uint32_t diepempmsk; // 834 Device IN Endpoint FIFO Empty Interrupt Mask + volatile uint32_t deachint; // 838 Device Each Endpoint Interrupt + volatile uint32_t deachmsk; // 83C Device Each Endpoint Interrupt msk + volatile uint32_t diepeachmsk[16]; // 840..87C Device Each IN Endpoint mask + volatile uint32_t doepeachmsk[16]; // 880..8BF Device Each OUT Endpoint mask + uint32_t reserved8c0[16]; // 8C0..8FF //------------- Device Endpoint -------------// - dwc2_epin_t epin[16]; // 900..AFC IN Endpoints - dwc2_epout_t epout[16]; // B00..CFC OUT Endpoints + dwc2_epin_t epin[16]; // 900..AFF IN Endpoints + dwc2_epout_t epout[16]; // B00..CFF OUT Endpoints + uint32_t reservedd00[64]; // D00..DFF + + //------------- Power Clock -------------// + volatile uint32_t pcgctrl; // E00 Power and Clock Gating Control + volatile uint32_t pcgcctl1; // E04 + uint32_t reservede08[126]; // E08..FFF + + //------------- FIFOs -------------// + volatile uint32_t fifo[16][0x400]; // 1000..FFFF Endpoint FIFO } dwc2_regs_t; -TU_VERIFY_STATIC(offsetof(dwc2_regs_t, hcfg ) == 0x400, "incorrect size"); -TU_VERIFY_STATIC(offsetof(dwc2_regs_t, channel) == 0x500, "incorrect size"); -TU_VERIFY_STATIC(offsetof(dwc2_regs_t, dcfg ) == 0x800, "incorrect size"); -TU_VERIFY_STATIC(offsetof(dwc2_regs_t, epin ) == 0x900, "incorrect size"); -TU_VERIFY_STATIC(offsetof(dwc2_regs_t, epout ) == 0xB00, "incorrect size"); +TU_VERIFY_STATIC(offsetof(dwc2_regs_t, hcfg ) == 0x0400, "incorrect size"); +TU_VERIFY_STATIC(offsetof(dwc2_regs_t, channel) == 0x0500, "incorrect size"); +TU_VERIFY_STATIC(offsetof(dwc2_regs_t, dcfg ) == 0x0800, "incorrect size"); +TU_VERIFY_STATIC(offsetof(dwc2_regs_t, epin ) == 0x0900, "incorrect size"); +TU_VERIFY_STATIC(offsetof(dwc2_regs_t, epout ) == 0x0B00, "incorrect size"); +TU_VERIFY_STATIC(offsetof(dwc2_regs_t, pcgctrl) == 0x0E00, "incorrect size"); +TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); //--------------------------------------------------------------------+ // Register Base Address -- cgit v1.3.1 From 34844c90610763a91c421bc889ffe4a9d988e14a Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 26 Oct 2021 12:53:29 +0700 Subject: use dwc2->fifo[] --- src/portable/synopsys/dwc2/dcd_dwc2.c | 14 ++++++++------ src/portable/synopsys/dwc2/dwc2_type.h | 1 + 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 718773a00..1909f45fd 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -53,7 +53,6 @@ #define DWC2_REG(_port) ((dwc2_regs_t*) DWC2_REG_BASE) #define EPIN_REG(_port) (DWC2_REG(_port)->epin) #define EPOUT_REG(_port) (DWC2_REG(_port)->epout) -#define FIFO_BASE(_port, _x) ((volatile uint32_t*) (DWC2_REG_BASE + DWC2_FIFO_BASE + (_x) * DWC2_FIFO_SIZE)) enum { @@ -758,7 +757,8 @@ static void read_fifo_packet(uint8_t rhport, uint8_t * dst, uint16_t len) { (void) rhport; - volatile uint32_t * rx_fifo = FIFO_BASE(rhport, 0); + dwc2_regs_t * dwc2 = DWC2_REG(rhport); + volatile uint32_t * rx_fifo = dwc2->fifo[0]; // Reading full available 32 bit words from fifo uint16_t full_words = len >> 2; @@ -794,7 +794,8 @@ static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t * src, u { (void) rhport; - volatile uint32_t * tx_fifo = FIFO_BASE(rhport, fifo_num); + dwc2_regs_t * dwc2 = DWC2_REG(rhport); + volatile uint32_t * tx_fifo = dwc2->fifo[fifo_num]; // Pushing full available 32 bit words to fifo uint16_t full_words = len >> 2; @@ -822,9 +823,10 @@ static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t * src, u } } -static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep) { +static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep) +{ dwc2_regs_t * dwc2 = DWC2_REG(rhport); - volatile uint32_t * rx_fifo = FIFO_BASE(rhport, 0); + volatile uint32_t * rx_fifo = dwc2->fifo[0]; // Pop control word off FIFO uint32_t ctl_word = dwc2->grxstsp; @@ -972,7 +974,7 @@ static void handle_epin_ints(uint8_t rhport, dwc2_regs_t * dwc2, dwc2_epin_t * i // Push packet to Tx-FIFO if (xfer->ff) { - volatile uint32_t * tx_fifo = FIFO_BASE(rhport, n); + volatile uint32_t * tx_fifo = dwc2->fifo[n]; tu_fifo_read_n_const_addr_full_words(xfer->ff, (void *)(uintptr_t) tx_fifo, packet_size); } else diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index 95d043b86..5669aa88d 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -164,6 +164,7 @@ union { uint32_t reservede08[126]; // E08..FFF //------------- FIFOs -------------// + // Word-accessed only using first pointer since it auto shift volatile uint32_t fifo[16][0x400]; // 1000..FFFF Endpoint FIFO } dwc2_regs_t; -- cgit v1.3.1 From e7655a75673fd444f39185feb4a9a0edf8ac07fe Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 26 Oct 2021 13:02:26 +0700 Subject: update the access epout --- src/portable/synopsys/dwc2/dcd_dwc2.c | 85 +++++++++++++++++------------------ 1 file changed, 41 insertions(+), 44 deletions(-) diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 1909f45fd..11040a6cd 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -52,7 +52,6 @@ #define DWC2_REG(_port) ((dwc2_regs_t*) DWC2_REG_BASE) #define EPIN_REG(_port) (DWC2_REG(_port)->epin) -#define EPOUT_REG(_port) (DWC2_REG(_port)->epout) enum { @@ -114,8 +113,6 @@ static void bus_reset(uint8_t rhport) (void) rhport; dwc2_regs_t * dwc2 = DWC2_REG(rhport); - dwc2_epout_t * out_ep = EPOUT_REG(rhport); - dwc2_epin_t * in_ep = EPIN_REG(rhport); tu_memclr(xfer_status, sizeof(xfer_status)); _out_ep_closed = false; @@ -125,7 +122,7 @@ static void bus_reset(uint8_t rhport) // 1. NAK for all OUT endpoints for(uint8_t n = 0; n < DWC2_EP_MAX; n++) { - out_ep[n].doepctl |= DOEPCTL_SNAK; + dwc2->epout[n].doepctl |= DOEPCTL_SNAK; } // 2. Un-mask interrupt bits @@ -191,10 +188,10 @@ static void bus_reset(uint8_t rhport) dwc2->dieptxf0 = (16 << TX0FD_Pos) | (DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx); // Fixed control EP0 size to 64 bytes - in_ep[0].diepctl &= ~(0x03 << DIEPCTL_MPSIZ_Pos); + dwc2->epin[0].diepctl &= ~(0x03 << DIEPCTL_MPSIZ_Pos); xfer_status[0][TUSB_DIR_OUT].max_size = xfer_status[0][TUSB_DIR_IN].max_size = 64; - out_ep[0].doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos); + dwc2->epout[0].doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos); dwc2->gintmsk |= GINTMSK_OEPINT | GINTMSK_IEPINT; } @@ -274,48 +271,52 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c (void) rhport; dwc2_regs_t * dwc2 = DWC2_REG(rhport); - dwc2_epout_t * out_ep = EPOUT_REG(rhport); dwc2_epin_t * in_ep = EPIN_REG(rhport); // EP0 is limited to one packet each xfer // We use multiple transaction of xfer->max_size length to get a whole transfer done - if(epnum == 0) { - xfer_ctl_t * const xfer = XFER_CTL_BASE(epnum, dir); + if ( epnum == 0 ) + { + xfer_ctl_t *const xfer = XFER_CTL_BASE(epnum, dir); total_bytes = tu_min16(ep0_pending[dir], xfer->max_size); ep0_pending[dir] -= total_bytes; } // IN and OUT endpoint xfers are interrupt-driven, we just schedule them here. - if(dir == TUSB_DIR_IN) { + if ( dir == TUSB_DIR_IN ) + { // A full IN transfer (multiple packets, possibly) triggers XFRC. in_ep[epnum].dieptsiz = (num_packets << DIEPTSIZ_PKTCNT_Pos) | - ((total_bytes << DIEPTSIZ_XFRSIZ_Pos) & DIEPTSIZ_XFRSIZ_Msk); + ((total_bytes << DIEPTSIZ_XFRSIZ_Pos) & DIEPTSIZ_XFRSIZ_Msk); in_ep[epnum].diepctl |= DIEPCTL_EPENA | DIEPCTL_CNAK; // For ISO endpoint set correct odd/even bit for next frame. - if ((in_ep[epnum].diepctl & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) + if ( (in_ep[epnum].diepctl & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1 ) { // Take odd/even bit from frame counter. uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos)); in_ep[epnum].diepctl |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk); } // Enable fifo empty interrupt only if there are something to put in the fifo. - if(total_bytes != 0) { + if ( total_bytes != 0 ) + { dwc2->diepempmsk |= (1 << epnum); } - } else { + } + else + { // A full OUT transfer (multiple packets, possibly) triggers XFRC. - out_ep[epnum].doeptsiz &= ~(DOEPTSIZ_PKTCNT_Msk | DOEPTSIZ_XFRSIZ); - out_ep[epnum].doeptsiz |= (num_packets << DOEPTSIZ_PKTCNT_Pos) | - ((total_bytes << DOEPTSIZ_XFRSIZ_Pos) & DOEPTSIZ_XFRSIZ_Msk); + dwc2->epout[epnum].doeptsiz &= ~(DOEPTSIZ_PKTCNT_Msk | DOEPTSIZ_XFRSIZ); + dwc2->epout[epnum].doeptsiz |= (num_packets << DOEPTSIZ_PKTCNT_Pos) | + ((total_bytes << DOEPTSIZ_XFRSIZ_Pos) & DOEPTSIZ_XFRSIZ_Msk); - out_ep[epnum].doepctl |= DOEPCTL_EPENA | DOEPCTL_CNAK; - if ((out_ep[epnum].doepctl & DOEPCTL_EPTYP) == DOEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) + dwc2->epout[epnum].doepctl |= DOEPCTL_EPENA | DOEPCTL_CNAK; + if ( (dwc2->epout[epnum].doepctl & DOEPCTL_EPTYP) == DOEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1 ) { // Take odd/even bit from frame counter. uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos)); - out_ep[epnum].doepctl |= (odd_frame_now ? DOEPCTL_SD0PID_SEVNFRM_Msk : DOEPCTL_SODDFRM_Msk); + dwc2->epout[epnum].doepctl |= (odd_frame_now ? DOEPCTL_SD0PID_SEVNFRM_Msk : DOEPCTL_SODDFRM_Msk); } } } @@ -461,7 +462,6 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) (void) rhport; dwc2_regs_t * dwc2 = DWC2_REG(rhport); - dwc2_epout_t * out_ep = EPOUT_REG(rhport); dwc2_epin_t * in_ep = EPIN_REG(rhport); uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress); @@ -489,7 +489,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) dwc2->grxfsiz = sz; } - out_ep[epnum].doepctl |= (1 << DOEPCTL_USBAEP_Pos) | + dwc2->epout[epnum].doepctl |= (1 << DOEPCTL_USBAEP_Pos) | (desc_edpt->bmAttributes.xfer << DOEPCTL_EPTYP_Pos) | (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DOEPCTL_SD0PID_SEVNFRM : 0) | (xfer->max_size << DOEPCTL_MPSIZ_Pos); @@ -548,7 +548,6 @@ void dcd_edpt_close_all (uint8_t rhport) (void) rhport; dwc2_regs_t * dwc2 = DWC2_REG(rhport); - dwc2_epout_t * out_ep = EPOUT_REG(rhport); dwc2_epin_t * in_ep = EPIN_REG(rhport); // Disable non-control interrupt @@ -557,7 +556,7 @@ void dcd_edpt_close_all (uint8_t rhport) for(uint8_t n = 1; n < DWC2_EP_MAX; n++) { // disable OUT endpoint - out_ep[n].doepctl = 0; + dwc2->epout[n].doepctl = 0; xfer_status[n][TUSB_DIR_OUT].max_size = 0; // disable IN endpoint @@ -634,7 +633,6 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall) (void) rhport; dwc2_regs_t * dwc2 = DWC2_REG(rhport); - dwc2_epout_t * out_ep = EPOUT_REG(rhport); dwc2_epin_t * in_ep = EPIN_REG(rhport); uint8_t const epnum = tu_edpt_number(ep_addr); @@ -668,9 +666,9 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall) else { // Only disable currently enabled non-control endpoint - if ( (epnum == 0) || !(out_ep[epnum].doepctl & DOEPCTL_EPENA) ) + if ( (epnum == 0) || !(dwc2->epout[epnum].doepctl & DOEPCTL_EPENA) ) { - out_ep[epnum].doepctl |= stall ? DOEPCTL_STALL : 0; + dwc2->epout[epnum].doepctl |= stall ? DOEPCTL_STALL : 0; } else { @@ -682,10 +680,10 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall) while ( (dwc2->gintsts & GINTSTS_BOUTNAKEFF_Msk) == 0 ) {} // Ditto here- disable the endpoint. - out_ep[epnum].doepctl |= DOEPCTL_EPDIS | (stall ? DOEPCTL_STALL : 0); - while ( (out_ep[epnum].doepint & DOEPINT_EPDISD_Msk) == 0 ) {} + dwc2->epout[epnum].doepctl |= DOEPCTL_EPDIS | (stall ? DOEPCTL_STALL : 0); + while ( (dwc2->epout[epnum].doepint & DOEPINT_EPDISD_Msk) == 0 ) {} - out_ep[epnum].doepint = DOEPINT_EPDISD; + dwc2->epout[epnum].doepint = DOEPINT_EPDISD; // Allow other OUT endpoints to keep receiving. dwc2->dctl |= DCTL_CGONAK; @@ -731,7 +729,7 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) { (void) rhport; - dwc2_epout_t * out_ep = EPOUT_REG(rhport); + dwc2_regs_t * dwc2 = DWC2_REG(rhport); dwc2_epin_t * in_ep = EPIN_REG(rhport); uint8_t const epnum = tu_edpt_number(ep_addr); @@ -745,8 +743,8 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) } else { - out_ep[epnum].doepctl &= ~DOEPCTL_STALL; - out_ep[epnum].doepctl |= DOEPCTL_SD0PID_SEVNFRM; + dwc2->epout[epnum].doepctl &= ~DOEPCTL_STALL; + dwc2->epout[epnum].doepctl |= DOEPCTL_SD0PID_SEVNFRM; } } @@ -823,7 +821,7 @@ static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t * src, u } } -static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep) +static void handle_rxflvl_ints(uint8_t rhport) { dwc2_regs_t * dwc2 = DWC2_REG(rhport); volatile uint32_t * rx_fifo = dwc2->fifo[0]; @@ -860,7 +858,7 @@ static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep) // Truncate transfer length in case of short packet if(bcnt < xfer->max_size) { - xfer->total_len -= (out_ep[epnum].doeptsiz & DOEPTSIZ_XFRSIZ_Msk) >> DOEPTSIZ_XFRSIZ_Pos; + xfer->total_len -= (dwc2->epout[epnum].doeptsiz & DOEPTSIZ_XFRSIZ_Msk) >> DOEPTSIZ_XFRSIZ_Pos; if(epnum == 0) { xfer->total_len -= ep0_pending[TUSB_DIR_OUT]; ep0_pending[TUSB_DIR_OUT] = 0; @@ -873,7 +871,7 @@ static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep) break; case 0x04: // Setup packet done (Interrupt) - out_ep[epnum].doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos); + dwc2->epout[epnum].doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos); break; case 0x06: // Setup packet recvd @@ -889,7 +887,7 @@ static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep) } } -static void handle_epout_ints (uint8_t rhport, dwc2_regs_t *dwc2, dwc2_epout_t *out_ep) +static void handle_epout_ints (uint8_t rhport, dwc2_regs_t *dwc2) { // DAINT for a given EP clears when DOEPINTx is cleared. // OEPINT will be cleared when DAINT's out bits are cleared. @@ -900,16 +898,16 @@ static void handle_epout_ints (uint8_t rhport, dwc2_regs_t *dwc2, dwc2_epout_t * if ( dwc2->daint & (1 << (DAINT_OEPINT_Pos + n)) ) { // SETUP packet Setup Phase done. - if ( out_ep[n].doepint & DOEPINT_STUP ) + if ( dwc2->epout[n].doepint & DOEPINT_STUP ) { - out_ep[n].doepint = DOEPINT_STUP; + dwc2->epout[n].doepint = DOEPINT_STUP; dcd_event_setup_received(rhport, (uint8_t*) &_setup_packet[0], true); } // OUT XFER complete - if ( out_ep[n].doepint & DOEPINT_XFRC ) + if ( dwc2->epout[n].doepint & DOEPINT_XFRC ) { - out_ep[n].doepint = DOEPINT_XFRC; + dwc2->epout[n].doepint = DOEPINT_XFRC; // EP0 can only handle one packet if ( (n == 0) && ep0_pending[TUSB_DIR_OUT] ) @@ -999,7 +997,6 @@ static void handle_epin_ints(uint8_t rhport, dwc2_regs_t * dwc2, dwc2_epin_t * i void dcd_int_handler(uint8_t rhport) { dwc2_regs_t * dwc2 = DWC2_REG(rhport); - dwc2_epout_t * out_ep = EPOUT_REG(rhport); dwc2_epin_t * in_ep = EPIN_REG(rhport); uint32_t const int_status = dwc2->gintsts & dwc2->gintmsk; @@ -1072,7 +1069,7 @@ void dcd_int_handler(uint8_t rhport) // Loop until all available packets were handled do { - handle_rxflvl_ints(rhport, out_ep); + handle_rxflvl_ints(rhport); } while(dwc2->gotgint & GINTSTS_RXFLVL); // Manage RX FIFO size @@ -1091,7 +1088,7 @@ void dcd_int_handler(uint8_t rhport) if(int_status & GINTSTS_OEPINT) { // OEPINT is read-only - handle_epout_ints(rhport, dwc2, out_ep); + handle_epout_ints(rhport, dwc2); } // IN endpoint interrupt handling. -- cgit v1.3.1 From de413183d4b02a42dc1df798a1f62fb2d164eb60 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 26 Oct 2021 13:07:00 +0700 Subject: use dwc2->epin --- src/portable/synopsys/dwc2/dcd_dwc2.c | 71 +++++++++++++++++------------------ 1 file changed, 34 insertions(+), 37 deletions(-) diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 11040a6cd..ec1dac66c 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -51,7 +51,6 @@ //--------------------------------------------------------------------+ #define DWC2_REG(_port) ((dwc2_regs_t*) DWC2_REG_BASE) -#define EPIN_REG(_port) (DWC2_REG(_port)->epin) enum { @@ -271,7 +270,6 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c (void) rhport; dwc2_regs_t * dwc2 = DWC2_REG(rhport); - dwc2_epin_t * in_ep = EPIN_REG(rhport); // EP0 is limited to one packet each xfer // We use multiple transaction of xfer->max_size length to get a whole transfer done @@ -286,17 +284,17 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c if ( dir == TUSB_DIR_IN ) { // A full IN transfer (multiple packets, possibly) triggers XFRC. - in_ep[epnum].dieptsiz = (num_packets << DIEPTSIZ_PKTCNT_Pos) | + dwc2->epin[epnum].dieptsiz = (num_packets << DIEPTSIZ_PKTCNT_Pos) | ((total_bytes << DIEPTSIZ_XFRSIZ_Pos) & DIEPTSIZ_XFRSIZ_Msk); - in_ep[epnum].diepctl |= DIEPCTL_EPENA | DIEPCTL_CNAK; + dwc2->epin[epnum].diepctl |= DIEPCTL_EPENA | DIEPCTL_CNAK; // For ISO endpoint set correct odd/even bit for next frame. - if ( (in_ep[epnum].diepctl & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1 ) + if ( (dwc2->epin[epnum].diepctl & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1 ) { // Take odd/even bit from frame counter. uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos)); - in_ep[epnum].diepctl |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk); + dwc2->epin[epnum].diepctl |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk); } // Enable fifo empty interrupt only if there are something to put in the fifo. if ( total_bytes != 0 ) @@ -462,7 +460,6 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) (void) rhport; dwc2_regs_t * dwc2 = DWC2_REG(rhport); - dwc2_epin_t * in_ep = EPIN_REG(rhport); uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress); uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress); @@ -530,7 +527,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) // Both TXFD and TXSA are in unit of 32-bit words. dwc2->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | (DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx); - in_ep[epnum].diepctl |= (1 << DIEPCTL_USBAEP_Pos) | + dwc2->epin[epnum].diepctl |= (1 << DIEPCTL_USBAEP_Pos) | (epnum << DIEPCTL_TXFNUM_Pos) | (desc_edpt->bmAttributes.xfer << DIEPCTL_EPTYP_Pos) | (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DIEPCTL_SD0PID_SEVNFRM : 0) | @@ -548,7 +545,6 @@ void dcd_edpt_close_all (uint8_t rhport) (void) rhport; dwc2_regs_t * dwc2 = DWC2_REG(rhport); - dwc2_epin_t * in_ep = EPIN_REG(rhport); // Disable non-control interrupt dwc2->daintmsk = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos); @@ -560,7 +556,7 @@ void dcd_edpt_close_all (uint8_t rhport) xfer_status[n][TUSB_DIR_OUT].max_size = 0; // disable IN endpoint - in_ep[n].diepctl = 0; + dwc2->epin[n].diepctl = 0; xfer_status[n][TUSB_DIR_IN].max_size = 0; } @@ -633,7 +629,6 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall) (void) rhport; dwc2_regs_t * dwc2 = DWC2_REG(rhport); - dwc2_epin_t * in_ep = EPIN_REG(rhport); uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); @@ -641,21 +636,21 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall) if ( dir == TUSB_DIR_IN ) { // Only disable currently enabled non-control endpoint - if ( (epnum == 0) || !(in_ep[epnum].diepctl & DIEPCTL_EPENA) ) + if ( (epnum == 0) || !(dwc2->epin[epnum].diepctl & DIEPCTL_EPENA) ) { - in_ep[epnum].diepctl |= DIEPCTL_SNAK | (stall ? DIEPCTL_STALL : 0); + dwc2->epin[epnum].diepctl |= DIEPCTL_SNAK | (stall ? DIEPCTL_STALL : 0); } else { // Stop transmitting packets and NAK IN xfers. - in_ep[epnum].diepctl |= DIEPCTL_SNAK; - while ( (in_ep[epnum].diepint & DIEPINT_INEPNE) == 0 ) {} + dwc2->epin[epnum].diepctl |= DIEPCTL_SNAK; + while ( (dwc2->epin[epnum].diepint & DIEPINT_INEPNE) == 0 ) {} // Disable the endpoint. - in_ep[epnum].diepctl |= DIEPCTL_EPDIS | (stall ? DIEPCTL_STALL : 0); - while ( (in_ep[epnum].diepint & DIEPINT_EPDISD_Msk) == 0 ) {} + dwc2->epin[epnum].diepctl |= DIEPCTL_EPDIS | (stall ? DIEPCTL_STALL : 0); + while ( (dwc2->epin[epnum].diepint & DIEPINT_EPDISD_Msk) == 0 ) {} - in_ep[epnum].diepint = DIEPINT_EPDISD; + dwc2->epin[epnum].diepint = DIEPINT_EPDISD; } // Flush the FIFO, and wait until we have confirmed it cleared. @@ -730,7 +725,6 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) (void) rhport; dwc2_regs_t * dwc2 = DWC2_REG(rhport); - dwc2_epin_t * in_ep = EPIN_REG(rhport); uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); @@ -738,8 +732,8 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) // Clear stall and reset data toggle if ( dir == TUSB_DIR_IN ) { - in_ep[epnum].diepctl &= ~DIEPCTL_STALL; - in_ep[epnum].diepctl |= DIEPCTL_SD0PID_SEVNFRM; + dwc2->epin[epnum].diepctl &= ~DIEPCTL_STALL; + dwc2->epin[epnum].diepctl |= DIEPCTL_SD0PID_SEVNFRM; } else { @@ -924,7 +918,8 @@ static void handle_epout_ints (uint8_t rhport, dwc2_regs_t *dwc2) } } -static void handle_epin_ints(uint8_t rhport, dwc2_regs_t * dwc2, dwc2_epin_t * in_ep) { +static void handle_epin_ints (uint8_t rhport, dwc2_regs_t *dwc2) +{ // DAINT for a given EP clears when DIEPINTx is cleared. // IEPINT will be cleared when DAINT's out bits are cleared. for ( uint8_t n = 0; n < DWC2_EP_MAX; n++ ) @@ -934,46 +929,49 @@ static void handle_epin_ints(uint8_t rhport, dwc2_regs_t * dwc2, dwc2_epin_t * i if ( dwc2->daint & (1 << (DAINT_IEPINT_Pos + n)) ) { // IN XFER complete (entire xfer). - if ( in_ep[n].diepint & DIEPINT_XFRC ) + if ( dwc2->epin[n].diepint & DIEPINT_XFRC ) { - in_ep[n].diepint = DIEPINT_XFRC; + dwc2->epin[n].diepint = DIEPINT_XFRC; // EP0 can only handle one packet - if((n == 0) && ep0_pending[TUSB_DIR_IN]) { + if ( (n == 0) && ep0_pending[TUSB_DIR_IN] ) + { // Schedule another packet to be transmitted. edpt_schedule_packets(rhport, n, TUSB_DIR_IN, 1, ep0_pending[TUSB_DIR_IN]); - } else { + } + else + { dcd_event_xfer_complete(rhport, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true); } } // XFER FIFO empty - if ( (in_ep[n].diepint & DIEPINT_TXFE) && (dwc2->diepempmsk & (1 << n)) ) + if ( (dwc2->epin[n].diepint & DIEPINT_TXFE) && (dwc2->diepempmsk & (1 << n)) ) { // diepint's TXFE bit is read-only, software cannot clear it. // It will only be cleared by hardware when written bytes is more than // - 64 bytes or // - Half of TX FIFO size (configured by DIEPTXF) - uint16_t remaining_packets = (in_ep[n].dieptsiz & DIEPTSIZ_PKTCNT_Msk) >> DIEPTSIZ_PKTCNT_Pos; + uint16_t remaining_packets = (dwc2->epin[n].dieptsiz & DIEPTSIZ_PKTCNT_Msk) >> DIEPTSIZ_PKTCNT_Pos; // Process every single packet (only whole packets can be written to fifo) - for(uint16_t i = 0; i < remaining_packets; i++) + for ( uint16_t i = 0; i < remaining_packets; i++ ) { - uint16_t const remaining_bytes = (in_ep[n].dieptsiz & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos; + uint16_t const remaining_bytes = (dwc2->epin[n].dieptsiz & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos; // Packet can not be larger than ep max size uint16_t const packet_size = tu_min16(remaining_bytes, xfer->max_size); // It's only possible to write full packets into FIFO. Therefore DTXFSTS register of current // EP has to be checked if the buffer can take another WHOLE packet - if(packet_size > ((in_ep[n].dtxfsts & DTXFSTS_INEPTFSAV_Msk) << 2)) break; + if ( packet_size > ((dwc2->epin[n].dtxfsts & DTXFSTS_INEPTFSAV_Msk) << 2) ) break; // Push packet to Tx-FIFO - if (xfer->ff) + if ( xfer->ff ) { - volatile uint32_t * tx_fifo = dwc2->fifo[n]; - tu_fifo_read_n_const_addr_full_words(xfer->ff, (void *)(uintptr_t) tx_fifo, packet_size); + volatile uint32_t *tx_fifo = dwc2->fifo[n]; + tu_fifo_read_n_const_addr_full_words(xfer->ff, (void*) (uintptr_t) tx_fifo, packet_size); } else { @@ -985,7 +983,7 @@ static void handle_epin_ints(uint8_t rhport, dwc2_regs_t * dwc2, dwc2_epin_t * i } // Turn off TXFE if all bytes are written. - if (((in_ep[n].dieptsiz & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos) == 0) + if ( ((dwc2->epin[n].dieptsiz & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos) == 0 ) { dwc2->diepempmsk &= ~(1 << n); } @@ -997,7 +995,6 @@ static void handle_epin_ints(uint8_t rhport, dwc2_regs_t * dwc2, dwc2_epin_t * i void dcd_int_handler(uint8_t rhport) { dwc2_regs_t * dwc2 = DWC2_REG(rhport); - dwc2_epin_t * in_ep = EPIN_REG(rhport); uint32_t const int_status = dwc2->gintsts & dwc2->gintmsk; @@ -1095,7 +1092,7 @@ void dcd_int_handler(uint8_t rhport) if(int_status & GINTSTS_IEPINT) { // IEPINT bit read-only - handle_epin_ints(rhport, dwc2, in_ep); + handle_epin_ints(rhport, dwc2); } // // Check for Incomplete isochronous IN transfer -- cgit v1.3.1 From 4ebfd00d6741233a3dfcc3a74ee71f593887e847 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 26 Oct 2021 13:33:40 +0700 Subject: clean up --- src/portable/synopsys/dwc2/dcd_dwc2.c | 146 +++++++++++++++++++--------------- 1 file changed, 80 insertions(+), 66 deletions(-) diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index ec1dac66c..15dece1df 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -111,7 +111,7 @@ static void bus_reset(uint8_t rhport) { (void) rhport; - dwc2_regs_t * dwc2 = DWC2_REG(rhport); + dwc2_regs_t * dwc2 = DWC2_REG(rhport); tu_memclr(xfer_status, sizeof(xfer_status)); _out_ep_closed = false; @@ -269,7 +269,7 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c { (void) rhport; - dwc2_regs_t * dwc2 = DWC2_REG(rhport); + dwc2_regs_t * dwc2 = DWC2_REG(rhport); // EP0 is limited to one packet each xfer // We use multiple transaction of xfer->max_size length to get a whole transfer done @@ -283,18 +283,20 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c // IN and OUT endpoint xfers are interrupt-driven, we just schedule them here. if ( dir == TUSB_DIR_IN ) { + dwc2_epin_t* epin = dwc2->epin; + // A full IN transfer (multiple packets, possibly) triggers XFRC. - dwc2->epin[epnum].dieptsiz = (num_packets << DIEPTSIZ_PKTCNT_Pos) | + epin[epnum].dieptsiz = (num_packets << DIEPTSIZ_PKTCNT_Pos) | ((total_bytes << DIEPTSIZ_XFRSIZ_Pos) & DIEPTSIZ_XFRSIZ_Msk); - dwc2->epin[epnum].diepctl |= DIEPCTL_EPENA | DIEPCTL_CNAK; + epin[epnum].diepctl |= DIEPCTL_EPENA | DIEPCTL_CNAK; // For ISO endpoint set correct odd/even bit for next frame. - if ( (dwc2->epin[epnum].diepctl & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1 ) + if ( (epin[epnum].diepctl & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1 ) { // Take odd/even bit from frame counter. uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos)); - dwc2->epin[epnum].diepctl |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk); + epin[epnum].diepctl |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk); } // Enable fifo empty interrupt only if there are something to put in the fifo. if ( total_bytes != 0 ) @@ -304,17 +306,19 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c } else { + dwc2_epout_t* epout = dwc2->epout; + // A full OUT transfer (multiple packets, possibly) triggers XFRC. - dwc2->epout[epnum].doeptsiz &= ~(DOEPTSIZ_PKTCNT_Msk | DOEPTSIZ_XFRSIZ); - dwc2->epout[epnum].doeptsiz |= (num_packets << DOEPTSIZ_PKTCNT_Pos) | + epout[epnum].doeptsiz &= ~(DOEPTSIZ_PKTCNT_Msk | DOEPTSIZ_XFRSIZ); + epout[epnum].doeptsiz |= (num_packets << DOEPTSIZ_PKTCNT_Pos) | ((total_bytes << DOEPTSIZ_XFRSIZ_Pos) & DOEPTSIZ_XFRSIZ_Msk); - dwc2->epout[epnum].doepctl |= DOEPCTL_EPENA | DOEPCTL_CNAK; - if ( (dwc2->epout[epnum].doepctl & DOEPCTL_EPTYP) == DOEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1 ) + epout[epnum].doepctl |= DOEPCTL_EPENA | DOEPCTL_CNAK; + if ( (epout[epnum].doepctl & DOEPCTL_EPTYP) == DOEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1 ) { // Take odd/even bit from frame counter. uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos)); - dwc2->epout[epnum].doepctl |= (odd_frame_now ? DOEPCTL_SD0PID_SEVNFRM_Msk : DOEPCTL_SODDFRM_Msk); + epout[epnum].doepctl |= (odd_frame_now ? DOEPCTL_SD0PID_SEVNFRM_Msk : DOEPCTL_SODDFRM_Msk); } } } @@ -421,7 +425,7 @@ void dcd_remote_wakeup(uint8_t rhport) { (void) rhport; - dwc2_regs_t* dwc2 = DWC2_REG(rhport); + dwc2_regs_t * dwc2 = DWC2_REG(rhport); // set remote wakeup dwc2->dctl |= DCTL_RWUSIG; @@ -459,7 +463,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) { (void) rhport; - dwc2_regs_t * dwc2 = DWC2_REG(rhport); + dwc2_regs_t * dwc2 = DWC2_REG(rhport); uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress); uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress); @@ -486,10 +490,10 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) dwc2->grxfsiz = sz; } - dwc2->epout[epnum].doepctl |= (1 << DOEPCTL_USBAEP_Pos) | - (desc_edpt->bmAttributes.xfer << DOEPCTL_EPTYP_Pos) | - (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DOEPCTL_SD0PID_SEVNFRM : 0) | - (xfer->max_size << DOEPCTL_MPSIZ_Pos); + dwc2->epout[epnum].doepctl |= (1 << DOEPCTL_USBAEP_Pos) | + (desc_edpt->bmAttributes.xfer << DOEPCTL_EPTYP_Pos) | + (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DOEPCTL_SD0PID_SEVNFRM : 0) | + (xfer->max_size << DOEPCTL_MPSIZ_Pos); dwc2->daintmsk |= (1 << (DAINTMSK_OEPM_Pos + epnum)); } @@ -528,10 +532,10 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) dwc2->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | (DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx); dwc2->epin[epnum].diepctl |= (1 << DIEPCTL_USBAEP_Pos) | - (epnum << DIEPCTL_TXFNUM_Pos) | - (desc_edpt->bmAttributes.xfer << DIEPCTL_EPTYP_Pos) | - (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DIEPCTL_SD0PID_SEVNFRM : 0) | - (xfer->max_size << DIEPCTL_MPSIZ_Pos); + (epnum << DIEPCTL_TXFNUM_Pos) | + (desc_edpt->bmAttributes.xfer << DIEPCTL_EPTYP_Pos) | + (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DIEPCTL_SD0PID_SEVNFRM : 0) | + (xfer->max_size << DIEPCTL_MPSIZ_Pos); dwc2->daintmsk |= (1 << (DAINTMSK_IEPM_Pos + epnum)); } @@ -544,7 +548,7 @@ void dcd_edpt_close_all (uint8_t rhport) { (void) rhport; - dwc2_regs_t * dwc2 = DWC2_REG(rhport); + dwc2_regs_t * dwc2 = DWC2_REG(rhport); // Disable non-control interrupt dwc2->daintmsk = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos); @@ -628,29 +632,31 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall) { (void) rhport; - dwc2_regs_t * dwc2 = DWC2_REG(rhport); + dwc2_regs_t *dwc2 = DWC2_REG(rhport); uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); if ( dir == TUSB_DIR_IN ) { + dwc2_epin_t* epin = dwc2->epin; + // Only disable currently enabled non-control endpoint - if ( (epnum == 0) || !(dwc2->epin[epnum].diepctl & DIEPCTL_EPENA) ) + if ( (epnum == 0) || !(epin[epnum].diepctl & DIEPCTL_EPENA) ) { - dwc2->epin[epnum].diepctl |= DIEPCTL_SNAK | (stall ? DIEPCTL_STALL : 0); + epin[epnum].diepctl |= DIEPCTL_SNAK | (stall ? DIEPCTL_STALL : 0); } else { // Stop transmitting packets and NAK IN xfers. - dwc2->epin[epnum].diepctl |= DIEPCTL_SNAK; - while ( (dwc2->epin[epnum].diepint & DIEPINT_INEPNE) == 0 ) {} + epin[epnum].diepctl |= DIEPCTL_SNAK; + while ( (epin[epnum].diepint & DIEPINT_INEPNE) == 0 ) {} // Disable the endpoint. - dwc2->epin[epnum].diepctl |= DIEPCTL_EPDIS | (stall ? DIEPCTL_STALL : 0); - while ( (dwc2->epin[epnum].diepint & DIEPINT_EPDISD_Msk) == 0 ) {} + epin[epnum].diepctl |= DIEPCTL_EPDIS | (stall ? DIEPCTL_STALL : 0); + while ( (epin[epnum].diepint & DIEPINT_EPDISD_Msk) == 0 ) {} - dwc2->epin[epnum].diepint = DIEPINT_EPDISD; + epin[epnum].diepint = DIEPINT_EPDISD; } // Flush the FIFO, and wait until we have confirmed it cleared. @@ -660,10 +666,12 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall) } else { + dwc2_epout_t* epout = dwc2->epout; + // Only disable currently enabled non-control endpoint - if ( (epnum == 0) || !(dwc2->epout[epnum].doepctl & DOEPCTL_EPENA) ) + if ( (epnum == 0) || !(epout[epnum].doepctl & DOEPCTL_EPENA) ) { - dwc2->epout[epnum].doepctl |= stall ? DOEPCTL_STALL : 0; + epout[epnum].doepctl |= stall ? DOEPCTL_STALL : 0; } else { @@ -675,10 +683,10 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall) while ( (dwc2->gintsts & GINTSTS_BOUTNAKEFF_Msk) == 0 ) {} // Ditto here- disable the endpoint. - dwc2->epout[epnum].doepctl |= DOEPCTL_EPDIS | (stall ? DOEPCTL_STALL : 0); - while ( (dwc2->epout[epnum].doepint & DOEPINT_EPDISD_Msk) == 0 ) {} + epout[epnum].doepctl |= DOEPCTL_EPDIS | (stall ? DOEPCTL_STALL : 0); + while ( (epout[epnum].doepint & DOEPINT_EPDISD_Msk) == 0 ) {} - dwc2->epout[epnum].doepint = DOEPINT_EPDISD; + epout[epnum].doepint = DOEPINT_EPDISD; // Allow other OUT endpoints to keep receiving. dwc2->dctl |= DCTL_CGONAK; @@ -826,20 +834,20 @@ static void handle_rxflvl_ints(uint8_t rhport) uint8_t epnum = (ctl_word & GRXSTSP_EPNUM_Msk) >> GRXSTSP_EPNUM_Pos; uint16_t bcnt = (ctl_word & GRXSTSP_BCNT_Msk) >> GRXSTSP_BCNT_Pos; - switch(pktsts) + switch ( pktsts ) { - case 0x01: // Global OUT NAK (Interrupt) - break; + case 0x01: // Global OUT NAK (Interrupt) + break; - case 0x02: // Out packet recvd + case 0x02: // Out packet received { - xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT); + xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT); // Read packet off RxFIFO - if (xfer->ff) + if ( xfer->ff ) { // Ring buffer - tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void *)(uintptr_t) rx_fifo, bcnt); + tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void*) (uintptr_t) rx_fifo, bcnt); } else { @@ -851,9 +859,11 @@ static void handle_rxflvl_ints(uint8_t rhport) } // Truncate transfer length in case of short packet - if(bcnt < xfer->max_size) { + if ( bcnt < xfer->max_size ) + { xfer->total_len -= (dwc2->epout[epnum].doeptsiz & DOEPTSIZ_XFRSIZ_Msk) >> DOEPTSIZ_XFRSIZ_Pos; - if(epnum == 0) { + if ( epnum == 0 ) + { xfer->total_len -= ep0_pending[TUSB_DIR_OUT]; ep0_pending[TUSB_DIR_OUT] = 0; } @@ -861,28 +871,30 @@ static void handle_rxflvl_ints(uint8_t rhport) } break; - case 0x03: // Out packet done (Interrupt) - break; + case 0x03: // Out packet done (Interrupt) + break; - case 0x04: // Setup packet done (Interrupt) + case 0x04: // Setup packet done (Interrupt) dwc2->epout[epnum].doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos); - break; + break; - case 0x06: // Setup packet recvd + case 0x06: // Setup packet recvd // We can receive up to three setup packets in succession, but // only the last one is valid. - _setup_packet[0] = (* rx_fifo); - _setup_packet[1] = (* rx_fifo); - break; + _setup_packet[0] = (*rx_fifo); + _setup_packet[1] = (*rx_fifo); + break; - default: // Invalid + default: // Invalid TU_BREAKPOINT(); - break; + break; } } static void handle_epout_ints (uint8_t rhport, dwc2_regs_t *dwc2) { + dwc2_epout_t* epout = dwc2->epout; + // DAINT for a given EP clears when DOEPINTx is cleared. // OEPINT will be cleared when DAINT's out bits are cleared. for ( uint8_t n = 0; n < DWC2_EP_MAX; n++ ) @@ -892,16 +904,16 @@ static void handle_epout_ints (uint8_t rhport, dwc2_regs_t *dwc2) if ( dwc2->daint & (1 << (DAINT_OEPINT_Pos + n)) ) { // SETUP packet Setup Phase done. - if ( dwc2->epout[n].doepint & DOEPINT_STUP ) + if ( epout[n].doepint & DOEPINT_STUP ) { - dwc2->epout[n].doepint = DOEPINT_STUP; + epout[n].doepint = DOEPINT_STUP; dcd_event_setup_received(rhport, (uint8_t*) &_setup_packet[0], true); } // OUT XFER complete - if ( dwc2->epout[n].doepint & DOEPINT_XFRC ) + if ( epout[n].doepint & DOEPINT_XFRC ) { - dwc2->epout[n].doepint = DOEPINT_XFRC; + epout[n].doepint = DOEPINT_XFRC; // EP0 can only handle one packet if ( (n == 0) && ep0_pending[TUSB_DIR_OUT] ) @@ -920,6 +932,8 @@ static void handle_epout_ints (uint8_t rhport, dwc2_regs_t *dwc2) static void handle_epin_ints (uint8_t rhport, dwc2_regs_t *dwc2) { + dwc2_epin_t* epin = dwc2->epin; + // DAINT for a given EP clears when DIEPINTx is cleared. // IEPINT will be cleared when DAINT's out bits are cleared. for ( uint8_t n = 0; n < DWC2_EP_MAX; n++ ) @@ -929,9 +943,9 @@ static void handle_epin_ints (uint8_t rhport, dwc2_regs_t *dwc2) if ( dwc2->daint & (1 << (DAINT_IEPINT_Pos + n)) ) { // IN XFER complete (entire xfer). - if ( dwc2->epin[n].diepint & DIEPINT_XFRC ) + if ( epin[n].diepint & DIEPINT_XFRC ) { - dwc2->epin[n].diepint = DIEPINT_XFRC; + epin[n].diepint = DIEPINT_XFRC; // EP0 can only handle one packet if ( (n == 0) && ep0_pending[TUSB_DIR_IN] ) @@ -946,26 +960,26 @@ static void handle_epin_ints (uint8_t rhport, dwc2_regs_t *dwc2) } // XFER FIFO empty - if ( (dwc2->epin[n].diepint & DIEPINT_TXFE) && (dwc2->diepempmsk & (1 << n)) ) + if ( (epin[n].diepint & DIEPINT_TXFE) && (dwc2->diepempmsk & (1 << n)) ) { // diepint's TXFE bit is read-only, software cannot clear it. // It will only be cleared by hardware when written bytes is more than // - 64 bytes or // - Half of TX FIFO size (configured by DIEPTXF) - uint16_t remaining_packets = (dwc2->epin[n].dieptsiz & DIEPTSIZ_PKTCNT_Msk) >> DIEPTSIZ_PKTCNT_Pos; + uint16_t remaining_packets = (epin[n].dieptsiz & DIEPTSIZ_PKTCNT_Msk) >> DIEPTSIZ_PKTCNT_Pos; // Process every single packet (only whole packets can be written to fifo) for ( uint16_t i = 0; i < remaining_packets; i++ ) { - uint16_t const remaining_bytes = (dwc2->epin[n].dieptsiz & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos; + uint16_t const remaining_bytes = (epin[n].dieptsiz & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos; // Packet can not be larger than ep max size uint16_t const packet_size = tu_min16(remaining_bytes, xfer->max_size); // It's only possible to write full packets into FIFO. Therefore DTXFSTS register of current // EP has to be checked if the buffer can take another WHOLE packet - if ( packet_size > ((dwc2->epin[n].dtxfsts & DTXFSTS_INEPTFSAV_Msk) << 2) ) break; + if ( packet_size > ((epin[n].dtxfsts & DTXFSTS_INEPTFSAV_Msk) << 2) ) break; // Push packet to Tx-FIFO if ( xfer->ff ) @@ -983,7 +997,7 @@ static void handle_epin_ints (uint8_t rhport, dwc2_regs_t *dwc2) } // Turn off TXFE if all bytes are written. - if ( ((dwc2->epin[n].dieptsiz & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos) == 0 ) + if ( ((epin[n].dieptsiz & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos) == 0 ) { dwc2->diepempmsk &= ~(1 << n); } @@ -994,7 +1008,7 @@ static void handle_epin_ints (uint8_t rhport, dwc2_regs_t *dwc2) void dcd_int_handler(uint8_t rhport) { - dwc2_regs_t * dwc2 = DWC2_REG(rhport); + dwc2_regs_t *dwc2 = DWC2_REG(rhport); uint32_t const int_status = dwc2->gintsts & dwc2->gintmsk; -- cgit v1.3.1 From 5d05f8758fcf66ac8192eeefea7ff567ac749eb8 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 26 Oct 2021 13:36:43 +0700 Subject: more clean up --- src/portable/synopsys/dwc2/dcd_dwc2.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 15dece1df..d9e21652e 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -823,7 +823,7 @@ static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t * src, u } } -static void handle_rxflvl_ints(uint8_t rhport) +static void handle_rxflvl_irq(uint8_t rhport) { dwc2_regs_t * dwc2 = DWC2_REG(rhport); volatile uint32_t * rx_fifo = dwc2->fifo[0]; @@ -891,8 +891,9 @@ static void handle_rxflvl_ints(uint8_t rhport) } } -static void handle_epout_ints (uint8_t rhport, dwc2_regs_t *dwc2) +static void handle_epout_irq (uint8_t rhport) { + dwc2_regs_t *dwc2 = DWC2_REG(rhport); dwc2_epout_t* epout = dwc2->epout; // DAINT for a given EP clears when DOEPINTx is cleared. @@ -930,8 +931,9 @@ static void handle_epout_ints (uint8_t rhport, dwc2_regs_t *dwc2) } } -static void handle_epin_ints (uint8_t rhport, dwc2_regs_t *dwc2) +static void handle_epin_irq (uint8_t rhport) { + dwc2_regs_t *dwc2 = DWC2_REG(rhport); dwc2_epin_t* epin = dwc2->epin; // DAINT for a given EP clears when DIEPINTx is cleared. @@ -1080,7 +1082,7 @@ void dcd_int_handler(uint8_t rhport) // Loop until all available packets were handled do { - handle_rxflvl_ints(rhport); + handle_rxflvl_irq(rhport); } while(dwc2->gotgint & GINTSTS_RXFLVL); // Manage RX FIFO size @@ -1099,14 +1101,14 @@ void dcd_int_handler(uint8_t rhport) if(int_status & GINTSTS_OEPINT) { // OEPINT is read-only - handle_epout_ints(rhport, dwc2); + handle_epout_irq(rhport); } // IN endpoint interrupt handling. if(int_status & GINTSTS_IEPINT) { // IEPINT bit read-only - handle_epin_ints(rhport, dwc2); + handle_epin_irq(rhport); } // // Check for Incomplete isochronous IN transfer -- cgit v1.3.1 From 68fa9d406495410914b55c50984d5a1b821ee80c Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 26 Oct 2021 13:56:56 +0700 Subject: enhance fifo read/write --- src/portable/synopsys/dwc2/dcd_dwc2.c | 54 ++++++++++++----------------------- 1 file changed, 19 insertions(+), 35 deletions(-) diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index d9e21652e..67f84a083 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -758,39 +758,29 @@ static void read_fifo_packet(uint8_t rhport, uint8_t * dst, uint16_t len) (void) rhport; dwc2_regs_t * dwc2 = DWC2_REG(rhport); - volatile uint32_t * rx_fifo = dwc2->fifo[0]; + volatile const uint32_t * rx_fifo = dwc2->fifo[0]; // Reading full available 32 bit words from fifo uint16_t full_words = len >> 2; - for ( uint16_t i = 0; i < full_words; i++ ) + while(full_words--) { - uint32_t tmp = *rx_fifo; - dst[0] = tmp & 0x000000FF; - dst[1] = (tmp & 0x0000FF00) >> 8; - dst[2] = (tmp & 0x00FF0000) >> 16; - dst[3] = (tmp & 0xFF000000) >> 24; + tu_unaligned_write32(dst, *rx_fifo); dst += 4; } // Read the remaining 1-3 bytes from fifo - uint8_t bytes_rem = len & 0x03; + uint8_t const bytes_rem = len & 0x03; if ( bytes_rem != 0 ) { - uint32_t tmp = *rx_fifo; - dst[0] = tmp & 0x000000FF; - if ( bytes_rem > 1 ) - { - dst[1] = (tmp & 0x0000FF00) >> 8; - } - if ( bytes_rem > 2 ) - { - dst[2] = (tmp & 0x00FF0000) >> 16; - } + uint32_t const tmp = *rx_fifo; + dst[0] = tu_u32_byte0(tmp); + if ( bytes_rem > 1 ) dst[1] = tu_u32_byte1(tmp); + if ( bytes_rem > 2 ) dst[2] = tu_u32_byte2(tmp); } } // Write a single data packet to EPIN FIFO -static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t * src, uint16_t len) +static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t const * src, uint16_t len) { (void) rhport; @@ -799,26 +789,20 @@ static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t * src, u // Pushing full available 32 bit words to fifo uint16_t full_words = len >> 2; - for ( uint16_t i = 0; i < full_words; i++ ) + while(full_words--) { - *tx_fifo = (src[3] << 24) | (src[2] << 16) | (src[1] << 8) | src[0]; + *tx_fifo = tu_unaligned_read32(src); src += 4; } // Write the remaining 1-3 bytes into fifo - uint8_t bytes_rem = len & 0x03; + uint8_t const bytes_rem = len & 0x03; if ( bytes_rem ) { - uint32_t tmp_word = 0; - tmp_word |= src[0]; - if ( bytes_rem > 1 ) - { - tmp_word |= src[1] << 8; - } - if ( bytes_rem > 2 ) - { - tmp_word |= src[2] << 16; - } + uint32_t tmp_word = src[0]; + if ( bytes_rem > 1 ) tmp_word |= (src[1] << 8); + if ( bytes_rem > 2 ) tmp_word |= (src[2] << 16); + *tx_fifo = tmp_word; } } @@ -830,9 +814,9 @@ static void handle_rxflvl_irq(uint8_t rhport) // Pop control word off FIFO uint32_t ctl_word = dwc2->grxstsp; - uint8_t pktsts = (ctl_word & GRXSTSP_PKTSTS_Msk) >> GRXSTSP_PKTSTS_Pos; - uint8_t epnum = (ctl_word & GRXSTSP_EPNUM_Msk) >> GRXSTSP_EPNUM_Pos; - uint16_t bcnt = (ctl_word & GRXSTSP_BCNT_Msk) >> GRXSTSP_BCNT_Pos; + uint8_t pktsts = (ctl_word & GRXSTSP_PKTSTS_Msk ) >> GRXSTSP_PKTSTS_Pos; + uint8_t epnum = (ctl_word & GRXSTSP_EPNUM_Msk ) >> GRXSTSP_EPNUM_Pos; + uint16_t bcnt = (ctl_word & GRXSTSP_BCNT_Msk ) >> GRXSTSP_BCNT_Pos; switch ( pktsts ) { -- cgit v1.3.1 From bb5dab5c2e81be277214a6704a8d90e89a5b4759 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 26 Oct 2021 22:48:01 +0700 Subject: add hw config struct --- hw/bsp/board.c | 2 +- src/common/tusb_common.h | 4 +- src/portable/synopsys/dwc2/dcd_dwc2.c | 92 +++++++++++-- src/portable/synopsys/dwc2/dwc2_type.h | 234 ++++++++++++++++++++++----------- 4 files changed, 240 insertions(+), 92 deletions(-) diff --git a/hw/bsp/board.c b/hw/bsp/board.c index 2c18b61b4..afacdef9f 100644 --- a/hw/bsp/board.c +++ b/hw/bsp/board.c @@ -96,7 +96,7 @@ void board_led_task(void) TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count) { (void) fhdl; - SEGGER_RTT_Write(0, (char*) buf, (int) count); + SEGGER_RTT_Write(0, (const char*) buf, (int) count); return count; } diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h index bf9641622..e62bcde12 100644 --- a/src/common/tusb_common.h +++ b/src/common/tusb_common.h @@ -303,8 +303,8 @@ void tu_print_var(uint8_t const* buf, uint32_t bufsize) #define TU_LOG1 tu_printf #define TU_LOG1_MEM tu_print_mem #define TU_LOG1_VAR(_x) tu_print_var((uint8_t const*)(_x), sizeof(*(_x))) -#define TU_LOG1_INT(_x) tu_printf(#_x " = %ld\r\n", (uint32_t) (_x) ) -#define TU_LOG1_HEX(_x) tu_printf(#_x " = %lX\r\n", (uint32_t) (_x) ) +#define TU_LOG1_INT(_x) tu_printf(#_x " = %ld\r\n", (unsigned long) (_x) ) +#define TU_LOG1_HEX(_x) tu_printf(#_x " = %lX\r\n", (unsigned long) (_x) ) // Log Level 2: Warn #if CFG_TUSB_DEBUG >= 2 diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 67f84a083..7b02c75cd 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -74,14 +74,14 @@ typedef struct { } xfer_ctl_t; xfer_ctl_t xfer_status[DWC2_EP_MAX][2]; -#define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir] +#define XFER_CTL_BASE(_ep, _dir) (&xfer_status[_ep][_dir]) // EP0 transfers are limited to 1 packet - larger sizes has to be split static uint16_t ep0_pending[2]; // Index determines direction as tusb_dir_t type // TX FIFO RAM allocation so far in words - RX FIFO size is readily available from dwc2->grxfsiz static uint16_t _allocated_fifo_words_tx; // TX FIFO size in words (IN EPs) -static bool _out_ep_closed; // Flag to check if RX FIFO size needs an update (reduce its size) +static bool _out_ep_closed; // Flag to check if RX FIFO size needs an update (reduce its size) // Calculate the RX FIFO size according to recommendations from reference manual static inline uint16_t calc_rx_ff_size(uint16_t ep_size) @@ -120,14 +120,15 @@ static void bus_reset(uint8_t rhport) dwc2->dcfg &= ~DCFG_DAD_Msk; // 1. NAK for all OUT endpoints - for(uint8_t n = 0; n < DWC2_EP_MAX; n++) { + for ( uint8_t n = 0; n < DWC2_EP_MAX; n++ ) + { dwc2->epout[n].doepctl |= DOEPCTL_SNAK; } // 2. Un-mask interrupt bits dwc2->daintmsk = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos); dwc2->doepmsk = DOEPMSK_STUPM | DOEPMSK_XFRCM; - dwc2->diepmsk = DIEPMSK_TOM | DIEPMSK_XFRCM; + dwc2->diepmsk = DIEPMSK_TOM | DIEPMSK_XFRCM; // "USB Data FIFOs" section in reference manual // Peripheral FIFO architecture @@ -188,7 +189,8 @@ static void bus_reset(uint8_t rhport) // Fixed control EP0 size to 64 bytes dwc2->epin[0].diepctl &= ~(0x03 << DIEPCTL_MPSIZ_Pos); - xfer_status[0][TUSB_DIR_OUT].max_size = xfer_status[0][TUSB_DIR_IN].max_size = 64; + xfer_status[0][TUSB_DIR_OUT].max_size = 64; + xfer_status[0][TUSB_DIR_IN ].max_size = 64; dwc2->epout[0].doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos); @@ -210,7 +212,7 @@ static void set_speed(uint8_t rhport, tusb_speed_t speed) if ( rhport == 1 ) { - bitvalue = ((TUSB_SPEED_HIGH == speed) ? DCD_HIGH_SPEED : DCD_FULL_SPEED_USE_HS); + bitvalue = (TUSB_SPEED_HIGH == speed ? DCD_HIGH_SPEED : DCD_FULL_SPEED_USE_HS); } else { @@ -287,7 +289,7 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c // A full IN transfer (multiple packets, possibly) triggers XFRC. epin[epnum].dieptsiz = (num_packets << DIEPTSIZ_PKTCNT_Pos) | - ((total_bytes << DIEPTSIZ_XFRSIZ_Pos) & DIEPTSIZ_XFRSIZ_Msk); + ((total_bytes << DIEPTSIZ_XFRSIZ_Pos) & DIEPTSIZ_XFRSIZ_Msk); epin[epnum].diepctl |= DIEPCTL_EPENA | DIEPCTL_CNAK; @@ -311,10 +313,11 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c // A full OUT transfer (multiple packets, possibly) triggers XFRC. epout[epnum].doeptsiz &= ~(DOEPTSIZ_PKTCNT_Msk | DOEPTSIZ_XFRSIZ); epout[epnum].doeptsiz |= (num_packets << DOEPTSIZ_PKTCNT_Pos) | - ((total_bytes << DOEPTSIZ_XFRSIZ_Pos) & DOEPTSIZ_XFRSIZ_Msk); + ((total_bytes << DOEPTSIZ_XFRSIZ_Pos) & DOEPTSIZ_XFRSIZ_Msk); epout[epnum].doepctl |= DOEPCTL_EPENA | DOEPCTL_CNAK; - if ( (epout[epnum].doepctl & DOEPCTL_EPTYP) == DOEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1 ) + if ( (epout[epnum].doepctl & DOEPCTL_EPTYP) == DOEPCTL_EPTYP_0 && + XFER_CTL_BASE(epnum, dir)->interval == 1 ) { // Take odd/even bit from frame counter. uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos)); @@ -326,13 +329,82 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c /*------------------------------------------------------------------*/ /* Controller API *------------------------------------------------------------------*/ +void print_dwc2_info(dwc2_regs_t * dwc2) +{ + dwc2_ghwcfg2_t const * hw_cfg2 = &dwc2->ghwcfg2_bm; + dwc2_ghwcfg3_t const * hw_cfg3 = &dwc2->ghwcfg3_bm; + dwc2_ghwcfg4_t const * hw_cfg4 = &dwc2->ghwcfg4_bm; + + TU_LOG_HEX(1, dwc2->guid); + TU_LOG_HEX(1, dwc2->gsnpsid); + TU_LOG_HEX(1, dwc2->ghwcfg1); + + // HW configure 2 + TU_LOG(1, "\r\n"); + TU_LOG_HEX(1, dwc2->ghwcfg2); + TU_LOG_INT(1, hw_cfg2->op_mode ); + TU_LOG_INT(1, hw_cfg2->arch ); + TU_LOG_INT(1, hw_cfg2->point2point ); + TU_LOG_INT(1, hw_cfg2->hs_phy_type ); + TU_LOG_INT(1, hw_cfg2->fs_phy_type ); + TU_LOG_INT(1, hw_cfg2->num_dev_ep ); + TU_LOG_INT(1, hw_cfg2->num_host_ch ); + TU_LOG_INT(1, hw_cfg2->period_channel_support ); + TU_LOG_INT(1, hw_cfg2->enable_dynamic_fifo ); + TU_LOG_INT(1, hw_cfg2->mul_cpu_int ); + TU_LOG_INT(1, hw_cfg2->nperiod_tx_q_depth ); + TU_LOG_INT(1, hw_cfg2->host_period_tx_q_depth ); + TU_LOG_INT(1, hw_cfg2->dev_token_q_depth ); + TU_LOG_INT(1, hw_cfg2->otg_enable_ic_usb ); + + // HW configure 3 + TU_LOG(1, "\r\n"); + TU_LOG_HEX(1, dwc2->ghwcfg3); + TU_LOG_INT(1, hw_cfg3->xfer_size_width ); + TU_LOG_INT(1, hw_cfg3->packet_size_width ); + TU_LOG_INT(1, hw_cfg3->otg_enable ); + TU_LOG_INT(1, hw_cfg3->i2c_enable ); + TU_LOG_INT(1, hw_cfg3->vendor_ctrl_itf ); + TU_LOG_INT(1, hw_cfg3->optional_feature_removed ); + TU_LOG_INT(1, hw_cfg3->synch_reset ); + TU_LOG_INT(1, hw_cfg3->otg_adp_support ); + TU_LOG_INT(1, hw_cfg3->otg_enable_hsic ); + TU_LOG_INT(1, hw_cfg3->otg_bc_support ); + TU_LOG_INT(1, hw_cfg3->lpm_mode ); + TU_LOG_INT(1, hw_cfg3->total_fifo_size ); + + // HW configure 4 + TU_LOG(1, "\r\n"); + TU_LOG_HEX(1, dwc2->ghwcfg4); + TU_LOG_INT(1, hw_cfg4->num_dev_period_in_ep ); + TU_LOG_INT(1, hw_cfg4->power_optimized ); + TU_LOG_INT(1, hw_cfg4->ahb_freq_min ); + TU_LOG_INT(1, hw_cfg4->hibernation ); + TU_LOG_INT(1, hw_cfg4->service_interval_mode ); + TU_LOG_INT(1, hw_cfg4->ipg_isoc_en ); + TU_LOG_INT(1, hw_cfg4->acg_enable ); + TU_LOG_INT(1, hw_cfg4->utmi_phy_data_width ); + TU_LOG_INT(1, hw_cfg4->dev_ctrl_ep_num ); + TU_LOG_INT(1, hw_cfg4->iddg_filter_enabled ); + TU_LOG_INT(1, hw_cfg4->vbus_valid_filter_enabled ); + TU_LOG_INT(1, hw_cfg4->a_valid_filter_enabled ); + TU_LOG_INT(1, hw_cfg4->b_valid_filter_enabled ); + TU_LOG_INT(1, hw_cfg4->dedicated_fifos ); + TU_LOG_INT(1, hw_cfg4->num_dev_in_eps ); + TU_LOG_INT(1, hw_cfg4->dma_desc_enable ); + TU_LOG_INT(1, hw_cfg4->dma_dynamic ); +} + void dcd_init (uint8_t rhport) { // Programming model begins in the last section of the chapter on the USB // peripheral in each Reference Manual. dwc2_regs_t * dwc2 = DWC2_REG(rhport); - // check GSNPSID + // check gsnpsid + //TU_LOG_HEX(1, dwc2->gsnpsid); + + print_dwc2_info(dwc2); // No HNP/SRP (no OTG support), program timeout later. if ( rhport == 1 ) diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index 5669aa88d..58e628970 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -19,6 +19,27 @@ #include "stdint.h" +/* DWC OTG HW Release versions */ +#define DWC2_CORE_REV_2_71a 0x4f54271a +#define DWC2_CORE_REV_2_72a 0x4f54272a +#define DWC2_CORE_REV_2_80a 0x4f54280a +#define DWC2_CORE_REV_2_90a 0x4f54290a +#define DWC2_CORE_REV_2_91a 0x4f54291a +#define DWC2_CORE_REV_2_92a 0x4f54292a +#define DWC2_CORE_REV_2_94a 0x4f54294a +#define DWC2_CORE_REV_3_00a 0x4f54300a +#define DWC2_CORE_REV_3_10a 0x4f54310a +#define DWC2_CORE_REV_4_00a 0x4f54400a +#define DWC2_CORE_REV_4_20a 0x4f54420a +#define DWC2_FS_IOT_REV_1_00a 0x5531100a +#define DWC2_HS_IOT_REV_1_00a 0x5532100a +#define DWC2_CORE_REV_MASK 0x0000ffff + +/* DWC OTG HW Core ID */ +#define DWC2_OTG_ID 0x4f540000 +#define DWC2_FS_IOT_ID 0x55310000 +#define DWC2_HS_IOT_ID 0x55320000 + #ifdef __cplusplus extern "C" { #endif @@ -37,93 +58,165 @@ typedef struct } HS_PHYC_GlobalTypeDef; #endif +typedef struct TU_ATTR_PACKED +{ + uint32_t op_mode : 3; // 0: HNP and SRP | 1: SRP | 2: non-HNP, non-SRP + uint32_t arch : 2; // 0: slave-only | 1: External DMA | 2: Internal DMA | 3: others + uint32_t point2point : 1; // 0: support hub and split | 1: no hub, no split + uint32_t hs_phy_type : 2; // 0: not supported | 1: UTMI+ | 2: ULPI | 3: UTMI+ and ULPI + uint32_t fs_phy_type : 2; // 0: not supported | 1: dedicated | 2: UTMI+ | 3: ULPI + uint32_t num_dev_ep : 4; // Number of device endpoints (not including EP0) + uint32_t num_host_ch : 4; // Number of host channel + uint32_t period_channel_support : 1; // Support Periodic OUT Host Channel + uint32_t enable_dynamic_fifo : 1; // Dynamic FIFO Sizing Enabled + uint32_t mul_cpu_int : 1; // Multi-Processor Interrupt Enabled + uint32_t reserved21 : 1; + uint32_t nperiod_tx_q_depth : 2; // Non-periodic request queue depth: 0 = 2. 1 = 4, 2 = 8 + uint32_t host_period_tx_q_depth : 2; // Host periodic request queue depth: 0 = 2. 1 = 4, 2 = 8 + uint32_t dev_token_q_depth : 5; // Device IN token sequence learning queue depth: 0-30 + uint32_t otg_enable_ic_usb : 1; // IC_USB mode specified for mode of operation +} dwc2_ghwcfg2_t; + +TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg2_t) == 4, "incorrect size"); + +typedef struct TU_ATTR_PACKED +{ + uint32_t xfer_size_width : 4; // Transfer size counter in bits = 11 + n (max 19 bits) + uint32_t packet_size_width : 3; // Packet size counter in bits = 4 + n (max 10 bits) + uint32_t otg_enable : 1; // 1 is OTG capable + uint32_t i2c_enable : 1; // I2C interface is available + uint32_t vendor_ctrl_itf : 1; // Vendor control interface is available + uint32_t optional_feature_removed : 1; // remove User ID, GPIO, SOF toggle & counter + uint32_t synch_reset : 1; // 0: async reset | 1: synch reset + uint32_t otg_adp_support : 1; // ADP logic is present along with HSOTG controller + uint32_t otg_enable_hsic : 1; // 1: HSIC-capable with shared UTMI PHY interface | 0: non-HSIC + uint32_t otg_bc_support : 1; // support battery charger + uint32_t lpm_mode : 1; // LPC mode + uint32_t total_fifo_size : 16; // DFIFO depth value in terms of 32-bit words +}dwc2_ghwcfg3_t; + +TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg3_t) == 4, "incorrect size"); + +typedef struct TU_ATTR_PACKED +{ + uint32_t num_dev_period_in_ep : 4; // Number of Device Periodic IN Endpoints + uint32_t power_optimized : 1; // Partial Power Down Enabled + uint32_t ahb_freq_min : 1; // 1: minimum of AHB frequency is less than 60 MHz + uint32_t hibernation : 1; // Hibernation feature is enabled + uint32_t reserved7 : 3; + uint32_t service_interval_mode : 1; // Service Interval supported + uint32_t ipg_isoc_en : 1; // IPG ISOC supported + uint32_t acg_enable : 1; // ACG enabled + uint32_t reserved13 : 1; + uint32_t utmi_phy_data_width : 2; // 0: 8 bits | 1: 16 bits | 2: 8/16 software selectable + uint32_t dev_ctrl_ep_num : 4; // Number of Device control endpoints in addition to EP0 + uint32_t iddg_filter_enabled : 1; + uint32_t vbus_valid_filter_enabled : 1; + uint32_t a_valid_filter_enabled : 1; + uint32_t b_valid_filter_enabled : 1; + uint32_t dedicated_fifos : 1; // Dedicated tx fifo for device IN Endpoint is enabled + uint32_t num_dev_in_eps : 4; // Number of Device IN Endpoints including EP0 + uint32_t dma_desc_enable : 1; // scatter/gather DMA configuration + uint32_t dma_dynamic : 1; // Dynamic scatter/gather DMA +}dwc2_ghwcfg4_t; + +TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg4_t) == 4, "incorrect size"); + // Host Channel typedef struct { - volatile uint32_t hcchar; // 500 + 20*ch Host Channel Characteristics Register - volatile uint32_t hcsplt; // 504 + 20*ch Host Channel Split Control Register - volatile uint32_t hcint; // 508 + 20*ch Host Channel Interrupt Register - volatile uint32_t hcintmsk; // 50C + 20*ch Host Channel Interrupt Mask Register - volatile uint32_t hctsiz; // 510 + 20*ch Host Channel Transfer Size Register - volatile uint32_t hcdma; // 514 + 20*ch Host Channel DMA Address Register + volatile uint32_t hcchar; // 500 + 20*ch Host Channel Characteristics + volatile uint32_t hcsplt; // 504 + 20*ch Host Channel Split Control + volatile uint32_t hcint; // 508 + 20*ch Host Channel Interrupt + volatile uint32_t hcintmsk; // 50C + 20*ch Host Channel Interrupt Mask + volatile uint32_t hctsiz; // 510 + 20*ch Host Channel Transfer Size + volatile uint32_t hcdma; // 514 + 20*ch Host Channel DMA Address uint32_t reserved518; // 518 + 20*ch - volatile uint32_t hcdmab; // 51C + 20*ch Host Channel DMA Address Register + volatile uint32_t hcdmab; // 51C + 20*ch Host Channel DMA Address } dwc2_channel_t; // Endpoint IN typedef struct { - volatile uint32_t diepctl; // 900 + 20*ep Device IN Endpoint Control - uint32_t reserved04; // 904 - volatile uint32_t diepint; // 908 + 20*ep Device IN Endpoint Interrupt - uint32_t reserved0c; // 90C - volatile uint32_t dieptsiz; // 910 + 20*ep Device IN Endpoint Transfer Size - volatile uint32_t diepdma; // 914 + 20*ep Device IN Endpoint DMA Address - volatile uint32_t dtxfsts; // 918 + 20*ep Device IN Endpoint Tx FIFO Status - uint32_t reserved1c; // 91C + volatile uint32_t diepctl; // 900 + 20*ep Device IN Endpoint Control + uint32_t reserved04; // 904 + volatile uint32_t diepint; // 908 + 20*ep Device IN Endpoint Interrupt + uint32_t reserved0c; // 90C + volatile uint32_t dieptsiz; // 910 + 20*ep Device IN Endpoint Transfer Size + volatile uint32_t diepdma; // 914 + 20*ep Device IN Endpoint DMA Address + volatile uint32_t dtxfsts; // 918 + 20*ep Device IN Endpoint Tx FIFO Status + uint32_t reserved1c; // 91C } dwc2_epin_t; // Endpoint OUT typedef struct { - volatile uint32_t doepctl; // B00 + 20*ep Device OUT Endpoint Control - uint32_t reserved04; // B04 - volatile uint32_t doepint; // B08 + 20*ep Device OUT Endpoint Interrupt - uint32_t reserved0c; // B0C - volatile uint32_t doeptsiz; // B10 + 20*ep Device OUT Endpoint Transfer Size - volatile uint32_t doepdma; // B14 + 20*ep Device OUT Endpoint DMA Address - uint32_t reserved18[2]; // B18..B1C + volatile uint32_t doepctl; // B00 + 20*ep Device OUT Endpoint Control + uint32_t reserved04; // B04 + volatile uint32_t doepint; // B08 + 20*ep Device OUT Endpoint Interrupt + uint32_t reserved0c; // B0C + volatile uint32_t doeptsiz; // B10 + 20*ep Device OUT Endpoint Transfer Size + volatile uint32_t doepdma; // B14 + 20*ep Device OUT Endpoint DMA Address + uint32_t reserved18[2]; // B18..B1C } dwc2_epout_t; typedef struct { //------------- Core Global -------------// - volatile uint32_t gotgctl; // 000 OTG Control and Status Register - volatile uint32_t gotgint; // 004 OTG Interrupt Register - volatile uint32_t gahbcfg; // 008 AHB Configuration Register - volatile uint32_t gusbcfg; // 00c USB Configuration Register - volatile uint32_t grstctl; // 010 Reset Register - volatile uint32_t gintsts; // 014 Interrupt Register - volatile uint32_t gintmsk; // 018 Interrupt Mask Register - volatile uint32_t grxstsr; // 01c Receive Status Debug Read Register - volatile uint32_t grxstsp; // 020 Receive Status Read/Pop Register - volatile uint32_t grxfsiz; // 024 Receive FIFO Size Register + volatile uint32_t gotgctl; // 000 OTG Control and Status + volatile uint32_t gotgint; // 004 OTG Interrupt + volatile uint32_t gahbcfg; // 008 AHB Configuration + volatile uint32_t gusbcfg; // 00c USB Configuration + volatile uint32_t grstctl; // 010 Reset + volatile uint32_t gintsts; // 014 Interrupt + volatile uint32_t gintmsk; // 018 Interrupt Mask + volatile uint32_t grxstsr; // 01c Receive Status Debug Read + volatile uint32_t grxstsp; // 020 Receive Status Read/Pop + volatile uint32_t grxfsiz; // 024 Receive FIFO Size union { - volatile uint32_t dieptxf0; // 028 EP0 Tx FIFO Size Register - volatile uint32_t gnptxfsiz; // 028 Non-periodic Transmit FIFO Size Register + volatile uint32_t dieptxf0; // 028 EP0 Tx FIFO Size + volatile uint32_t gnptxfsiz; // 028 Non-periodic Transmit FIFO Size }; - volatile uint32_t gnptxsts; // 02c Non-periodic Transmit FIFO/Queue Status Register - volatile uint32_t gi2cctl; // 030 I2C Address Register - volatile uint32_t gpvndctl; // 034 PHY Vendor Control Register + volatile uint32_t gnptxsts; // 02c Non-periodic Transmit FIFO/Queue Status + volatile uint32_t gi2cctl; // 030 I2C Address + volatile uint32_t gpvndctl; // 034 PHY Vendor Control union { - volatile uint32_t ggpio; // 038 General Purpose IO Register + volatile uint32_t ggpio; // 038 General Purpose IO volatile uint32_t stm32_gccfg; // 038 STM32 General Core Configuration }; - volatile uint32_t guid; // 03C User ID Register - volatile uint32_t gsnpsid; // 040 Synopsys ID Register - volatile uint32_t ghwcfg1; // 044 User Hardware Configuration 1 Register - volatile uint32_t ghwcfg2; // 048 User Hardware Configuration 2 Register - volatile uint32_t ghwcfg3; // 04C User Hardware Configuration 3 Register - volatile uint32_t ghwcfg4; // 050 User Hardware Configuration 4 Register - volatile uint32_t glpmcfg; // 054 Core LPM Configuration Register - volatile uint32_t gpwrdn; // 058 Power Down Register - volatile uint32_t gdfifocfg; // 05C DFIFO Software Configuration Register - volatile uint32_t gadpctl; // 060 ADP Timer, Control and Status Register - + volatile uint32_t guid; // 03C User (Application programmable) ID + volatile uint32_t gsnpsid; // 040 Synopsys ID + Release version + volatile uint32_t ghwcfg1; // 044 User Hardware Configuration1: endpoint dir (2 bit per ep) +union { + volatile uint32_t ghwcfg2; // 048 User Hardware Configuration2 + dwc2_ghwcfg2_t ghwcfg2_bm; +}; +union { + volatile uint32_t ghwcfg3; // 04C User Hardware Configuration3 + dwc2_ghwcfg3_t ghwcfg3_bm; +}; +union { + volatile uint32_t ghwcfg4; // 050 User Hardware Configuration4 + dwc2_ghwcfg4_t ghwcfg4_bm; +}; + volatile uint32_t glpmcfg; // 054 Core LPM Configuration + volatile uint32_t gpwrdn; // 058 Power Down + volatile uint32_t gdfifocfg; // 05C DFIFO Software Configuration + volatile uint32_t gadpctl; // 060 ADP Timer, Control and Status uint32_t reserved64[39]; // 064..0FF - volatile uint32_t hptxfsiz; // 100 Host Periodic Tx FIFO Size Register - volatile uint32_t dieptxf[15]; // 104..13C Device Periodic Transmit FIFO Size Register + volatile uint32_t hptxfsiz; // 100 Host Periodic Tx FIFO Size + volatile uint32_t dieptxf[15]; // 104..13C Device Periodic Transmit FIFO Size uint32_t reserved140[176]; // 140..3FF //------------- Host -------------// - volatile uint32_t hcfg; // 400 Host Configuration Register - volatile uint32_t hfir; // 404 Host Frame Interval Register + volatile uint32_t hcfg; // 400 Host Configuration + volatile uint32_t hfir; // 404 Host Frame Interval volatile uint32_t hfnum; // 408 Host Frame Number / Frame Remaining uint32_t reserved40c; // 40C volatile uint32_t hptxsts; // 410 Host Periodic TX FIFO / Queue Status - volatile uint32_t haint; // 414 Host All Channels Interrupt Register + volatile uint32_t haint; // 414 Host All Channels Interrupt volatile uint32_t haintmsk; // 418 Host All Channels Interrupt Mask - volatile uint32_t hflbaddr; // 41C Host Frame List Base Address Register + volatile uint32_t hflbaddr; // 41C Host Frame List Base Address uint32_t reserved420[8]; // 420..43F volatile uint32_t hprt; // 440 Host Port Control and Status uint32_t reserved444[47]; // 444..4FF @@ -133,18 +226,18 @@ union { uint32_t reserved700[64]; // 700..7FF //------------- Device -------------// - volatile uint32_t dcfg; // 800 Device Configuration Register - volatile uint32_t dctl; // 804 Device Control Register - volatile uint32_t dsts; // 808 Device Status Register (RO) + volatile uint32_t dcfg; // 800 Device Configuration + volatile uint32_t dctl; // 804 Device Control + volatile uint32_t dsts; // 808 Device Status (RO) uint32_t reserved80c; // 80C volatile uint32_t diepmsk; // 810 Device IN Endpoint Interrupt Mask volatile uint32_t doepmsk; // 814 Device OUT Endpoint Interrupt Mask volatile uint32_t daint; // 818 Device All Endpoints Interrupt volatile uint32_t daintmsk; // 81C Device All Endpoints Interrupt Mask - volatile uint32_t dtknqr1; // 820 Device IN token sequence learning queue read register1 - volatile uint32_t dtknqr2; // 824 Device IN token sequence learning queue read register2 - volatile uint32_t dvbusdis; // 828 Device VBUS Discharge Time Register - volatile uint32_t dvbuspulse; // 82C Device VBUS Pulsing Time Register + volatile uint32_t dtknqr1; // 820 Device IN token sequence learning queue read1 + volatile uint32_t dtknqr2; // 824 Device IN token sequence learning queue read2 + volatile uint32_t dvbusdis; // 828 Device VBUS Discharge Time + volatile uint32_t dvbuspulse; // 82C Device VBUS Pulsing Time volatile uint32_t dthrctl; // 830 Device threshold Control volatile uint32_t diepempmsk; // 834 Device IN Endpoint FIFO Empty Interrupt Mask volatile uint32_t deachint; // 838 Device Each Endpoint Interrupt @@ -176,23 +269,6 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, epout ) == 0x0B00, "incorrect size"); TU_VERIFY_STATIC(offsetof(dwc2_regs_t, pcgctrl) == 0x0E00, "incorrect size"); TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); -//--------------------------------------------------------------------+ -// Register Base Address -//--------------------------------------------------------------------+ - -#define DWC2_GLOBAL_BASE 0x00000000UL -#define DWC2_DEVICE_BASE 0x00000800UL -#define DWC2_IN_ENDPOINT_BASE 0x00000900UL -#define DWC2_OUT_ENDPOINT_BASE 0x00000B00UL -#define DWC2_EP_REG_SIZE 0x00000020UL -#define DWC2_HOST_BASE 0x00000400UL -#define DWC2_HOST_PORT_BASE 0x00000440UL -#define DWC2_HOST_CHANNEL_BASE 0x00000500UL -#define DWC2_HOST_CHANNEL_SIZE 0x00000020UL -#define DWC2_PCGCCTL_BASE 0x00000E00UL -#define DWC2_FIFO_BASE 0x00001000UL -#define DWC2_FIFO_SIZE 0x00001000UL - //--------------------------------------------------------------------+ // Register Bit Definitions //--------------------------------------------------------------------+ -- cgit v1.3.1 From 9f1cd1a753400327072973cbf2437f6c51bd5509 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 26 Oct 2021 23:10:26 +0700 Subject: add synopsys id check, rename GCCFG_* to STM32_GCCFG-* --- src/portable/synopsys/dwc2/dcd_dwc2.c | 13 +++--- src/portable/synopsys/dwc2/dwc2_type.h | 72 +++++++++++++++++----------------- 2 files changed, 43 insertions(+), 42 deletions(-) diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 7b02c75cd..58305838f 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -401,8 +401,9 @@ void dcd_init (uint8_t rhport) // peripheral in each Reference Manual. dwc2_regs_t * dwc2 = DWC2_REG(rhport); - // check gsnpsid - //TU_LOG_HEX(1, dwc2->gsnpsid); + // Check Synopsys ID + uint32_t const gsnpsid = dwc2->gsnpsid & 0xffff0000u; + TU_ASSERT(gsnpsid == DWC2_OTG_ID || gsnpsid == DWC2_FS_IOT_ID || gsnpsid == DWC2_HS_IOT_ID, ); print_dwc2_info(dwc2); @@ -412,7 +413,7 @@ void dcd_init (uint8_t rhport) // On selected MCUs HS port1 can be used with external PHY via ULPI interface #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED // deactivate internal PHY - dwc2->stm32_gccfg &= ~GCCFG_PWRDWN; + dwc2->stm32_gccfg &= ~STM32_GCCFG_PWRDWN; // Init The UTMI Interface dwc2->gusbcfg &= ~(GUSBCFG_TSDPS | GUSBCFG_ULPIFSLS | GUSBCFG_PHYSEL); @@ -428,7 +429,7 @@ void dcd_init (uint8_t rhport) // Select UTMI Interface dwc2->gusbcfg &= ~GUSBCFG_ULPI_UTMI_SEL; - dwc2->stm32_gccfg |= GCCFG_PHYHSEN; + dwc2->stm32_gccfg |= STM32_GCCFG_PHYHSEN; // Enables control of a High Speed USB PHY USB_HS_PHYCInit(); @@ -463,7 +464,7 @@ void dcd_init (uint8_t rhport) set_speed(rhport, TUD_OPT_HIGH_SPEED ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL); // Enable internal USB transceiver, unless using HS core (port 1) with external PHY. - if (!(rhport == 1 && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED))) dwc2->stm32_gccfg |= GCCFG_PWRDWN; + if (!(rhport == 1 && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED))) dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN; dwc2->gintmsk |= GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_USBSUSPM | GINTMSK_WUIM | GINTMSK_RXFLVLM; @@ -546,7 +547,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) xfer->max_size = tu_edpt_packet_size(desc_edpt); xfer->interval = desc_edpt->bInterval; - uint16_t const fifo_size = (xfer->max_size + 3) / 4; // Round up to next full word + uint16_t const fifo_size = tu_div_ceil(xfer->max_size, 4); if(dir == TUSB_DIR_OUT) { diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index 58e628970..113f99180 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -1051,42 +1051,42 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define DEACHINT_OEP1INT DEACHINT_OEP1INT_Msk // OUT endpoint 1 interrupt bit */ /******************** Bit definition for GCCFG register ********************/ -#define GCCFG_DCDET_Pos (0U) -#define GCCFG_DCDET_Msk (0x1UL << GCCFG_DCDET_Pos) // 0x00000001 */ -#define GCCFG_DCDET GCCFG_DCDET_Msk // Data contact detection (DCD) status */ -#define GCCFG_PDET_Pos (1U) -#define GCCFG_PDET_Msk (0x1UL << GCCFG_PDET_Pos) // 0x00000002 */ -#define GCCFG_PDET GCCFG_PDET_Msk // Primary detection (PD) status */ -#define GCCFG_SDET_Pos (2U) -#define GCCFG_SDET_Msk (0x1UL << GCCFG_SDET_Pos) // 0x00000004 */ -#define GCCFG_SDET GCCFG_SDET_Msk // Secondary detection (SD) status */ -#define GCCFG_PS2DET_Pos (3U) -#define GCCFG_PS2DET_Msk (0x1UL << GCCFG_PS2DET_Pos) // 0x00000008 */ -#define GCCFG_PS2DET GCCFG_PS2DET_Msk // DM pull-up detection status */ -#define GCCFG_PWRDWN_Pos (16U) -#define GCCFG_PWRDWN_Msk (0x1UL << GCCFG_PWRDWN_Pos) // 0x00010000 */ -#define GCCFG_PWRDWN GCCFG_PWRDWN_Msk // Power down */ -#define GCCFG_BCDEN_Pos (17U) -#define GCCFG_BCDEN_Msk (0x1UL << GCCFG_BCDEN_Pos) // 0x00020000 */ -#define GCCFG_BCDEN GCCFG_BCDEN_Msk // Battery charging detector (BCD) enable */ -#define GCCFG_DCDEN_Pos (18U) -#define GCCFG_DCDEN_Msk (0x1UL << GCCFG_DCDEN_Pos) // 0x00040000 */ -#define GCCFG_DCDEN GCCFG_DCDEN_Msk // Data contact detection (DCD) mode enable*/ -#define GCCFG_PDEN_Pos (19U) -#define GCCFG_PDEN_Msk (0x1UL << GCCFG_PDEN_Pos) // 0x00080000 */ -#define GCCFG_PDEN GCCFG_PDEN_Msk // Primary detection (PD) mode enable*/ -#define GCCFG_SDEN_Pos (20U) -#define GCCFG_SDEN_Msk (0x1UL << GCCFG_SDEN_Pos) // 0x00100000 */ -#define GCCFG_SDEN GCCFG_SDEN_Msk // Secondary detection (SD) mode enable */ -#define GCCFG_VBDEN_Pos (21U) -#define GCCFG_VBDEN_Msk (0x1UL << GCCFG_VBDEN_Pos) // 0x00200000 */ -#define GCCFG_VBDEN GCCFG_VBDEN_Msk // VBUS mode enable */ -#define GCCFG_OTGIDEN_Pos (22U) -#define GCCFG_OTGIDEN_Msk (0x1UL << GCCFG_OTGIDEN_Pos) // 0x00400000 */ -#define GCCFG_OTGIDEN GCCFG_OTGIDEN_Msk // OTG Id enable */ -#define GCCFG_PHYHSEN_Pos (23U) -#define GCCFG_PHYHSEN_Msk (0x1UL << GCCFG_PHYHSEN_Pos) // 0x00800000 */ -#define GCCFG_PHYHSEN GCCFG_PHYHSEN_Msk // HS PHY enable */ +#define STM32_GCCFG_DCDET_Pos (0U) +#define STM32_GCCFG_DCDET_Msk (0x1UL << STM32_GCCFG_DCDET_Pos) // 0x00000001 */ +#define STM32_GCCFG_DCDET STM32_GCCFG_DCDET_Msk // Data contact detection (DCD) status */ +#define STM32_GCCFG_PDET_Pos (1U) +#define STM32_GCCFG_PDET_Msk (0x1UL << STM32_GCCFG_PDET_Pos) // 0x00000002 */ +#define STM32_GCCFG_PDET STM32_GCCFG_PDET_Msk // Primary detection (PD) status */ +#define STM32_GCCFG_SDET_Pos (2U) +#define STM32_GCCFG_SDET_Msk (0x1UL << STM32_GCCFG_SDET_Pos) // 0x00000004 */ +#define STM32_GCCFG_SDET STM32_GCCFG_SDET_Msk // Secondary detection (SD) status */ +#define STM32_GCCFG_PS2DET_Pos (3U) +#define STM32_GCCFG_PS2DET_Msk (0x1UL << STM32_GCCFG_PS2DET_Pos) // 0x00000008 */ +#define STM32_GCCFG_PS2DET STM32_GCCFG_PS2DET_Msk // DM pull-up detection status */ +#define STM32_GCCFG_PWRDWN_Pos (16U) +#define STM32_GCCFG_PWRDWN_Msk (0x1UL << STM32_GCCFG_PWRDWN_Pos) // 0x00010000 */ +#define STM32_GCCFG_PWRDWN STM32_GCCFG_PWRDWN_Msk // Power down */ +#define STM32_GCCFG_BCDEN_Pos (17U) +#define STM32_GCCFG_BCDEN_Msk (0x1UL << STM32_GCCFG_BCDEN_Pos) // 0x00020000 */ +#define STM32_GCCFG_BCDEN STM32_GCCFG_BCDEN_Msk // Battery charging detector (BCD) enable */ +#define STM32_GCCFG_DCDEN_Pos (18U) +#define STM32_GCCFG_DCDEN_Msk (0x1UL << STM32_GCCFG_DCDEN_Pos) // 0x00040000 */ +#define STM32_GCCFG_DCDEN STM32_GCCFG_DCDEN_Msk // Data contact detection (DCD) mode enable*/ +#define STM32_GCCFG_PDEN_Pos (19U) +#define STM32_GCCFG_PDEN_Msk (0x1UL << STM32_GCCFG_PDEN_Pos) // 0x00080000 */ +#define STM32_GCCFG_PDEN STM32_GCCFG_PDEN_Msk // Primary detection (PD) mode enable*/ +#define STM32_GCCFG_SDEN_Pos (20U) +#define STM32_GCCFG_SDEN_Msk (0x1UL << STM32_GCCFG_SDEN_Pos) // 0x00100000 */ +#define STM32_GCCFG_SDEN STM32_GCCFG_SDEN_Msk // Secondary detection (SD) mode enable */ +#define STM32_GCCFG_VBDEN_Pos (21U) +#define STM32_GCCFG_VBDEN_Msk (0x1UL << STM32_GCCFG_VBDEN_Pos) // 0x00200000 */ +#define STM32_GCCFG_VBDEN STM32_GCCFG_VBDEN_Msk // VBUS mode enable */ +#define STM32_GCCFG_OTGIDEN_Pos (22U) +#define STM32_GCCFG_OTGIDEN_Msk (0x1UL << STM32_GCCFG_OTGIDEN_Pos) // 0x00400000 */ +#define STM32_GCCFG_OTGIDEN STM32_GCCFG_OTGIDEN_Msk // OTG Id enable */ +#define STM32_GCCFG_PHYHSEN_Pos (23U) +#define STM32_GCCFG_PHYHSEN_Msk (0x1UL << STM32_GCCFG_PHYHSEN_Pos) // 0x00800000 */ +#define STM32_GCCFG_PHYHSEN STM32_GCCFG_PHYHSEN_Msk // HS PHY enable */ /******************** Bit definition for DEACHINTMSK register ********************/ #define DEACHINTMSK_IEP1INTM_Pos (1U) -- cgit v1.3.1 From 49aa69a301abfc86e1182d329c1f3b586cdcf204 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 26 Oct 2021 23:57:48 +0700 Subject: update bcm dcd --- src/device/dcd_attr.h | 2 +- src/portable/broadcom/synopsys/dcd_synopsys.c | 18 +++++++++--------- src/portable/st/synopsys/dcd_synopsys.c | 2 +- 3 files changed, 11 insertions(+), 11 deletions(-) diff --git a/src/device/dcd_attr.h b/src/device/dcd_attr.h index 61f31e38a..90f3a526a 100644 --- a/src/device/dcd_attr.h +++ b/src/device/dcd_attr.h @@ -181,7 +181,7 @@ #define DCD_ATTR_ENDPOINT_MAX 4 //------------- Broadcom -------------// -#elif TU_CHECK_MCU(BCM2711) +#elif TU_CHECK_MCU(OPT_MCU_BCM2711) #define DCD_ATTR_ENDPOINT_MAX 8 #else diff --git a/src/portable/broadcom/synopsys/dcd_synopsys.c b/src/portable/broadcom/synopsys/dcd_synopsys.c index 87150f683..041158871 100644 --- a/src/portable/broadcom/synopsys/dcd_synopsys.c +++ b/src/portable/broadcom/synopsys/dcd_synopsys.c @@ -37,9 +37,9 @@ // We disable SOF for now until needed later on #define USE_SOF 0 -#if TUSB_OPT_DEVICE_ENABLED && \ - ( (CFG_TUSB_MCU == OPT_MCU_BCM2711 ) \ - ) +#if TUSB_OPT_DEVICE_ENABLED && \ + (CFG_TUSB_MCU == OPT_MCU_BCM2711 ) \ + // EP_MAX : Max number of bi-directional endpoints including EP0 // EP_FIFO_SIZE : Size of dedicated USB SRAM @@ -656,10 +656,10 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) TU_ASSERT(epnum < EP_MAX); xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir); - xfer->max_size = desc_edpt->wMaxPacketSize.size; + xfer->max_size = tu_edpt_packet_size(desc_edpt); xfer->interval = desc_edpt->bInterval; - uint16_t const fifo_size = (desc_edpt->wMaxPacketSize.size + 3) / 4; // Round up to next full word + uint16_t const fifo_size = (xfer->max_size + 3) / 4; // Round up to next full word if(dir == TUSB_DIR_OUT) { @@ -678,7 +678,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) out_ep[epnum].DOEPCTL |= (1 << USB_OTG_DOEPCTL_USBAEP_Pos) | (desc_edpt->bmAttributes.xfer << USB_OTG_DOEPCTL_EPTYP_Pos) | (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_OTG_DOEPCTL_SD0PID_SEVNFRM : 0) | - (desc_edpt->wMaxPacketSize.size << USB_OTG_DOEPCTL_MPSIZ_Pos); + (xfer->max_size << USB_OTG_DOEPCTL_MPSIZ_Pos); dev->DAINTMSK |= (1 << (USB_OTG_DAINTMSK_OEPM_Pos + epnum)); } @@ -720,7 +720,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) (epnum << USB_OTG_DIEPCTL_TXFNUM_Pos) | (desc_edpt->bmAttributes.xfer << USB_OTG_DIEPCTL_EPTYP_Pos) | (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_OTG_DIEPCTL_SD0PID_SEVNFRM : 0) | - (desc_edpt->wMaxPacketSize.size << USB_OTG_DIEPCTL_MPSIZ_Pos); + (xfer->max_size << USB_OTG_DIEPCTL_MPSIZ_Pos); dev->DAINTMSK |= (1 << (USB_OTG_DAINTMSK_IEPM_Pos + epnum)); } @@ -1010,7 +1010,7 @@ static void handle_rxflvl_ints(uint8_t rhport, USB_OTG_OUTEndpointTypeDef * out_ if (xfer->ff) { // Ring buffer - tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void *) rx_fifo, bcnt); + tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void *)(uintptr_t) rx_fifo, bcnt); } else { @@ -1130,7 +1130,7 @@ static void handle_epin_ints(uint8_t rhport, USB_OTG_DeviceTypeDef * dev, USB_OT if (xfer->ff) { usb_fifo_t tx_fifo = FIFO_BASE(rhport, n); - tu_fifo_read_n_const_addr_full_words(xfer->ff, (void *) tx_fifo, packet_size); + tu_fifo_read_n_const_addr_full_words(xfer->ff, (void *)(uintptr_t) tx_fifo, packet_size); } else { diff --git a/src/portable/st/synopsys/dcd_synopsys.c b/src/portable/st/synopsys/dcd_synopsys.c index 4e2bbd076..4782ead8c 100644 --- a/src/portable/st/synopsys/dcd_synopsys.c +++ b/src/portable/st/synopsys/dcd_synopsys.c @@ -370,7 +370,7 @@ static bool USB_HS_PHYCInit(void) { USB_HS_PHYC_GlobalTypeDef *usb_hs_phyc = (USB_HS_PHYC_GlobalTypeDef*) USB_HS_PHYC_CONTROLLER_BASE; - // Enable LDO + // Enable LDO: Note STM32F72/3xx Reference Manual rev 3 June 2018 incorrectly defined this bit as Disabled !! usb_hs_phyc->USB_HS_PHYC_LDO |= USB_HS_PHYC_LDO_ENABLE; // Wait until LDO ready -- cgit v1.3.1 From 7def38005853df94a61365c52cae27e8cba2cf81 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 28 Oct 2021 12:52:18 +0700 Subject: support bcm2711 on pi4, enhance dcd init with utmi and ulpi hs phy --- hw/bsp/raspberrypi4/family.mk | 8 +- hw/bsp/stm32f7/boards/stm32f723disco/board.mk | 3 + hw/bsp/stm32f7/family.mk | 2 +- hw/bsp/stm32h7/family.mk | 2 +- src/portable/synopsys/dwc2/dcd_dwc2.c | 162 +++++++++++++------------- src/portable/synopsys/dwc2/dwc2_bcm.h | 72 ++++++++++++ src/portable/synopsys/dwc2/dwc2_stm32.h | 49 +++++++- src/portable/synopsys/dwc2/dwc2_type.h | 46 +++++--- 8 files changed, 242 insertions(+), 102 deletions(-) create mode 100644 src/portable/synopsys/dwc2/dwc2_bcm.h diff --git a/hw/bsp/raspberrypi4/family.mk b/hw/bsp/raspberrypi4/family.mk index 0424b2154..b0326c056 100644 --- a/hw/bsp/raspberrypi4/family.mk +++ b/hw/bsp/raspberrypi4/family.mk @@ -16,8 +16,11 @@ CFLAGS += \ -mgeneral-regs-only \ -DCFG_TUSB_MCU=OPT_MCU_BCM2711 +# mcu driver cause following warnings +CFLAGS += -Wno-error=cast-qual + SRC_C += \ - src/portable/broadcom/synopsys/dcd_synopsys.c \ + src/portable/synopsys/dwc2/dcd_dwc2.c \ $(MCU_DIR)/broadcom/gen/interrupt_handlers.c \ $(MCU_DIR)/broadcom/interrupts.c \ $(MCU_DIR)/broadcom/io.c \ @@ -39,3 +42,6 @@ SRC_S += $(MCU_DIR)/broadcom/boot.S $(BUILD)/kernel8.img: $(BUILD)/$(PROJECT).elf $(OBJCOPY) -O binary $^ $@ + +flash: $(BUILD)/kernel8.img + @$(CP) $< /home/$(USER)/Documents/code/pi4_tinyusb/boot_cpy diff --git a/hw/bsp/stm32f7/boards/stm32f723disco/board.mk b/hw/bsp/stm32f7/boards/stm32f723disco/board.mk index 8f05199d0..66d9ff8fb 100644 --- a/hw/bsp/stm32f7/boards/stm32f723disco/board.mk +++ b/hw/bsp/stm32f7/boards/stm32f723disco/board.mk @@ -10,3 +10,6 @@ SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f723xx.s # flash target using on-board stlink flash: flash-stlink + +# For flash-jlink target +JLINK_DEVICE = stm32f723ie diff --git a/hw/bsp/stm32f7/family.mk b/hw/bsp/stm32f7/family.mk index ead0c977a..8482e6dd2 100644 --- a/hw/bsp/stm32f7/family.mk +++ b/hw/bsp/stm32f7/family.mk @@ -34,7 +34,7 @@ endif CFLAGS += -Wno-error=shadow -Wno-error=cast-align SRC_C += \ - src/portable/st/synopsys/dcd_synopsys.c \ + src/portable/synopsys/dwc2/dcd_dwc2.c \ $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \ $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \ $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \ diff --git a/hw/bsp/stm32h7/family.mk b/hw/bsp/stm32h7/family.mk index e35e75610..6a257e22d 100644 --- a/hw/bsp/stm32h7/family.mk +++ b/hw/bsp/stm32h7/family.mk @@ -30,7 +30,7 @@ CFLAGS += -Wno-error=maybe-uninitialized -Wno-error=cast-align # All source paths should be relative to the top level. SRC_C += \ - src/portable/st/synopsys/dcd_synopsys.c \ + src/portable/synopsys/dwc2/dcd_dwc2.c \ $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \ $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \ $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \ diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 58305838f..0d2766c38 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -31,7 +31,7 @@ #include "device/dcd_attr.h" #if TUSB_OPT_DEVICE_ENABLED && \ - ( defined(DCD_ATTR_DWC2_STM32) || TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3, OPT_MCU_GD32VF103) ) + ( defined(DCD_ATTR_DWC2_STM32) || TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3, OPT_MCU_GD32VF103, OPT_MCU_BCM2711) ) #include "device/dcd.h" #include "dwc2_type.h" @@ -42,6 +42,8 @@ #include "dwc2_esp32.h" #elif TU_CHECK_MCU(OPT_MCU_GD32VF103) #include "dwc2_gd32.h" +#elif TU_CHECK_MCU(OPT_MCU_BCM2711) + #include "dwc2_bcm.h" #else #error "Unsupported MCUs" #endif @@ -185,7 +187,7 @@ static void bus_reset(uint8_t rhport) _allocated_fifo_words_tx = 16; // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word ) - dwc2->dieptxf0 = (16 << TX0FD_Pos) | (DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx); + dwc2->dieptxf0 = (16 << DIEPTXF0_TX0FD_Pos) | (DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx); // Fixed control EP0 size to 64 bytes dwc2->epin[0].diepctl &= ~(0x03 << DIEPCTL_MPSIZ_Pos); @@ -226,47 +228,6 @@ static void set_speed(uint8_t rhport, tusb_speed_t speed) dwc2->dcfg |= (bitvalue << DCFG_DSPD_Pos); } -#if defined(USB_HS_PHYC) -static bool USB_HS_PHYCInit(void) -{ - USB_HS_PHYC_GlobalTypeDef *usb_hs_phyc = (USB_HS_PHYC_GlobalTypeDef*) USB_HS_PHYC_CONTROLLER_BASE; - - // Enable LDO - usb_hs_phyc->USB_HS_PHYC_LDO |= USB_HS_PHYC_LDO_ENABLE; - - // Wait until LDO ready - while ( 0 == (usb_hs_phyc->USB_HS_PHYC_LDO & USB_HS_PHYC_LDO_STATUS) ) {} - - uint32_t phyc_pll = 0; - - // TODO Try to get HSE_VALUE from registers instead of depending CFLAGS - switch ( HSE_VALUE ) - { - case 12000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12MHZ ; break; - case 12500000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12_5MHZ ; break; - case 16000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_16MHZ ; break; - case 24000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_24MHZ ; break; - case 25000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_25MHZ ; break; - case 32000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_Msk ; break; // Value not defined in header - default: - TU_ASSERT(0); - } - usb_hs_phyc->USB_HS_PHYC_PLL = phyc_pll; - - // Control the tuning interface of the High Speed PHY - // Use magic value (USB_HS_PHYC_TUNE_VALUE) from ST driver - usb_hs_phyc->USB_HS_PHYC_TUNE |= 0x00000F13U; - - // Enable PLL internal PHY - usb_hs_phyc->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN; - - // Original ST code has 2 ms delay for PLL stabilization. - // Primitive test shows that more than 10 USB un/replug cycle showed no error with enumeration - - return true; -} -#endif - static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t const dir, uint16_t const num_packets, uint16_t total_bytes) { (void) rhport; @@ -369,7 +330,7 @@ void print_dwc2_info(dwc2_regs_t * dwc2) TU_LOG_INT(1, hw_cfg3->synch_reset ); TU_LOG_INT(1, hw_cfg3->otg_adp_support ); TU_LOG_INT(1, hw_cfg3->otg_enable_hsic ); - TU_LOG_INT(1, hw_cfg3->otg_bc_support ); + TU_LOG_INT(1, hw_cfg3->battery_charger_support ); TU_LOG_INT(1, hw_cfg3->lpm_mode ); TU_LOG_INT(1, hw_cfg3->total_fifo_size ); @@ -395,56 +356,102 @@ void print_dwc2_info(dwc2_regs_t * dwc2) TU_LOG_INT(1, hw_cfg4->dma_dynamic ); } +static void reset_core(dwc2_regs_t * dwc2) +{ + // reset core + dwc2->grstctl |= GRSTCTL_CSRST; + + // wait for reset bit is cleared + // TODO version 4.20a should wait for RESET DONE mask + while (dwc2->grstctl & GRSTCTL_CSRST) { } + + // wait for AHB master IDLE + while ( !(dwc2->grstctl & GRSTCTL_AHBIDL) ) { } + + // wait for device mode ? +} + void dcd_init (uint8_t rhport) { // Programming model begins in the last section of the chapter on the USB // peripheral in each Reference Manual. dwc2_regs_t * dwc2 = DWC2_REG(rhport); - // Check Synopsys ID - uint32_t const gsnpsid = dwc2->gsnpsid & 0xffff0000u; + // Check Synopsys ID, failed if controller is not enabled + uint32_t const gsnpsid = dwc2->gsnpsid & GSNPSID_ID_MASK; TU_ASSERT(gsnpsid == DWC2_OTG_ID || gsnpsid == DWC2_FS_IOT_ID || gsnpsid == DWC2_HS_IOT_ID, ); print_dwc2_info(dwc2); - // No HNP/SRP (no OTG support), program timeout later. - if ( rhport == 1 ) + // Force device mode + dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FHMOD) | GUSBCFG_FDMOD; + + uint32_t const hs_phy_type = dwc2->ghwcfg2_bm.hs_phy_type; + + if( !TUD_OPT_HIGH_SPEED || hs_phy_type == HS_PHY_TYPE_NONE) { - // On selected MCUs HS port1 can be used with external PHY via ULPI interface -#if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED - // deactivate internal PHY + // max speed is full or core does not support highspeed + TU_LOG2("Fullspeed PHY init\r\n"); + + // Select FS PHY + dwc2->gusbcfg |= GUSBCFG_PHYSEL; + + // Reset core after selecting PHY + reset_core(dwc2); + + #if defined(DCD_ATTR_DWC2_STM32) + // activate FS PHY on stm32 + dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN; + #endif + }else + { + // Highspeed mode + + #if defined(DCD_ATTR_DWC2_STM32) + // Disable STM32 FS PHY dwc2->stm32_gccfg &= ~STM32_GCCFG_PWRDWN; + #endif - // Init The UTMI Interface - dwc2->gusbcfg &= ~(GUSBCFG_TSDPS | GUSBCFG_ULPIFSLS | GUSBCFG_PHYSEL); + uint32_t gusbcfg = dwc2->gusbcfg; - // Select default internal VBUS Indicator and Drive for ULPI - dwc2->gusbcfg &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI); -#else - dwc2->gusbcfg |= GUSBCFG_PHYSEL; -#endif + // De-select FS PHY + gusbcfg &= ~GUSBCFG_PHYSEL; -#if defined(USB_HS_PHYC) - // Highspeed with embedded UTMI PHYC + if (hs_phy_type == HS_PHY_TYPE_ULPI) + { + TU_LOG2("Highspeed ULPI PHY init\r\n"); - // Select UTMI Interface - dwc2->gusbcfg &= ~GUSBCFG_ULPI_UTMI_SEL; - dwc2->stm32_gccfg |= STM32_GCCFG_PHYHSEN; + // Select ULPI + gusbcfg |= GUSBCFG_ULPI_UTMI_SEL; - // Enables control of a High Speed USB PHY - USB_HS_PHYCInit(); -#endif - } else - { - // Enable internal PHY - dwc2->gusbcfg |= GUSBCFG_PHYSEL; - } + // ULPI 8-bit interface, single data rate + gusbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL); - // Reset core after selecting PHYst - // Wait AHB IDLE, reset then wait until it is cleared - while ((dwc2->grstctl & GRSTCTL_AHBIDL) == 0U) {} - dwc2->grstctl |= GRSTCTL_CSRST; - while ((dwc2->grstctl & GRSTCTL_CSRST) == GRSTCTL_CSRST) {} + // default internal VBUS Indicator and Drive + gusbcfg &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI); + + // Disable FS/LS ULPI + gusbcfg &= ~(GUSBCFG_ULPIFSLS | GUSBCFG_ULPICSM); + }else + { + TU_LOG2("Highspeed UTMI+ PHY init\r\n"); + + // Select UTMI+ with 8-bit interface + gusbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16); + + // Set 16-bit interface if supported + if (dwc2->ghwcfg4_bm.utmi_phy_data_width) gusbcfg |= GUSBCFG_PHYIF16; + + #if defined(DCD_ATTR_DWC2_STM32) && defined(USB_HS_PHYC) + dwc2_stm32_utmi_phy_init(dwc2); + #endif + } + + dwc2->gusbcfg = gusbcfg; + + // Reset core after selecting PHY + reset_core(dwc2); + } // Restart PHY clock dwc2->pcgctrl = 0; @@ -463,9 +470,6 @@ void dcd_init (uint8_t rhport) set_speed(rhport, TUD_OPT_HIGH_SPEED ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL); - // Enable internal USB transceiver, unless using HS core (port 1) with external PHY. - if (!(rhport == 1 && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED))) dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN; - dwc2->gintmsk |= GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_USBSUSPM | GINTMSK_WUIM | GINTMSK_RXFLVLM; diff --git a/src/portable/synopsys/dwc2/dwc2_bcm.h b/src/portable/synopsys/dwc2/dwc2_bcm.h new file mode 100644 index 000000000..da1f23ae0 --- /dev/null +++ b/src/portable/synopsys/dwc2/dwc2_bcm.h @@ -0,0 +1,72 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef _TUSB_DWC2_BCM_H_ +#define _TUSB_DWC2_BCM_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "broadcom/interrupts.h" + +#define DWC2_REG_BASE 0xFE980000UL +#define DWC2_EP_MAX 8 +#define DWC2_EP_FIFO_SIZE 4096 + +TU_ATTR_ALWAYS_INLINE +static inline void dwc2_dcd_int_enable(uint8_t rhport) +{ + (void) rhport; + BP_EnableIRQ(USB_IRQn); +} + +TU_ATTR_ALWAYS_INLINE +static inline void dwc2_dcd_int_disable (uint8_t rhport) +{ + (void) rhport; + BP_DisableIRQ(USB_IRQn); +} + +TU_ATTR_ALWAYS_INLINE +static inline void dwc2_remote_wakeup_delay(void) +{ + // try to delay for 1 ms + // TODO implement later +} + +static inline void dwc2_set_turnaround(dwc2_regs_t * core, tusb_speed_t speed) +{ + // TODO implement later + (void) core; + (void) speed; +} + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h index 236936d66..b77cda2ca 100644 --- a/src/portable/synopsys/dwc2/dwc2_stm32.h +++ b/src/portable/synopsys/dwc2/dwc2_stm32.h @@ -113,14 +113,14 @@ static inline void dwc2_remote_wakeup_delay(void) } // Set turn-around timeout according to link speed -static inline void dwc2_set_turnaround(dwc2_regs_t * core, tusb_speed_t speed) +static inline void dwc2_set_turnaround(dwc2_regs_t * dwc2, tusb_speed_t speed) { - core->gusbcfg &= ~GUSBCFG_TRDT; + dwc2->gusbcfg &= ~GUSBCFG_TRDT; if ( speed == TUSB_SPEED_HIGH ) { // Use fixed 0x09 for Highspeed - core->gusbcfg |= (0x09 << GUSBCFG_TRDT_Pos); + dwc2->gusbcfg |= (0x09 << GUSBCFG_TRDT_Pos); } else { @@ -149,11 +149,52 @@ static inline void dwc2_set_turnaround(dwc2_regs_t * core, tusb_speed_t speed) turnaround = 0xFU; // Fullspeed depends on MCU clocks, but we will use 0x06 for 32+ Mhz - core->gusbcfg |= (turnaround << GUSBCFG_TRDT_Pos); + dwc2->gusbcfg |= (turnaround << GUSBCFG_TRDT_Pos); } } +#if defined(USB_HS_PHYC) +static inline void dwc2_stm32_utmi_phy_init(dwc2_regs_t * dwc2) +{ + USB_HS_PHYC_GlobalTypeDef *usb_hs_phyc = (USB_HS_PHYC_GlobalTypeDef*) USB_HS_PHYC_CONTROLLER_BASE; + + // Enable UTMI HS PHY + dwc2->stm32_gccfg |= STM32_GCCFG_PHYHSEN; + + // Enable LDO + usb_hs_phyc->USB_HS_PHYC_LDO |= USB_HS_PHYC_LDO_ENABLE; + + // Wait until LDO ready + while ( 0 == (usb_hs_phyc->USB_HS_PHYC_LDO & USB_HS_PHYC_LDO_STATUS) ) {} + uint32_t phyc_pll = 0; + + // TODO Try to get HSE_VALUE from registers instead of depending CFLAGS + switch ( HSE_VALUE ) + { + case 12000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12MHZ ; break; + case 12500000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12_5MHZ ; break; + case 16000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_16MHZ ; break; + case 24000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_24MHZ ; break; + case 25000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_25MHZ ; break; + case 32000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_Msk ; break; // Value not defined in header + default: + TU_ASSERT(false, ); + } + usb_hs_phyc->USB_HS_PHYC_PLL = phyc_pll; + + // Control the tuning interface of the High Speed PHY + // Use magic value (USB_HS_PHYC_TUNE_VALUE) from ST driver + usb_hs_phyc->USB_HS_PHYC_TUNE |= 0x00000F13U; + + // Enable PLL internal PHY + usb_hs_phyc->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN; + + // Original ST code has 2 ms delay for PLL stabilization. + // Primitive test shows that more than 10 USB un/replug cycle showed no error with enumeration +} + +#endif #ifdef __cplusplus } diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index 113f99180..5ded366d7 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -58,6 +58,13 @@ typedef struct } HS_PHYC_GlobalTypeDef; #endif +enum { + HS_PHY_TYPE_NONE = 0 , + HS_PHY_TYPE_UTMI , // internal PHY (mostly) + HS_PHY_TYPE_ULPI , // external PHY + HS_PHY_TYPE_UTMI_ULPI , +}; + typedef struct TU_ATTR_PACKED { uint32_t op_mode : 3; // 0: HNP and SRP | 1: SRP | 2: non-HNP, non-SRP @@ -90,7 +97,7 @@ typedef struct TU_ATTR_PACKED uint32_t synch_reset : 1; // 0: async reset | 1: synch reset uint32_t otg_adp_support : 1; // ADP logic is present along with HSOTG controller uint32_t otg_enable_hsic : 1; // 1: HSIC-capable with shared UTMI PHY interface | 0: non-HSIC - uint32_t otg_bc_support : 1; // support battery charger + uint32_t battery_charger_support : 1; // support battery charger uint32_t lpm_mode : 1; // LPC mode uint32_t total_fifo_size : 16; // DFIFO depth value in terms of 32-bit words }dwc2_ghwcfg3_t; @@ -494,6 +501,8 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define GAHBCFG_PTXFELVL_Msk (0x1UL << GAHBCFG_PTXFELVL_Pos) // 0x00000100 */ #define GAHBCFG_PTXFELVL GAHBCFG_PTXFELVL_Msk // Periodic TxFIFO empty level */ +#define GSNPSID_ID_MASK TU_GENMASK(31, 16) + /******************** Bit definition for GUSBCFG register ********************/ #define GUSBCFG_TOCAL_Pos (0U) #define GUSBCFG_TOCAL_Msk (0x7UL << GUSBCFG_TOCAL_Pos) // 0x00000007 */ @@ -501,15 +510,16 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define GUSBCFG_TOCAL_0 (0x1UL << GUSBCFG_TOCAL_Pos) // 0x00000001 */ #define GUSBCFG_TOCAL_1 (0x2UL << GUSBCFG_TOCAL_Pos) // 0x00000002 */ #define GUSBCFG_TOCAL_2 (0x4UL << GUSBCFG_TOCAL_Pos) // 0x00000004 */ -#define GUSBCFG_PHYIF_Pos (3U) -#define GUSBCFG_PHYIF_Msk (0x1UL << GUSBCFG_PHYIF_Pos) // 0x00000008 */ -#define GUSBCFG_PHYIF GUSBCFG_PHYIF_Msk // PHY Interface (PHYIf) */ +#define GUSBCFG_PHYIF16_Pos (3U) +#define GUSBCFG_PHYIF16_Msk (0x1UL << GUSBCFG_PHYIF16_Pos) // 0x00000008 */ +#define GUSBCFG_PHYIF16 GUSBCFG_PHYIF16_Msk // PHY Interface (PHYIf) */ #define GUSBCFG_ULPI_UTMI_SEL_Pos (4U) #define GUSBCFG_ULPI_UTMI_SEL_Msk (0x1UL << GUSBCFG_ULPI_UTMI_SEL_Pos) // 0x00000010 */ #define GUSBCFG_ULPI_UTMI_SEL GUSBCFG_ULPI_UTMI_SEL_Msk // ULPI or UTMI+ Select (ULPI_UTMI_Sel) */ #define GUSBCFG_PHYSEL_Pos (6U) #define GUSBCFG_PHYSEL_Msk (0x1UL << GUSBCFG_PHYSEL_Pos) // 0x00000040 */ #define GUSBCFG_PHYSEL GUSBCFG_PHYSEL_Msk // USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */ +#define GUSBCFG_DDRSEL TU_BIT(7) // Single Data Rate (SDR) or Double Data Rate (DDR) or ULPI interface. #define GUSBCFG_SRPCAP_Pos (8U) #define GUSBCFG_SRPCAP_Msk (0x1UL << GUSBCFG_SRPCAP_Pos) // 0x00000100 */ #define GUSBCFG_SRPCAP GUSBCFG_SRPCAP_Msk // SRP-capable */ @@ -587,6 +597,8 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define GRSTCTL_TXFNUM_2 (0x04UL << GRSTCTL_TXFNUM_Pos) // 0x00000100 */ #define GRSTCTL_TXFNUM_3 (0x08UL << GRSTCTL_TXFNUM_Pos) // 0x00000200 */ #define GRSTCTL_TXFNUM_4 (0x10UL << GRSTCTL_TXFNUM_Pos) // 0x00000400 */ +#define GRSTCTL_CSFTRST_DONE_Pos (29) +#define GRSTCTL_CSFTRST_DONE (1u << GRSTCTL_CSFTRST_DONE_Pos) // Reset Done, only available from v4.20a #define GRSTCTL_DMAREQ_Pos (30U) #define GRSTCTL_DMAREQ_Msk (0x1UL << GRSTCTL_DMAREQ_Pos) // 0x40000000 */ #define GRSTCTL_DMAREQ GRSTCTL_DMAREQ_Msk // DMA request signal */ @@ -898,6 +910,7 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define DAINTMSK_OEPM_Msk (0xFFFFUL << DAINTMSK_OEPM_Pos) // 0xFFFF0000 */ #define DAINTMSK_OEPM DAINTMSK_OEPM_Msk // OUT EP interrupt mask bits */ +#if 0 /******************** Bit definition for OTG register ********************/ #define CHNUM_Pos (0U) #define CHNUM_Msk (0xFUL << CHNUM_Pos) // 0x0000000F */ @@ -939,6 +952,7 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define FRMNUM_1 (0x2UL << FRMNUM_Pos) // 0x00400000 */ #define FRMNUM_2 (0x4UL << FRMNUM_Pos) // 0x00800000 */ #define FRMNUM_3 (0x8UL << FRMNUM_Pos) // 0x01000000 */ +#endif /******************** Bit definition for GRXFSIZ register ********************/ #define GRXFSIZ_RXFD_Pos (0U) @@ -951,18 +965,18 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define DVBUSDIS_VBUSDT DVBUSDIS_VBUSDT_Msk // Device VBUS discharge time */ /******************** Bit definition for OTG register ********************/ -#define NPTXFSA_Pos (0U) -#define NPTXFSA_Msk (0xFFFFUL << NPTXFSA_Pos) // 0x0000FFFF */ -#define NPTXFSA NPTXFSA_Msk // Nonperiodic transmit RAM start address */ -#define NPTXFD_Pos (16U) -#define NPTXFD_Msk (0xFFFFUL << NPTXFD_Pos) // 0xFFFF0000 */ -#define NPTXFD NPTXFD_Msk // Nonperiodic TxFIFO depth */ -#define TX0FSA_Pos (0U) -#define TX0FSA_Msk (0xFFFFUL << TX0FSA_Pos) // 0x0000FFFF */ -#define TX0FSA TX0FSA_Msk // Endpoint 0 transmit RAM start address */ -#define TX0FD_Pos (16U) -#define TX0FD_Msk (0xFFFFUL << TX0FD_Pos) // 0xFFFF0000 */ -#define TX0FD TX0FD_Msk // Endpoint 0 TxFIFO depth */ +#define GNPTXFSIZ_NPTXFSA_Pos (0U) +#define GNPTXFSIZ_NPTXFSA_Msk (0xFFFFUL << NPTXFSA_Pos) // 0x0000FFFF */ +#define GNPTXFSIZ_NPTXFSA GNPTXFSIZ_NPTXFSA_Msk // Nonperiodic transmit RAM start address */ +#define GNPTXFSIZ_NPTXFD_Pos (16U) +#define GNPTXFSIZ_NPTXFD_Msk (0xFFFFUL << NPTXFD_Pos) // 0xFFFF0000 */ +#define GNPTXFSIZ_NPTXFD GNPTXFSIZ_NPTXFD_Msk // Nonperiodic TxFIFO depth */ +#define DIEPTXF0_TX0FSA_Pos (0U) +#define DIEPTXF0_TX0FSA_Msk (0xFFFFUL << TX0FSA_Pos) // 0x0000FFFF */ +#define DIEPTXF0_TX0FSA DIEPTXF0_TX0FSA_Msk // Endpoint 0 transmit RAM start address */ +#define DIEPTXF0_TX0FD_Pos (16U) +#define DIEPTXF0_TX0FD_Msk (0xFFFFUL << TX0FD_Pos) // 0xFFFF0000 */ +#define DIEPTXF0_TX0FD DIEPTXF0_TX0FD_Msk // Endpoint 0 TxFIFO depth */ /******************** Bit definition for DVBUSPULSE register ********************/ #define DVBUSPULSE_DVBUSP_Pos (0U) -- cgit v1.3.1 From 6c67fc412516950622a13fb34ddc10b64b9b3843 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 29 Oct 2021 00:53:30 +0700 Subject: correctly init hs phy for bcm --- examples/device/cdc_msc/src/tusb_config.h | 5 +- examples/device/hid_composite/src/tusb_config.h | 4 +- src/common/tusb_types.h | 4 +- src/portable/synopsys/dwc2/dcd_dwc2.c | 211 ++++++++++++++---------- src/portable/synopsys/dwc2/dwc2_type.h | 166 +++++++++---------- 5 files changed, 204 insertions(+), 186 deletions(-) diff --git a/examples/device/cdc_msc/src/tusb_config.h b/examples/device/cdc_msc/src/tusb_config.h index a3802f536..499966cb4 100644 --- a/examples/device/cdc_msc/src/tusb_config.h +++ b/examples/device/cdc_msc/src/tusb_config.h @@ -47,9 +47,8 @@ // RHPort max operational speed can defined by board.mk // Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed #ifndef BOARD_DEVICE_RHPORT_SPEED - #if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \ - CFG_TUSB_MCU == OPT_MCU_NUC505 || CFG_TUSB_MCU == OPT_MCU_CXD56 || CFG_TUSB_MCU == OPT_MCU_SAMX7X || \ - CFG_TUSB_MCU == OPT_MCU_BCM2711) + #if TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX, OPT_MCU_MIMXRT10XX, OPT_MCU_NUC505) ||\ + TU_CHECK_MCU(OPT_MCU_CXD56, OPT_MCU_SAMX7X, OPT_MCU_BCM2711) #define BOARD_DEVICE_RHPORT_SPEED OPT_MODE_HIGH_SPEED #else #define BOARD_DEVICE_RHPORT_SPEED OPT_MODE_FULL_SPEED diff --git a/examples/device/hid_composite/src/tusb_config.h b/examples/device/hid_composite/src/tusb_config.h index 868424e6d..8fa5e5cd4 100644 --- a/examples/device/hid_composite/src/tusb_config.h +++ b/examples/device/hid_composite/src/tusb_config.h @@ -47,8 +47,8 @@ // RHPort max operational speed can defined by board.mk // Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed #ifndef BOARD_DEVICE_RHPORT_SPEED - #if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \ - CFG_TUSB_MCU == OPT_MCU_NUC505 || CFG_TUSB_MCU == OPT_MCU_CXD56 || CFG_TUSB_MCU == OPT_MCU_SAMX7X) + #if TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX, OPT_MCU_MIMXRT10XX, OPT_MCU_NUC505) ||\ + TU_CHECK_MCU(OPT_MCU_CXD56, OPT_MCU_SAMX7X, OPT_MCU_BCM2711) #define BOARD_DEVICE_RHPORT_SPEED OPT_MODE_HIGH_SPEED #else #define BOARD_DEVICE_RHPORT_SPEED OPT_MODE_FULL_SPEED diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h index 233def466..5b26f5aec 100644 --- a/src/common/tusb_types.h +++ b/src/common/tusb_types.h @@ -47,8 +47,8 @@ typedef enum { TUSB_SPEED_FULL = 0, - TUSB_SPEED_LOW , - TUSB_SPEED_HIGH, + TUSB_SPEED_LOW = 1, + TUSB_SPEED_HIGH = 2, TUSB_SPEED_INVALID = 0xff, }tusb_speed_t; diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 0d2766c38..ce9b58e03 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -199,35 +199,6 @@ static void bus_reset(uint8_t rhport) dwc2->gintmsk |= GINTMSK_OEPINT | GINTMSK_IEPINT; } - -static tusb_speed_t get_speed(uint8_t rhport) -{ - (void) rhport; - dwc2_regs_t * dwc2 = DWC2_REG(rhport); - uint32_t const enum_spd = (dwc2->dsts & DSTS_ENUMSPD_Msk) >> DSTS_ENUMSPD_Pos; - return (enum_spd == DCD_HIGH_SPEED) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL; -} - -static void set_speed(uint8_t rhport, tusb_speed_t speed) -{ - uint32_t bitvalue; - - if ( rhport == 1 ) - { - bitvalue = (TUSB_SPEED_HIGH == speed ? DCD_HIGH_SPEED : DCD_FULL_SPEED_USE_HS); - } - else - { - bitvalue = DCD_FULL_SPEED; - } - - dwc2_regs_t * dwc2 = DWC2_REG(rhport); - - // Clear and set speed bits - dwc2->dcfg &= ~(3 << DCFG_DSPD_Pos); - dwc2->dcfg |= (bitvalue << DCFG_DSPD_Pos); -} - static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t const dir, uint16_t const num_packets, uint16_t total_bytes) { (void) rhport; @@ -371,90 +342,136 @@ static void reset_core(dwc2_regs_t * dwc2) // wait for device mode ? } -void dcd_init (uint8_t rhport) +static bool has_hs_phy(dwc2_regs_t * dwc2) { - // Programming model begins in the last section of the chapter on the USB - // peripheral in each Reference Manual. - dwc2_regs_t * dwc2 = DWC2_REG(rhport); + return TUD_OPT_HIGH_SPEED && dwc2->ghwcfg2_bm.hs_phy_type != HS_PHY_TYPE_NONE; +} - // Check Synopsys ID, failed if controller is not enabled - uint32_t const gsnpsid = dwc2->gsnpsid & GSNPSID_ID_MASK; - TU_ASSERT(gsnpsid == DWC2_OTG_ID || gsnpsid == DWC2_FS_IOT_ID || gsnpsid == DWC2_HS_IOT_ID, ); +static void phy_fs_init(dwc2_regs_t * dwc2) +{ + TU_LOG1("Fullspeed PHY init\r\n"); - print_dwc2_info(dwc2); + // Select FS PHY + dwc2->gusbcfg |= GUSBCFG_PHYSEL; - // Force device mode - dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FHMOD) | GUSBCFG_FDMOD; + // Reset core after selecting PHY + reset_core(dwc2); - uint32_t const hs_phy_type = dwc2->ghwcfg2_bm.hs_phy_type; + // set turn around + // The values above are calculated for the minimum AHB frequency of 30 MHz. USB turnaround + // time is critical for certification where long cables and 5-Hubs are used, so if + // you need the AHB to run at less than 30 MHz, and if USB turnaround time is not critical, + // these bits can be programmed to a larger value. + dwc2_set_turnaround(dwc2, TUSB_SPEED_FULL); - if( !TUD_OPT_HIGH_SPEED || hs_phy_type == HS_PHY_TYPE_NONE) - { - // max speed is full or core does not support highspeed - TU_LOG2("Fullspeed PHY init\r\n"); + // set max speed + dwc2->dcfg = (dwc2->dcfg & ~DCFG_DSPD_Msk) | (DCFG_DSPD_FS << DCFG_DSPD_Pos); - // Select FS PHY - dwc2->gusbcfg |= GUSBCFG_PHYSEL; + #if defined(DCD_ATTR_DWC2_STM32) + // activate FS PHY on stm32 + dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN; + #endif +} - // Reset core after selecting PHY - reset_core(dwc2); +static void phy_hs_init(dwc2_regs_t * dwc2) +{ + uint32_t gusbcfg = dwc2->gusbcfg; - #if defined(DCD_ATTR_DWC2_STM32) - // activate FS PHY on stm32 - dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN; - #endif - }else + // De-select FS PHY + gusbcfg &= ~GUSBCFG_PHYSEL; + + if (dwc2->ghwcfg2_bm.hs_phy_type == HS_PHY_TYPE_ULPI) { - // Highspeed mode + TU_LOG1("Highspeed ULPI PHY init\r\n"); - #if defined(DCD_ATTR_DWC2_STM32) - // Disable STM32 FS PHY - dwc2->stm32_gccfg &= ~STM32_GCCFG_PWRDWN; - #endif + // Select ULPI + gusbcfg |= GUSBCFG_ULPI_UTMI_SEL; - uint32_t gusbcfg = dwc2->gusbcfg; + // ULPI 8-bit interface, single data rate + gusbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL); - // De-select FS PHY - gusbcfg &= ~GUSBCFG_PHYSEL; + // default internal VBUS Indicator and Drive + gusbcfg &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI); - if (hs_phy_type == HS_PHY_TYPE_ULPI) - { - TU_LOG2("Highspeed ULPI PHY init\r\n"); + // Disable FS/LS ULPI + gusbcfg &= ~(GUSBCFG_ULPIFSLS | GUSBCFG_ULPICSM); + }else + { + TU_LOG1("Highspeed UTMI+ PHY init\r\n"); - // Select ULPI - gusbcfg |= GUSBCFG_ULPI_UTMI_SEL; + // Select UTMI+ with 8-bit interface + gusbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16); - // ULPI 8-bit interface, single data rate - gusbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL); + // Set 16-bit interface if supported + if (dwc2->ghwcfg4_bm.utmi_phy_data_width) gusbcfg |= GUSBCFG_PHYIF16; - // default internal VBUS Indicator and Drive - gusbcfg &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI); + #if defined(DCD_ATTR_DWC2_STM32) && defined(USB_HS_PHYC) + dwc2_stm32_utmi_phy_init(dwc2); + #endif + } - // Disable FS/LS ULPI - gusbcfg &= ~(GUSBCFG_ULPIFSLS | GUSBCFG_ULPICSM); - }else - { - TU_LOG2("Highspeed UTMI+ PHY init\r\n"); + // Apply config + dwc2->gusbcfg = gusbcfg; + + #if defined(DCD_ATTR_DWC2_STM32) + // Disable STM32 FS PHY + dwc2->stm32_gccfg &= ~STM32_GCCFG_PWRDWN; + #endif + + // Reset core after selecting PHY + reset_core(dwc2); + + // Set turn-around, must after core reset otherwise it will be clear + // 9 if UTMI interface is 8-bit, 5 if 16-bit + // The values above are calculated for the minimum AHB frequency of 30 MHz. USB turnaround + // time is critical for certification where long cables and 5-Hubs are used, so if + // you need the AHB to run at less than 30 MHz, and if USB turnaround time is not critical, + // these bits can be programmed to a larger value. + gusbcfg &= ~GUSBCFG_TRDT_Msk; + gusbcfg |= (dwc2->ghwcfg4_bm.utmi_phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos; + dwc2->gusbcfg = gusbcfg; // Apply config + + // Set max speed + dwc2->dcfg = (dwc2->dcfg & ~DCFG_DSPD_Msk) | (DCFG_DSPD_HS << DCFG_DSPD_Pos); +} - // Select UTMI+ with 8-bit interface - gusbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16); +void dcd_init (uint8_t rhport) +{ + // Programming model begins in the last section of the chapter on the USB + // peripheral in each Reference Manual. + dwc2_regs_t * dwc2 = DWC2_REG(rhport); - // Set 16-bit interface if supported - if (dwc2->ghwcfg4_bm.utmi_phy_data_width) gusbcfg |= GUSBCFG_PHYIF16; + // Check Synopsys ID, failed if controller is not enabled + uint32_t const gsnpsid = dwc2->gsnpsid & GSNPSID_ID_MASK; + TU_ASSERT(gsnpsid == DWC2_OTG_ID || gsnpsid == DWC2_FS_IOT_ID || gsnpsid == DWC2_HS_IOT_ID, ); - #if defined(DCD_ATTR_DWC2_STM32) && defined(USB_HS_PHYC) - dwc2_stm32_utmi_phy_init(dwc2); - #endif - } + print_dwc2_info(dwc2); - dwc2->gusbcfg = gusbcfg; + // Force device mode + dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FHMOD) | GUSBCFG_FDMOD; - // Reset core after selecting PHY - reset_core(dwc2); + if( !has_hs_phy(dwc2) ) + { + // core does not support highspeed or hs-phy is not present + phy_fs_init(dwc2); + }else + { + // Highspeed + phy_hs_init(dwc2); } + /* Set HS/FS Timeout Calibration to 7 (max available value). + * The number of PHY clocks that the application programs in + * this field is added to the high/full speed interpacket timeout + * duration in the core to account for any additional delays + * introduced by the PHY. This can be required, because the delay + * introduced by the PHY in generating the linestate condition + * can vary from one PHY to another. + */ + // dwc2->gusbcfg |= (7ul << GUSBCFG_TOCAL_Pos); + // Restart PHY clock - dwc2->pcgctrl = 0; + dwc2->pcgctl &= ~(PCGCTL_STOPPCLK | PCGCTL_GATEHCLK | PCGCTL_PWRCLMP | PCGCTL_RSTPDWNMODULE); // Clear all interrupts dwc2->gintsts |= dwc2->gintsts; @@ -468,8 +485,6 @@ void dcd_init (uint8_t rhport) // (non zero-length packet), send STALL back and discard. dwc2->dcfg |= DCFG_NZLSOHSK; - set_speed(rhport, TUD_OPT_HIGH_SPEED ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL); - dwc2->gintmsk |= GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_USBSUSPM | GINTMSK_WUIM | GINTMSK_RXFLVLM; @@ -1088,9 +1103,23 @@ void dcd_int_handler(uint8_t rhport) dwc2->gintsts = GINTSTS_ENUMDNE; - tusb_speed_t const speed = get_speed(rhport); + tusb_speed_t speed; + switch ((dwc2->dsts & DSTS_ENUMSPD_Msk) >> DSTS_ENUMSPD_Pos) + { + case DSTS_ENUMSPD_HS: + speed = TUSB_SPEED_HIGH; + break; + + case DSTS_ENUMSPD_FS_HSPHY: + case DSTS_ENUMSPD_FS: + speed = TUSB_SPEED_FULL; + break; + + case DSTS_ENUMSPD_LS: + speed = TUSB_SPEED_LOW; + break; + } - dwc2_set_turnaround(dwc2, speed); dcd_event_bus_reset(rhport, speed, true); } diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index 5ded366d7..7e472310f 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -259,8 +259,8 @@ union { uint32_t reservedd00[64]; // D00..DFF //------------- Power Clock -------------// - volatile uint32_t pcgctrl; // E00 Power and Clock Gating Control - volatile uint32_t pcgcctl1; // E04 + volatile uint32_t pcgctl; // E00 Power and Clock Gating Control + volatile uint32_t pcgctl1; // E04 uint32_t reservede08[126]; // E08..FFF //------------- FIFOs -------------// @@ -273,7 +273,7 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, channel) == 0x0500, "incorrect size"); TU_VERIFY_STATIC(offsetof(dwc2_regs_t, dcfg ) == 0x0800, "incorrect size"); TU_VERIFY_STATIC(offsetof(dwc2_regs_t, epin ) == 0x0900, "incorrect size"); TU_VERIFY_STATIC(offsetof(dwc2_regs_t, epout ) == 0x0B00, "incorrect size"); -TU_VERIFY_STATIC(offsetof(dwc2_regs_t, pcgctrl) == 0x0E00, "incorrect size"); +TU_VERIFY_STATIC(offsetof(dwc2_regs_t, pcgctl ) == 0x0E00, "incorrect size"); TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); //--------------------------------------------------------------------+ @@ -346,39 +346,6 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define HCFG_FSLSS_Msk (0x1UL << HCFG_FSLSS_Pos) // 0x00000004 */ #define HCFG_FSLSS HCFG_FSLSS_Msk // FS- and LS-only support */ -/******************** Bit definition for DCFG register ********************/ -#define DCFG_DSPD_Pos (0U) -#define DCFG_DSPD_Msk (0x3UL << DCFG_DSPD_Pos) // 0x00000003 */ -#define DCFG_DSPD DCFG_DSPD_Msk // Device speed */ -#define DCFG_DSPD_0 (0x1UL << DCFG_DSPD_Pos) // 0x00000001 */ -#define DCFG_DSPD_1 (0x2UL << DCFG_DSPD_Pos) // 0x00000002 */ -#define DCFG_NZLSOHSK_Pos (2U) -#define DCFG_NZLSOHSK_Msk (0x1UL << DCFG_NZLSOHSK_Pos) // 0x00000004 */ -#define DCFG_NZLSOHSK DCFG_NZLSOHSK_Msk // Nonzero-length status OUT handshake */ - -#define DCFG_DAD_Pos (4U) -#define DCFG_DAD_Msk (0x7FUL << DCFG_DAD_Pos) // 0x000007F0 */ -#define DCFG_DAD DCFG_DAD_Msk // Device address */ -#define DCFG_DAD_0 (0x01UL << DCFG_DAD_Pos) // 0x00000010 */ -#define DCFG_DAD_1 (0x02UL << DCFG_DAD_Pos) // 0x00000020 */ -#define DCFG_DAD_2 (0x04UL << DCFG_DAD_Pos) // 0x00000040 */ -#define DCFG_DAD_3 (0x08UL << DCFG_DAD_Pos) // 0x00000080 */ -#define DCFG_DAD_4 (0x10UL << DCFG_DAD_Pos) // 0x00000100 */ -#define DCFG_DAD_5 (0x20UL << DCFG_DAD_Pos) // 0x00000200 */ -#define DCFG_DAD_6 (0x40UL << DCFG_DAD_Pos) // 0x00000400 */ - -#define DCFG_PFIVL_Pos (11U) -#define DCFG_PFIVL_Msk (0x3UL << DCFG_PFIVL_Pos) // 0x00001800 */ -#define DCFG_PFIVL DCFG_PFIVL_Msk // Periodic (micro)frame interval */ -#define DCFG_PFIVL_0 (0x1UL << DCFG_PFIVL_Pos) // 0x00000800 */ -#define DCFG_PFIVL_1 (0x2UL << DCFG_PFIVL_Pos) // 0x00001000 */ - -#define DCFG_PERSCHIVL_Pos (24U) -#define DCFG_PERSCHIVL_Msk (0x3UL << DCFG_PERSCHIVL_Pos) // 0x03000000 */ -#define DCFG_PERSCHIVL DCFG_PERSCHIVL_Msk // Periodic scheduling interval */ -#define DCFG_PERSCHIVL_0 (0x1UL << DCFG_PERSCHIVL_Pos) // 0x01000000 */ -#define DCFG_PERSCHIVL_1 (0x2UL << DCFG_PERSCHIVL_Pos) // 0x02000000 */ - /******************** Bit definition for PCGCR register ********************/ #define PCGCR_STPPCLK_Pos (0U) #define PCGCR_STPPCLK_Msk (0x1UL << PCGCR_STPPCLK_Pos) // 0x00000001 */ @@ -413,6 +380,41 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define GOTGINT_IDCHNG_Msk (0x1UL << GOTGINT_IDCHNG_Pos) // 0x00100000 */ #define GOTGINT_IDCHNG GOTGINT_IDCHNG_Msk // Change in ID pin input value */ +/******************** Bit definition for DCFG register ********************/ +#define DCFG_DSPD_Pos (0U) +#define DCFG_DSPD_Msk (0x3UL << DCFG_DSPD_Pos) // 0x00000003 +#define DCFG_DSPD_HS 0 // Highspeed +#define DCFG_DSPD_FS_HSPHY 1 // Fullspeed on HS PHY +#define DCFG_DSPD_LS 2 // Lowspeed +#define DCFG_DSPD_FS 3 // Fullspeed on FS PHY + +#define DCFG_NZLSOHSK_Pos (2U) +#define DCFG_NZLSOHSK_Msk (0x1UL << DCFG_NZLSOHSK_Pos) // 0x00000004 */ +#define DCFG_NZLSOHSK DCFG_NZLSOHSK_Msk // Nonzero-length status OUT handshake */ + +#define DCFG_DAD_Pos (4U) +#define DCFG_DAD_Msk (0x7FUL << DCFG_DAD_Pos) // 0x000007F0 */ +#define DCFG_DAD DCFG_DAD_Msk // Device address */ +#define DCFG_DAD_0 (0x01UL << DCFG_DAD_Pos) // 0x00000010 */ +#define DCFG_DAD_1 (0x02UL << DCFG_DAD_Pos) // 0x00000020 */ +#define DCFG_DAD_2 (0x04UL << DCFG_DAD_Pos) // 0x00000040 */ +#define DCFG_DAD_3 (0x08UL << DCFG_DAD_Pos) // 0x00000080 */ +#define DCFG_DAD_4 (0x10UL << DCFG_DAD_Pos) // 0x00000100 */ +#define DCFG_DAD_5 (0x20UL << DCFG_DAD_Pos) // 0x00000200 */ +#define DCFG_DAD_6 (0x40UL << DCFG_DAD_Pos) // 0x00000400 */ + +#define DCFG_PFIVL_Pos (11U) +#define DCFG_PFIVL_Msk (0x3UL << DCFG_PFIVL_Pos) // 0x00001800 */ +#define DCFG_PFIVL DCFG_PFIVL_Msk // Periodic (micro)frame interval */ +#define DCFG_PFIVL_0 (0x1UL << DCFG_PFIVL_Pos) // 0x00000800 */ +#define DCFG_PFIVL_1 (0x2UL << DCFG_PFIVL_Pos) // 0x00001000 */ + +#define DCFG_PERSCHIVL_Pos (24U) +#define DCFG_PERSCHIVL_Msk (0x3UL << DCFG_PERSCHIVL_Pos) // 0x03000000 */ +#define DCFG_PERSCHIVL DCFG_PERSCHIVL_Msk // Periodic scheduling interval */ +#define DCFG_PERSCHIVL_0 (0x1UL << DCFG_PERSCHIVL_Pos) // 0x01000000 */ +#define DCFG_PERSCHIVL_1 (0x2UL << DCFG_PERSCHIVL_Pos) // 0x02000000 */ + /******************** Bit definition for DCTL register ********************/ #define DCTL_RWUSIG_Pos (0U) #define DCTL_RWUSIG_Msk (0x1UL << DCTL_RWUSIG_Pos) // 0x00000001 */ @@ -466,12 +468,15 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define DSTS_SUSPSTS_Pos (0U) #define DSTS_SUSPSTS_Msk (0x1UL << DSTS_SUSPSTS_Pos) // 0x00000001 */ #define DSTS_SUSPSTS DSTS_SUSPSTS_Msk // Suspend status */ - #define DSTS_ENUMSPD_Pos (1U) #define DSTS_ENUMSPD_Msk (0x3UL << DSTS_ENUMSPD_Pos) // 0x00000006 */ #define DSTS_ENUMSPD DSTS_ENUMSPD_Msk // Enumerated speed */ -#define DSTS_ENUMSPD_0 (0x1UL << DSTS_ENUMSPD_Pos) // 0x00000002 */ -#define DSTS_ENUMSPD_1 (0x2UL << DSTS_ENUMSPD_Pos) // 0x00000004 */ +#define DSTS_ENUMSPD_HS 0 // Highspeed +#define DSTS_ENUMSPD_FS_HSPHY 1 // Fullspeed on HS PHY +#define DSTS_ENUMSPD_LS 2 // Lowspeed +#define DSTS_ENUMSPD_FS 3 // Fullspeed on FS PHY + + #define DSTS_EERR_Pos (3U) #define DSTS_EERR_Msk (0x1UL << DSTS_EERR_Pos) // 0x00000008 */ #define DSTS_EERR DSTS_EERR_Msk // Erratic error */ @@ -501,15 +506,12 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define GAHBCFG_PTXFELVL_Msk (0x1UL << GAHBCFG_PTXFELVL_Pos) // 0x00000100 */ #define GAHBCFG_PTXFELVL GAHBCFG_PTXFELVL_Msk // Periodic TxFIFO empty level */ -#define GSNPSID_ID_MASK TU_GENMASK(31, 16) +#define GSNPSID_ID_MASK TU_GENMASK(31, 16) /******************** Bit definition for GUSBCFG register ********************/ #define GUSBCFG_TOCAL_Pos (0U) #define GUSBCFG_TOCAL_Msk (0x7UL << GUSBCFG_TOCAL_Pos) // 0x00000007 */ #define GUSBCFG_TOCAL GUSBCFG_TOCAL_Msk // FS timeout calibration */ -#define GUSBCFG_TOCAL_0 (0x1UL << GUSBCFG_TOCAL_Pos) // 0x00000001 */ -#define GUSBCFG_TOCAL_1 (0x2UL << GUSBCFG_TOCAL_Pos) // 0x00000002 */ -#define GUSBCFG_TOCAL_2 (0x4UL << GUSBCFG_TOCAL_Pos) // 0x00000004 */ #define GUSBCFG_PHYIF16_Pos (3U) #define GUSBCFG_PHYIF16_Msk (0x1UL << GUSBCFG_PHYIF16_Pos) // 0x00000008 */ #define GUSBCFG_PHYIF16 GUSBCFG_PHYIF16_Msk // PHY Interface (PHYIf) */ @@ -519,7 +521,7 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define GUSBCFG_PHYSEL_Pos (6U) #define GUSBCFG_PHYSEL_Msk (0x1UL << GUSBCFG_PHYSEL_Pos) // 0x00000040 */ #define GUSBCFG_PHYSEL GUSBCFG_PHYSEL_Msk // USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */ -#define GUSBCFG_DDRSEL TU_BIT(7) // Single Data Rate (SDR) or Double Data Rate (DDR) or ULPI interface. +#define GUSBCFG_DDRSEL TU_BIT(7) // Single Data Rate (SDR) or Double Data Rate (DDR) or ULPI interface. #define GUSBCFG_SRPCAP_Pos (8U) #define GUSBCFG_SRPCAP_Msk (0x1UL << GUSBCFG_SRPCAP_Pos) // 0x00000100 */ #define GUSBCFG_SRPCAP GUSBCFG_SRPCAP_Msk // SRP-capable */ @@ -597,8 +599,8 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define GRSTCTL_TXFNUM_2 (0x04UL << GRSTCTL_TXFNUM_Pos) // 0x00000100 */ #define GRSTCTL_TXFNUM_3 (0x08UL << GRSTCTL_TXFNUM_Pos) // 0x00000200 */ #define GRSTCTL_TXFNUM_4 (0x10UL << GRSTCTL_TXFNUM_Pos) // 0x00000400 */ -#define GRSTCTL_CSFTRST_DONE_Pos (29) -#define GRSTCTL_CSFTRST_DONE (1u << GRSTCTL_CSFTRST_DONE_Pos) // Reset Done, only available from v4.20a +#define GRSTCTL_CSFTRST_DONE_Pos (29) +#define GRSTCTL_CSFTRST_DONE (1u << GRSTCTL_CSFTRST_DONE_Pos) // Reset Done, only available from v4.20a #define GRSTCTL_DMAREQ_Pos (30U) #define GRSTCTL_DMAREQ_Msk (0x1UL << GRSTCTL_DMAREQ_Pos) // 0x40000000 */ #define GRSTCTL_DMAREQ GRSTCTL_DMAREQ_Msk // DMA request signal */ @@ -1672,48 +1674,36 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define DOEPTSIZ_STUPCNT_0 (0x1UL << DOEPTSIZ_STUPCNT_Pos) // 0x20000000 */ #define DOEPTSIZ_STUPCNT_1 (0x2UL << DOEPTSIZ_STUPCNT_Pos) // 0x40000000 */ -/******************** Bit definition for PCGCCTL register ********************/ -#define PCGCCTL_STOPCLK_Pos (0U) -#define PCGCCTL_STOPCLK_Msk (0x1UL << PCGCCTL_STOPCLK_Pos) // 0x00000001 */ -#define PCGCCTL_STOPCLK PCGCCTL_STOPCLK_Msk // SETUP packet count */ -#define PCGCCTL_GATECLK_Pos (1U) -#define PCGCCTL_GATECLK_Msk (0x1UL << PCGCCTL_GATECLK_Pos) // 0x00000002 */ -#define PCGCCTL_GATECLK PCGCCTL_GATECLK_Msk //Bit 0 */ -#define PCGCCTL_PHYSUSP_Pos (4U) -#define PCGCCTL_PHYSUSP_Msk (0x1UL << PCGCCTL_PHYSUSP_Pos) // 0x00000010 */ -#define PCGCCTL_PHYSUSP PCGCCTL_PHYSUSP_Msk //Bit 1 */ - -/******************** Bit definition for USBPHYC_PLL1 register ********************/ -#define HS_PHYC_PLL1_PLLEN_Pos (0U) -#define HS_PHYC_PLL1_PLLEN_Msk (0x1UL << HS_PHYC_PLL1_PLLEN_Pos) // 0x00000001 */ -#define HS_PHYC_PLL1_PLLEN HS_PHYC_PLL1_PLLEN_Msk // Enable PLL */ -#define HS_PHYC_PLL1_PLLSEL_Pos (1U) -#define HS_PHYC_PLL1_PLLSEL_Msk (0x7UL << HS_PHYC_PLL1_PLLSEL_Pos) // 0x0000000E */ -#define HS_PHYC_PLL1_PLLSEL HS_PHYC_PLL1_PLLSEL_Msk // Controls PHY frequency operation selection */ -#define HS_PHYC_PLL1_PLLSEL_1 (0x1UL << HS_PHYC_PLL1_PLLSEL_Pos) // 0x00000002 */ -#define HS_PHYC_PLL1_PLLSEL_2 (0x2UL << HS_PHYC_PLL1_PLLSEL_Pos) // 0x00000004 */ -#define HS_PHYC_PLL1_PLLSEL_3 (0x4UL << HS_PHYC_PLL1_PLLSEL_Pos) // 0x00000008 */ - -#define HS_PHYC_PLL1_PLLSEL_12MHZ 0x00000000U // PHY PLL1 input clock frequency 12 MHz */ -#define HS_PHYC_PLL1_PLLSEL_12_5MHZ HS_PHYC_PLL1_PLLSEL_1 // PHY PLL1 input clock frequency 12.5 MHz */ -#define HS_PHYC_PLL1_PLLSEL_16MHZ (uint32_t)(HS_PHYC_PLL1_PLLSEL_1 | HS_PHYC_PLL1_PLLSEL_2) // PHY PLL1 input clock frequency 16 MHz */ -#define HS_PHYC_PLL1_PLLSEL_24MHZ HS_PHYC_PLL1_PLLSEL_3 // PHY PLL1 input clock frequency 24 MHz */ -#define HS_PHYC_PLL1_PLLSEL_25MHZ (uint32_t)(HS_PHYC_PLL1_PLLSEL_2 | HS_PHYC_PLL1_PLLSEL_3) // PHY PLL1 input clock frequency 25 MHz */ - -/******************** Bit definition for USBPHYC_LDO register ********************/ -#define HS_PHYC_LDO_USED_Pos (0U) -#define HS_PHYC_LDO_USED_Msk (0x1UL << HS_PHYC_LDO_USED_Pos) // 0x00000001 */ -#define HS_PHYC_LDO_USED HS_PHYC_LDO_USED_Msk // Monitors the usage status of the PHY's LDO */ -#define HS_PHYC_LDO_STATUS_Pos (1U) -#define HS_PHYC_LDO_STATUS_Msk (0x1UL << HS_PHYC_LDO_STATUS_Pos) // 0x00000002 */ -#define HS_PHYC_LDO_STATUS HS_PHYC_LDO_STATUS_Msk // Monitors the status of the PHY's LDO. */ -#define HS_PHYC_LDO_DISABLE_Pos (2U) -#define HS_PHYC_LDO_DISABLE_Msk (0x1UL << HS_PHYC_LDO_DISABLE_Pos) // 0x00000004 */ -#define HS_PHYC_LDO_DISABLE HS_PHYC_LDO_DISABLE_Msk // Controls disable of the High Speed PHY's LDO */ - -#define HS_PHYC_LDO_ENABLE_Pos HS_PHYC_LDO_DISABLE_Pos -#define HS_PHYC_LDO_ENABLE_Msk HS_PHYC_LDO_DISABLE_Msk -#define HS_PHYC_LDO_ENABLE HS_PHYC_LDO_DISABLE +/******************** Bit definition for PCGCTL register ********************/ +#define PCGCTL_IF_DEV_MODE TU_BIT(31) +#define PCGCTL_P2HD_PRT_SPD_MASK (0x3ul << 29) +#define PCGCTL_P2HD_PRT_SPD_SHIFT 29 +#define PCGCTL_P2HD_DEV_ENUM_SPD_MASK (0x3ul << 27) +#define PCGCTL_P2HD_DEV_ENUM_SPD_SHIFT 27 +#define PCGCTL_MAC_DEV_ADDR_MASK (0x7ful << 20) +#define PCGCTL_MAC_DEV_ADDR_SHIFT 20 +#define PCGCTL_MAX_TERMSEL TU_BIT(19) +#define PCGCTL_MAX_XCVRSELECT_MASK (0x3ul << 17) +#define PCGCTL_MAX_XCVRSELECT_SHIFT 17 +#define PCGCTL_PORT_POWER TU_BIT(16) +#define PCGCTL_PRT_CLK_SEL_MASK (0x3ul << 14) +#define PCGCTL_PRT_CLK_SEL_SHIFT 14 +#define PCGCTL_ESS_REG_RESTORED TU_BIT(13) +#define PCGCTL_EXTND_HIBER_SWITCH TU_BIT(12) +#define PCGCTL_EXTND_HIBER_PWRCLMP TU_BIT(11) +#define PCGCTL_ENBL_EXTND_HIBER TU_BIT(10) +#define PCGCTL_RESTOREMODE TU_BIT(9) +#define PCGCTL_RESETAFTSUSP TU_BIT(8) +#define PCGCTL_DEEP_SLEEP TU_BIT(7) +#define PCGCTL_PHY_IN_SLEEP TU_BIT(6) +#define PCGCTL_ENBL_SLEEP_GATING TU_BIT(5) +#define PCGCTL_RSTPDWNMODULE TU_BIT(3) +#define PCGCTL_PWRCLMP TU_BIT(2) +#define PCGCTL_GATEHCLK TU_BIT(1) +#define PCGCTL_STOPPCLK TU_BIT(0) + +#define PCGCTL1_TIMER (0x3ul << 1) +#define PCGCTL1_GATEEN TU_BIT(0) #ifdef __cplusplus } -- cgit v1.3.1 From 8e95b807f7250ec759389a4b0551f90419d14ac6 Mon Sep 17 00:00:00 2001 From: Matt Johnston Date: Fri, 29 Oct 2021 12:53:07 +0800 Subject: samd21: Make LED_PIN and BUTTON_PIN optional Some boards don't have them, just ignore --- hw/bsp/samd21/family.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/hw/bsp/samd21/family.c b/hw/bsp/samd21/family.c index eb5b55863..10e40e3f0 100644 --- a/hw/bsp/samd21/family.c +++ b/hw/bsp/samd21/family.c @@ -73,12 +73,16 @@ void board_init(void) SysTick_Config(CONF_CPU_FREQUENCY / 1000); // Led init +#ifdef LED_PIN gpio_set_pin_direction(LED_PIN, GPIO_DIRECTION_OUT); board_led_write(false); +#endif // Button init +#ifdef BUTTON_PIN gpio_set_pin_direction(BUTTON_PIN, GPIO_DIRECTION_IN); gpio_set_pin_pull_mode(BUTTON_PIN, BUTTON_STATE_ACTIVE ? GPIO_PULL_DOWN : GPIO_PULL_UP); +#endif #if CFG_TUSB_OS == OPT_OS_FREERTOS // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) @@ -119,12 +123,19 @@ void board_init(void) void board_led_write(bool state) { + (void)state; +#ifdef LED_PIN gpio_set_pin_level(LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON)); +#endif } uint32_t board_button_read(void) { +#ifdef BUTTON_PIN return BUTTON_STATE_ACTIVE == gpio_get_pin_level(BUTTON_PIN); +#else + return 0; +#endif } int board_uart_read(uint8_t* buf, int len) -- cgit v1.3.1 From 660e8b8c887091e17323c361f25e804a5d06d6df Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 29 Oct 2021 16:08:19 +0700 Subject: skip snpsid check for gd32, abstract phyfs turnaround, set max timeout calibration. still has issue with gd32 with msc (does work with running with rtt as log). --- src/common/tusb_common.h | 3 + src/portable/synopsys/dwc2/dcd_dwc2.c | 191 +++++++++++++++++--------------- src/portable/synopsys/dwc2/dwc2_bcm.h | 7 +- src/portable/synopsys/dwc2/dwc2_esp32.h | 8 +- src/portable/synopsys/dwc2/dwc2_gd32.h | 8 +- src/portable/synopsys/dwc2/dwc2_stm32.h | 61 +++++----- src/portable/synopsys/dwc2/dwc2_type.h | 13 ++- 7 files changed, 144 insertions(+), 147 deletions(-) diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h index e62bcde12..9b9e2b007 100644 --- a/src/common/tusb_common.h +++ b/src/common/tusb_common.h @@ -111,6 +111,9 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u32_byte2(uint32_t ui32) { return TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u32_byte1(uint32_t ui32) { return TU_U32_BYTE1(ui32); } TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u32_byte0(uint32_t ui32) { return TU_U32_BYTE0(ui32); } +TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_u32_high16(uint32_t ui32) { return (uint16_t) (ui32 >> 16); } +TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_u32_low16 (uint32_t ui32) { return (uint16_t) (ui32 & 0x0000ffffu); } + TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u16_high(uint16_t ui16) { return TU_U16_HIGH(ui16); } TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u16_low (uint16_t ui16) { return TU_U16_LOW(ui16); } diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index ce9b58e03..aad7e45cc 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -54,16 +54,8 @@ #define DWC2_REG(_port) ((dwc2_regs_t*) DWC2_REG_BASE) -enum -{ - DCD_HIGH_SPEED = 0, // Highspeed mode - DCD_FULL_SPEED_USE_HS = 1, // Full speed in Highspeed port (probably with internal PHY) - DCD_FULL_SPEED = 3, // Full speed with internal PHY -}; - -// PHYSEL, ULPISEL -// UTMI internal HS PHY -// ULPI external HS PHY +// Debug level for DWC2 +#define DWC2_DEBUG 1 static TU_ATTR_ALIGNED(4) uint32_t _setup_packet[2]; @@ -261,71 +253,73 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c /*------------------------------------------------------------------*/ /* Controller API *------------------------------------------------------------------*/ +#if CFG_TUSB_DEBUG >= DWC2_DEBUG void print_dwc2_info(dwc2_regs_t * dwc2) { dwc2_ghwcfg2_t const * hw_cfg2 = &dwc2->ghwcfg2_bm; dwc2_ghwcfg3_t const * hw_cfg3 = &dwc2->ghwcfg3_bm; dwc2_ghwcfg4_t const * hw_cfg4 = &dwc2->ghwcfg4_bm; - TU_LOG_HEX(1, dwc2->guid); - TU_LOG_HEX(1, dwc2->gsnpsid); - TU_LOG_HEX(1, dwc2->ghwcfg1); + TU_LOG_HEX(DWC2_DEBUG, dwc2->guid); + TU_LOG_HEX(DWC2_DEBUG, dwc2->gsnpsid); + TU_LOG_HEX(DWC2_DEBUG, dwc2->ghwcfg1); // HW configure 2 - TU_LOG(1, "\r\n"); - TU_LOG_HEX(1, dwc2->ghwcfg2); - TU_LOG_INT(1, hw_cfg2->op_mode ); - TU_LOG_INT(1, hw_cfg2->arch ); - TU_LOG_INT(1, hw_cfg2->point2point ); - TU_LOG_INT(1, hw_cfg2->hs_phy_type ); - TU_LOG_INT(1, hw_cfg2->fs_phy_type ); - TU_LOG_INT(1, hw_cfg2->num_dev_ep ); - TU_LOG_INT(1, hw_cfg2->num_host_ch ); - TU_LOG_INT(1, hw_cfg2->period_channel_support ); - TU_LOG_INT(1, hw_cfg2->enable_dynamic_fifo ); - TU_LOG_INT(1, hw_cfg2->mul_cpu_int ); - TU_LOG_INT(1, hw_cfg2->nperiod_tx_q_depth ); - TU_LOG_INT(1, hw_cfg2->host_period_tx_q_depth ); - TU_LOG_INT(1, hw_cfg2->dev_token_q_depth ); - TU_LOG_INT(1, hw_cfg2->otg_enable_ic_usb ); + TU_LOG(DWC2_DEBUG, "\r\n"); + TU_LOG_HEX(DWC2_DEBUG, dwc2->ghwcfg2); + TU_LOG_INT(DWC2_DEBUG, hw_cfg2->op_mode ); + TU_LOG_INT(DWC2_DEBUG, hw_cfg2->arch ); + TU_LOG_INT(DWC2_DEBUG, hw_cfg2->point2point ); + TU_LOG_INT(DWC2_DEBUG, hw_cfg2->hs_phy_type ); + TU_LOG_INT(DWC2_DEBUG, hw_cfg2->fs_phy_type ); + TU_LOG_INT(DWC2_DEBUG, hw_cfg2->num_dev_ep ); + TU_LOG_INT(DWC2_DEBUG, hw_cfg2->num_host_ch ); + TU_LOG_INT(DWC2_DEBUG, hw_cfg2->period_channel_support ); + TU_LOG_INT(DWC2_DEBUG, hw_cfg2->enable_dynamic_fifo ); + TU_LOG_INT(DWC2_DEBUG, hw_cfg2->mul_cpu_int ); + TU_LOG_INT(DWC2_DEBUG, hw_cfg2->nperiod_tx_q_depth ); + TU_LOG_INT(DWC2_DEBUG, hw_cfg2->host_period_tx_q_depth ); + TU_LOG_INT(DWC2_DEBUG, hw_cfg2->dev_token_q_depth ); + TU_LOG_INT(DWC2_DEBUG, hw_cfg2->otg_enable_ic_usb ); // HW configure 3 - TU_LOG(1, "\r\n"); - TU_LOG_HEX(1, dwc2->ghwcfg3); - TU_LOG_INT(1, hw_cfg3->xfer_size_width ); - TU_LOG_INT(1, hw_cfg3->packet_size_width ); - TU_LOG_INT(1, hw_cfg3->otg_enable ); - TU_LOG_INT(1, hw_cfg3->i2c_enable ); - TU_LOG_INT(1, hw_cfg3->vendor_ctrl_itf ); - TU_LOG_INT(1, hw_cfg3->optional_feature_removed ); - TU_LOG_INT(1, hw_cfg3->synch_reset ); - TU_LOG_INT(1, hw_cfg3->otg_adp_support ); - TU_LOG_INT(1, hw_cfg3->otg_enable_hsic ); - TU_LOG_INT(1, hw_cfg3->battery_charger_support ); - TU_LOG_INT(1, hw_cfg3->lpm_mode ); - TU_LOG_INT(1, hw_cfg3->total_fifo_size ); + TU_LOG(DWC2_DEBUG, "\r\n"); + TU_LOG_HEX(DWC2_DEBUG, dwc2->ghwcfg3); + TU_LOG_INT(DWC2_DEBUG, hw_cfg3->xfer_size_width ); + TU_LOG_INT(DWC2_DEBUG, hw_cfg3->packet_size_width ); + TU_LOG_INT(DWC2_DEBUG, hw_cfg3->otg_enable ); + TU_LOG_INT(DWC2_DEBUG, hw_cfg3->i2c_enable ); + TU_LOG_INT(DWC2_DEBUG, hw_cfg3->vendor_ctrl_itf ); + TU_LOG_INT(DWC2_DEBUG, hw_cfg3->optional_feature_removed ); + TU_LOG_INT(DWC2_DEBUG, hw_cfg3->synch_reset ); + TU_LOG_INT(DWC2_DEBUG, hw_cfg3->otg_adp_support ); + TU_LOG_INT(DWC2_DEBUG, hw_cfg3->otg_enable_hsic ); + TU_LOG_INT(DWC2_DEBUG, hw_cfg3->battery_charger_support ); + TU_LOG_INT(DWC2_DEBUG, hw_cfg3->lpm_mode ); + TU_LOG_INT(DWC2_DEBUG, hw_cfg3->total_fifo_size ); // HW configure 4 - TU_LOG(1, "\r\n"); - TU_LOG_HEX(1, dwc2->ghwcfg4); - TU_LOG_INT(1, hw_cfg4->num_dev_period_in_ep ); - TU_LOG_INT(1, hw_cfg4->power_optimized ); - TU_LOG_INT(1, hw_cfg4->ahb_freq_min ); - TU_LOG_INT(1, hw_cfg4->hibernation ); - TU_LOG_INT(1, hw_cfg4->service_interval_mode ); - TU_LOG_INT(1, hw_cfg4->ipg_isoc_en ); - TU_LOG_INT(1, hw_cfg4->acg_enable ); - TU_LOG_INT(1, hw_cfg4->utmi_phy_data_width ); - TU_LOG_INT(1, hw_cfg4->dev_ctrl_ep_num ); - TU_LOG_INT(1, hw_cfg4->iddg_filter_enabled ); - TU_LOG_INT(1, hw_cfg4->vbus_valid_filter_enabled ); - TU_LOG_INT(1, hw_cfg4->a_valid_filter_enabled ); - TU_LOG_INT(1, hw_cfg4->b_valid_filter_enabled ); - TU_LOG_INT(1, hw_cfg4->dedicated_fifos ); - TU_LOG_INT(1, hw_cfg4->num_dev_in_eps ); - TU_LOG_INT(1, hw_cfg4->dma_desc_enable ); - TU_LOG_INT(1, hw_cfg4->dma_dynamic ); + TU_LOG(DWC2_DEBUG, "\r\n"); + TU_LOG_HEX(DWC2_DEBUG, dwc2->ghwcfg4); + TU_LOG_INT(DWC2_DEBUG, hw_cfg4->num_dev_period_in_ep ); + TU_LOG_INT(DWC2_DEBUG, hw_cfg4->power_optimized ); + TU_LOG_INT(DWC2_DEBUG, hw_cfg4->ahb_freq_min ); + TU_LOG_INT(DWC2_DEBUG, hw_cfg4->hibernation ); + TU_LOG_INT(DWC2_DEBUG, hw_cfg4->service_interval_mode ); + TU_LOG_INT(DWC2_DEBUG, hw_cfg4->ipg_isoc_en ); + TU_LOG_INT(DWC2_DEBUG, hw_cfg4->acg_enable ); + TU_LOG_INT(DWC2_DEBUG, hw_cfg4->utmi_phy_data_width ); + TU_LOG_INT(DWC2_DEBUG, hw_cfg4->dev_ctrl_ep_num ); + TU_LOG_INT(DWC2_DEBUG, hw_cfg4->iddg_filter_enabled ); + TU_LOG_INT(DWC2_DEBUG, hw_cfg4->vbus_valid_filter_enabled ); + TU_LOG_INT(DWC2_DEBUG, hw_cfg4->a_valid_filter_enabled ); + TU_LOG_INT(DWC2_DEBUG, hw_cfg4->b_valid_filter_enabled ); + TU_LOG_INT(DWC2_DEBUG, hw_cfg4->dedicated_fifos ); + TU_LOG_INT(DWC2_DEBUG, hw_cfg4->num_dev_in_eps ); + TU_LOG_INT(DWC2_DEBUG, hw_cfg4->dma_desc_enable ); + TU_LOG_INT(DWC2_DEBUG, hw_cfg4->dma_dynamic ); } +#endif static void reset_core(dwc2_regs_t * dwc2) { @@ -342,14 +336,15 @@ static void reset_core(dwc2_regs_t * dwc2) // wait for device mode ? } -static bool has_hs_phy(dwc2_regs_t * dwc2) +static bool phy_hs_supported(dwc2_regs_t * dwc2) { + // note: esp32 incorrect report its hs_phy_type as utmi return TUD_OPT_HIGH_SPEED && dwc2->ghwcfg2_bm.hs_phy_type != HS_PHY_TYPE_NONE; } static void phy_fs_init(dwc2_regs_t * dwc2) { - TU_LOG1("Fullspeed PHY init\r\n"); + TU_LOG(DWC2_DEBUG, "Fullspeed PHY init\r\n"); // Select FS PHY dwc2->gusbcfg |= GUSBCFG_PHYSEL; @@ -358,11 +353,11 @@ static void phy_fs_init(dwc2_regs_t * dwc2) reset_core(dwc2); // set turn around - // The values above are calculated for the minimum AHB frequency of 30 MHz. USB turnaround - // time is critical for certification where long cables and 5-Hubs are used, so if - // you need the AHB to run at less than 30 MHz, and if USB turnaround time is not critical, + // USB turnaround time is critical for certification where long cables and 5-Hubs are used. + // So if you need the AHB to run at less than 30 MHz, and if USB turnaround time is not critical, // these bits can be programmed to a larger value. - dwc2_set_turnaround(dwc2, TUSB_SPEED_FULL); + //TU_LOG_INT(DWC2_DEBUG, (dwc2->gusbcfg & GUSBCFG_TRDT_Msk) >> GUSBCFG_TRDT_Pos ); + dwc2_phyfs_set_turnaround(dwc2); // set max speed dwc2->dcfg = (dwc2->dcfg & ~DCFG_DSPD_Msk) | (DCFG_DSPD_FS << DCFG_DSPD_Pos); @@ -382,7 +377,7 @@ static void phy_hs_init(dwc2_regs_t * dwc2) if (dwc2->ghwcfg2_bm.hs_phy_type == HS_PHY_TYPE_ULPI) { - TU_LOG1("Highspeed ULPI PHY init\r\n"); + TU_LOG(DWC2_DEBUG, "Highspeed ULPI PHY init\r\n"); // Select ULPI gusbcfg |= GUSBCFG_ULPI_UTMI_SEL; @@ -397,7 +392,7 @@ static void phy_hs_init(dwc2_regs_t * dwc2) gusbcfg &= ~(GUSBCFG_ULPIFSLS | GUSBCFG_ULPICSM); }else { - TU_LOG1("Highspeed UTMI+ PHY init\r\n"); + TU_LOG(DWC2_DEBUG, "Highspeed UTMI+ PHY init\r\n"); // Select UTMI+ with 8-bit interface gusbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16); @@ -422,11 +417,8 @@ static void phy_hs_init(dwc2_regs_t * dwc2) reset_core(dwc2); // Set turn-around, must after core reset otherwise it will be clear - // 9 if UTMI interface is 8-bit, 5 if 16-bit - // The values above are calculated for the minimum AHB frequency of 30 MHz. USB turnaround - // time is critical for certification where long cables and 5-Hubs are used, so if - // you need the AHB to run at less than 30 MHz, and if USB turnaround time is not critical, - // these bits can be programmed to a larger value. + // - 9 if using 8-bit PHY interface + // - 5 if using 16-bit PHY interface gusbcfg &= ~GUSBCFG_TRDT_Msk; gusbcfg |= (dwc2->ghwcfg4_bm.utmi_phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos; dwc2->gusbcfg = gusbcfg; // Apply config @@ -435,31 +427,45 @@ static void phy_hs_init(dwc2_regs_t * dwc2) dwc2->dcfg = (dwc2->dcfg & ~DCFG_DSPD_Msk) | (DCFG_DSPD_HS << DCFG_DSPD_Pos); } +static bool check_dwc2(dwc2_regs_t * dwc2) +{ + // For some reasons: GD32VF103 snpsid and all hwcfg register are always zero (skip it) +#if !TU_CHECK_MCU(OPT_MCU_GD32VF103) + uint32_t const gsnpsid = dwc2->gsnpsid & GSNPSID_ID_MASK; + TU_ASSERT(gsnpsid == DWC2_OTG_ID || gsnpsid == DWC2_FS_IOT_ID || gsnpsid == DWC2_HS_IOT_ID); +#endif + +#if CFG_TUSB_DEBUG >= DWC2_DEBUG + print_dwc2_info(dwc2); +#endif + + return true; +} + void dcd_init (uint8_t rhport) { // Programming model begins in the last section of the chapter on the USB // peripheral in each Reference Manual. dwc2_regs_t * dwc2 = DWC2_REG(rhport); - // Check Synopsys ID, failed if controller is not enabled - uint32_t const gsnpsid = dwc2->gsnpsid & GSNPSID_ID_MASK; - TU_ASSERT(gsnpsid == DWC2_OTG_ID || gsnpsid == DWC2_FS_IOT_ID || gsnpsid == DWC2_HS_IOT_ID, ); - - print_dwc2_info(dwc2); + // Check Synopsys ID register, failed if controller clock/power is not enabled + TU_VERIFY(check_dwc2(dwc2), ); // Force device mode dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FHMOD) | GUSBCFG_FDMOD; - if( !has_hs_phy(dwc2) ) - { - // core does not support highspeed or hs-phy is not present - phy_fs_init(dwc2); - }else + if( phy_hs_supported(dwc2) ) { // Highspeed phy_hs_init(dwc2); + }else + { + // core does not support highspeed or hs-phy is not present + phy_fs_init(dwc2); } + TU_LOG_HEX(DWC2_DEBUG, dwc2->gusbcfg); + /* Set HS/FS Timeout Calibration to 7 (max available value). * The number of PHY clocks that the application programs in * this field is added to the high/full speed interpacket timeout @@ -468,7 +474,7 @@ void dcd_init (uint8_t rhport) * introduced by the PHY in generating the linestate condition * can vary from one PHY to another. */ - // dwc2->gusbcfg |= (7ul << GUSBCFG_TOCAL_Pos); + dwc2->gusbcfg |= (7ul << GUSBCFG_TOCAL_Pos); // Restart PHY clock dwc2->pcgctl &= ~(PCGCTL_STOPPCLK | PCGCTL_GATEHCLK | PCGCTL_PWRCLMP | PCGCTL_RSTPDWNMODULE); @@ -617,7 +623,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) _allocated_fifo_words_tx += fifo_size; - TU_LOG(2, " Allocated %u bytes at offset %u", fifo_size*4, DWC2_EP_FIFO_SIZE-_allocated_fifo_words_tx*4); + TU_LOG(DWC2_DEBUG, " Allocated %u bytes at offset %u", fifo_size*4, DWC2_EP_FIFO_SIZE-_allocated_fifo_words_tx*4); // DIEPTXF starts at FIFO #1. // Both TXFD and TXSA are in unit of 32-bit words. @@ -1110,14 +1116,15 @@ void dcd_int_handler(uint8_t rhport) speed = TUSB_SPEED_HIGH; break; + case DSTS_ENUMSPD_LS: + speed = TUSB_SPEED_LOW; + break; + case DSTS_ENUMSPD_FS_HSPHY: case DSTS_ENUMSPD_FS: + default: speed = TUSB_SPEED_FULL; break; - - case DSTS_ENUMSPD_LS: - speed = TUSB_SPEED_LOW; - break; } dcd_event_bus_reset(rhport, speed, true); @@ -1204,7 +1211,7 @@ void dcd_int_handler(uint8_t rhport) // // Check for Incomplete isochronous IN transfer // if(int_status & GINTSTS_IISOIXFR) { // printf(" IISOIXFR!\r\n"); - //// TU_LOG2(" IISOIXFR!\r\n"); + //// TU_LOG(DWC2_DEBUG, " IISOIXFR!\r\n"); // } } diff --git a/src/portable/synopsys/dwc2/dwc2_bcm.h b/src/portable/synopsys/dwc2/dwc2_bcm.h index da1f23ae0..c064946cf 100644 --- a/src/portable/synopsys/dwc2/dwc2_bcm.h +++ b/src/portable/synopsys/dwc2/dwc2_bcm.h @@ -58,11 +58,10 @@ static inline void dwc2_remote_wakeup_delay(void) // TODO implement later } -static inline void dwc2_set_turnaround(dwc2_regs_t * core, tusb_speed_t speed) +static inline void dwc2_phyfs_set_turnaround(dwc2_regs_t * dwc2) { - // TODO implement later - (void) core; - (void) speed; + (void) dwc2; + // do nothing since bcm alwyas use HS PHY } #ifdef __cplusplus diff --git a/src/portable/synopsys/dwc2/dwc2_esp32.h b/src/portable/synopsys/dwc2/dwc2_esp32.h index b8a040041..af5d5f093 100644 --- a/src/portable/synopsys/dwc2/dwc2_esp32.h +++ b/src/portable/synopsys/dwc2/dwc2_esp32.h @@ -67,12 +67,10 @@ static inline void dwc2_remote_wakeup_delay(void) vTaskDelay(pdMS_TO_TICKS(1)); } -static inline void dwc2_set_turnaround(dwc2_regs_t * core, tusb_speed_t speed) +static inline void dwc2_phyfs_set_turnaround(dwc2_regs_t * dwc2) { - (void) core; - (void) speed; - - // keep the reset value + (void) dwc2; + // keep the reset value which is 5 on this port } #ifdef __cplusplus diff --git a/src/portable/synopsys/dwc2/dwc2_gd32.h b/src/portable/synopsys/dwc2/dwc2_gd32.h index de3ccb3b0..15e73ad1e 100644 --- a/src/portable/synopsys/dwc2/dwc2_gd32.h +++ b/src/portable/synopsys/dwc2/dwc2_gd32.h @@ -76,12 +76,10 @@ static inline void dwc2_remote_wakeup_delay(void) while ( count-- ) __asm volatile ("nop"); } -static inline void dwc2_set_turnaround(dwc2_regs_t * core, tusb_speed_t speed) +static inline void dwc2_phyfs_set_turnaround(dwc2_regs_t * dwc2) { - (void) core; - (void) speed; - - // keep the reset value + // use recommeded value 6 by stm32 for mcu with AHB clock > 32Mhz + dwc2->gusbcfg = (dwc2->gusbcfg & GUSBCFG_TRDT_Msk) | (6u << GUSBCFG_TRDT_Pos); } diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h index b77cda2ca..4d0ed3f0a 100644 --- a/src/portable/synopsys/dwc2/dwc2_stm32.h +++ b/src/portable/synopsys/dwc2/dwc2_stm32.h @@ -113,44 +113,33 @@ static inline void dwc2_remote_wakeup_delay(void) } // Set turn-around timeout according to link speed -static inline void dwc2_set_turnaround(dwc2_regs_t * dwc2, tusb_speed_t speed) +static inline void dwc2_phyfs_set_turnaround(dwc2_regs_t * dwc2) { - dwc2->gusbcfg &= ~GUSBCFG_TRDT; - - if ( speed == TUSB_SPEED_HIGH ) - { - // Use fixed 0x09 for Highspeed - dwc2->gusbcfg |= (0x09 << GUSBCFG_TRDT_Pos); - } + // Turnaround timeout depends on the AHB clock dictated by STM32 Reference Manual + uint32_t turnaround; + + if ( SystemCoreClock >= 32000000U ) + turnaround = 0x6u; + else if ( SystemCoreClock >= 27500000U ) + turnaround = 0x7u; + else if ( SystemCoreClock >= 24000000U ) + turnaround = 0x8u; + else if ( SystemCoreClock >= 21800000U ) + turnaround = 0x9u; + else if ( SystemCoreClock >= 20000000U ) + turnaround = 0xAu; + else if ( SystemCoreClock >= 18500000U ) + turnaround = 0xBu; + else if ( SystemCoreClock >= 17200000U ) + turnaround = 0xCu; + else if ( SystemCoreClock >= 16000000U ) + turnaround = 0xDu; + else if ( SystemCoreClock >= 15000000U ) + turnaround = 0xEu; else - { - // Turnaround timeout depends on the MCU clock - uint32_t turnaround; - - if ( SystemCoreClock >= 32000000U ) - turnaround = 0x6U; - else if ( SystemCoreClock >= 27500000U ) - turnaround = 0x7U; - else if ( SystemCoreClock >= 24000000U ) - turnaround = 0x8U; - else if ( SystemCoreClock >= 21800000U ) - turnaround = 0x9U; - else if ( SystemCoreClock >= 20000000U ) - turnaround = 0xAU; - else if ( SystemCoreClock >= 18500000U ) - turnaround = 0xBU; - else if ( SystemCoreClock >= 17200000U ) - turnaround = 0xCU; - else if ( SystemCoreClock >= 16000000U ) - turnaround = 0xDU; - else if ( SystemCoreClock >= 15000000U ) - turnaround = 0xEU; - else - turnaround = 0xFU; - - // Fullspeed depends on MCU clocks, but we will use 0x06 for 32+ Mhz - dwc2->gusbcfg |= (turnaround << GUSBCFG_TRDT_Pos); - } + turnaround = 0xFu; + + dwc2->gusbcfg = (dwc2->gusbcfg & GUSBCFG_TRDT_Msk) | (turnaround << GUSBCFG_TRDT_Pos); } #if defined(USB_HS_PHYC) diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index 7e472310f..7b3db4dd9 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -59,12 +59,19 @@ typedef struct #endif enum { - HS_PHY_TYPE_NONE = 0 , + HS_PHY_TYPE_NONE = 0 , // not supported HS_PHY_TYPE_UTMI , // internal PHY (mostly) HS_PHY_TYPE_ULPI , // external PHY HS_PHY_TYPE_UTMI_ULPI , }; +enum { + FS_PHY_TYPE_NONE = 0, // not supported + FS_PHY_TYPE_DEDICATED, + FS_PHY_TYPE_UTMI, + FS_PHY_TYPE_ULPI, +}; + typedef struct TU_ATTR_PACKED { uint32_t op_mode : 3; // 0: HNP and SRP | 1: SRP | 2: non-HNP, non-SRP @@ -531,10 +538,6 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define GUSBCFG_TRDT_Pos (10U) #define GUSBCFG_TRDT_Msk (0xFUL << GUSBCFG_TRDT_Pos) // 0x00003C00 */ #define GUSBCFG_TRDT GUSBCFG_TRDT_Msk // USB turnaround time */ -#define GUSBCFG_TRDT_0 (0x1UL << GUSBCFG_TRDT_Pos) // 0x00000400 */ -#define GUSBCFG_TRDT_1 (0x2UL << GUSBCFG_TRDT_Pos) // 0x00000800 */ -#define GUSBCFG_TRDT_2 (0x4UL << GUSBCFG_TRDT_Pos) // 0x00001000 */ -#define GUSBCFG_TRDT_3 (0x8UL << GUSBCFG_TRDT_Pos) // 0x00002000 */ #define GUSBCFG_PHYLPCS_Pos (15U) #define GUSBCFG_PHYLPCS_Msk (0x1UL << GUSBCFG_PHYLPCS_Pos) // 0x00008000 */ #define GUSBCFG_PHYLPCS GUSBCFG_PHYLPCS_Msk // PHY Low-power clock select */ -- cgit v1.3.1 From 19a26729b03bab188746b5e835878530c7bed65d Mon Sep 17 00:00:00 2001 From: Matt Johnston Date: Fri, 17 Sep 2021 17:56:24 +0800 Subject: Add Adafruit QT Py board Straight copy of itsybitsy_m0/ with MCU changed to ATSAMD21E18 LED and button are disabled. LED is a neopixel so could be added later. --- hw/bsp/samd21/boards/qtpy/board.h | 46 ++++++++++++ hw/bsp/samd21/boards/qtpy/board.mk | 11 +++ hw/bsp/samd21/boards/qtpy/qtpy.ld | 146 +++++++++++++++++++++++++++++++++++++ 3 files changed, 203 insertions(+) create mode 100644 hw/bsp/samd21/boards/qtpy/board.h create mode 100644 hw/bsp/samd21/boards/qtpy/board.mk create mode 100644 hw/bsp/samd21/boards/qtpy/qtpy.ld diff --git a/hw/bsp/samd21/boards/qtpy/board.h b/hw/bsp/samd21/boards/qtpy/board.h new file mode 100644 index 000000000..6f8325e49 --- /dev/null +++ b/hw/bsp/samd21/boards/qtpy/board.h @@ -0,0 +1,46 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +// LED is neopixel, leave unset for now + +// Button is wired to reset + +// UART +#define UART_RX_PIN 8 +#define UART_TX_PIN 7 + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/samd21/boards/qtpy/board.mk b/hw/bsp/samd21/boards/qtpy/board.mk new file mode 100644 index 000000000..6cefa84c3 --- /dev/null +++ b/hw/bsp/samd21/boards/qtpy/board.mk @@ -0,0 +1,11 @@ +# For Adafruit QT Py board + +CFLAGS += -D__SAMD21E18A__ -DCFG_EXAMPLE_VIDEO_READONLY + +# All source paths should be relative to the top level. +LD_FILE = $(BOARD_PATH)/$(BOARD).ld + +# For flash-jlink target +JLINK_DEVICE = ATSAMD21E18 + +flash: flash-bossac diff --git a/hw/bsp/samd21/boards/qtpy/qtpy.ld b/hw/bsp/samd21/boards/qtpy/qtpy.ld new file mode 100644 index 000000000..f0c93340c --- /dev/null +++ b/hw/bsp/samd21/boards/qtpy/qtpy.ld @@ -0,0 +1,146 @@ +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAMD21G18A + * + * Copyright (c) 2017 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00000000 + 8K, LENGTH = 0x00040000 - 8K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000; + +ENTRY(Reset_Handler) + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + end = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} -- cgit v1.3.1 From 9cd5a87c64425b8a7427531735f06f255117aeeb Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 30 Oct 2021 20:42:55 +0700 Subject: add support for EFM32GG merge GG12 GG12 to simply OPT_MCU_EFM32GG --- hw/bsp/board_mcu.h | 2 +- hw/bsp/sltb009a/board.mk | 4 +- hw/bsp/stm32f4/family.c | 7 ++ hw/bsp/stm32h7/boards/stm32h743eval/board.mk | 1 + hw/bsp/stm32h7/family.mk | 12 ++- src/device/dcd_attr.h | 2 +- src/host/hcd_attr.h | 2 +- src/portable/synopsys/dwc2/dcd_dwc2.c | 90 ++++++++++------- src/portable/synopsys/dwc2/dwc2_bcm.h | 17 +++- src/portable/synopsys/dwc2/dwc2_esp32.h | 18 +++- src/portable/synopsys/dwc2/dwc2_gd32.h | 18 +++- src/portable/synopsys/dwc2/dwc2_stm32.h | 143 +++++++++++++++------------ src/portable/synopsys/dwc2/dwc2_type.h | 2 +- src/tusb_option.h | 2 - 14 files changed, 199 insertions(+), 121 deletions(-) diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h index a4d57597c..c840db89e 100644 --- a/hw/bsp/board_mcu.h +++ b/hw/bsp/board_mcu.h @@ -125,7 +125,7 @@ #elif CFG_TUSB_MCU == OPT_MCU_RP2040 #include "pico.h" -#elif CFG_TUSB_MCU == OPT_MCU_EFM32GG || CFG_TUSB_MCU == OPT_MCU_EFM32GG11 || CFG_TUSB_MCU == OPT_MCU_EFM32GG12 +#elif CFG_TUSB_MCU == OPT_MCU_EFM32GG #include "em_device.h" #elif CFG_TUSB_MCU == OPT_MCU_RX63X || CFG_TUSB_MCU == OPT_MCU_RX65X diff --git a/hw/bsp/sltb009a/board.mk b/hw/bsp/sltb009a/board.mk index e8a24d1bd..7a046b34b 100644 --- a/hw/bsp/sltb009a/board.mk +++ b/hw/bsp/sltb009a/board.mk @@ -8,7 +8,7 @@ CFLAGS += \ -D__STARTUP_CLEAR_BSS \ -D__START=main \ -DEFM32GG12B810F1024GM64 \ - -DCFG_TUSB_MCU=OPT_MCU_EFM32GG12 + -DCFG_TUSB_MCU=OPT_MCU_EFM32GG # mcu driver cause following warnings #CFLAGS += -Wno-error=unused-parameter @@ -24,7 +24,7 @@ LD_FILE = $(SILABS_CMSIS)/Source/GCC/$(SILABS_FAMILY).ld SRC_C += \ $(SILABS_CMSIS)/Source/system_$(SILABS_FAMILY).c \ - src/portable/silabs/efm32/dcd_efm32.c + src/portable/synopsys/dwc2/dcd_dwc2.c SRC_S += \ $(SILABS_CMSIS)/Source/GCC/startup_$(SILABS_FAMILY).S diff --git a/hw/bsp/stm32f4/family.c b/hw/bsp/stm32f4/family.c index 31f27fa3f..82d4957e7 100644 --- a/hw/bsp/stm32f4/family.c +++ b/hw/bsp/stm32f4/family.c @@ -36,6 +36,11 @@ void OTG_FS_IRQHandler(void) tud_int_handler(0); } +void OTG_HS_IRQHandler(void) +{ + tud_int_handler(1); +} + //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ @@ -134,6 +139,8 @@ void board_init(void) // Enable USB OTG clock __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); +// __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); + board_vbus_sense_init(); } diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/board.mk b/hw/bsp/stm32h7/boards/stm32h743eval/board.mk index 96d14a795..b768a0ee6 100644 --- a/hw/bsp/stm32h7/boards/stm32h743eval/board.mk +++ b/hw/bsp/stm32h7/boards/stm32h743eval/board.mk @@ -2,6 +2,7 @@ CFLAGS += -DSTM32H743xx -DHSE_VALUE=25000000 # Default is Highspeed port PORT ?= 1 +SPEED ?= high SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h743xx.s LD_FILE = $(BOARD_PATH)/stm32h743xx_flash.ld diff --git a/hw/bsp/stm32h7/family.mk b/hw/bsp/stm32h7/family.mk index 6a257e22d..096d04d0c 100644 --- a/hw/bsp/stm32h7/family.mk +++ b/hw/bsp/stm32h7/family.mk @@ -19,16 +19,22 @@ CFLAGS += \ -DBOARD_DEVICE_RHPORT_NUM=$(PORT) ifeq ($(PORT), 1) - CFLAGS += -DBOARD_DEVICE_RHPORT_SPEED=OPT_MODE_HIGH_SPEED - $(info "PORT1 High Speed") + ifeq ($(SPEED), high) + CFLAGS += -DBOARD_DEVICE_RHPORT_SPEED=OPT_MODE_HIGH_SPEED + $(info "Using OTG_HS in HighSpeed mode") + else + CFLAGS += -DBOARD_DEVICE_RHPORT_SPEED=OPT_MODE_FULL_SPEED + $(info "Using OTG_HS in FullSpeed mode") + endif else - $(info "PORT0 Full Speed") + $(info "Using OTG_FS") endif # suppress warning caused by vendor mcu driver CFLAGS += -Wno-error=maybe-uninitialized -Wno-error=cast-align # All source paths should be relative to the top level. + SRC_C += \ src/portable/synopsys/dwc2/dcd_dwc2.c \ $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \ diff --git a/src/device/dcd_attr.h b/src/device/dcd_attr.h index 90f3a526a..70854f9c6 100644 --- a/src/device/dcd_attr.h +++ b/src/device/dcd_attr.h @@ -169,7 +169,7 @@ #define DCD_ATTR_ENDPOINT_MAX 16 //------------- Silabs -------------// -#elif TU_CHECK_MCU(OPT_MCU_EFM32GG, OPT_MCU_EFM32GG11, OPT_MCU_EFM32GG12) +#elif TU_CHECK_MCU(OPT_MCU_EFM32GG) #define DCD_ATTR_ENDPOINT_MAX 7 //------------- Renesas -------------// diff --git a/src/host/hcd_attr.h b/src/host/hcd_attr.h index a9bc242d7..06011c63c 100644 --- a/src/host/hcd_attr.h +++ b/src/host/hcd_attr.h @@ -82,7 +82,7 @@ #elif TU_CHECK_MCU(OPT_MCU_RP2040) //------------- Silabs -------------// -#elif TU_CHECK_MCU(OPT_MCU_EFM32GG, OPT_MCU_EFM32GG11, OPT_MCU_EFM32GG12) +#elif TU_CHECK_MCU(OPT_MCU_EFM32GG) //------------- Renesas -------------// #elif TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index aad7e45cc..16780cba8 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -31,7 +31,9 @@ #include "device/dcd_attr.h" #if TUSB_OPT_DEVICE_ENABLED && \ - ( defined(DCD_ATTR_DWC2_STM32) || TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3, OPT_MCU_GD32VF103, OPT_MCU_BCM2711) ) + ( defined(DCD_ATTR_DWC2_STM32) || \ + TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3, OPT_MCU_GD32VF103) || \ + TU_CHECK_MCU(OPT_MCU_EFM32GG, OPT_MCU_BCM2711) ) #include "device/dcd.h" #include "dwc2_type.h" @@ -44,6 +46,8 @@ #include "dwc2_gd32.h" #elif TU_CHECK_MCU(OPT_MCU_BCM2711) #include "dwc2_bcm.h" +#elif TU_CHECK_MCU(OPT_MCU_EFM32GG) + #include "dwc2_efm32.h" #else #error "Unsupported MCUs" #endif @@ -260,6 +264,9 @@ void print_dwc2_info(dwc2_regs_t * dwc2) dwc2_ghwcfg3_t const * hw_cfg3 = &dwc2->ghwcfg3_bm; dwc2_ghwcfg4_t const * hw_cfg4 = &dwc2->ghwcfg4_bm; + TU_LOG_HEX(DWC2_DEBUG, dwc2->gotgctl); + TU_LOG_HEX(DWC2_DEBUG, dwc2->gusbcfg); + TU_LOG_HEX(DWC2_DEBUG, dwc2->dcfg); TU_LOG_HEX(DWC2_DEBUG, dwc2->guid); TU_LOG_HEX(DWC2_DEBUG, dwc2->gsnpsid); TU_LOG_HEX(DWC2_DEBUG, dwc2->ghwcfg1); @@ -349,23 +356,22 @@ static void phy_fs_init(dwc2_regs_t * dwc2) // Select FS PHY dwc2->gusbcfg |= GUSBCFG_PHYSEL; + // MCU specific PHY init before reset + dwc2_phy_init(dwc2, HS_PHY_TYPE_NONE); + // Reset core after selecting PHY reset_core(dwc2); - // set turn around // USB turnaround time is critical for certification where long cables and 5-Hubs are used. // So if you need the AHB to run at less than 30 MHz, and if USB turnaround time is not critical, - // these bits can be programmed to a larger value. - //TU_LOG_INT(DWC2_DEBUG, (dwc2->gusbcfg & GUSBCFG_TRDT_Msk) >> GUSBCFG_TRDT_Pos ); - dwc2_phyfs_set_turnaround(dwc2); + // these bits can be programmed to a larger value. Default is 5 + dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_TRDT_Msk) | (5u << GUSBCFG_TRDT_Pos); + + // MCU specific PHY update post reset + dwc2_phy_update(dwc2, HS_PHY_TYPE_NONE); // set max speed dwc2->dcfg = (dwc2->dcfg & ~DCFG_DSPD_Msk) | (DCFG_DSPD_FS << DCFG_DSPD_Pos); - - #if defined(DCD_ATTR_DWC2_STM32) - // activate FS PHY on stm32 - dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN; - #endif } static void phy_hs_init(dwc2_regs_t * dwc2) @@ -399,19 +405,13 @@ static void phy_hs_init(dwc2_regs_t * dwc2) // Set 16-bit interface if supported if (dwc2->ghwcfg4_bm.utmi_phy_data_width) gusbcfg |= GUSBCFG_PHYIF16; - - #if defined(DCD_ATTR_DWC2_STM32) && defined(USB_HS_PHYC) - dwc2_stm32_utmi_phy_init(dwc2); - #endif } // Apply config dwc2->gusbcfg = gusbcfg; - #if defined(DCD_ATTR_DWC2_STM32) - // Disable STM32 FS PHY - dwc2->stm32_gccfg &= ~STM32_GCCFG_PWRDWN; - #endif + // mcu specific phy init + dwc2_phy_init(dwc2, dwc2->ghwcfg2_bm.hs_phy_type); // Reset core after selecting PHY reset_core(dwc2); @@ -421,7 +421,10 @@ static void phy_hs_init(dwc2_regs_t * dwc2) // - 5 if using 16-bit PHY interface gusbcfg &= ~GUSBCFG_TRDT_Msk; gusbcfg |= (dwc2->ghwcfg4_bm.utmi_phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos; - dwc2->gusbcfg = gusbcfg; // Apply config + dwc2->gusbcfg = gusbcfg; + + // MCU specific PHY update post reset + dwc2_phy_update(dwc2, dwc2->ghwcfg2_bm.hs_phy_type); // Set max speed dwc2->dcfg = (dwc2->dcfg & ~DCFG_DSPD_Msk) | (DCFG_DSPD_HS << DCFG_DSPD_Pos); @@ -429,16 +432,16 @@ static void phy_hs_init(dwc2_regs_t * dwc2) static bool check_dwc2(dwc2_regs_t * dwc2) { +#if CFG_TUSB_DEBUG >= DWC2_DEBUG + print_dwc2_info(dwc2); +#endif + // For some reasons: GD32VF103 snpsid and all hwcfg register are always zero (skip it) #if !TU_CHECK_MCU(OPT_MCU_GD32VF103) uint32_t const gsnpsid = dwc2->gsnpsid & GSNPSID_ID_MASK; TU_ASSERT(gsnpsid == DWC2_OTG_ID || gsnpsid == DWC2_FS_IOT_ID || gsnpsid == DWC2_HS_IOT_ID); #endif -#if CFG_TUSB_DEBUG >= DWC2_DEBUG - print_dwc2_info(dwc2); -#endif - return true; } @@ -451,8 +454,10 @@ void dcd_init (uint8_t rhport) // Check Synopsys ID register, failed if controller clock/power is not enabled TU_VERIFY(check_dwc2(dwc2), ); - // Force device mode - dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FHMOD) | GUSBCFG_FDMOD; + dcd_disconnect(rhport); + + // max number of endpoints & total_fifo_size are: + // hw_cfg2->num_dev_ep, hw_cfg2->total_fifo_size if( phy_hs_supported(dwc2) ) { @@ -464,7 +469,11 @@ void dcd_init (uint8_t rhport) phy_fs_init(dwc2); } - TU_LOG_HEX(DWC2_DEBUG, dwc2->gusbcfg); + // Restart PHY clock + dwc2->pcgctl &= ~(PCGCTL_STOPPCLK | PCGCTL_GATEHCLK | PCGCTL_PWRCLMP | PCGCTL_RSTPDWNMODULE); + + // Force device mode + dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FHMOD) | GUSBCFG_FDMOD; /* Set HS/FS Timeout Calibration to 7 (max available value). * The number of PHY clocks that the application programs in @@ -476,27 +485,34 @@ void dcd_init (uint8_t rhport) */ dwc2->gusbcfg |= (7ul << GUSBCFG_TOCAL_Pos); - // Restart PHY clock - dwc2->pcgctl &= ~(PCGCTL_STOPPCLK | PCGCTL_GATEHCLK | PCGCTL_PWRCLMP | PCGCTL_RSTPDWNMODULE); + // If USB host misbehaves during status portion of control xfer + // (non zero-length packet), send STALL back and discard. + dwc2->dcfg |= DCFG_NZLSOHSK; + + // Clear A,B, VBus valid override + dwc2->gotgctl &= ~(GOTGCTL_BVALOEN | GOTGCTL_AVALOEN | GOTGCTL_VBVALOEN); // Clear all interrupts dwc2->gintsts |= dwc2->gintsts; + dwc2->gotgint |= dwc2->gotgint; // Required as part of core initialization. // TODO: How should mode mismatch be handled? It will cause // the core to stop working/require reset. - dwc2->gintmsk |= GINTMSK_OTGINT | GINTMSK_MMISM; - - // If USB host misbehaves during status portion of control xfer - // (non zero-length packet), send STALL back and discard. - dwc2->dcfg |= DCFG_NZLSOHSK; - - dwc2->gintmsk |= GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_USBSUSPM | - GINTMSK_WUIM | GINTMSK_RXFLVLM; + dwc2->gintmsk = GINTMSK_OTGINT | GINTMSK_MMISM | GINTMSK_RXFLVLM | + GINTMSK_USBSUSPM | GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_WUIM; // Enable global interrupt dwc2->gahbcfg |= GAHBCFG_GINT; + // make sure we are in device mode +// TU_ASSERT(!(dwc2->gintsts & GINTSTS_CMOD), ); + +// TU_LOG_HEX(DWC2_DEBUG, dwc2->gotgctl); +// TU_LOG_HEX(DWC2_DEBUG, dwc2->gusbcfg); +// TU_LOG_HEX(DWC2_DEBUG, dwc2->dcfg); +// TU_LOG_HEX(DWC2_DEBUG, dwc2->gahbcfg); + dcd_connect(rhport); } @@ -1096,6 +1112,8 @@ void dcd_int_handler(uint8_t rhport) uint32_t const int_status = dwc2->gintsts & dwc2->gintmsk; +// TU_LOG_HEX(DWC2_DEBUG, int_status); + if(int_status & GINTSTS_USBRST) { // USBRST is start of reset. diff --git a/src/portable/synopsys/dwc2/dwc2_bcm.h b/src/portable/synopsys/dwc2/dwc2_bcm.h index c064946cf..38d10930c 100644 --- a/src/portable/synopsys/dwc2/dwc2_bcm.h +++ b/src/portable/synopsys/dwc2/dwc2_bcm.h @@ -51,17 +51,28 @@ static inline void dwc2_dcd_int_disable (uint8_t rhport) BP_DisableIRQ(USB_IRQn); } -TU_ATTR_ALWAYS_INLINE static inline void dwc2_remote_wakeup_delay(void) { // try to delay for 1 ms // TODO implement later } -static inline void dwc2_phyfs_set_turnaround(dwc2_regs_t * dwc2) +// MCU specific PHY init, called BEFORE core reset +static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type) { (void) dwc2; - // do nothing since bcm alwyas use HS PHY + (void) hs_phy_type; + + // nothing to do +} + +// MCU specific PHY update, it is called AFTER init() and core reset +static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type) +{ + (void) dwc2; + (void) hs_phy_type; + + // nothing to do } #ifdef __cplusplus diff --git a/src/portable/synopsys/dwc2/dwc2_esp32.h b/src/portable/synopsys/dwc2/dwc2_esp32.h index af5d5f093..78da277d5 100644 --- a/src/portable/synopsys/dwc2/dwc2_esp32.h +++ b/src/portable/synopsys/dwc2/dwc2_esp32.h @@ -50,12 +50,14 @@ static void dcd_int_handler_wrap(void* arg) dcd_int_handler(0); } +TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_enable (uint8_t rhport) { (void) rhport; esp_intr_alloc(ETS_USB_INTR_SOURCE, ESP_INTR_FLAG_LOWMED, dcd_int_handler_wrap, NULL, &usb_ih); } +TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_disable (uint8_t rhport) { (void) rhport; @@ -67,10 +69,22 @@ static inline void dwc2_remote_wakeup_delay(void) vTaskDelay(pdMS_TO_TICKS(1)); } -static inline void dwc2_phyfs_set_turnaround(dwc2_regs_t * dwc2) +// MCU specific PHY init, called BEFORE core reset +static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type) { (void) dwc2; - // keep the reset value which is 5 on this port + (void) hs_phy_type; + + // nothing to do +} + +// MCU specific PHY update, it is called AFTER init() and core reset +static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type) +{ + (void) dwc2; + (void) hs_phy_type; + + // nothing to do } #ifdef __cplusplus diff --git a/src/portable/synopsys/dwc2/dwc2_gd32.h b/src/portable/synopsys/dwc2/dwc2_gd32.h index 15e73ad1e..f8fa01ee0 100644 --- a/src/portable/synopsys/dwc2/dwc2_gd32.h +++ b/src/portable/synopsys/dwc2/dwc2_gd32.h @@ -68,7 +68,6 @@ static inline void dwc2_dcd_int_disable (uint8_t rhport) __eclic_disable_interrupt(RHPORT_IRQn); } -TU_ATTR_ALWAYS_INLINE static inline void dwc2_remote_wakeup_delay(void) { // try to delay for 1 ms @@ -76,12 +75,23 @@ static inline void dwc2_remote_wakeup_delay(void) while ( count-- ) __asm volatile ("nop"); } -static inline void dwc2_phyfs_set_turnaround(dwc2_regs_t * dwc2) +// MCU specific PHY init, called BEFORE core reset +static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type) { - // use recommeded value 6 by stm32 for mcu with AHB clock > 32Mhz - dwc2->gusbcfg = (dwc2->gusbcfg & GUSBCFG_TRDT_Msk) | (6u << GUSBCFG_TRDT_Pos); + (void) dwc2; + (void) hs_phy_type; + + // nothing to do } +// MCU specific PHY update, it is called AFTER init() and core reset +static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type) +{ + (void) dwc2; + (void) hs_phy_type; + + // nothing to do +} #ifdef __cplusplus } diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h index 4d0ed3f0a..469045ac4 100644 --- a/src/portable/synopsys/dwc2/dwc2_stm32.h +++ b/src/portable/synopsys/dwc2/dwc2_stm32.h @@ -112,79 +112,92 @@ static inline void dwc2_remote_wakeup_delay(void) while ( count-- ) __NOP(); } -// Set turn-around timeout according to link speed -static inline void dwc2_phyfs_set_turnaround(dwc2_regs_t * dwc2) +// MCU specific PHY init, called BEFORE core reset +static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type) { - // Turnaround timeout depends on the AHB clock dictated by STM32 Reference Manual - uint32_t turnaround; - - if ( SystemCoreClock >= 32000000U ) - turnaround = 0x6u; - else if ( SystemCoreClock >= 27500000U ) - turnaround = 0x7u; - else if ( SystemCoreClock >= 24000000U ) - turnaround = 0x8u; - else if ( SystemCoreClock >= 21800000U ) - turnaround = 0x9u; - else if ( SystemCoreClock >= 20000000U ) - turnaround = 0xAu; - else if ( SystemCoreClock >= 18500000U ) - turnaround = 0xBu; - else if ( SystemCoreClock >= 17200000U ) - turnaround = 0xCu; - else if ( SystemCoreClock >= 16000000U ) - turnaround = 0xDu; - else if ( SystemCoreClock >= 15000000U ) - turnaround = 0xEu; - else - turnaround = 0xFu; - - dwc2->gusbcfg = (dwc2->gusbcfg & GUSBCFG_TRDT_Msk) | (turnaround << GUSBCFG_TRDT_Pos); + if ( hs_phy_type == HS_PHY_TYPE_NONE ) + { + // Enable on-chip FS PHY + dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN; + }else + { + // Disable FS PHY + dwc2->stm32_gccfg &= ~STM32_GCCFG_PWRDWN; + + // Enable on-chip HS PHY + if (hs_phy_type == HS_PHY_TYPE_UTMI || hs_phy_type == HS_PHY_TYPE_UTMI_ULPI) + { +#ifdef USB_HS_PHYC + // Enable UTMI HS PHY + dwc2->stm32_gccfg |= STM32_GCCFG_PHYHSEN; + + // Enable LDO + USB_HS_PHYC->USB_HS_PHYC_LDO |= USB_HS_PHYC_LDO_ENABLE; + + // Wait until LDO ready + while ( 0 == (USB_HS_PHYC->USB_HS_PHYC_LDO & USB_HS_PHYC_LDO_STATUS) ) {} + + uint32_t phyc_pll = 0; + + // TODO Try to get HSE_VALUE from registers instead of depending CFLAGS + switch ( HSE_VALUE ) + { + case 12000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12MHZ ; break; + case 12500000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12_5MHZ ; break; + case 16000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_16MHZ ; break; + case 24000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_24MHZ ; break; + case 25000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_25MHZ ; break; + case 32000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_Msk ; break; // Value not defined in header + default: + TU_ASSERT(false, ); + } + USB_HS_PHYC->USB_HS_PHYC_PLL = phyc_pll; + + // Control the tuning interface of the High Speed PHY + // Use magic value (USB_HS_PHYC_TUNE_VALUE) from ST driver for F7 + USB_HS_PHYC->USB_HS_PHYC_TUNE |= 0x00000F13U; + + // Enable PLL internal PHY + USB_HS_PHYC->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN; +#endif + } + } } -#if defined(USB_HS_PHYC) -static inline void dwc2_stm32_utmi_phy_init(dwc2_regs_t * dwc2) +// MCU specific PHY update, it is called AFTER init() and core reset +static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type) { - USB_HS_PHYC_GlobalTypeDef *usb_hs_phyc = (USB_HS_PHYC_GlobalTypeDef*) USB_HS_PHYC_CONTROLLER_BASE; - - // Enable UTMI HS PHY - dwc2->stm32_gccfg |= STM32_GCCFG_PHYHSEN; - - // Enable LDO - usb_hs_phyc->USB_HS_PHYC_LDO |= USB_HS_PHYC_LDO_ENABLE; - - // Wait until LDO ready - while ( 0 == (usb_hs_phyc->USB_HS_PHYC_LDO & USB_HS_PHYC_LDO_STATUS) ) {} - - uint32_t phyc_pll = 0; - - // TODO Try to get HSE_VALUE from registers instead of depending CFLAGS - switch ( HSE_VALUE ) + // used to set turnaround time for fullspeed, nothing to do in highspeed mode + if ( hs_phy_type == HS_PHY_TYPE_NONE ) { - case 12000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12MHZ ; break; - case 12500000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12_5MHZ ; break; - case 16000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_16MHZ ; break; - case 24000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_24MHZ ; break; - case 25000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_25MHZ ; break; - case 32000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_Msk ; break; // Value not defined in header - default: - TU_ASSERT(false, ); + // Turnaround timeout depends on the AHB clock dictated by STM32 Reference Manual + uint32_t turnaround; + + if ( SystemCoreClock >= 32000000u ) + turnaround = 0x6u; + else if ( SystemCoreClock >= 27500000u ) + turnaround = 0x7u; + else if ( SystemCoreClock >= 24000000u ) + turnaround = 0x8u; + else if ( SystemCoreClock >= 21800000u ) + turnaround = 0x9u; + else if ( SystemCoreClock >= 20000000u ) + turnaround = 0xAu; + else if ( SystemCoreClock >= 18500000u ) + turnaround = 0xBu; + else if ( SystemCoreClock >= 17200000u ) + turnaround = 0xCu; + else if ( SystemCoreClock >= 16000000u ) + turnaround = 0xDu; + else if ( SystemCoreClock >= 15000000u ) + turnaround = 0xEu; + else + turnaround = 0xFu; + + dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_TRDT_Msk) | (turnaround << GUSBCFG_TRDT_Pos); } - usb_hs_phyc->USB_HS_PHYC_PLL = phyc_pll; - - // Control the tuning interface of the High Speed PHY - // Use magic value (USB_HS_PHYC_TUNE_VALUE) from ST driver - usb_hs_phyc->USB_HS_PHYC_TUNE |= 0x00000F13U; - - // Enable PLL internal PHY - usb_hs_phyc->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN; - - // Original ST code has 2 ms delay for PLL stabilization. - // Primitive test shows that more than 10 USB un/replug cycle showed no error with enumeration } -#endif - #ifdef __cplusplus } #endif diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index 7b3db4dd9..583a7274a 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -528,7 +528,7 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define GUSBCFG_PHYSEL_Pos (6U) #define GUSBCFG_PHYSEL_Msk (0x1UL << GUSBCFG_PHYSEL_Pos) // 0x00000040 */ #define GUSBCFG_PHYSEL GUSBCFG_PHYSEL_Msk // USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */ -#define GUSBCFG_DDRSEL TU_BIT(7) // Single Data Rate (SDR) or Double Data Rate (DDR) or ULPI interface. +#define GUSBCFG_DDRSEL TU_BIT(7) // Single Data Rate (SDR) or Double Data Rate (DDR) or ULPI interface. #define GUSBCFG_SRPCAP_Pos (8U) #define GUSBCFG_SRPCAP_Msk (0x1UL << GUSBCFG_SRPCAP_Pos) // 0x00000100 */ #define GUSBCFG_SRPCAP GUSBCFG_SRPCAP_Msk // SRP-capable */ diff --git a/src/tusb_option.h b/src/tusb_option.h index de0279dda..4da07e241 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -113,8 +113,6 @@ // Silabs #define OPT_MCU_EFM32GG 1300 ///< Silabs EFM32GG -#define OPT_MCU_EFM32GG11 1301 ///< Silabs EFM32GG11 -#define OPT_MCU_EFM32GG12 1302 ///< Silabs EFM32GG12 // Renesas RX #define OPT_MCU_RX63X 1400 ///< Renesas RX63N/631 -- cgit v1.3.1 From b85a6898af6fb75d5e877d418748a22c92a6d7bf Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 30 Oct 2021 20:45:58 +0700 Subject: remove dcd_efm32 --- src/portable/silabs/efm32/dcd_efm32.c | 936 -------------------------------- src/portable/synopsys/dwc2/dwc2_efm32.h | 87 +++ 2 files changed, 87 insertions(+), 936 deletions(-) delete mode 100644 src/portable/silabs/efm32/dcd_efm32.c create mode 100644 src/portable/synopsys/dwc2/dwc2_efm32.h diff --git a/src/portable/silabs/efm32/dcd_efm32.c b/src/portable/silabs/efm32/dcd_efm32.c deleted file mode 100644 index ccae113a3..000000000 --- a/src/portable/silabs/efm32/dcd_efm32.c +++ /dev/null @@ -1,936 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2021 Rafael Silva (@perigoso) - * Copyright (c) 2021 Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#include "tusb_option.h" - -#if TUSB_OPT_DEVICE_ENABLED && ( \ - (CFG_TUSB_MCU == OPT_MCU_EFM32GG) || \ - (CFG_TUSB_MCU == OPT_MCU_EFM32GG11) || \ - (CFG_TUSB_MCU == OPT_MCU_EFM32GG12) ) - -/* Silabs */ -#include "em_device.h" - -#include "device/dcd.h" - -/* - * Since TinyUSB doesn't use SOF for now, and this interrupt too often (1ms interval) - * We disable SOF for now until needed later on - */ -#define USE_SOF 0 - -/* - * Number of endpoints - * 12 software-configurable endpoints (6 IN, 6 OUT) in addition to endpoint 0 - */ -#define EP_COUNT 7 - -/* FIFO size in bytes */ -#define EP_FIFO_SIZE 2048 - -/* Max number of IN EP FIFOs */ -#define EP_FIFO_NUM 7 - -/* */ -typedef struct { - uint8_t *buffer; - uint16_t total_len; - uint16_t queued_len; - uint16_t max_size; - bool short_packet; -} xfer_ctl_t; - -static uint32_t _setup_packet[2]; - -#define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir] -static xfer_ctl_t xfer_status[EP_COUNT][2]; - -/* Keep count of how many FIFOs are in use */ -static uint8_t _allocated_fifos = 1; /* FIFO0 is always in use */ - -static volatile uint32_t* tx_fifo[EP_FIFO_NUM] = { - USB->FIFO0D, - USB->FIFO1D, - USB->FIFO2D, - USB->FIFO3D, - USB->FIFO4D, - USB->FIFO5D, - USB->FIFO6D, -}; - -/* Register Helpers */ -#define DCTL_WO_BITMASK (USB_DCTL_CGOUTNAK | USB_DCTL_SGOUTNAK | USB_DCTL_CGNPINNAK | USB_DCTL_SGNPINNAK) -#define GUSBCFG_WO_BITMASK (USB_GUSBCFG_CORRUPTTXPKT) -#define DEPCTL_WO_BITMASK (USB_DIEP_CTL_CNAK | USB_DIEP_CTL_SNAK | USB_DIEP_CTL_SETD0PIDEF | USB_DIEP_CTL_SETD1PIDOF) - -/* Will either return an unused FIFO number, or 0 if all are used. */ -static uint8_t get_free_fifo(void) -{ - if(_allocated_fifos < EP_FIFO_NUM) return _allocated_fifos++; - return 0; -} - -/* -static void flush_rx_fifo(void) -{ - USB->GRSTCTL = USB_GRSTCTL_RXFFLSH; - while(USB->GRSTCTL & USB_GRSTCTL_RXFFLSH); -} -*/ - -static void flush_tx_fifo(uint8_t fifo_num) -{ - USB->GRSTCTL = USB_GRSTCTL_TXFFLSH | (fifo_num << _USB_GRSTCTL_TXFNUM_SHIFT); - while(USB->GRSTCTL & USB_GRSTCTL_TXFFLSH); -} - -/* Setup the control endpoint 0. */ -static void bus_reset(void) -{ - USB->DOEP0CTL |= USB_DIEP_CTL_SNAK; - for(uint8_t i = 0; i < EP_COUNT - 1; i++) - { - USB->DOEP[i].CTL |= USB_DIEP_CTL_SNAK; - } - - /* reset address */ - USB->DCFG &= ~_USB_DCFG_DEVADDR_MASK; - - USB->DAINTMSK |= USB_DAINTMSK_OUTEPMSK0 | USB_DAINTMSK_INEPMSK0; - USB->DOEPMSK |= USB_DOEPMSK_SETUPMSK | USB_DOEPMSK_XFERCOMPLMSK; - USB->DIEPMSK |= USB_DIEPMSK_TIMEOUTMSK | USB_DIEPMSK_XFERCOMPLMSK; - - /* - * - All EP OUT shared a unique OUT FIFO which uses - * * 10 locations in hardware for setup packets + setup control words (up to 3 setup packets). - * * 2 locations for OUT endpoint control words. - * * 16 for largest packet size of 64 bytes. ( TODO Highspeed is 512 bytes) - * * 1 location for global NAK (not required/used here). - * * It is recommended to allocate 2 times the largest packet size, therefore - * Recommended value = 10 + 1 + 2 x (16+2) = 47 --> Let's make it 52 - */ - flush_tx_fifo(_USB_GRSTCTL_TXFNUM_FALL); // Flush All - USB->GRXFSIZ = 52; - - /* Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word ) */ - USB->GNPTXFSIZ = (16 << _USB_GNPTXFSIZ_NPTXFINEPTXF0DEP_SHIFT) | (USB->GRXFSIZ & _USB_GNPTXFSIZ_NPTXFSTADDR_MASK); - - /* Ready to receive SETUP packet */ - USB->DOEP0TSIZ |= (1 << _USB_DOEP0TSIZ_SUPCNT_SHIFT); - - USB->GINTMSK |= USB_GINTMSK_IEPINTMSK | USB_GINTMSK_OEPINTMSK; -} - -static void enum_done_processing(void) -{ - /* Maximum packet size for EP 0 is set for both directions by writing DIEPCTL */ - if((USB->DSTS & _USB_DSTS_ENUMSPD_MASK) == USB_DSTS_ENUMSPD_FS) - { - /* Full Speed (PHY on 48 MHz) */ - USB->DOEP0CTL = (USB->DOEP0CTL & ~_USB_DOEP0CTL_MPS_MASK) | _USB_DOEP0CTL_MPS_64B; /* Maximum Packet Size 64 bytes */ - USB->DOEP0CTL &= ~_USB_DOEP0CTL_STALL_MASK; /* clear Stall */ - xfer_status[0][TUSB_DIR_OUT].max_size = 64; - xfer_status[0][TUSB_DIR_IN].max_size = 64; - } - else - { - /* Low Speed (PHY on 6 MHz) */ - USB->DOEP0CTL = (USB->DOEP0CTL & ~_USB_DOEP0CTL_MPS_MASK) | _USB_DOEP0CTL_MPS_8B; /* Maximum Packet Size 64 bytes */ - USB->DOEP0CTL &= ~_USB_DOEP0CTL_STALL_MASK; /* clear Stall */ - xfer_status[0][TUSB_DIR_OUT].max_size = 8; - xfer_status[0][TUSB_DIR_IN].max_size = 8; - } -} - - -/*------------------------------------------------------------------*/ -/* Controller API */ -/*------------------------------------------------------------------*/ -void dcd_init(uint8_t rhport) -{ - (void) rhport; - - /* Reset Core */ - USB->PCGCCTL &= ~USB_PCGCCTL_STOPPCLK; - USB->PCGCCTL &= ~(USB_PCGCCTL_PWRCLMP | USB_PCGCCTL_RSTPDWNMODULE); - - /* Core Soft Reset */ - USB->GRSTCTL |= USB_GRSTCTL_CSFTRST; - while(USB->GRSTCTL & USB_GRSTCTL_CSFTRST); - - while(!(USB->GRSTCTL & USB_GRSTCTL_AHBIDLE)); - - /* Enable PHY pins */ - USB->ROUTE = USB_ROUTE_PHYPEN; - - dcd_disconnect(rhport); - - /* - * Set device speed (Full speed PHY) - * Stall on non-zero len status OUT packets (ctrl transfers) - * periodic frame interval to 80% - */ - USB->DCFG = (USB->DCFG & ~(_USB_DCFG_DEVSPD_MASK | _USB_DCFG_PERFRINT_MASK)) | USB_DCFG_DEVSPD_FS | USB_DCFG_NZSTSOUTHSHK; - - /* Enable Global Interrupts */ - USB->GAHBCFG = (USB->GAHBCFG & ~_USB_GAHBCFG_HBSTLEN_MASK) | USB_GAHBCFG_GLBLINTRMSK; - - /* Force Device Mode */ - USB->GUSBCFG = (USB->GUSBCFG & ~(GUSBCFG_WO_BITMASK | USB_GUSBCFG_FORCEHSTMODE)) | USB_GUSBCFG_FORCEDEVMODE; - - /* No Overrides */ - USB->GOTGCTL &= ~(USB_GOTGCTL_BVALIDOVVAL | USB_GOTGCTL_BVALIDOVEN | USB_GOTGCTL_VBVALIDOVVAL); - - /* Ignore frame numbers on ISO transfers. */ - USB->DCTL = (USB->DCTL & ~DCTL_WO_BITMASK) | USB_DCTL_IGNRFRMNUM; - - /* Setting SNAKs */ - USB->DOEP0CTL |= USB_DIEP_CTL_SNAK; - for(uint8_t i = 0; i < EP_COUNT - 1; i++) - { - USB->DOEP[i].CTL |= USB_DIEP_CTL_SNAK; - } - - /* D. Interruption masking */ - /* Disable all device interrupts */ - USB->DIEPMSK = 0; - USB->DOEPMSK = 0; - USB->DAINTMSK = 0; - USB->DIEPEMPMSK = 0; - USB->GINTMSK = 0; - USB->GOTGINT = ~0U; /* clear OTG ints */ - USB->GINTSTS = ~0U; /* clear pending ints */ - USB->GINTMSK = USB_GINTMSK_MODEMISMSK | - #if USE_SOF - USB_GINTMSK_SOFMSK | - #endif - USB_GINTMSK_ERLYSUSPMSK | - USB_GINTMSK_USBSUSPMSK | - USB_GINTMSK_USBRSTMSK | - USB_GINTMSK_ENUMDONEMSK | - USB_GINTMSK_RESETDETMSK | - USB_GINTMSK_DISCONNINTMSK; - - NVIC_ClearPendingIRQ(USB_IRQn); - - dcd_connect(rhport); -} - -void dcd_set_address(uint8_t rhport, uint8_t dev_addr) -{ - (void) rhport; - - USB->DCFG = (USB->DCFG & ~_USB_DCFG_DEVADDR_MASK) | (dev_addr << _USB_DCFG_DEVADDR_SHIFT); - - /* Response with status after changing device address */ - dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0); -} - -void dcd_remote_wakeup(uint8_t rhport) -{ - (void) rhport; -} - -void dcd_connect(uint8_t rhport) -{ - (void) rhport; - - /* connect by enabling internal pull-up resistor on D+/D- */ - USB->DCTL &= ~(DCTL_WO_BITMASK | USB_DCTL_SFTDISCON); -} - -void dcd_disconnect(uint8_t rhport) -{ - (void) rhport; - - /* disconnect by disabling internal pull-up resistor on D+/D- */ - USB->DCTL = (USB->DCTL & ~(DCTL_WO_BITMASK)) | USB_DCTL_SFTDISCON; -} - -/*------------------------------------------------------------------*/ -/* DCD Endpoint Port */ -/*------------------------------------------------------------------*/ -void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) -{ - (void) rhport; - - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); - - if(dir == TUSB_DIR_IN) - { - if(epnum == 0) - { - USB->DIEP0CTL = (USB->DIEP0CTL & ~DEPCTL_WO_BITMASK) | USB_DIEP0CTL_SNAK | USB_DIEP0CTL_STALL; - - flush_tx_fifo(_USB_GRSTCTL_TXFNUM_F0); - } - else - { - /* Only disable currently enabled non-control endpoint */ - if(USB->DIEP[epnum - 1].CTL & USB_DIEP_CTL_EPENA) - { - USB->DIEP[epnum - 1].CTL = (USB->DIEP[epnum - 1].CTL & ~DEPCTL_WO_BITMASK) | USB_DIEP_CTL_EPDIS | USB_DIEP_CTL_SNAK | USB_DIEP_CTL_STALL; - while(!(USB->DIEP[epnum - 1].INT & USB_DIEP_INT_EPDISBLD)); - USB->DIEP[epnum - 1].INT |= USB_DIEP_INT_EPDISBLD; - } - else - { - USB->DIEP[epnum - 1].CTL = (USB->DIEP[epnum - 1].CTL & ~DEPCTL_WO_BITMASK) | USB_DIEP_CTL_SNAK | USB_DIEP_CTL_STALL; - } - - /* Flush the FIFO */ - uint8_t const fifo_num = ((USB->DIEP[epnum - 1].CTL & _USB_DIEP_CTL_TXFNUM_MASK) >> _USB_DIEP_CTL_TXFNUM_SHIFT); - flush_tx_fifo(fifo_num); - } - } - else - { - if(epnum == 0) - { - USB->DOEP0CTL = (USB->DOEP0CTL & ~DEPCTL_WO_BITMASK) | USB_DIEP0CTL_STALL; - } - else - { - /* Only disable currently enabled non-control endpoint */ - if(USB->DOEP[epnum - 1].CTL & USB_DIEP_CTL_EPENA) - { - /* Asserting GONAK is required to STALL an OUT endpoint. */ - USB->DCTL |= USB_DCTL_SGOUTNAK; - while(!(USB->GINTSTS & USB_GINTSTS_GOUTNAKEFF)); - - /* Disable the endpoint. Note that only STALL and not SNAK is set here. */ - USB->DOEP[epnum - 1].CTL = (USB->DOEP[epnum - 1].CTL & ~DEPCTL_WO_BITMASK) | USB_DIEP_CTL_EPDIS | USB_DIEP_CTL_STALL; - while(USB->DOEP[epnum - 1].INT & USB_DIEP_INT_EPDISBLD); - USB->DOEP[epnum - 1].INT |= USB_DIEP_INT_EPDISBLD; - - /* Allow other OUT endpoints to keep receiving. */ - USB->DCTL |= USB_DCTL_CGOUTNAK; - } - else - { - USB->DIEP[epnum - 1].CTL = (USB->DIEP[epnum - 1].CTL & ~DEPCTL_WO_BITMASK) | USB_DIEP_CTL_STALL; - } - } - } -} - -void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) -{ - (void) rhport; - - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); - - if(dir == TUSB_DIR_IN) - { - if(epnum == 0) - { - USB->DIEP0CTL &= ~(DEPCTL_WO_BITMASK | USB_DIEP0CTL_STALL); - } - else - { - USB->DIEP[epnum - 1].CTL &= ~(DEPCTL_WO_BITMASK | USB_DIEP_CTL_STALL); - - /* Required by USB spec to reset DATA toggle bit to DATA0 on interrupt and bulk endpoints. */ - uint8_t eptype = (USB->DIEP[epnum - 1].CTL & _USB_DIEP_CTL_EPTYPE_MASK) >> _USB_DIEP_CTL_EPTYPE_SHIFT; - - if((eptype == _USB_DIEP_CTL_EPTYPE_BULK) || (eptype == _USB_DIEP_CTL_EPTYPE_INT)) - { - USB->DIEP[epnum - 1].CTL |= USB_DIEP_CTL_SETD0PIDEF; - } - } - } - else - { - if(epnum == 0) - { - USB->DOEP0CTL &= ~(DEPCTL_WO_BITMASK | USB_DOEP0CTL_STALL); - } - else - { - USB->DOEP[epnum - 1].CTL &= ~(DEPCTL_WO_BITMASK | USB_DOEP_CTL_STALL); - - /* Required by USB spec to reset DATA toggle bit to DATA0 on interrupt and bulk endpoints. */ - uint8_t eptype = (USB->DOEP[epnum - 1].CTL & _USB_DOEP_CTL_EPTYPE_MASK) >> _USB_DOEP_CTL_EPTYPE_SHIFT; - - if((eptype == _USB_DOEP_CTL_EPTYPE_BULK) || (eptype == _USB_DOEP_CTL_EPTYPE_INT)) - { - USB->DOEP[epnum - 1].CTL |= USB_DOEP_CTL_SETD0PIDEF; - } - } - } -} - -bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) -{ - (void)rhport; - - uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress); - uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress); - - TU_ASSERT(epnum < EP_COUNT); - TU_ASSERT(epnum != 0); - - xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir); - xfer->max_size = tu_edpt_packet_size(p_endpoint_desc); - - if(dir == TUSB_DIR_OUT) - { - USB->DOEP[epnum - 1].CTL |= USB_DOEP_CTL_USBACTEP | - (p_endpoint_desc->bmAttributes.xfer << _USB_DOEP_CTL_EPTYPE_SHIFT) | - (xfer->max_size << _USB_DOEP_CTL_MPS_SHIFT); - USB->DAINTMSK |= (1 << (_USB_DAINTMSK_OUTEPMSK0_SHIFT + epnum)); - } - else - { - uint8_t fifo_num = get_free_fifo(); - TU_ASSERT(fifo_num != 0); - - USB->DIEP[epnum - 1].CTL &= ~(_USB_DIEP_CTL_TXFNUM_MASK | _USB_DIEP_CTL_EPTYPE_MASK | USB_DIEP_CTL_SETD0PIDEF | _USB_DIEP_CTL_MPS_MASK); - USB->DIEP[epnum - 1].CTL |= USB_DIEP_CTL_USBACTEP | - (fifo_num << _USB_DIEP_CTL_TXFNUM_SHIFT) | - (p_endpoint_desc->bmAttributes.xfer << _USB_DIEP_CTL_EPTYPE_SHIFT) | - ((p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS) ? USB_DIEP_CTL_SETD0PIDEF : 0) | - (xfer->max_size << 0); - - USB->DAINTMSK |= (1 << epnum); - - /* Both TXFD and TXSA are in unit of 32-bit words. */ - /* IN FIFO 0 was configured during enumeration, hence the "+ 16". */ - uint16_t const allocated_size = (USB->GRXFSIZ & _USB_GRXFSIZ_RXFDEP_MASK) + 16; - uint16_t const fifo_size = (EP_FIFO_SIZE/4 - allocated_size) / (EP_FIFO_NUM-1); - uint32_t const fifo_offset = allocated_size + fifo_size*(fifo_num-1); - - /* DIEPTXF starts at FIFO #1. */ - volatile uint32_t* usb_dieptxf = &USB->DIEPTXF1; - usb_dieptxf[epnum - 1] = (fifo_size << _USB_DIEPTXF1_INEPNTXFDEP_SHIFT) | fifo_offset; - } - return true; -} - -void dcd_edpt_close_all (uint8_t rhport) -{ - (void) rhport; - // TODO implement dcd_edpt_close_all() -} - -bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) -{ - (void)rhport; - - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); - - xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir); - xfer->buffer = buffer; - xfer->total_len = total_bytes; - xfer->queued_len = 0; - xfer->short_packet = false; - - uint16_t num_packets = (total_bytes / xfer->max_size); - uint8_t short_packet_size = total_bytes % xfer->max_size; - - // Zero-size packet is special case. - if(short_packet_size > 0 || (total_bytes == 0)) - { - num_packets++; - } - - // IN and OUT endpoint xfers are interrupt-driven, we just schedule them - // here. - if(dir == TUSB_DIR_IN) - { - if(epnum == 0) - { - // A full IN transfer (multiple packets, possibly) triggers XFRC. - USB->DIEP0TSIZ = (num_packets << _USB_DIEP0TSIZ_PKTCNT_SHIFT) | total_bytes; - USB->DIEP0CTL |= USB_DIEP0CTL_EPENA | USB_DIEP0CTL_CNAK; // Enable | CNAK - } - else - { - // A full IN transfer (multiple packets, possibly) triggers XFRC. - USB->DIEP[epnum - 1].TSIZ = (num_packets << _USB_DIEP_TSIZ_PKTCNT_SHIFT) | total_bytes; - USB->DIEP[epnum - 1].CTL |= USB_DIEP_CTL_EPENA | USB_DIEP_CTL_CNAK; // Enable | CNAK - } - - // Enable fifo empty interrupt only if there are something to put in the fifo. - if(total_bytes != 0) - { - USB->DIEPEMPMSK |= (1 << epnum); - } - } - else - { - if(epnum == 0) - { - // A full IN transfer (multiple packets, possibly) triggers XFRC. - USB->DOEP0TSIZ |= (1 << _USB_DOEP0TSIZ_PKTCNT_SHIFT) | ((xfer->max_size & _USB_DOEP0TSIZ_XFERSIZE_MASK) << _USB_DOEP0TSIZ_XFERSIZE_SHIFT); - USB->DOEP0CTL |= USB_DOEP0CTL_EPENA | USB_DOEP0CTL_CNAK; - } - else - { - // A full IN transfer (multiple packets, possibly) triggers XFRC. - USB->DOEP[epnum - 1].TSIZ |= (1 << _USB_DOEP_TSIZ_PKTCNT_SHIFT) | ((xfer->max_size & _USB_DOEP_TSIZ_XFERSIZE_MASK) << _USB_DOEP_TSIZ_XFERSIZE_SHIFT); - USB->DOEP[epnum - 1].CTL |= USB_DOEP_CTL_EPENA | USB_DOEP_CTL_CNAK; - } - } - return true; -} - -/*------------------------------------------------------------------*/ -/* IRQ */ -/*------------------------------------------------------------------*/ -void dcd_int_enable(uint8_t rhport) -{ - (void) rhport; - - NVIC_EnableIRQ(USB_IRQn); -} - -void dcd_int_disable(uint8_t rhport) -{ - (void) rhport; - - NVIC_DisableIRQ(USB_IRQn); -} - -static void receive_packet(xfer_ctl_t *xfer, uint16_t xfer_size) -{ - uint16_t remaining = xfer->total_len - xfer->queued_len; - uint16_t to_recv_size; - - if(remaining <= xfer->max_size) - { - /* Avoid buffer overflow. */ - to_recv_size = (xfer_size > remaining) ? remaining : xfer_size; - } - else - { - /* Room for full packet, choose recv_size based on what the microcontroller claims. */ - to_recv_size = (xfer_size > xfer->max_size) ? xfer->max_size : xfer_size; - } - - uint8_t to_recv_rem = to_recv_size % 4; - uint16_t to_recv_size_aligned = to_recv_size - to_recv_rem; - - /* Do not assume xfer buffer is aligned. */ - uint8_t *base = (xfer->buffer + xfer->queued_len); - - /* This for loop always runs at least once- skip if less than 4 bytes to collect. */ - if(to_recv_size >= 4) - { - for(uint16_t i = 0; i < to_recv_size_aligned; i += 4) - { - uint32_t tmp = (*USB->FIFO0D); - base[i] = tmp & 0x000000FF; - base[i + 1] = (tmp & 0x0000FF00) >> 8; - base[i + 2] = (tmp & 0x00FF0000) >> 16; - base[i + 3] = (tmp & 0xFF000000) >> 24; - } - } - - /* Do not read invalid bytes from RX FIFO. */ - if(to_recv_rem != 0) - { - uint32_t tmp = (*USB->FIFO0D); - uint8_t *last_32b_bound = base + to_recv_size_aligned; - - last_32b_bound[0] = tmp & 0x000000FF; - if(to_recv_rem > 1) - { - last_32b_bound[1] = (tmp & 0x0000FF00) >> 8; - } - if(to_recv_rem > 2) - { - last_32b_bound[2] = (tmp & 0x00FF0000) >> 16; - } - } - - xfer->queued_len += xfer_size; - - /* Per USB spec, a short OUT packet (including length 0) is always */ - /* indicative of the end of a transfer (at least for ctl, bulk, int). */ - xfer->short_packet = (xfer_size < xfer->max_size); -} - -static void transmit_packet(xfer_ctl_t *xfer, uint8_t fifo_num) -{ - uint16_t remaining; - if(fifo_num == 0) - { - remaining = (USB->DIEP0TSIZ & 0x7FFFFU) >> _USB_DIEP0TSIZ_XFERSIZE_SHIFT; - } - else - { - remaining = (USB->DIEP[fifo_num - 1].TSIZ & 0x7FFFFU) >> _USB_DIEP_TSIZ_XFERSIZE_SHIFT; - } - xfer->queued_len = xfer->total_len - remaining; - - uint16_t to_xfer_size = (remaining > xfer->max_size) ? xfer->max_size : remaining; - uint8_t to_xfer_rem = to_xfer_size % 4; - uint16_t to_xfer_size_aligned = to_xfer_size - to_xfer_rem; - - /* Buffer might not be aligned to 32b, so we need to force alignment by copying to a temp var. */ - uint8_t *base = (xfer->buffer + xfer->queued_len); - - /* This for loop always runs at least once- skip if less than 4 bytes to send off. */ - if(to_xfer_size >= 4) - { - for(uint16_t i = 0; i < to_xfer_size_aligned; i += 4) - { - uint32_t tmp = base[i] | (base[i + 1] << 8) | (base[i + 2] << 16) | (base[i + 3] << 24); - *tx_fifo[fifo_num] = tmp; - } - } - - /* Do not read beyond end of buffer if not divisible by 4. */ - if(to_xfer_rem != 0) - { - uint32_t tmp = 0; - uint8_t *last_32b_bound = base + to_xfer_size_aligned; - - tmp |= last_32b_bound[0]; - if(to_xfer_rem > 1) - { - tmp |= (last_32b_bound[1] << 8); - } - if(to_xfer_rem > 2) - { - tmp |= (last_32b_bound[2] << 16); - } - - *tx_fifo[fifo_num] = tmp; - } -} - -static void read_rx_fifo(void) -{ - /* - * Pop control word off FIFO (completed xfers will have 2 control words, - * we only pop one ctl word each interrupt). - */ - uint32_t const ctl_word = USB->GRXSTSP; - uint8_t const pktsts = (ctl_word & _USB_GRXSTSP_PKTSTS_MASK) >> _USB_GRXSTSP_PKTSTS_SHIFT; - uint8_t const epnum = (ctl_word & _USB_GRXSTSP_CHNUM_MASK ) >> _USB_GRXSTSP_CHNUM_SHIFT; - uint16_t const bcnt = (ctl_word & _USB_GRXSTSP_BCNT_MASK ) >> _USB_GRXSTSP_BCNT_SHIFT; - - switch(pktsts) - { - case 0x01: /* Global OUT NAK (Interrupt) */ - break; - - case 0x02: - { - /* Out packet recvd */ - xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT); - receive_packet(xfer, bcnt); - } - break; - - case 0x03: - /* Out packet done (Interrupt) */ - break; - - case 0x04: - /* Step 2: Setup transaction completed (Interrupt) */ - /* After this event, OEPINT interrupt will occur with SETUP bit set */ - if(epnum == 0) - { - USB->DOEP0TSIZ |= (1 << _USB_DOEP0TSIZ_SUPCNT_SHIFT); - } - - break; - - case 0x06: - { - /* Step1: Setup data packet received */ - - /* - * We can receive up to three setup packets in succession, but - * only the last one is valid. Therefore we just overwrite it - */ - _setup_packet[0] = (*USB->FIFO0D); - _setup_packet[1] = (*USB->FIFO0D); - } - break; - - default: - /* Invalid, breakpoint. */ - TU_BREAKPOINT(); - break; - } -} - -static void handle_epout_ints(void) -{ - // GINTSTS will be cleared with DAINT == 0 - // DAINT for a given EP clears when DOEPINTx is cleared. - // DOEPINT will be cleared when DAINT's out bits are cleared. - - for(uint8_t n = 0; n < EP_COUNT; n++) - { - xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT); - - if(n == 0) - { - if(USB->DAINT & (1 << (_USB_DAINT_OUTEPINT0_SHIFT + n))) - { - // SETUP packet Setup Phase done. - if((USB->DOEP0INT & USB_DOEP0INT_SETUP)) - { - USB->DOEP0INT = USB_DOEP0INT_STUPPKTRCVD | USB_DOEP0INT_SETUP; // clear - dcd_event_setup_received(0, (uint8_t *)&_setup_packet[0], true); - } - - // OUT XFER complete (single packet).q - if(USB->DOEP0INT & USB_DOEP0INT_XFERCOMPL) - { - USB->DOEP0INT = USB_DOEP0INT_XFERCOMPL; - - // Transfer complete if short packet or total len is transferred - if(xfer->short_packet || (xfer->queued_len == xfer->total_len)) - { - xfer->short_packet = false; - dcd_event_xfer_complete(0, n, xfer->queued_len, XFER_RESULT_SUCCESS, true); - } - else - { - // Schedule another packet to be received. - USB->DOEP0TSIZ |= (1 << _USB_DOEP0TSIZ_PKTCNT_SHIFT) | ((xfer->max_size & _USB_DOEP0TSIZ_XFERSIZE_MASK) << _USB_DOEP0TSIZ_XFERSIZE_SHIFT); - USB->DOEP0CTL |= USB_DOEP0CTL_EPENA | USB_DOEP0CTL_CNAK; - } - } - } - } - else - { - if(USB->DAINT & (1 << (_USB_DAINT_OUTEPINT0_SHIFT + n))) - { - // SETUP packet Setup Phase done. - if((USB->DOEP[n - 1].INT & USB_DOEP_INT_SETUP)) - { - USB->DOEP[n - 1].INT = USB_DOEP_INT_STUPPKTRCVD | USB_DOEP_INT_SETUP; // clear - dcd_event_setup_received(0, (uint8_t *)&_setup_packet[0], true); - } - - // OUT XFER complete (single packet).q - if(USB->DOEP[n - 1].INT & USB_DOEP_INT_XFERCOMPL) - { - USB->DOEP[n - 1].INT = USB_DOEP_INT_XFERCOMPL; - - // Transfer complete if short packet or total len is transferred - if(xfer->short_packet || (xfer->queued_len == xfer->total_len)) - { - xfer->short_packet = false; - dcd_event_xfer_complete(0, n, xfer->queued_len, XFER_RESULT_SUCCESS, true); - } - else - { - // Schedule another packet to be received. - USB->DOEP[n - 1].TSIZ |= (1 << _USB_DOEP_TSIZ_PKTCNT_SHIFT) | ((xfer->max_size & _USB_DOEP_TSIZ_XFERSIZE_MASK) << _USB_DOEP_TSIZ_XFERSIZE_SHIFT); - USB->DOEP[n - 1].CTL |= USB_DOEP_CTL_EPENA | USB_DOEP_CTL_CNAK; - } - } - } - } - } -} - -static void handle_epin_ints(void) -{ - - for(uint32_t n = 0; n < EP_COUNT; n++) - { - xfer_ctl_t *xfer = &xfer_status[n][TUSB_DIR_IN]; - - if(n == 0) - { - if(USB->DAINT & (1 << n)) - { - /* IN XFER complete (entire xfer). */ - if(USB->DIEP0INT & USB_DIEP0INT_XFERCOMPL) - { - USB->DIEP0INT = USB_DIEP0INT_XFERCOMPL; - dcd_event_xfer_complete(0, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true); - } - - /* XFER FIFO empty */ - if(USB->DIEP0INT & USB_DIEP0INT_TXFEMP) - { - USB->DIEP0INT = USB_DIEP0INT_TXFEMP; - transmit_packet(xfer, n); - - /* Turn off TXFE if all bytes are written. */ - if(xfer->queued_len == xfer->total_len) - { - USB->DIEPEMPMSK &= ~(1 << n); - } - } - - /* XFER Timeout */ - if(USB->DIEP0INT & USB_DIEP0INT_TIMEOUT) - { - /* Clear interrupt or enpoint will hang. */ - USB->DIEP0INT = USB_DIEP0INT_TIMEOUT; - } - } - } - else - { - if(USB->DAINT & (1 << n)) - { - /* IN XFER complete (entire xfer). */ - if(USB->DIEP[n - 1].INT & USB_DIEP_INT_XFERCOMPL) - { - USB->DIEP[n - 1].INT = USB_DIEP_INT_XFERCOMPL; - dcd_event_xfer_complete(0, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true); - } - - /* XFER FIFO empty */ - if(USB->DIEP[n - 1].INT & USB_DIEP_INT_TXFEMP) - { - USB->DIEP[n - 1].INT = USB_DIEP_INT_TXFEMP; - transmit_packet(xfer, n); - - /* Turn off TXFE if all bytes are written. */ - if(xfer->queued_len == xfer->total_len) - { - USB->DIEPEMPMSK &= ~(1 << n); - } - } - - /* XFER Timeout */ - if(USB->DIEP[n - 1].INT & USB_DIEP_INT_TIMEOUT) - { - /* Clear interrupt or enpoint will hang. */ - USB->DIEP[n - 1].INT = USB_DIEP_INT_TIMEOUT; - } - } - } - } -} - -void dcd_int_handler(uint8_t rhport) -{ - (void) rhport; - - const uint32_t int_status = USB->GINTSTS; - - /* USB Reset */ - if(int_status & USB_GINTSTS_USBRST) - { - /* start of reset */ - USB->GINTSTS = USB_GINTSTS_USBRST; - /* FIFOs will be reassigned when the endpoints are reopen */ - _allocated_fifos = 1; - bus_reset(); - } - - /* Reset detected Interrupt */ - if(int_status & USB_GINTSTS_RESETDET) - { - USB->GINTSTS = USB_GINTSTS_RESETDET; - bus_reset(); - } - - /* Enumeration Done */ - if(int_status & USB_GINTSTS_ENUMDONE) - { - /* This interrupt is considered the end of reset. */ - USB->GINTSTS = USB_GINTSTS_ENUMDONE; - enum_done_processing(); - dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true); - } - - /* OTG Interrupt */ - if(int_status & USB_GINTSTS_OTGINT) - { - /* OTG INT bit is read-only */ - - uint32_t const otg_int = USB->GOTGINT; - - if(otg_int & USB_GOTGINT_SESENDDET) - { - dcd_event_bus_signal(0, DCD_EVENT_UNPLUGGED, true); - } - - USB->GOTGINT = otg_int; - } - - #if USE_SOF - if(int_status & USB_GINTSTS_SOF) - { - USB->GINTSTS = USB_GINTSTS_SOF; - dcd_event_bus_signal(0, DCD_EVENT_SOF, true); - } - #endif - - /* RxFIFO Non-Empty */ - if(int_status & USB_GINTSTS_RXFLVL) - { - /* RXFLVL bit is read-only */ - - /* Mask out RXFLVL while reading data from FIFO */ - USB->GINTMSK &= ~USB_GINTMSK_RXFLVLMSK; - read_rx_fifo(); - USB->GINTMSK |= USB_GINTMSK_RXFLVLMSK; - } - - /* OUT Endpoints Interrupt */ - if(int_status & USB_GINTMSK_OEPINTMSK) - { - /* OEPINT is read-only */ - handle_epout_ints(); - } - - /* IN Endpoints Interrupt */ - if(int_status & USB_GINTMSK_IEPINTMSK) - { - /* IEPINT bit read-only */ - handle_epin_ints(); - } - - /* unhandled */ - USB->GINTSTS |= USB_GINTSTS_CURMOD | - USB_GINTSTS_MODEMIS | - USB_GINTSTS_OTGINT | - USB_GINTSTS_NPTXFEMP | - USB_GINTSTS_GINNAKEFF | - USB_GINTSTS_GOUTNAKEFF | - USB_GINTSTS_ERLYSUSP | - USB_GINTSTS_USBSUSP | - USB_GINTSTS_ISOOUTDROP | - USB_GINTSTS_EOPF | - USB_GINTSTS_EPMIS | - USB_GINTSTS_INCOMPISOIN | - USB_GINTSTS_INCOMPLP | - USB_GINTSTS_FETSUSP | - USB_GINTSTS_PTXFEMP; -} - -#endif diff --git a/src/portable/synopsys/dwc2/dwc2_efm32.h b/src/portable/synopsys/dwc2/dwc2_efm32.h new file mode 100644 index 000000000..ee4c3c715 --- /dev/null +++ b/src/portable/synopsys/dwc2/dwc2_efm32.h @@ -0,0 +1,87 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Rafael Silva (@perigoso) + * Copyright (c) 2021, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef _DWC2_EFM32_H_ +#define _DWC2_EFM32_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "em_device.h" + +// EFM32 has custom control register before DWC registers +#define DWC2_REG_BASE (USB_BASE + offsetof(USB_TypeDef, GOTGCTL)) +#define DWC2_EP_MAX 7 +#define DWC2_EP_FIFO_SIZE 2048 + +TU_ATTR_ALWAYS_INLINE +static inline void dwc2_dcd_int_enable(uint8_t rhport) +{ + (void) rhport; + NVIC_EnableIRQ(USB_IRQn); +} + +TU_ATTR_ALWAYS_INLINE +static inline void dwc2_dcd_int_disable (uint8_t rhport) +{ + (void) rhport; + NVIC_DisableIRQ(USB_IRQn); +} + +static inline void dwc2_remote_wakeup_delay(void) +{ + // try to delay for 1 ms +// uint32_t count = SystemCoreClock / 1000; +// while ( count-- ) __NOP(); +} + +// MCU specific PHY init, called BEFORE core reset +static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type) +{ + (void) dwc2; + (void) hs_phy_type; + + // Enable PHY + USB->ROUTE = USB_ROUTE_PHYPEN; +} + +// MCU specific PHY update, it is called AFTER init() and core reset +static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type) +{ + (void) dwc2; + (void) hs_phy_type; + + // EFM32 Manual: turn around must be 5 (reset & default value) + // dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_TRDT_Msk) | (5u << GUSBCFG_TRDT_Pos); +} + +#ifdef __cplusplus +} +#endif + +#endif -- cgit v1.3.1 From 215e0595ab568215a7d0a0c927b076bd02951fa6 Mon Sep 17 00:00:00 2001 From: hathach Date: Sun, 31 Oct 2021 00:09:40 +0700 Subject: change F207 to use new dwc2 --- hw/bsp/stm32f207nucleo/board.mk | 2 +- hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk | 3 +++ src/portable/synopsys/dwc2/dcd_dwc2.c | 6 +++--- 3 files changed, 7 insertions(+), 4 deletions(-) diff --git a/hw/bsp/stm32f207nucleo/board.mk b/hw/bsp/stm32f207nucleo/board.mk index 2b979f3d8..fa7d28399 100644 --- a/hw/bsp/stm32f207nucleo/board.mk +++ b/hw/bsp/stm32f207nucleo/board.mk @@ -21,7 +21,7 @@ CFLAGS += -Wno-error=sign-compare LD_FILE = hw/bsp/$(BOARD)/STM32F207ZGTx_FLASH.ld SRC_C += \ - src/portable/st/synopsys/dcd_synopsys.c \ + src/portable/synopsys/dwc2/dcd_dwc2.c \ $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \ $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \ $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \ diff --git a/hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk b/hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk index 2400a4ba7..7710619e5 100644 --- a/hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk +++ b/hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk @@ -8,5 +8,8 @@ CFLAGS += \ LD_FILE = $(BOARD_PATH)/STM32F767ZITx_FLASH.ld SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f767xx.s +# For flash-jlink target +JLINK_DEVICE = stm32f767zi + # flash target using on-board stlink flash: flash-stlink diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 16780cba8..e2a999ac0 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -264,9 +264,9 @@ void print_dwc2_info(dwc2_regs_t * dwc2) dwc2_ghwcfg3_t const * hw_cfg3 = &dwc2->ghwcfg3_bm; dwc2_ghwcfg4_t const * hw_cfg4 = &dwc2->ghwcfg4_bm; - TU_LOG_HEX(DWC2_DEBUG, dwc2->gotgctl); - TU_LOG_HEX(DWC2_DEBUG, dwc2->gusbcfg); - TU_LOG_HEX(DWC2_DEBUG, dwc2->dcfg); +// TU_LOG_HEX(DWC2_DEBUG, dwc2->gotgctl); +// TU_LOG_HEX(DWC2_DEBUG, dwc2->gusbcfg); +// TU_LOG_HEX(DWC2_DEBUG, dwc2->dcfg); TU_LOG_HEX(DWC2_DEBUG, dwc2->guid); TU_LOG_HEX(DWC2_DEBUG, dwc2->gsnpsid); TU_LOG_HEX(DWC2_DEBUG, dwc2->ghwcfg1); -- cgit v1.3.1 From 4ea8f1441dda442d784ee57f39a0adc75bf69e56 Mon Sep 17 00:00:00 2001 From: hathach Date: Sun, 31 Oct 2021 00:19:17 +0700 Subject: correct freertos port for efm32gg --- examples/device/cdc_msc_freertos/.skip.MCU_EFM32GG12 | 0 examples/device/hid_composite_freertos/.skip.MCU_EFM32GG12 | 0 hw/bsp/sltb009a/board.mk | 6 +----- 3 files changed, 1 insertion(+), 5 deletions(-) delete mode 100644 examples/device/cdc_msc_freertos/.skip.MCU_EFM32GG12 delete mode 100644 examples/device/hid_composite_freertos/.skip.MCU_EFM32GG12 diff --git a/examples/device/cdc_msc_freertos/.skip.MCU_EFM32GG12 b/examples/device/cdc_msc_freertos/.skip.MCU_EFM32GG12 deleted file mode 100644 index e69de29bb..000000000 diff --git a/examples/device/hid_composite_freertos/.skip.MCU_EFM32GG12 b/examples/device/hid_composite_freertos/.skip.MCU_EFM32GG12 deleted file mode 100644 index e69de29bb..000000000 diff --git a/hw/bsp/sltb009a/board.mk b/hw/bsp/sltb009a/board.mk index 7a046b34b..f5c240ca2 100644 --- a/hw/bsp/sltb009a/board.mk +++ b/hw/bsp/sltb009a/board.mk @@ -34,12 +34,8 @@ INC += \ $(TOP)/$(SILABS_CMSIS)/Include \ $(TOP)/hw/bsp/$(BOARD) -# For TinyUSB port source -VENDOR = silabs -CHIP_FAMILY = efm32 - # For freeRTOS port source -FREERTOS_PORT = ARM_CM4 +FREERTOS_PORT = ARM_CM3 # For flash-jlink target JLINK_DEVICE = EFM32GG12B810F1024 -- cgit v1.3.1 From ba34f420db26faf7d42f574cce0c3b4c0f4ccb38 Mon Sep 17 00:00:00 2001 From: Jean Gressmann Date: Sat, 30 Oct 2021 14:39:03 +0200 Subject: Adds support for Adafruit Trinket M0 --- hw/bsp/samd21/boards/trinket_m0/board.h | 34 ++++++ hw/bsp/samd21/boards/trinket_m0/board.mk | 5 + hw/bsp/samd21/boards/trinket_m0/trinket_m0.ld | 146 ++++++++++++++++++++++++++ hw/bsp/samd21/family.c | 83 +++++++++++++++ 4 files changed, 268 insertions(+) create mode 100644 hw/bsp/samd21/boards/trinket_m0/board.h create mode 100644 hw/bsp/samd21/boards/trinket_m0/board.mk create mode 100644 hw/bsp/samd21/boards/trinket_m0/trinket_m0.ld diff --git a/hw/bsp/samd21/boards/trinket_m0/board.h b/hw/bsp/samd21/boards/trinket_m0/board.h new file mode 100644 index 000000000..c8692e6bd --- /dev/null +++ b/hw/bsp/samd21/boards/trinket_m0/board.h @@ -0,0 +1,34 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Jean Gressmann + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + */ + +#pragma once + +// LED +#define LED_PIN 10 // PA10 +#define LED_STATE_ON 1 + +// UART +#define UART_SERCOM 0 + diff --git a/hw/bsp/samd21/boards/trinket_m0/board.mk b/hw/bsp/samd21/boards/trinket_m0/board.mk new file mode 100644 index 000000000..803ffe892 --- /dev/null +++ b/hw/bsp/samd21/boards/trinket_m0/board.mk @@ -0,0 +1,5 @@ +CFLAGS += -D__SAMD21E18A__ -DCFG_EXAMPLE_VIDEO_READONLY + +# All source paths should be relative to the top level. +LD_FILE = $(BOARD_PATH)/trinket_m0.ld + diff --git a/hw/bsp/samd21/boards/trinket_m0/trinket_m0.ld b/hw/bsp/samd21/boards/trinket_m0/trinket_m0.ld new file mode 100644 index 000000000..f0c93340c --- /dev/null +++ b/hw/bsp/samd21/boards/trinket_m0/trinket_m0.ld @@ -0,0 +1,146 @@ +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAMD21G18A + * + * Copyright (c) 2017 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00000000 + 8K, LENGTH = 0x00040000 - 8K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000; + +ENTRY(Reset_Handler) + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + end = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/hw/bsp/samd21/family.c b/hw/bsp/samd21/family.c index 10e40e3f0..3fa6ea7d8 100644 --- a/hw/bsp/samd21/family.c +++ b/hw/bsp/samd21/family.c @@ -44,6 +44,11 @@ void USB_Handler(void) tud_int_handler(0); } +//--------------------------------------------------------------------+ +// UART support +//--------------------------------------------------------------------+ +void uart_init(void); + //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM DECLARATION //--------------------------------------------------------------------+ @@ -84,6 +89,8 @@ void board_init(void) gpio_set_pin_pull_mode(BUTTON_PIN, BUTTON_STATE_ACTIVE ? GPIO_PULL_DOWN : GPIO_PULL_UP); #endif + uart_init(); + #if CFG_TUSB_OS == OPT_OS_FREERTOS // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); @@ -138,6 +145,81 @@ uint32_t board_button_read(void) #endif } +#if defined(UART_SERCOM) + +#define BOARD_SERCOM2(n) SERCOM ## n +#define BOARD_SERCOM(n) BOARD_SERCOM2(n) + +void uart_init(void) +{ +#if UART_SERCOM == 0 + gpio_set_pin_function(PIN_PA06, PINMUX_PA06D_SERCOM0_PAD2); + gpio_set_pin_function(PIN_PA07, PINMUX_PA07D_SERCOM0_PAD3); + + // setup clock (48MHz) + _pm_enable_bus_clock(PM_BUS_APBC, SERCOM0); + _gclk_enable_channel(SERCOM0_GCLK_ID_CORE, GCLK_CLKCTRL_GEN_GCLK0_Val); + + SERCOM0->USART.CTRLA.bit.SWRST = 1; /* reset SERCOM & enable config */ + while(SERCOM0->USART.SYNCBUSY.bit.SWRST); + + SERCOM0->USART.CTRLA.reg = /* CMODE = 0 -> async, SAMPA = 0, FORM = 0 -> USART frame, SMPR = 0 -> arithmetic baud rate */ + SERCOM_USART_CTRLA_SAMPR(1) | /* 0 = 16x / arithmetic baud rate, 1 = 16x / fractional baud rate */ +// SERCOM_USART_CTRLA_FORM(0) | /* 0 = USART Frame, 2 = LIN Master */ + SERCOM_USART_CTRLA_DORD | /* LSB first */ + SERCOM_USART_CTRLA_MODE(1) | /* 0 = Asynchronous, 1 = USART with internal clock */ + SERCOM_USART_CTRLA_RXPO(3) | /* pad 3 */ + SERCOM_USART_CTRLA_TXPO(1); /* pad 2 */ + + SERCOM0->USART.CTRLB.reg = + SERCOM_USART_CTRLB_TXEN | /* tx enabled */ + SERCOM_USART_CTRLB_RXEN; /* rx enabled */ + + SERCOM0->USART.BAUD.reg = SERCOM_USART_BAUD_FRAC_FP(0) | SERCOM_USART_BAUD_FRAC_BAUD(26); + + SERCOM0->USART.CTRLA.bit.ENABLE = 1; /* activate SERCOM */ + while(SERCOM0->USART.SYNCBUSY.bit.ENABLE); /* wait for SERCOM to be ready */ +#endif +} + +static inline void uart_send_buffer(uint8_t const *text, size_t len) +{ + for (size_t i = 0; i < len; ++i) { + BOARD_SERCOM(UART_SERCOM)->USART.DATA.reg = text[i]; + while((BOARD_SERCOM(UART_SERCOM)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) == 0); + } +} + +static inline void uart_send_str(const char* text) +{ + while (*text) { + BOARD_SERCOM(UART_SERCOM)->USART.DATA.reg = *text++; + while((BOARD_SERCOM(UART_SERCOM)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) == 0); + } +} + +int board_uart_read(uint8_t* buf, int len) +{ + (void) buf; (void) len; + return 0; +} + +int board_uart_write(void const * buf, int len) +{ + if (len < 0) { + uart_send_str(buf); + } else { + uart_send_buffer(buf, len); + } + return len; +} + +#else // ! defined(UART_SERCOM) +void uart_init(void) +{ + +} + int board_uart_read(uint8_t* buf, int len) { (void) buf; (void) len; @@ -149,6 +231,7 @@ int board_uart_write(void const * buf, int len) (void) buf; (void) len; return 0; } +#endif #if CFG_TUSB_OS == OPT_OS_NONE volatile uint32_t system_ticks = 0; -- cgit v1.3.1 From 5fb16a8f2c2c160e9e3e3c1161b038b6fc421c14 Mon Sep 17 00:00:00 2001 From: Jean Gressmann Date: Mon, 1 Nov 2021 18:01:18 +0100 Subject: samd21: enable SysTick only if running w/o OS --- hw/bsp/samd21/family.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/bsp/samd21/family.c b/hw/bsp/samd21/family.c index 3fa6ea7d8..cead582e9 100644 --- a/hw/bsp/samd21/family.c +++ b/hw/bsp/samd21/family.c @@ -75,7 +75,9 @@ void board_init(void) // Update SystemCoreClock since it is hard coded with asf4 and not correct // Init 1ms tick timer (samd SystemCoreClock may not correct) SystemCoreClock = CONF_CPU_FREQUENCY; +#if CFG_TUSB_OS == OPT_OS_NONE SysTick_Config(CONF_CPU_FREQUENCY / 1000); +#endif // Led init #ifdef LED_PIN -- cgit v1.3.1 From aa682d730123a1191782b1a160ce25ea20580ee6 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 2 Nov 2021 13:52:30 +0700 Subject: add fix for stm32l4 (version 3.10a) which generate transfer complete when setup recieved and control out data complete --- hw/bsp/stm32l476disco/board.mk | 6 +- hw/bsp/stm32l476disco/stm32l476disco.c | 8 +- src/device/dcd_attr.h | 1 + src/portable/synopsys/dwc2/dcd_dwc2.c | 151 ++++++++++++++++++++++----------- src/portable/synopsys/dwc2/dwc2_type.h | 11 +++ 5 files changed, 122 insertions(+), 55 deletions(-) diff --git a/hw/bsp/stm32l476disco/board.mk b/hw/bsp/stm32l476disco/board.mk index 28824efdc..8d9e267cf 100644 --- a/hw/bsp/stm32l476disco/board.mk +++ b/hw/bsp/stm32l476disco/board.mk @@ -21,8 +21,9 @@ CFLAGS += -Wno-error=maybe-uninitialized -Wno-error=cast-align # All source paths should be relative to the top level. LD_FILE = hw/bsp/$(BOARD)/STM32L476VGTx_FLASH.ld +#src/portable/st/synopsys/dcd_synopsys.c SRC_C += \ - src/portable/st/synopsys/dcd_synopsys.c \ + src/portable/synopsys/dwc2/dcd_dwc2.c \ $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \ $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \ $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \ @@ -52,5 +53,4 @@ JLINK_DEVICE = stm32l476vg STM32Prog = STM32_Programmer_CLI # flash target using on-board stlink -flash: $(BUILD)/$(PROJECT).elf - $(STM32Prog) --connect port=swd --write $< --go +flash: flash-stlink diff --git a/hw/bsp/stm32l476disco/stm32l476disco.c b/hw/bsp/stm32l476disco/stm32l476disco.c index b18846685..bc1b6c929 100644 --- a/hw/bsp/stm32l476disco/stm32l476disco.c +++ b/hw/bsp/stm32l476disco/stm32l476disco.c @@ -186,8 +186,12 @@ void board_init(void) /* Enable USB FS Clock */ __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); - // Enable VBUS sense (B device) via pin PA9 - USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN; +// // Enable VBUS sense (B device) via pin PA9 +// USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN; + + // L476Disco use general GPIO PC11 for VBUS sensing instead of dedicated PA9 as others + // Disable VBUS Sense and force device mode + USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN; } //--------------------------------------------------------------------+ diff --git a/src/device/dcd_attr.h b/src/device/dcd_attr.h index 70854f9c6..952a8b8c8 100644 --- a/src/device/dcd_attr.h +++ b/src/device/dcd_attr.h @@ -125,6 +125,7 @@ #elif TU_CHECK_MCU(OPT_MCU_STM32L4) #if defined (STM32L475xx) || defined (STM32L476xx) || \ defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || \ + defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \ defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || \ defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define DCD_ATTR_ENDPOINT_MAX 6 diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index e2a999ac0..83abc635b 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -123,8 +123,8 @@ static void bus_reset(uint8_t rhport) dwc2->epout[n].doepctl |= DOEPCTL_SNAK; } - // 2. Un-mask interrupt bits - dwc2->daintmsk = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos); + // 2. Set up interrupt mask + dwc2->daintmsk = TU_BIT(DAINTMSK_OEPM_Pos) | TU_BIT(DAINTMSK_IEPM_Pos); dwc2->doepmsk = DOEPMSK_STUPM | DOEPMSK_XFRCM; dwc2->diepmsk = DIEPMSK_TOM | DIEPMSK_XFRCM; @@ -472,9 +472,6 @@ void dcd_init (uint8_t rhport) // Restart PHY clock dwc2->pcgctl &= ~(PCGCTL_STOPPCLK | PCGCTL_GATEHCLK | PCGCTL_PWRCLMP | PCGCTL_RSTPDWNMODULE); - // Force device mode - dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FHMOD) | GUSBCFG_FDMOD; - /* Set HS/FS Timeout Calibration to 7 (max available value). * The number of PHY clocks that the application programs in * this field is added to the high/full speed interpacket timeout @@ -485,13 +482,16 @@ void dcd_init (uint8_t rhport) */ dwc2->gusbcfg |= (7ul << GUSBCFG_TOCAL_Pos); + // Force device mode + dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FHMOD) | GUSBCFG_FDMOD; + + // Clear A override, force B Valid + dwc2->gotgctl = (dwc2->gotgctl & ~GOTGCTL_AVALOEN) | GOTGCTL_BVALOEN | GOTGCTL_BVALOVAL; + // If USB host misbehaves during status portion of control xfer // (non zero-length packet), send STALL back and discard. dwc2->dcfg |= DCFG_NZLSOHSK; - // Clear A,B, VBus valid override - dwc2->gotgctl &= ~(GOTGCTL_BVALOEN | GOTGCTL_AVALOEN | GOTGCTL_VBVALOEN); - // Clear all interrupts dwc2->gintsts |= dwc2->gintsts; dwc2->gotgint |= dwc2->gotgint; @@ -609,7 +609,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DOEPCTL_SD0PID_SEVNFRM : 0) | (xfer->max_size << DOEPCTL_MPSIZ_Pos); - dwc2->daintmsk |= (1 << (DAINTMSK_OEPM_Pos + epnum)); + dwc2->daintmsk |= TU_BIT(DAINTMSK_OEPM_Pos + epnum); } else { @@ -696,19 +696,21 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t if(epnum == 0) { ep0_pending[dir] = total_bytes; + // Schedule the first transaction for EP0 transfer edpt_schedule_packets(rhport, epnum, dir, 1, ep0_pending[dir]); - return true; } + else + { + uint16_t num_packets = (total_bytes / xfer->max_size); + uint16_t const short_packet_size = total_bytes % xfer->max_size; - uint16_t num_packets = (total_bytes / xfer->max_size); - uint16_t const short_packet_size = total_bytes % xfer->max_size; - - // Zero-size packet is special case. - if ( short_packet_size > 0 || (total_bytes == 0) ) num_packets++; + // Zero-size packet is special case. + if ( (short_packet_size > 0) || (total_bytes == 0) ) num_packets++; - // Schedule packets to be sent within interrupt - edpt_schedule_packets(rhport, epnum, dir, num_packets, total_bytes); + // Schedule packets to be sent within interrupt + edpt_schedule_packets(rhport, epnum, dir, num_packets, total_bytes); + } return true; } @@ -924,21 +926,49 @@ static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t const * static void handle_rxflvl_irq(uint8_t rhport) { dwc2_regs_t * dwc2 = DWC2_REG(rhport); - volatile uint32_t * rx_fifo = dwc2->fifo[0]; + volatile uint32_t const * rx_fifo = dwc2->fifo[0]; // Pop control word off FIFO - uint32_t ctl_word = dwc2->grxstsp; - uint8_t pktsts = (ctl_word & GRXSTSP_PKTSTS_Msk ) >> GRXSTSP_PKTSTS_Pos; - uint8_t epnum = (ctl_word & GRXSTSP_EPNUM_Msk ) >> GRXSTSP_EPNUM_Pos; - uint16_t bcnt = (ctl_word & GRXSTSP_BCNT_Msk ) >> GRXSTSP_BCNT_Pos; + uint32_t const ctl_word = dwc2->grxstsp; + uint8_t const pktsts = (ctl_word & GRXSTSP_PKTSTS_Msk ) >> GRXSTSP_PKTSTS_Pos; + uint8_t const epnum = (ctl_word & GRXSTSP_EPNUM_Msk ) >> GRXSTSP_EPNUM_Pos; + uint16_t const bcnt = (ctl_word & GRXSTSP_BCNT_Msk ) >> GRXSTSP_BCNT_Pos; + + dwc2_epout_t* epout = &dwc2->epout[epnum]; + +#if CFG_TUSB_DEBUG >= (DWC2_DEBUG + 1) + const char * pktsts_str[] = + { + "ASSERT", "Global NAK (ISR)", "Out Data Received", "Out Transfer Complete (ISR)", + "Setup Complete (ISR)", "ASSERT", "Setup Data Received" + }; + TU_LOG_LOCATION(); + TU_LOG(DWC2_DEBUG, " EP %02X, Byte Count %u, %s\r\n", epnum, bcnt, pktsts_str[pktsts]); + TU_LOG(DWC2_DEBUG, " daint = %08lX, doepint = %04lX\r\n", dwc2->daint, epout->doepint); +#endif switch ( pktsts ) { - case 0x01: // Global OUT NAK (Interrupt) + // Global OUT NAK: do nothign + case GRXSTS_PKTSTS_GLOBALOUTNAK: break; + + case GRXSTS_PKTSTS_SETUPRX: + // Setup packet received + + // We can receive up to three setup packets in succession, but + // only the last one is valid. + _setup_packet[0] = (*rx_fifo); + _setup_packet[1] = (*rx_fifo); + break; + + case GRXSTS_PKTSTS_SETUPDONE: + // Setup packet done (Interrupt) + epout->doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos); break; - case 0x02: // Out packet received + case GRXSTS_PKTSTS_OUTRX: { + // Out packet received xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT); // Read packet off RxFIFO @@ -959,7 +989,7 @@ static void handle_rxflvl_irq(uint8_t rhport) // Truncate transfer length in case of short packet if ( bcnt < xfer->max_size ) { - xfer->total_len -= (dwc2->epout[epnum].doeptsiz & DOEPTSIZ_XFRSIZ_Msk) >> DOEPTSIZ_XFRSIZ_Pos; + xfer->total_len -= (epout->doeptsiz & DOEPTSIZ_XFRSIZ_Msk) >> DOEPTSIZ_XFRSIZ_Pos; if ( epnum == 0 ) { xfer->total_len -= ep0_pending[TUSB_DIR_OUT]; @@ -969,18 +999,28 @@ static void handle_rxflvl_irq(uint8_t rhport) } break; - case 0x03: // Out packet done (Interrupt) - break; - - case 0x04: // Setup packet done (Interrupt) - dwc2->epout[epnum].doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos); - break; + // Out packet done (Interrupt) + case GRXSTS_PKTSTS_OUTDONE: + // Occurred on STM32L47 with dwc2 version 3.10a but not found on other version like 2.80a or 3.30a + // May (or not) be 3.10a specific feature/bug or depending on MCU configuration + // XFRC complete is additionally generated when + // - setup packet is received + // - complete the data stage of control write is complete + if ((epnum == 0) && (bcnt == 0) && (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a)) + { + if (epout->doepint & DOEPINT_STPKTRX) + { + // skip this "no-data" transfer complete event + // STPKTRX will be clear later by setup received handler + epout->doepint = DOEPINT_XFRC; + } - case 0x06: // Setup packet recvd - // We can receive up to three setup packets in succession, but - // only the last one is valid. - _setup_packet[0] = (*rx_fifo); - _setup_packet[1] = (*rx_fifo); + if (epout->doepint & DOEPINT_OTEPSPR) + { + // skip this "no-data" transfer complete event + epout->doepint = DOEPINT_XFRC | DOEPINT_OTEPSPR; + } + } break; default: // Invalid @@ -992,27 +1032,38 @@ static void handle_rxflvl_irq(uint8_t rhport) static void handle_epout_irq (uint8_t rhport) { dwc2_regs_t *dwc2 = DWC2_REG(rhport); - dwc2_epout_t* epout = dwc2->epout; // DAINT for a given EP clears when DOEPINTx is cleared. // OEPINT will be cleared when DAINT's out bits are cleared. for ( uint8_t n = 0; n < DWC2_EP_MAX; n++ ) { - xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT); - - if ( dwc2->daint & (1 << (DAINT_OEPINT_Pos + n)) ) + if ( dwc2->daint & TU_BIT(DAINT_OEPINT_Pos + n) ) { + dwc2_epout_t* epout = &dwc2->epout[n]; + + uint32_t const doepint = epout->doepint; + // SETUP packet Setup Phase done. - if ( epout[n].doepint & DOEPINT_STUP ) + if ( doepint & DOEPINT_STUP ) { - epout[n].doepint = DOEPINT_STUP; - dcd_event_setup_received(rhport, (uint8_t*) &_setup_packet[0], true); + uint32_t clear_flag = DOEPINT_STUP; + + // STPKTRX is only available for version from 3_00a + if ((doepint & DOEPINT_STPKTRX) && (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a)) + { + clear_flag |= DOEPINT_STPKTRX; + } + + epout->doepint = clear_flag; + dcd_event_setup_received(rhport, (uint8_t*) _setup_packet, true); } // OUT XFER complete - if ( epout[n].doepint & DOEPINT_XFRC ) + if ( epout->doepint & DOEPINT_XFRC ) { - epout[n].doepint = DOEPINT_XFRC; + epout->doepint = DOEPINT_XFRC; + + xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT); // EP0 can only handle one packet if ( (n == 0) && ep0_pending[TUSB_DIR_OUT] ) @@ -1038,11 +1089,11 @@ static void handle_epin_irq (uint8_t rhport) // IEPINT will be cleared when DAINT's out bits are cleared. for ( uint8_t n = 0; n < DWC2_EP_MAX; n++ ) { - xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_IN); - - if ( dwc2->daint & (1 << (DAINT_IEPINT_Pos + n)) ) + if ( dwc2->daint & TU_BIT(DAINT_IEPINT_Pos + n) ) { // IN XFER complete (entire xfer). + xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_IN); + if ( epin[n].diepint & DIEPINT_XFRC ) { epin[n].diepint = DIEPINT_XFRC; @@ -1215,14 +1266,14 @@ void dcd_int_handler(uint8_t rhport) // OUT endpoint interrupt handling. if(int_status & GINTSTS_OEPINT) { - // OEPINT is read-only + // OEPINT is read-only, clear using DOEPINTn handle_epout_irq(rhport); } // IN endpoint interrupt handling. if(int_status & GINTSTS_IEPINT) { - // IEPINT bit read-only + // IEPINT bit read-only, clear using DIEPINTn handle_epin_irq(rhport); } diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index 583a7274a..6e52ebc7b 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -907,6 +907,17 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define GRXSTSP_PKTSTS_Msk (0xFUL << GRXSTSP_PKTSTS_Pos) // 0x001E0000 */ #define GRXSTSP_PKTSTS GRXSTSP_PKTSTS_Msk // OUT EP interrupt mask bits */ +#define GRXSTS_PKTSTS_GLOBALOUTNAK 1 +#define GRXSTS_PKTSTS_OUTRX 2 +#define GRXSTS_PKTSTS_HCHIN 2 +#define GRXSTS_PKTSTS_OUTDONE 3 +#define GRXSTS_PKTSTS_HCHIN_XFER_COMP 3 +#define GRXSTS_PKTSTS_SETUPDONE 4 +#define GRXSTS_PKTSTS_DATATOGGLEERR 5 +#define GRXSTS_PKTSTS_SETUPRX 6 +#define GRXSTS_PKTSTS_HCHHALTED 7 + + /******************** Bit definition for DAINTMSK register ********************/ #define DAINTMSK_IEPM_Pos (0U) #define DAINTMSK_IEPM_Msk (0xFFFFUL << DAINTMSK_IEPM_Pos) // 0x0000FFFF */ -- cgit v1.3.1 From b80942987346bc3731fb3b40696065be039d59a9 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 2 Nov 2021 14:51:15 +0700 Subject: minor clean up --- src/portable/synopsys/dwc2/dcd_dwc2.c | 40 +++++++++++++++++------------------ 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 83abc635b..9750757aa 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -936,16 +936,16 @@ static void handle_rxflvl_irq(uint8_t rhport) dwc2_epout_t* epout = &dwc2->epout[epnum]; -#if CFG_TUSB_DEBUG >= (DWC2_DEBUG + 1) - const char * pktsts_str[] = - { - "ASSERT", "Global NAK (ISR)", "Out Data Received", "Out Transfer Complete (ISR)", - "Setup Complete (ISR)", "ASSERT", "Setup Data Received" - }; - TU_LOG_LOCATION(); - TU_LOG(DWC2_DEBUG, " EP %02X, Byte Count %u, %s\r\n", epnum, bcnt, pktsts_str[pktsts]); - TU_LOG(DWC2_DEBUG, " daint = %08lX, doepint = %04lX\r\n", dwc2->daint, epout->doepint); -#endif +//#if CFG_TUSB_DEBUG >= DWC2_DEBUG +// const char * pktsts_str[] = +// { +// "ASSERT", "Global NAK (ISR)", "Out Data Received", "Out Transfer Complete (ISR)", +// "Setup Complete (ISR)", "ASSERT", "Setup Data Received" +// }; +// TU_LOG_LOCATION(); +// TU_LOG(DWC2_DEBUG, " EP %02X, Byte Count %u, %s\r\n", epnum, bcnt, pktsts_str[pktsts]); +// TU_LOG(DWC2_DEBUG, " daint = %08lX, doepint = %04X\r\n", (unsigned long) dwc2->daint, (unsigned int) epout->doepint); +//#endif switch ( pktsts ) { @@ -1008,17 +1008,19 @@ static void handle_rxflvl_irq(uint8_t rhport) // - complete the data stage of control write is complete if ((epnum == 0) && (bcnt == 0) && (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a)) { - if (epout->doepint & DOEPINT_STPKTRX) - { - // skip this "no-data" transfer complete event - // STPKTRX will be clear later by setup received handler - epout->doepint = DOEPINT_XFRC; - } + uint32_t doepint = epout->doepint; - if (epout->doepint & DOEPINT_OTEPSPR) + if (doepint & (DOEPINT_STPKTRX | DOEPINT_OTEPSPR)) { // skip this "no-data" transfer complete event - epout->doepint = DOEPINT_XFRC | DOEPINT_OTEPSPR; + // Note: STPKTRX will be clear later by setup received handler + uint32_t clear_flags = DOEPINT_XFRC; + + if (doepint & DOEPINT_OTEPSPR) clear_flags |= DOEPINT_OTEPSPR; + + epout->doepint = clear_flags; + + // TU_LOG(DWC2_DEBUG, " FIX extra transfer complete on setup/data compete\r\n"); } } break; @@ -1163,8 +1165,6 @@ void dcd_int_handler(uint8_t rhport) uint32_t const int_status = dwc2->gintsts & dwc2->gintmsk; -// TU_LOG_HEX(DWC2_DEBUG, int_status); - if(int_status & GINTSTS_USBRST) { // USBRST is start of reset. -- cgit v1.3.1 From 7e688947265075afdaa343e69ec29a2b2cac5f33 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 2 Nov 2021 15:15:54 +0700 Subject: grouping stm32L4 family in bsp --- .../boards/stm32l476_disco/STM32L476VGTx_FLASH.ld | 183 +++++++++ hw/bsp/stm32l4/boards/stm32l476_disco/board.h | 139 +++++++ hw/bsp/stm32l4/boards/stm32l476_disco/board.mk | 10 + .../boards/stm32l4p5_nucleo/STM32L4P5ZGTX_FLASH.ld | 200 ++++++++++ hw/bsp/stm32l4/boards/stm32l4p5_nucleo/board.h | 137 +++++++ hw/bsp/stm32l4/boards/stm32l4p5_nucleo/board.mk | 10 + .../boards/stm32l4r5_nucleo/STM32L4RXxI_FLASH.ld | 167 ++++++++ hw/bsp/stm32l4/boards/stm32l4r5_nucleo/board.h | 137 +++++++ hw/bsp/stm32l4/boards/stm32l4r5_nucleo/board.mk | 14 + hw/bsp/stm32l4/family.c | 198 ++++++++++ hw/bsp/stm32l4/family.mk | 45 +++ hw/bsp/stm32l4/stm32l4xx_hal_conf.h | 420 +++++++++++++++++++++ hw/bsp/stm32l476disco/STM32L476VGTx_FLASH.ld | 183 --------- hw/bsp/stm32l476disco/board.mk | 56 --- hw/bsp/stm32l476disco/stm32l476disco.c | 246 ------------ hw/bsp/stm32l476disco/stm32l4xx_hal_conf.h | 420 --------------------- hw/bsp/stm32l4r5nucleo/STM32L4RXxI_FLASH.ld | 167 -------- hw/bsp/stm32l4r5nucleo/board.mk | 50 --- hw/bsp/stm32l4r5nucleo/stm32l4r5nucleo.c | 287 -------------- hw/bsp/stm32l4r5nucleo/stm32l4xx_hal_conf.h | 419 -------------------- src/portable/synopsys/dwc2/dcd_dwc2.c | 2 +- 21 files changed, 1661 insertions(+), 1829 deletions(-) create mode 100644 hw/bsp/stm32l4/boards/stm32l476_disco/STM32L476VGTx_FLASH.ld create mode 100644 hw/bsp/stm32l4/boards/stm32l476_disco/board.h create mode 100644 hw/bsp/stm32l4/boards/stm32l476_disco/board.mk create mode 100644 hw/bsp/stm32l4/boards/stm32l4p5_nucleo/STM32L4P5ZGTX_FLASH.ld create mode 100644 hw/bsp/stm32l4/boards/stm32l4p5_nucleo/board.h create mode 100644 hw/bsp/stm32l4/boards/stm32l4p5_nucleo/board.mk create mode 100644 hw/bsp/stm32l4/boards/stm32l4r5_nucleo/STM32L4RXxI_FLASH.ld create mode 100644 hw/bsp/stm32l4/boards/stm32l4r5_nucleo/board.h create mode 100644 hw/bsp/stm32l4/boards/stm32l4r5_nucleo/board.mk create mode 100644 hw/bsp/stm32l4/family.c create mode 100644 hw/bsp/stm32l4/family.mk create mode 100644 hw/bsp/stm32l4/stm32l4xx_hal_conf.h delete mode 100644 hw/bsp/stm32l476disco/STM32L476VGTx_FLASH.ld delete mode 100644 hw/bsp/stm32l476disco/board.mk delete mode 100644 hw/bsp/stm32l476disco/stm32l476disco.c delete mode 100644 hw/bsp/stm32l476disco/stm32l4xx_hal_conf.h delete mode 100644 hw/bsp/stm32l4r5nucleo/STM32L4RXxI_FLASH.ld delete mode 100644 hw/bsp/stm32l4r5nucleo/board.mk delete mode 100644 hw/bsp/stm32l4r5nucleo/stm32l4r5nucleo.c delete mode 100644 hw/bsp/stm32l4r5nucleo/stm32l4xx_hal_conf.h diff --git a/hw/bsp/stm32l4/boards/stm32l476_disco/STM32L476VGTx_FLASH.ld b/hw/bsp/stm32l4/boards/stm32l476_disco/STM32L476VGTx_FLASH.ld new file mode 100644 index 000000000..98f468ac0 --- /dev/null +++ b/hw/bsp/stm32l4/boards/stm32l476_disco/STM32L476VGTx_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : LinkerScript.ld +** +** Abstract : Linker script for STM32L476VGTx Device with +** 1024KByte FLASH, 96KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +** (c)Copyright Ac6. +** You may use this file as-is or modify it according to the needs of your +** project. Distribution of this file (unmodified or modified) is not +** permitted. Ac6 permit registered System Workbench for MCU users the +** rights to distribute the assembled, compiled & linked contents of this +** file as part of an application binary file, provided that it is built +** using the System Workbench for MCU toolchain. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20018000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x500; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 1024K +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 96K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(8); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(8); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(8); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(8); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(8); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(8); + } >FLASH + + .ARM.extab : + { + . = ALIGN(8); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(8); + } >FLASH + .ARM : { + . = ALIGN(8); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(8); + } >FLASH + + .preinit_array : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(8); + } >FLASH + + .init_array : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(8); + } >FLASH + .fini_array : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(8); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(8); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(8); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/hw/bsp/stm32l4/boards/stm32l476_disco/board.h b/hw/bsp/stm32l4/boards/stm32l476_disco/board.h new file mode 100644 index 000000000..42c657d5e --- /dev/null +++ b/hw/bsp/stm32l4/boards/stm32l476_disco/board.h @@ -0,0 +1,139 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#define LED_PORT GPIOB +#define LED_PIN GPIO_PIN_2 +#define LED_STATE_ON 1 + +#define BUTTON_PORT GPIOA +#define BUTTON_PIN GPIO_PIN_0 +#define BUTTON_STATE_ACTIVE 1 + +#define UART_DEV USART2 +#define UART_CLK_EN __HAL_RCC_USART2_CLK_ENABLE +#define UART_GPIO_PORT GPIOD +#define UART_GPIO_AF GPIO_AF7_USART2 +#define UART_TX_PIN GPIO_PIN_5 +#define UART_RX_PIN GPIO_PIN_6 + +//--------------------------------------------------------------------+ +// RCC Clock +//--------------------------------------------------------------------+ + +/** + * @brief System Clock Configuration + * The system Clock is configured as follow : + * + * If define USB_USE_LSE_MSI_CLOCK enabled: + * System Clock source = PLL (MSI) + * SYSCLK(Hz) = 80000000 + * HCLK(Hz) = 80000000 + * AHB Prescaler = 1 + * APB1 Prescaler = 1 + * APB2 Prescaler = 2 + * MSI Frequency(Hz) = 4800000 + * LSE Frequency(Hz) = 32768 + * PLL_M = 6 + * PLL_N = 40 + * PLL_P = 7 + * PLL_Q = 4 + * PLL_R = 4 + * Flash Latency(WS) = 4 + * @param None + * @retval None + */ +static inline void board_clock_init(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; + + /* Enable the LSE Oscillator */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + /* Enable the CSS interrupt in case LSE signal is corrupted or not present */ + HAL_RCCEx_DisableLSECSS(); + + /* Set tick interrupt priority, default HAL value is intentionally invalid + and that prevents PLL initialization in HAL_RCC_OscConfig() */ + HAL_InitTick((1UL << __NVIC_PRIO_BITS) - 1UL); + + /* Enable MSI Oscillator and activate PLL with MSI as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.MSIState = RCC_MSI_ON; + RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; + RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; + RCC_OscInitStruct.PLL.PLLM = 6; + RCC_OscInitStruct.PLL.PLLN = 40; + RCC_OscInitStruct.PLL.PLLP = 7; + RCC_OscInitStruct.PLL.PLLQ = 4; + RCC_OscInitStruct.PLL.PLLR = 4; + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + /* Enable MSI Auto-calibration through LSE */ + HAL_RCCEx_EnableMSIPLLMode(); + + /* Select MSI output as USB clock source */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 + clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4); +} + +static inline void board_vbus_sense_init(void) +{ + // L476Disco use general GPIO PC11 for VBUS sensing instead of dedicated PA9 as others + // Disable VBUS Sense and force device mode + USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN; + + USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN | USB_OTG_GOTGCTL_BVALOVAL; +} + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/stm32l4/boards/stm32l476_disco/board.mk b/hw/bsp/stm32l4/boards/stm32l476_disco/board.mk new file mode 100644 index 000000000..e7b8557a5 --- /dev/null +++ b/hw/bsp/stm32l4/boards/stm32l476_disco/board.mk @@ -0,0 +1,10 @@ +CFLAGS += \ + -DSTM32L476xx \ + +# All source paths should be relative to the top level. +LD_FILE = $(BOARD_PATH)/STM32L476VGTx_FLASH.ld + +SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l476xx.s + +# For flash-jlink target +JLINK_DEVICE = stm32l476vg diff --git a/hw/bsp/stm32l4/boards/stm32l4p5_nucleo/STM32L4P5ZGTX_FLASH.ld b/hw/bsp/stm32l4/boards/stm32l4p5_nucleo/STM32L4P5ZGTX_FLASH.ld new file mode 100644 index 000000000..c1a490a70 --- /dev/null +++ b/hw/bsp/stm32l4/boards/stm32l4p5_nucleo/STM32L4P5ZGTX_FLASH.ld @@ -0,0 +1,200 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld +** +** Author : Auto-generated by STM32CubeIDE +** +** Abstract : Linker script for STM32L4P5ZGTx Device from STM32L4PLUS series +** 1024Kbytes ROM +** 320Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is without any warranty +** of any kind. +** +***************************************************************************** +** @attention +** +**

© COPYRIGHT(c) 2019 STMicroelectronics

+** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** 1. Redistributions of source code must retain the above copyright notice, +** this list of conditions and the following disclaimer. +** 2. Redistributions in binary form must reproduce the above copyright notice, +** this list of conditions and the following disclaimer in the documentation +** and/or other materials provided with the distribution. +** 3. Neither the name of STMicroelectronics nor the names of its contributors +** may be used to endorse or promote products derived from this software +** without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + 0x0001FFFF; /* end of "SRAM1" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 320K + ROM (rx) : ORIGIN = 0x08000000, LENGTH = 1024K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "ROM" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >ROM + + /* The program code and other data into "ROM" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >ROM + + /* Constant data into "ROM" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >ROM + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >ROM + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >ROM + + .preinit_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >ROM + + .init_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >ROM + + .fini_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >ROM + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> ROM + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/hw/bsp/stm32l4/boards/stm32l4p5_nucleo/board.h b/hw/bsp/stm32l4/boards/stm32l4p5_nucleo/board.h new file mode 100644 index 000000000..1df389aed --- /dev/null +++ b/hw/bsp/stm32l4/boards/stm32l4p5_nucleo/board.h @@ -0,0 +1,137 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#define LED_PORT GPIOB +#define LED_PIN GPIO_PIN_14 +#define LED_STATE_ON 1 + +#define BUTTON_PORT GPIOC +#define BUTTON_PIN GPIO_PIN_13 +#define BUTTON_STATE_ACTIVE 1 + +#define UART_DEV LPUART1 +#define UART_CLK_EN __HAL_RCC_LPUART1_CLK_ENABLE +#define UART_GPIO_PORT GPIOG +#define UART_GPIO_AF GPIO_AF8_LPUART1 +#define UART_TX_PIN GPIO_PIN_7 +#define UART_RX_PIN GPIO_PIN_8 + +//--------------------------------------------------------------------+ +// RCC Clock +//--------------------------------------------------------------------+ + +/** + * @brief System Clock Configuration + * The system Clock is configured as follow : + * System Clock source = PLL (MSI) + * SYSCLK(Hz) = 120000000 + * HCLK(Hz) = 120000000 + * AHB Prescaler = 1 + * APB1 Prescaler = 1 + * APB2 Prescaler = 1 + * MSI Frequency(Hz) = 48000000 + * PLL_M = 12 + * PLL_N = 60 + * PLL_P = 2 + * PLL_Q = 2 + * VDD(V) = 3.3 + * Main regulator output voltage = Scale1 mode + * Flash Latency(WS) = 5 + * The USB clock configuration from PLLSAI: + * PLLSAIP = 8 FIXME + * PLLSAIN = 384 FIXME + * PLLSAIQ = 7 FIXME + * @param None + * @retval None + */ + +static inline void board_clock_init(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + /* Activate PLL with MSI , stabilizied via PLL by LSE */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.MSIState = RCC_MSI_ON; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; + RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; + RCC_OscInitStruct.PLL.PLLM = 12; + RCC_OscInitStruct.PLL.PLLN = 60; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 2; + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + /* Enable MSI Auto-calibration through LSE */ + HAL_RCCEx_EnableMSIPLLMode(); + + /* Select MSI output as USB clock source */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + + /* Select MSI output as USB clock source */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1; + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 + clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + // Avoid overshoot and start with HCLK 60 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV2; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3); + + /* AHB prescaler divider at 1 as second step */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5); +} + +static inline void board_vbus_sense_init(void) +{ + // Enable VBUS sense (B device) via pin PA9 + USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN; +} + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/stm32l4/boards/stm32l4p5_nucleo/board.mk b/hw/bsp/stm32l4/boards/stm32l4p5_nucleo/board.mk new file mode 100644 index 000000000..8252dd838 --- /dev/null +++ b/hw/bsp/stm32l4/boards/stm32l4p5_nucleo/board.mk @@ -0,0 +1,10 @@ +CFLAGS += \ + -DSTM32L4P5xx \ + +# All source paths should be relative to the top level. +LD_FILE = $(BOARD_PATH)/STM32L4P5ZGTX_FLASH.ld + +SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l4p5xx.s + +# For flash-jlink target +JLINK_DEVICE = stm32l4p5zg diff --git a/hw/bsp/stm32l4/boards/stm32l4r5_nucleo/STM32L4RXxI_FLASH.ld b/hw/bsp/stm32l4/boards/stm32l4r5_nucleo/STM32L4RXxI_FLASH.ld new file mode 100644 index 000000000..f93a16041 --- /dev/null +++ b/hw/bsp/stm32l4/boards/stm32l4r5_nucleo/STM32L4RXxI_FLASH.ld @@ -0,0 +1,167 @@ +/* +***************************************************************************** +** + +** File : LinkerScript.ld +** +** Abstract : Linker script for STM32L4RxI Device with +** 2048KByte FLASH, 640KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +** (c)Copyright Ac6. +** You may use this file as-is or modify it according to the needs of your +** project. Distribution of this file (unmodified or modified) is not +** permitted. Ac6 permit registered System Workbench for MCU users the +** rights to distribute the assembled, compiled & linked contents of this +** file as part of an application binary file, provided that it is built +** using the System Workbench for MCU toolchain. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x200a0000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x460; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 640K +FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 2048K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/hw/bsp/stm32l4/boards/stm32l4r5_nucleo/board.h b/hw/bsp/stm32l4/boards/stm32l4r5_nucleo/board.h new file mode 100644 index 000000000..1df389aed --- /dev/null +++ b/hw/bsp/stm32l4/boards/stm32l4r5_nucleo/board.h @@ -0,0 +1,137 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#define LED_PORT GPIOB +#define LED_PIN GPIO_PIN_14 +#define LED_STATE_ON 1 + +#define BUTTON_PORT GPIOC +#define BUTTON_PIN GPIO_PIN_13 +#define BUTTON_STATE_ACTIVE 1 + +#define UART_DEV LPUART1 +#define UART_CLK_EN __HAL_RCC_LPUART1_CLK_ENABLE +#define UART_GPIO_PORT GPIOG +#define UART_GPIO_AF GPIO_AF8_LPUART1 +#define UART_TX_PIN GPIO_PIN_7 +#define UART_RX_PIN GPIO_PIN_8 + +//--------------------------------------------------------------------+ +// RCC Clock +//--------------------------------------------------------------------+ + +/** + * @brief System Clock Configuration + * The system Clock is configured as follow : + * System Clock source = PLL (MSI) + * SYSCLK(Hz) = 120000000 + * HCLK(Hz) = 120000000 + * AHB Prescaler = 1 + * APB1 Prescaler = 1 + * APB2 Prescaler = 1 + * MSI Frequency(Hz) = 48000000 + * PLL_M = 12 + * PLL_N = 60 + * PLL_P = 2 + * PLL_Q = 2 + * VDD(V) = 3.3 + * Main regulator output voltage = Scale1 mode + * Flash Latency(WS) = 5 + * The USB clock configuration from PLLSAI: + * PLLSAIP = 8 FIXME + * PLLSAIN = 384 FIXME + * PLLSAIQ = 7 FIXME + * @param None + * @retval None + */ + +static inline void board_clock_init(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + /* Activate PLL with MSI , stabilizied via PLL by LSE */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.MSIState = RCC_MSI_ON; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; + RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; + RCC_OscInitStruct.PLL.PLLM = 12; + RCC_OscInitStruct.PLL.PLLN = 60; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 2; + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + /* Enable MSI Auto-calibration through LSE */ + HAL_RCCEx_EnableMSIPLLMode(); + + /* Select MSI output as USB clock source */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + + /* Select MSI output as USB clock source */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1; + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 + clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + // Avoid overshoot and start with HCLK 60 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV2; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3); + + /* AHB prescaler divider at 1 as second step */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5); +} + +static inline void board_vbus_sense_init(void) +{ + // Enable VBUS sense (B device) via pin PA9 + USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN; +} + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/stm32l4/boards/stm32l4r5_nucleo/board.mk b/hw/bsp/stm32l4/boards/stm32l4r5_nucleo/board.mk new file mode 100644 index 000000000..3d7fa227b --- /dev/null +++ b/hw/bsp/stm32l4/boards/stm32l4r5_nucleo/board.mk @@ -0,0 +1,14 @@ +CFLAGS += \ + -DHSE_VALUE=8000000 \ + -DSTM32L4R5xx \ + +# All source paths should be relative to the top level. +LD_FILE = $(BOARD_PATH)/STM32L4RXxI_FLASH.ld + +SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l4r5xx.s + +# For flash-jlink target +JLINK_DEVICE = stm32l4r5zi + +# flash target using on-board stlink +flash: flash-stlink diff --git a/hw/bsp/stm32l4/family.c b/hw/bsp/stm32l4/family.c new file mode 100644 index 000000000..c15be98e5 --- /dev/null +++ b/hw/bsp/stm32l4/family.c @@ -0,0 +1,198 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 William D. Jones (thor0505@comcast.net), + * Ha Thach (tinyusb.org) + * Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "stm32l4xx_hal.h" +#include "bsp/board.h" +#include "board.h" + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void OTG_FS_IRQHandler(void) +{ + tud_int_handler(0); +} + +//--------------------------------------------------------------------+ +// MACRO TYPEDEF CONSTANT ENUM +//--------------------------------------------------------------------+ + +UART_HandleTypeDef UartHandle; + +void board_init(void) +{ + board_clock_init(); + + // Enable All GPIOs clocks + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOF_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + UART_CLK_EN(); + +#if CFG_TUSB_OS == OPT_OS_NONE + // 1ms tick timer + SysTick_Config(SystemCoreClock / 1000); +#elif CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + //NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); +#endif + + /* Enable USB power on Pwrctrl CR2 register */ + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + +#if defined(PWR_CR5_R1MODE) + /* Enable voltage range 1 boost mode for frequency above 80 Mhz */ + HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST); +#endif + + /* Enable USB power on Pwrctrl CR2 register */ + HAL_PWREx_EnableVddUSB(); + + GPIO_InitTypeDef GPIO_InitStruct; + + // LED + GPIO_InitStruct.Pin = LED_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct); + + // Button + GPIO_InitStruct.Pin = BUTTON_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct); + + // IOSV bit MUST be set to access GPIO port G[2:15] */ + __HAL_RCC_PWR_CLK_ENABLE(); + HAL_PWREx_EnableVddIO2(); + + // Uart + GPIO_InitStruct.Pin = UART_TX_PIN | UART_RX_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Alternate = UART_GPIO_AF; + HAL_GPIO_Init(UART_GPIO_PORT, &GPIO_InitStruct); + + UartHandle.Instance = UART_DEV; + UartHandle.Init.BaudRate = CFG_BOARD_UART_BAUDRATE; + UartHandle.Init.WordLength = UART_WORDLENGTH_8B; + UartHandle.Init.StopBits = UART_STOPBITS_1; + UartHandle.Init.Parity = UART_PARITY_NONE; + UartHandle.Init.HwFlowCtl = UART_HWCONTROL_NONE; + UartHandle.Init.Mode = UART_MODE_TX_RX; + UartHandle.Init.OverSampling = UART_OVERSAMPLING_16; + UartHandle.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + //UartHandle.Init.ClockPrescaler = UART_PRESCALER_DIV1; + UartHandle.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + + HAL_UART_Init(&UartHandle); + + /* Configure USB FS GPIOs */ + /* Configure DM DP Pins */ + GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12); + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* Configure VBUS Pin */ + GPIO_InitStruct.Pin = GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* Configure ID pin */ + GPIO_InitStruct.Pin = GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* Enable USB FS Clocks */ + __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); + + board_vbus_sense_init(); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +void board_led_write(bool state) +{ + HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON)); +} + +uint32_t board_button_read(void) +{ + return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN); +} + +int board_uart_read(uint8_t* buf, int len) +{ + (void) buf; (void) len; + return 0; +} + +int board_uart_write(void const * buf, int len) +{ + HAL_UART_Transmit(&UartHandle, (uint8_t*)(uintptr_t) buf, len, 0xffff); + return len; +} + +#if CFG_TUSB_OS == OPT_OS_NONE +volatile uint32_t system_ticks = 0; +void SysTick_Handler (void) +{ + system_ticks++; +} + +uint32_t board_millis(void) +{ + return system_ticks; +} +#endif + +void HardFault_Handler (void) +{ + asm("bkpt"); +} + +// Required by __libc_init_array in startup code if we are compiling using +// -nostdlib/-nostartfiles. +void _init(void) +{ + +} diff --git a/hw/bsp/stm32l4/family.mk b/hw/bsp/stm32l4/family.mk new file mode 100644 index 000000000..d6f55e5f9 --- /dev/null +++ b/hw/bsp/stm32l4/family.mk @@ -0,0 +1,45 @@ +ST_FAMILY = l4 +DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver + +ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY) +ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver + +include $(TOP)/$(BOARD_PATH)/board.mk + +CFLAGS += \ + -flto \ + -mthumb \ + -mabi=aapcs \ + -mcpu=cortex-m4 \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -nostdlib -nostartfiles \ + -DCFG_TUSB_MCU=OPT_MCU_STM32L4 + +# suppress warning caused by vendor mcu driver +CFLAGS += -Wno-error=maybe-uninitialized -Wno-error=cast-align + +#src/portable/st/synopsys/dcd_synopsys.c +SRC_C += \ + src/portable/synopsys/dwc2/dcd_dwc2.c \ + $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \ + $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \ + $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \ + $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \ + $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \ + $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr.c \ + $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr_ex.c \ + $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \ + $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c + +INC += \ + $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ + $(TOP)/$(ST_CMSIS)/Include \ + $(TOP)/$(ST_HAL_DRIVER)/Inc \ + $(TOP)/$(BOARD_PATH) + +# For freeRTOS port source +FREERTOS_PORT = ARM_CM4F + +# flash target using on-board stlink +flash: flash-stlink diff --git a/hw/bsp/stm32l4/stm32l4xx_hal_conf.h b/hw/bsp/stm32l4/stm32l4xx_hal_conf.h new file mode 100644 index 000000000..312f86da1 --- /dev/null +++ b/hw/bsp/stm32l4/stm32l4xx_hal_conf.h @@ -0,0 +1,420 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_conf.h + * @author MCD Application Team + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32l4xx_hal_conf.h. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L4xx_HAL_CONF_H +#define __STM32L4xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +/* #define HAL_ADC_MODULE_ENABLED */ +/* #define HAL_CAN_MODULE_ENABLED */ +/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ +/* #define HAL_COMP_MODULE_ENABLED */ +#define HAL_CORTEX_MODULE_ENABLED +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_DAC_MODULE_ENABLED */ +/* #define HAL_DFSDM_MODULE_ENABLED */ +#define HAL_DMA_MODULE_ENABLED +/* #define HAL_FIREWALL_MODULE_ENABLED */ +#define HAL_FLASH_MODULE_ENABLED +/* #define HAL_NAND_MODULE_ENABLED */ +// #define HAL_NOR_MODULE_ENABLED +// #define HAL_SRAM_MODULE_ENABLED +/* #define HAL_HCD_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +//#define HAL_I2C_MODULE_ENABLED +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +//#define HAL_LCD_MODULE_ENABLED +/* #define HAL_LPTIM_MODULE_ENABLED */ +/* #define HAL_OPAMP_MODULE_ENABLED */ +//#define HAL_PCD_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +/* #define HAL_QSPI_MODULE_ENABLED */ +#define HAL_RCC_MODULE_ENABLED +/* #define HAL_RNG_MODULE_ENABLED */ +/* #define HAL_RTC_MODULE_ENABLED */ +//#define HAL_SAI_MODULE_ENABLED +//#define HAL_SD_MODULE_ENABLED +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_SMBUS_MODULE_ENABLED */ +/* #define HAL_SPI_MODULE_ENABLED */ +/* #define HAL_SWPMI_MODULE_ENABLED */ +/* #define HAL_TIM_MODULE_ENABLED */ +/* #define HAL_TSC_MODULE_ENABLED */ +#define HAL_UART_MODULE_ENABLED +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ + + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal Multiple Speed oscillator (MSI) default value. + * This value is the default MSI range value after Reset. + */ +#if !defined (MSI_VALUE) + #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/ +#endif /* MSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG. + * This internal oscillator is mainly dedicated to provide a high precision clock to + * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. + * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency + * which is subject to manufacturing process variations. + */ +#if !defined (HSI48_VALUE) + #define HSI48_VALUE 48000000U /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. + The real value my vary depending on manufacturing process variations.*/ +#endif /* HSI48_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE 32768U /*!< Value of the External oscillator in Hz*/ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for SAI1 peripheral + * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source + * frequency. + */ +#if !defined (EXTERNAL_SAI1_CLOCK_VALUE) + #define EXTERNAL_SAI1_CLOCK_VALUE 48000U /*!< Value of the SAI1 External clock source in Hz*/ +#endif /* EXTERNAL_SAI1_CLOCK_VALUE */ + +/** + * @brief External clock source for SAI2 peripheral + * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source + * frequency. + */ +#if !defined (EXTERNAL_SAI2_CLOCK_VALUE) + #define EXTERNAL_SAI2_CLOCK_VALUE 48000U /*!< Value of the SAI2 External clock source in Hz*/ +#endif /* EXTERNAL_SAI2_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE 3300U /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY 0U /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 0U +#define INSTRUCTION_CACHE_ENABLE 1U +#define DATA_CACHE_ENABLE 1U + + +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ +#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */ +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ +#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ +#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ +#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ +#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ +#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ +#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */ +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ +#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ +#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U /* HRTIM register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ +#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U /* JPEG register callback disabled */ +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ +#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ +#define USE_HAL_MDIOS_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */ +#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */ +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ +#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_SWPMI_REGISTER_CALLBACKS 0U /* SWPMI register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver + * Activated: CRC code is present inside driver + * Deactivated: CRC code cleaned from driver + */ + +#define USE_SPI_CRC 1U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32l4xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32l4xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32l4xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32l4xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32l4xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32l4xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32l4xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #include "Legacy/stm32l4xx_hal_can_legacy.h" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + +#ifdef HAL_COMP_MODULE_ENABLED + #include "stm32l4xx_hal_comp.h" +#endif /* HAL_COMP_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32l4xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32l4xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32l4xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_FIREWALL_MODULE_ENABLED + #include "stm32l4xx_hal_firewall.h" +#endif /* HAL_FIREWALL_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32l4xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32l4xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32l4xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32l4xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32l4xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32l4xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LCD_MODULE_ENABLED + #include "stm32l4xx_hal_lcd.h" +#endif /* HAL_LCD_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED +#include "stm32l4xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_OPAMP_MODULE_ENABLED +#include "stm32l4xx_hal_opamp.h" +#endif /* HAL_OPAMP_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32l4xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32l4xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32l4xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32l4xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32l4xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32l4xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32l4xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32l4xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_SWPMI_MODULE_ENABLED + #include "stm32l4xx_hal_swpmi.h" +#endif /* HAL_SWPMI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32l4xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_TSC_MODULE_ENABLED + #include "stm32l4xx_hal_tsc.h" +#endif /* HAL_TSC_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32l4xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32l4xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32l4xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32l4xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32l4xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32l4xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32l4xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t *file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L4xx_HAL_CONF_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hw/bsp/stm32l476disco/STM32L476VGTx_FLASH.ld b/hw/bsp/stm32l476disco/STM32L476VGTx_FLASH.ld deleted file mode 100644 index 98f468ac0..000000000 --- a/hw/bsp/stm32l476disco/STM32L476VGTx_FLASH.ld +++ /dev/null @@ -1,183 +0,0 @@ -/* -***************************************************************************** -** - -** File : LinkerScript.ld -** -** Abstract : Linker script for STM32L476VGTx Device with -** 1024KByte FLASH, 96KByte RAM -** -** Set heap size, stack size and stack location according -** to application requirements. -** -** Set memory bank area and size if external memory is used. -** -** Target : STMicroelectronics STM32 -** -** -** Distribution: The file is distributed as is, without any warranty -** of any kind. -** -** (c)Copyright Ac6. -** You may use this file as-is or modify it according to the needs of your -** project. Distribution of this file (unmodified or modified) is not -** permitted. Ac6 permit registered System Workbench for MCU users the -** rights to distribute the assembled, compiled & linked contents of this -** file as part of an application binary file, provided that it is built -** using the System Workbench for MCU toolchain. -** -***************************************************************************** -*/ - -/* Entry Point */ -ENTRY(Reset_Handler) - -/* Highest address of the user mode stack */ -_estack = 0x20018000; /* end of RAM */ -/* Generate a link error if heap and stack don't fit into RAM */ -_Min_Heap_Size = 0x500; /* required amount of heap */ -_Min_Stack_Size = 0x1000; /* required amount of stack */ - -/* Specify the memory areas */ -MEMORY -{ -FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 1024K -RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 96K -} - -/* Define output sections */ -SECTIONS -{ - /* The startup code goes first into FLASH */ - .isr_vector : - { - . = ALIGN(8); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(8); - } >FLASH - - /* The program code and other data goes into FLASH */ - .text : - { - . = ALIGN(8); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - - KEEP (*(.init)) - KEEP (*(.fini)) - - . = ALIGN(8); - _etext = .; /* define a global symbols at end of code */ - } >FLASH - - /* Constant data goes into FLASH */ - .rodata : - { - . = ALIGN(8); - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - . = ALIGN(8); - } >FLASH - - .ARM.extab : - { - . = ALIGN(8); - *(.ARM.extab* .gnu.linkonce.armextab.*) - . = ALIGN(8); - } >FLASH - .ARM : { - . = ALIGN(8); - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - . = ALIGN(8); - } >FLASH - - .preinit_array : - { - . = ALIGN(8); - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - . = ALIGN(8); - } >FLASH - - .init_array : - { - . = ALIGN(8); - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - . = ALIGN(8); - } >FLASH - .fini_array : - { - . = ALIGN(8); - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - . = ALIGN(8); - } >FLASH - - /* used by the startup to initialize data */ - _sidata = LOADADDR(.data); - - /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : - { - . = ALIGN(8); - _sdata = .; /* create a global symbol at data start */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - - . = ALIGN(8); - _edata = .; /* define a global symbol at data end */ - } >RAM AT> FLASH - - - /* Uninitialized data section */ - . = ALIGN(4); - .bss : - { - /* This is used by the startup in order to initialize the .bss secion */ - _sbss = .; /* define a global symbol at bss start */ - __bss_start__ = _sbss; - *(.bss) - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end */ - __bss_end__ = _ebss; - } >RAM - - /* User_heap_stack section, used to check that there is enough RAM left */ - ._user_heap_stack : - { - . = ALIGN(8); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - . = . + _Min_Heap_Size; - . = . + _Min_Stack_Size; - . = ALIGN(8); - } >RAM - - - - /* Remove information from the standard libraries */ - /DISCARD/ : - { - libc.a ( * ) - libm.a ( * ) - libgcc.a ( * ) - } - - .ARM.attributes 0 : { *(.ARM.attributes) } -} - - diff --git a/hw/bsp/stm32l476disco/board.mk b/hw/bsp/stm32l476disco/board.mk deleted file mode 100644 index 8d9e267cf..000000000 --- a/hw/bsp/stm32l476disco/board.mk +++ /dev/null @@ -1,56 +0,0 @@ -ST_FAMILY = l4 -DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver - -ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY) -ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver - -CFLAGS += \ - -flto \ - -mthumb \ - -mabi=aapcs \ - -mcpu=cortex-m4 \ - -mfloat-abi=hard \ - -mfpu=fpv4-sp-d16 \ - -nostdlib -nostartfiles \ - -DSTM32L476xx \ - -DCFG_TUSB_MCU=OPT_MCU_STM32L4 - -# suppress warning caused by vendor mcu driver -CFLAGS += -Wno-error=maybe-uninitialized -Wno-error=cast-align - -# All source paths should be relative to the top level. -LD_FILE = hw/bsp/$(BOARD)/STM32L476VGTx_FLASH.ld - -#src/portable/st/synopsys/dcd_synopsys.c -SRC_C += \ - src/portable/synopsys/dwc2/dcd_dwc2.c \ - $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \ - $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \ - $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \ - $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \ - $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \ - $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr.c \ - $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr_ex.c \ - $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \ - $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c - -SRC_S += \ - $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l476xx.s - -INC += \ - $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ - $(TOP)/$(ST_CMSIS)/Include \ - $(TOP)/$(ST_HAL_DRIVER)/Inc \ - $(TOP)/hw/bsp/$(BOARD) - -# For freeRTOS port source -FREERTOS_PORT = ARM_CM4F - -# For flash-jlink target -JLINK_DEVICE = stm32l476vg - -# Path to STM32 Cube Programmer CLI, should be added into system path -STM32Prog = STM32_Programmer_CLI - -# flash target using on-board stlink -flash: flash-stlink diff --git a/hw/bsp/stm32l476disco/stm32l476disco.c b/hw/bsp/stm32l476disco/stm32l476disco.c deleted file mode 100644 index bc1b6c929..000000000 --- a/hw/bsp/stm32l476disco/stm32l476disco.c +++ /dev/null @@ -1,246 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2019 Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#include "../board.h" - -#include "stm32l4xx_hal.h" - -//--------------------------------------------------------------------+ -// Forward USB interrupt events to TinyUSB IRQ Handler -//--------------------------------------------------------------------+ -void OTG_FS_IRQHandler(void) -{ - tud_int_handler(0); -} - -//--------------------------------------------------------------------+ -// MACRO TYPEDEF CONSTANT ENUM -//--------------------------------------------------------------------+ - -#define LED_PORT GPIOB -#define LED_PIN GPIO_PIN_2 -#define LED_STATE_ON 1 - -#define BUTTON_PORT GPIOA -#define BUTTON_PIN GPIO_PIN_0 -#define BUTTON_STATE_ACTIVE 1 - - -// enable all LED, Button, Uart, USB clock -static void all_rcc_clk_enable(void) -{ - __HAL_RCC_GPIOA_CLK_ENABLE(); // USB D+, D-, Button - __HAL_RCC_GPIOB_CLK_ENABLE(); // LED - __HAL_RCC_GPIOC_CLK_ENABLE(); // VBUS pin -} - - -/** - * @brief System Clock Configuration - * The system Clock is configured as follow : - * - * If define USB_USE_LSE_MSI_CLOCK enabled: - * System Clock source = PLL (MSI) - * SYSCLK(Hz) = 80000000 - * HCLK(Hz) = 80000000 - * AHB Prescaler = 1 - * APB1 Prescaler = 1 - * APB2 Prescaler = 2 - * MSI Frequency(Hz) = 4800000 - * LSE Frequency(Hz) = 32768 - * PLL_M = 6 - * PLL_N = 40 - * PLL_P = 7 - * PLL_Q = 4 - * PLL_R = 4 - * Flash Latency(WS) = 4 - * @param None - * @retval None - */ -static void SystemClock_Config(void) -{ - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; - - /* Enable the LSE Oscillator */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.LSEState = RCC_LSE_ON; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; - HAL_RCC_OscConfig(&RCC_OscInitStruct); - - /* Enable the CSS interrupt in case LSE signal is corrupted or not present */ - HAL_RCCEx_DisableLSECSS(); - - /* Set tick interrupt priority, default HAL value is intentionally invalid - and that prevents PLL initialization in HAL_RCC_OscConfig() */ - HAL_InitTick((1UL << __NVIC_PRIO_BITS) - 1UL); - - /* Enable MSI Oscillator and activate PLL with MSI as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; - RCC_OscInitStruct.MSIState = RCC_MSI_ON; - RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; - RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; - RCC_OscInitStruct.PLL.PLLM = 6; - RCC_OscInitStruct.PLL.PLLN = 40; - RCC_OscInitStruct.PLL.PLLP = 7; - RCC_OscInitStruct.PLL.PLLQ = 4; - RCC_OscInitStruct.PLL.PLLR = 4; - HAL_RCC_OscConfig(&RCC_OscInitStruct); - - /* Enable MSI Auto-calibration through LSE */ - HAL_RCCEx_EnableMSIPLLMode(); - - /* Select MSI output as USB clock source */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; - PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; - HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 - clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; - HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4); -} - -void board_init(void) -{ - SystemClock_Config(); - all_rcc_clk_enable(); - -#if CFG_TUSB_OS == OPT_OS_NONE - // 1ms tick timer - SysTick_Config(SystemCoreClock / 1000); -#elif CFG_TUSB_OS == OPT_OS_FREERTOS - // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) - //NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); -#endif - - /* Enable Power Clock*/ - __HAL_RCC_PWR_CLK_ENABLE(); - - /* Enable USB power on Pwrctrl CR2 register */ - HAL_PWREx_EnableVddUSB(); - - GPIO_InitTypeDef GPIO_InitStruct; - - // LED - GPIO_InitStruct.Pin = LED_PIN; - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - GPIO_InitStruct.Pull = GPIO_PULLUP; - GPIO_InitStruct.Speed = GPIO_SPEED_FAST; - HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct); - - board_led_write(false); - - // Button - GPIO_InitStruct.Pin = BUTTON_PIN; - GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_PULLDOWN; - GPIO_InitStruct.Speed = GPIO_SPEED_FAST; - HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct); - - // USB - /* Configure DM DP Pins */ - GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12); - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /* Configure VBUS Pin */ - GPIO_InitStruct.Pin = GPIO_PIN_11; - GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /* Enable USB FS Clock */ - __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); - -// // Enable VBUS sense (B device) via pin PA9 -// USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN; - - // L476Disco use general GPIO PC11 for VBUS sensing instead of dedicated PA9 as others - // Disable VBUS Sense and force device mode - USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN; -} - -//--------------------------------------------------------------------+ -// board porting API -//--------------------------------------------------------------------+ - -void board_led_write(bool state) -{ - HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON)); -} - -uint32_t board_button_read(void) -{ - return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN); -} - -int board_uart_read(uint8_t* buf, int len) -{ - (void) buf; (void) len; - return 0; -} - -int board_uart_write(void const * buf, int len) -{ - (void) buf; (void) len; - return 0; -} - -#if CFG_TUSB_OS == OPT_OS_NONE -volatile uint32_t system_ticks = 0; -void SysTick_Handler (void) -{ - system_ticks++; -} - -uint32_t board_millis(void) -{ - return system_ticks; -} -#endif - -void HardFault_Handler (void) -{ - asm("bkpt"); -} - -// Required by __libc_init_array in startup code if we are compiling using -// -nostdlib/-nostartfiles. -void _init(void) -{ - -} diff --git a/hw/bsp/stm32l476disco/stm32l4xx_hal_conf.h b/hw/bsp/stm32l476disco/stm32l4xx_hal_conf.h deleted file mode 100644 index 312f86da1..000000000 --- a/hw/bsp/stm32l476disco/stm32l4xx_hal_conf.h +++ /dev/null @@ -1,420 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_conf.h - * @author MCD Application Team - * @brief HAL configuration template file. - * This file should be copied to the application folder and renamed - * to stm32l4xx_hal_conf.h. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_CONF_H -#define __STM32L4xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED -/* #define HAL_ADC_MODULE_ENABLED */ -/* #define HAL_CAN_MODULE_ENABLED */ -/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ -/* #define HAL_COMP_MODULE_ENABLED */ -#define HAL_CORTEX_MODULE_ENABLED -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -/* #define HAL_DFSDM_MODULE_ENABLED */ -#define HAL_DMA_MODULE_ENABLED -/* #define HAL_FIREWALL_MODULE_ENABLED */ -#define HAL_FLASH_MODULE_ENABLED -/* #define HAL_NAND_MODULE_ENABLED */ -// #define HAL_NOR_MODULE_ENABLED -// #define HAL_SRAM_MODULE_ENABLED -/* #define HAL_HCD_MODULE_ENABLED */ -#define HAL_GPIO_MODULE_ENABLED -//#define HAL_I2C_MODULE_ENABLED -/* #define HAL_IRDA_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ -//#define HAL_LCD_MODULE_ENABLED -/* #define HAL_LPTIM_MODULE_ENABLED */ -/* #define HAL_OPAMP_MODULE_ENABLED */ -//#define HAL_PCD_MODULE_ENABLED -#define HAL_PWR_MODULE_ENABLED -/* #define HAL_QSPI_MODULE_ENABLED */ -#define HAL_RCC_MODULE_ENABLED -/* #define HAL_RNG_MODULE_ENABLED */ -/* #define HAL_RTC_MODULE_ENABLED */ -//#define HAL_SAI_MODULE_ENABLED -//#define HAL_SD_MODULE_ENABLED -/* #define HAL_SMARTCARD_MODULE_ENABLED */ -/* #define HAL_SMBUS_MODULE_ENABLED */ -/* #define HAL_SPI_MODULE_ENABLED */ -/* #define HAL_SWPMI_MODULE_ENABLED */ -/* #define HAL_TIM_MODULE_ENABLED */ -/* #define HAL_TSC_MODULE_ENABLED */ -#define HAL_UART_MODULE_ENABLED -/* #define HAL_USART_MODULE_ENABLED */ -/* #define HAL_WWDG_MODULE_ENABLED */ - - -/* ########################## Oscillator Values adaptation ####################*/ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal Multiple Speed oscillator (MSI) default value. - * This value is the default MSI range value after Reset. - */ -#if !defined (MSI_VALUE) - #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/ -#endif /* MSI_VALUE */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG. - * This internal oscillator is mainly dedicated to provide a high precision clock to - * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. - * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency - * which is subject to manufacturing process variations. - */ -#if !defined (HSI48_VALUE) - #define HSI48_VALUE 48000000U /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. - The real value my vary depending on manufacturing process variations.*/ -#endif /* HSI48_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/ -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature.*/ -/** - * @brief External Low Speed oscillator (LSE) value. - * This value is used by the UART, RTC HAL module to compute the system frequency - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE 32768U /*!< Value of the External oscillator in Hz*/ -#endif /* LSE_VALUE */ - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief External clock source for SAI1 peripheral - * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source - * frequency. - */ -#if !defined (EXTERNAL_SAI1_CLOCK_VALUE) - #define EXTERNAL_SAI1_CLOCK_VALUE 48000U /*!< Value of the SAI1 External clock source in Hz*/ -#endif /* EXTERNAL_SAI1_CLOCK_VALUE */ - -/** - * @brief External clock source for SAI2 peripheral - * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source - * frequency. - */ -#if !defined (EXTERNAL_SAI2_CLOCK_VALUE) - #define EXTERNAL_SAI2_CLOCK_VALUE 48000U /*!< Value of the SAI2 External clock source in Hz*/ -#endif /* EXTERNAL_SAI2_CLOCK_VALUE */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE 3300U /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY 0U /*!< tick interrupt priority */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 0U -#define INSTRUCTION_CACHE_ENABLE 1U -#define DATA_CACHE_ENABLE 1U - - -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ -#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ -#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */ -#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ -#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ -#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ -#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ -#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ -#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ -#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */ -#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ -#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ -#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ -#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ -#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ -#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ -#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U /* HRTIM register callback disabled */ -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ -#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U /* JPEG register callback disabled */ -#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ -#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ -#define USE_HAL_MDIOS_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */ -#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */ -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ -#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ -#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ -#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ -#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ -#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ -#define USE_HAL_SWPMI_REGISTER_CALLBACKS 0U /* SWPMI register callback disabled */ -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ -#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ -#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1U */ - -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver - * Activated: CRC code is present inside driver - * Deactivated: CRC code cleaned from driver - */ - -#define USE_SPI_CRC 1U - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32l4xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32l4xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32l4xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_DFSDM_MODULE_ENABLED - #include "stm32l4xx_hal_dfsdm.h" -#endif /* HAL_DFSDM_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32l4xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32l4xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32l4xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_CAN_LEGACY_MODULE_ENABLED - #include "Legacy/stm32l4xx_hal_can_legacy.h" -#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ - -#ifdef HAL_COMP_MODULE_ENABLED - #include "stm32l4xx_hal_comp.h" -#endif /* HAL_COMP_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32l4xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32l4xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32l4xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_FIREWALL_MODULE_ENABLED - #include "stm32l4xx_hal_firewall.h" -#endif /* HAL_FIREWALL_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32l4xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32l4xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32l4xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED - #include "stm32l4xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32l4xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32l4xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_LCD_MODULE_ENABLED - #include "stm32l4xx_hal_lcd.h" -#endif /* HAL_LCD_MODULE_ENABLED */ - -#ifdef HAL_LPTIM_MODULE_ENABLED -#include "stm32l4xx_hal_lptim.h" -#endif /* HAL_LPTIM_MODULE_ENABLED */ - -#ifdef HAL_OPAMP_MODULE_ENABLED -#include "stm32l4xx_hal_opamp.h" -#endif /* HAL_OPAMP_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32l4xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_QSPI_MODULE_ENABLED - #include "stm32l4xx_hal_qspi.h" -#endif /* HAL_QSPI_MODULE_ENABLED */ - -#ifdef HAL_RNG_MODULE_ENABLED - #include "stm32l4xx_hal_rng.h" -#endif /* HAL_RNG_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32l4xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SAI_MODULE_ENABLED - #include "stm32l4xx_hal_sai.h" -#endif /* HAL_SAI_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32l4xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_SMBUS_MODULE_ENABLED - #include "stm32l4xx_hal_smbus.h" -#endif /* HAL_SMBUS_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32l4xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_SWPMI_MODULE_ENABLED - #include "stm32l4xx_hal_swpmi.h" -#endif /* HAL_SWPMI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32l4xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_TSC_MODULE_ENABLED - #include "stm32l4xx_hal_tsc.h" -#endif /* HAL_TSC_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32l4xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32l4xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32l4xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32l4xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32l4xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32l4xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_HCD_MODULE_ENABLED - #include "stm32l4xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t *file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L4xx_HAL_CONF_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/hw/bsp/stm32l4r5nucleo/STM32L4RXxI_FLASH.ld b/hw/bsp/stm32l4r5nucleo/STM32L4RXxI_FLASH.ld deleted file mode 100644 index f93a16041..000000000 --- a/hw/bsp/stm32l4r5nucleo/STM32L4RXxI_FLASH.ld +++ /dev/null @@ -1,167 +0,0 @@ -/* -***************************************************************************** -** - -** File : LinkerScript.ld -** -** Abstract : Linker script for STM32L4RxI Device with -** 2048KByte FLASH, 640KByte RAM -** -** Set heap size, stack size and stack location according -** to application requirements. -** -** Set memory bank area and size if external memory is used. -** -** Target : STMicroelectronics STM32 -** -** -** Distribution: The file is distributed as is, without any warranty -** of any kind. -** -** (c)Copyright Ac6. -** You may use this file as-is or modify it according to the needs of your -** project. Distribution of this file (unmodified or modified) is not -** permitted. Ac6 permit registered System Workbench for MCU users the -** rights to distribute the assembled, compiled & linked contents of this -** file as part of an application binary file, provided that it is built -** using the System Workbench for MCU toolchain. -** -***************************************************************************** -*/ - -/* Entry Point */ -ENTRY(Reset_Handler) - -/* Highest address of the user mode stack */ -_estack = 0x200a0000; /* end of RAM */ -/* Generate a link error if heap and stack don't fit into RAM */ -_Min_Heap_Size = 0x200; /* required amount of heap */ -_Min_Stack_Size = 0x460; /* required amount of stack */ - -/* Specify the memory areas */ -MEMORY -{ -RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 640K -FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 2048K -} - -/* Define output sections */ -SECTIONS -{ - /* The startup code goes first into FLASH */ - .isr_vector : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } >FLASH - - /* The program code and other data goes into FLASH */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - - KEEP (*(.init)) - KEEP (*(.fini)) - - . = ALIGN(4); - _etext = .; /* define a global symbols at end of code */ - } >FLASH - - /* Constant data goes into FLASH */ - .rodata : - { - . = ALIGN(4); - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - . = ALIGN(4); - } >FLASH - - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } >FLASH - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } >FLASH - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } >FLASH - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } >FLASH - - /* used by the startup to initialize data */ - _sidata = LOADADDR(.data); - - /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end */ - } >RAM AT> FLASH - - - /* Uninitialized data section */ - . = ALIGN(4); - .bss : - { - /* This is used by the startup in order to initialize the .bss secion */ - _sbss = .; /* define a global symbol at bss start */ - __bss_start__ = _sbss; - *(.bss) - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end */ - __bss_end__ = _ebss; - } >RAM - - /* User_heap_stack section, used to check that there is enough RAM left */ - ._user_heap_stack : - { - . = ALIGN(8); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - . = . + _Min_Heap_Size; - . = . + _Min_Stack_Size; - . = ALIGN(8); - } >RAM - - - - /* Remove information from the standard libraries */ - /DISCARD/ : - { - libc.a ( * ) - libm.a ( * ) - libgcc.a ( * ) - } - - .ARM.attributes 0 : { *(.ARM.attributes) } -} diff --git a/hw/bsp/stm32l4r5nucleo/board.mk b/hw/bsp/stm32l4r5nucleo/board.mk deleted file mode 100644 index 12a291d0a..000000000 --- a/hw/bsp/stm32l4r5nucleo/board.mk +++ /dev/null @@ -1,50 +0,0 @@ -ST_FAMILY = l4 -DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver - -ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY) -ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver - -CFLAGS += \ - -flto \ - -mthumb \ - -mabi=aapcs \ - -mcpu=cortex-m4 \ - -mfloat-abi=hard \ - -mfpu=fpv4-sp-d16 \ - -nostdlib -nostartfiles \ - -DHSE_VALUE=8000000 \ - -DSTM32L4R5xx \ - -DCFG_TUSB_MCU=OPT_MCU_STM32L4 - -# suppress warning caused by vendor mcu driver -CFLAGS += -Wno-error=maybe-uninitialized -Wno-error=cast-align - -# All source paths should be relative to the top level. -LD_FILE = hw/bsp/$(BOARD)/STM32L4RXxI_FLASH.ld - -SRC_C += \ - src/portable/st/synopsys/dcd_synopsys.c \ - $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \ - $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \ - $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \ - $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \ - $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \ - $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr.c \ - $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr_ex.c \ - $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \ - $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c - -SRC_S += \ - $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l4r5xx.s - -INC += \ - $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ - $(TOP)/$(ST_CMSIS)/Include \ - $(TOP)/$(ST_HAL_DRIVER)/Inc \ - $(TOP)/hw/bsp/$(BOARD) - -# For freeRTOS port source -FREERTOS_PORT = ARM_CM4F - -# flash target using on-board stlink -flash: flash-stlink diff --git a/hw/bsp/stm32l4r5nucleo/stm32l4r5nucleo.c b/hw/bsp/stm32l4r5nucleo/stm32l4r5nucleo.c deleted file mode 100644 index 8c661b602..000000000 --- a/hw/bsp/stm32l4r5nucleo/stm32l4r5nucleo.c +++ /dev/null @@ -1,287 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2019 William D. Jones (thor0505@comcast.net), - * Ha Thach (tinyusb.org) - * Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#include "../board.h" - -#include "stm32l4xx_hal.h" - -//--------------------------------------------------------------------+ -// Forward USB interrupt events to TinyUSB IRQ Handler -//--------------------------------------------------------------------+ -void OTG_FS_IRQHandler(void) -{ - tud_int_handler(0); -} - -//--------------------------------------------------------------------+ -// MACRO TYPEDEF CONSTANT ENUM -//--------------------------------------------------------------------+ - -#define LED_PORT GPIOB -#define LED_PIN GPIO_PIN_14 -#define LED_STATE_ON 1 - -#define BUTTON_PORT GPIOC -#define BUTTON_PIN GPIO_PIN_13 -#define BUTTON_STATE_ACTIVE 1 - -#define UARTx LPUART1 -#define UART_GPIO_PORT GPIOG -#define UART_GPIO_AF GPIO_AF8_LPUART1 -#define UART_TX_PIN GPIO_PIN_7 -#define UART_RX_PIN GPIO_PIN_8 - -UART_HandleTypeDef UartHandle; - -// enable all LED, Button, Uart, USB clock -static void all_rcc_clk_enable(void) -{ - __HAL_RCC_GPIOA_CLK_ENABLE(); // USB D+, D- - __HAL_RCC_GPIOB_CLK_ENABLE(); // LED - __HAL_RCC_GPIOC_CLK_ENABLE(); // Button - __HAL_RCC_GPIOG_CLK_ENABLE(); // Uart TX, RX - __HAL_RCC_LPUART1_CLK_ENABLE(); // LPUart1 module -} - -/** - * @brief System Clock Configuration - * The system Clock is configured as follow : - * System Clock source = PLL (MSI) - * SYSCLK(Hz) = 120000000 - * HCLK(Hz) = 120000000 - * AHB Prescaler = 1 - * APB1 Prescaler = 1 - * APB2 Prescaler = 1 - * MSI Frequency(Hz) = 48000000 - * PLL_M = 12 - * PLL_N = 60 - * PLL_P = 2 - * PLL_Q = 2 - * VDD(V) = 3.3 - * Main regulator output voltage = Scale1 mode - * Flash Latency(WS) = 5 - * The USB clock configuration from PLLSAI: - * PLLSAIP = 8 FIXME - * PLLSAIN = 384 FIXME - * PLLSAIQ = 7 FIXME - * @param None - * @retval None - */ -void SystemClock_Config(void) -{ - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - - /* Activate PLL with MSI , stabilizied via PLL by LSE */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI; - RCC_OscInitStruct.MSIState = RCC_MSI_ON; - RCC_OscInitStruct.LSEState = RCC_LSE_ON; - RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; - RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; - RCC_OscInitStruct.PLL.PLLM = 12; - RCC_OscInitStruct.PLL.PLLN = 60; - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - RCC_OscInitStruct.PLL.PLLQ = 2; - HAL_RCC_OscConfig(&RCC_OscInitStruct); - - /* Enable MSI Auto-calibration through LSE */ - HAL_RCCEx_EnableMSIPLLMode(); - - /* Select MSI output as USB clock source */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; - PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; - HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); - - /* Select MSI output as USB clock source */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; - PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1; - HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 - clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - // Avoid overshoot and start with HCLK 60 MHz - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV2; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; - HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3); - - /* AHB prescaler divider at 1 as second step */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5); -} - -void board_init(void) -{ - /* Enable Power Clock*/ - __HAL_RCC_PWR_CLK_ENABLE(); - /* Enable voltage range 1 boost mode for frequency above 80 Mhz */ - HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST); - - /* Set tick interrupt priority, default HAL value is intentionally invalid - and that prevents PLL initialization in HAL_RCC_OscConfig() */ - - HAL_InitTick((1UL << __NVIC_PRIO_BITS) - 1UL); - - SystemClock_Config(); - all_rcc_clk_enable(); - -#if CFG_TUSB_OS == OPT_OS_NONE - // 1ms tick timer - SysTick_Config(SystemCoreClock / 1000); -#elif CFG_TUSB_OS == OPT_OS_FREERTOS - // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) - //NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); -#endif - - /* Enable USB power on Pwrctrl CR2 register */ - HAL_PWREx_EnableVddUSB(); - - GPIO_InitTypeDef GPIO_InitStruct; - - // LED - GPIO_InitStruct.Pin = LED_PIN; - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - GPIO_InitStruct.Pull = GPIO_PULLUP; - HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct); - - // Button - GPIO_InitStruct.Pin = BUTTON_PIN; - GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct); - - // IOSV bit MUST be set to access GPIO port G[2:15] */ - __HAL_RCC_PWR_CLK_ENABLE(); - HAL_PWREx_EnableVddIO2(); - - // Uart - GPIO_InitStruct.Pin = UART_TX_PIN | UART_RX_PIN; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_PULLUP; - GPIO_InitStruct.Alternate = UART_GPIO_AF; - HAL_GPIO_Init(UART_GPIO_PORT, &GPIO_InitStruct); - - UartHandle.Instance = UARTx; - UartHandle.Init.BaudRate = CFG_BOARD_UART_BAUDRATE; - UartHandle.Init.WordLength = UART_WORDLENGTH_8B; - UartHandle.Init.StopBits = UART_STOPBITS_1; - UartHandle.Init.Parity = UART_PARITY_NONE; - UartHandle.Init.HwFlowCtl = UART_HWCONTROL_NONE; - UartHandle.Init.Mode = UART_MODE_TX_RX; - UartHandle.Init.OverSampling = UART_OVERSAMPLING_16; - UartHandle.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; - UartHandle.Init.ClockPrescaler = UART_PRESCALER_DIV1; - UartHandle.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; - - HAL_UART_Init(&UartHandle); - - /* Configure USB FS GPIOs */ - /* Configure DM DP Pins */ - GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12); - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /* Configure VBUS Pin */ - GPIO_InitStruct.Pin = GPIO_PIN_9; - GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /* Configure ID pin */ - GPIO_InitStruct.Pin = GPIO_PIN_10; - GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; - GPIO_InitStruct.Pull = GPIO_PULLUP; - GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /* Enable USB FS Clocks */ - __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); - - // Enable VBUS sense (B device) via pin PA9 - USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN; -} - -//--------------------------------------------------------------------+ -// Board porting API -//--------------------------------------------------------------------+ - -void board_led_write(bool state) -{ - HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON)); -} - -uint32_t board_button_read(void) -{ - return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN); -} - -int board_uart_read(uint8_t* buf, int len) -{ - (void) buf; (void) len; - return 0; -} - -int board_uart_write(void const * buf, int len) -{ - HAL_UART_Transmit(&UartHandle, (uint8_t*)(uintptr_t) buf, len, 0xffff); - return len; -} - -#if CFG_TUSB_OS == OPT_OS_NONE -volatile uint32_t system_ticks = 0; -void SysTick_Handler (void) -{ - system_ticks++; -} - -uint32_t board_millis(void) -{ - return system_ticks; -} -#endif - -void HardFault_Handler (void) -{ - asm("bkpt"); -} - -// Required by __libc_init_array in startup code if we are compiling using -// -nostdlib/-nostartfiles. -void _init(void) -{ - -} diff --git a/hw/bsp/stm32l4r5nucleo/stm32l4xx_hal_conf.h b/hw/bsp/stm32l4r5nucleo/stm32l4xx_hal_conf.h deleted file mode 100644 index 470ef1290..000000000 --- a/hw/bsp/stm32l4r5nucleo/stm32l4xx_hal_conf.h +++ /dev/null @@ -1,419 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_conf.h - * @author MCD Application Team - * @brief HAL configuration template file. - * This file should be copied to the application folder and renamed - * to stm32l4xx_hal_conf.h. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_CONF_H -#define __STM32L4xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED -/* #define HAL_ADC_MODULE_ENABLED */ -/* #define HAL_CAN_MODULE_ENABLED */ -/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ -/* #define HAL_COMP_MODULE_ENABLED */ -#define HAL_CORTEX_MODULE_ENABLED -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -/* #define HAL_DFSDM_MODULE_ENABLED */ -#define HAL_DMA_MODULE_ENABLED -/* #define HAL_FIREWALL_MODULE_ENABLED */ -#define HAL_FLASH_MODULE_ENABLED -/* #define HAL_NAND_MODULE_ENABLED */ -// #define HAL_NOR_MODULE_ENABLED -// #define HAL_SRAM_MODULE_ENABLED -/* #define HAL_HCD_MODULE_ENABLED */ -#define HAL_GPIO_MODULE_ENABLED -//#define HAL_I2C_MODULE_ENABLED -/* #define HAL_IRDA_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ -//#define HAL_LCD_MODULE_ENABLED -/* #define HAL_LPTIM_MODULE_ENABLED */ -/* #define HAL_OPAMP_MODULE_ENABLED */ -//#define HAL_PCD_MODULE_ENABLED -#define HAL_PWR_MODULE_ENABLED -/* #define HAL_QSPI_MODULE_ENABLED */ -#define HAL_RCC_MODULE_ENABLED -/* #define HAL_RNG_MODULE_ENABLED */ -/* #define HAL_RTC_MODULE_ENABLED */ -//#define HAL_SAI_MODULE_ENABLED -//#define HAL_SD_MODULE_ENABLED -/* #define HAL_SMARTCARD_MODULE_ENABLED */ -/* #define HAL_SMBUS_MODULE_ENABLED */ -/* #define HAL_SPI_MODULE_ENABLED */ -/* #define HAL_SWPMI_MODULE_ENABLED */ -/* #define HAL_TIM_MODULE_ENABLED */ -/* #define HAL_TSC_MODULE_ENABLED */ -#define HAL_UART_MODULE_ENABLED -/* #define HAL_USART_MODULE_ENABLED */ -/* #define HAL_WWDG_MODULE_ENABLED */ - - -/* ########################## Oscillator Values adaptation ####################*/ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal Multiple Speed oscillator (MSI) default value. - * This value is the default MSI range value after Reset. - */ -#if !defined (MSI_VALUE) - #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/ -#endif /* MSI_VALUE */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG. - * This internal oscillator is mainly dedicated to provide a high precision clock to - * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. - * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency - * which is subject to manufacturing process variations. - */ -#if !defined (HSI48_VALUE) - #define HSI48_VALUE 48000000U /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. - The real value my vary depending on manufacturing process variations.*/ -#endif /* HSI48_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/ -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature.*/ -/** - * @brief External Low Speed oscillator (LSE) value. - * This value is used by the UART, RTC HAL module to compute the system frequency - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE 32768U /*!< Value of the External oscillator in Hz*/ -#endif /* LSE_VALUE */ - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief External clock source for SAI1 peripheral - * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source - * frequency. - */ -#if !defined (EXTERNAL_SAI1_CLOCK_VALUE) - #define EXTERNAL_SAI1_CLOCK_VALUE 48000U /*!< Value of the SAI1 External clock source in Hz*/ -#endif /* EXTERNAL_SAI1_CLOCK_VALUE */ - -/** - * @brief External clock source for SAI2 peripheral - * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source - * frequency. - */ -#if !defined (EXTERNAL_SAI2_CLOCK_VALUE) - #define EXTERNAL_SAI2_CLOCK_VALUE 48000U /*!< Value of the SAI2 External clock source in Hz*/ -#endif /* EXTERNAL_SAI2_CLOCK_VALUE */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE 3300U /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY 0U /*!< tick interrupt priority */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 0U -#define INSTRUCTION_CACHE_ENABLE 1U -#define DATA_CACHE_ENABLE 1U - -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ -#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ -#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */ -#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ -#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ -#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ -#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ -#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ -#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ -#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */ -#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ -#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ -#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ -#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ -#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ -#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ -#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U /* HRTIM register callback disabled */ -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ -#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U /* JPEG register callback disabled */ -#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ -#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ -#define USE_HAL_MDIOS_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */ -#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */ -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ -#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ -#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ -#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ -#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ -#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ -#define USE_HAL_SWPMI_REGISTER_CALLBACKS 0U /* SWPMI register callback disabled */ -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ -#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ -#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1U */ - -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver - * Activated: CRC code is present inside driver - * Deactivated: CRC code cleaned from driver - */ - -#define USE_SPI_CRC 1U - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32l4xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32l4xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32l4xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_DFSDM_MODULE_ENABLED - #include "stm32l4xx_hal_dfsdm.h" -#endif /* HAL_DFSDM_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32l4xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32l4xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32l4xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_CAN_LEGACY_MODULE_ENABLED - #include "Legacy/stm32l4xx_hal_can_legacy.h" -#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ - -#ifdef HAL_COMP_MODULE_ENABLED - #include "stm32l4xx_hal_comp.h" -#endif /* HAL_COMP_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32l4xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32l4xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32l4xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_FIREWALL_MODULE_ENABLED - #include "stm32l4xx_hal_firewall.h" -#endif /* HAL_FIREWALL_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32l4xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32l4xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32l4xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED - #include "stm32l4xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32l4xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32l4xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_LCD_MODULE_ENABLED - #include "stm32l4xx_hal_lcd.h" -#endif /* HAL_LCD_MODULE_ENABLED */ - -#ifdef HAL_LPTIM_MODULE_ENABLED -#include "stm32l4xx_hal_lptim.h" -#endif /* HAL_LPTIM_MODULE_ENABLED */ - -#ifdef HAL_OPAMP_MODULE_ENABLED -#include "stm32l4xx_hal_opamp.h" -#endif /* HAL_OPAMP_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32l4xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_QSPI_MODULE_ENABLED - #include "stm32l4xx_hal_qspi.h" -#endif /* HAL_QSPI_MODULE_ENABLED */ - -#ifdef HAL_RNG_MODULE_ENABLED - #include "stm32l4xx_hal_rng.h" -#endif /* HAL_RNG_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32l4xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SAI_MODULE_ENABLED - #include "stm32l4xx_hal_sai.h" -#endif /* HAL_SAI_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32l4xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_SMBUS_MODULE_ENABLED - #include "stm32l4xx_hal_smbus.h" -#endif /* HAL_SMBUS_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32l4xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_SWPMI_MODULE_ENABLED - #include "stm32l4xx_hal_swpmi.h" -#endif /* HAL_SWPMI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32l4xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_TSC_MODULE_ENABLED - #include "stm32l4xx_hal_tsc.h" -#endif /* HAL_TSC_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32l4xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32l4xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32l4xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32l4xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32l4xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32l4xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_HCD_MODULE_ENABLED - #include "stm32l4xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t *file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L4xx_HAL_CONF_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 9750757aa..a850d4e15 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -59,7 +59,7 @@ #define DWC2_REG(_port) ((dwc2_regs_t*) DWC2_REG_BASE) // Debug level for DWC2 -#define DWC2_DEBUG 1 +#define DWC2_DEBUG 2 static TU_ATTR_ALIGNED(4) uint32_t _setup_packet[2]; -- cgit v1.3.1 From 4431ced598ca8ee1f07d6acd7f1424f17755c155 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 2 Nov 2021 16:20:39 +0700 Subject: add L4 to ci, update doc --- .github/workflows/build.yml | 1 + README.rst | 2 +- docs/reference/supported.rst | 39 ++++++++++++++++++++++++++++++++++----- 3 files changed, 36 insertions(+), 6 deletions(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index b16cf3f87..53a1628a0 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -56,6 +56,7 @@ jobs: - 'stm32f4' - 'stm32f7' - 'stm32h7' + - 'stm32l4' steps: - name: Setup Python uses: actions/setup-python@v2 diff --git a/README.rst b/README.rst index 11804ccd1..329c0da53 100644 --- a/README.rst +++ b/README.rst @@ -47,7 +47,7 @@ The stack supports the following MCUs: - **Renesas:** RX63N, RX65N - **Silabs:** EFM32GG12 - **Sony:** CXD56 -- **ST:** STM32 series: L0, L1, F0, F1, F2, F3, F4, F7, H7 both FullSpeed and HighSpeed +- **ST:** STM32 series: L0, L1, L4, F0, F1, F2, F3, F4, F7, H7 both FullSpeed and HighSpeed - **TI:** MSP430 - **ValentyUSB:** eptri diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst index c8a441f18..ef924adb4 100644 --- a/docs/reference/supported.rst +++ b/docs/reference/supported.rst @@ -305,29 +305,58 @@ Sony ST STM32 -------- -- `Adafruit Feather STM32F405 `__ -- `Micro Python PyBoard v1.1 `__ -- `STLink-V3 Mini `__ -- `STM32 L035c8 Discovery `__ -- `STM32 L4R5zi Nucleo `__ +F0 +^^ - `STM32 F070rb Nucleo `__ - `STM32 F072 Evaluation `__ - `STM32 F072rb Discovery `__ + +F1 +^^ - `STM32 F103c8 Blue Pill `__ - `STM32 F103rc Mini v2.0 `__ + +F2 +^^ - `STM32 F207zg Nucleo `__ + +F3 +^^ - `STM32 F303vc Discovery `__ + +F4 +^^ +- `Adafruit Feather STM32F405 `__ +- `Micro Python PyBoard v1.1 `__ - `STM32 F401cc Black Pill `__ - `STM32 F407vg Discovery `__ - `STM32 F411ce Black Pill `__ - `STM32 F411ve Discovery `__ - `STM32 F412zg Discovery `__ - `STM32 F412zg Nucleo `__ + +F7 +^^ + +- `STLink-V3 Mini `__ - `STM32 F723e Discovery `__ - `STM32 F746zg Nucleo `__ - `STM32 F746g Discovery `__ - `STM32 F767zi Nucleo `__ - `STM32 F769i Discovery `__ + +L0 +^^ +- `STM32 L035c8 Discovery `__ + +L4 +^^ +- `STM32 L476vg Discovery `__ +- `STM32 L4P5zg Nucleo `__ +- `STM32 L4R5zi Nucleo `__ + +H7 +^^ - `STM32 H743zi Nucleo `__ - `STM32 H743i Evaluation `__ - `STM32 H745i Discovery `__ -- cgit v1.3.1 From 1046786acf0ab35bf41009b985f7627d6b859a48 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 2 Nov 2021 18:17:59 +0700 Subject: change broadcom submodule path from git to http --- .gitmodules | 3 +-- hw/bsp/raspberrypi4/family.mk | 2 ++ 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/.gitmodules b/.gitmodules index b86245990..79dec144e 100644 --- a/.gitmodules +++ b/.gitmodules @@ -129,5 +129,4 @@ url = https://github.com/hathach/mm32sdk.git [submodule "hw/mcu/broadcom"] path = hw/mcu/broadcom - url = git@github.com:adafruit/broadcom-peripherals.git - branch = main-build + url = https://github.com/adafruit/broadcom-peripherals.git diff --git a/hw/bsp/raspberrypi4/family.mk b/hw/bsp/raspberrypi4/family.mk index b0326c056..b1d14a6ec 100644 --- a/hw/bsp/raspberrypi4/family.mk +++ b/hw/bsp/raspberrypi4/family.mk @@ -43,5 +43,7 @@ SRC_S += $(MCU_DIR)/broadcom/boot.S $(BUILD)/kernel8.img: $(BUILD)/$(PROJECT).elf $(OBJCOPY) -O binary $^ $@ +# Copy to kernel to netboot drive or SD card +# Change destinaation to fit your need flash: $(BUILD)/kernel8.img @$(CP) $< /home/$(USER)/Documents/code/pi4_tinyusb/boot_cpy -- cgit v1.3.1 From 0e733ae14bf4c165abcd27ccb1408927b72a0047 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 2 Nov 2021 21:46:23 +0700 Subject: add pi4 to ci build in build_aarch64 --- .github/workflows/build.yml | 160 --------------------- .github/workflows/build_aarch64.yml | 67 +++++++++ .github/workflows/build_arm.yml | 160 +++++++++++++++++++++ .gitmodules | 1 + examples/device/audio_4_channel_mic/src/main.c | 2 +- examples/device/audio_test/src/main.c | 2 +- examples/device/cdc_msc_freertos/.skip.MCU_BCM2711 | 0 .../hid_composite_freertos/.skip.MCU_BCM2711 | 0 hw/bsp/raspberrypi4/family.mk | 5 +- 9 files changed, 232 insertions(+), 165 deletions(-) delete mode 100644 .github/workflows/build.yml create mode 100644 .github/workflows/build_aarch64.yml create mode 100644 .github/workflows/build_arm.yml create mode 100644 examples/device/cdc_msc_freertos/.skip.MCU_BCM2711 create mode 100644 examples/device/hid_composite_freertos/.skip.MCU_BCM2711 diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml deleted file mode 100644 index 53a1628a0..000000000 --- a/.github/workflows/build.yml +++ /dev/null @@ -1,160 +0,0 @@ -name: Build ARM - -on: - pull_request: - push: - release: - types: - - created - -jobs: - # --------------------------------------- - # Unit testing with Ceedling - # --------------------------------------- - unit-test: - runs-on: ubuntu-latest - steps: - - name: Setup Ruby - uses: actions/setup-ruby@v1 - with: - ruby-version: '2.7' - - - name: Checkout TinyUSB - uses: actions/checkout@v2 - - - name: Unit Tests - run: | - # Install Ceedling - gem install ceedling - cd test - ceedling test:all - - # --------------------------------------- - # Build ARM family - # --------------------------------------- - build-arm: - runs-on: ubuntu-latest - strategy: - fail-fast: false - matrix: - family: - # Alphabetical order - - 'imxrt' - - 'lpc15' - - 'lpc18' - - 'lpc54' - - 'lpc55' - - 'mm32' - - 'nrf' - - 'rp2040' - - 'samd11' - - 'samd21' - - 'samd51' - - 'saml2x' - - 'stm32f0' - - 'stm32f1' - - 'stm32f4' - - 'stm32f7' - - 'stm32h7' - - 'stm32l4' - steps: - - name: Setup Python - uses: actions/setup-python@v2 - - - name: Checkout TinyUSB - uses: actions/checkout@v2 - - - name: Checkout common submodules in lib - run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip lib/sct_neopixel - - - name: Checkout hathach/linkermap - uses: actions/checkout@v2 - with: - repository: hathach/linkermap - path: linkermap - - - name: Checkout pico-sdk - if: matrix.family == 'rp2040' - run: | - git clone --depth 1 -b develop https://github.com/raspberrypi/pico-sdk ~/pico-sdk - echo >> $GITHUB_ENV PICO_SDK_PATH=~/pico-sdk - - - name: Set Toolchain URL - run: echo >> $GITHUB_ENV TOOLCHAIN_URL=https://github.com/xpack-dev-tools/arm-none-eabi-gcc-xpack/releases/download/v10.2.1-1.1/xpack-arm-none-eabi-gcc-10.2.1-1.1-linux-x64.tar.gz - - - name: Cache Toolchain - uses: actions/cache@v2 - id: cache-toolchain - with: - path: ~/cache/ - key: ${{ runner.os }}-21-03-04-${{ env.TOOLCHAIN_URL }} - - - name: Install Toolchain - if: steps.cache-toolchain.outputs.cache-hit != 'true' - run: | - mkdir -p ~/cache/toolchain - wget --progress=dot:mega $TOOLCHAIN_URL -O toolchain.tar.gz - tar -C ~/cache/toolchain -xaf toolchain.tar.gz - - - name: Set Toolchain Path - run: echo >> $GITHUB_PATH `echo ~/cache/toolchain/*/bin` - - - name: Build - run: python3 tools/build_family.py ${{ matrix.family }} - - - name: Linker Map - run: | - pip install linkermap/ - for ex in `ls -d examples/device/*/`; do \ - find ${ex} -name *.map -print -quit | \ - xargs -I % sh -c 'echo "::group::%"; linkermap -v %; echo "::endgroup::"'; \ - done - - # --------------------------------------- - # Build all no-family (opharned) boards - # --------------------------------------- - build-board: - runs-on: ubuntu-latest - strategy: - fail-fast: false - matrix: - example: - # Alphabetical order, a group of 4 - - 'device/audio_test device/board_test device/cdc_dual_ports device/cdc_msc' - - 'device/cdc_msc_freertos device/dfu_runtime device/hid_composite device/hid_composite_freertos' - - 'device/hid_generic_inout device/hid_multiple_interface device/midi_test device/msc_dual_lun' - - 'device/net_lwip_webserver' - - 'device/uac2_headset device/usbtmc device/webusb_serial host/cdc_msc_hid' - - steps: - - name: Setup Python - uses: actions/setup-python@v2 - - - name: Checkout TinyUSB - uses: actions/checkout@v2 - - - name: Checkout common submodules in lib - run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip - - - name: Set Toolchain URL - run: echo >> $GITHUB_ENV TOOLCHAIN_URL=https://github.com/xpack-dev-tools/arm-none-eabi-gcc-xpack/releases/download/v10.2.1-1.1/xpack-arm-none-eabi-gcc-10.2.1-1.1-linux-x64.tar.gz - - - name: Cache Toolchain - uses: actions/cache@v2 - id: cache-toolchain - with: - path: ~/cache/ - key: ${{ runner.os }}-21-03-04-${{ env.TOOLCHAIN_URL }} - - - name: Install Toolchain - if: steps.cache-toolchain.outputs.cache-hit != 'true' - run: | - mkdir -p ~/cache/toolchain - wget --progress=dot:mega $TOOLCHAIN_URL -O toolchain.tar.gz - tar -C ~/cache/toolchain -xaf toolchain.tar.gz - - - name: Set Toolchain Path - run: echo >> $GITHUB_PATH `echo ~/cache/toolchain/*/bin` - - - name: Build - run: python3 tools/build_board.py ${{ matrix.example }} diff --git a/.github/workflows/build_aarch64.yml b/.github/workflows/build_aarch64.yml new file mode 100644 index 000000000..0cc7a5de1 --- /dev/null +++ b/.github/workflows/build_aarch64.yml @@ -0,0 +1,67 @@ +name: Build AArch64 + +on: + pull_request: + push: + release: + types: + - created + +jobs: + # --------------------------------------- + # Build AARCH64 family + # --------------------------------------- + build-arm: + runs-on: ubuntu-latest + strategy: + fail-fast: false + matrix: + family: + # Alphabetical order + - 'raspberrypi4' + steps: + - name: Setup Python + uses: actions/setup-python@v2 + + - name: Checkout TinyUSB + uses: actions/checkout@v2 + + - name: Checkout common submodules in lib + run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip lib/sct_neopixel + + - name: Checkout hathach/linkermap + uses: actions/checkout@v2 + with: + repository: hathach/linkermap + path: linkermap + + - name: Set Toolchain URL + run: echo >> $GITHUB_ENV TOOLCHAIN_URL=https://developer.arm.com/-/media/Files/downloads/gnu-a/10.3-2021.07/binrel/gcc-arm-10.3-2021.07-x86_64-aarch64-none-elf.tar.xz + + - name: Cache Toolchain + uses: actions/cache@v2 + id: cache-toolchain + with: + path: ~/cache/ + key: ${{ runner.os }}-21-11-02-${{ env.TOOLCHAIN_URL }} + + - name: Install Toolchain + if: steps.cache-toolchain.outputs.cache-hit != 'true' + run: | + mkdir -p ~/cache/toolchain + wget --progress=dot:mega $TOOLCHAIN_URL -O toolchain.tar.gz + tar -C ~/cache/toolchain -xaf toolchain.tar.gz + + - name: Set Toolchain Path + run: echo >> $GITHUB_PATH `echo ~/cache/toolchain/*/bin` + + - name: Build + run: python3 tools/build_family.py ${{ matrix.family }} + + - name: Linker Map + run: | + pip install linkermap/ + for ex in `ls -d examples/device/*/`; do \ + find ${ex} -name *.map -print -quit | \ + xargs -I % sh -c 'echo "::group::%"; linkermap -v %; echo "::endgroup::"'; \ + done diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml new file mode 100644 index 000000000..53a1628a0 --- /dev/null +++ b/.github/workflows/build_arm.yml @@ -0,0 +1,160 @@ +name: Build ARM + +on: + pull_request: + push: + release: + types: + - created + +jobs: + # --------------------------------------- + # Unit testing with Ceedling + # --------------------------------------- + unit-test: + runs-on: ubuntu-latest + steps: + - name: Setup Ruby + uses: actions/setup-ruby@v1 + with: + ruby-version: '2.7' + + - name: Checkout TinyUSB + uses: actions/checkout@v2 + + - name: Unit Tests + run: | + # Install Ceedling + gem install ceedling + cd test + ceedling test:all + + # --------------------------------------- + # Build ARM family + # --------------------------------------- + build-arm: + runs-on: ubuntu-latest + strategy: + fail-fast: false + matrix: + family: + # Alphabetical order + - 'imxrt' + - 'lpc15' + - 'lpc18' + - 'lpc54' + - 'lpc55' + - 'mm32' + - 'nrf' + - 'rp2040' + - 'samd11' + - 'samd21' + - 'samd51' + - 'saml2x' + - 'stm32f0' + - 'stm32f1' + - 'stm32f4' + - 'stm32f7' + - 'stm32h7' + - 'stm32l4' + steps: + - name: Setup Python + uses: actions/setup-python@v2 + + - name: Checkout TinyUSB + uses: actions/checkout@v2 + + - name: Checkout common submodules in lib + run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip lib/sct_neopixel + + - name: Checkout hathach/linkermap + uses: actions/checkout@v2 + with: + repository: hathach/linkermap + path: linkermap + + - name: Checkout pico-sdk + if: matrix.family == 'rp2040' + run: | + git clone --depth 1 -b develop https://github.com/raspberrypi/pico-sdk ~/pico-sdk + echo >> $GITHUB_ENV PICO_SDK_PATH=~/pico-sdk + + - name: Set Toolchain URL + run: echo >> $GITHUB_ENV TOOLCHAIN_URL=https://github.com/xpack-dev-tools/arm-none-eabi-gcc-xpack/releases/download/v10.2.1-1.1/xpack-arm-none-eabi-gcc-10.2.1-1.1-linux-x64.tar.gz + + - name: Cache Toolchain + uses: actions/cache@v2 + id: cache-toolchain + with: + path: ~/cache/ + key: ${{ runner.os }}-21-03-04-${{ env.TOOLCHAIN_URL }} + + - name: Install Toolchain + if: steps.cache-toolchain.outputs.cache-hit != 'true' + run: | + mkdir -p ~/cache/toolchain + wget --progress=dot:mega $TOOLCHAIN_URL -O toolchain.tar.gz + tar -C ~/cache/toolchain -xaf toolchain.tar.gz + + - name: Set Toolchain Path + run: echo >> $GITHUB_PATH `echo ~/cache/toolchain/*/bin` + + - name: Build + run: python3 tools/build_family.py ${{ matrix.family }} + + - name: Linker Map + run: | + pip install linkermap/ + for ex in `ls -d examples/device/*/`; do \ + find ${ex} -name *.map -print -quit | \ + xargs -I % sh -c 'echo "::group::%"; linkermap -v %; echo "::endgroup::"'; \ + done + + # --------------------------------------- + # Build all no-family (opharned) boards + # --------------------------------------- + build-board: + runs-on: ubuntu-latest + strategy: + fail-fast: false + matrix: + example: + # Alphabetical order, a group of 4 + - 'device/audio_test device/board_test device/cdc_dual_ports device/cdc_msc' + - 'device/cdc_msc_freertos device/dfu_runtime device/hid_composite device/hid_composite_freertos' + - 'device/hid_generic_inout device/hid_multiple_interface device/midi_test device/msc_dual_lun' + - 'device/net_lwip_webserver' + - 'device/uac2_headset device/usbtmc device/webusb_serial host/cdc_msc_hid' + + steps: + - name: Setup Python + uses: actions/setup-python@v2 + + - name: Checkout TinyUSB + uses: actions/checkout@v2 + + - name: Checkout common submodules in lib + run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip + + - name: Set Toolchain URL + run: echo >> $GITHUB_ENV TOOLCHAIN_URL=https://github.com/xpack-dev-tools/arm-none-eabi-gcc-xpack/releases/download/v10.2.1-1.1/xpack-arm-none-eabi-gcc-10.2.1-1.1-linux-x64.tar.gz + + - name: Cache Toolchain + uses: actions/cache@v2 + id: cache-toolchain + with: + path: ~/cache/ + key: ${{ runner.os }}-21-03-04-${{ env.TOOLCHAIN_URL }} + + - name: Install Toolchain + if: steps.cache-toolchain.outputs.cache-hit != 'true' + run: | + mkdir -p ~/cache/toolchain + wget --progress=dot:mega $TOOLCHAIN_URL -O toolchain.tar.gz + tar -C ~/cache/toolchain -xaf toolchain.tar.gz + + - name: Set Toolchain Path + run: echo >> $GITHUB_PATH `echo ~/cache/toolchain/*/bin` + + - name: Build + run: python3 tools/build_board.py ${{ matrix.example }} diff --git a/.gitmodules b/.gitmodules index 79dec144e..a95e64ee6 100644 --- a/.gitmodules +++ b/.gitmodules @@ -130,3 +130,4 @@ [submodule "hw/mcu/broadcom"] path = hw/mcu/broadcom url = https://github.com/adafruit/broadcom-peripherals.git + branch = main-build diff --git a/examples/device/audio_4_channel_mic/src/main.c b/examples/device/audio_4_channel_mic/src/main.c index 983b87e5b..d085dd43a 100644 --- a/examples/device/audio_4_channel_mic/src/main.c +++ b/examples/device/audio_4_channel_mic/src/main.c @@ -141,7 +141,7 @@ void tud_resume_cb(void) void audio_task(void) { // Yet to be filled - e.g. put meas data into TX FIFOs etc. - asm("nop"); + // asm("nop"); } //--------------------------------------------------------------------+ diff --git a/examples/device/audio_test/src/main.c b/examples/device/audio_test/src/main.c index 9a2fdd3a1..ed13ce993 100644 --- a/examples/device/audio_test/src/main.c +++ b/examples/device/audio_test/src/main.c @@ -142,7 +142,7 @@ void tud_resume_cb(void) void audio_task(void) { // Yet to be filled - e.g. put meas data into TX FIFOs etc. - asm("nop"); + // asm("nop"); } //--------------------------------------------------------------------+ diff --git a/examples/device/cdc_msc_freertos/.skip.MCU_BCM2711 b/examples/device/cdc_msc_freertos/.skip.MCU_BCM2711 new file mode 100644 index 000000000..e69de29bb diff --git a/examples/device/hid_composite_freertos/.skip.MCU_BCM2711 b/examples/device/hid_composite_freertos/.skip.MCU_BCM2711 new file mode 100644 index 000000000..e69de29bb diff --git a/hw/bsp/raspberrypi4/family.mk b/hw/bsp/raspberrypi4/family.mk index b1d14a6ec..2e61b9e74 100644 --- a/hw/bsp/raspberrypi4/family.mk +++ b/hw/bsp/raspberrypi4/family.mk @@ -1,9 +1,8 @@ -UF2_FAMILY_ID = 0x57755a57 +MCU_DIR = hw/mcu/broadcom +DEPS_SUBMODULES += $(MCU_DIR) include $(TOP)/$(BOARD_PATH)/board.mk -MCU_DIR = hw/mcu/broadcom - CC = clang CFLAGS += \ -- cgit v1.3.1 From 28b177484d15971dc12ec76dfe71ffcae433835a Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 2 Nov 2021 22:27:00 +0700 Subject: skip net example for pi4 due to ssize_t conflict --- examples/device/net_lwip_webserver/.skip.MCU_BCM2711 | 1 + 1 file changed, 1 insertion(+) create mode 100644 examples/device/net_lwip_webserver/.skip.MCU_BCM2711 diff --git a/examples/device/net_lwip_webserver/.skip.MCU_BCM2711 b/examples/device/net_lwip_webserver/.skip.MCU_BCM2711 new file mode 100644 index 000000000..bdc68f5db --- /dev/null +++ b/examples/device/net_lwip_webserver/.skip.MCU_BCM2711 @@ -0,0 +1 @@ +tinyusb/lib/lwip/src/include/lwip/arch.h:202:13: error: conflicting types for 'ssize_t' \ No newline at end of file -- cgit v1.3.1 From e16506cb52d6d8e8b2a2e2910f10c32a89a6d322 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 3 Nov 2021 12:24:10 +0700 Subject: clean up --- hw/bsp/raspberrypi4/family.c | 17 +++-------------- hw/bsp/raspberrypi4/family.mk | 3 +++ src/portable/synopsys/dwc2/dwc2_bcm.h | 5 +++++ 3 files changed, 11 insertions(+), 14 deletions(-) diff --git a/hw/bsp/raspberrypi4/family.c b/hw/bsp/raspberrypi4/family.c index ffeb05f9f..95b28c6fc 100644 --- a/hw/bsp/raspberrypi4/family.c +++ b/hw/bsp/raspberrypi4/family.c @@ -30,10 +30,9 @@ #include "broadcom/interrupts.h" #include "broadcom/io.h" #include "broadcom/mmu.h" +//#include "broadcom/caches.h" #include "broadcom/vcmailbox.h" -uint32_t SystemCoreClock = 700 * 1000 * 1000; - //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ @@ -49,11 +48,6 @@ void USB_IRQHandler(void) //--------------------------------------------------------------------+ // Board porting API //--------------------------------------------------------------------+ - -void print(const char* str) { - board_uart_write(str, strlen(str)); -} - void board_init(void) { gpio_initOutputPinWithPullNone(18); @@ -63,13 +57,14 @@ void board_init(void) gpio_setPinOutputBool(18, true); gpio_initOutputPinWithPullNone(42); setup_mmu_flat_map(); +// init_caches(); + // gpio_initOutputPinWithPullNone(23); // gpio_initOutputPinWithPullNone(24); // gpio_initOutputPinWithPullNone(25); gpio_setPinOutputBool(18, false); uart_init(); gpio_setPinOutputBool(18, true); - const char* greeting = "hello to gdb2\r\n"; gpio_setPinOutputBool(18, false); for (size_t i = 0; i < 5; i++) { // while (true) { @@ -92,7 +87,6 @@ void board_init(void) } // uart_writeText("hello from io\n"); // gpio_setPinOutputBool(24, true); - board_uart_write(greeting, strlen(greeting)); // gpio_setPinOutputBool(24, false); // gpio_setPinOutputBool(25, true); // print(); @@ -110,13 +104,8 @@ void board_init(void) // } // while (1) uart_update(); - printf("hello %d\r\n", 21); - // Turn on USB peripheral. - print("Turning on USB power\r\n"); - vcmailbox_set_power_state(VCMAILBOX_DEVICE_USB_HCD, true); - print("USB power on\r\n"); BP_SetPriority(USB_IRQn, 0x00); BP_ClearPendingIRQ(USB_IRQn); diff --git a/hw/bsp/raspberrypi4/family.mk b/hw/bsp/raspberrypi4/family.mk index 2e61b9e74..2a0a87788 100644 --- a/hw/bsp/raspberrypi4/family.mk +++ b/hw/bsp/raspberrypi4/family.mk @@ -6,6 +6,7 @@ include $(TOP)/$(BOARD_PATH)/board.mk CC = clang CFLAGS += \ + -mcpu=cortex-a72 \ -Wall \ -O0 \ -ffreestanding \ @@ -26,6 +27,8 @@ SRC_C += \ $(MCU_DIR)/broadcom/mmu.c \ $(MCU_DIR)/broadcom/vcmailbox.c +# $(MCU_DIR)/broadcom/caches.c \ + CROSS_COMPILE = aarch64-none-elf- SKIP_NANOLIB = 1 diff --git a/src/portable/synopsys/dwc2/dwc2_bcm.h b/src/portable/synopsys/dwc2/dwc2_bcm.h index 38d10930c..317e79cf7 100644 --- a/src/portable/synopsys/dwc2/dwc2_bcm.h +++ b/src/portable/synopsys/dwc2/dwc2_bcm.h @@ -32,11 +32,16 @@ #endif #include "broadcom/interrupts.h" +//#include "broadcom/caches.h" #define DWC2_REG_BASE 0xFE980000UL #define DWC2_EP_MAX 8 #define DWC2_EP_FIFO_SIZE 4096 +//#define dcache_clean(_addr, _size) data_clean(_addr, _size) +//#define dcache_invalidate(_addr, _size) data_invalidate(_addr, _size) +//#define dcache_clean_invalidate(_addr, _size) data_clean_and_invalidate(_addr, _size) + TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_enable(uint8_t rhport) { -- cgit v1.3.1 From 0faff5a859cfd91f92a9b91f65a1d6a164f0a7be Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 3 Nov 2021 13:13:08 +0700 Subject: update broadcom peripherals to latest --- hw/bsp/raspberrypi4/family.c | 4 ++-- hw/bsp/raspberrypi4/family.mk | 2 +- hw/mcu/broadcom | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/bsp/raspberrypi4/family.c b/hw/bsp/raspberrypi4/family.c index 95b28c6fc..7a7a0e9ff 100644 --- a/hw/bsp/raspberrypi4/family.c +++ b/hw/bsp/raspberrypi4/family.c @@ -30,7 +30,7 @@ #include "broadcom/interrupts.h" #include "broadcom/io.h" #include "broadcom/mmu.h" -//#include "broadcom/caches.h" +#include "broadcom/caches.h" #include "broadcom/vcmailbox.h" //--------------------------------------------------------------------+ @@ -57,7 +57,7 @@ void board_init(void) gpio_setPinOutputBool(18, true); gpio_initOutputPinWithPullNone(42); setup_mmu_flat_map(); -// init_caches(); + init_caches(); // gpio_initOutputPinWithPullNone(23); // gpio_initOutputPinWithPullNone(24); diff --git a/hw/bsp/raspberrypi4/family.mk b/hw/bsp/raspberrypi4/family.mk index 2a0a87788..475cfa4ff 100644 --- a/hw/bsp/raspberrypi4/family.mk +++ b/hw/bsp/raspberrypi4/family.mk @@ -25,9 +25,9 @@ SRC_C += \ $(MCU_DIR)/broadcom/interrupts.c \ $(MCU_DIR)/broadcom/io.c \ $(MCU_DIR)/broadcom/mmu.c \ + $(MCU_DIR)/broadcom/caches.c \ $(MCU_DIR)/broadcom/vcmailbox.c -# $(MCU_DIR)/broadcom/caches.c \ CROSS_COMPILE = aarch64-none-elf- diff --git a/hw/mcu/broadcom b/hw/mcu/broadcom index 55cd6f798..d126323fc 160000 --- a/hw/mcu/broadcom +++ b/hw/mcu/broadcom @@ -1 +1 @@ -Subproject commit 55cd6f798a45cac905d7bf81baa2bcbf7de7c42e +Subproject commit d126323fc77e81d1f18677a439685a4754ea02aa -- cgit v1.3.1 From b51d038b656688b6150470d23752a306ee150da3 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 4 Nov 2021 12:30:11 +0700 Subject: fix issue with bcm2711 caching issue by ading ISB() after dwc2_dcd_int_enable90 also add hwcfg_list for reference --- src/portable/synopsys/dwc2/dcd_dwc2.c | 16 +- src/portable/synopsys/dwc2/dwc2_bcm.h | 10 +- src/portable/synopsys/dwc2/hwcfg_list.md | 722 +++++++++++++++++++++++++++++++ 3 files changed, 743 insertions(+), 5 deletions(-) create mode 100644 src/portable/synopsys/dwc2/hwcfg_list.md diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index a850d4e15..3967f225e 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -56,11 +56,25 @@ // MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ +// DWC2 registers #define DWC2_REG(_port) ((dwc2_regs_t*) DWC2_REG_BASE) // Debug level for DWC2 #define DWC2_DEBUG 2 +#ifndef dcache_clean +#define dcache_clean(_addr, _size) +#endif + +#ifndef dcache_invalidate +#define dcache_invalidate(_addr, _size) +#endif + +#ifndef dcache_clean_invalidate +#define dcache_clean_invalidate(_addr, _size) +#endif + + static TU_ATTR_ALIGNED(4) uint32_t _setup_packet[2]; typedef struct { @@ -71,7 +85,7 @@ typedef struct { uint8_t interval; } xfer_ctl_t; -xfer_ctl_t xfer_status[DWC2_EP_MAX][2]; +static xfer_ctl_t xfer_status[DWC2_EP_MAX][2]; #define XFER_CTL_BASE(_ep, _dir) (&xfer_status[_ep][_dir]) // EP0 transfers are limited to 1 packet - larger sizes has to be split diff --git a/src/portable/synopsys/dwc2/dwc2_bcm.h b/src/portable/synopsys/dwc2/dwc2_bcm.h index 317e79cf7..0263d19ba 100644 --- a/src/portable/synopsys/dwc2/dwc2_bcm.h +++ b/src/portable/synopsys/dwc2/dwc2_bcm.h @@ -32,21 +32,22 @@ #endif #include "broadcom/interrupts.h" -//#include "broadcom/caches.h" +#include "broadcom/caches.h" #define DWC2_REG_BASE 0xFE980000UL #define DWC2_EP_MAX 8 #define DWC2_EP_FIFO_SIZE 4096 -//#define dcache_clean(_addr, _size) data_clean(_addr, _size) -//#define dcache_invalidate(_addr, _size) data_invalidate(_addr, _size) -//#define dcache_clean_invalidate(_addr, _size) data_clean_and_invalidate(_addr, _size) +#define dcache_clean(_addr, _size) data_clean(_addr, _size) +#define dcache_invalidate(_addr, _size) data_invalidate(_addr, _size) +#define dcache_clean_invalidate(_addr, _size) data_clean_and_invalidate(_addr, _size) TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_enable(uint8_t rhport) { (void) rhport; BP_EnableIRQ(USB_IRQn); + __asm__ volatile("isb"); } TU_ATTR_ALWAYS_INLINE @@ -54,6 +55,7 @@ static inline void dwc2_dcd_int_disable (uint8_t rhport) { (void) rhport; BP_DisableIRQ(USB_IRQn); + __asm__ volatile("isb"); } static inline void dwc2_remote_wakeup_delay(void) diff --git a/src/portable/synopsys/dwc2/hwcfg_list.md b/src/portable/synopsys/dwc2/hwcfg_list.md new file mode 100644 index 000000000..495a30fd0 --- /dev/null +++ b/src/portable/synopsys/dwc2/hwcfg_list.md @@ -0,0 +1,722 @@ +# DWC2 Hardware Configuration Registers + +## Broadcom BCM2711 (Pi4) + +dwc2->guid = 2708A000 +dwc2->gsnpsid = 4F54280A +dwc2->ghwcfg1 = 0 + +dwc2->ghwcfg2 = 228DDD50 +hw_cfg2->op_mode = 0 +hw_cfg2->arch = 2 +hw_cfg2->point2point = 0 +hw_cfg2->hs_phy_type = 1 +hw_cfg2->fs_phy_type = 1 +hw_cfg2->num_dev_ep = 7 +hw_cfg2->num_host_ch = 7 +hw_cfg2->period_channel_support = 1 +hw_cfg2->enable_dynamic_fifo = 1 +hw_cfg2->mul_cpu_int = 0 +hw_cfg2->nperiod_tx_q_depth = 2 +hw_cfg2->host_period_tx_q_depth = 2 +hw_cfg2->dev_token_q_depth = 8 +hw_cfg2->otg_enable_ic_usb = 0 + +dwc2->ghwcfg3 = FF000E8 +hw_cfg3->xfer_size_width = 8 +hw_cfg3->packet_size_width = 6 +hw_cfg3->otg_enable = 1 +hw_cfg3->i2c_enable = 0 +hw_cfg3->vendor_ctrl_itf = 0 +hw_cfg3->optional_feature_removed = 0 +hw_cfg3->synch_reset = 0 +hw_cfg3->otg_adp_support = 0 +hw_cfg3->otg_enable_hsic = 0 +hw_cfg3->battery_charger_support = 0 +hw_cfg3->lpm_mode = 0 +hw_cfg3->total_fifo_size = 4080 + +dwc2->ghwcfg4 = 1FF00020 +hw_cfg4->num_dev_period_in_ep = 0 +hw_cfg4->power_optimized = 0 +hw_cfg4->ahb_freq_min = 1 +hw_cfg4->hibernation = 0 +hw_cfg4->service_interval_mode = 0 +hw_cfg4->ipg_isoc_en = 0 +hw_cfg4->acg_enable = 0 +hw_cfg4->utmi_phy_data_width = 0 +hw_cfg4->dev_ctrl_ep_num = 0 +hw_cfg4->iddg_filter_enabled = 1 +hw_cfg4->vbus_valid_filter_enabled = 1 +hw_cfg4->a_valid_filter_enabled = 1 +hw_cfg4->b_valid_filter_enabled = 1 +hw_cfg4->dedicated_fifos = 1 +hw_cfg4->num_dev_in_eps = 15 +hw_cfg4->dma_desc_enable = 0 +hw_cfg4->dma_dynamic = 0 + +## EFM32GG FS + +dwc2->guid = 0 +dwc2->gsnpsid = 4F54330A +dwc2->ghwcfg1 = 0 + +dwc2->ghwcfg2 = 228F5910 +hw_cfg2->op_mode = 0 +hw_cfg2->arch = 2 +hw_cfg2->point2point = 0 +hw_cfg2->hs_phy_type = 0 +hw_cfg2->fs_phy_type = 1 +hw_cfg2->num_dev_ep = 6 +hw_cfg2->num_host_ch = 13 +hw_cfg2->period_channel_support = 1 +hw_cfg2->enable_dynamic_fifo = 1 +hw_cfg2->mul_cpu_int = 0 +hw_cfg2->nperiod_tx_q_depth = 2 +hw_cfg2->host_period_tx_q_depth = 2 +hw_cfg2->dev_token_q_depth = 8 +hw_cfg2->otg_enable_ic_usb = 0 + +dwc2->ghwcfg3 = 1F204E8 +hw_cfg3->xfer_size_width = 8 +hw_cfg3->packet_size_width = 6 +hw_cfg3->otg_enable = 1 +hw_cfg3->i2c_enable = 0 +hw_cfg3->vendor_ctrl_itf = 0 +hw_cfg3->optional_feature_removed = 1 +hw_cfg3->synch_reset = 0 +hw_cfg3->otg_adp_support = 0 +hw_cfg3->otg_enable_hsic = 0 +hw_cfg3->battery_charger_support = 0 +hw_cfg3->lpm_mode = 0 +hw_cfg3->total_fifo_size = 498 + +dwc2->ghwcfg4 = 1BF08030 +hw_cfg4->num_dev_period_in_ep = 0 +hw_cfg4->power_optimized = 1 +hw_cfg4->ahb_freq_min = 1 +hw_cfg4->hibernation = 0 +hw_cfg4->service_interval_mode = 0 +hw_cfg4->ipg_isoc_en = 0 +hw_cfg4->acg_enable = 0 +hw_cfg4->utmi_phy_data_width = 2 +hw_cfg4->dev_ctrl_ep_num = 0 +hw_cfg4->iddg_filter_enabled = 1 +hw_cfg4->vbus_valid_filter_enabled = 1 +hw_cfg4->a_valid_filter_enabled = 1 +hw_cfg4->b_valid_filter_enabled = 1 +hw_cfg4->dedicated_fifos = 1 +hw_cfg4->num_dev_in_eps = 13 +hw_cfg4->dma_desc_enable = 0 +hw_cfg4->dma_dynamic = 0 + +## ESP32-S2 Fullspeed + +dwc2->guid = 0 +dwc2->gsnpsid = 4F54400A +dwc2->ghwcfg1 = 0 + +dwc2->ghwcfg2 = 224DD930 +hw_cfg2->op_mode = 2 +hw_cfg2->arch = 3 +hw_cfg2->point2point = 0 +hw_cfg2->hs_phy_type = 1 +hw_cfg2->fs_phy_type = 2 +hw_cfg2->num_dev_ep = 6 +hw_cfg2->num_host_ch = 9 +hw_cfg2->period_channel_support = 0 +hw_cfg2->enable_dynamic_fifo = 1 +hw_cfg2->mul_cpu_int = 1 +hw_cfg2->nperiod_tx_q_depth = 1 +hw_cfg2->host_period_tx_q_depth = 2 +hw_cfg2->dev_token_q_depth = 22 +hw_cfg2->otg_enable_ic_usb = 0 + +dwc2->ghwcfg3 = C804B5 +hw_cfg3->xfer_size_width = 10 +hw_cfg3->packet_size_width = 5 +hw_cfg3->otg_enable = 0 +hw_cfg3->i2c_enable = 0 +hw_cfg3->vendor_ctrl_itf = 1 +hw_cfg3->optional_feature_removed = 0 +hw_cfg3->synch_reset = 1 +hw_cfg3->otg_adp_support = 1 +hw_cfg3->otg_enable_hsic = 0 +hw_cfg3->battery_charger_support = 1 +hw_cfg3->lpm_mode = 0 +hw_cfg3->total_fifo_size = 23130 + +dwc2->ghwcfg4 = D3F0A030 +hw_cfg4->num_dev_period_in_ep = 10 +hw_cfg4->power_optimized = 1 +hw_cfg4->ahb_freq_min = 0 +hw_cfg4->hibernation = 1 +hw_cfg4->service_interval_mode = 0 +hw_cfg4->ipg_isoc_en = 1 +hw_cfg4->acg_enable = 1 +hw_cfg4->utmi_phy_data_width = 1 +hw_cfg4->dev_ctrl_ep_num = 10 +hw_cfg4->iddg_filter_enabled = 1 +hw_cfg4->vbus_valid_filter_enabled = 0 +hw_cfg4->a_valid_filter_enabled = 1 +hw_cfg4->b_valid_filter_enabled = 0 +hw_cfg4->dedicated_fifos = 0 +hw_cfg4->num_dev_in_eps = 13 +hw_cfg4->dma_desc_enable = 0 +hw_cfg4->dma_dynamic = 1 + +## STM32F407 and STM32F207 + +STM32F407 and STM32F207 are exactly the same + +### STM32F407 Fullspeed + +dwc2->guid = 1200 +dwc2->gsnpsid = 4F54281A +dwc2->ghwcfg1 = 0 + +dwc2->ghwcfg2 = 229DCD20 +hw_cfg2->op_mode = 0 +hw_cfg2->arch = 0 +hw_cfg2->point2point = 1 +hw_cfg2->hs_phy_type = 0 +hw_cfg2->fs_phy_type = 1 +hw_cfg2->num_dev_ep = 3 +hw_cfg2->num_host_ch = 7 +hw_cfg2->period_channel_support = 1 +hw_cfg2->enable_dynamic_fifo = 1 +hw_cfg2->mul_cpu_int = 1 +hw_cfg2->nperiod_tx_q_depth = 2 +hw_cfg2->host_period_tx_q_depth = 2 +hw_cfg2->dev_token_q_depth = 8 +hw_cfg2->otg_enable_ic_usb = 0 + +dwc2->ghwcfg3 = 20001E8 +hw_cfg3->xfer_size_width = 8 +hw_cfg3->packet_size_width = 6 +hw_cfg3->otg_enable = 1 +hw_cfg3->i2c_enable = 1 +hw_cfg3->vendor_ctrl_itf = 0 +hw_cfg3->optional_feature_removed = 0 +hw_cfg3->synch_reset = 0 +hw_cfg3->otg_adp_support = 0 +hw_cfg3->otg_enable_hsic = 0 +hw_cfg3->battery_charger_support = 0 +hw_cfg3->lpm_mode = 0 +hw_cfg3->total_fifo_size = 512 + +dwc2->ghwcfg4 = FF08030 +hw_cfg4->num_dev_period_in_ep = 0 +hw_cfg4->power_optimized = 1 +hw_cfg4->ahb_freq_min = 1 +hw_cfg4->hibernation = 0 +hw_cfg4->service_interval_mode = 0 +hw_cfg4->ipg_isoc_en = 0 +hw_cfg4->acg_enable = 0 +hw_cfg4->utmi_phy_data_width = 2 +hw_cfg4->dev_ctrl_ep_num = 0 +hw_cfg4->iddg_filter_enabled = 1 +hw_cfg4->vbus_valid_filter_enabled = 1 +hw_cfg4->a_valid_filter_enabled = 1 +hw_cfg4->b_valid_filter_enabled = 1 +hw_cfg4->dedicated_fifos = 1 +hw_cfg4->num_dev_in_eps = 7 +hw_cfg4->dma_desc_enable = 0 +hw_cfg4->dma_dynamic = 0 + +### STM32F407 Highspeed + +dwc2->guid = 1100 +dwc2->gsnpsid = 4F54281A +dwc2->ghwcfg1 = 0 + +dwc2->ghwcfg2 = 229ED590 +hw_cfg2->op_mode = 0 +hw_cfg2->arch = 2 +hw_cfg2->point2point = 0 +hw_cfg2->hs_phy_type = 2 +hw_cfg2->fs_phy_type = 1 +hw_cfg2->num_dev_ep = 5 +hw_cfg2->num_host_ch = 11 +hw_cfg2->period_channel_support = 1 +hw_cfg2->enable_dynamic_fifo = 1 +hw_cfg2->mul_cpu_int = 1 +hw_cfg2->nperiod_tx_q_depth = 2 +hw_cfg2->host_period_tx_q_depth = 2 +hw_cfg2->dev_token_q_depth = 8 +hw_cfg2->otg_enable_ic_usb = 0 + +dwc2->ghwcfg3 = 3F403E8 +hw_cfg3->xfer_size_width = 8 +hw_cfg3->packet_size_width = 6 +hw_cfg3->otg_enable = 1 +hw_cfg3->i2c_enable = 1 +hw_cfg3->vendor_ctrl_itf = 1 +hw_cfg3->optional_feature_removed = 0 +hw_cfg3->synch_reset = 0 +hw_cfg3->otg_adp_support = 0 +hw_cfg3->otg_enable_hsic = 0 +hw_cfg3->battery_charger_support = 0 +hw_cfg3->lpm_mode = 0 +hw_cfg3->total_fifo_size = 1012 + +dwc2->ghwcfg4 = 17F00030 +hw_cfg4->num_dev_period_in_ep = 0 +hw_cfg4->power_optimized = 1 +hw_cfg4->ahb_freq_min = 1 +hw_cfg4->hibernation = 0 +hw_cfg4->service_interval_mode = 0 +hw_cfg4->ipg_isoc_en = 0 +hw_cfg4->acg_enable = 0 +hw_cfg4->utmi_phy_data_width = 0 +hw_cfg4->dev_ctrl_ep_num = 0 +hw_cfg4->iddg_filter_enabled = 1 +hw_cfg4->vbus_valid_filter_enabled = 1 +hw_cfg4->a_valid_filter_enabled = 1 +hw_cfg4->b_valid_filter_enabled = 1 +hw_cfg4->dedicated_fifos = 1 +hw_cfg4->num_dev_in_eps = 11 +hw_cfg4->dma_desc_enable = 0 +hw_cfg4->dma_dynamic = 0 + +## STM32F411 Fullspeed + +dwc2->guid = 1200 +dwc2->gsnpsid = 4F54281A +dwc2->ghwcfg1 = 0 + +dwc2->ghwcfg2 = 229DCD20 +hw_cfg2->op_mode = 0 +hw_cfg2->arch = 0 +hw_cfg2->point2point = 1 +hw_cfg2->hs_phy_type = 0 +hw_cfg2->fs_phy_type = 1 +hw_cfg2->num_dev_ep = 3 +hw_cfg2->num_host_ch = 7 +hw_cfg2->period_channel_support = 1 +hw_cfg2->enable_dynamic_fifo = 1 +hw_cfg2->mul_cpu_int = 1 +hw_cfg2->nperiod_tx_q_depth = 2 +hw_cfg2->host_period_tx_q_depth = 2 +hw_cfg2->dev_token_q_depth = 8 +hw_cfg2->otg_enable_ic_usb = 0 + +dwc2->ghwcfg3 = 20001E8 +hw_cfg3->xfer_size_width = 8 +hw_cfg3->packet_size_width = 6 +hw_cfg3->otg_enable = 1 +hw_cfg3->i2c_enable = 1 +hw_cfg3->vendor_ctrl_itf = 0 +hw_cfg3->optional_feature_removed = 0 +hw_cfg3->synch_reset = 0 +hw_cfg3->otg_adp_support = 0 +hw_cfg3->otg_enable_hsic = 0 +hw_cfg3->battery_charger_support = 0 +hw_cfg3->lpm_mode = 0 +hw_cfg3->total_fifo_size = 512 + +dwc2->ghwcfg4 = FF08030 +hw_cfg4->num_dev_period_in_ep = 0 +hw_cfg4->power_optimized = 1 +hw_cfg4->ahb_freq_min = 1 +hw_cfg4->hibernation = 0 +hw_cfg4->service_interval_mode = 0 +hw_cfg4->ipg_isoc_en = 0 +hw_cfg4->acg_enable = 0 +hw_cfg4->utmi_phy_data_width = 2 +hw_cfg4->dev_ctrl_ep_num = 0 +hw_cfg4->iddg_filter_enabled = 1 +hw_cfg4->vbus_valid_filter_enabled = 1 +hw_cfg4->a_valid_filter_enabled = 1 +hw_cfg4->b_valid_filter_enabled = 1 +hw_cfg4->dedicated_fifos = 1 +hw_cfg4->num_dev_in_eps = 7 +hw_cfg4->dma_desc_enable = 0 +hw_cfg4->dma_dynamic = 0 + +## STM32F412 FS + +dwc2->guid = 2000 +dwc2->gsnpsid = 4F54320A +dwc2->ghwcfg1 = 0 + +dwc2->ghwcfg2 = 229ED520 +hw_cfg2->op_mode = 0 +hw_cfg2->arch = 0 +hw_cfg2->point2point = 1 +hw_cfg2->hs_phy_type = 0 +hw_cfg2->fs_phy_type = 1 +hw_cfg2->num_dev_ep = 5 +hw_cfg2->num_host_ch = 11 +hw_cfg2->period_channel_support = 1 +hw_cfg2->enable_dynamic_fifo = 1 +hw_cfg2->mul_cpu_int = 1 +hw_cfg2->nperiod_tx_q_depth = 2 +hw_cfg2->host_period_tx_q_depth = 2 +hw_cfg2->dev_token_q_depth = 8 +hw_cfg2->otg_enable_ic_usb = 0 + +dwc2->ghwcfg3 = 200D1E8 +hw_cfg3->xfer_size_width = 8 +hw_cfg3->packet_size_width = 6 +hw_cfg3->otg_enable = 1 +hw_cfg3->i2c_enable = 1 +hw_cfg3->vendor_ctrl_itf = 0 +hw_cfg3->optional_feature_removed = 0 +hw_cfg3->synch_reset = 0 +hw_cfg3->otg_adp_support = 1 +hw_cfg3->otg_enable_hsic = 0 +hw_cfg3->battery_charger_support = 1 +hw_cfg3->lpm_mode = 1 +hw_cfg3->total_fifo_size = 512 + +dwc2->ghwcfg4 = 17F08030 +hw_cfg4->num_dev_period_in_ep = 0 +hw_cfg4->power_optimized = 1 +hw_cfg4->ahb_freq_min = 1 +hw_cfg4->hibernation = 0 +hw_cfg4->service_interval_mode = 0 +hw_cfg4->ipg_isoc_en = 0 +hw_cfg4->acg_enable = 0 +hw_cfg4->utmi_phy_data_width = 2 +hw_cfg4->dev_ctrl_ep_num = 0 +hw_cfg4->iddg_filter_enabled = 1 +hw_cfg4->vbus_valid_filter_enabled = 1 +hw_cfg4->a_valid_filter_enabled = 1 +hw_cfg4->b_valid_filter_enabled = 1 +hw_cfg4->dedicated_fifos = 1 +hw_cfg4->num_dev_in_eps = 11 +hw_cfg4->dma_desc_enable = 0 +hw_cfg4->dma_dynamic = 0 + +## STM32F723 + +### STM32F723 HighSpeed + +dwc2->guid = 3100 +dwc2->gsnpsid = 4F54330A +dwc2->ghwcfg1 = 0 + +dwc2->ghwcfg2 = 229FE1D0 +hw_cfg2->op_mode = 0 +hw_cfg2->arch = 2 +hw_cfg2->point2point = 0 +hw_cfg2->hs_phy_type = 3 +hw_cfg2->fs_phy_type = 1 +hw_cfg2->num_dev_ep = 8 +hw_cfg2->num_host_ch = 15 +hw_cfg2->period_channel_support = 1 +hw_cfg2->enable_dynamic_fifo = 1 +hw_cfg2->mul_cpu_int = 1 +hw_cfg2->nperiod_tx_q_depth = 2 +hw_cfg2->host_period_tx_q_depth = 2 +hw_cfg2->dev_token_q_depth = 8 +hw_cfg2->otg_enable_ic_usb = 0 + +dwc2->ghwcfg3 = 3EED2E8 +hw_cfg3->xfer_size_width = 8 +hw_cfg3->packet_size_width = 6 +hw_cfg3->otg_enable = 1 +hw_cfg3->i2c_enable = 0 +hw_cfg3->vendor_ctrl_itf = 1 +hw_cfg3->optional_feature_removed = 0 +hw_cfg3->synch_reset = 0 +hw_cfg3->otg_adp_support = 1 +hw_cfg3->otg_enable_hsic = 0 +hw_cfg3->battery_charger_support = 1 +hw_cfg3->lpm_mode = 1 +hw_cfg3->total_fifo_size = 1006 + +dwc2->ghwcfg4 = 23F00030 +hw_cfg4->num_dev_period_in_ep = 0 +hw_cfg4->power_optimized = 1 +hw_cfg4->ahb_freq_min = 1 +hw_cfg4->hibernation = 0 +hw_cfg4->service_interval_mode = 0 +hw_cfg4->ipg_isoc_en = 0 +hw_cfg4->acg_enable = 0 +hw_cfg4->utmi_phy_data_width = 0 +hw_cfg4->dev_ctrl_ep_num = 0 +hw_cfg4->iddg_filter_enabled = 1 +hw_cfg4->vbus_valid_filter_enabled = 1 +hw_cfg4->a_valid_filter_enabled = 1 +hw_cfg4->b_valid_filter_enabled = 1 +hw_cfg4->dedicated_fifos = 1 +hw_cfg4->num_dev_in_eps = 1 +hw_cfg4->dma_desc_enable = 1 +hw_cfg4->dma_dynamic = 0 + +### STM32F723 Fullspeed + +dwc2->guid = 3000 +dwc2->gsnpsid = 4F54330A +dwc2->ghwcfg1 = 0 + +dwc2->ghwcfg2 = 229ED520 +hw_cfg2->op_mode = 0 +hw_cfg2->arch = 0 +hw_cfg2->point2point = 1 +hw_cfg2->hs_phy_type = 0 +hw_cfg2->fs_phy_type = 1 +hw_cfg2->num_dev_ep = 5 +hw_cfg2->num_host_ch = 11 +hw_cfg2->period_channel_support = 1 +hw_cfg2->enable_dynamic_fifo = 1 +hw_cfg2->mul_cpu_int = 1 +hw_cfg2->nperiod_tx_q_depth = 2 +hw_cfg2->host_period_tx_q_depth = 2 +hw_cfg2->dev_token_q_depth = 8 +hw_cfg2->otg_enable_ic_usb = 0 + +dwc2->ghwcfg3 = 200D1E8 +hw_cfg3->xfer_size_width = 8 +hw_cfg3->packet_size_width = 6 +hw_cfg3->otg_enable = 1 +hw_cfg3->i2c_enable = 1 +hw_cfg3->vendor_ctrl_itf = 0 +hw_cfg3->optional_feature_removed = 0 +hw_cfg3->synch_reset = 0 +hw_cfg3->otg_adp_support = 1 +hw_cfg3->otg_enable_hsic = 0 +hw_cfg3->battery_charger_support = 1 +hw_cfg3->lpm_mode = 1 +hw_cfg3->total_fifo_size = 512 + +dwc2->ghwcfg4 = 17F08030 +hw_cfg4->num_dev_period_in_ep = 0 +hw_cfg4->power_optimized = 1 +hw_cfg4->ahb_freq_min = 1 +hw_cfg4->hibernation = 0 +hw_cfg4->service_interval_mode = 0 +hw_cfg4->ipg_isoc_en = 0 +hw_cfg4->acg_enable = 0 +hw_cfg4->utmi_phy_data_width = 2 +hw_cfg4->dev_ctrl_ep_num = 0 +hw_cfg4->iddg_filter_enabled = 1 +hw_cfg4->vbus_valid_filter_enabled = 1 +hw_cfg4->a_valid_filter_enabled = 1 +hw_cfg4->b_valid_filter_enabled = 1 +hw_cfg4->dedicated_fifos = 1 +hw_cfg4->num_dev_in_eps = 11 +hw_cfg4->dma_desc_enable = 0 +hw_cfg4->dma_dynamic = 0 + +## STM32F767 FS + +dwc2->guid = 2000 +dwc2->gsnpsid = 4F54320A +dwc2->ghwcfg1 = 0 + +dwc2->ghwcfg2 = 229ED520 +hw_cfg2->op_mode = 0 +hw_cfg2->arch = 0 +hw_cfg2->point2point = 1 +hw_cfg2->hs_phy_type = 0 +hw_cfg2->fs_phy_type = 1 +hw_cfg2->num_dev_ep = 5 +hw_cfg2->num_host_ch = 11 +hw_cfg2->period_channel_support = 1 +hw_cfg2->enable_dynamic_fifo = 1 +hw_cfg2->mul_cpu_int = 1 +hw_cfg2->nperiod_tx_q_depth = 2 +hw_cfg2->host_period_tx_q_depth = 2 +hw_cfg2->dev_token_q_depth = 8 +hw_cfg2->otg_enable_ic_usb = 0 + +dwc2->ghwcfg3 = 200D1E8 +hw_cfg3->xfer_size_width = 8 +hw_cfg3->packet_size_width = 6 +hw_cfg3->otg_enable = 1 +hw_cfg3->i2c_enable = 1 +hw_cfg3->vendor_ctrl_itf = 0 +hw_cfg3->optional_feature_removed = 0 +hw_cfg3->synch_reset = 0 +hw_cfg3->otg_adp_support = 1 +hw_cfg3->otg_enable_hsic = 0 +hw_cfg3->battery_charger_support = 1 +hw_cfg3->lpm_mode = 1 +hw_cfg3->total_fifo_size = 512 + +dwc2->ghwcfg4 = 17F08030 +hw_cfg4->num_dev_period_in_ep = 0 +hw_cfg4->power_optimized = 1 +hw_cfg4->ahb_freq_min = 1 +hw_cfg4->hibernation = 0 +hw_cfg4->service_interval_mode = 0 +hw_cfg4->ipg_isoc_en = 0 +hw_cfg4->acg_enable = 0 +hw_cfg4->utmi_phy_data_width = 2 +hw_cfg4->dev_ctrl_ep_num = 0 +hw_cfg4->iddg_filter_enabled = 1 +hw_cfg4->vbus_valid_filter_enabled = 1 +hw_cfg4->a_valid_filter_enabled = 1 +hw_cfg4->b_valid_filter_enabled = 1 +hw_cfg4->dedicated_fifos = 1 +hw_cfg4->num_dev_in_eps = 11 +hw_cfg4->dma_desc_enable = 0 +hw_cfg4->dma_dynamic = 0 + +## STM32H743 (both cores HS) + +dwc2->guid = 2300 +dwc2->gsnpsid = 4F54330A +dwc2->ghwcfg1 = 0 + +dwc2->ghwcfg2 = 229FE190 +hw_cfg2->op_mode = 0 +hw_cfg2->arch = 2 +hw_cfg2->point2point = 0 +hw_cfg2->hs_phy_type = 2 +hw_cfg2->fs_phy_type = 1 +hw_cfg2->num_dev_ep = 8 +hw_cfg2->num_host_ch = 15 +hw_cfg2->period_channel_support = 1 +hw_cfg2->enable_dynamic_fifo = 1 +hw_cfg2->mul_cpu_int = 1 +hw_cfg2->nperiod_tx_q_depth = 2 +hw_cfg2->host_period_tx_q_depth = 2 +hw_cfg2->dev_token_q_depth = 8 +hw_cfg2->otg_enable_ic_usb = 0 + +dwc2->ghwcfg3 = 3B8D2E8 +hw_cfg3->xfer_size_width = 8 +hw_cfg3->packet_size_width = 6 +hw_cfg3->otg_enable = 1 +hw_cfg3->i2c_enable = 0 +hw_cfg3->vendor_ctrl_itf = 1 +hw_cfg3->optional_feature_removed = 0 +hw_cfg3->synch_reset = 0 +hw_cfg3->otg_adp_support = 1 +hw_cfg3->otg_enable_hsic = 0 +hw_cfg3->battery_charger_support = 1 +hw_cfg3->lpm_mode = 1 +hw_cfg3->total_fifo_size = 952 + +dwc2->ghwcfg4 = E3F00030 +hw_cfg4->num_dev_period_in_ep = 0 +hw_cfg4->power_optimized = 1 +hw_cfg4->ahb_freq_min = 1 +hw_cfg4->hibernation = 0 +hw_cfg4->service_interval_mode = 0 +hw_cfg4->ipg_isoc_en = 0 +hw_cfg4->acg_enable = 0 +hw_cfg4->utmi_phy_data_width = 0 +hw_cfg4->dev_ctrl_ep_num = 0 +hw_cfg4->iddg_filter_enabled = 1 +hw_cfg4->vbus_valid_filter_enabled = 1 +hw_cfg4->a_valid_filter_enabled = 1 +hw_cfg4->b_valid_filter_enabled = 1 +hw_cfg4->dedicated_fifos = 1 +hw_cfg4->num_dev_in_eps = 1 +hw_cfg4->dma_desc_enable = 1 +hw_cfg4->dma_dynamic = 1 + +## STM32L476 FS + +dwc2->guid = 2000 +dwc2->gsnpsid = 4F54310A +dwc2->ghwcfg1 = 0 + +dwc2->ghwcfg2 = 229ED520 +hw_cfg2->op_mode = 0 +hw_cfg2->arch = 0 +hw_cfg2->point2point = 1 +hw_cfg2->hs_phy_type = 0 +hw_cfg2->fs_phy_type = 1 +hw_cfg2->num_dev_ep = 5 +hw_cfg2->num_host_ch = 11 +hw_cfg2->period_channel_support = 1 +hw_cfg2->enable_dynamic_fifo = 1 +hw_cfg2->mul_cpu_int = 1 +hw_cfg2->nperiod_tx_q_depth = 2 +hw_cfg2->host_period_tx_q_depth = 2 +hw_cfg2->dev_token_q_depth = 8 +hw_cfg2->otg_enable_ic_usb = 0 + +dwc2->ghwcfg3 = 200D1E8 +hw_cfg3->xfer_size_width = 8 +hw_cfg3->packet_size_width = 6 +hw_cfg3->otg_enable = 1 +hw_cfg3->i2c_enable = 1 +hw_cfg3->vendor_ctrl_itf = 0 +hw_cfg3->optional_feature_removed = 0 +hw_cfg3->synch_reset = 0 +hw_cfg3->otg_adp_support = 1 +hw_cfg3->otg_enable_hsic = 0 +hw_cfg3->battery_charger_support = 1 +hw_cfg3->lpm_mode = 1 +hw_cfg3->total_fifo_size = 512 + +dwc2->ghwcfg4 = 17F08030 +hw_cfg4->num_dev_period_in_ep = 0 +hw_cfg4->power_optimized = 1 +hw_cfg4->ahb_freq_min = 1 +hw_cfg4->hibernation = 0 +hw_cfg4->service_interval_mode = 0 +hw_cfg4->ipg_isoc_en = 0 +hw_cfg4->acg_enable = 0 +hw_cfg4->utmi_phy_data_width = 2 +hw_cfg4->dev_ctrl_ep_num = 0 +hw_cfg4->iddg_filter_enabled = 1 +hw_cfg4->vbus_valid_filter_enabled = 1 +hw_cfg4->a_valid_filter_enabled = 1 +hw_cfg4->b_valid_filter_enabled = 1 +hw_cfg4->dedicated_fifos = 1 +hw_cfg4->num_dev_in_eps = 11 +hw_cfg4->dma_desc_enable = 0 +hw_cfg4->dma_dynamic = 0 + +## GD32VF103 Fullspeed + +dwc2->guid = 1000 +dwc2->gsnpsid = 0 +dwc2->ghwcfg1 = 0 + +dwc2->ghwcfg2 = 0 +hw_cfg2->op_mode = 0 +hw_cfg2->arch = 0 +hw_cfg2->point2point = 0 +hw_cfg2->hs_phy_type = 0 +hw_cfg2->fs_phy_type = 0 +hw_cfg2->num_dev_ep = 0 +hw_cfg2->num_host_ch = 0 +hw_cfg2->period_channel_support = 0 +hw_cfg2->enable_dynamic_fifo = 0 +hw_cfg2->mul_cpu_int = 0 +hw_cfg2->nperiod_tx_q_depth = 0 +hw_cfg2->host_period_tx_q_depth = 0 +hw_cfg2->dev_token_q_depth = 0 +hw_cfg2->otg_enable_ic_usb = 0 + +dwc2->ghwcfg3 = 0 +hw_cfg3->xfer_size_width = 0 +hw_cfg3->packet_size_width = 0 +hw_cfg3->otg_enable = 0 +hw_cfg3->i2c_enable = 0 +hw_cfg3->vendor_ctrl_itf = 0 +hw_cfg3->optional_feature_removed = 0 +hw_cfg3->synch_reset = 0 +hw_cfg3->otg_adp_support = 0 +hw_cfg3->otg_enable_hsic = 0 +hw_cfg3->battery_charger_support = 0 +hw_cfg3->lpm_mode = 0 +hw_cfg3->total_fifo_size = 0 + +dwc2->ghwcfg4 = 0 +hw_cfg4->num_dev_period_in_ep = 0 +hw_cfg4->power_optimized = 0 +hw_cfg4->ahb_freq_min = 0 +hw_cfg4->hibernation = 0 +hw_cfg4->service_interval_mode = 0 +hw_cfg4->ipg_isoc_en = 0 +hw_cfg4->acg_enable = 0 +hw_cfg4->utmi_phy_data_width = 0 +hw_cfg4->dev_ctrl_ep_num = 0 +hw_cfg4->iddg_filter_enabled = 0 +hw_cfg4->vbus_valid_filter_enabled = 0 +hw_cfg4->a_valid_filter_enabled = 0 +hw_cfg4->b_valid_filter_enabled = 0 +hw_cfg4->dedicated_fifos = 0 +hw_cfg4->num_dev_in_eps = 0 +hw_cfg4->dma_desc_enable = 0 +hw_cfg4->dma_dynamic = 0 -- cgit v1.3.1 From 4a8ac71711a70ccb122fdb59d731dc01cfed1464 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 4 Nov 2021 12:31:16 +0700 Subject: Add timer1 on pi4 for blinky this get usb irq triggered even without ISB() in previous commit --- README.rst | 6 ++-- hw/bsp/raspberrypi4/family.c | 77 +++++++++++++++---------------------------- hw/bsp/raspberrypi4/family.mk | 2 +- 3 files changed, 30 insertions(+), 55 deletions(-) diff --git a/README.rst b/README.rst index 329c0da53..1db022fc8 100644 --- a/README.rst +++ b/README.rst @@ -35,7 +35,7 @@ The stack supports the following MCUs: - **Dialog:** DA1469x - **Espressif:** ESP32-S2, ESP32-S3 - **MicroChip:** SAMD11, SAMD21, SAMD51, SAME5x, SAMG55, SAML21, SAML22, SAME7x -- **NordicSemi:** nRF52833, nRF52840 +- **NordicSemi:** nRF52833, nRF52840, nRF5340 - **Nuvoton:** NUC120, NUC121/NUC125, NUC126, NUC505 - **NXP:** @@ -45,9 +45,9 @@ The stack supports the following MCUs: - **Raspberry Pi:** RP2040 - **Renesas:** RX63N, RX65N -- **Silabs:** EFM32GG12 +- **Silabs:** EFM32GG - **Sony:** CXD56 -- **ST:** STM32 series: L0, L1, L4, F0, F1, F2, F3, F4, F7, H7 both FullSpeed and HighSpeed +- **ST:** STM32 series: L0, L1, L4, L4+, F0, F1, F2, F3, F4, F7, H7 - **TI:** MSP430 - **ValentyUSB:** eptri diff --git a/hw/bsp/raspberrypi4/family.c b/hw/bsp/raspberrypi4/family.c index 7a7a0e9ff..ba0b2700a 100644 --- a/hw/bsp/raspberrypi4/family.c +++ b/hw/bsp/raspberrypi4/family.c @@ -33,6 +33,14 @@ #include "broadcom/caches.h" #include "broadcom/vcmailbox.h" +// LED +#define LED_PIN 18 +#define LED_STATE_ON 1 + +// Button +#define BUTTON_PIN 16 +#define BUTTON_STATE_ACTIVE 0 + //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ @@ -50,63 +58,27 @@ void USB_IRQHandler(void) //--------------------------------------------------------------------+ void board_init(void) { - gpio_initOutputPinWithPullNone(18); - gpio_initOutputPinWithPullNone(19); - gpio_initOutputPinWithPullNone(20); - gpio_initOutputPinWithPullNone(21); - gpio_setPinOutputBool(18, true); - gpio_initOutputPinWithPullNone(42); setup_mmu_flat_map(); init_caches(); - // gpio_initOutputPinWithPullNone(23); - // gpio_initOutputPinWithPullNone(24); - // gpio_initOutputPinWithPullNone(25); - gpio_setPinOutputBool(18, false); + // LED + gpio_initOutputPinWithPullNone(LED_PIN); + board_led_write(true); + + // Button + // TODO + + // Uart uart_init(); - gpio_setPinOutputBool(18, true); - gpio_setPinOutputBool(18, false); - for (size_t i = 0; i < 5; i++) { - // while (true) { - for (size_t j = 0; j < 1000000; j++) { - __asm__("nop"); - } - gpio_setPinOutputBool(42, true); - gpio_setPinOutputBool(18, true); - gpio_setPinOutputBool(19, true); - gpio_setPinOutputBool(20, true); - gpio_setPinOutputBool(21, true); - for (size_t j = 0; j < 1000000; j++) { - __asm__("nop"); - } - gpio_setPinOutputBool(42, false); - gpio_setPinOutputBool(18, false); - gpio_setPinOutputBool(19, false); - gpio_setPinOutputBool(20, false); - gpio_setPinOutputBool(21, false); - } - // uart_writeText("hello from io\n"); - // gpio_setPinOutputBool(24, true); - // gpio_setPinOutputBool(24, false); - // gpio_setPinOutputBool(25, true); - // print(); - // gpio_setPinOutputBool(25, false); - // while (true) { - // // for (size_t i = 0; i < 5; i++) { - // for (size_t j = 0; j < 10000000000; j++) { - // __asm__("nop"); - // } - // gpio_setPinOutputBool(42, true); - // for (size_t j = 0; j < 10000000000; j++) { - // __asm__("nop"); - // } - // gpio_setPinOutputBool(42, false); - // } - // while (1) uart_update(); // Turn on USB peripheral. vcmailbox_set_power_state(VCMAILBOX_DEVICE_USB_HCD, true); + // Timer 1/1024 second tick + SYSTMR->CS_b.M1 = 1; + SYSTMR->C1 = SYSTMR->CLO + 977; + BP_EnableIRQ(TIMER_1_IRQn); + BP_SetPriority(USB_IRQn, 0x00); BP_ClearPendingIRQ(USB_IRQn); BP_EnableIRQ(USB_IRQn); @@ -115,7 +87,7 @@ void board_init(void) void board_led_write(bool state) { - gpio_setPinOutputBool(42, state); + gpio_setPinOutputBool(LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON)); } uint32_t board_button_read(void) @@ -145,9 +117,12 @@ int board_uart_write(void const * buf, int len) #if CFG_TUSB_OS == OPT_OS_NONE volatile uint32_t system_ticks = 0; -void SysTick_Handler (void) + +void TIMER_1_IRQHandler(void) { system_ticks++; + SYSTMR->C1 += 977; + SYSTMR->CS_b.M1 = 1; } uint32_t board_millis(void) diff --git a/hw/bsp/raspberrypi4/family.mk b/hw/bsp/raspberrypi4/family.mk index 475cfa4ff..c65070a71 100644 --- a/hw/bsp/raspberrypi4/family.mk +++ b/hw/bsp/raspberrypi4/family.mk @@ -48,4 +48,4 @@ $(BUILD)/kernel8.img: $(BUILD)/$(PROJECT).elf # Copy to kernel to netboot drive or SD card # Change destinaation to fit your need flash: $(BUILD)/kernel8.img - @$(CP) $< /home/$(USER)/Documents/code/pi4_tinyusb/boot_cpy + $(CP) $< /home/$(USER)/Documents/code/pi4_tinyusb/boot_cpy -- cgit v1.3.1 From 6cfdf697eba5b2af6ea383c2bed52557d7610893 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 4 Nov 2021 12:42:28 +0700 Subject: add hint/question with ISB --- src/portable/synopsys/dwc2/dwc2_bcm.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/portable/synopsys/dwc2/dwc2_bcm.h b/src/portable/synopsys/dwc2/dwc2_bcm.h index 0263d19ba..fcec0b0d2 100644 --- a/src/portable/synopsys/dwc2/dwc2_bcm.h +++ b/src/portable/synopsys/dwc2/dwc2_bcm.h @@ -47,7 +47,7 @@ static inline void dwc2_dcd_int_enable(uint8_t rhport) { (void) rhport; BP_EnableIRQ(USB_IRQn); - __asm__ volatile("isb"); + __asm__ volatile("isb"); // needed if TIMER1 IRQ is not enabled !? } TU_ATTR_ALWAYS_INLINE @@ -55,7 +55,7 @@ static inline void dwc2_dcd_int_disable (uint8_t rhport) { (void) rhport; BP_DisableIRQ(USB_IRQn); - __asm__ volatile("isb"); + __asm__ volatile("isb"); // needed if TIMER1 IRQ is not enabled !? } static inline void dwc2_remote_wakeup_delay(void) -- cgit v1.3.1 From 8b3708b44f69a50817ffa9e8a5360e587f3e3fe2 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 4 Nov 2021 13:57:03 +0700 Subject: rename l4 board to match other convention --- .../boards/stm32l476_disco/STM32L476VGTx_FLASH.ld | 183 ------------------- hw/bsp/stm32l4/boards/stm32l476_disco/board.h | 139 -------------- hw/bsp/stm32l4/boards/stm32l476_disco/board.mk | 10 -- .../boards/stm32l476disco/STM32L476VGTx_FLASH.ld | 183 +++++++++++++++++++ hw/bsp/stm32l4/boards/stm32l476disco/board.h | 139 ++++++++++++++ hw/bsp/stm32l4/boards/stm32l476disco/board.mk | 10 ++ .../boards/stm32l4p5_nucleo/STM32L4P5ZGTX_FLASH.ld | 200 --------------------- hw/bsp/stm32l4/boards/stm32l4p5_nucleo/board.h | 137 -------------- hw/bsp/stm32l4/boards/stm32l4p5_nucleo/board.mk | 10 -- .../boards/stm32l4p5nucleo/STM32L4P5ZGTX_FLASH.ld | 200 +++++++++++++++++++++ hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.h | 137 ++++++++++++++ hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.mk | 10 ++ .../boards/stm32l4r5_nucleo/STM32L4RXxI_FLASH.ld | 167 ----------------- hw/bsp/stm32l4/boards/stm32l4r5_nucleo/board.h | 137 -------------- hw/bsp/stm32l4/boards/stm32l4r5_nucleo/board.mk | 14 -- .../boards/stm32l4r5nucleo/STM32L4RXxI_FLASH.ld | 167 +++++++++++++++++ hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.h | 137 ++++++++++++++ hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.mk | 14 ++ 18 files changed, 997 insertions(+), 997 deletions(-) delete mode 100644 hw/bsp/stm32l4/boards/stm32l476_disco/STM32L476VGTx_FLASH.ld delete mode 100644 hw/bsp/stm32l4/boards/stm32l476_disco/board.h delete mode 100644 hw/bsp/stm32l4/boards/stm32l476_disco/board.mk create mode 100644 hw/bsp/stm32l4/boards/stm32l476disco/STM32L476VGTx_FLASH.ld create mode 100644 hw/bsp/stm32l4/boards/stm32l476disco/board.h create mode 100644 hw/bsp/stm32l4/boards/stm32l476disco/board.mk delete mode 100644 hw/bsp/stm32l4/boards/stm32l4p5_nucleo/STM32L4P5ZGTX_FLASH.ld delete mode 100644 hw/bsp/stm32l4/boards/stm32l4p5_nucleo/board.h delete mode 100644 hw/bsp/stm32l4/boards/stm32l4p5_nucleo/board.mk create mode 100644 hw/bsp/stm32l4/boards/stm32l4p5nucleo/STM32L4P5ZGTX_FLASH.ld create mode 100644 hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.h create mode 100644 hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.mk delete mode 100644 hw/bsp/stm32l4/boards/stm32l4r5_nucleo/STM32L4RXxI_FLASH.ld delete mode 100644 hw/bsp/stm32l4/boards/stm32l4r5_nucleo/board.h delete mode 100644 hw/bsp/stm32l4/boards/stm32l4r5_nucleo/board.mk create mode 100644 hw/bsp/stm32l4/boards/stm32l4r5nucleo/STM32L4RXxI_FLASH.ld create mode 100644 hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.h create mode 100644 hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.mk diff --git a/hw/bsp/stm32l4/boards/stm32l476_disco/STM32L476VGTx_FLASH.ld b/hw/bsp/stm32l4/boards/stm32l476_disco/STM32L476VGTx_FLASH.ld deleted file mode 100644 index 98f468ac0..000000000 --- a/hw/bsp/stm32l4/boards/stm32l476_disco/STM32L476VGTx_FLASH.ld +++ /dev/null @@ -1,183 +0,0 @@ -/* -***************************************************************************** -** - -** File : LinkerScript.ld -** -** Abstract : Linker script for STM32L476VGTx Device with -** 1024KByte FLASH, 96KByte RAM -** -** Set heap size, stack size and stack location according -** to application requirements. -** -** Set memory bank area and size if external memory is used. -** -** Target : STMicroelectronics STM32 -** -** -** Distribution: The file is distributed as is, without any warranty -** of any kind. -** -** (c)Copyright Ac6. -** You may use this file as-is or modify it according to the needs of your -** project. Distribution of this file (unmodified or modified) is not -** permitted. Ac6 permit registered System Workbench for MCU users the -** rights to distribute the assembled, compiled & linked contents of this -** file as part of an application binary file, provided that it is built -** using the System Workbench for MCU toolchain. -** -***************************************************************************** -*/ - -/* Entry Point */ -ENTRY(Reset_Handler) - -/* Highest address of the user mode stack */ -_estack = 0x20018000; /* end of RAM */ -/* Generate a link error if heap and stack don't fit into RAM */ -_Min_Heap_Size = 0x500; /* required amount of heap */ -_Min_Stack_Size = 0x1000; /* required amount of stack */ - -/* Specify the memory areas */ -MEMORY -{ -FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 1024K -RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 96K -} - -/* Define output sections */ -SECTIONS -{ - /* The startup code goes first into FLASH */ - .isr_vector : - { - . = ALIGN(8); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(8); - } >FLASH - - /* The program code and other data goes into FLASH */ - .text : - { - . = ALIGN(8); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - - KEEP (*(.init)) - KEEP (*(.fini)) - - . = ALIGN(8); - _etext = .; /* define a global symbols at end of code */ - } >FLASH - - /* Constant data goes into FLASH */ - .rodata : - { - . = ALIGN(8); - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - . = ALIGN(8); - } >FLASH - - .ARM.extab : - { - . = ALIGN(8); - *(.ARM.extab* .gnu.linkonce.armextab.*) - . = ALIGN(8); - } >FLASH - .ARM : { - . = ALIGN(8); - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - . = ALIGN(8); - } >FLASH - - .preinit_array : - { - . = ALIGN(8); - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - . = ALIGN(8); - } >FLASH - - .init_array : - { - . = ALIGN(8); - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - . = ALIGN(8); - } >FLASH - .fini_array : - { - . = ALIGN(8); - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - . = ALIGN(8); - } >FLASH - - /* used by the startup to initialize data */ - _sidata = LOADADDR(.data); - - /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : - { - . = ALIGN(8); - _sdata = .; /* create a global symbol at data start */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - - . = ALIGN(8); - _edata = .; /* define a global symbol at data end */ - } >RAM AT> FLASH - - - /* Uninitialized data section */ - . = ALIGN(4); - .bss : - { - /* This is used by the startup in order to initialize the .bss secion */ - _sbss = .; /* define a global symbol at bss start */ - __bss_start__ = _sbss; - *(.bss) - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end */ - __bss_end__ = _ebss; - } >RAM - - /* User_heap_stack section, used to check that there is enough RAM left */ - ._user_heap_stack : - { - . = ALIGN(8); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - . = . + _Min_Heap_Size; - . = . + _Min_Stack_Size; - . = ALIGN(8); - } >RAM - - - - /* Remove information from the standard libraries */ - /DISCARD/ : - { - libc.a ( * ) - libm.a ( * ) - libgcc.a ( * ) - } - - .ARM.attributes 0 : { *(.ARM.attributes) } -} - - diff --git a/hw/bsp/stm32l4/boards/stm32l476_disco/board.h b/hw/bsp/stm32l4/boards/stm32l476_disco/board.h deleted file mode 100644 index 42c657d5e..000000000 --- a/hw/bsp/stm32l4/boards/stm32l476_disco/board.h +++ /dev/null @@ -1,139 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2020, Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#ifndef BOARD_H_ -#define BOARD_H_ - -#ifdef __cplusplus - extern "C" { -#endif - -#define LED_PORT GPIOB -#define LED_PIN GPIO_PIN_2 -#define LED_STATE_ON 1 - -#define BUTTON_PORT GPIOA -#define BUTTON_PIN GPIO_PIN_0 -#define BUTTON_STATE_ACTIVE 1 - -#define UART_DEV USART2 -#define UART_CLK_EN __HAL_RCC_USART2_CLK_ENABLE -#define UART_GPIO_PORT GPIOD -#define UART_GPIO_AF GPIO_AF7_USART2 -#define UART_TX_PIN GPIO_PIN_5 -#define UART_RX_PIN GPIO_PIN_6 - -//--------------------------------------------------------------------+ -// RCC Clock -//--------------------------------------------------------------------+ - -/** - * @brief System Clock Configuration - * The system Clock is configured as follow : - * - * If define USB_USE_LSE_MSI_CLOCK enabled: - * System Clock source = PLL (MSI) - * SYSCLK(Hz) = 80000000 - * HCLK(Hz) = 80000000 - * AHB Prescaler = 1 - * APB1 Prescaler = 1 - * APB2 Prescaler = 2 - * MSI Frequency(Hz) = 4800000 - * LSE Frequency(Hz) = 32768 - * PLL_M = 6 - * PLL_N = 40 - * PLL_P = 7 - * PLL_Q = 4 - * PLL_R = 4 - * Flash Latency(WS) = 4 - * @param None - * @retval None - */ -static inline void board_clock_init(void) -{ - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; - - /* Enable the LSE Oscillator */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.LSEState = RCC_LSE_ON; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; - HAL_RCC_OscConfig(&RCC_OscInitStruct); - - /* Enable the CSS interrupt in case LSE signal is corrupted or not present */ - HAL_RCCEx_DisableLSECSS(); - - /* Set tick interrupt priority, default HAL value is intentionally invalid - and that prevents PLL initialization in HAL_RCC_OscConfig() */ - HAL_InitTick((1UL << __NVIC_PRIO_BITS) - 1UL); - - /* Enable MSI Oscillator and activate PLL with MSI as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; - RCC_OscInitStruct.MSIState = RCC_MSI_ON; - RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; - RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; - RCC_OscInitStruct.PLL.PLLM = 6; - RCC_OscInitStruct.PLL.PLLN = 40; - RCC_OscInitStruct.PLL.PLLP = 7; - RCC_OscInitStruct.PLL.PLLQ = 4; - RCC_OscInitStruct.PLL.PLLR = 4; - HAL_RCC_OscConfig(&RCC_OscInitStruct); - - /* Enable MSI Auto-calibration through LSE */ - HAL_RCCEx_EnableMSIPLLMode(); - - /* Select MSI output as USB clock source */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; - PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; - HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 - clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; - HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4); -} - -static inline void board_vbus_sense_init(void) -{ - // L476Disco use general GPIO PC11 for VBUS sensing instead of dedicated PA9 as others - // Disable VBUS Sense and force device mode - USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN; - - USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN | USB_OTG_GOTGCTL_BVALOVAL; -} - -#ifdef __cplusplus - } -#endif - -#endif /* BOARD_H_ */ diff --git a/hw/bsp/stm32l4/boards/stm32l476_disco/board.mk b/hw/bsp/stm32l4/boards/stm32l476_disco/board.mk deleted file mode 100644 index e7b8557a5..000000000 --- a/hw/bsp/stm32l4/boards/stm32l476_disco/board.mk +++ /dev/null @@ -1,10 +0,0 @@ -CFLAGS += \ - -DSTM32L476xx \ - -# All source paths should be relative to the top level. -LD_FILE = $(BOARD_PATH)/STM32L476VGTx_FLASH.ld - -SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l476xx.s - -# For flash-jlink target -JLINK_DEVICE = stm32l476vg diff --git a/hw/bsp/stm32l4/boards/stm32l476disco/STM32L476VGTx_FLASH.ld b/hw/bsp/stm32l4/boards/stm32l476disco/STM32L476VGTx_FLASH.ld new file mode 100644 index 000000000..98f468ac0 --- /dev/null +++ b/hw/bsp/stm32l4/boards/stm32l476disco/STM32L476VGTx_FLASH.ld @@ -0,0 +1,183 @@ +/* +***************************************************************************** +** + +** File : LinkerScript.ld +** +** Abstract : Linker script for STM32L476VGTx Device with +** 1024KByte FLASH, 96KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +** (c)Copyright Ac6. +** You may use this file as-is or modify it according to the needs of your +** project. Distribution of this file (unmodified or modified) is not +** permitted. Ac6 permit registered System Workbench for MCU users the +** rights to distribute the assembled, compiled & linked contents of this +** file as part of an application binary file, provided that it is built +** using the System Workbench for MCU toolchain. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20018000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x500; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 1024K +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 96K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(8); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(8); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(8); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(8); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(8); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(8); + } >FLASH + + .ARM.extab : + { + . = ALIGN(8); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(8); + } >FLASH + .ARM : { + . = ALIGN(8); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(8); + } >FLASH + + .preinit_array : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(8); + } >FLASH + + .init_array : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(8); + } >FLASH + .fini_array : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(8); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(8); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(8); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/hw/bsp/stm32l4/boards/stm32l476disco/board.h b/hw/bsp/stm32l4/boards/stm32l476disco/board.h new file mode 100644 index 000000000..42c657d5e --- /dev/null +++ b/hw/bsp/stm32l4/boards/stm32l476disco/board.h @@ -0,0 +1,139 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#define LED_PORT GPIOB +#define LED_PIN GPIO_PIN_2 +#define LED_STATE_ON 1 + +#define BUTTON_PORT GPIOA +#define BUTTON_PIN GPIO_PIN_0 +#define BUTTON_STATE_ACTIVE 1 + +#define UART_DEV USART2 +#define UART_CLK_EN __HAL_RCC_USART2_CLK_ENABLE +#define UART_GPIO_PORT GPIOD +#define UART_GPIO_AF GPIO_AF7_USART2 +#define UART_TX_PIN GPIO_PIN_5 +#define UART_RX_PIN GPIO_PIN_6 + +//--------------------------------------------------------------------+ +// RCC Clock +//--------------------------------------------------------------------+ + +/** + * @brief System Clock Configuration + * The system Clock is configured as follow : + * + * If define USB_USE_LSE_MSI_CLOCK enabled: + * System Clock source = PLL (MSI) + * SYSCLK(Hz) = 80000000 + * HCLK(Hz) = 80000000 + * AHB Prescaler = 1 + * APB1 Prescaler = 1 + * APB2 Prescaler = 2 + * MSI Frequency(Hz) = 4800000 + * LSE Frequency(Hz) = 32768 + * PLL_M = 6 + * PLL_N = 40 + * PLL_P = 7 + * PLL_Q = 4 + * PLL_R = 4 + * Flash Latency(WS) = 4 + * @param None + * @retval None + */ +static inline void board_clock_init(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; + + /* Enable the LSE Oscillator */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + /* Enable the CSS interrupt in case LSE signal is corrupted or not present */ + HAL_RCCEx_DisableLSECSS(); + + /* Set tick interrupt priority, default HAL value is intentionally invalid + and that prevents PLL initialization in HAL_RCC_OscConfig() */ + HAL_InitTick((1UL << __NVIC_PRIO_BITS) - 1UL); + + /* Enable MSI Oscillator and activate PLL with MSI as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.MSIState = RCC_MSI_ON; + RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; + RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; + RCC_OscInitStruct.PLL.PLLM = 6; + RCC_OscInitStruct.PLL.PLLN = 40; + RCC_OscInitStruct.PLL.PLLP = 7; + RCC_OscInitStruct.PLL.PLLQ = 4; + RCC_OscInitStruct.PLL.PLLR = 4; + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + /* Enable MSI Auto-calibration through LSE */ + HAL_RCCEx_EnableMSIPLLMode(); + + /* Select MSI output as USB clock source */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 + clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4); +} + +static inline void board_vbus_sense_init(void) +{ + // L476Disco use general GPIO PC11 for VBUS sensing instead of dedicated PA9 as others + // Disable VBUS Sense and force device mode + USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN; + + USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN | USB_OTG_GOTGCTL_BVALOVAL; +} + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/stm32l4/boards/stm32l476disco/board.mk b/hw/bsp/stm32l4/boards/stm32l476disco/board.mk new file mode 100644 index 000000000..e7b8557a5 --- /dev/null +++ b/hw/bsp/stm32l4/boards/stm32l476disco/board.mk @@ -0,0 +1,10 @@ +CFLAGS += \ + -DSTM32L476xx \ + +# All source paths should be relative to the top level. +LD_FILE = $(BOARD_PATH)/STM32L476VGTx_FLASH.ld + +SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l476xx.s + +# For flash-jlink target +JLINK_DEVICE = stm32l476vg diff --git a/hw/bsp/stm32l4/boards/stm32l4p5_nucleo/STM32L4P5ZGTX_FLASH.ld b/hw/bsp/stm32l4/boards/stm32l4p5_nucleo/STM32L4P5ZGTX_FLASH.ld deleted file mode 100644 index c1a490a70..000000000 --- a/hw/bsp/stm32l4/boards/stm32l4p5_nucleo/STM32L4P5ZGTX_FLASH.ld +++ /dev/null @@ -1,200 +0,0 @@ -/* -****************************************************************************** -** -** File : LinkerScript.ld -** -** Author : Auto-generated by STM32CubeIDE -** -** Abstract : Linker script for STM32L4P5ZGTx Device from STM32L4PLUS series -** 1024Kbytes ROM -** 320Kbytes RAM -** -** Set heap size, stack size and stack location according -** to application requirements. -** -** Set memory bank area and size if external memory is used. -** -** Target : STMicroelectronics STM32 -** -** Distribution: The file is distributed as is without any warranty -** of any kind. -** -***************************************************************************** -** @attention -** -**

© COPYRIGHT(c) 2019 STMicroelectronics

-** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** 1. Redistributions of source code must retain the above copyright notice, -** this list of conditions and the following disclaimer. -** 2. Redistributions in binary form must reproduce the above copyright notice, -** this list of conditions and the following disclaimer in the documentation -** and/or other materials provided with the distribution. -** 3. Neither the name of STMicroelectronics nor the names of its contributors -** may be used to endorse or promote products derived from this software -** without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -***************************************************************************** -*/ - -/* Entry Point */ -ENTRY(Reset_Handler) - -/* Highest address of the user mode stack */ -_estack = ORIGIN(RAM) + 0x0001FFFF; /* end of "SRAM1" Ram type memory */ - -_Min_Heap_Size = 0x200; /* required amount of heap */ -_Min_Stack_Size = 0x400; /* required amount of stack */ - -/* Memories definition */ -MEMORY -{ - RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 320K - ROM (rx) : ORIGIN = 0x08000000, LENGTH = 1024K -} - -/* Sections */ -SECTIONS -{ - /* The startup code into "ROM" Rom type memory */ - .isr_vector : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } >ROM - - /* The program code and other data into "ROM" Rom type memory */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - - KEEP (*(.init)) - KEEP (*(.fini)) - - . = ALIGN(4); - _etext = .; /* define a global symbols at end of code */ - } >ROM - - /* Constant data into "ROM" Rom type memory */ - .rodata : - { - . = ALIGN(4); - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - . = ALIGN(4); - } >ROM - - .ARM.extab : { - . = ALIGN(4); - *(.ARM.extab* .gnu.linkonce.armextab.*) - . = ALIGN(4); - } >ROM - - .ARM : { - . = ALIGN(4); - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - . = ALIGN(4); - } >ROM - - .preinit_array : - { - . = ALIGN(4); - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - . = ALIGN(4); - } >ROM - - .init_array : - { - . = ALIGN(4); - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - . = ALIGN(4); - } >ROM - - .fini_array : - { - . = ALIGN(4); - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - . = ALIGN(4); - } >ROM - - /* Used by the startup to initialize data */ - _sidata = LOADADDR(.data); - - /* Initialized data sections into "RAM" Ram type memory */ - .data : - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end */ - - } >RAM AT> ROM - - /* Uninitialized data section into "RAM" Ram type memory */ - . = ALIGN(4); - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - _sbss = .; /* define a global symbol at bss start */ - __bss_start__ = _sbss; - *(.bss) - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end */ - __bss_end__ = _ebss; - } >RAM - - /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ - ._user_heap_stack : - { - . = ALIGN(8); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - . = . + _Min_Heap_Size; - . = . + _Min_Stack_Size; - . = ALIGN(8); - } >RAM - - /* Remove information from the compiler libraries */ - /DISCARD/ : - { - libc.a ( * ) - libm.a ( * ) - libgcc.a ( * ) - } - - .ARM.attributes 0 : { *(.ARM.attributes) } -} diff --git a/hw/bsp/stm32l4/boards/stm32l4p5_nucleo/board.h b/hw/bsp/stm32l4/boards/stm32l4p5_nucleo/board.h deleted file mode 100644 index 1df389aed..000000000 --- a/hw/bsp/stm32l4/boards/stm32l4p5_nucleo/board.h +++ /dev/null @@ -1,137 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2020, Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#ifndef BOARD_H_ -#define BOARD_H_ - -#ifdef __cplusplus - extern "C" { -#endif - -#define LED_PORT GPIOB -#define LED_PIN GPIO_PIN_14 -#define LED_STATE_ON 1 - -#define BUTTON_PORT GPIOC -#define BUTTON_PIN GPIO_PIN_13 -#define BUTTON_STATE_ACTIVE 1 - -#define UART_DEV LPUART1 -#define UART_CLK_EN __HAL_RCC_LPUART1_CLK_ENABLE -#define UART_GPIO_PORT GPIOG -#define UART_GPIO_AF GPIO_AF8_LPUART1 -#define UART_TX_PIN GPIO_PIN_7 -#define UART_RX_PIN GPIO_PIN_8 - -//--------------------------------------------------------------------+ -// RCC Clock -//--------------------------------------------------------------------+ - -/** - * @brief System Clock Configuration - * The system Clock is configured as follow : - * System Clock source = PLL (MSI) - * SYSCLK(Hz) = 120000000 - * HCLK(Hz) = 120000000 - * AHB Prescaler = 1 - * APB1 Prescaler = 1 - * APB2 Prescaler = 1 - * MSI Frequency(Hz) = 48000000 - * PLL_M = 12 - * PLL_N = 60 - * PLL_P = 2 - * PLL_Q = 2 - * VDD(V) = 3.3 - * Main regulator output voltage = Scale1 mode - * Flash Latency(WS) = 5 - * The USB clock configuration from PLLSAI: - * PLLSAIP = 8 FIXME - * PLLSAIN = 384 FIXME - * PLLSAIQ = 7 FIXME - * @param None - * @retval None - */ - -static inline void board_clock_init(void) -{ - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - - /* Activate PLL with MSI , stabilizied via PLL by LSE */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI; - RCC_OscInitStruct.MSIState = RCC_MSI_ON; - RCC_OscInitStruct.LSEState = RCC_LSE_ON; - RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; - RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; - RCC_OscInitStruct.PLL.PLLM = 12; - RCC_OscInitStruct.PLL.PLLN = 60; - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - RCC_OscInitStruct.PLL.PLLQ = 2; - HAL_RCC_OscConfig(&RCC_OscInitStruct); - - /* Enable MSI Auto-calibration through LSE */ - HAL_RCCEx_EnableMSIPLLMode(); - - /* Select MSI output as USB clock source */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; - PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; - HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); - - /* Select MSI output as USB clock source */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; - PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1; - HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 - clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - // Avoid overshoot and start with HCLK 60 MHz - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV2; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; - HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3); - - /* AHB prescaler divider at 1 as second step */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5); -} - -static inline void board_vbus_sense_init(void) -{ - // Enable VBUS sense (B device) via pin PA9 - USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN; -} - -#ifdef __cplusplus - } -#endif - -#endif /* BOARD_H_ */ diff --git a/hw/bsp/stm32l4/boards/stm32l4p5_nucleo/board.mk b/hw/bsp/stm32l4/boards/stm32l4p5_nucleo/board.mk deleted file mode 100644 index 8252dd838..000000000 --- a/hw/bsp/stm32l4/boards/stm32l4p5_nucleo/board.mk +++ /dev/null @@ -1,10 +0,0 @@ -CFLAGS += \ - -DSTM32L4P5xx \ - -# All source paths should be relative to the top level. -LD_FILE = $(BOARD_PATH)/STM32L4P5ZGTX_FLASH.ld - -SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l4p5xx.s - -# For flash-jlink target -JLINK_DEVICE = stm32l4p5zg diff --git a/hw/bsp/stm32l4/boards/stm32l4p5nucleo/STM32L4P5ZGTX_FLASH.ld b/hw/bsp/stm32l4/boards/stm32l4p5nucleo/STM32L4P5ZGTX_FLASH.ld new file mode 100644 index 000000000..c1a490a70 --- /dev/null +++ b/hw/bsp/stm32l4/boards/stm32l4p5nucleo/STM32L4P5ZGTX_FLASH.ld @@ -0,0 +1,200 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld +** +** Author : Auto-generated by STM32CubeIDE +** +** Abstract : Linker script for STM32L4P5ZGTx Device from STM32L4PLUS series +** 1024Kbytes ROM +** 320Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is without any warranty +** of any kind. +** +***************************************************************************** +** @attention +** +**

© COPYRIGHT(c) 2019 STMicroelectronics

+** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** 1. Redistributions of source code must retain the above copyright notice, +** this list of conditions and the following disclaimer. +** 2. Redistributions in binary form must reproduce the above copyright notice, +** this list of conditions and the following disclaimer in the documentation +** and/or other materials provided with the distribution. +** 3. Neither the name of STMicroelectronics nor the names of its contributors +** may be used to endorse or promote products derived from this software +** without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + 0x0001FFFF; /* end of "SRAM1" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 320K + ROM (rx) : ORIGIN = 0x08000000, LENGTH = 1024K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "ROM" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >ROM + + /* The program code and other data into "ROM" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >ROM + + /* Constant data into "ROM" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >ROM + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >ROM + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >ROM + + .preinit_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >ROM + + .init_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >ROM + + .fini_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >ROM + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> ROM + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.h b/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.h new file mode 100644 index 000000000..1df389aed --- /dev/null +++ b/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.h @@ -0,0 +1,137 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#define LED_PORT GPIOB +#define LED_PIN GPIO_PIN_14 +#define LED_STATE_ON 1 + +#define BUTTON_PORT GPIOC +#define BUTTON_PIN GPIO_PIN_13 +#define BUTTON_STATE_ACTIVE 1 + +#define UART_DEV LPUART1 +#define UART_CLK_EN __HAL_RCC_LPUART1_CLK_ENABLE +#define UART_GPIO_PORT GPIOG +#define UART_GPIO_AF GPIO_AF8_LPUART1 +#define UART_TX_PIN GPIO_PIN_7 +#define UART_RX_PIN GPIO_PIN_8 + +//--------------------------------------------------------------------+ +// RCC Clock +//--------------------------------------------------------------------+ + +/** + * @brief System Clock Configuration + * The system Clock is configured as follow : + * System Clock source = PLL (MSI) + * SYSCLK(Hz) = 120000000 + * HCLK(Hz) = 120000000 + * AHB Prescaler = 1 + * APB1 Prescaler = 1 + * APB2 Prescaler = 1 + * MSI Frequency(Hz) = 48000000 + * PLL_M = 12 + * PLL_N = 60 + * PLL_P = 2 + * PLL_Q = 2 + * VDD(V) = 3.3 + * Main regulator output voltage = Scale1 mode + * Flash Latency(WS) = 5 + * The USB clock configuration from PLLSAI: + * PLLSAIP = 8 FIXME + * PLLSAIN = 384 FIXME + * PLLSAIQ = 7 FIXME + * @param None + * @retval None + */ + +static inline void board_clock_init(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + /* Activate PLL with MSI , stabilizied via PLL by LSE */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.MSIState = RCC_MSI_ON; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; + RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; + RCC_OscInitStruct.PLL.PLLM = 12; + RCC_OscInitStruct.PLL.PLLN = 60; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 2; + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + /* Enable MSI Auto-calibration through LSE */ + HAL_RCCEx_EnableMSIPLLMode(); + + /* Select MSI output as USB clock source */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + + /* Select MSI output as USB clock source */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1; + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 + clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + // Avoid overshoot and start with HCLK 60 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV2; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3); + + /* AHB prescaler divider at 1 as second step */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5); +} + +static inline void board_vbus_sense_init(void) +{ + // Enable VBUS sense (B device) via pin PA9 + USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN; +} + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.mk b/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.mk new file mode 100644 index 000000000..8252dd838 --- /dev/null +++ b/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.mk @@ -0,0 +1,10 @@ +CFLAGS += \ + -DSTM32L4P5xx \ + +# All source paths should be relative to the top level. +LD_FILE = $(BOARD_PATH)/STM32L4P5ZGTX_FLASH.ld + +SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l4p5xx.s + +# For flash-jlink target +JLINK_DEVICE = stm32l4p5zg diff --git a/hw/bsp/stm32l4/boards/stm32l4r5_nucleo/STM32L4RXxI_FLASH.ld b/hw/bsp/stm32l4/boards/stm32l4r5_nucleo/STM32L4RXxI_FLASH.ld deleted file mode 100644 index f93a16041..000000000 --- a/hw/bsp/stm32l4/boards/stm32l4r5_nucleo/STM32L4RXxI_FLASH.ld +++ /dev/null @@ -1,167 +0,0 @@ -/* -***************************************************************************** -** - -** File : LinkerScript.ld -** -** Abstract : Linker script for STM32L4RxI Device with -** 2048KByte FLASH, 640KByte RAM -** -** Set heap size, stack size and stack location according -** to application requirements. -** -** Set memory bank area and size if external memory is used. -** -** Target : STMicroelectronics STM32 -** -** -** Distribution: The file is distributed as is, without any warranty -** of any kind. -** -** (c)Copyright Ac6. -** You may use this file as-is or modify it according to the needs of your -** project. Distribution of this file (unmodified or modified) is not -** permitted. Ac6 permit registered System Workbench for MCU users the -** rights to distribute the assembled, compiled & linked contents of this -** file as part of an application binary file, provided that it is built -** using the System Workbench for MCU toolchain. -** -***************************************************************************** -*/ - -/* Entry Point */ -ENTRY(Reset_Handler) - -/* Highest address of the user mode stack */ -_estack = 0x200a0000; /* end of RAM */ -/* Generate a link error if heap and stack don't fit into RAM */ -_Min_Heap_Size = 0x200; /* required amount of heap */ -_Min_Stack_Size = 0x460; /* required amount of stack */ - -/* Specify the memory areas */ -MEMORY -{ -RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 640K -FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 2048K -} - -/* Define output sections */ -SECTIONS -{ - /* The startup code goes first into FLASH */ - .isr_vector : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } >FLASH - - /* The program code and other data goes into FLASH */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - - KEEP (*(.init)) - KEEP (*(.fini)) - - . = ALIGN(4); - _etext = .; /* define a global symbols at end of code */ - } >FLASH - - /* Constant data goes into FLASH */ - .rodata : - { - . = ALIGN(4); - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - . = ALIGN(4); - } >FLASH - - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } >FLASH - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } >FLASH - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } >FLASH - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } >FLASH - - /* used by the startup to initialize data */ - _sidata = LOADADDR(.data); - - /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end */ - } >RAM AT> FLASH - - - /* Uninitialized data section */ - . = ALIGN(4); - .bss : - { - /* This is used by the startup in order to initialize the .bss secion */ - _sbss = .; /* define a global symbol at bss start */ - __bss_start__ = _sbss; - *(.bss) - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end */ - __bss_end__ = _ebss; - } >RAM - - /* User_heap_stack section, used to check that there is enough RAM left */ - ._user_heap_stack : - { - . = ALIGN(8); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - . = . + _Min_Heap_Size; - . = . + _Min_Stack_Size; - . = ALIGN(8); - } >RAM - - - - /* Remove information from the standard libraries */ - /DISCARD/ : - { - libc.a ( * ) - libm.a ( * ) - libgcc.a ( * ) - } - - .ARM.attributes 0 : { *(.ARM.attributes) } -} diff --git a/hw/bsp/stm32l4/boards/stm32l4r5_nucleo/board.h b/hw/bsp/stm32l4/boards/stm32l4r5_nucleo/board.h deleted file mode 100644 index 1df389aed..000000000 --- a/hw/bsp/stm32l4/boards/stm32l4r5_nucleo/board.h +++ /dev/null @@ -1,137 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2020, Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#ifndef BOARD_H_ -#define BOARD_H_ - -#ifdef __cplusplus - extern "C" { -#endif - -#define LED_PORT GPIOB -#define LED_PIN GPIO_PIN_14 -#define LED_STATE_ON 1 - -#define BUTTON_PORT GPIOC -#define BUTTON_PIN GPIO_PIN_13 -#define BUTTON_STATE_ACTIVE 1 - -#define UART_DEV LPUART1 -#define UART_CLK_EN __HAL_RCC_LPUART1_CLK_ENABLE -#define UART_GPIO_PORT GPIOG -#define UART_GPIO_AF GPIO_AF8_LPUART1 -#define UART_TX_PIN GPIO_PIN_7 -#define UART_RX_PIN GPIO_PIN_8 - -//--------------------------------------------------------------------+ -// RCC Clock -//--------------------------------------------------------------------+ - -/** - * @brief System Clock Configuration - * The system Clock is configured as follow : - * System Clock source = PLL (MSI) - * SYSCLK(Hz) = 120000000 - * HCLK(Hz) = 120000000 - * AHB Prescaler = 1 - * APB1 Prescaler = 1 - * APB2 Prescaler = 1 - * MSI Frequency(Hz) = 48000000 - * PLL_M = 12 - * PLL_N = 60 - * PLL_P = 2 - * PLL_Q = 2 - * VDD(V) = 3.3 - * Main regulator output voltage = Scale1 mode - * Flash Latency(WS) = 5 - * The USB clock configuration from PLLSAI: - * PLLSAIP = 8 FIXME - * PLLSAIN = 384 FIXME - * PLLSAIQ = 7 FIXME - * @param None - * @retval None - */ - -static inline void board_clock_init(void) -{ - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - - /* Activate PLL with MSI , stabilizied via PLL by LSE */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI; - RCC_OscInitStruct.MSIState = RCC_MSI_ON; - RCC_OscInitStruct.LSEState = RCC_LSE_ON; - RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; - RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; - RCC_OscInitStruct.PLL.PLLM = 12; - RCC_OscInitStruct.PLL.PLLN = 60; - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - RCC_OscInitStruct.PLL.PLLQ = 2; - HAL_RCC_OscConfig(&RCC_OscInitStruct); - - /* Enable MSI Auto-calibration through LSE */ - HAL_RCCEx_EnableMSIPLLMode(); - - /* Select MSI output as USB clock source */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; - PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; - HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); - - /* Select MSI output as USB clock source */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; - PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1; - HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 - clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - // Avoid overshoot and start with HCLK 60 MHz - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV2; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; - HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3); - - /* AHB prescaler divider at 1 as second step */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5); -} - -static inline void board_vbus_sense_init(void) -{ - // Enable VBUS sense (B device) via pin PA9 - USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN; -} - -#ifdef __cplusplus - } -#endif - -#endif /* BOARD_H_ */ diff --git a/hw/bsp/stm32l4/boards/stm32l4r5_nucleo/board.mk b/hw/bsp/stm32l4/boards/stm32l4r5_nucleo/board.mk deleted file mode 100644 index 3d7fa227b..000000000 --- a/hw/bsp/stm32l4/boards/stm32l4r5_nucleo/board.mk +++ /dev/null @@ -1,14 +0,0 @@ -CFLAGS += \ - -DHSE_VALUE=8000000 \ - -DSTM32L4R5xx \ - -# All source paths should be relative to the top level. -LD_FILE = $(BOARD_PATH)/STM32L4RXxI_FLASH.ld - -SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l4r5xx.s - -# For flash-jlink target -JLINK_DEVICE = stm32l4r5zi - -# flash target using on-board stlink -flash: flash-stlink diff --git a/hw/bsp/stm32l4/boards/stm32l4r5nucleo/STM32L4RXxI_FLASH.ld b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/STM32L4RXxI_FLASH.ld new file mode 100644 index 000000000..f93a16041 --- /dev/null +++ b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/STM32L4RXxI_FLASH.ld @@ -0,0 +1,167 @@ +/* +***************************************************************************** +** + +** File : LinkerScript.ld +** +** Abstract : Linker script for STM32L4RxI Device with +** 2048KByte FLASH, 640KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +** (c)Copyright Ac6. +** You may use this file as-is or modify it according to the needs of your +** project. Distribution of this file (unmodified or modified) is not +** permitted. Ac6 permit registered System Workbench for MCU users the +** rights to distribute the assembled, compiled & linked contents of this +** file as part of an application binary file, provided that it is built +** using the System Workbench for MCU toolchain. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x200a0000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x460; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 640K +FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 2048K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.h b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.h new file mode 100644 index 000000000..1df389aed --- /dev/null +++ b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.h @@ -0,0 +1,137 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#define LED_PORT GPIOB +#define LED_PIN GPIO_PIN_14 +#define LED_STATE_ON 1 + +#define BUTTON_PORT GPIOC +#define BUTTON_PIN GPIO_PIN_13 +#define BUTTON_STATE_ACTIVE 1 + +#define UART_DEV LPUART1 +#define UART_CLK_EN __HAL_RCC_LPUART1_CLK_ENABLE +#define UART_GPIO_PORT GPIOG +#define UART_GPIO_AF GPIO_AF8_LPUART1 +#define UART_TX_PIN GPIO_PIN_7 +#define UART_RX_PIN GPIO_PIN_8 + +//--------------------------------------------------------------------+ +// RCC Clock +//--------------------------------------------------------------------+ + +/** + * @brief System Clock Configuration + * The system Clock is configured as follow : + * System Clock source = PLL (MSI) + * SYSCLK(Hz) = 120000000 + * HCLK(Hz) = 120000000 + * AHB Prescaler = 1 + * APB1 Prescaler = 1 + * APB2 Prescaler = 1 + * MSI Frequency(Hz) = 48000000 + * PLL_M = 12 + * PLL_N = 60 + * PLL_P = 2 + * PLL_Q = 2 + * VDD(V) = 3.3 + * Main regulator output voltage = Scale1 mode + * Flash Latency(WS) = 5 + * The USB clock configuration from PLLSAI: + * PLLSAIP = 8 FIXME + * PLLSAIN = 384 FIXME + * PLLSAIQ = 7 FIXME + * @param None + * @retval None + */ + +static inline void board_clock_init(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + /* Activate PLL with MSI , stabilizied via PLL by LSE */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.MSIState = RCC_MSI_ON; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; + RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; + RCC_OscInitStruct.PLL.PLLM = 12; + RCC_OscInitStruct.PLL.PLLN = 60; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 2; + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + /* Enable MSI Auto-calibration through LSE */ + HAL_RCCEx_EnableMSIPLLMode(); + + /* Select MSI output as USB clock source */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + + /* Select MSI output as USB clock source */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1; + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 + clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + // Avoid overshoot and start with HCLK 60 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV2; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3); + + /* AHB prescaler divider at 1 as second step */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5); +} + +static inline void board_vbus_sense_init(void) +{ + // Enable VBUS sense (B device) via pin PA9 + USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN; +} + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.mk b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.mk new file mode 100644 index 000000000..3d7fa227b --- /dev/null +++ b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.mk @@ -0,0 +1,14 @@ +CFLAGS += \ + -DHSE_VALUE=8000000 \ + -DSTM32L4R5xx \ + +# All source paths should be relative to the top level. +LD_FILE = $(BOARD_PATH)/STM32L4RXxI_FLASH.ld + +SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l4r5xx.s + +# For flash-jlink target +JLINK_DEVICE = stm32l4r5zi + +# flash target using on-board stlink +flash: flash-stlink -- cgit v1.3.1 From f90f5ea3699facfd5681c3bf21e0500f169f8f07 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 4 Nov 2021 16:16:51 +0700 Subject: adding g4 family with g474nucleo, able to blink led and button --- hw/bsp/stm32f7/boards/stm32f746nucleo/board.h | 2 + .../boards/stm32g474nucleo/STM32G474RETx_FLASH.ld | 190 ++++++++++ hw/bsp/stm32g4/boards/stm32g474nucleo/board.h | 95 +++++ hw/bsp/stm32g4/boards/stm32g474nucleo/board.mk | 8 + hw/bsp/stm32g4/family.c | 173 ++++++++++ hw/bsp/stm32g4/family.mk | 44 +++ hw/bsp/stm32g4/stm32g4xx_hal_conf.h | 381 +++++++++++++++++++++ src/device/dcd_attr.h | 3 + src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 16 +- .../st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h | 4 + src/tusb_option.h | 22 +- 11 files changed, 927 insertions(+), 11 deletions(-) create mode 100644 hw/bsp/stm32g4/boards/stm32g474nucleo/STM32G474RETx_FLASH.ld create mode 100644 hw/bsp/stm32g4/boards/stm32g474nucleo/board.h create mode 100644 hw/bsp/stm32g4/boards/stm32g474nucleo/board.mk create mode 100644 hw/bsp/stm32g4/family.c create mode 100644 hw/bsp/stm32g4/family.mk create mode 100644 hw/bsp/stm32g4/stm32g4xx_hal_conf.h diff --git a/hw/bsp/stm32f7/boards/stm32f746nucleo/board.h b/hw/bsp/stm32f7/boards/stm32f746nucleo/board.h index 093445ede..92c109a72 100644 --- a/hw/bsp/stm32f7/boards/stm32f746nucleo/board.h +++ b/hw/bsp/stm32f7/boards/stm32f746nucleo/board.h @@ -76,6 +76,8 @@ static inline void board_clock_init(void) RCC_OscInitStruct.PLL.PLLQ = 9; HAL_RCC_OscConfig(&RCC_OscInitStruct); + // TODO need to enable usb clock source + /* Activate the OverDrive to reach the 216 MHz Frequency */ HAL_PWREx_EnableOverDrive(); diff --git a/hw/bsp/stm32g4/boards/stm32g474nucleo/STM32G474RETx_FLASH.ld b/hw/bsp/stm32g4/boards/stm32g474nucleo/STM32G474RETx_FLASH.ld new file mode 100644 index 000000000..935d97c87 --- /dev/null +++ b/hw/bsp/stm32g4/boards/stm32g474nucleo/STM32G474RETx_FLASH.ld @@ -0,0 +1,190 @@ +/* +****************************************************************************** +** + +** File : LinkerScript.ld +** +** Author : Auto-generated by Ac6 System Workbench +** +** Abstract : Linker script for STM32G474RETx series +** 512Kbytes FLASH and 160Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +***************************************************************************** +** @attention +** +**

© COPYRIGHT(c) 2014 Ac6

+** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** 1. Redistributions of source code must retain the above copyright notice, +** this list of conditions and the following disclaimer. +** 2. Redistributions in binary form must reproduce the above copyright notice, +** this list of conditions and the following disclaimer in the documentation +** and/or other materials provided with the distribution. +** 3. Neither the name of Ac6 nor the names of its contributors +** may be used to endorse or promote products derived from this software +** without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20020000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K +CCMSRAM (xrw) : ORIGIN = 0x10000000, LENGTH = 32K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h new file mode 100644 index 000000000..8d33373af --- /dev/null +++ b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h @@ -0,0 +1,95 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +// LED +#define LED_PORT GPIOA +#define LED_PIN GPIO_PIN_5 +#define LED_STATE_ON 0 + +// Button +#define BUTTON_PORT GPIOC +#define BUTTON_PIN GPIO_PIN_13 +#define BUTTON_STATE_ACTIVE 1 + +// UART Enable for STLink VCOM +#define UART_DEV LPUART1 +#define UART_CLK_EN __HAL_RCC_LPUART1_CLK_ENABLE +#define UART_GPIO_PORT GPIOA +#define UART_GPIO_AF GPIO_AF12_LPUART1 +#define UART_TX_PIN GPIO_PIN_2 +#define UART_RX_PIN GPIO_PIN_3 + +//--------------------------------------------------------------------+ +// RCC Clock +//--------------------------------------------------------------------+ +static inline void board_clock_init(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + // Configure the main internal regulator output voltage + HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST); + + // Initializes the CPU, AHB and APB busses clocks + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4; + RCC_OscInitStruct.PLL.PLLN = 85; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; + RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + // Initializes the CPU, AHB and APB busses clocks + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_8); +} + +static inline void board_vbus_sense_init(void) +{ + // Enable VBUS sense (B device) via pin PA9 +} + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/stm32g4/boards/stm32g474nucleo/board.mk b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.mk new file mode 100644 index 000000000..1951fcba0 --- /dev/null +++ b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.mk @@ -0,0 +1,8 @@ +CFLAGS += -DSTM32G474xx + +LD_FILE = $(BOARD_PATH)/STM32G474RETx_FLASH.ld + +SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32g474xx.s + +# For flash-jlink target +JLINK_DEVICE = stm32g474re diff --git a/hw/bsp/stm32g4/family.c b/hw/bsp/stm32g4/family.c new file mode 100644 index 000000000..cddd85af0 --- /dev/null +++ b/hw/bsp/stm32g4/family.c @@ -0,0 +1,173 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "stm32g4xx_hal.h" +#include "bsp/board.h" +#include "board.h" + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void OTG_FS_IRQHandler(void) +{ + tud_int_handler(0); +} + +void OTG_HS_IRQHandler(void) +{ + tud_int_handler(1); +} + +//--------------------------------------------------------------------+ +// MACRO TYPEDEF CONSTANT ENUM +//--------------------------------------------------------------------+ +UART_HandleTypeDef UartHandle; + +void board_init(void) +{ + board_clock_init(); + + // Enable All GPIOs clocks + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + + UART_CLK_EN(); + +#if CFG_TUSB_OS == OPT_OS_NONE + // 1ms tick timer + SysTick_Config(SystemCoreClock / 1000); +#elif CFG_TUSB_OS == OPT_OS_FREERTOS + // Explicitly disable systick to prevent its ISR runs before scheduler start + SysTick->CTRL &= ~1U; + + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(OTG_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); +#endif + + GPIO_InitTypeDef GPIO_InitStruct; + + // LED + GPIO_InitStruct.Pin = LED_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct); + + board_led_write(false); + + // Button + GPIO_InitStruct.Pin = BUTTON_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN : GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct); + +#ifdef UART_DEV + // UART + GPIO_InitStruct.Pin = UART_TX_PIN | UART_RX_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + GPIO_InitStruct.Alternate = UART_GPIO_AF; + HAL_GPIO_Init(UART_GPIO_PORT, &GPIO_InitStruct); + + UartHandle = (UART_HandleTypeDef){ + .Instance = UART_DEV, + .Init.BaudRate = CFG_BOARD_UART_BAUDRATE, + .Init.WordLength = UART_WORDLENGTH_8B, + .Init.StopBits = UART_STOPBITS_1, + .Init.Parity = UART_PARITY_NONE, + .Init.HwFlowCtl = UART_HWCONTROL_NONE, + .Init.Mode = UART_MODE_TX_RX, + .Init.OverSampling = UART_OVERSAMPLING_16 + }; + HAL_UART_Init(&UartHandle); +#endif + + // TODO Configure USB GPIOs + + board_vbus_sense_init(); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +void board_led_write(bool state) +{ + HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON)); +} + +uint32_t board_button_read(void) +{ + return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN); +} + +int board_uart_read(uint8_t* buf, int len) +{ + (void) buf; (void) len; + return 0; +} + +int board_uart_write(void const * buf, int len) +{ +#ifdef UART_DEV + HAL_UART_Transmit(&UartHandle, (uint8_t*)(uintptr_t) buf, len, 0xffff); + return len; +#else + (void) buf; (void) len; (void) UartHandle; + return 0; +#endif +} + +#if CFG_TUSB_OS == OPT_OS_NONE +volatile uint32_t system_ticks = 0; +void SysTick_Handler (void) +{ + system_ticks++; +} + +uint32_t board_millis(void) +{ + return system_ticks; +} +#endif + +void HardFault_Handler (void) +{ + asm("bkpt"); +} + +// Required by __libc_init_array in startup code if we are compiling using +// -nostdlib/-nostartfiles. +void _init(void) +{ + +} diff --git a/hw/bsp/stm32g4/family.mk b/hw/bsp/stm32g4/family.mk new file mode 100644 index 000000000..04222f3bb --- /dev/null +++ b/hw/bsp/stm32g4/family.mk @@ -0,0 +1,44 @@ +UF2_FAMILY_ID = 0x4c71240a +ST_FAMILY = g4 +DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver + +ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY) +ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver + +include $(TOP)/$(BOARD_PATH)/board.mk + +CFLAGS += \ + -flto \ + -mthumb \ + -mabi=aapcs \ + -mcpu=cortex-m4 \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -nostdlib -nostartfiles \ + -DCFG_TUSB_MCU=OPT_MCU_STM32G4 + +# suppress warning caused by vendor mcu driver +CFLAGS += -Wno-error=cast-align + +SRC_C += \ + src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \ + $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \ + $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \ + $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \ + $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr_ex.c \ + $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \ + $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \ + $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c \ + $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ + $(TOP)/$(ST_CMSIS)/Include \ + $(TOP)/$(ST_HAL_DRIVER)/Inc + +# For freeRTOS port source +FREERTOS_PORT = ARM_CM4F + +# flash target using on-board stlink +flash: flash-stlink diff --git a/hw/bsp/stm32g4/stm32g4xx_hal_conf.h b/hw/bsp/stm32g4/stm32g4xx_hal_conf.h new file mode 100644 index 000000000..ad5f7dbd4 --- /dev/null +++ b/hw/bsp/stm32g4/stm32g4xx_hal_conf.h @@ -0,0 +1,381 @@ +/** + ****************************************************************************** + * @file stm32g4xx_hal_conf.h + * @author MCD Application Team + * @brief HAL configuration file + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G4xx_HAL_CONF_H +#define STM32G4xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ + +#define HAL_MODULE_ENABLED + + /*#define HAL_ADC_MODULE_ENABLED */ +/*#define HAL_COMP_MODULE_ENABLED */ +/*#define HAL_CORDIC_MODULE_ENABLED */ +/*#define HAL_CRC_MODULE_ENABLED */ +/*#define HAL_CRYP_MODULE_ENABLED */ +/*#define HAL_DAC_MODULE_ENABLED */ +/*#define HAL_FDCAN_MODULE_ENABLED */ +/*#define HAL_FMAC_MODULE_ENABLED */ +/*#define HAL_HRTIM_MODULE_ENABLED */ +/*#define HAL_IRDA_MODULE_ENABLED */ +/*#define HAL_IWDG_MODULE_ENABLED */ +/*#define HAL_I2C_MODULE_ENABLED */ +/*#define HAL_I2S_MODULE_ENABLED */ +/*#define HAL_LPTIM_MODULE_ENABLED */ +/*#define HAL_NAND_MODULE_ENABLED */ +/*#define HAL_NOR_MODULE_ENABLED */ +/*#define HAL_OPAMP_MODULE_ENABLED */ +/*#define HAL_PCD_MODULE_ENABLED */ +/*#define HAL_QSPI_MODULE_ENABLED */ +/*#define HAL_RNG_MODULE_ENABLED */ +/*#define HAL_RTC_MODULE_ENABLED */ +/*#define HAL_SAI_MODULE_ENABLED */ +/*#define HAL_SMARTCARD_MODULE_ENABLED */ +/*#define HAL_SMBUS_MODULE_ENABLED */ +/*#define HAL_SPI_MODULE_ENABLED */ +/*#define HAL_SRAM_MODULE_ENABLED */ +/*#define HAL_TIM_MODULE_ENABLED */ +#define HAL_UART_MODULE_ENABLED +/*#define HAL_USART_MODULE_ENABLED */ +/*#define HAL_WWDG_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## Register Callbacks selection ############################## */ +/** + * @brief This is the list of modules where register callback can be used + */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U +#define USE_HAL_COMP_REGISTER_CALLBACKS 0U +#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U +#define USE_HAL_EXTI_REGISTER_CALLBACKS 0U +#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U +#define USE_HAL_FMAC_REGISTER_CALLBACKS 0U +#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U +#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U +#define USE_HAL_UART_REGISTER_CALLBACKS 0U +#define USE_HAL_USART_REGISTER_CALLBACKS 0U +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE (24000000UL) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI48) value for USB FS and RNG. + * This internal oscillator is mainly dedicated to provide a high precision clock to + * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. + * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency + * which is subject to manufacturing process variations. + */ +#if !defined (HSI48_VALUE) + #define HSI48_VALUE (48000000UL) /*!< Value of the Internal High Speed oscillator for USB FS/RNG in Hz. + The real value my vary depending on manufacturing process variations.*/ +#endif /* HSI48_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) +/*!< Value of the Internal Low Speed oscillator in Hz +The real value may vary depending on the variations in voltage and temperature.*/ +#define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) +#define LSE_VALUE (32768UL) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) +#define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S and SAI peripherals + * This value is used by the I2S and SAI HAL modules to compute the I2S and SAI clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) +#define EXTERNAL_CLOCK_VALUE (12288000UL) /*!< Value of the External oscillator in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ + +#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY (0UL) /*!< tick interrupt priority (lowest by default) */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 0U +#define INSTRUCTION_CACHE_ENABLE 1U +#define DATA_CACHE_ENABLE 1U + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver + * Activated: CRC code is present inside driver + * Deactivated: CRC code cleaned from driver + */ + +#define USE_SPI_CRC 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED +#include "stm32g4xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED +#include "stm32g4xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED +#include "stm32g4xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED +#include "stm32g4xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED +#include "stm32g4xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_COMP_MODULE_ENABLED +#include "stm32g4xx_hal_comp.h" +#endif /* HAL_COMP_MODULE_ENABLED */ + +#ifdef HAL_CORDIC_MODULE_ENABLED +#include "stm32g4xx_hal_cordic.h" +#endif /* HAL_CORDIC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED +#include "stm32g4xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED +#include "stm32g4xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED +#include "stm32g4xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED +#include "stm32g4xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_FDCAN_MODULE_ENABLED +#include "stm32g4xx_hal_fdcan.h" +#endif /* HAL_FDCAN_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED +#include "stm32g4xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_FMAC_MODULE_ENABLED +#include "stm32g4xx_hal_fmac.h" +#endif /* HAL_FMAC_MODULE_ENABLED */ + +#ifdef HAL_HRTIM_MODULE_ENABLED +#include "stm32g4xx_hal_hrtim.h" +#endif /* HAL_HRTIM_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED +#include "stm32g4xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED +#include "stm32g4xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED +#include "stm32g4xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED +#include "stm32g4xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED +#include "stm32g4xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED +#include "stm32g4xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED +#include "stm32g4xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_OPAMP_MODULE_ENABLED +#include "stm32g4xx_hal_opamp.h" +#endif /* HAL_OPAMP_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED +#include "stm32g4xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED +#include "stm32g4xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED +#include "stm32g4xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED +#include "stm32g4xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED +#include "stm32g4xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED +#include "stm32g4xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED +#include "stm32g4xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED +#include "stm32g4xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED +#include "stm32g4xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED +#include "stm32g4xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED +#include "stm32g4xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED +#include "stm32g4xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED +#include "stm32g4xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED +#include "stm32g4xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ +#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ +void assert_failed(uint8_t *file, uint32_t line); +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G4xx_HAL_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/device/dcd_attr.h b/src/device/dcd_attr.h index 952a8b8c8..1d34b94ba 100644 --- a/src/device/dcd_attr.h +++ b/src/device/dcd_attr.h @@ -119,6 +119,9 @@ #define DCD_ATTR_ENDPOINT_MAX 9 #define DCD_ATTR_DWC2_STM32 +#elif TU_CHECK_MCU(OPT_MCU_STM32G4) + #define DCD_ATTR_ENDPOINT_MAX 8 + #elif TU_CHECK_MCU(OPT_MCU_STM32L0, OPT_MCU_STM32L1) #define DCD_ATTR_ENDPOINT_MAX 8 diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index 933f352a2..177a7ad2a 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -110,7 +110,7 @@ #endif #if TUSB_OPT_DEVICE_ENABLED && \ - ( TU_CHECK_MCU(OPT_MCU_STM32F0, OPT_MCU_STM32F3, OPT_MCU_STM32L0, OPT_MCU_STM32L1) || \ + ( TU_CHECK_MCU(OPT_MCU_STM32F0, OPT_MCU_STM32F3, OPT_MCU_STM32L0, OPT_MCU_STM32L1, OPT_MCU_STM32G4) || \ (TU_CHECK_MCU(OPT_MCU_STM32F1) && defined(STM32F1_FSDEV)) \ ) @@ -296,8 +296,10 @@ void dcd_int_enable (uint8_t rhport) __ISB(); #if CFG_TUSB_MCU == OPT_MCU_STM32F0 || CFG_TUSB_MCU == OPT_MCU_STM32L0 NVIC_EnableIRQ(USB_IRQn); + #elif CFG_TUSB_MCU == OPT_MCU_STM32L1 NVIC_EnableIRQ(USB_LP_IRQn); + #elif CFG_TUSB_MCU == OPT_MCU_STM32F3 // Some STM32F302/F303 devices allow to remap the USB interrupt vectors from // shared USB/CAN IRQs to separate CAN and USB IRQs. @@ -320,6 +322,12 @@ void dcd_int_enable (uint8_t rhport) NVIC_EnableIRQ(USB_HP_CAN1_TX_IRQn); NVIC_EnableIRQ(USB_LP_CAN1_RX0_IRQn); NVIC_EnableIRQ(USBWakeUp_IRQn); + +#elif CFG_TUSB_MCU == OPT_MCU_STM32G4 + NVIC_EnableIRQ(USB_HP_IRQn); + NVIC_EnableIRQ(USB_LP_IRQn); + NVIC_EnableIRQ(USBWakeUp_IRQn); + #else #error Unknown arch in USB driver #endif @@ -356,6 +364,12 @@ void dcd_int_disable(uint8_t rhport) NVIC_DisableIRQ(USB_HP_CAN1_TX_IRQn); NVIC_DisableIRQ(USB_LP_CAN1_RX0_IRQn); NVIC_DisableIRQ(USBWakeUp_IRQn); + +#elif CFG_TUSB_MCU == OPT_MCU_STM32G4 + NVIC_DisableIRQ(USB_HP_IRQn); + NVIC_DisableIRQ(USB_LP_IRQn); + NVIC_DisableIRQ(USBWakeUp_IRQn); + #else #error Unknown arch in USB driver #endif diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h index eca8bf575..596f7be6c 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h @@ -87,6 +87,10 @@ #include "stm32l1xx.h" #define PMA_LENGTH (512u) +#elif CFG_TUSB_MCU == OPT_MCU_STM32G4 + #include "stm32g4xx.h" + #define PMA_LENGTH (1024u) + #else #error You are using an untested or unimplemented STM32 variant. Please update the driver. // This includes L1x0, L1x1, L1x2, L4x2 and L4x3, G1x1, G1x3, and G1x4 diff --git a/src/tusb_option.h b/src/tusb_option.h index 4da07e241..c1fc8a71c 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -68,16 +68,18 @@ #define OPT_MCU_SAMX7X 207 ///< MicroChip SAME70, S70, V70, V71 family // STM32 -#define OPT_MCU_STM32F0 300 ///< ST STM32F0 -#define OPT_MCU_STM32F1 301 ///< ST STM32F1 -#define OPT_MCU_STM32F2 302 ///< ST STM32F2 -#define OPT_MCU_STM32F3 303 ///< ST STM32F3 -#define OPT_MCU_STM32F4 304 ///< ST STM32F4 -#define OPT_MCU_STM32F7 305 ///< ST STM32F7 -#define OPT_MCU_STM32H7 306 ///< ST STM32H7 -#define OPT_MCU_STM32L0 307 ///< ST STM32L0 -#define OPT_MCU_STM32L1 308 ///< ST STM32L1 -#define OPT_MCU_STM32L4 309 ///< ST STM32L4 +#define OPT_MCU_STM32F0 300 ///< ST F0 +#define OPT_MCU_STM32F1 301 ///< ST F1 +#define OPT_MCU_STM32F2 302 ///< ST F2 +#define OPT_MCU_STM32F3 303 ///< ST F3 +#define OPT_MCU_STM32F4 304 ///< ST F4 +#define OPT_MCU_STM32F7 305 ///< ST F7 +#define OPT_MCU_STM32H7 306 ///< ST H7 +#define OPT_MCU_STM32L1 308 ///< ST L1 +#define OPT_MCU_STM32L0 307 ///< ST L0 +#define OPT_MCU_STM32L4 309 ///< ST L4 +#define OPT_MCU_STM32G0 310 ///< ST G0 +#define OPT_MCU_STM32G4 311 ///< ST G4 // Sony #define OPT_MCU_CXD56 400 ///< SONY CXD56 -- cgit v1.3.1 From 310f287f4476d22f126c9fc2995f6be7e2b64662 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 4 Nov 2021 17:52:55 +0700 Subject: couldn't get g4 usb clock and pin setup just yet. Leave it as it is for now --- hw/bsp/stm32g4/boards/stm32g474nucleo/board.h | 35 +++++++++++++++++++++++++++ hw/bsp/stm32g4/family.c | 21 +++++++++++++--- 2 files changed, 52 insertions(+), 4 deletions(-) diff --git a/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h index 8d33373af..fd9d50183 100644 --- a/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h +++ b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h @@ -31,6 +31,10 @@ extern "C" { #endif +// G474RE Nucleo does not has usb connection. We need to manually connect +// - PA11 for D+, CN10.14 +// - PA12 for D-, CN10.12 + // LED #define LED_PORT GPIOA #define LED_PIN GPIO_PIN_5 @@ -49,6 +53,7 @@ #define UART_TX_PIN GPIO_PIN_2 #define UART_RX_PIN GPIO_PIN_3 + //--------------------------------------------------------------------+ // RCC Clock //--------------------------------------------------------------------+ @@ -81,6 +86,36 @@ static inline void board_clock_init(void) RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_8); + +#if 0 // TODO need to check if USB clock is enabled + /* Enable HSI48 */ + memset(&RCC_OscInitStruct, 0, sizeof(RCC_OscInitStruct)); + + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + /*Enable CRS Clock*/ + RCC_CRSInitTypeDef RCC_CRSInitStruct= {0}; + __HAL_RCC_CRS_CLK_ENABLE(); + + /* Default Synchro Signal division factor (not divided) */ + RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1; + + /* Set the SYNCSRC[1:0] bits according to CRS_Source value */ + RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB; + + /* HSI48 is synchronized with USB SOF at 1KHz rate */ + RCC_CRSInitStruct.ReloadValue = __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000, 1000); + RCC_CRSInitStruct.ErrorLimitValue = RCC_CRS_ERRORLIMIT_DEFAULT; + + /* Set the TRIM[5:0] to the default value */ + RCC_CRSInitStruct.HSI48CalibrationValue = RCC_CRS_HSI48CALIBRATION_DEFAULT; + + /* Start automatic synchronization */ + HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct); +#endif } static inline void board_vbus_sense_init(void) diff --git a/hw/bsp/stm32g4/family.c b/hw/bsp/stm32g4/family.c index cddd85af0..318f50746 100644 --- a/hw/bsp/stm32g4/family.c +++ b/hw/bsp/stm32g4/family.c @@ -31,14 +31,19 @@ //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ -void OTG_FS_IRQHandler(void) +void USB_HP_IRQHandler(void) { tud_int_handler(0); } -void OTG_HS_IRQHandler(void) +void USB_LP_IRQHandler(void) { - tud_int_handler(1); + tud_int_handler(0); +} + +void USBWakeUp_IRQHandler(void) +{ + tud_int_handler(0); } //--------------------------------------------------------------------+ @@ -111,7 +116,15 @@ void board_init(void) HAL_UART_Init(&UartHandle); #endif - // TODO Configure USB GPIOs + // USB Pins TODO double check USB clock and pin setup + // Configure USB DM and DP pins. This is optional, and maintained only for user guidance. +// GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12); +// GPIO_InitStruct.Mode = GPIO_MODE_INPUT; +// GPIO_InitStruct.Pull = GPIO_NOPULL; +// GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; +// HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); +// +// __HAL_RCC_USB_CLK_ENABLE(); board_vbus_sense_init(); } -- cgit v1.3.1 From e35bb6341cd3a9b81085969cdce60cb3af9ed57e Mon Sep 17 00:00:00 2001 From: Jerzy Kasenberg Date: Thu, 4 Nov 2021 21:46:17 +0100 Subject: broadcom/dcd: Fix mynewt build dcd_synopsys.c included broadcom/interrupts.h before preprocessor check whether file should be used. Since mynewt build does not include all folders it resulted in build error. Now offending include is moved few lines after preprocessor check. --- src/portable/broadcom/synopsys/dcd_synopsys.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/portable/broadcom/synopsys/dcd_synopsys.c b/src/portable/broadcom/synopsys/dcd_synopsys.c index 041158871..494bb70ee 100644 --- a/src/portable/broadcom/synopsys/dcd_synopsys.c +++ b/src/portable/broadcom/synopsys/dcd_synopsys.c @@ -29,6 +29,10 @@ #include "tusb_option.h" +#if TUSB_OPT_DEVICE_ENABLED && \ + (CFG_TUSB_MCU == OPT_MCU_BCM2711 ) \ + + #include "synopsys_common.h" #include "broadcom/interrupts.h" @@ -37,10 +41,6 @@ // We disable SOF for now until needed later on #define USE_SOF 0 -#if TUSB_OPT_DEVICE_ENABLED && \ - (CFG_TUSB_MCU == OPT_MCU_BCM2711 ) \ - - // EP_MAX : Max number of bi-directional endpoints including EP0 // EP_FIFO_SIZE : Size of dedicated USB SRAM #if CFG_TUSB_MCU == OPT_MCU_BCM2711 -- cgit v1.3.1 From ec99bec8cba0ba948832c19641468558d59f6289 Mon Sep 17 00:00:00 2001 From: Rafael Silva Date: Thu, 4 Nov 2021 23:00:05 +0000 Subject: docs: update supported device table remove known issue #750 from silabs EFM32GG table entry --- docs/reference/supported.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst index ef924adb4..1c3ef5a07 100644 --- a/docs/reference/supported.rst +++ b/docs/reference/supported.rst @@ -88,7 +88,7 @@ Supported MCUs | +--------------------+-------------------+--------------------+-------------------+-------------------+--------------+ | | RX65N | |:green_square:| | | |:green_square:| | |:x:| | | +--------------+--------------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| Silabs | EFM32GG12 | |:green_square:| | |:x:| | |:green_square:| | |:x:| | #750 | +| Silabs | EFM32GG12 | |:green_square:| | |:x:| | |:green_square:| | |:x:| | | +--------------+--------------------+-------------------+--------------------+-------------------+-------------------+--------------+ | Sony | CXD56 | |:green_square:| | |:x:| | |:green_square:| | |:x:| | | +--------------+-------+------------+-------------------+--------------------+-------------------+-------------------+--------------+ -- cgit v1.3.1 From a3fc107d94f5126667a51f82b7997a3c629972c4 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 5 Nov 2021 11:40:53 +0700 Subject: xmc4500 led blinky, button ok --- examples/device/board_test/src/main.c | 1 + hw/bsp/xmc4000/boards/xmc4500_relax/board.h | 88 ++++++++++++++++++++ hw/bsp/xmc4000/boards/xmc4500_relax/board.mk | 9 +++ hw/bsp/xmc4000/family.c | 117 +++++++++++++++++++++++++++ hw/bsp/xmc4000/family.mk | 37 +++++++++ src/device/dcd_attr.h | 4 + src/tusb_option.h | 3 + 7 files changed, 259 insertions(+) create mode 100644 hw/bsp/xmc4000/boards/xmc4500_relax/board.h create mode 100644 hw/bsp/xmc4000/boards/xmc4500_relax/board.mk create mode 100644 hw/bsp/xmc4000/family.c create mode 100644 hw/bsp/xmc4000/family.mk diff --git a/examples/device/board_test/src/main.c b/examples/device/board_test/src/main.c index c77dd5647..5e28cbb27 100644 --- a/examples/device/board_test/src/main.c +++ b/examples/device/board_test/src/main.c @@ -47,6 +47,7 @@ enum { int main(void) { board_init(); + board_led_write(true); uint32_t start_ms = 0; bool led_state = false; diff --git a/hw/bsp/xmc4000/boards/xmc4500_relax/board.h b/hw/bsp/xmc4000/boards/xmc4500_relax/board.h new file mode 100644 index 000000000..3e2cb9583 --- /dev/null +++ b/hw/bsp/xmc4000/boards/xmc4500_relax/board.h @@ -0,0 +1,88 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#define LED_PIN P1_1 +#define LED_STATE_ON 1 + +#define BUTTON_PIN P1_14 +#define BUTTON_STATE_ACTIVE 0 + +//#define UART_DEV USART6 +//#define UART_CLK_EN __HAL_RCC_USART6_CLK_ENABLE +//#define UART_GPIO_AF GPIO_AF8_USART6 +// +//#define UART_TX_PORT GPIOC +//#define UART_TX_PIN GPIO_PIN_6 +// +//#define UART_RX_PORT GPIOC +//#define UART_RX_PIN GPIO_PIN_7 + +static inline void board_clock_init(void) +{ + /* Clock configuration */ + /* fPLL = 120MHz */ + /* fSYS = 120MHz */ + /* fUSBPLL = 192MHz */ + /* fUSB = 48MHz */ + const XMC_SCU_CLOCK_CONFIG_t clock_config = + { + .syspll_config.p_div = 2, + .syspll_config.n_div = 80, + .syspll_config.k_div = 4, + .syspll_config.mode = XMC_SCU_CLOCK_SYSPLL_MODE_NORMAL, + .syspll_config.clksrc = XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP, + .enable_oschp = true, + .calibration_mode = XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_FACTORY, + .fsys_clksrc = XMC_SCU_CLOCK_SYSCLKSRC_PLL, + .fsys_clkdiv = 1, + .fcpu_clkdiv = 1, + .fccu_clkdiv = 1, + .fperipheral_clkdiv = 1 + }; + + /* Setup settings for USB clock */ + XMC_SCU_CLOCK_Init(&clock_config); + + XMC_SCU_CLOCK_EnableUsbPll(); + XMC_SCU_CLOCK_StartUsbPll(2, 64); + XMC_SCU_CLOCK_SetUsbClockDivider(4); + XMC_SCU_CLOCK_SetUsbClockSource(XMC_SCU_CLOCK_USBCLKSRC_USBPLL); + XMC_SCU_CLOCK_EnableClock(XMC_SCU_CLOCK_USB); +} + + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/xmc4000/boards/xmc4500_relax/board.mk b/hw/bsp/xmc4000/boards/xmc4500_relax/board.mk new file mode 100644 index 000000000..a2c2c5aaf --- /dev/null +++ b/hw/bsp/xmc4000/boards/xmc4500_relax/board.mk @@ -0,0 +1,9 @@ +MCU_VARIANT = XMC4500 +CFLAGS += \ + -DXMC4500_F100x1024 \ + +LD_FILE = $(MCU_DIR)/CMSIS/Infineon/COMPONENT_$(MCU_VARIANT)/Source/TOOLCHAIN_GCC_ARM/XMC4500x1024.ld + +JLINK_DEVICE = XMC4500-1024 + +flash: flash-jlink diff --git a/hw/bsp/xmc4000/family.c b/hw/bsp/xmc4000/family.c new file mode 100644 index 000000000..8b5f82f15 --- /dev/null +++ b/hw/bsp/xmc4000/family.c @@ -0,0 +1,117 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "xmc_gpio.h" +#include "xmc_scu.h" + +#include "bsp/board.h" +#include "board.h" + +void board_init(void) +{ + board_clock_init(); + SystemCoreClockUpdate(); + + // LED + XMC_GPIO_CONFIG_t led_cfg; + led_cfg.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL; + led_cfg.output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH; + led_cfg.output_strength = XMC_GPIO_OUTPUT_STRENGTH_MEDIUM; + XMC_GPIO_Init(LED_PIN, &led_cfg); + + // Button + XMC_GPIO_CONFIG_t button_cfg; + button_cfg.mode = XMC_GPIO_MODE_INPUT_TRISTATE; + XMC_GPIO_Init(BUTTON_PIN, &button_cfg); + +#if CFG_TUSB_OS == OPT_OS_NONE + // 1ms tick timer + SysTick_Config(SystemCoreClock / 1000); + +#elif CFG_TUSB_OS == OPT_OS_FREERTOS + // Explicitly disable systick to prevent its ISR runs before scheduler start + SysTick->CTRL &= ~1U; + + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(USB0_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); +#endif +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +void board_led_write(bool state) +{ + uint32_t is_high = state ? LED_STATE_ON : (1-LED_STATE_ON); + + XMC_GPIO_SetOutputLevel(LED_PIN, is_high ? XMC_GPIO_OUTPUT_LEVEL_HIGH : XMC_GPIO_OUTPUT_LEVEL_LOW); +} + +uint32_t board_button_read(void) +{ + return BUTTON_STATE_ACTIVE == XMC_GPIO_GetInput(BUTTON_PIN); +} + +int board_uart_read(uint8_t* buf, int len) +{ +#ifdef UART_DEV + for(int i=0;i Date: Fri, 5 Nov 2021 12:00:27 +0700 Subject: add xmclib as submodule --- .gitmodules | 3 +++ hw/bsp/xmc4000/family.mk | 2 +- hw/mcu/infineon/mtb-xmclib-cat3 | 1 + 3 files changed, 5 insertions(+), 1 deletion(-) create mode 160000 hw/mcu/infineon/mtb-xmclib-cat3 diff --git a/.gitmodules b/.gitmodules index a95e64ee6..5c79ea910 100644 --- a/.gitmodules +++ b/.gitmodules @@ -131,3 +131,6 @@ path = hw/mcu/broadcom url = https://github.com/adafruit/broadcom-peripherals.git branch = main-build +[submodule "hw/mcu/infineon/mtb-xmclib-cat3"] + path = hw/mcu/infineon/mtb-xmclib-cat3 + url = https://github.com/Infineon/mtb-xmclib-cat3.git diff --git a/hw/bsp/xmc4000/family.mk b/hw/bsp/xmc4000/family.mk index fc417d41d..e5b9f7b1a 100644 --- a/hw/bsp/xmc4000/family.mk +++ b/hw/bsp/xmc4000/family.mk @@ -1,7 +1,7 @@ UF2_FAMILY_ID = 0x00 MCU_DIR = hw/mcu/infineon/mtb-xmclib-cat3 -#DEPS_SUBMODULES += $(MCU_DIR) +DEPS_SUBMODULES += $(MCU_DIR) include $(TOP)/$(BOARD_PATH)/board.mk diff --git a/hw/mcu/infineon/mtb-xmclib-cat3 b/hw/mcu/infineon/mtb-xmclib-cat3 new file mode 160000 index 000000000..daf5500d0 --- /dev/null +++ b/hw/mcu/infineon/mtb-xmclib-cat3 @@ -0,0 +1 @@ +Subproject commit daf5500d03cba23e68c2f241c30af79cd9d63880 -- cgit v1.3.1 From d87a897a7bc524139f844a323df4e0679b2deebe Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 5 Nov 2021 13:13:21 +0700 Subject: xmc4500 ported, cdc msc example run fine --- hw/bsp/xmc4000/family.c | 13 +++++ hw/bsp/xmc4000/family.mk | 3 ++ src/portable/synopsys/dwc2/dcd_dwc2.c | 4 +- src/portable/synopsys/dwc2/dwc2_xmc.h | 87 ++++++++++++++++++++++++++++++++ src/portable/synopsys/dwc2/hwcfg_list.md | 55 ++++++++++++++++++++ 5 files changed, 161 insertions(+), 1 deletion(-) create mode 100644 src/portable/synopsys/dwc2/dwc2_xmc.h diff --git a/hw/bsp/xmc4000/family.c b/hw/bsp/xmc4000/family.c index 8b5f82f15..bf6684736 100644 --- a/hw/bsp/xmc4000/family.c +++ b/hw/bsp/xmc4000/family.c @@ -30,6 +30,15 @@ #include "bsp/board.h" #include "board.h" + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void USB0_0_IRQHandler(void) +{ + tud_int_handler(0); +} + void board_init(void) { board_clock_init(); @@ -58,6 +67,10 @@ void board_init(void) // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) NVIC_SetPriority(USB0_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); #endif + + // USB Power Enable + XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USB0); + XMC_SCU_POWER_EnableUsb(); } //--------------------------------------------------------------------+ diff --git a/hw/bsp/xmc4000/family.mk b/hw/bsp/xmc4000/family.mk index e5b9f7b1a..0b32bdeb5 100644 --- a/hw/bsp/xmc4000/family.mk +++ b/hw/bsp/xmc4000/family.mk @@ -18,6 +18,8 @@ CFLAGS += \ # mcu driver cause following warnings #CFLAGS += -Wno-error=shadow -Wno-error=cast-align +SKIP_NANOLIB = 1 + SRC_C += \ src/portable/synopsys/dwc2/dcd_dwc2.c \ $(MCU_DIR)/Newlib/syscalls.c \ @@ -25,6 +27,7 @@ SRC_C += \ $(MCU_DIR)/XMCLib/src/xmc4_gpio.c \ $(MCU_DIR)/XMCLib/src/xmc4_scu.c + SRC_S += $(MCU_DIR)/CMSIS/Infineon/COMPONENT_$(MCU_VARIANT)/Source/TOOLCHAIN_GCC_ARM/startup_$(MCU_VARIANT).S INC += \ diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 3967f225e..44a5f8932 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -33,7 +33,7 @@ #if TUSB_OPT_DEVICE_ENABLED && \ ( defined(DCD_ATTR_DWC2_STM32) || \ TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3, OPT_MCU_GD32VF103) || \ - TU_CHECK_MCU(OPT_MCU_EFM32GG, OPT_MCU_BCM2711) ) + TU_CHECK_MCU(OPT_MCU_EFM32GG, OPT_MCU_BCM2711, OPT_MCU_XMC4000) ) #include "device/dcd.h" #include "dwc2_type.h" @@ -48,6 +48,8 @@ #include "dwc2_bcm.h" #elif TU_CHECK_MCU(OPT_MCU_EFM32GG) #include "dwc2_efm32.h" +#elif TU_CHECK_MCU(OPT_MCU_XMC4000) + #include "dwc2_xmc.h" #else #error "Unsupported MCUs" #endif diff --git a/src/portable/synopsys/dwc2/dwc2_xmc.h b/src/portable/synopsys/dwc2/dwc2_xmc.h new file mode 100644 index 000000000..4e6bebb01 --- /dev/null +++ b/src/portable/synopsys/dwc2/dwc2_xmc.h @@ -0,0 +1,87 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Rafael Silva (@perigoso) + * Copyright (c) 2021, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef _DWC2_XMC_H_ +#define _DWC2_XMC_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "xmc_device.h" + +// XMC has custom control register before DWC registers +#define DWC2_REG_BASE USB0_BASE +#define DWC2_EP_MAX 7 +#define DWC2_EP_FIFO_SIZE 2048 + +TU_ATTR_ALWAYS_INLINE +static inline void dwc2_dcd_int_enable(uint8_t rhport) +{ + (void) rhport; + NVIC_EnableIRQ(USB0_0_IRQn); +} + +TU_ATTR_ALWAYS_INLINE +static inline void dwc2_dcd_int_disable (uint8_t rhport) +{ + (void) rhport; + NVIC_DisableIRQ(USB0_0_IRQn); +} + +static inline void dwc2_remote_wakeup_delay(void) +{ + // try to delay for 1 ms +// uint32_t count = SystemCoreClock / 1000; +// while ( count-- ) __NOP(); +} + +// MCU specific PHY init, called BEFORE core reset +static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type) +{ + (void) dwc2; + (void) hs_phy_type; + + // Enable PHY + //USB->ROUTE = USB_ROUTE_PHYPEN; +} + +// MCU specific PHY update, it is called AFTER init() and core reset +static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type) +{ + (void) dwc2; + (void) hs_phy_type; + + // XMC Manual: turn around must be 5 (reset & default value) + // dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_TRDT_Msk) | (5u << GUSBCFG_TRDT_Pos); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/portable/synopsys/dwc2/hwcfg_list.md b/src/portable/synopsys/dwc2/hwcfg_list.md index 495a30fd0..b5590da00 100644 --- a/src/portable/synopsys/dwc2/hwcfg_list.md +++ b/src/portable/synopsys/dwc2/hwcfg_list.md @@ -720,3 +720,58 @@ hw_cfg4->dedicated_fifos = 0 hw_cfg4->num_dev_in_eps = 0 hw_cfg4->dma_desc_enable = 0 hw_cfg4->dma_dynamic = 0 + +## XMC4500 + +dwc2->guid = AEC000 +dwc2->gsnpsid = 4F54292A +dwc2->ghwcfg1 = 0 + +dwc2->ghwcfg2 = 228F5930 +hw_cfg2->op_mode = 0 +hw_cfg2->arch = 2 +hw_cfg2->point2point = 1 +hw_cfg2->hs_phy_type = 0 +hw_cfg2->fs_phy_type = 1 +hw_cfg2->num_dev_ep = 6 +hw_cfg2->num_host_ch = 13 +hw_cfg2->period_channel_support = 1 +hw_cfg2->enable_dynamic_fifo = 1 +hw_cfg2->mul_cpu_int = 0 +hw_cfg2->nperiod_tx_q_depth = 2 +hw_cfg2->host_period_tx_q_depth = 2 +hw_cfg2->dev_token_q_depth = 8 +hw_cfg2->otg_enable_ic_usb = 0 + +dwc2->ghwcfg3 = 27A01E5 +hw_cfg3->xfer_size_width = 5 +hw_cfg3->packet_size_width = 6 +hw_cfg3->otg_enable = 1 +hw_cfg3->i2c_enable = 1 +hw_cfg3->vendor_ctrl_itf = 0 +hw_cfg3->optional_feature_removed = 0 +hw_cfg3->synch_reset = 0 +hw_cfg3->otg_adp_support = 0 +hw_cfg3->otg_enable_hsic = 0 +hw_cfg3->battery_charger_support = 0 +hw_cfg3->lpm_mode = 0 +hw_cfg3->total_fifo_size = 634 + +dwc2->ghwcfg4 = DBF08030 +hw_cfg4->num_dev_period_in_ep = 0 +hw_cfg4->power_optimized = 1 +hw_cfg4->ahb_freq_min = 1 +hw_cfg4->hibernation = 0 +hw_cfg4->service_interval_mode = 0 +hw_cfg4->ipg_isoc_en = 0 +hw_cfg4->acg_enable = 0 +hw_cfg4->utmi_phy_data_width = 2 +hw_cfg4->dev_ctrl_ep_num = 0 +hw_cfg4->iddg_filter_enabled = 1 +hw_cfg4->vbus_valid_filter_enabled = 1 +hw_cfg4->a_valid_filter_enabled = 1 +hw_cfg4->b_valid_filter_enabled = 1 +hw_cfg4->dedicated_fifos = 1 +hw_cfg4->num_dev_in_eps = 13 +hw_cfg4->dma_desc_enable = 0 +hw_cfg4->dma_dynamic = 1 -- cgit v1.3.1 From 422f439bf73450b9f08ff6fb2bf961205ba1c5f5 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 5 Nov 2021 13:18:54 +0700 Subject: update docs --- README.rst | 1 + docs/reference/supported.rst | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/README.rst b/README.rst index 1db022fc8..60df78ca4 100644 --- a/README.rst +++ b/README.rst @@ -34,6 +34,7 @@ The stack supports the following MCUs: - **Dialog:** DA1469x - **Espressif:** ESP32-S2, ESP32-S3 +- **Infineon:** XMC4500 - **MicroChip:** SAMD11, SAMD21, SAMD51, SAME5x, SAMG55, SAML21, SAML22, SAME7x - **NordicSemi:** nRF52833, nRF52840, nRF5340 - **Nuvoton:** NUC120, NUC121/NUC125, NUC126, NUC505 diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst index ef924adb4..95f3e1da9 100644 --- a/docs/reference/supported.rst +++ b/docs/reference/supported.rst @@ -149,6 +149,14 @@ Espressif ESP32-S2 - `ESP32-S2-Kaluga-1 `__ - `ESP32-S2-Saola-1 `__ +Infineon +--------- + +XMC4000 +^^^^^^^ + +- `XMC4500 Relax (Lite) Kit `__ + MicroChip --------- -- cgit v1.3.1 From 3fc3e400b0ad91a0f15fe0c45bb924a9b1d65249 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 5 Nov 2021 13:23:31 +0700 Subject: add xmc4000 to ci build --- .github/workflows/build_arm.yml | 1 + hw/bsp/board_mcu.h | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml index 53a1628a0..8db0fe04f 100644 --- a/.github/workflows/build_arm.yml +++ b/.github/workflows/build_arm.yml @@ -57,6 +57,7 @@ jobs: - 'stm32f7' - 'stm32h7' - 'stm32l4' + - 'xmc4000' steps: - name: Setup Python uses: actions/setup-python@v2 diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h index c840db89e..1e2577de0 100644 --- a/hw/bsp/board_mcu.h +++ b/hw/bsp/board_mcu.h @@ -136,6 +136,10 @@ #elif CFG_TUSB_MCU == OPT_MCU_MM32F327X #include "mm32_device.h" + +#elif CFG_TUSB_MCU == OPT_MCU_XMC4000 + #include "xmc_device.h" + #else #error "Missing MCU header" #endif -- cgit v1.3.1 From e692fa9ae4b6c8ff7b66dedbecaf745ae2166851 Mon Sep 17 00:00:00 2001 From: Liam Fraser Date: Fri, 5 Nov 2021 09:39:31 +0000 Subject: RP2040 HCD: Move invalid ep->active assert in hw_trans_complete. The check for ep->active should only happen if a setup packet was just sent. Otherwise the transaction is handled in hw_handle_buff_status. --- src/portable/raspberrypi/rp2040/hcd_rp2040.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c index 627e957e8..768cccc86 100644 --- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c @@ -160,12 +160,11 @@ static void hw_handle_buff_status(void) static void hw_trans_complete(void) { - struct hw_endpoint *ep = &epx; - assert(ep->active); - if (usb_hw->sie_ctrl & USB_SIE_CTRL_SEND_SETUP_BITS) { pico_trace("Sent setup packet\n"); + struct hw_endpoint *ep = &epx; + assert(ep->active); hw_xfer_complete(ep, XFER_RESULT_SUCCESS); } else -- cgit v1.3.1 From ec8ece2c9d0f801d6aa763b964719d375c5441d4 Mon Sep 17 00:00:00 2001 From: Jerzy Kasenberg Date: Fri, 5 Nov 2021 12:23:59 +0100 Subject: bth: Update driver to interface association changes Two interfaces that are required by Bluetooth Primary Controller do not have IAD according to Bluetooth specification. Those two interfaces were opened separately in process_set_config(). Later interface association was inferred for BTH (along with other drivers), since then only one call to open() is place for BTH driver that should prepare both interfaces at once. To make it work again btd_open() parses two interfaces at once. --- src/class/bth/bth_device.c | 112 +++++++++++++++++++++++---------------------- 1 file changed, 58 insertions(+), 54 deletions(-) diff --git a/src/class/bth/bth_device.c b/src/class/bth/bth_device.c index f445deed2..8ef609622 100755 --- a/src/class/bth/bth_device.c +++ b/src/class/bth/bth_device.c @@ -112,74 +112,78 @@ uint16_t btd_open(uint8_t rhport, tusb_desc_interface_t const *itf_desc, uint16_ TUD_BT_APP_SUBCLASS == itf_desc->bInterfaceSubClass && TUD_BT_PROTOCOL_PRIMARY_CONTROLLER == itf_desc->bInterfaceProtocol, 0); - // Distinguish interface by number of endpoints, as both interface have same class, subclass and protocol - if (itf_desc->bNumEndpoints == 3 && max_len >= hci_itf_size) - { - _btd_itf.itf_num = itf_desc->bInterfaceNumber; + TU_ASSERT(itf_desc->bNumEndpoints == 3 && max_len >= hci_itf_size); - desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next(itf_desc); + _btd_itf.itf_num = itf_desc->bInterfaceNumber; - TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType && TUSB_XFER_INTERRUPT == desc_ep->bmAttributes.xfer, 0); - TU_ASSERT(usbd_edpt_open(rhport, desc_ep), 0); - _btd_itf.ep_ev = desc_ep->bEndpointAddress; + desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next(itf_desc); - // Open endpoint pair - TU_ASSERT(usbd_open_edpt_pair(rhport, tu_desc_next(desc_ep), 2, TUSB_XFER_BULK, &_btd_itf.ep_acl_out, - &_btd_itf.ep_acl_in), 0); + TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType && TUSB_XFER_INTERRUPT == desc_ep->bmAttributes.xfer, 0); + TU_ASSERT(usbd_edpt_open(rhport, desc_ep), 0); + _btd_itf.ep_ev = desc_ep->bEndpointAddress; - // Prepare for incoming data from host - TU_ASSERT(usbd_edpt_xfer(rhport, _btd_itf.ep_acl_out, _btd_itf.epout_buf, CFG_TUD_BTH_DATA_EPSIZE), 0); + // Open endpoint pair + TU_ASSERT(usbd_open_edpt_pair(rhport, tu_desc_next(desc_ep), 2, TUSB_XFER_BULK, &_btd_itf.ep_acl_out, + &_btd_itf.ep_acl_in), 0); - drv_len = hci_itf_size; - } - else if (itf_desc->bNumEndpoints == 2 && max_len >= iso_alt_itf_size) - { - uint8_t dir; + itf_desc = (tusb_desc_interface_t const *)tu_desc_next(tu_desc_next(tu_desc_next(desc_ep))); - desc_ep = (tusb_desc_endpoint_t const *)tu_desc_next(itf_desc); + // Prepare for incoming data from host + TU_ASSERT(usbd_edpt_xfer(rhport, _btd_itf.ep_acl_out, _btd_itf.epout_buf, CFG_TUD_BTH_DATA_EPSIZE), 0); + + drv_len = hci_itf_size; + + // Ensure this is still BT Primary Controller + TU_ASSERT(TUSB_CLASS_WIRELESS_CONTROLLER == itf_desc->bInterfaceClass && + TUD_BT_APP_SUBCLASS == itf_desc->bInterfaceSubClass && + TUD_BT_PROTOCOL_PRIMARY_CONTROLLER == itf_desc->bInterfaceProtocol, 0); + TU_ASSERT(itf_desc->bNumEndpoints == 2 && max_len >= iso_alt_itf_size + drv_len); + + uint8_t dir; + + desc_ep = (tusb_desc_endpoint_t const *)tu_desc_next(itf_desc); + TU_ASSERT(itf_desc->bAlternateSetting < CFG_TUD_BTH_ISO_ALT_COUNT, 0); + TU_ASSERT(desc_ep->bDescriptorType == TUSB_DESC_ENDPOINT, 0); + dir = tu_edpt_dir(desc_ep->bEndpointAddress); + _btd_itf.ep_voice[dir] = desc_ep->bEndpointAddress; + // Store endpoint size for alternative + _btd_itf.ep_voice_size[dir][itf_desc->bAlternateSetting] = (uint8_t) tu_edpt_packet_size(desc_ep); + + desc_ep = (tusb_desc_endpoint_t const *)tu_desc_next(desc_ep); + TU_ASSERT(desc_ep->bDescriptorType == TUSB_DESC_ENDPOINT, 0); + dir = tu_edpt_dir(desc_ep->bEndpointAddress); + _btd_itf.ep_voice[dir] = desc_ep->bEndpointAddress; + // Store endpoint size for alternative + _btd_itf.ep_voice_size[dir][itf_desc->bAlternateSetting] = (uint8_t) tu_edpt_packet_size(desc_ep); + drv_len += iso_alt_itf_size; + + for (int i = 1; i < CFG_TUD_BTH_ISO_ALT_COUNT && drv_len + iso_alt_itf_size <= max_len; ++i) { + // Make sure rest of alternatives matches + itf_desc = (tusb_desc_interface_t const *)tu_desc_next(desc_ep); + if (itf_desc->bDescriptorType != TUSB_DESC_INTERFACE || + TUSB_CLASS_WIRELESS_CONTROLLER != itf_desc->bInterfaceClass || + TUD_BT_APP_SUBCLASS != itf_desc->bInterfaceSubClass || + TUD_BT_PROTOCOL_PRIMARY_CONTROLLER != itf_desc->bInterfaceProtocol) + { + // Not an Iso interface instance + break; + } TU_ASSERT(itf_desc->bAlternateSetting < CFG_TUD_BTH_ISO_ALT_COUNT, 0); - TU_ASSERT(desc_ep->bDescriptorType == TUSB_DESC_ENDPOINT, 0); + + desc_ep = (tusb_desc_endpoint_t const *)tu_desc_next(itf_desc); dir = tu_edpt_dir(desc_ep->bEndpointAddress); - _btd_itf.ep_voice[dir] = desc_ep->bEndpointAddress; - // Store endpoint size for alternative + // Verify that alternative endpoint are same as first ones + TU_ASSERT(desc_ep->bDescriptorType == TUSB_DESC_ENDPOINT && + _btd_itf.ep_voice[dir] == desc_ep->bEndpointAddress, 0); _btd_itf.ep_voice_size[dir][itf_desc->bAlternateSetting] = (uint8_t) tu_edpt_packet_size(desc_ep); desc_ep = (tusb_desc_endpoint_t const *)tu_desc_next(desc_ep); - TU_ASSERT(desc_ep->bDescriptorType == TUSB_DESC_ENDPOINT, 0); dir = tu_edpt_dir(desc_ep->bEndpointAddress); - _btd_itf.ep_voice[dir] = desc_ep->bEndpointAddress; - // Store endpoint size for alternative + // Verify that alternative endpoint are same as first ones + TU_ASSERT(desc_ep->bDescriptorType == TUSB_DESC_ENDPOINT && + _btd_itf.ep_voice[dir] == desc_ep->bEndpointAddress, 0); _btd_itf.ep_voice_size[dir][itf_desc->bAlternateSetting] = (uint8_t) tu_edpt_packet_size(desc_ep); drv_len += iso_alt_itf_size; - - for (int i = 1; i < CFG_TUD_BTH_ISO_ALT_COUNT && drv_len + iso_alt_itf_size <= max_len; ++i) { - // Make sure rest of alternatives matches - itf_desc = (tusb_desc_interface_t const *)tu_desc_next(desc_ep); - if (itf_desc->bDescriptorType != TUSB_DESC_INTERFACE || - TUSB_CLASS_WIRELESS_CONTROLLER != itf_desc->bInterfaceClass || - TUD_BT_APP_SUBCLASS != itf_desc->bInterfaceSubClass || - TUD_BT_PROTOCOL_PRIMARY_CONTROLLER != itf_desc->bInterfaceProtocol) - { - // Not an Iso interface instance - break; - } - TU_ASSERT(itf_desc->bAlternateSetting < CFG_TUD_BTH_ISO_ALT_COUNT, 0); - - desc_ep = (tusb_desc_endpoint_t const *)tu_desc_next(itf_desc); - dir = tu_edpt_dir(desc_ep->bEndpointAddress); - // Verify that alternative endpoint are same as first ones - TU_ASSERT(desc_ep->bDescriptorType == TUSB_DESC_ENDPOINT && - _btd_itf.ep_voice[dir] == desc_ep->bEndpointAddress, 0); - _btd_itf.ep_voice_size[dir][itf_desc->bAlternateSetting] = (uint8_t) tu_edpt_packet_size(desc_ep); - - desc_ep = (tusb_desc_endpoint_t const *)tu_desc_next(desc_ep); - dir = tu_edpt_dir(desc_ep->bEndpointAddress); - // Verify that alternative endpoint are same as first ones - TU_ASSERT(desc_ep->bDescriptorType == TUSB_DESC_ENDPOINT && - _btd_itf.ep_voice[dir] == desc_ep->bEndpointAddress, 0); - _btd_itf.ep_voice_size[dir][itf_desc->bAlternateSetting] = (uint8_t) tu_edpt_packet_size(desc_ep); - drv_len += iso_alt_itf_size; - } } return drv_len; -- cgit v1.3.1 From d20a5b3a0918cdccfccbed6f623ff0e854392c82 Mon Sep 17 00:00:00 2001 From: Jerzy Kasenberg Date: Fri, 5 Nov 2021 13:03:31 +0100 Subject: bth: Add IAD to BT descriptor Bluetooth's specification defines IAD for primary controller. While it seems that Windows and Linux can leave without this, there is no reason TinyUSB should not provide it. --- src/device/usbd.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/device/usbd.h b/src/device/usbd.h index 8d02de1ff..ec34817fa 100644 --- a/src/device/usbd.h +++ b/src/device/usbd.h @@ -763,8 +763,8 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb #define CFG_TUD_BTH_ISO_ALT_COUNT 0 #endif -// Length of template descriptor: 30 bytes + number of ISO alternatives * 23 -#define TUD_BTH_DESC_LEN (9 + 7 + 7 + 7 + (CFG_TUD_BTH_ISO_ALT_COUNT) * (9 + 7 + 7)) +// Length of template descriptor: 38 bytes + number of ISO alternatives * 23 +#define TUD_BTH_DESC_LEN (8 + 9 + 7 + 7 + 7 + (CFG_TUD_BTH_ISO_ALT_COUNT) * (9 + 7 + 7)) /* Primary Interface */ #define TUD_BTH_PRI_ITF(_itfnum, _stridx, _ep_evt, _ep_evt_size, _ep_evt_interval, _ep_in, _ep_out, _ep_size) \ @@ -806,6 +806,8 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb // Interface number, string index, attributes, event endpoint, event endpoint size, interval, data in, data out, data endpoint size, iso endpoint sizes // TODO BTH should also use IAD like CDC for composite device #define TUD_BTH_DESCRIPTOR(_itfnum, _stridx, _ep_evt, _ep_evt_size, _ep_evt_interval, _ep_in, _ep_out, _ep_size,...) \ + /* Interface Associate */\ + 8, TUSB_DESC_INTERFACE_ASSOCIATION, _itfnum, 2, TUD_BT_APP_CLASS, TUD_BT_APP_SUBCLASS, TUD_BT_PROTOCOL_PRIMARY_CONTROLLER, 0,\ TUD_BTH_PRI_ITF(_itfnum, _stridx, _ep_evt, _ep_evt_size, _ep_evt_interval, _ep_in, _ep_out, _ep_size) \ TUD_BTH_ISO_ITFS(_itfnum + 1, _ep_in + 1, _ep_out + 1, __VA_ARGS__) -- cgit v1.3.1 From f183d0810bb4570bf569cb08a6644933b8813dff Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Sat, 23 Oct 2021 15:14:28 +0900 Subject: Add files for msp432e4 --- hw/bsp/msp432e4/boards/msp_exp432e401y/board.h | 46 +++++++ hw/bsp/msp432e4/family.c | 174 +++++++++++++++++++++++++ hw/bsp/msp432e4/family.mk | 48 +++++++ src/device/dcd_attr.h | 2 +- src/tusb_option.h | 1 + 5 files changed, 270 insertions(+), 1 deletion(-) create mode 100644 hw/bsp/msp432e4/boards/msp_exp432e401y/board.h create mode 100644 hw/bsp/msp432e4/family.c create mode 100644 hw/bsp/msp432e4/family.mk diff --git a/hw/bsp/msp432e4/boards/msp_exp432e401y/board.h b/hw/bsp/msp432e4/boards/msp_exp432e401y/board.h new file mode 100644 index 000000000..b449f3ca4 --- /dev/null +++ b/hw/bsp/msp432e4/boards/msp_exp432e401y/board.h @@ -0,0 +1,46 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#define LED_PORT P1OUT +#define LED_PIN BIT0 +#define LED_STATE_ON 1 + +#define BUTTON_PORT P1IN +#define BUTTON_PIN BIT1 +#define BUTTON_STATE_ACTIVE 0 + +#ifdef __cplusplus + extern "C" { +#endif + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/hw/bsp/msp432e4/family.c b/hw/bsp/msp432e4/family.c new file mode 100644 index 000000000..3bb36042d --- /dev/null +++ b/hw/bsp/msp432e4/family.c @@ -0,0 +1,174 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "bsp/board.h" +#include "board.h" +#include "msp.h" + +/* Frequency of the external crystal oscillator */ +#define XTAL_FREQUENCY 25000000UL + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void USB0_IRQHandler(void) +{ + tud_int_handler(0); +} + +//--------------------------------------------------------------------+ +// MACRO TYPEDEF CONSTANT ENUM +//--------------------------------------------------------------------+ + +void board_init(void) +{ + /* Turn off power domains that unused peripherals belong to */ + SYSCTL->PCCAN = 0u; +#ifdef __MCU_HAS_LCD0__ + SYSCTL->PCLCD = 0u; +#endif + SYSCTL->PCEMAC = 0u; + SYSCTL->PCEPHY = 0u; + SYSCTL->PCCCM = 0u; + + /* --- Setup system clock --- */ + /* Start power-up process of the main oscillator */ + SYSCTL->MOSCCTL = SYSCTL_MOSCCTL_OSCRNG; + while (!(SYSCTL->RIS & SYSCTL_RIS_MOSCPUPRIS)) ; /* Wait for completion */ + SYSCTL->MISC = SYSCTL_MISC_MOSCPUPMIS; /* Clear the completion interrupt status */ + /* Set the main oscillator to PLL reference clock */ + SYSCTL->RSCLKCFG = SYSCTL_RSCLKCFG_PLLSRC_MOSC; + /* PLL freq. = (MOSC freq. / 10) * 96 = 240MHz */ + SYSCTL->PLLFREQ1 = (4 << SYSCTL_PLLFREQ1_N_S) | (1 << SYSCTL_PLLFREQ1_Q_S); + SYSCTL->PLLFREQ0 = (96 << SYSCTL_PLLFREQ0_MINT_S) | SYSCTL_PLLFREQ0_PLLPWR; + /* Set BCHT=6, BCE=0, WS=5 for 120MHz system clock */ + SYSCTL->MEMTIM0 = SYSCTL_MEMTIM0_EBCHT_3_5 | (5 << SYSCTL_MEMTIM0_EWS_S) | + SYSCTL_MEMTIM0_FBCHT_3_5 | (5 << SYSCTL_MEMTIM0_FWS_S) | SYSCTL_MEMTIM0_MB1; + /* Wait for completion of PLL power-up process */ + while (!(SYSCTL->RIS & SYSCTL_RIS_PLLLRIS)) ; + SYSCTL->MISC = SYSCTL_MISC_PLLLMIS; /* Clear the completion interrupt status */ + /* Switch the system clock to PLL/4 */ + SYSCTL->RSCLKCFG = SYSCTL_RSCLKCFG_MEMTIMU | SYSCTL_RSCLKCFG_ACG | + SYSCTL_RSCLKCFG_USEPLL | SYSCTL_RSCLKCFG_PLLSRC_MOSC | (1 << SYSCTL_RSCLKCFG_PSYSDIV_S); + + SystemCoreClockUpdate(); +#if CFG_TUSB_OS == OPT_OS_NONE + SysTick_Config(SystemCoreClock / 1000); +#endif + + /* USR_LED1 PN1 */ + SYSCTL->RCGCGPIO |= 1u << 12; + while (!(SYSCTL->PRGPIO & (1u << 12))) ; + GPION->DIR = 2u; + GPION->DEN = 2u; + + /* USR_SW1 PJ0 */ + SYSCTL->RCGCGPIO |= 1u << 8; + while (!(SYSCTL->PRGPIO & (1u << 8))) ; + GPIOJ->PUR = 1u; + GPIOJ->DEN = 1u; + + /* UART PA0,1 */ + SYSCTL->RCGCGPIO |= 1u << 0; + while (!(SYSCTL->PRGPIO & (1u << 0))) ; + GPIOA->AFSEL = 3u; + GPIOA->PCTL = 0x11u; + GPIOA->DEN = 3u; + + SYSCTL->RCGCUART |= 1u << 0; + while (!(SYSCTL->PRUART & (1u << 0))) ; + UART0->CTL = 0; + UART0->IBRD = 8; /* 8.68056 = 16MHz / (16 * 115200) */ + UART0->FBRD = 44; /* 0.6875 = 44/64 -> 115108bps (0.08%) */ + UART0->LCRH = UART_LCRH_WLEN_8 | UART_LCRH_FEN; + UART0->CC = UART_CC_CS_PIOSC; /* Set the baud clock to PIOSC */ + UART0->CTL = UART_CTL_RXE | UART_CTL_TXE | UART_CTL_UARTEN; + + /* USB PB1(VBUS) PL6,7(DP,DM) */ + SYSCTL->RCGCGPIO |= (1u << 1) | (1u << 10); + while (((1u << 1) | (1u << 10)) != (SYSCTL->PRGPIO & ((1u << 1) | (1u << 10)))) ; + GPIOB->AMSEL = 1u << 1; + GPIOL->AMSEL = (1u << 6) | (1u << 7); + + SYSCTL->RCGCUSB = 1u; /* Open the clock gate for SYSCLK */ + while (!(SYSCTL->PRUSB & (1u << 0))) ; + USB0->CC = USB_CC_CLKEN | (3u << USB_CC_CLKDIV_S); /* 60MHz = 240MHz / 4 */ + __DMB(); /* Wait for completion of opening of the clock gate */ + + SYSCTL->SRUSB = 1u; + for (int i = 0; i < 16; ++i) __NOP(); + SYSCTL->SRUSB = 0u; + +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +void board_led_write(bool state) +{ + if (state) + GPION->DATA |= 2u; + else + GPION->DATA &= ~2u; +} + +uint32_t board_button_read(void) +{ + return (GPIOJ->DATA & 1u) ? 0u : 1u; +} + +int board_uart_read(uint8_t * buf, int len) +{ + for (int i = 0; i < len; ++i) { + while (UART0->FR & UART_FR_RXFE) ; + *buf++ = UART0->DR; + } + return len; +} + +int board_uart_write(void const * buf, int len) +{ + uint8_t const *p = (uint8_t const *)buf; + for (int i = 0; i < len; ++i) { + while (UART0->FR & UART_FR_TXFF) ; + UART0->DR = *p++; + } + return len; +} + +#if CFG_TUSB_OS == OPT_OS_NONE +volatile uint32_t system_ticks = 0u; +void SysTick_Handler(void) +{ + system_ticks++; +} + +uint32_t board_millis(void) +{ + return system_ticks; +} +#endif diff --git a/hw/bsp/msp432e4/family.mk b/hw/bsp/msp432e4/family.mk new file mode 100644 index 000000000..d0ea13456 --- /dev/null +++ b/hw/bsp/msp432e4/family.mk @@ -0,0 +1,48 @@ +DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/ti + +CFLAGS += \ + -flto \ + -mthumb \ + -mslow-flash-data \ + -mabi=aapcs \ + -mcpu=cortex-m4 \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -D__MSP432E401Y__ \ + -DCFG_TUSB_MCU=OPT_MCU_MSP432E4xx + +# All source paths should be relative to the top level. +LD_FILE = hw/mcu/ti/msp432e4/Source/msp432e401y.ld +LDINC += $(TOP)/hw/mcu/ti/msp432e4/Include +LDFLAGS += $(addprefix -L,$(LDINC)) + +MCU_DIR = hw/mcu/ti/msp432e4 + +SRC_C += \ + src/portable/mentor/dcd_musb.c \ + $(MCU_DIR)/Source/system_msp432e401y.c + +INC += \ + $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ + $(TOP)/$(MCU_DIR)/Include \ + $(TOP)/$(BOARD_PATH) + +SRC_S += $(MCU_DIR)/Source/startup_msp432e411y_gcc.S + +# For freeRTOS port source +FREERTOS_PORT = ARM_CM4F + +# export for libmsp430.so to same installation +ifneq ($(OS),Windows_NT) +export LD_LIBRARY_PATH=$(dir $(shell which MSP430Flasher)) +endif + +# flash target using TI MSP430-Flasher +# http://www.ti.com/tool/MSP430-FLASHER +# Please add its installation dir to PATH +flash: $(BUILD)/$(PROJECT).hex + MSP430Flasher -w $< -z [VCC] + +# flash target using mspdebug. +flash-mspdebug: $(BUILD)/$(PROJECT).elf + $(MSPDEBUG) tilib "prog $<" --allow-fw-update diff --git a/src/device/dcd_attr.h b/src/device/dcd_attr.h index 15d8ce204..1befa89b6 100644 --- a/src/device/dcd_attr.h +++ b/src/device/dcd_attr.h @@ -143,7 +143,7 @@ #define DCD_ATTR_ENDPOINT_EXCLUSIVE_NUMBER //------------- TI -------------// -#elif TU_CHECK_MCU(OPT_MCU_MSP430x5xx) +#elif TU_CHECK_MCU(OPT_MCU_MSP430x5xx, OPT_MCU_MSP432E4xx) #define DCD_ATTR_ENDPOINT_MAX 8 //------------- ValentyUSB -------------// diff --git a/src/tusb_option.h b/src/tusb_option.h index e33d5a057..aaf4f3657 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -86,6 +86,7 @@ // TI MSP430 #define OPT_MCU_MSP430x5xx 500 ///< TI MSP430x5xx +#define OPT_MCU_MSP432E4xx 510 ///< TI MSP432E4xx // ValentyUSB eptri #define OPT_MCU_VALENTYUSB_EPTRI 600 ///< Fomu eptri config -- cgit v1.3.1 From 50ca0dda2ca4fe32f681f2955c9ec39355e3082e Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Sat, 30 Oct 2021 23:41:23 +0900 Subject: Add dcd_musb.c --- hw/bsp/msp432e4/family.c | 2 + hw/bsp/msp432e4/family.mk | 17 +- src/portable/mentor/musb/dcd_musb.c | 836 ++++++++++++++++++++++++++++++++++++ 3 files changed, 845 insertions(+), 10 deletions(-) create mode 100644 src/portable/mentor/musb/dcd_musb.c diff --git a/hw/bsp/msp432e4/family.c b/hw/bsp/msp432e4/family.c index 3bb36042d..567d5dc93 100644 --- a/hw/bsp/msp432e4/family.c +++ b/hw/bsp/msp432e4/family.c @@ -122,6 +122,8 @@ void board_init(void) for (int i = 0; i < 16; ++i) __NOP(); SYSCTL->SRUSB = 0u; + USB0->CC = USB_CC_CLKEN | (3u << USB_CC_CLKDIV_S); /* 60MHz = 240MHz / 4 */ + __DMB(); /* Wait for completion of opening of the clock gate */ } //--------------------------------------------------------------------+ diff --git a/hw/bsp/msp432e4/family.mk b/hw/bsp/msp432e4/family.mk index d0ea13456..aad5c77e8 100644 --- a/hw/bsp/msp432e4/family.mk +++ b/hw/bsp/msp432e4/family.mk @@ -11,6 +11,9 @@ CFLAGS += \ -D__MSP432E401Y__ \ -DCFG_TUSB_MCU=OPT_MCU_MSP432E4xx +# mcu driver cause following warnings +CFLAGS += -Wno-error=cast-qual -Wno-error=format= + # All source paths should be relative to the top level. LD_FILE = hw/mcu/ti/msp432e4/Source/msp432e401y.ld LDINC += $(TOP)/hw/mcu/ti/msp432e4/Include @@ -19,7 +22,7 @@ LDFLAGS += $(addprefix -L,$(LDINC)) MCU_DIR = hw/mcu/ti/msp432e4 SRC_C += \ - src/portable/mentor/dcd_musb.c \ + src/portable/mentor/musb/dcd_musb.c \ $(MCU_DIR)/Source/system_msp432e401y.c INC += \ @@ -37,12 +40,6 @@ ifneq ($(OS),Windows_NT) export LD_LIBRARY_PATH=$(dir $(shell which MSP430Flasher)) endif -# flash target using TI MSP430-Flasher -# http://www.ti.com/tool/MSP430-FLASHER -# Please add its installation dir to PATH -flash: $(BUILD)/$(PROJECT).hex - MSP430Flasher -w $< -z [VCC] - -# flash target using mspdebug. -flash-mspdebug: $(BUILD)/$(PROJECT).elf - $(MSPDEBUG) tilib "prog $<" --allow-fw-update +# For flash-jlink target +JLINK_DEVICE = MSP432E401Y +JLINK_IF = SWD diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c new file mode 100644 index 000000000..f073cd93f --- /dev/null +++ b/src/portable/mentor/musb/dcd_musb.c @@ -0,0 +1,836 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Koji KITAYAMA + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "tusb_option.h" + +#if CFG_TUSB_MCU == OPT_MCU_MSP432E4xx + +#if __GNUC__ > 8 && defined(__ARM_FEATURE_UNALIGNED) +/* GCC warns that an address may be unaligned, even though + * the target CPU has the capability for unaligned memory access. */ +_Pragma("GCC diagnostic ignored \"-Waddress-of-packed-member\""); +#endif + +#include "device/dcd.h" +#include "msp.h" + +/*------------------------------------------------------------------ + * MACRO TYPEDEF CONSTANT ENUM DECLARATION + *------------------------------------------------------------------*/ +#define REQUEST_TYPE_INVALID (0xFFu) + +typedef struct { + uint_fast16_t beg; /* offset of including first element */ + uint_fast16_t end; /* offset of excluding the last element */ +} free_block_t; + +typedef struct TU_ATTR_PACKED { + uint16_t TXMAXP; + uint8_t TXCSRL; + uint8_t TXCSRH; + uint16_t RXMAXP; + uint8_t RXCSRL; + uint8_t RXCSRH; + uint16_t RXCOUNT; + uint16_t RESERVED[3]; +} hw_endpoint_t; + +typedef union { + uint8_t u8; + uint16_t u16; + uint32_t u32; +} hw_fifo_t; + +typedef struct TU_ATTR_PACKED +{ + void *buf; /* the start address of a transfer data buffer */ + uint16_t length; /* the number of bytes in the buffer */ + uint16_t remaining; /* the number of bytes remaining in the buffer */ +} pipe_state_t; + +typedef struct +{ + tusb_control_request_t setup_packet; + uint16_t remaining_ctrl; /* The number of bytes remaining in data stage of control transfer. */ + int8_t status_out; + pipe_state_t pipe0; + pipe_state_t pipe[2][7]; +} dcd_data_t; + +/*------------------------------------------------------------------ + * INTERNAL OBJECT & FUNCTION DECLARATION + *------------------------------------------------------------------*/ +static dcd_data_t _dcd; + + +static inline free_block_t *find_containing_block(free_block_t *beg, free_block_t *end, uint_fast16_t addr) +{ + free_block_t *cur = beg; + for (; cur < end && ((addr < cur->beg) || (cur->end <= addr)); ++cur) ; + return cur; +} + +static inline int update_free_block_list(free_block_t *blks, unsigned num, uint_fast16_t addr, uint_fast16_t size) +{ + free_block_t *p = find_containing_block(blks, blks + num, addr); + TU_ASSERT(p != blks + num, -2); + if (p->beg == addr) { + /* Shrink block */ + p->beg = addr + size; + if (p->beg != p->end) return 0; + /* remove block */ + free_block_t *end = blks + num; + while (p + 1 < end) { + *p = *(p + 1); + ++p; + } + return -1; + } else { + /* Split into 2 blocks */ + free_block_t tmp = { + .beg = addr + size, + .end = p->end + }; + p->end = addr; + if (p->beg == p->end) { + if (tmp.beg != tmp.end) { + *p = tmp; + return 0; + } + /* remove block */ + free_block_t *end = blks + num; + while (p + 1 < end) { + *p = *(p + 1); + ++p; + } + return -1; + } + if (tmp.beg == tmp.end) return 0; + blks[num] = tmp; + return 1; + } +} + +static inline unsigned free_block_size(free_block_t const *blk) +{ + return blk->end - blk->beg; +} + +#if 0 +static inline void print_block_list(free_block_t const *blk, unsigned num) +{ + TU_LOG1("*************\n"); + for (unsigned i = 0; i < num; ++i) { + TU_LOG1(" Blk%u %u %u\n", i, blk->beg, blk->end); + ++blk; + } +} +#else +#define print_block_list(a,b) +#endif + +static unsigned find_free_memory(uint_fast16_t size_in_log2_minus3) +{ + free_block_t free_blocks[2 * (DCD_ATTR_ENDPOINT_MAX - 1)]; + unsigned num_blocks = 1; + + /* Initialize free memory block list */ + free_blocks[0].beg = 64 / 8; + free_blocks[0].end = (4 << 10) / 8; /* 4KiB / 8 bytes */ + for (int i = 1; i < DCD_ATTR_ENDPOINT_MAX; ++i) { + uint_fast16_t addr; + int num; + USB0->EPIDX = i; + addr = USB0->TXFIFOADD; + if (addr) { + unsigned sz = USB0->TXFIFOSZ; + unsigned sft = (sz & USB_TXFIFOSZ_SIZE_M) + ((sz & USB_TXFIFOSZ_DPB) ? 1: 0); + num = update_free_block_list(free_blocks, num_blocks, addr, 1 << sft); + TU_ASSERT(-2 < num, 0); + num_blocks += num; + print_block_list(free_blocks, num_blocks); + } + addr = USB0->RXFIFOADD; + if (addr) { + unsigned sz = USB0->RXFIFOSZ; + unsigned sft = (sz & USB_RXFIFOSZ_SIZE_M) + ((sz & USB_RXFIFOSZ_DPB) ? 1: 0); + num = update_free_block_list(free_blocks, num_blocks, addr, 1 << sft); + TU_ASSERT(-2 < num, 0); + num_blocks += num; + print_block_list(free_blocks, num_blocks); + } + } + print_block_list(free_blocks, num_blocks); + + /* Find the best fit memory block */ + uint_fast16_t size_in_8byte_unit = 1 << size_in_log2_minus3; + free_block_t const *min = NULL; + uint_fast16_t min_sz = 0xFFFFu; + free_block_t const *end = &free_blocks[num_blocks]; + for (free_block_t const *cur = &free_blocks[0]; cur < end; ++cur) { + uint_fast16_t sz = free_block_size(cur); + if (sz < size_in_8byte_unit) continue; + if (size_in_8byte_unit == sz) return cur->beg; + if (sz < min_sz) min = cur; + } + TU_ASSERT(min, 0); + return min->beg; +} + +static inline volatile hw_endpoint_t* edpt_regs(unsigned epnum_minus1) +{ + volatile hw_endpoint_t *regs = (volatile hw_endpoint_t*)((uintptr_t)&USB0->TXMAXP1); + return regs + epnum_minus1; +} + +static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) +{ + volatile hw_fifo_t *reg = (volatile hw_fifo_t*)fifo; + uintptr_t addr = (uintptr_t)buf; + while (len >= 4) { + reg->u32 = *(uint32_t const *)addr; + addr += 4; + len -= 4; + } + if (len >= 2) { + reg->u16 = *(uint16_t const *)addr; + addr += 2; + len -= 2; + } + if (len) { + reg->u8 = *(uint8_t const *)addr; + } +} + +static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len) +{ + volatile hw_fifo_t *reg = (volatile hw_fifo_t*)fifo; + uintptr_t addr = (uintptr_t)buf; + while (len >= 4) { + *(uint32_t *)addr = reg->u32; + addr += 4; + len -= 4; + } + if (len >= 2) { + *(uint32_t *)addr = reg->u16; + addr += 2; + len -= 2; + } + if (len) { + *(uint32_t *)addr = reg->u8; + } +} + +static void process_setup_packet(uint8_t rhport) +{ + uint32_t *p = (void*)&_dcd.setup_packet; + p[0] = USB0->FIFO0_WORD; + p[1] = USB0->FIFO0_WORD; + + _dcd.pipe0.buf = NULL; + _dcd.pipe0.length = 0; + _dcd.pipe0.remaining = 0; + dcd_event_setup_received(rhport, (const uint8_t*)(uintptr_t)&_dcd.setup_packet, true); + + const unsigned len = _dcd.setup_packet.wLength; + _dcd.remaining_ctrl = len; + const unsigned dir_in = tu_edpt_dir(_dcd.setup_packet.bmRequestType); + /* Clear RX FIFO and reverse the transaction direction */ + if (len && dir_in) USB0->CSRL0 = USB_CSRL0_RXRDYC; +} + +static bool handle_xfer_in(uint_fast8_t ep_addr) +{ + unsigned epnum_minus1 = tu_edpt_number(ep_addr) - 1; + pipe_state_t *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1]; + const unsigned rem = pipe->remaining; + + if (!rem) { + pipe->buf = NULL; + return true; + } + + volatile hw_endpoint_t *regs = edpt_regs(epnum_minus1); + const unsigned mps = regs->TXMAXP; + const unsigned len = TU_MIN(mps, rem); + void *buf = pipe->buf; + // TU_LOG1(" %p mps %d len %d rem %d\n", buf, mps, len, rem); + if (len) { + pipe_write_packet(buf, &USB0->FIFO1_WORD + epnum_minus1, len); + pipe->buf = buf + len; + pipe->remaining = rem - len; + } + regs->TXCSRL = USB_TXCSRL1_TXRDY; + // TU_LOG1(" TXCSRL%d = %x %d\n", epnum_minus1 + 1, regs->TXCSRL, rem - len); + return false; +} + +static bool handle_xfer_out(uint_fast8_t ep_addr) +{ + unsigned epnum_minus1 = tu_edpt_number(ep_addr) - 1; + pipe_state_t *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1]; + volatile hw_endpoint_t *regs = edpt_regs(epnum_minus1); + // TU_LOG1(" RXCSRL%d = %x\n", epnum_minus1 + 1, regs->RXCSRL); + + TU_ASSERT(regs->RXCSRL & USB_RXCSRL1_RXRDY); + + const unsigned mps = regs->RXMAXP; + const unsigned rem = pipe->remaining; + const unsigned vld = regs->RXCOUNT; + const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); + void *buf = pipe->buf; + if (len) { + pipe_read_packet(buf, &USB0->FIFO1_WORD + epnum_minus1, len); + pipe->buf = buf + len; + pipe->remaining = rem - len; + } + if ((len < mps) || (rem == len)) { + pipe->buf = NULL; + return NULL != buf; + } + regs->RXCSRL = 0; /* Clear RXRDY bit */ + return false; +} + +static bool edpt_n_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) +{ + (void)rhport; + + unsigned epnum_minus1 = tu_edpt_number(ep_addr) - 1; + unsigned dir_in = tu_edpt_dir(ep_addr); + + pipe_state_t *pipe = &_dcd.pipe[dir_in][epnum_minus1]; + pipe->buf = buffer; + pipe->length = total_bytes; + pipe->remaining = total_bytes; + + if (dir_in) { + handle_xfer_in(ep_addr); + } else { + volatile hw_endpoint_t *regs = edpt_regs(epnum_minus1); + if (regs->RXCSRL & USB_RXCSRL1_RXRDY) regs->RXCSRL = 0; + } + return true; +} + +static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) +{ + (void)rhport; + TU_ASSERT(total_bytes <= 64); /* Current implementation supports for only up to 64 bytes. */ + + const unsigned req = _dcd.setup_packet.bmRequestType; + TU_ASSERT(req != REQUEST_TYPE_INVALID || total_bytes == 0); + + if (req == REQUEST_TYPE_INVALID || _dcd.status_out) { + /* STATUS OUT stage. + * MUSB controller automatically handles STATUS OUT packets without + * software helps. We do not have to do anything. And STATUS stage + * may have already finished and received the next setup packet + * without calling this function, so we have no choice but to + * invoke the callback function of status packet here. */ + // TU_LOG1(" STATUS OUT USB0->CSRL0 = %x\n", USB0->CSRL0); + _dcd.status_out = 0; + if (req == REQUEST_TYPE_INVALID) { + dcd_event_xfer_complete(rhport, ep_addr, total_bytes, XFER_RESULT_SUCCESS, false); + } else { + /* The next setup packet has already been received, it aborts + * invoking callback function to avoid confusing TUSB stack. */ + TU_LOG1("Drop CONTROL_STAGE_ACK\n"); + } + return true; + } + const unsigned dir_in = tu_edpt_dir(ep_addr); + if (tu_edpt_dir(req) == dir_in) { /* DATA stage */ + TU_ASSERT(total_bytes <= _dcd.remaining_ctrl); + const unsigned rem = _dcd.remaining_ctrl; + const unsigned len = TU_MIN(TU_MIN(rem, 64), total_bytes); + if (dir_in) { + pipe_write_packet(buffer, &USB0->FIFO0_WORD, len); + + _dcd.pipe0.buf = buffer + len; + _dcd.pipe0.length = len; + _dcd.pipe0.remaining = 0; + + _dcd.remaining_ctrl = rem - len; + if ((len < 64) || (rem == len)) { + _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; /* Change to STATUS/SETUP stage */ + _dcd.status_out = 1; + /* Flush TX FIFO and reverse the transaction direction. */ + USB0->CSRL0 = USB_CSRL0_TXRDY | USB_CSRL0_DATAEND; + } else { + USB0->CSRL0 = USB_CSRL0_TXRDY; /* Flush TX FIFO to return ACK. */ + } + // TU_LOG1(" IN USB0->CSRL0 = %x\n", USB0->CSRL0); + } else { + // TU_LOG1(" OUT USB0->CSRL0 = %x\n", USB0->CSRL0); + _dcd.pipe0.buf = buffer; + _dcd.pipe0.length = len; + _dcd.pipe0.remaining = len; + USB0->CSRL0 = USB_CSRL0_RXRDYC; /* Clear RX FIFO to return ACK. */ + } + } else if (dir_in) { + // TU_LOG1(" STATUS IN USB0->CSRL0 = %x\n", USB0->CSRL0); + _dcd.pipe0.buf = NULL; + _dcd.pipe0.length = 0; + _dcd.pipe0.remaining = 0; + /* Clear RX FIFO and reverse the transaction direction */ + USB0->CSRL0 = USB_CSRL0_RXRDYC | USB_CSRL0_DATAEND; + } + return true; +} + +static void process_ep0(uint8_t rhport) +{ + uint_fast8_t csrl = USB0->CSRL0; + + // TU_LOG1(" EP0 USB0->CSRL0 = %x\n", csrl); + + if (csrl & USB_CSRL0_STALLED) { + /* Returned STALL packet to HOST. */ + USB0->CSRL0 = 0; /* Clear STALL */ + return; + } + + unsigned req = _dcd.setup_packet.bmRequestType; + if (csrl & USB_CSRL0_SETEND) { + TU_LOG1(" ABORT by the next packets\n"); + USB0->CSRL0 = USB_CSRL0_SETENDC; + if (req != REQUEST_TYPE_INVALID && _dcd.pipe0.buf) { + /* DATA stage was aborted by receiving STATUS or SETUP packet. */ + _dcd.pipe0.buf = NULL; + _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; + dcd_event_xfer_complete(rhport, + req & TUSB_DIR_IN_MASK, + _dcd.pipe0.length - _dcd.pipe0.remaining, + XFER_RESULT_SUCCESS, true); + } + req = REQUEST_TYPE_INVALID; + if (!(csrl & USB_CSRL0_RXRDY)) return; /* Received SETUP packet */ + } + + if (csrl & USB_CSRL0_RXRDY) { + /* Received SETUP or DATA OUT packet */ + if (req == REQUEST_TYPE_INVALID) { + /* SETUP */ + TU_ASSERT(sizeof(tusb_control_request_t) == USB0->COUNT0,); + process_setup_packet(rhport); + return; + } + if (_dcd.pipe0.buf) { + /* DATA OUT */ + const unsigned vld = USB0->COUNT0; + const unsigned rem = _dcd.pipe0.remaining; + const unsigned len = TU_MIN(TU_MIN(rem, 64), vld); + pipe_read_packet(_dcd.pipe0.buf, &USB0->FIFO0_WORD, len); + + _dcd.pipe0.remaining = rem - len; + _dcd.remaining_ctrl -= len; + + _dcd.pipe0.buf = NULL; + dcd_event_xfer_complete(rhport, + tu_edpt_addr(0, TUSB_DIR_OUT), + _dcd.pipe0.length - _dcd.pipe0.remaining, + XFER_RESULT_SUCCESS, true); + } + return; + } + + /* When CSRL0 is zero, it means that completion of sending a any length packet + * or receiving a zero length packet. */ + if (req != REQUEST_TYPE_INVALID && !tu_edpt_dir(req)) { + /* STATUS IN */ + if (*(const uint16_t*)(uintptr_t)&_dcd.setup_packet == 0x0500) { + /* The address must be changed on completion of the control transfer. */ + USB0->FADDR = (uint8_t)_dcd.setup_packet.wValue; + } + _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; + dcd_event_xfer_complete(rhport, + tu_edpt_addr(0, TUSB_DIR_IN), + _dcd.pipe0.length - _dcd.pipe0.remaining, + XFER_RESULT_SUCCESS, true); + return; + } + if (_dcd.pipe0.buf) { + /* DATA IN */ + _dcd.pipe0.buf = NULL; + dcd_event_xfer_complete(rhport, + tu_edpt_addr(0, TUSB_DIR_IN), + _dcd.pipe0.length - _dcd.pipe0.remaining, + XFER_RESULT_SUCCESS, true); + } +} + +static void process_edpt_n(uint8_t rhport, uint_fast8_t ep_addr) +{ + bool completed; + const unsigned dir_in = tu_edpt_dir(ep_addr); + const unsigned epn_minus1 = tu_edpt_number(ep_addr) - 1; + + volatile hw_endpoint_t *regs = edpt_regs(epn_minus1); + if (dir_in) { + // TU_LOG1(" TXCSRL%d = %x\n", epn_minus1 + 1, regs->TXCSRL); + if (regs->TXCSRL & USB_TXCSRL1_STALLED) { + regs->TXCSRL &= ~(USB_TXCSRL1_STALLED | USB_TXCSRL1_UNDRN); + return; + } + completed = handle_xfer_in(ep_addr); + } else { + // TU_LOG1(" RXCSRL%d = %x\n", epn_minus1 + 1, regs->RXCSRL); + if (regs->RXCSRL & USB_RXCSRL1_STALLED) { + regs->RXCSRL &= ~(USB_RXCSRL1_STALLED | USB_RXCSRL1_OVER); + return; + } + completed = handle_xfer_out(ep_addr); + } + + if (completed) { + pipe_state_t *pipe = &_dcd.pipe[dir_in][tu_edpt_number(ep_addr) - 1]; + dcd_event_xfer_complete(rhport, ep_addr, + pipe->length - pipe->remaining, + XFER_RESULT_SUCCESS, true); + } +} + +static void process_bus_reset(uint8_t rhport) +{ + /* When bmRequestType is REQUEST_TYPE_INVALID(0xFF), + * a control transfer state is SETUP or STATUS stage. */ + _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; + _dcd.status_out = 0; + /* When pipe0.buf has not NULL, DATA stage works in progress. */ + _dcd.pipe0.buf = NULL; + + /* Clear FIFO settings */ + for (unsigned i = 1; i < DCD_ATTR_ENDPOINT_MAX; ++i) { + USB0->EPIDX = i; + USB0->TXFIFOSZ = 0; + USB0->TXFIFOADD = 0; + USB0->RXFIFOSZ = 0; + USB0->RXFIFOADD = 0; + } + dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true); +} + +/*------------------------------------------------------------------ + * Device API + *------------------------------------------------------------------*/ + +void dcd_init(uint8_t rhport) +{ + (void)rhport; + USB0->IE |= USB_IE_SUSPND; + NVIC_ClearPendingIRQ(USB0_IRQn); + + dcd_connect(rhport); +} + +void dcd_int_enable(uint8_t rhport) +{ + (void)rhport; + NVIC_EnableIRQ(USB0_IRQn); +} + +void dcd_int_disable(uint8_t rhport) +{ + (void)rhport; + NVIC_DisableIRQ(USB0_IRQn); +} + +// Receive Set Address request, mcu port must also include status IN response +void dcd_set_address(uint8_t rhport, uint8_t dev_addr) +{ + (void)rhport; + (void)dev_addr; + _dcd.pipe0.buf = NULL; + _dcd.pipe0.length = 0; + _dcd.pipe0.remaining = 0; + /* Clear RX FIFO to return ACK. */ + USB0->CSRL0 = USB_CSRL0_RXRDYC | USB_CSRL0_DATAEND; +} + +// Wake up host +void dcd_remote_wakeup(uint8_t rhport) +{ + (void)rhport; + USB0->POWER |= USB_POWER_RESUME; + + unsigned cnt = SystemCoreClock / 1000; + while (cnt--) __NOP(); + + USB0->POWER &= ~USB_POWER_RESUME; +} + +// Connect by enabling internal pull-up resistor on D+/D- +void dcd_connect(uint8_t rhport) +{ + (void)rhport; + USB0->POWER |= USB_POWER_SOFTCONN; +} + +// Disconnect by disabling internal pull-up resistor on D+/D- +void dcd_disconnect(uint8_t rhport) +{ + (void)rhport; + USB0->POWER &= ~USB_POWER_SOFTCONN; +} + +//--------------------------------------------------------------------+ +// Endpoint API +//--------------------------------------------------------------------+ + +// Configure endpoint's registers according to descriptor +bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) +{ + (void) rhport; + + const unsigned ep_addr = ep_desc->bEndpointAddress; + const unsigned epn = tu_edpt_number(ep_addr); + const unsigned dir_in = tu_edpt_dir(ep_addr); + const unsigned xfer = ep_desc->bmAttributes.xfer; + const unsigned mps = tu_edpt_packet_size(ep_desc); + + TU_ASSERT(epn < DCD_ATTR_ENDPOINT_MAX); + + pipe_state_t *pipe = &_dcd.pipe[dir_in][epn - 1]; + pipe->buf = NULL; + pipe->length = 0; + pipe->remaining = 0; + + volatile hw_endpoint_t *regs = edpt_regs(epn - 1); + if (dir_in) { + regs->TXMAXP = mps; + regs->TXCSRH = (xfer == TUSB_XFER_ISOCHRONOUS) ? USB_TXCSRH1_ISO : 0; + if (regs->TXCSRL & USB_TXCSRL1_TXRDY) + regs->TXCSRL = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH; + else + regs->TXCSRL = USB_TXCSRL1_CLRDT; + } else { + regs->RXMAXP = mps; + regs->RXCSRH = (xfer == TUSB_XFER_ISOCHRONOUS) ? USB_RXCSRH1_ISO : 0; + if (regs->RXCSRL & USB_RXCSRL1_RXRDY) + regs->RXCSRL = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH; + else + regs->RXCSRL = USB_RXCSRL1_CLRDT; + } + + /* Setup FIFO */ + int size_in_log2_minus3 = 28 - TU_MIN(28, __CLZ((uint32_t)mps)); + if ((8u << size_in_log2_minus3) < mps) ++size_in_log2_minus3; + unsigned addr = find_free_memory(size_in_log2_minus3); + TU_ASSERT(addr); + + USB0->EPIDX = epn; + if (dir_in) { + USB0->TXFIFOADD = addr; + USB0->TXFIFOSZ = size_in_log2_minus3; + } else { + USB0->RXFIFOADD = addr; + USB0->RXFIFOSZ = size_in_log2_minus3; + } + + return true; +} + +void dcd_edpt_close_all(uint8_t rhport) +{ + (void) rhport; + volatile hw_endpoint_t *regs = (volatile hw_endpoint_t *)(uintptr_t)&USB0->TXMAXP1; + unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn); + NVIC_DisableIRQ(USB0_IRQn); + for (unsigned i = 1; i < DCD_ATTR_ENDPOINT_MAX; ++i) { + regs->TXMAXP = 0; + regs->TXCSRH = 0; + if (regs->TXCSRL & USB_TXCSRL1_TXRDY) + regs->TXCSRL = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH; + else + regs->TXCSRL = USB_TXCSRL1_CLRDT; + + regs->RXMAXP = 0; + regs->RXCSRH = 0; + if (regs->RXCSRL & USB_RXCSRL1_RXRDY) + regs->RXCSRL = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH; + else + regs->RXCSRL = USB_RXCSRL1_CLRDT; + + USB0->EPIDX = i; + USB0->TXFIFOSZ = 0; + USB0->TXFIFOADD = 0; + USB0->RXFIFOSZ = 0; + USB0->RXFIFOADD = 0; + } + if (ie) NVIC_EnableIRQ(USB0_IRQn); +} + +void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) +{ + (void)rhport; + unsigned const epn = tu_edpt_number(ep_addr); + unsigned const dir_in = tu_edpt_dir(ep_addr); + + hw_endpoint_t volatile *regs = edpt_regs(epn - 1); + unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn); + NVIC_DisableIRQ(USB0_IRQn); + if (dir_in) { + regs->TXMAXP = 0; + regs->TXCSRH = 0; + if (regs->TXCSRL & USB_TXCSRL1_TXRDY) + regs->TXCSRL = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH; + else + regs->TXCSRL = USB_TXCSRL1_CLRDT; + + USB0->EPIDX = epn; + USB0->TXFIFOSZ = 0; + USB0->TXFIFOADD = 0; + } else { + regs->RXMAXP = 0; + regs->RXCSRH = 0; + if (regs->RXCSRL & USB_RXCSRL1_RXRDY) + regs->RXCSRL = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH; + else + regs->RXCSRL = USB_RXCSRL1_CLRDT; + + USB0->EPIDX = epn; + USB0->RXFIFOSZ = 0; + USB0->RXFIFOADD = 0; + } + if (ie) NVIC_EnableIRQ(USB0_IRQn); +} + +// Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack +bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) +{ + (void)rhport; + bool ret; + // TU_LOG1("X %x %d\n", ep_addr, total_bytes); + + unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn); + NVIC_DisableIRQ(USB0_IRQn); + if (tu_edpt_number(ep_addr)) + ret = edpt_n_xfer(rhport, ep_addr, buffer, total_bytes); + else + ret = edpt0_xfer(rhport, ep_addr, buffer, total_bytes); + if (ie) NVIC_EnableIRQ(USB0_IRQn); + return ret; +} + +// Submit a transfer where is managed by FIFO, When complete dcd_event_xfer_complete() is invoked to notify the stack - optional, however, must be listed in usbd.c +bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes) +{ + (void) rhport; + (void) ep_addr; + (void) ff; + (void) total_bytes; + return false; +} + +// Stall endpoint +void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) +{ + (void)rhport; + unsigned const epn = tu_edpt_number(ep_addr); + unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn); + NVIC_DisableIRQ(USB0_IRQn); + if (0 == epn) { + if (!ep_addr) { /* Ignore EP80 */ + _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; + _dcd.pipe0.buf = NULL; + USB0->CSRL0 = USB_CSRL0_STALL; + } + } else { + volatile hw_endpoint_t *regs = edpt_regs(epn - 1); + if (tu_edpt_dir(ep_addr)) { /* IN */ + regs->TXCSRL = USB_TXCSRL1_STALL; + } else { /* OUT */ + TU_ASSERT(!(regs->RXCSRL & USB_RXCSRL1_RXRDY),); + regs->RXCSRL = USB_RXCSRL1_STALL; + } + } + if (ie) NVIC_EnableIRQ(USB0_IRQn); +} + +// clear stall, data toggle is also reset to DATA0 +void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) +{ + (void)rhport; + unsigned const epn = tu_edpt_number(ep_addr); + hw_endpoint_t volatile *regs = edpt_regs(epn - 1); + unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn); + NVIC_DisableIRQ(USB0_IRQn); + if (tu_edpt_dir(ep_addr)) { /* IN */ + regs->TXCSRL = USB_TXCSRL1_CLRDT; + } else { /* OUT */ + regs->RXCSRL = USB_RXCSRL1_CLRDT; + } + if (ie) NVIC_EnableIRQ(USB0_IRQn); +} + +/*------------------------------------------------------------------- + * ISR + *-------------------------------------------------------------------*/ +void dcd_int_handler(uint8_t rhport) +{ + uint_fast8_t is, txis, rxis; + + is = USB0->IS; /* read and clear interrupt status */ + txis = USB0->TXIS; /* read and clear interrupt status */ + rxis = USB0->RXIS; /* read and clear interrupt status */ + // TU_LOG1("D%2x T%2x R%2x\n", is, txis, rxis); + + is &= USB0->IE; /* Clear disabled interrupts */ + if (is & USB_IS_DISCON) { + } + if (is & USB_IS_SOF) { + dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true); + } + if (is & USB_IS_RESET) { + process_bus_reset(rhport); + } + if (is & USB_IS_RESUME) { + dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true); + } + if (is & USB_IS_SUSPEND) { + dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); + } + + txis &= USB0->TXIE; /* Clear disabled interrupts */ + if (txis & USB_TXIE_EP0) { + process_ep0(rhport); + txis &= ~TU_BIT(0); + } + while (txis) { + unsigned const num = __builtin_ctz(txis); + process_edpt_n(rhport, tu_edpt_addr(num, TUSB_DIR_IN)); + txis &= ~TU_BIT(num); + } + rxis &= USB0->RXIE; /* Clear disabled interrupts */ + while (rxis) { + unsigned const num = __builtin_ctz(rxis); + process_edpt_n(rhport, tu_edpt_addr(num, TUSB_DIR_OUT)); + rxis &= ~TU_BIT(num); + } +} + +#endif -- cgit v1.3.1 From 0b3c8c4a59e993f7f51452b2bd3d0decdc56d6c9 Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Thu, 4 Nov 2021 22:36:36 +0900 Subject: Implement dcd_edpt_xfer_fifo for dcd_musb --- src/class/audio/audio_device.c | 3 +- src/portable/mentor/musb/dcd_musb.c | 66 +++++++++++++++++++++++++++++-------- 2 files changed, 55 insertions(+), 14 deletions(-) diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c index 28b1c1a7c..38bfc023b 100644 --- a/src/class/audio/audio_device.c +++ b/src/class/audio/audio_device.c @@ -102,7 +102,8 @@ CFG_TUSB_MCU == OPT_MCU_GD32VF103 || \ CFG_TUSB_MCU == OPT_MCU_LPC18XX || \ CFG_TUSB_MCU == OPT_MCU_LPC43XX || \ - CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX + CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \ + CFG_TUSB_MCU == OPT_MCU_MSP432E4xx #if TUD_AUDIO_PREFER_RING_BUFFER #define USE_LINEAR_BUFFER 0 #else diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c index f073cd93f..5a5aa51bc 100644 --- a/src/portable/mentor/musb/dcd_musb.c +++ b/src/portable/mentor/musb/dcd_musb.c @@ -77,7 +77,8 @@ typedef struct uint16_t remaining_ctrl; /* The number of bytes remaining in data stage of control transfer. */ int8_t status_out; pipe_state_t pipe0; - pipe_state_t pipe[2][7]; + pipe_state_t pipe[2][7]; /* pipe[direction][endpoint number - 1] */ + uint16_t pipe_buf_is_fifo[2]; /* Bitmap. Each bit means whether 1:TU_FIFO or 0:POD. */ } dcd_data_t; /*------------------------------------------------------------------ @@ -244,6 +245,30 @@ static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len) } } +static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigned len, unsigned dir) +{ + static const struct { + void (*tu_fifo_get_info)(tu_fifo_t *f, tu_fifo_buffer_info_t *info); + void (*tu_fifo_advance)(tu_fifo_t *f, uint16_t n); + void (*pipe_read_write)(void *buf, volatile void *fifo, unsigned len); + } ops[] = { + /* OUT */ {tu_fifo_get_write_info,tu_fifo_advance_write_pointer,pipe_read_packet}, + /* IN */ {tu_fifo_get_read_info, tu_fifo_advance_read_pointer, pipe_write_packet}, + }; + tu_fifo_buffer_info_t info; + ops[dir].tu_fifo_get_info(f, &info); + unsigned total_len = len; + len = TU_MIN(total_len, info.len_lin); + ops[dir].pipe_read_write(info.ptr_lin, fifo, len); + unsigned rem = total_len - len; + if (rem) { + len = TU_MIN(rem, info.len_wrap); + ops[dir].pipe_read_write(info.ptr_wrap, fifo, len); + rem -= len; + } + ops[dir].tu_fifo_advance(f, total_len - rem); +} + static void process_setup_packet(uint8_t rhport) { uint32_t *p = (void*)&_dcd.setup_packet; @@ -279,8 +304,12 @@ static bool handle_xfer_in(uint_fast8_t ep_addr) void *buf = pipe->buf; // TU_LOG1(" %p mps %d len %d rem %d\n", buf, mps, len, rem); if (len) { - pipe_write_packet(buf, &USB0->FIFO1_WORD + epnum_minus1, len); - pipe->buf = buf + len; + if (_dcd.pipe_buf_is_fifo[TUSB_DIR_IN] & TU_BIT(epnum_minus1)) { + pipe_read_write_packet_ff(buf, &USB0->FIFO1_WORD + epnum_minus1, len, TUSB_DIR_IN); + } else { + pipe_write_packet(buf, &USB0->FIFO1_WORD + epnum_minus1, len); + pipe->buf = buf + len; + } pipe->remaining = rem - len; } regs->TXCSRL = USB_TXCSRL1_TXRDY; @@ -303,8 +332,12 @@ static bool handle_xfer_out(uint_fast8_t ep_addr) const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); void *buf = pipe->buf; if (len) { - pipe_read_packet(buf, &USB0->FIFO1_WORD + epnum_minus1, len); - pipe->buf = buf + len; + if (_dcd.pipe_buf_is_fifo[TUSB_DIR_OUT] & TU_BIT(epnum_minus1)) { + pipe_read_write_packet_ff(buf, &USB0->FIFO1_WORD + epnum_minus1, len, TUSB_DIR_OUT); + } else { + pipe_read_packet(buf, &USB0->FIFO1_WORD + epnum_minus1, len); + pipe->buf = buf + len; + } pipe->remaining = rem - len; } if ((len < mps) || (rem == len)) { @@ -725,12 +758,13 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t (void)rhport; bool ret; // TU_LOG1("X %x %d\n", ep_addr, total_bytes); - + unsigned const epnum = tu_edpt_number(ep_addr); unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn); NVIC_DisableIRQ(USB0_IRQn); - if (tu_edpt_number(ep_addr)) + if (epnum) { + _dcd.pipe_buf_is_fifo[tu_edpt_dir(ep_addr)] &= ~TU_BIT(epnum - 1); ret = edpt_n_xfer(rhport, ep_addr, buffer, total_bytes); - else + } else ret = edpt0_xfer(rhport, ep_addr, buffer, total_bytes); if (ie) NVIC_EnableIRQ(USB0_IRQn); return ret; @@ -739,11 +773,17 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t // Submit a transfer where is managed by FIFO, When complete dcd_event_xfer_complete() is invoked to notify the stack - optional, however, must be listed in usbd.c bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes) { - (void) rhport; - (void) ep_addr; - (void) ff; - (void) total_bytes; - return false; + (void)rhport; + bool ret; + // TU_LOG1("X %x %d\n", ep_addr, total_bytes); + unsigned const epnum = tu_edpt_number(ep_addr); + TU_ASSERT(epnum); + unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn); + NVIC_DisableIRQ(USB0_IRQn); + _dcd.pipe_buf_is_fifo[tu_edpt_dir(ep_addr)] |= TU_BIT(epnum - 1); + ret = edpt_n_xfer(rhport, ep_addr, (uint8_t*)ff, total_bytes); + if (ie) NVIC_EnableIRQ(USB0_IRQn); + return ret; } // Stall endpoint -- cgit v1.3.1 From e4520e7aa7a0a585d79b8a345525a67cf2f39ef6 Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Fri, 5 Nov 2021 20:14:59 +0900 Subject: Add statements for FreeRTOS --- hw/bsp/board_mcu.h | 3 +++ hw/bsp/msp432e4/family.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h index 1e2577de0..ea2f23fe9 100644 --- a/hw/bsp/board_mcu.h +++ b/hw/bsp/board_mcu.h @@ -98,6 +98,9 @@ #elif CFG_TUSB_MCU == OPT_MCU_MSP430x5xx #include "msp430.h" +#elif CFG_TUSB_MCU == OPT_MCU_MSP432E4xx + #include "msp.h" + #elif CFG_TUSB_MCU == OPT_MCU_VALENTYUSB_EPTRI // no header needed diff --git a/hw/bsp/msp432e4/family.c b/hw/bsp/msp432e4/family.c index 567d5dc93..b20af563b 100644 --- a/hw/bsp/msp432e4/family.c +++ b/hw/bsp/msp432e4/family.c @@ -77,6 +77,9 @@ void board_init(void) SystemCoreClockUpdate(); #if CFG_TUSB_OS == OPT_OS_NONE SysTick_Config(SystemCoreClock / 1000); +#elif CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); #endif /* USR_LED1 PN1 */ -- cgit v1.3.1 From 23ef8b2c64aea2217254b34a8b34cf7cc6d4e364 Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Sat, 6 Nov 2021 19:32:15 +0900 Subject: Change the variables for a switch and a LED to symbols defined by the macros --- hw/bsp/msp432e4/boards/msp_exp432e401y/board.h | 12 ++++++------ hw/bsp/msp432e4/family.c | 27 ++++++++++++-------------- 2 files changed, 18 insertions(+), 21 deletions(-) diff --git a/hw/bsp/msp432e4/boards/msp_exp432e401y/board.h b/hw/bsp/msp432e4/boards/msp_exp432e401y/board.h index b449f3ca4..3130d663b 100644 --- a/hw/bsp/msp432e4/boards/msp_exp432e401y/board.h +++ b/hw/bsp/msp432e4/boards/msp_exp432e401y/board.h @@ -27,13 +27,13 @@ #ifndef BOARD_H_ #define BOARD_H_ -#define LED_PORT P1OUT -#define LED_PIN BIT0 -#define LED_STATE_ON 1 +#define CLK_LED 12u +#define GPIO_LED GPION +#define GPIO_LED_PIN 1u -#define BUTTON_PORT P1IN -#define BUTTON_PIN BIT1 -#define BUTTON_STATE_ACTIVE 0 +#define CLK_BUTTON 8u +#define GPIO_BUTTON GPIOJ +#define GPIO_BUTTON_PIN 0u #ifdef __cplusplus extern "C" { diff --git a/hw/bsp/msp432e4/family.c b/hw/bsp/msp432e4/family.c index b20af563b..7114da693 100644 --- a/hw/bsp/msp432e4/family.c +++ b/hw/bsp/msp432e4/family.c @@ -28,9 +28,6 @@ #include "board.h" #include "msp.h" -/* Frequency of the external crystal oscillator */ -#define XTAL_FREQUENCY 25000000UL - //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ @@ -82,17 +79,17 @@ void board_init(void) NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); #endif - /* USR_LED1 PN1 */ - SYSCTL->RCGCGPIO |= 1u << 12; - while (!(SYSCTL->PRGPIO & (1u << 12))) ; - GPION->DIR = 2u; - GPION->DEN = 2u; + /* USR_LED1 ON1 */ + SYSCTL->RCGCGPIO |= TU_BIT(CLK_LED); + while (!(SYSCTL->PRGPIO & TU_BIT(CLK_LED))) ; + GPIO_LED->DIR = TU_BIT(GPIO_LED_PIN); + GPIO_LED->DEN = TU_BIT(GPIO_LED_PIN); /* USR_SW1 PJ0 */ - SYSCTL->RCGCGPIO |= 1u << 8; - while (!(SYSCTL->PRGPIO & (1u << 8))) ; - GPIOJ->PUR = 1u; - GPIOJ->DEN = 1u; + SYSCTL->RCGCGPIO |= TU_BIT(CLK_BUTTON); + while (!(SYSCTL->PRGPIO & TU_BIT(CLK_BUTTON))) ; + GPIO_BUTTON->PUR = TU_BIT(GPIO_BUTTON_PIN); + GPIO_BUTTON->DEN = TU_BIT(GPIO_BUTTON_PIN); /* UART PA0,1 */ SYSCTL->RCGCGPIO |= 1u << 0; @@ -136,14 +133,14 @@ void board_init(void) void board_led_write(bool state) { if (state) - GPION->DATA |= 2u; + GPIO_LED->DATA |= TU_BIT(GPIO_LED_PIN); else - GPION->DATA &= ~2u; + GPIO_LED->DATA &= ~TU_BIT(GPIO_LED_PIN); } uint32_t board_button_read(void) { - return (GPIOJ->DATA & 1u) ? 0u : 1u; + return (GPIO_BUTTON->DATA & TU_BIT(GPIO_BUTTON_PIN)) ? 0u : 1u; } int board_uart_read(uint8_t * buf, int len) -- cgit v1.3.1 From 30d3bf8bec430c235bd0948687613455db8ff3b9 Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Sat, 6 Nov 2021 23:05:27 +0900 Subject: Update TI driver --- hw/mcu/ti | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/mcu/ti b/hw/mcu/ti index ed52d354c..143ed6cc2 160000 --- a/hw/mcu/ti +++ b/hw/mcu/ti @@ -1 +1 @@ -Subproject commit ed52d354c99e25a5e9db2376eb5e7058c81c3ebd +Subproject commit 143ed6cc20a7615d042b03b21e070197d473e6e5 -- cgit v1.3.1 From dd7eb368305ebf3c7e374341e037f1af22ce9e05 Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Sat, 6 Nov 2021 23:10:11 +0900 Subject: Remove unnecessary lines --- hw/bsp/msp432e4/family.mk | 5 ----- 1 file changed, 5 deletions(-) diff --git a/hw/bsp/msp432e4/family.mk b/hw/bsp/msp432e4/family.mk index aad5c77e8..ee7faa208 100644 --- a/hw/bsp/msp432e4/family.mk +++ b/hw/bsp/msp432e4/family.mk @@ -35,11 +35,6 @@ SRC_S += $(MCU_DIR)/Source/startup_msp432e411y_gcc.S # For freeRTOS port source FREERTOS_PORT = ARM_CM4F -# export for libmsp430.so to same installation -ifneq ($(OS),Windows_NT) -export LD_LIBRARY_PATH=$(dir $(shell which MSP430Flasher)) -endif - # For flash-jlink target JLINK_DEVICE = MSP432E401Y JLINK_IF = SWD -- cgit v1.3.1 From 26461d1efe956f5d23c58546364c6bdbffc246df Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Sun, 7 Nov 2021 18:25:11 +0900 Subject: Fix DCD_EVENT_XFER_COMPLETE was signaled, even after EP is closed --- src/portable/mentor/musb/dcd_musb.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c index 5a5aa51bc..04139dd78 100644 --- a/src/portable/mentor/musb/dcd_musb.c +++ b/src/portable/mentor/musb/dcd_musb.c @@ -556,6 +556,9 @@ static void process_bus_reset(uint8_t rhport) /* When pipe0.buf has not NULL, DATA stage works in progress. */ _dcd.pipe0.buf = NULL; + USB0->TXIE = 1; /* Enable only EP0 */ + USB0->RXIE = 0; + /* Clear FIFO settings */ for (unsigned i = 1; i < DCD_ATTR_ENDPOINT_MAX; ++i) { USB0->EPIDX = i; @@ -660,6 +663,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) regs->TXCSRL = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH; else regs->TXCSRL = USB_TXCSRL1_CLRDT; + USB0->TXIE |= TU_BIT(epn); } else { regs->RXMAXP = mps; regs->RXCSRH = (xfer == TUSB_XFER_ISOCHRONOUS) ? USB_RXCSRH1_ISO : 0; @@ -667,6 +671,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) regs->RXCSRL = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH; else regs->RXCSRL = USB_RXCSRL1_CLRDT; + USB0->RXIE |= TU_BIT(epn); } /* Setup FIFO */ @@ -693,6 +698,8 @@ void dcd_edpt_close_all(uint8_t rhport) volatile hw_endpoint_t *regs = (volatile hw_endpoint_t *)(uintptr_t)&USB0->TXMAXP1; unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn); NVIC_DisableIRQ(USB0_IRQn); + USB0->TXIE = 1; /* Enable only EP0 */ + USB0->RXIE = 0; for (unsigned i = 1; i < DCD_ATTR_ENDPOINT_MAX; ++i) { regs->TXMAXP = 0; regs->TXCSRH = 0; @@ -727,6 +734,7 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn); NVIC_DisableIRQ(USB0_IRQn); if (dir_in) { + USB0->TXIE &= ~TU_BIT(epn); regs->TXMAXP = 0; regs->TXCSRH = 0; if (regs->TXCSRL & USB_TXCSRL1_TXRDY) @@ -738,6 +746,7 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) USB0->TXFIFOSZ = 0; USB0->TXFIFOADD = 0; } else { + USB0->RXIE &= ~TU_BIT(epn); regs->RXMAXP = 0; regs->RXCSRH = 0; if (regs->RXCSRL & USB_RXCSRL1_RXRDY) -- cgit v1.3.1 From 23e6e0ef335fac28dc7731a62cca05f838a78caa Mon Sep 17 00:00:00 2001 From: hathach Date: Sun, 7 Nov 2021 13:41:32 +0700 Subject: merge pull request 670 for tm4c123gxl bsp --- hw/bsp/board_mcu.h | 3 + hw/bsp/ek-tm4c123gxl/board.mk | 50 ++++++++++++ hw/bsp/ek-tm4c123gxl/tm4c123.ld | 65 +++++++++++++++ hw/bsp/ek-tm4c123gxl/tm4c123gxl.c | 163 ++++++++++++++++++++++++++++++++++++++ src/tusb_option.h | 1 + 5 files changed, 282 insertions(+) create mode 100644 hw/bsp/ek-tm4c123gxl/board.mk create mode 100644 hw/bsp/ek-tm4c123gxl/tm4c123.ld create mode 100644 hw/bsp/ek-tm4c123gxl/tm4c123gxl.c diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h index ea2f23fe9..2928ea657 100644 --- a/hw/bsp/board_mcu.h +++ b/hw/bsp/board_mcu.h @@ -143,6 +143,9 @@ #elif CFG_TUSB_MCU == OPT_MCU_XMC4000 #include "xmc_device.h" +#elif CFG_TUSB_MCU == OPT_MCU_TM4C123 + #include "TM4C123.h" + #else #error "Missing MCU header" #endif diff --git a/hw/bsp/ek-tm4c123gxl/board.mk b/hw/bsp/ek-tm4c123gxl/board.mk new file mode 100644 index 000000000..f6522dc2c --- /dev/null +++ b/hw/bsp/ek-tm4c123gxl/board.mk @@ -0,0 +1,50 @@ + +DEPS_SUBMODULES += hw/mcu/ti + +CFLAGS += \ + -flto \ + -mthumb \ + -mabi=aapcs \ + -mcpu=cortex-m4 \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -DCFG_TUSB_MCU=OPT_MCU_TM4C123 \ + -uvectors \ + -DTM4C123GH6PM + +# lpc_types.h cause following errors +CFLAGS += -Wno-error=strict-prototypes + +MCU_DIR=hw/mcu/ti/tm4c123xx/ + +CMSIS=$(TOP)/hw/mcu/ti/tm4c123xx/CMSIS/5.7.0/CMSIS/Include + +TI_HDR=$(TOP)/hw/mcu/ti/tm4c123xx/Include/TM4C123/ + +# All source paths should be relative to the top level. + +LD_FILE = hw/bsp/$(BOARD)/tm4c123.ld + +INC += \ + $(CMSIS) \ + $(TI_HDR) \ + $(TOP)/hw/bsp + + +SRC_C += \ + $(MCU_DIR)/Source/system_TM4C123.c \ + $(MCU_DIR)/Source/GCC/tm4c123_startup.c + +# For TinyUSB port source +VENDOR = ti +CHIP_FAMILY = tm4c123xx + +# For freeRTOS port source +FREERTOS_PORT = ARM_CM4F + +# For flash-jlink target +JLINK_DEVICE = LPC1769 + +# flash using jlink +flash: $(BUILD)/$(PROJECT).elf + openocd -f board/ti_ek-tm4c123gxl.cfg -c "program $< verify reset exit" diff --git a/hw/bsp/ek-tm4c123gxl/tm4c123.ld b/hw/bsp/ek-tm4c123gxl/tm4c123.ld new file mode 100644 index 000000000..e2720a9ac --- /dev/null +++ b/hw/bsp/ek-tm4c123gxl/tm4c123.ld @@ -0,0 +1,65 @@ +ENTRY(Reset_Handler) + +_estack = 0x20008000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + + +MEMORY +{ + FLASH(rx) : ORIGIN = 0x00000000, LENGTH = 256K + SRAM(rwx) : ORIGIN = 0x20000000, LENGTH = 32K +} + +SECTIONS +{ + .text : + { + . = ALIGN(4) ; + *(.vectors) + *(.text) + *(.text.*) + *(.init) + *(.fini) + *(.rodata) + *(.rodata.*) + . = ALIGN(4) ; + __end_text = . ; + } >FLASH + + .data : AT(ADDR(.text) + SIZEOF(.text)) + { + . = ALIGN(4); + __start_data = . ; + __la_data = LOADADDR(.data); + *(.data) + *(.data.*) + . = ALIGN(4); + __end_data = . ; + + } >SRAM + + .bss : + { + . = ALIGN(4) ; + __start_bss = . ; + __bss_start__ = __start_bss; + *(.bss) + *(.bss.*) + *(.COMMON) + __end_bss = . ; + . = ALIGN(4); + }>SRAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >SRAM +} diff --git a/hw/bsp/ek-tm4c123gxl/tm4c123gxl.c b/hw/bsp/ek-tm4c123gxl/tm4c123gxl.c new file mode 100644 index 000000000..d78b0f7e3 --- /dev/null +++ b/hw/bsp/ek-tm4c123gxl/tm4c123gxl.c @@ -0,0 +1,163 @@ +#include +#include + +#define BOARD_UART UART0 +#define BOARD_UART_PORT GPIOA +#define BOARD_BTN_PORT GPIOF +#define BOARD_BTN 4 +#define BOARD_BTN_Msk (1u<<4) +#define LED_PORT GPIOF +#define LED_PIN_RED 1 +#define LED_PIN_BLUE 2 +#define LED_PIN_GREEN 3 +#define LED_STATE_ON 1 + +static void board_uart_init(void) +{ + SYSCTL->RCGCUART |= (1<<0); // Enable the clock to UART0 + SYSCTL->RCGCGPIO |= (1<<0); // Enable the clock to GPIOA + + GPIOA->AFSEL |= (1<<1)|(1<<0); // Enable the alternate function on pin PA0 & PA1 + GPIOA->PCTL |= (1<<0)|(1<<4); // Configure the GPIOPCTL register to select UART0 in PA0 and PA1 + GPIOA->DEN |= (1<<0)|(1<<1); // Enable the digital functionality in PA0 and PA1 + + /** BAUDRATE = 9600 bits per second, refer manual for calculation **/ + + UART0->CTL &= ~(1<<0); // Disable UART0 by clearing UARTEN bit in the UARTCTL register + UART0->IBRD = 325; // Write the integer portion of the BRD to the UARTIRD register + UART0->FBRD = 33; // Write the fractional portion of the BRD to the UARTFBRD registerer + + UART0->LCRH = (0x3<<5); // 8-bit, no parity, 1 stop bit + UART0->CC = 0x0; // Configure the UART clock source as system clock + + UART0->CTL = (1<<0)|(1<<8)|(1<<9); // UART0 Enable, Transmit Enable, Recieve Enable +} + +static void initialize_board_led(GPIOA_Type* port, uint8_t PinMsk, uint8_t dirmsk) +{ + /* Enable PortF Clock */ + SYSCTL -> RCGCGPIO |= (1<<5) ; + + /* Let the clock stabilize */ + while(! ((SYSCTL->PRGPIO) & (1<<5)) ) ; + + /* Port Digital Enable */ + port->DEN |= PinMsk; + + /* Set direction */ + port->DIR = dirmsk ; +} + +static void board_switch_init(void) +{ + GPIOF->DIR &= ~(1<PUR |= (1<DEN |= (1<DATA |= PinMsk; + else + port->DATA &= ~(PinMsk); +} + +static uint32_t ReadGPIOPin(GPIOA_Type *port, uint8_t pinMsk) +{ + return (port -> DATA & pinMsk) ; +} + +void board_init(void) +{ + SystemCoreClockUpdate(); + +#if CFG_TUSB_OS == OPT_OS_NONE + // 1ms tick timer + SysTick_Config(SystemCoreClock / 1000); +#elif CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); +#endif + + /* Reset USB */ + SYSCTL->SRCR2 |= (1u<<16); + + for (volatile uint8_t i=0; i<20; i++); + + SYSCTL->SRCR2 &= ~(1u<<16); + + /* Open the USB clock gate */ + SYSCTL->RCGCUSB |= (1<<0); + + /* Power-up USB PLL */ + SYSCTL->RCC2 &= ~(1u<<14); + + /* USB IO Initialization */ + SYSCTL->RCGCGPIO |= (1u<<3); + + /* Let the clock stabilize */ + while(!(SYSCTL->PRGPIO & (1u<<3))); + + /* USB IOs to Analog Mode */ + GPIOD->AFSEL &= ~ ( (1u<<4) | (1u<<5) ); + GPIOD->DEN &= ~ ( (1u<<4) | (1u<<5) ); + GPIOD->AMSEL |= ( (1u<<4) | (1u<<5) ); + + uint8_t leds = (1<FR &(1<<5)) != 0); // Poll until previous data was shofted out + UART0->DR= data[i]; // Write UART0 DATA REGISTER + } + + return len; +} + +int board_uart_read(uint8_t* buf, int len) +{ + (void) buf; (void) len; + return 0; +} + + +#if CFG_TUSB_OS == OPT_OS_NONE +volatile uint32_t system_ticks = 0; +void SysTick_Handler (void) +{ + system_ticks++; +} + +uint32_t board_millis(void) +{ + return system_ticks; +} +#endif + diff --git a/src/tusb_option.h b/src/tusb_option.h index aaf4f3657..50a922840 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -87,6 +87,7 @@ // TI MSP430 #define OPT_MCU_MSP430x5xx 500 ///< TI MSP430x5xx #define OPT_MCU_MSP432E4xx 510 ///< TI MSP432E4xx +#define OPT_MCU_TM4C123 511 ///< TI Tiva C 123x // ValentyUSB eptri #define OPT_MCU_VALENTYUSB_EPTRI 600 ///< Fomu eptri config -- cgit v1.3.1 From 91646d039c7dac8e16042c42c2d7197034111aeb Mon Sep 17 00:00:00 2001 From: hathach Date: Sun, 7 Nov 2021 17:45:16 +0700 Subject: add flash-openocd target. correct ek-tm4c123 button state --- examples/device/99-tinyusb.rules | 7 +++++++ examples/rules.mk | 13 +++++++++---- hw/bsp/ek-tm4c123gxl/board.mk | 35 ++++++++++++----------------------- hw/bsp/ek-tm4c123gxl/tm4c123gxl.c | 6 +++++- 4 files changed, 33 insertions(+), 28 deletions(-) diff --git a/examples/device/99-tinyusb.rules b/examples/device/99-tinyusb.rules index e6372ed58..d306bada5 100644 --- a/examples/device/99-tinyusb.rules +++ b/examples/device/99-tinyusb.rules @@ -12,3 +12,10 @@ ATTRS{idVendor}=="cafe", MODE="0666", GROUP="dialout" # Rule to blacklist TinyUSB example from being manipulated by ModemManager. SUBSYSTEMS=="usb", ATTRS{idVendor}=="cafe", ENV{ID_MM_DEVICE_IGNORE}="1" + +# Xplained Pro SamG55 Device +SUBSYSTEMS=="usb", ATTRS{idVendor}=="03eb", ATTRS{idProduct}=="2111", MODE="0666", GROUP="users", ENV{ID_MM_DEVICE_IGNORE}="1" +SUBSYSTEMS=="tty", ATTRS{idVendor}=="03eb", ATTRS{idProduct}=="2111", MODE="0666", GROUP="users", ENV{ID_MM_DEVICE_IGNORE}="1" + +# TI Stellaris/Tiva-C Launchpad ICDI +SUBSYSTEM=="usb", ATTRS{idVendor}=="1cbe", ATTRS{idProduct}=="00fd", MODE="0666" diff --git a/examples/rules.mk b/examples/rules.mk index 92fa4e14d..4cc35cb22 100644 --- a/examples/rules.mk +++ b/examples/rules.mk @@ -158,13 +158,14 @@ endif # Flash Targets # --------------------------------------- -# Flash binary using Jlink +# Jlink binary ifeq ($(OS),Windows_NT) JLINKEXE = JLink.exe else JLINKEXE = JLinkExe endif +# Jlink Interface JLINK_IF ?= swd # Flash using jlink @@ -177,18 +178,22 @@ flash-jlink: $(BUILD)/$(PROJECT).hex @echo exit >> $(BUILD)/$(BOARD).jlink $(JLINKEXE) -device $(JLINK_DEVICE) -if $(JLINK_IF) -JTAGConf -1,-1 -speed auto -CommandFile $(BUILD)/$(BOARD).jlink -# flash STM32 MCU using stlink with STM32 Cube Programmer CLI +# Flash STM32 MCU using stlink with STM32 Cube Programmer CLI flash-stlink: $(BUILD)/$(PROJECT).elf STM32_Programmer_CLI --connect port=swd --write $< --go -# flash with pyocd +# Flash using pyocd PYOCD_OPTION ?= flash-pyocd: $(BUILD)/$(PROJECT).hex pyocd flash -t $(PYOCD_TARGET) $(PYOCD_OPTION) $< pyocd reset -t $(PYOCD_TARGET) -# flash with Black Magic Probe +# Flash using openocd +OPENOCD_OPTION ?= +flash-openocd: $(BUILD)/$(PROJECT).elf + openocd $(OPENOCD_OPTION) -c "program $< verify reset exit" +# flash with Black Magic Probe # This symlink is created by https://github.com/blacksphere/blackmagic/blob/master/driver/99-blackmagic.rules BMP ?= /dev/ttyBmpGdb diff --git a/hw/bsp/ek-tm4c123gxl/board.mk b/hw/bsp/ek-tm4c123gxl/board.mk index f6522dc2c..368e79f4e 100644 --- a/hw/bsp/ek-tm4c123gxl/board.mk +++ b/hw/bsp/ek-tm4c123gxl/board.mk @@ -1,4 +1,3 @@ - DEPS_SUBMODULES += hw/mcu/ti CFLAGS += \ @@ -12,39 +11,29 @@ CFLAGS += \ -uvectors \ -DTM4C123GH6PM -# lpc_types.h cause following errors -CFLAGS += -Wno-error=strict-prototypes +# mcu driver cause following warnings +CFLAGS += -Wno-error=strict-prototypes -Wno-error=cast-qual MCU_DIR=hw/mcu/ti/tm4c123xx/ -CMSIS=$(TOP)/hw/mcu/ti/tm4c123xx/CMSIS/5.7.0/CMSIS/Include - -TI_HDR=$(TOP)/hw/mcu/ti/tm4c123xx/Include/TM4C123/ - # All source paths should be relative to the top level. - -LD_FILE = hw/bsp/$(BOARD)/tm4c123.ld +LD_FILE = $(BOARD_PATH)/tm4c123.ld INC += \ - $(CMSIS) \ - $(TI_HDR) \ - $(TOP)/hw/bsp - + $(TOP)/$(MCU_DIR)/CMSIS/5.7.0/CMSIS/Include \ + $(TOP)/$(MCU_DIR)/Include/TM4C123 \ + $(TOP)/hw/bsp SRC_C += \ - $(MCU_DIR)/Source/system_TM4C123.c \ - $(MCU_DIR)/Source/GCC/tm4c123_startup.c - -# For TinyUSB port source -VENDOR = ti -CHIP_FAMILY = tm4c123xx + $(MCU_DIR)/Source/system_TM4C123.c \ + $(MCU_DIR)/Source/GCC/tm4c123_startup.c # For freeRTOS port source FREERTOS_PORT = ARM_CM4F # For flash-jlink target -JLINK_DEVICE = LPC1769 +JLINK_DEVICE = TM4C123GH6PM -# flash using jlink -flash: $(BUILD)/$(PROJECT).elf - openocd -f board/ti_ek-tm4c123gxl.cfg -c "program $< verify reset exit" +# flash using openocd +OPENOCD_OPTION = -f board/ti_ek-tm4c123gxl.cfg +flash: flash-openocd diff --git a/hw/bsp/ek-tm4c123gxl/tm4c123gxl.c b/hw/bsp/ek-tm4c123gxl/tm4c123gxl.c index d78b0f7e3..b370b7577 100644 --- a/hw/bsp/ek-tm4c123gxl/tm4c123gxl.c +++ b/hw/bsp/ek-tm4c123gxl/tm4c123gxl.c @@ -3,9 +3,12 @@ #define BOARD_UART UART0 #define BOARD_UART_PORT GPIOA + #define BOARD_BTN_PORT GPIOF #define BOARD_BTN 4 #define BOARD_BTN_Msk (1u<<4) +#define BUTTON_STATE_ACTIVE 0 + #define LED_PORT GPIOF #define LED_PIN_RED 1 #define LED_PIN_BLUE 2 @@ -125,7 +128,8 @@ void board_led_write(bool state) uint32_t board_button_read(void) { - return ReadGPIOPin(BOARD_BTN_PORT, BOARD_BTN_Msk); + uint32_t gpio_value = ReadGPIOPin(BOARD_BTN_PORT, BOARD_BTN_Msk); + return BUTTON_STATE_ACTIVE ? gpio_value : !gpio_value; } int board_uart_write(void const* buf, int len) -- cgit v1.3.1 From 6fea50f735d00dff23d958eec8cf4a386282c193 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 8 Nov 2021 16:41:08 +0700 Subject: musb work well with tm4c123 --- hw/bsp/ek-tm4c123gxl/board.mk | 1 + hw/bsp/ek-tm4c123gxl/tm4c123gxl.c | 173 +++++++++++++++++--------------- src/device/dcd_attr.h | 5 +- src/portable/mentor/musb/dcd_musb.c | 18 +++- src/portable/mentor/musb/musb_msp432e.h | 40 ++++++++ src/portable/mentor/musb/musb_tm4c.h | 45 +++++++++ src/tusb_option.h | 3 +- 7 files changed, 201 insertions(+), 84 deletions(-) create mode 100644 src/portable/mentor/musb/musb_msp432e.h create mode 100644 src/portable/mentor/musb/musb_tm4c.h diff --git a/hw/bsp/ek-tm4c123gxl/board.mk b/hw/bsp/ek-tm4c123gxl/board.mk index 368e79f4e..9d0d67e1c 100644 --- a/hw/bsp/ek-tm4c123gxl/board.mk +++ b/hw/bsp/ek-tm4c123gxl/board.mk @@ -25,6 +25,7 @@ INC += \ $(TOP)/hw/bsp SRC_C += \ + src/portable/mentor/musb/dcd_musb.c \ $(MCU_DIR)/Source/system_TM4C123.c \ $(MCU_DIR)/Source/GCC/tm4c123_startup.c diff --git a/hw/bsp/ek-tm4c123gxl/tm4c123gxl.c b/hw/bsp/ek-tm4c123gxl/tm4c123gxl.c index b370b7577..663fbf127 100644 --- a/hw/bsp/ek-tm4c123gxl/tm4c123gxl.c +++ b/hw/bsp/ek-tm4c123gxl/tm4c123gxl.c @@ -15,143 +15,156 @@ #define LED_PIN_GREEN 3 #define LED_STATE_ON 1 -static void board_uart_init(void) +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void USB0_Handler(void) { - SYSCTL->RCGCUART |= (1<<0); // Enable the clock to UART0 - SYSCTL->RCGCGPIO |= (1<<0); // Enable the clock to GPIOA + tud_int_handler(0); +} + +//--------------------------------------------------------------------+ +// MACRO TYPEDEF CONSTANT ENUM +//--------------------------------------------------------------------+ - GPIOA->AFSEL |= (1<<1)|(1<<0); // Enable the alternate function on pin PA0 & PA1 - GPIOA->PCTL |= (1<<0)|(1<<4); // Configure the GPIOPCTL register to select UART0 in PA0 and PA1 - GPIOA->DEN |= (1<<0)|(1<<1); // Enable the digital functionality in PA0 and PA1 +static void board_uart_init (void) +{ + SYSCTL->RCGCUART |= (1 << 0); // Enable the clock to UART0 + SYSCTL->RCGCGPIO |= (1 << 0); // Enable the clock to GPIOA - /** BAUDRATE = 9600 bits per second, refer manual for calculation **/ + GPIOA->AFSEL |= (1 << 1) | (1 << 0); // Enable the alternate function on pin PA0 & PA1 + GPIOA->PCTL |= (1 << 0) | (1 << 4); // Configure the GPIOPCTL register to select UART0 in PA0 and PA1 + GPIOA->DEN |= (1 << 0) | (1 << 1); // Enable the digital functionality in PA0 and PA1 - UART0->CTL &= ~(1<<0); // Disable UART0 by clearing UARTEN bit in the UARTCTL register - UART0->IBRD = 325; // Write the integer portion of the BRD to the UARTIRD register - UART0->FBRD = 33; // Write the fractional portion of the BRD to the UARTFBRD registerer + /** BAUDRATE = 9600 bits per second, refer manual for calculation **/ + UART0->CTL &= ~(1 << 0); // Disable UART0 by clearing UARTEN bit in the UARTCTL register + UART0->IBRD = 325; // Write the integer portion of the BRD to the UARTIRD register + UART0->FBRD = 33; // Write the fractional portion of the BRD to the UARTFBRD registerer - UART0->LCRH = (0x3<<5); // 8-bit, no parity, 1 stop bit - UART0->CC = 0x0; // Configure the UART clock source as system clock + UART0->LCRH = (0x3 << 5); // 8-bit, no parity, 1 stop bit + UART0->CC = 0x0; // Configure the UART clock source as system clock - UART0->CTL = (1<<0)|(1<<8)|(1<<9); // UART0 Enable, Transmit Enable, Recieve Enable + UART0->CTL = (1 << 0) | (1 << 8) | (1 << 9); // UART0 Enable, Transmit Enable, Recieve Enable } -static void initialize_board_led(GPIOA_Type* port, uint8_t PinMsk, uint8_t dirmsk) +static void initialize_board_led (GPIOA_Type *port, uint8_t PinMsk, uint8_t dirmsk) { - /* Enable PortF Clock */ - SYSCTL -> RCGCGPIO |= (1<<5) ; + /* Enable PortF Clock */ + SYSCTL->RCGCGPIO |= (1 << 5); - /* Let the clock stabilize */ - while(! ((SYSCTL->PRGPIO) & (1<<5)) ) ; + /* Let the clock stabilize */ + while ( !((SYSCTL->PRGPIO) & (1 << 5)) ) + ; - /* Port Digital Enable */ - port->DEN |= PinMsk; + /* Port Digital Enable */ + port->DEN |= PinMsk; - /* Set direction */ - port->DIR = dirmsk ; + /* Set direction */ + port->DIR = dirmsk; } -static void board_switch_init(void) +static void board_switch_init (void) { - GPIOF->DIR &= ~(1<PUR |= (1<DEN |= (1<DIR &= ~(1 << BOARD_BTN); + GPIOF->PUR |= (1 << BOARD_BTN); + GPIOF->DEN |= (1 << BOARD_BTN); } -static void WriteGPIOPin(GPIOA_Type* port, uint8_t PinMsk, bool state) +static void WriteGPIOPin (GPIOA_Type *port, uint8_t PinMsk, bool state) { - if(state) - port->DATA |= PinMsk; - else - port->DATA &= ~(PinMsk); + if ( state ) + port->DATA |= PinMsk; + else + port->DATA &= ~(PinMsk); } -static uint32_t ReadGPIOPin(GPIOA_Type *port, uint8_t pinMsk) +static uint32_t ReadGPIOPin (GPIOA_Type *port, uint8_t pinMsk) { - return (port -> DATA & pinMsk) ; + return (port->DATA & pinMsk); } -void board_init(void) +void board_init (void) { - SystemCoreClockUpdate(); - + SystemCoreClockUpdate(); + #if CFG_TUSB_OS == OPT_OS_NONE - // 1ms tick timer - SysTick_Config(SystemCoreClock / 1000); + // 1ms tick timer + SysTick_Config(SystemCoreClock / 1000); #elif CFG_TUSB_OS == OPT_OS_FREERTOS // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); #endif - /* Reset USB */ - SYSCTL->SRCR2 |= (1u<<16); + /* Reset USB */ + SYSCTL->SRCR2 |= (1u << 16); + + for ( volatile uint8_t i = 0; i < 20; i++ ) {} - for (volatile uint8_t i=0; i<20; i++); + SYSCTL->SRCR2 &= ~(1u << 16); - SYSCTL->SRCR2 &= ~(1u<<16); + /* Open the USB clock gate */ + SYSCTL->RCGCUSB |= (1 << 0); - /* Open the USB clock gate */ - SYSCTL->RCGCUSB |= (1<<0); + /* Power-up USB PLL */ + SYSCTL->RCC2 &= ~(1u << 14); - /* Power-up USB PLL */ - SYSCTL->RCC2 &= ~(1u<<14); + /* USB IO Initialization */ + SYSCTL->RCGCGPIO |= (1u << 3); - /* USB IO Initialization */ - SYSCTL->RCGCGPIO |= (1u<<3); - - /* Let the clock stabilize */ - while(!(SYSCTL->PRGPIO & (1u<<3))); + /* Let the clock stabilize */ + while ( !(SYSCTL->PRGPIO & (1u << 3)) ) + ; - /* USB IOs to Analog Mode */ - GPIOD->AFSEL &= ~ ( (1u<<4) | (1u<<5) ); - GPIOD->DEN &= ~ ( (1u<<4) | (1u<<5) ); - GPIOD->AMSEL |= ( (1u<<4) | (1u<<5) ); + /* USB IOs to Analog Mode */ + GPIOD->AFSEL &= ~((1u << 4) | (1u << 5)); + GPIOD->DEN &= ~((1u << 4) | (1u << 5)); + GPIOD->AMSEL |= ((1u << 4) | (1u << 5)); - uint8_t leds = (1<FR &(1<<5)) != 0); // Poll until previous data was shofted out - UART0->DR= data[i]; // Write UART0 DATA REGISTER - } + for ( int i = 0; i < len; i++ ) + { + while ( (UART0->FR & (1 << 5)) != 0 ) {} // Poll until previous data was shofted out + UART0->DR = data[i]; // Write UART0 DATA REGISTER + } - return len; + return len; } -int board_uart_read(uint8_t* buf, int len) +int board_uart_read (uint8_t *buf, int len) { - (void) buf; (void) len; + (void) buf; + (void) len; return 0; } - #if CFG_TUSB_OS == OPT_OS_NONE volatile uint32_t system_ticks = 0; void SysTick_Handler (void) @@ -159,7 +172,7 @@ void SysTick_Handler (void) system_ticks++; } -uint32_t board_millis(void) +uint32_t board_millis (void) { return system_ticks; } diff --git a/src/device/dcd_attr.h b/src/device/dcd_attr.h index 1befa89b6..7254f3362 100644 --- a/src/device/dcd_attr.h +++ b/src/device/dcd_attr.h @@ -143,7 +143,10 @@ #define DCD_ATTR_ENDPOINT_EXCLUSIVE_NUMBER //------------- TI -------------// -#elif TU_CHECK_MCU(OPT_MCU_MSP430x5xx, OPT_MCU_MSP432E4xx) +#elif TU_CHECK_MCU(OPT_MCU_MSP430x5xx) + #define DCD_ATTR_ENDPOINT_MAX 8 + +#elif TU_CHECK_MCU(OPT_MCU_MSP432E4xx, OPT_MCU_TM4C123, OPT_MCU_TM4C129) #define DCD_ATTR_ENDPOINT_MAX 8 //------------- ValentyUSB -------------// diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c index 04139dd78..c745b4969 100644 --- a/src/portable/mentor/musb/dcd_musb.c +++ b/src/portable/mentor/musb/dcd_musb.c @@ -26,7 +26,7 @@ #include "tusb_option.h" -#if CFG_TUSB_MCU == OPT_MCU_MSP432E4xx +#if TU_CHECK_MCU(OPT_MCU_MSP432E4xx, OPT_MCU_TM4C123, OPT_MCU_TM4C129) #if __GNUC__ > 8 && defined(__ARM_FEATURE_UNALIGNED) /* GCC warns that an address may be unaligned, even though @@ -35,7 +35,21 @@ _Pragma("GCC diagnostic ignored \"-Waddress-of-packed-member\""); #endif #include "device/dcd.h" -#include "msp.h" + +#if TU_CHECK_MCU(OPT_MCU_MSP432E4xx) + #include "musb_msp432e.h" + +#elif TU_CHECK_MCU(OPT_MCU_TM4C123, OPT_MCU_TM4C129) + #include "musb_tm4c.h" + + // HACK generalize later + #include "musb_type.h" + #define FIFO0_WORD FIFO0 + #define FIFO1_WORD FIFO1 + +#else + #error "Unsupported MCUs" +#endif /*------------------------------------------------------------------ * MACRO TYPEDEF CONSTANT ENUM DECLARATION diff --git a/src/portable/mentor/musb/musb_msp432e.h b/src/portable/mentor/musb/musb_msp432e.h new file mode 100644 index 000000000..fce21de88 --- /dev/null +++ b/src/portable/mentor/musb/musb_msp432e.h @@ -0,0 +1,40 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef _TUSB_MUSB_MSP432E_H_ +#define _TUSB_MUSB_MSP432E_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "msp.h" + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/src/portable/mentor/musb/musb_tm4c.h b/src/portable/mentor/musb/musb_tm4c.h new file mode 100644 index 000000000..65a1751b0 --- /dev/null +++ b/src/portable/mentor/musb/musb_tm4c.h @@ -0,0 +1,45 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef _TUSB_MUSB_TM4C_H_ +#define _TUSB_MUSB_TM4C_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#if CFG_TUSB_MCU == OPT_MCU_TM4C123 + #include "TM4C123.h" +//#elif CFG_TUSB_MCU == OPT_MCU_TM4C129 +#else + #error "Unsupported MCUs" +#endif + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/src/tusb_option.h b/src/tusb_option.h index 50a922840..246893ddb 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -87,7 +87,8 @@ // TI MSP430 #define OPT_MCU_MSP430x5xx 500 ///< TI MSP430x5xx #define OPT_MCU_MSP432E4xx 510 ///< TI MSP432E4xx -#define OPT_MCU_TM4C123 511 ///< TI Tiva C 123x +#define OPT_MCU_TM4C123 511 ///< TI Tiva-C 123x +#define OPT_MCU_TM4C129 512 ///< TI Tiva-C 129x // ValentyUSB eptri #define OPT_MCU_VALENTYUSB_EPTRI 600 ///< Fomu eptri config -- cgit v1.3.1 From f65917f51a3046c828ced5fbb982348542b382a5 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 8 Nov 2021 17:24:58 +0700 Subject: rename to simply OPT_MCU_MSP432E4, add msp432e to ci --- .github/workflows/build_arm.yml | 1 + hw/bsp/board_mcu.h | 2 +- hw/bsp/msp432e4/family.mk | 2 +- src/class/audio/audio_device.c | 2 +- src/device/dcd_attr.h | 2 +- src/portable/mentor/musb/dcd_musb.c | 4 ++-- src/tusb_option.h | 4 ++-- 7 files changed, 9 insertions(+), 8 deletions(-) diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml index 8db0fe04f..cf9246d52 100644 --- a/.github/workflows/build_arm.yml +++ b/.github/workflows/build_arm.yml @@ -45,6 +45,7 @@ jobs: - 'lpc54' - 'lpc55' - 'mm32' + - 'msp430e4' - 'nrf' - 'rp2040' - 'samd11' diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h index 2928ea657..f8b5c061c 100644 --- a/hw/bsp/board_mcu.h +++ b/hw/bsp/board_mcu.h @@ -98,7 +98,7 @@ #elif CFG_TUSB_MCU == OPT_MCU_MSP430x5xx #include "msp430.h" -#elif CFG_TUSB_MCU == OPT_MCU_MSP432E4xx +#elif CFG_TUSB_MCU == OPT_MCU_MSP432E4 #include "msp.h" #elif CFG_TUSB_MCU == OPT_MCU_VALENTYUSB_EPTRI diff --git a/hw/bsp/msp432e4/family.mk b/hw/bsp/msp432e4/family.mk index ee7faa208..b664c4c1b 100644 --- a/hw/bsp/msp432e4/family.mk +++ b/hw/bsp/msp432e4/family.mk @@ -9,7 +9,7 @@ CFLAGS += \ -mfloat-abi=hard \ -mfpu=fpv4-sp-d16 \ -D__MSP432E401Y__ \ - -DCFG_TUSB_MCU=OPT_MCU_MSP432E4xx + -DCFG_TUSB_MCU=OPT_MCU_MSP432E4 # mcu driver cause following warnings CFLAGS += -Wno-error=cast-qual -Wno-error=format= diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c index 38bfc023b..d9f2e284e 100644 --- a/src/class/audio/audio_device.c +++ b/src/class/audio/audio_device.c @@ -103,7 +103,7 @@ CFG_TUSB_MCU == OPT_MCU_LPC18XX || \ CFG_TUSB_MCU == OPT_MCU_LPC43XX || \ CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \ - CFG_TUSB_MCU == OPT_MCU_MSP432E4xx + CFG_TUSB_MCU == OPT_MCU_MSP432E4 #if TUD_AUDIO_PREFER_RING_BUFFER #define USE_LINEAR_BUFFER 0 #else diff --git a/src/device/dcd_attr.h b/src/device/dcd_attr.h index 7254f3362..73d592e5c 100644 --- a/src/device/dcd_attr.h +++ b/src/device/dcd_attr.h @@ -146,7 +146,7 @@ #elif TU_CHECK_MCU(OPT_MCU_MSP430x5xx) #define DCD_ATTR_ENDPOINT_MAX 8 -#elif TU_CHECK_MCU(OPT_MCU_MSP432E4xx, OPT_MCU_TM4C123, OPT_MCU_TM4C129) +#elif TU_CHECK_MCU(OPT_MCU_MSP432E4, OPT_MCU_TM4C123, OPT_MCU_TM4C129) #define DCD_ATTR_ENDPOINT_MAX 8 //------------- ValentyUSB -------------// diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c index c745b4969..4b4c2f9b2 100644 --- a/src/portable/mentor/musb/dcd_musb.c +++ b/src/portable/mentor/musb/dcd_musb.c @@ -26,7 +26,7 @@ #include "tusb_option.h" -#if TU_CHECK_MCU(OPT_MCU_MSP432E4xx, OPT_MCU_TM4C123, OPT_MCU_TM4C129) +#if TU_CHECK_MCU(OPT_MCU_MSP432E4, OPT_MCU_TM4C123, OPT_MCU_TM4C129) #if __GNUC__ > 8 && defined(__ARM_FEATURE_UNALIGNED) /* GCC warns that an address may be unaligned, even though @@ -36,7 +36,7 @@ _Pragma("GCC diagnostic ignored \"-Waddress-of-packed-member\""); #include "device/dcd.h" -#if TU_CHECK_MCU(OPT_MCU_MSP432E4xx) +#if TU_CHECK_MCU(OPT_MCU_MSP432E4) #include "musb_msp432e.h" #elif TU_CHECK_MCU(OPT_MCU_TM4C123, OPT_MCU_TM4C129) diff --git a/src/tusb_option.h b/src/tusb_option.h index 246893ddb..2edd310fa 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -84,9 +84,9 @@ // Sony #define OPT_MCU_CXD56 400 ///< SONY CXD56 -// TI MSP430 +// TI #define OPT_MCU_MSP430x5xx 500 ///< TI MSP430x5xx -#define OPT_MCU_MSP432E4xx 510 ///< TI MSP432E4xx +#define OPT_MCU_MSP432E4 510 ///< TI MSP432E4xx #define OPT_MCU_TM4C123 511 ///< TI Tiva-C 123x #define OPT_MCU_TM4C129 512 ///< TI Tiva-C 129x -- cgit v1.3.1 From 17ef1503c8adc96e1874fb4bf497b7fcf6b4808a Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 8 Nov 2021 17:37:21 +0700 Subject: move tm4c132 into bsp family, add it into ci --- .github/workflows/build_arm.yml | 1 + hw/bsp/ek-tm4c123gxl/board.mk | 40 ------ hw/bsp/ek-tm4c123gxl/tm4c123.ld | 65 --------- hw/bsp/ek-tm4c123gxl/tm4c123gxl.c | 180 ------------------------- hw/bsp/tm4c123/boards/ek-tm4c123gxl/board.h | 52 +++++++ hw/bsp/tm4c123/boards/ek-tm4c123gxl/board.mk | 11 ++ hw/bsp/tm4c123/boards/ek-tm4c123gxl/tm4c123.ld | 65 +++++++++ hw/bsp/tm4c123/family.c | 167 +++++++++++++++++++++++ hw/bsp/tm4c123/family.mk | 35 +++++ 9 files changed, 331 insertions(+), 285 deletions(-) delete mode 100644 hw/bsp/ek-tm4c123gxl/board.mk delete mode 100644 hw/bsp/ek-tm4c123gxl/tm4c123.ld delete mode 100644 hw/bsp/ek-tm4c123gxl/tm4c123gxl.c create mode 100644 hw/bsp/tm4c123/boards/ek-tm4c123gxl/board.h create mode 100644 hw/bsp/tm4c123/boards/ek-tm4c123gxl/board.mk create mode 100644 hw/bsp/tm4c123/boards/ek-tm4c123gxl/tm4c123.ld create mode 100644 hw/bsp/tm4c123/family.c create mode 100644 hw/bsp/tm4c123/family.mk diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml index cf9246d52..e4d64826e 100644 --- a/.github/workflows/build_arm.yml +++ b/.github/workflows/build_arm.yml @@ -58,6 +58,7 @@ jobs: - 'stm32f7' - 'stm32h7' - 'stm32l4' + - 'tm4c123' - 'xmc4000' steps: - name: Setup Python diff --git a/hw/bsp/ek-tm4c123gxl/board.mk b/hw/bsp/ek-tm4c123gxl/board.mk deleted file mode 100644 index 9d0d67e1c..000000000 --- a/hw/bsp/ek-tm4c123gxl/board.mk +++ /dev/null @@ -1,40 +0,0 @@ -DEPS_SUBMODULES += hw/mcu/ti - -CFLAGS += \ - -flto \ - -mthumb \ - -mabi=aapcs \ - -mcpu=cortex-m4 \ - -mfloat-abi=hard \ - -mfpu=fpv4-sp-d16 \ - -DCFG_TUSB_MCU=OPT_MCU_TM4C123 \ - -uvectors \ - -DTM4C123GH6PM - -# mcu driver cause following warnings -CFLAGS += -Wno-error=strict-prototypes -Wno-error=cast-qual - -MCU_DIR=hw/mcu/ti/tm4c123xx/ - -# All source paths should be relative to the top level. -LD_FILE = $(BOARD_PATH)/tm4c123.ld - -INC += \ - $(TOP)/$(MCU_DIR)/CMSIS/5.7.0/CMSIS/Include \ - $(TOP)/$(MCU_DIR)/Include/TM4C123 \ - $(TOP)/hw/bsp - -SRC_C += \ - src/portable/mentor/musb/dcd_musb.c \ - $(MCU_DIR)/Source/system_TM4C123.c \ - $(MCU_DIR)/Source/GCC/tm4c123_startup.c - -# For freeRTOS port source -FREERTOS_PORT = ARM_CM4F - -# For flash-jlink target -JLINK_DEVICE = TM4C123GH6PM - -# flash using openocd -OPENOCD_OPTION = -f board/ti_ek-tm4c123gxl.cfg -flash: flash-openocd diff --git a/hw/bsp/ek-tm4c123gxl/tm4c123.ld b/hw/bsp/ek-tm4c123gxl/tm4c123.ld deleted file mode 100644 index e2720a9ac..000000000 --- a/hw/bsp/ek-tm4c123gxl/tm4c123.ld +++ /dev/null @@ -1,65 +0,0 @@ -ENTRY(Reset_Handler) - -_estack = 0x20008000; /* end of RAM */ -/* Generate a link error if heap and stack don't fit into RAM */ -_Min_Heap_Size = 0; /* required amount of heap */ -_Min_Stack_Size = 0x1000; /* required amount of stack */ - - -MEMORY -{ - FLASH(rx) : ORIGIN = 0x00000000, LENGTH = 256K - SRAM(rwx) : ORIGIN = 0x20000000, LENGTH = 32K -} - -SECTIONS -{ - .text : - { - . = ALIGN(4) ; - *(.vectors) - *(.text) - *(.text.*) - *(.init) - *(.fini) - *(.rodata) - *(.rodata.*) - . = ALIGN(4) ; - __end_text = . ; - } >FLASH - - .data : AT(ADDR(.text) + SIZEOF(.text)) - { - . = ALIGN(4); - __start_data = . ; - __la_data = LOADADDR(.data); - *(.data) - *(.data.*) - . = ALIGN(4); - __end_data = . ; - - } >SRAM - - .bss : - { - . = ALIGN(4) ; - __start_bss = . ; - __bss_start__ = __start_bss; - *(.bss) - *(.bss.*) - *(.COMMON) - __end_bss = . ; - . = ALIGN(4); - }>SRAM - - /* User_heap_stack section, used to check that there is enough RAM left */ - ._user_heap_stack : - { - . = ALIGN(8); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - . = . + _Min_Heap_Size; - . = . + _Min_Stack_Size; - . = ALIGN(8); - } >SRAM -} diff --git a/hw/bsp/ek-tm4c123gxl/tm4c123gxl.c b/hw/bsp/ek-tm4c123gxl/tm4c123gxl.c deleted file mode 100644 index 663fbf127..000000000 --- a/hw/bsp/ek-tm4c123gxl/tm4c123gxl.c +++ /dev/null @@ -1,180 +0,0 @@ -#include -#include - -#define BOARD_UART UART0 -#define BOARD_UART_PORT GPIOA - -#define BOARD_BTN_PORT GPIOF -#define BOARD_BTN 4 -#define BOARD_BTN_Msk (1u<<4) -#define BUTTON_STATE_ACTIVE 0 - -#define LED_PORT GPIOF -#define LED_PIN_RED 1 -#define LED_PIN_BLUE 2 -#define LED_PIN_GREEN 3 -#define LED_STATE_ON 1 - -//--------------------------------------------------------------------+ -// Forward USB interrupt events to TinyUSB IRQ Handler -//--------------------------------------------------------------------+ -void USB0_Handler(void) -{ - tud_int_handler(0); -} - -//--------------------------------------------------------------------+ -// MACRO TYPEDEF CONSTANT ENUM -//--------------------------------------------------------------------+ - -static void board_uart_init (void) -{ - SYSCTL->RCGCUART |= (1 << 0); // Enable the clock to UART0 - SYSCTL->RCGCGPIO |= (1 << 0); // Enable the clock to GPIOA - - GPIOA->AFSEL |= (1 << 1) | (1 << 0); // Enable the alternate function on pin PA0 & PA1 - GPIOA->PCTL |= (1 << 0) | (1 << 4); // Configure the GPIOPCTL register to select UART0 in PA0 and PA1 - GPIOA->DEN |= (1 << 0) | (1 << 1); // Enable the digital functionality in PA0 and PA1 - - /** BAUDRATE = 9600 bits per second, refer manual for calculation **/ - UART0->CTL &= ~(1 << 0); // Disable UART0 by clearing UARTEN bit in the UARTCTL register - UART0->IBRD = 325; // Write the integer portion of the BRD to the UARTIRD register - UART0->FBRD = 33; // Write the fractional portion of the BRD to the UARTFBRD registerer - - UART0->LCRH = (0x3 << 5); // 8-bit, no parity, 1 stop bit - UART0->CC = 0x0; // Configure the UART clock source as system clock - - UART0->CTL = (1 << 0) | (1 << 8) | (1 << 9); // UART0 Enable, Transmit Enable, Recieve Enable -} - -static void initialize_board_led (GPIOA_Type *port, uint8_t PinMsk, uint8_t dirmsk) -{ - /* Enable PortF Clock */ - SYSCTL->RCGCGPIO |= (1 << 5); - - /* Let the clock stabilize */ - while ( !((SYSCTL->PRGPIO) & (1 << 5)) ) - ; - - /* Port Digital Enable */ - port->DEN |= PinMsk; - - /* Set direction */ - port->DIR = dirmsk; -} - -static void board_switch_init (void) -{ - GPIOF->DIR &= ~(1 << BOARD_BTN); - GPIOF->PUR |= (1 << BOARD_BTN); - GPIOF->DEN |= (1 << BOARD_BTN); -} - -static void WriteGPIOPin (GPIOA_Type *port, uint8_t PinMsk, bool state) -{ - if ( state ) - port->DATA |= PinMsk; - else - port->DATA &= ~(PinMsk); -} - -static uint32_t ReadGPIOPin (GPIOA_Type *port, uint8_t pinMsk) -{ - return (port->DATA & pinMsk); -} - -void board_init (void) -{ - SystemCoreClockUpdate(); - -#if CFG_TUSB_OS == OPT_OS_NONE - // 1ms tick timer - SysTick_Config(SystemCoreClock / 1000); -#elif CFG_TUSB_OS == OPT_OS_FREERTOS - // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) - NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); -#endif - - /* Reset USB */ - SYSCTL->SRCR2 |= (1u << 16); - - for ( volatile uint8_t i = 0; i < 20; i++ ) {} - - SYSCTL->SRCR2 &= ~(1u << 16); - - /* Open the USB clock gate */ - SYSCTL->RCGCUSB |= (1 << 0); - - /* Power-up USB PLL */ - SYSCTL->RCC2 &= ~(1u << 14); - - /* USB IO Initialization */ - SYSCTL->RCGCGPIO |= (1u << 3); - - /* Let the clock stabilize */ - while ( !(SYSCTL->PRGPIO & (1u << 3)) ) - ; - - /* USB IOs to Analog Mode */ - GPIOD->AFSEL &= ~((1u << 4) | (1u << 5)); - GPIOD->DEN &= ~((1u << 4) | (1u << 5)); - GPIOD->AMSEL |= ((1u << 4) | (1u << 5)); - - uint8_t leds = (1 << LED_PIN_RED) | (1 << LED_PIN_BLUE) | (1 << LED_PIN_GREEN); - uint8_t dirmsk = (1 << LED_PIN_RED) | (1 << LED_PIN_BLUE) | (1 << LED_PIN_GREEN); - - /* Configure GPIO for board LED */ - initialize_board_led(LED_PORT, leds, dirmsk); - - /* Configure GPIO for board switch */ - board_switch_init(); - - /* Initialize board UART */ - board_uart_init(); - -} - -void board_led_write (bool state) -{ - WriteGPIOPin(LED_PORT, (1 << LED_PIN_BLUE), state); -} - -uint32_t board_button_read (void) -{ - uint32_t gpio_value = ReadGPIOPin(BOARD_BTN_PORT, BOARD_BTN_Msk); - return BUTTON_STATE_ACTIVE ? gpio_value : !gpio_value; -} - -int board_uart_write (void const *buf, int len) -{ - uint8_t const * data = buf; - - for ( int i = 0; i < len; i++ ) - { - while ( (UART0->FR & (1 << 5)) != 0 ) {} // Poll until previous data was shofted out - UART0->DR = data[i]; // Write UART0 DATA REGISTER - } - - return len; -} - -int board_uart_read (uint8_t *buf, int len) -{ - (void) buf; - (void) len; - return 0; -} - -#if CFG_TUSB_OS == OPT_OS_NONE -volatile uint32_t system_ticks = 0; -void SysTick_Handler (void) -{ - system_ticks++; -} - -uint32_t board_millis (void) -{ - return system_ticks; -} -#endif - diff --git a/hw/bsp/tm4c123/boards/ek-tm4c123gxl/board.h b/hw/bsp/tm4c123/boards/ek-tm4c123gxl/board.h new file mode 100644 index 000000000..5732056ae --- /dev/null +++ b/hw/bsp/tm4c123/boards/ek-tm4c123gxl/board.h @@ -0,0 +1,52 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#define BOARD_UART UART0 +#define BOARD_UART_PORT GPIOA + +#define BOARD_BTN_PORT GPIOF +#define BOARD_BTN 4 +#define BOARD_BTN_Msk (1u<<4) +#define BUTTON_STATE_ACTIVE 0 + +#define LED_PORT GPIOF +#define LED_PIN_RED 1 +#define LED_PIN_BLUE 2 +#define LED_PIN_GREEN 3 +#define LED_STATE_ON 1 + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/hw/bsp/tm4c123/boards/ek-tm4c123gxl/board.mk b/hw/bsp/tm4c123/boards/ek-tm4c123gxl/board.mk new file mode 100644 index 000000000..d60365d1d --- /dev/null +++ b/hw/bsp/tm4c123/boards/ek-tm4c123gxl/board.mk @@ -0,0 +1,11 @@ +CFLAGS += -DTM4C123GH6PM + +LD_FILE = $(BOARD_PATH)/tm4c123.ld + +# For flash-jlink target +JLINK_DEVICE = TM4C123GH6PM + +# flash using openocd +OPENOCD_OPTION = -f board/ti_ek-tm4c123gxl.cfg + +flash: flash-openocd diff --git a/hw/bsp/tm4c123/boards/ek-tm4c123gxl/tm4c123.ld b/hw/bsp/tm4c123/boards/ek-tm4c123gxl/tm4c123.ld new file mode 100644 index 000000000..e2720a9ac --- /dev/null +++ b/hw/bsp/tm4c123/boards/ek-tm4c123gxl/tm4c123.ld @@ -0,0 +1,65 @@ +ENTRY(Reset_Handler) + +_estack = 0x20008000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0; /* required amount of heap */ +_Min_Stack_Size = 0x1000; /* required amount of stack */ + + +MEMORY +{ + FLASH(rx) : ORIGIN = 0x00000000, LENGTH = 256K + SRAM(rwx) : ORIGIN = 0x20000000, LENGTH = 32K +} + +SECTIONS +{ + .text : + { + . = ALIGN(4) ; + *(.vectors) + *(.text) + *(.text.*) + *(.init) + *(.fini) + *(.rodata) + *(.rodata.*) + . = ALIGN(4) ; + __end_text = . ; + } >FLASH + + .data : AT(ADDR(.text) + SIZEOF(.text)) + { + . = ALIGN(4); + __start_data = . ; + __la_data = LOADADDR(.data); + *(.data) + *(.data.*) + . = ALIGN(4); + __end_data = . ; + + } >SRAM + + .bss : + { + . = ALIGN(4) ; + __start_bss = . ; + __bss_start__ = __start_bss; + *(.bss) + *(.bss.*) + *(.COMMON) + __end_bss = . ; + . = ALIGN(4); + }>SRAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >SRAM +} diff --git a/hw/bsp/tm4c123/family.c b/hw/bsp/tm4c123/family.c new file mode 100644 index 000000000..048832dc9 --- /dev/null +++ b/hw/bsp/tm4c123/family.c @@ -0,0 +1,167 @@ +#include "TM4C123.h" +#include "bsp/board.h" +#include "board.h" + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void USB0_Handler(void) +{ + tud_int_handler(0); +} + +//--------------------------------------------------------------------+ +// MACRO TYPEDEF CONSTANT ENUM +//--------------------------------------------------------------------+ + +static void board_uart_init (void) +{ + SYSCTL->RCGCUART |= (1 << 0); // Enable the clock to UART0 + SYSCTL->RCGCGPIO |= (1 << 0); // Enable the clock to GPIOA + + GPIOA->AFSEL |= (1 << 1) | (1 << 0); // Enable the alternate function on pin PA0 & PA1 + GPIOA->PCTL |= (1 << 0) | (1 << 4); // Configure the GPIOPCTL register to select UART0 in PA0 and PA1 + GPIOA->DEN |= (1 << 0) | (1 << 1); // Enable the digital functionality in PA0 and PA1 + + /** BAUDRATE = 9600 bits per second, refer manual for calculation **/ + UART0->CTL &= ~(1 << 0); // Disable UART0 by clearing UARTEN bit in the UARTCTL register + UART0->IBRD = 325; // Write the integer portion of the BRD to the UARTIRD register + UART0->FBRD = 33; // Write the fractional portion of the BRD to the UARTFBRD registerer + + UART0->LCRH = (0x3 << 5); // 8-bit, no parity, 1 stop bit + UART0->CC = 0x0; // Configure the UART clock source as system clock + + UART0->CTL = (1 << 0) | (1 << 8) | (1 << 9); // UART0 Enable, Transmit Enable, Recieve Enable +} + +static void initialize_board_led (GPIOA_Type *port, uint8_t PinMsk, uint8_t dirmsk) +{ + /* Enable PortF Clock */ + SYSCTL->RCGCGPIO |= (1 << 5); + + /* Let the clock stabilize */ + while ( !((SYSCTL->PRGPIO) & (1 << 5)) ) + ; + + /* Port Digital Enable */ + port->DEN |= PinMsk; + + /* Set direction */ + port->DIR = dirmsk; +} + +static void board_switch_init (void) +{ + GPIOF->DIR &= ~(1 << BOARD_BTN); + GPIOF->PUR |= (1 << BOARD_BTN); + GPIOF->DEN |= (1 << BOARD_BTN); +} + +static void WriteGPIOPin (GPIOA_Type *port, uint8_t PinMsk, bool state) +{ + if ( state ) + port->DATA |= PinMsk; + else + port->DATA &= ~(PinMsk); +} + +static uint32_t ReadGPIOPin (GPIOA_Type *port, uint8_t pinMsk) +{ + return (port->DATA & pinMsk); +} + +void board_init (void) +{ + SystemCoreClockUpdate(); + +#if CFG_TUSB_OS == OPT_OS_NONE + // 1ms tick timer + SysTick_Config(SystemCoreClock / 1000); +#elif CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); +#endif + + /* Reset USB */ + SYSCTL->SRCR2 |= (1u << 16); + + for ( volatile uint8_t i = 0; i < 20; i++ ) {} + + SYSCTL->SRCR2 &= ~(1u << 16); + + /* Open the USB clock gate */ + SYSCTL->RCGCUSB |= (1 << 0); + + /* Power-up USB PLL */ + SYSCTL->RCC2 &= ~(1u << 14); + + /* USB IO Initialization */ + SYSCTL->RCGCGPIO |= (1u << 3); + + /* Let the clock stabilize */ + while ( !(SYSCTL->PRGPIO & (1u << 3)) ) + ; + + /* USB IOs to Analog Mode */ + GPIOD->AFSEL &= ~((1u << 4) | (1u << 5)); + GPIOD->DEN &= ~((1u << 4) | (1u << 5)); + GPIOD->AMSEL |= ((1u << 4) | (1u << 5)); + + uint8_t leds = (1 << LED_PIN_RED) | (1 << LED_PIN_BLUE) | (1 << LED_PIN_GREEN); + uint8_t dirmsk = (1 << LED_PIN_RED) | (1 << LED_PIN_BLUE) | (1 << LED_PIN_GREEN); + + /* Configure GPIO for board LED */ + initialize_board_led(LED_PORT, leds, dirmsk); + + /* Configure GPIO for board switch */ + board_switch_init(); + + /* Initialize board UART */ + board_uart_init(); + +} + +void board_led_write (bool state) +{ + WriteGPIOPin(LED_PORT, (1 << LED_PIN_BLUE), state); +} + +uint32_t board_button_read (void) +{ + uint32_t gpio_value = ReadGPIOPin(BOARD_BTN_PORT, BOARD_BTN_Msk); + return BUTTON_STATE_ACTIVE ? gpio_value : !gpio_value; +} + +int board_uart_write (void const *buf, int len) +{ + uint8_t const * data = buf; + + for ( int i = 0; i < len; i++ ) + { + while ( (UART0->FR & (1 << 5)) != 0 ) {} // Poll until previous data was shofted out + UART0->DR = data[i]; // Write UART0 DATA REGISTER + } + + return len; +} + +int board_uart_read (uint8_t *buf, int len) +{ + (void) buf; + (void) len; + return 0; +} + +#if CFG_TUSB_OS == OPT_OS_NONE +volatile uint32_t system_ticks = 0; +void SysTick_Handler (void) +{ + system_ticks++; +} + +uint32_t board_millis (void) +{ + return system_ticks; +} +#endif + diff --git a/hw/bsp/tm4c123/family.mk b/hw/bsp/tm4c123/family.mk new file mode 100644 index 000000000..9665a2d7d --- /dev/null +++ b/hw/bsp/tm4c123/family.mk @@ -0,0 +1,35 @@ +DEPS_SUBMODULES += hw/mcu/ti + +include $(TOP)/$(BOARD_PATH)/board.mk + +CFLAGS += \ + -flto \ + -mthumb \ + -mabi=aapcs \ + -mcpu=cortex-m4 \ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 \ + -DCFG_TUSB_MCU=OPT_MCU_TM4C123 \ + -uvectors \ + -DTM4C123GH6PM + +# mcu driver cause following warnings +CFLAGS += -Wno-error=strict-prototypes -Wno-error=cast-qual + +MCU_DIR=hw/mcu/ti/tm4c123xx/ + +# All source paths should be relative to the top level. +LD_FILE = $(BOARD_PATH)/tm4c123.ld + +INC += \ + $(TOP)/$(MCU_DIR)/CMSIS/5.7.0/CMSIS/Include \ + $(TOP)/$(MCU_DIR)/Include/TM4C123 \ + $(TOP)/$(BOARD_PATH) + +SRC_C += \ + src/portable/mentor/musb/dcd_musb.c \ + $(MCU_DIR)/Source/system_TM4C123.c \ + $(MCU_DIR)/Source/GCC/tm4c123_startup.c + +# For freeRTOS port source +FREERTOS_PORT = ARM_CM4F -- cgit v1.3.1 From d415bd4d7b144f470b8d1c12284abb161ac4dd5f Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 8 Nov 2021 17:39:37 +0700 Subject: add missing musb type file --- src/portable/mentor/musb/musb_type.h | 2624 ++++++++++++++++++++++++++++++++++ 1 file changed, 2624 insertions(+) create mode 100644 src/portable/mentor/musb/musb_type.h diff --git a/src/portable/mentor/musb/musb_type.h b/src/portable/mentor/musb/musb_type.h new file mode 100644 index 000000000..8f83305a5 --- /dev/null +++ b/src/portable/mentor/musb/musb_type.h @@ -0,0 +1,2624 @@ +/****************************************************************************** +* +* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*******************************************************************************/ + +#ifndef _TUSB_MUSB_TYPE_H_ +#define _TUSB_MUSB_TYPE_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FADDR register. +// +//***************************************************************************** +#define USB_FADDR_M 0x0000007F // Function Address +#define USB_FADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_POWER register. +// +//***************************************************************************** +#define USB_POWER_ISOUP 0x00000080 // Isochronous Update +#define USB_POWER_SOFTCONN 0x00000040 // Soft Connect/Disconnect +#define USB_POWER_HSENAB 0x00000020 // High Speed Enable +#define USB_POWER_HSMODE 0x00000010 // High Speed Enable +#define USB_POWER_RESET 0x00000008 // RESET Signaling +#define USB_POWER_RESUME 0x00000004 // RESUME Signaling +#define USB_POWER_SUSPEND 0x00000002 // SUSPEND Mode +#define USB_POWER_PWRDNPHY 0x00000001 // Power Down PHY + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXIS register. +// +//***************************************************************************** +#define USB_TXIS_EP7 0x00000080 // TX Endpoint 7 Interrupt +#define USB_TXIS_EP6 0x00000040 // TX Endpoint 6 Interrupt +#define USB_TXIS_EP5 0x00000020 // TX Endpoint 5 Interrupt +#define USB_TXIS_EP4 0x00000010 // TX Endpoint 4 Interrupt +#define USB_TXIS_EP3 0x00000008 // TX Endpoint 3 Interrupt +#define USB_TXIS_EP2 0x00000004 // TX Endpoint 2 Interrupt +#define USB_TXIS_EP1 0x00000002 // TX Endpoint 1 Interrupt +#define USB_TXIS_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXIS register. +// +//***************************************************************************** +#define USB_RXIS_EP7 0x00000080 // RX Endpoint 7 Interrupt +#define USB_RXIS_EP6 0x00000040 // RX Endpoint 6 Interrupt +#define USB_RXIS_EP5 0x00000020 // RX Endpoint 5 Interrupt +#define USB_RXIS_EP4 0x00000010 // RX Endpoint 4 Interrupt +#define USB_RXIS_EP3 0x00000008 // RX Endpoint 3 Interrupt +#define USB_RXIS_EP2 0x00000004 // RX Endpoint 2 Interrupt +#define USB_RXIS_EP1 0x00000002 // RX Endpoint 1 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXIE register. +// +//***************************************************************************** +#define USB_TXIE_EP7 0x00000080 // TX Endpoint 7 Interrupt Enable +#define USB_TXIE_EP6 0x00000040 // TX Endpoint 6 Interrupt Enable +#define USB_TXIE_EP5 0x00000020 // TX Endpoint 5 Interrupt Enable +#define USB_TXIE_EP4 0x00000010 // TX Endpoint 4 Interrupt Enable +#define USB_TXIE_EP3 0x00000008 // TX Endpoint 3 Interrupt Enable +#define USB_TXIE_EP2 0x00000004 // TX Endpoint 2 Interrupt Enable +#define USB_TXIE_EP1 0x00000002 // TX Endpoint 1 Interrupt Enable +#define USB_TXIE_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt + // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXIE register. +// +//***************************************************************************** +#define USB_RXIE_EP7 0x00000080 // RX Endpoint 7 Interrupt Enable +#define USB_RXIE_EP6 0x00000040 // RX Endpoint 6 Interrupt Enable +#define USB_RXIE_EP5 0x00000020 // RX Endpoint 5 Interrupt Enable +#define USB_RXIE_EP4 0x00000010 // RX Endpoint 4 Interrupt Enable +#define USB_RXIE_EP3 0x00000008 // RX Endpoint 3 Interrupt Enable +#define USB_RXIE_EP2 0x00000004 // RX Endpoint 2 Interrupt Enable +#define USB_RXIE_EP1 0x00000002 // RX Endpoint 1 Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IS register. +// +//***************************************************************************** +#define USB_IS_VBUSERR 0x00000080 // VBUS Error (OTG only) +#define USB_IS_SESREQ 0x00000040 // SESSION REQUEST (OTG only) +#define USB_IS_DISCON 0x00000020 // Session Disconnect (OTG only) +#define USB_IS_CONN 0x00000010 // Session Connect +#define USB_IS_SOF 0x00000008 // Start of Frame +#define USB_IS_BABBLE 0x00000004 // Babble Detected +#define USB_IS_RESET 0x00000004 // RESET Signaling Detected +#define USB_IS_RESUME 0x00000002 // RESUME Signaling Detected +#define USB_IS_SUSPEND 0x00000001 // SUSPEND Signaling Detected + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IE register. +// +//***************************************************************************** +#define USB_IE_VBUSERR 0x00000080 // Enable VBUS Error Interrupt (OTG + // only) +#define USB_IE_SESREQ 0x00000040 // Enable Session Request (OTG + // only) +#define USB_IE_DISCON 0x00000020 // Enable Disconnect Interrupt +#define USB_IE_CONN 0x00000010 // Enable Connect Interrupt +#define USB_IE_SOF 0x00000008 // Enable Start-of-Frame Interrupt +#define USB_IE_BABBLE 0x00000004 // Enable Babble Interrupt +#define USB_IE_RESET 0x00000004 // Enable RESET Interrupt +#define USB_IE_RESUME 0x00000002 // Enable RESUME Interrupt +#define USB_IE_SUSPND 0x00000001 // Enable SUSPEND Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FRAME register. +// +//***************************************************************************** +#define USB_FRAME_M 0x000007FF // Frame Number +#define USB_FRAME_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPIDX register. +// +//***************************************************************************** +#define USB_EPIDX_EPIDX_M 0x0000000F // Endpoint Index +#define USB_EPIDX_EPIDX_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TEST register. +// +//***************************************************************************** +#define USB_TEST_FORCEH 0x00000080 // Force Host Mode +#define USB_TEST_FIFOACC 0x00000040 // FIFO Access +#define USB_TEST_FORCEFS 0x00000020 // Force Full-Speed Mode +#define USB_TEST_FORCEHS 0x00000010 // Force High-Speed Mode +#define USB_TEST_TESTPKT 0x00000008 // Test Packet Mode Enable +#define USB_TEST_TESTK 0x00000004 // Test_K Mode Enable +#define USB_TEST_TESTJ 0x00000002 // Test_J Mode Enable +#define USB_TEST_TESTSE0NAK 0x00000001 // Test_SE0_NAK Test Mode Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO0 register. +// +//***************************************************************************** +#define USB_FIFO0_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO0_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO1 register. +// +//***************************************************************************** +#define USB_FIFO1_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO1_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO2 register. +// +//***************************************************************************** +#define USB_FIFO2_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO2_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO3 register. +// +//***************************************************************************** +#define USB_FIFO3_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO3_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO4 register. +// +//***************************************************************************** +#define USB_FIFO4_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO4_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO5 register. +// +//***************************************************************************** +#define USB_FIFO5_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO5_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO6 register. +// +//***************************************************************************** +#define USB_FIFO6_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO6_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO7 register. +// +//***************************************************************************** +#define USB_FIFO7_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO7_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DEVCTL register. +// +//***************************************************************************** +#define USB_DEVCTL_DEV 0x00000080 // Device Mode (OTG only) +#define USB_DEVCTL_FSDEV 0x00000040 // Full-Speed Device Detected +#define USB_DEVCTL_LSDEV 0x00000020 // Low-Speed Device Detected +#define USB_DEVCTL_VBUS_M 0x00000018 // VBUS Level (OTG only) +#define USB_DEVCTL_VBUS_NONE 0x00000000 // Below SessionEnd +#define USB_DEVCTL_VBUS_SEND 0x00000008 // Above SessionEnd, below AValid +#define USB_DEVCTL_VBUS_AVALID 0x00000010 // Above AValid, below VBUSValid +#define USB_DEVCTL_VBUS_VALID 0x00000018 // Above VBUSValid +#define USB_DEVCTL_HOST 0x00000004 // Host Mode +#define USB_DEVCTL_HOSTREQ 0x00000002 // Host Request (OTG only) +#define USB_DEVCTL_SESSION 0x00000001 // Session Start/End (OTG only) + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CCONF register. +// +//***************************************************************************** +#define USB_CCONF_TXEDMA 0x00000002 // TX Early DMA Enable +#define USB_CCONF_RXEDMA 0x00000001 // TX Early DMA Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFIFOSZ register. +// +//***************************************************************************** +#define USB_TXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support +#define USB_TXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size +#define USB_TXFIFOSZ_SIZE_8 0x00000000 // 8 +#define USB_TXFIFOSZ_SIZE_16 0x00000001 // 16 +#define USB_TXFIFOSZ_SIZE_32 0x00000002 // 32 +#define USB_TXFIFOSZ_SIZE_64 0x00000003 // 64 +#define USB_TXFIFOSZ_SIZE_128 0x00000004 // 128 +#define USB_TXFIFOSZ_SIZE_256 0x00000005 // 256 +#define USB_TXFIFOSZ_SIZE_512 0x00000006 // 512 +#define USB_TXFIFOSZ_SIZE_1024 0x00000007 // 1024 +#define USB_TXFIFOSZ_SIZE_2048 0x00000008 // 2048 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFIFOSZ register. +// +//***************************************************************************** +#define USB_RXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support +#define USB_RXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size +#define USB_RXFIFOSZ_SIZE_8 0x00000000 // 8 +#define USB_RXFIFOSZ_SIZE_16 0x00000001 // 16 +#define USB_RXFIFOSZ_SIZE_32 0x00000002 // 32 +#define USB_RXFIFOSZ_SIZE_64 0x00000003 // 64 +#define USB_RXFIFOSZ_SIZE_128 0x00000004 // 128 +#define USB_RXFIFOSZ_SIZE_256 0x00000005 // 256 +#define USB_RXFIFOSZ_SIZE_512 0x00000006 // 512 +#define USB_RXFIFOSZ_SIZE_1024 0x00000007 // 1024 +#define USB_RXFIFOSZ_SIZE_2048 0x00000008 // 2048 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFIFOADD +// register. +// +//***************************************************************************** +#define USB_TXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address +#define USB_TXFIFOADD_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFIFOADD +// register. +// +//***************************************************************************** +#define USB_RXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address +#define USB_RXFIFOADD_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_ULPIVBUSCTL +// register. +// +//***************************************************************************** +#define USB_ULPIVBUSCTL_USEEXTVBUSIND \ + 0x00000002 // Use External VBUS Indicator +#define USB_ULPIVBUSCTL_USEEXTVBUS \ + 0x00000001 // Use External VBUS + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_ULPIREGDATA +// register. +// +//***************************************************************************** +#define USB_ULPIREGDATA_REGDATA_M \ + 0x000000FF // Register Data +#define USB_ULPIREGDATA_REGDATA_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_ULPIREGADDR +// register. +// +//***************************************************************************** +#define USB_ULPIREGADDR_ADDR_M 0x000000FF // Register Address +#define USB_ULPIREGADDR_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_ULPIREGCTL +// register. +// +//***************************************************************************** +#define USB_ULPIREGCTL_RDWR 0x00000004 // Read/Write Control +#define USB_ULPIREGCTL_REGCMPLT 0x00000002 // Register Access Complete +#define USB_ULPIREGCTL_REGACC 0x00000001 // Initiate Register Access + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPINFO register. +// +//***************************************************************************** +#define USB_EPINFO_RXEP_M 0x000000F0 // RX Endpoints +#define USB_EPINFO_TXEP_M 0x0000000F // TX Endpoints +#define USB_EPINFO_RXEP_S 4 +#define USB_EPINFO_TXEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RAMINFO register. +// +//***************************************************************************** +#define USB_RAMINFO_DMACHAN_M 0x000000F0 // DMA Channels +#define USB_RAMINFO_RAMBITS_M 0x0000000F // RAM Address Bus Width +#define USB_RAMINFO_DMACHAN_S 4 +#define USB_RAMINFO_RAMBITS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CONTIM register. +// +//***************************************************************************** +#define USB_CONTIM_WTCON_M 0x000000F0 // Connect Wait +#define USB_CONTIM_WTID_M 0x0000000F // Wait ID +#define USB_CONTIM_WTCON_S 4 +#define USB_CONTIM_WTID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VPLEN register. +// +//***************************************************************************** +#define USB_VPLEN_VPLEN_M 0x000000FF // VBUS Pulse Length +#define USB_VPLEN_VPLEN_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_HSEOF register. +// +//***************************************************************************** +#define USB_HSEOF_HSEOFG_M 0x000000FF // HIgh-Speed End-of-Frame Gap +#define USB_HSEOF_HSEOFG_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FSEOF register. +// +//***************************************************************************** +#define USB_FSEOF_FSEOFG_M 0x000000FF // Full-Speed End-of-Frame Gap +#define USB_FSEOF_FSEOFG_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LSEOF register. +// +//***************************************************************************** +#define USB_LSEOF_LSEOFG_M 0x000000FF // Low-Speed End-of-Frame Gap +#define USB_LSEOF_LSEOFG_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR0 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR0_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR0_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR0 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR0_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR0_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT0 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT0_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT0_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR1 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR1_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR1 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR1_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT1 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT1_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT1_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR1 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR1_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR1 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR1_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT1 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT1_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT1_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR2 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR2_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR2 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR2_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT2 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT2_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT2_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR2 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR2_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR2 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR2_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT2 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT2_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT2_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR3 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR3_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR3 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR3_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT3 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT3_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT3_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR3 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR3_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR3 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR3_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT3 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT3_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT3_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR4 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR4_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR4 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR4_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT4 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT4_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT4_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR4 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR4_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR4 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR4_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT4 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT4_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT4_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR5 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR5_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR5 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR5_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT5 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT5_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT5_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR5 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR5_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR5 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR5_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT5 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT5_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT5_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR6 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR6_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR6 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR6_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT6 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT6_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT6_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR6 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR6_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR6 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR6_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT6 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT6_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT6_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR7 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR7_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR7 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR7_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT7 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT7_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT7_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR7 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR7_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR7 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR7_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT7 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT7_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT7_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CSRL0 register. +// +//***************************************************************************** +#define USB_CSRL0_NAKTO 0x00000080 // NAK Timeout +#define USB_CSRL0_SETENDC 0x00000080 // Setup End Clear +#define USB_CSRL0_STATUS 0x00000040 // STATUS Packet +#define USB_CSRL0_RXRDYC 0x00000040 // RXRDY Clear +#define USB_CSRL0_REQPKT 0x00000020 // Request Packet +#define USB_CSRL0_STALL 0x00000020 // Send Stall +#define USB_CSRL0_SETEND 0x00000010 // Setup End +#define USB_CSRL0_ERROR 0x00000010 // Error +#define USB_CSRL0_DATAEND 0x00000008 // Data End +#define USB_CSRL0_SETUP 0x00000008 // Setup Packet +#define USB_CSRL0_STALLED 0x00000004 // Endpoint Stalled +#define USB_CSRL0_TXRDY 0x00000002 // Transmit Packet Ready +#define USB_CSRL0_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CSRH0 register. +// +//***************************************************************************** +#define USB_CSRH0_DISPING 0x00000008 // PING Disable +#define USB_CSRH0_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_CSRH0_DT 0x00000002 // Data Toggle +#define USB_CSRH0_FLUSH 0x00000001 // Flush FIFO + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_COUNT0 register. +// +//***************************************************************************** +#define USB_COUNT0_COUNT_M 0x0000007F // FIFO Count +#define USB_COUNT0_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TYPE0 register. +// +//***************************************************************************** +#define USB_TYPE0_SPEED_M 0x000000C0 // Operating Speed +#define USB_TYPE0_SPEED_HIGH 0x00000040 // High +#define USB_TYPE0_SPEED_FULL 0x00000080 // Full +#define USB_TYPE0_SPEED_LOW 0x000000C0 // Low + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_NAKLMT register. +// +//***************************************************************************** +#define USB_NAKLMT_NAKLMT_M 0x0000001F // EP0 NAK Limit +#define USB_NAKLMT_NAKLMT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP1 register. +// +//***************************************************************************** +#define USB_TXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP1_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL1 register. +// +//***************************************************************************** +#define USB_TXCSRL1_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL1_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL1_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL1_STALL 0x00000010 // Send STALL +#define USB_TXCSRL1_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL1_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL1_ERROR 0x00000004 // Error +#define USB_TXCSRL1_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL1_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL1_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH1 register. +// +//***************************************************************************** +#define USB_TXCSRH1_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH1_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH1_MODE 0x00000020 // Mode +#define USB_TXCSRH1_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH1_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH1_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH1_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH1_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP1 register. +// +//***************************************************************************** +#define USB_RXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP1_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL1 register. +// +//***************************************************************************** +#define USB_RXCSRL1_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL1_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL1_STALL 0x00000020 // Send STALL +#define USB_RXCSRL1_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL1_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL1_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL1_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL1_OVER 0x00000004 // Overrun +#define USB_RXCSRL1_ERROR 0x00000004 // Error +#define USB_RXCSRL1_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL1_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH1 register. +// +//***************************************************************************** +#define USB_RXCSRH1_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH1_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH1_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH1_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH1_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH1_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH1_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH1_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH1_DT 0x00000002 // Data Toggle +#define USB_RXCSRH1_INCOMPRX 0x00000001 // Incomplete RX Transmission + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT1 register. +// +//***************************************************************************** +#define USB_RXCOUNT1_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT1_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE1 register. +// +//***************************************************************************** +#define USB_TXTYPE1_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE1_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE1_SPEED_HIGH 0x00000040 // High +#define USB_TXTYPE1_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE1_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE1_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE1_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE1_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE1_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE1_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE1_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE1_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL1 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL1_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL1_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL1_TXPOLL_S \ + 0 +#define USB_TXINTERVAL1_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE1 register. +// +//***************************************************************************** +#define USB_RXTYPE1_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE1_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE1_SPEED_HIGH 0x00000040 // High +#define USB_RXTYPE1_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE1_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE1_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE1_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE1_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE1_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE1_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE1_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE1_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL1 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL1_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL1_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL1_TXPOLL_S \ + 0 +#define USB_RXINTERVAL1_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP2 register. +// +//***************************************************************************** +#define USB_TXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP2_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL2 register. +// +//***************************************************************************** +#define USB_TXCSRL2_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL2_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL2_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL2_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL2_STALL 0x00000010 // Send STALL +#define USB_TXCSRL2_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL2_ERROR 0x00000004 // Error +#define USB_TXCSRL2_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL2_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL2_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH2 register. +// +//***************************************************************************** +#define USB_TXCSRH2_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH2_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH2_MODE 0x00000020 // Mode +#define USB_TXCSRH2_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH2_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH2_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH2_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH2_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP2 register. +// +//***************************************************************************** +#define USB_RXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP2_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL2 register. +// +//***************************************************************************** +#define USB_RXCSRL2_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL2_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL2_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL2_STALL 0x00000020 // Send STALL +#define USB_RXCSRL2_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL2_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL2_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL2_ERROR 0x00000004 // Error +#define USB_RXCSRL2_OVER 0x00000004 // Overrun +#define USB_RXCSRL2_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL2_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH2 register. +// +//***************************************************************************** +#define USB_RXCSRH2_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH2_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH2_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH2_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH2_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH2_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH2_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH2_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH2_DT 0x00000002 // Data Toggle +#define USB_RXCSRH2_INCOMPRX 0x00000001 // Incomplete RX Transmission + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT2 register. +// +//***************************************************************************** +#define USB_RXCOUNT2_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT2_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE2 register. +// +//***************************************************************************** +#define USB_TXTYPE2_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE2_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE2_SPEED_HIGH 0x00000040 // High +#define USB_TXTYPE2_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE2_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE2_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE2_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE2_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE2_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE2_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE2_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE2_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL2 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL2_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL2_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL2_NAKLMT_S \ + 0 +#define USB_TXINTERVAL2_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE2 register. +// +//***************************************************************************** +#define USB_RXTYPE2_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE2_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE2_SPEED_HIGH 0x00000040 // High +#define USB_RXTYPE2_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE2_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE2_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE2_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE2_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE2_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE2_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE2_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE2_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL2 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL2_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL2_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL2_TXPOLL_S \ + 0 +#define USB_RXINTERVAL2_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP3 register. +// +//***************************************************************************** +#define USB_TXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP3_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL3 register. +// +//***************************************************************************** +#define USB_TXCSRL3_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL3_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL3_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL3_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL3_STALL 0x00000010 // Send STALL +#define USB_TXCSRL3_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL3_ERROR 0x00000004 // Error +#define USB_TXCSRL3_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL3_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL3_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH3 register. +// +//***************************************************************************** +#define USB_TXCSRH3_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH3_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH3_MODE 0x00000020 // Mode +#define USB_TXCSRH3_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH3_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH3_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH3_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH3_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP3 register. +// +//***************************************************************************** +#define USB_RXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP3_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL3 register. +// +//***************************************************************************** +#define USB_RXCSRL3_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL3_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL3_STALL 0x00000020 // Send STALL +#define USB_RXCSRL3_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL3_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL3_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL3_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL3_ERROR 0x00000004 // Error +#define USB_RXCSRL3_OVER 0x00000004 // Overrun +#define USB_RXCSRL3_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL3_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH3 register. +// +//***************************************************************************** +#define USB_RXCSRH3_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH3_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH3_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH3_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH3_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH3_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH3_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH3_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH3_DT 0x00000002 // Data Toggle +#define USB_RXCSRH3_INCOMPRX 0x00000001 // Incomplete RX Transmission + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT3 register. +// +//***************************************************************************** +#define USB_RXCOUNT3_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT3_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE3 register. +// +//***************************************************************************** +#define USB_TXTYPE3_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE3_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE3_SPEED_HIGH 0x00000040 // High +#define USB_TXTYPE3_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE3_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE3_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE3_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE3_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE3_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE3_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE3_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE3_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL3 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL3_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL3_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL3_TXPOLL_S \ + 0 +#define USB_TXINTERVAL3_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE3 register. +// +//***************************************************************************** +#define USB_RXTYPE3_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE3_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE3_SPEED_HIGH 0x00000040 // High +#define USB_RXTYPE3_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE3_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE3_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE3_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE3_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE3_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE3_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE3_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE3_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL3 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL3_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL3_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL3_TXPOLL_S \ + 0 +#define USB_RXINTERVAL3_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP4 register. +// +//***************************************************************************** +#define USB_TXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP4_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL4 register. +// +//***************************************************************************** +#define USB_TXCSRL4_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL4_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL4_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL4_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL4_STALL 0x00000010 // Send STALL +#define USB_TXCSRL4_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL4_ERROR 0x00000004 // Error +#define USB_TXCSRL4_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL4_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL4_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH4 register. +// +//***************************************************************************** +#define USB_TXCSRH4_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH4_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH4_MODE 0x00000020 // Mode +#define USB_TXCSRH4_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH4_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH4_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH4_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH4_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP4 register. +// +//***************************************************************************** +#define USB_RXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP4_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL4 register. +// +//***************************************************************************** +#define USB_RXCSRL4_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL4_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL4_STALL 0x00000020 // Send STALL +#define USB_RXCSRL4_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL4_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL4_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL4_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL4_OVER 0x00000004 // Overrun +#define USB_RXCSRL4_ERROR 0x00000004 // Error +#define USB_RXCSRL4_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL4_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH4 register. +// +//***************************************************************************** +#define USB_RXCSRH4_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH4_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH4_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH4_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH4_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH4_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH4_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH4_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH4_DT 0x00000002 // Data Toggle +#define USB_RXCSRH4_INCOMPRX 0x00000001 // Incomplete RX Transmission + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT4 register. +// +//***************************************************************************** +#define USB_RXCOUNT4_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT4_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE4 register. +// +//***************************************************************************** +#define USB_TXTYPE4_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE4_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE4_SPEED_HIGH 0x00000040 // High +#define USB_TXTYPE4_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE4_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE4_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE4_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE4_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE4_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE4_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE4_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE4_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL4 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL4_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL4_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL4_NAKLMT_S \ + 0 +#define USB_TXINTERVAL4_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE4 register. +// +//***************************************************************************** +#define USB_RXTYPE4_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE4_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE4_SPEED_HIGH 0x00000040 // High +#define USB_RXTYPE4_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE4_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE4_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE4_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE4_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE4_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE4_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE4_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE4_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL4 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL4_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL4_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL4_NAKLMT_S \ + 0 +#define USB_RXINTERVAL4_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP5 register. +// +//***************************************************************************** +#define USB_TXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP5_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL5 register. +// +//***************************************************************************** +#define USB_TXCSRL5_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL5_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL5_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL5_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL5_STALL 0x00000010 // Send STALL +#define USB_TXCSRL5_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL5_ERROR 0x00000004 // Error +#define USB_TXCSRL5_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL5_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL5_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH5 register. +// +//***************************************************************************** +#define USB_TXCSRH5_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH5_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH5_MODE 0x00000020 // Mode +#define USB_TXCSRH5_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH5_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH5_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH5_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH5_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP5 register. +// +//***************************************************************************** +#define USB_RXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP5_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL5 register. +// +//***************************************************************************** +#define USB_RXCSRL5_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL5_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL5_STALL 0x00000020 // Send STALL +#define USB_RXCSRL5_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL5_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL5_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL5_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL5_ERROR 0x00000004 // Error +#define USB_RXCSRL5_OVER 0x00000004 // Overrun +#define USB_RXCSRL5_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL5_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH5 register. +// +//***************************************************************************** +#define USB_RXCSRH5_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH5_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH5_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH5_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH5_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH5_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH5_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH5_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH5_DT 0x00000002 // Data Toggle +#define USB_RXCSRH5_INCOMPRX 0x00000001 // Incomplete RX Transmission + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT5 register. +// +//***************************************************************************** +#define USB_RXCOUNT5_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT5_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE5 register. +// +//***************************************************************************** +#define USB_TXTYPE5_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE5_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE5_SPEED_HIGH 0x00000040 // High +#define USB_TXTYPE5_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE5_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE5_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE5_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE5_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE5_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE5_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE5_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE5_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL5 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL5_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL5_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL5_NAKLMT_S \ + 0 +#define USB_TXINTERVAL5_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE5 register. +// +//***************************************************************************** +#define USB_RXTYPE5_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE5_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE5_SPEED_HIGH 0x00000040 // High +#define USB_RXTYPE5_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE5_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE5_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE5_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE5_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE5_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE5_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE5_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE5_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL5 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL5_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL5_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL5_TXPOLL_S \ + 0 +#define USB_RXINTERVAL5_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP6 register. +// +//***************************************************************************** +#define USB_TXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP6_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL6 register. +// +//***************************************************************************** +#define USB_TXCSRL6_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL6_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL6_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL6_STALL 0x00000010 // Send STALL +#define USB_TXCSRL6_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL6_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL6_ERROR 0x00000004 // Error +#define USB_TXCSRL6_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL6_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL6_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH6 register. +// +//***************************************************************************** +#define USB_TXCSRH6_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH6_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH6_MODE 0x00000020 // Mode +#define USB_TXCSRH6_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH6_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH6_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH6_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH6_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP6 register. +// +//***************************************************************************** +#define USB_RXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP6_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL6 register. +// +//***************************************************************************** +#define USB_RXCSRL6_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL6_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL6_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL6_STALL 0x00000020 // Send STALL +#define USB_RXCSRL6_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL6_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL6_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL6_ERROR 0x00000004 // Error +#define USB_RXCSRL6_OVER 0x00000004 // Overrun +#define USB_RXCSRL6_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL6_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH6 register. +// +//***************************************************************************** +#define USB_RXCSRH6_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH6_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH6_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH6_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH6_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH6_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH6_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH6_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH6_DT 0x00000002 // Data Toggle +#define USB_RXCSRH6_INCOMPRX 0x00000001 // Incomplete RX Transmission + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT6 register. +// +//***************************************************************************** +#define USB_RXCOUNT6_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT6_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE6 register. +// +//***************************************************************************** +#define USB_TXTYPE6_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE6_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE6_SPEED_HIGH 0x00000040 // High +#define USB_TXTYPE6_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE6_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE6_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE6_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE6_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE6_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE6_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE6_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE6_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL6 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL6_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL6_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL6_TXPOLL_S \ + 0 +#define USB_TXINTERVAL6_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE6 register. +// +//***************************************************************************** +#define USB_RXTYPE6_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE6_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE6_SPEED_HIGH 0x00000040 // High +#define USB_RXTYPE6_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE6_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE6_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE6_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE6_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE6_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE6_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE6_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE6_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL6 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL6_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL6_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL6_NAKLMT_S \ + 0 +#define USB_RXINTERVAL6_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP7 register. +// +//***************************************************************************** +#define USB_TXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP7_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL7 register. +// +//***************************************************************************** +#define USB_TXCSRL7_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL7_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL7_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL7_STALL 0x00000010 // Send STALL +#define USB_TXCSRL7_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL7_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL7_ERROR 0x00000004 // Error +#define USB_TXCSRL7_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL7_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL7_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH7 register. +// +//***************************************************************************** +#define USB_TXCSRH7_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH7_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH7_MODE 0x00000020 // Mode +#define USB_TXCSRH7_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH7_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH7_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH7_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH7_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP7 register. +// +//***************************************************************************** +#define USB_RXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP7_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL7 register. +// +//***************************************************************************** +#define USB_RXCSRL7_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL7_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL7_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL7_STALL 0x00000020 // Send STALL +#define USB_RXCSRL7_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL7_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL7_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL7_ERROR 0x00000004 // Error +#define USB_RXCSRL7_OVER 0x00000004 // Overrun +#define USB_RXCSRL7_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL7_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH7 register. +// +//***************************************************************************** +#define USB_RXCSRH7_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH7_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH7_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH7_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH7_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH7_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH7_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH7_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH7_DT 0x00000002 // Data Toggle +#define USB_RXCSRH7_INCOMPRX 0x00000001 // Incomplete RX Transmission + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT7 register. +// +//***************************************************************************** +#define USB_RXCOUNT7_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT7_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE7 register. +// +//***************************************************************************** +#define USB_TXTYPE7_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE7_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE7_SPEED_HIGH 0x00000040 // High +#define USB_TXTYPE7_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE7_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE7_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE7_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE7_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE7_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE7_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE7_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE7_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL7 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL7_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL7_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL7_NAKLMT_S \ + 0 +#define USB_TXINTERVAL7_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE7 register. +// +//***************************************************************************** +#define USB_RXTYPE7_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE7_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE7_SPEED_HIGH 0x00000040 // High +#define USB_RXTYPE7_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE7_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE7_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE7_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE7_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE7_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE7_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE7_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE7_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL7 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL7_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL7_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL7_NAKLMT_S \ + 0 +#define USB_RXINTERVAL7_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAINTR register. +// +//***************************************************************************** +#define USB_DMAINTR_CH7 0x00000080 // Channel 7 DMA Interrupt +#define USB_DMAINTR_CH6 0x00000040 // Channel 6 DMA Interrupt +#define USB_DMAINTR_CH5 0x00000020 // Channel 5 DMA Interrupt +#define USB_DMAINTR_CH4 0x00000010 // Channel 4 DMA Interrupt +#define USB_DMAINTR_CH3 0x00000008 // Channel 3 DMA Interrupt +#define USB_DMAINTR_CH2 0x00000004 // Channel 2 DMA Interrupt +#define USB_DMAINTR_CH1 0x00000002 // Channel 1 DMA Interrupt +#define USB_DMAINTR_CH0 0x00000001 // Channel 0 DMA Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL0 register. +// +//***************************************************************************** +#define USB_DMACTL0_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL0_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL0_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL0_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL0_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL0_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL0_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL0_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL0_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL0_DIR 0x00000002 // DMA Direction +#define USB_DMACTL0_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL0_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR0 register. +// +//***************************************************************************** +#define USB_DMAADDR0_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR0_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT0 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT0_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT0_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL1 register. +// +//***************************************************************************** +#define USB_DMACTL1_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL1_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL1_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL1_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL1_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL1_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL1_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL1_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL1_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL1_DIR 0x00000002 // DMA Direction +#define USB_DMACTL1_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL1_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR1 register. +// +//***************************************************************************** +#define USB_DMAADDR1_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR1_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT1 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT1_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT1_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL2 register. +// +//***************************************************************************** +#define USB_DMACTL2_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL2_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL2_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL2_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL2_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL2_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL2_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL2_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL2_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL2_DIR 0x00000002 // DMA Direction +#define USB_DMACTL2_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL2_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR2 register. +// +//***************************************************************************** +#define USB_DMAADDR2_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR2_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT2 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT2_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT2_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL3 register. +// +//***************************************************************************** +#define USB_DMACTL3_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL3_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL3_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL3_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL3_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL3_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL3_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL3_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL3_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL3_DIR 0x00000002 // DMA Direction +#define USB_DMACTL3_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL3_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR3 register. +// +//***************************************************************************** +#define USB_DMAADDR3_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR3_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT3 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT3_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT3_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL4 register. +// +//***************************************************************************** +#define USB_DMACTL4_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL4_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL4_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL4_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL4_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL4_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL4_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL4_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL4_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL4_DIR 0x00000002 // DMA Direction +#define USB_DMACTL4_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL4_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR4 register. +// +//***************************************************************************** +#define USB_DMAADDR4_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR4_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT4 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT4_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT4_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL5 register. +// +//***************************************************************************** +#define USB_DMACTL5_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL5_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL5_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL5_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL5_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL5_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL5_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL5_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL5_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL5_DIR 0x00000002 // DMA Direction +#define USB_DMACTL5_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL5_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR5 register. +// +//***************************************************************************** +#define USB_DMAADDR5_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR5_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT5 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT5_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT5_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL6 register. +// +//***************************************************************************** +#define USB_DMACTL6_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL6_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL6_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL6_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL6_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL6_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL6_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL6_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL6_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL6_DIR 0x00000002 // DMA Direction +#define USB_DMACTL6_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL6_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR6 register. +// +//***************************************************************************** +#define USB_DMAADDR6_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR6_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT6 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT6_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT6_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL7 register. +// +//***************************************************************************** +#define USB_DMACTL7_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL7_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL7_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL7_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL7_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL7_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL7_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL7_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL7_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL7_DIR 0x00000002 // DMA Direction +#define USB_DMACTL7_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL7_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR7 register. +// +//***************************************************************************** +#define USB_DMAADDR7_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR7_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT7 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT7_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT7_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT1_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT1_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT2 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT2_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT2_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT3 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT3_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT3_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT4 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT4_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT4_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT5 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT5_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT5_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT6 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT6_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT6_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT7 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT7_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT7_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS +// register. +// +//***************************************************************************** +#define USB_RXDPKTBUFDIS_EP7 0x00000080 // EP7 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP6 0x00000040 // EP6 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP5 0x00000020 // EP5 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP4 0x00000010 // EP4 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP3 0x00000008 // EP3 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP2 0x00000004 // EP2 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP1 0x00000002 // EP1 RX Double-Packet Buffer + // Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS +// register. +// +//***************************************************************************** +#define USB_TXDPKTBUFDIS_EP7 0x00000080 // EP7 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP6 0x00000040 // EP6 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP5 0x00000020 // EP5 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP4 0x00000010 // EP4 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP3 0x00000008 // EP3 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP2 0x00000004 // EP2 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP1 0x00000002 // EP1 TX Double-Packet Buffer + // Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CTO register. +// +//***************************************************************************** +#define USB_CTO_CCTV_M 0x0000FFFF // Configurable Chirp Timeout Value +#define USB_CTO_CCTV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_HHSRTN register. +// +//***************************************************************************** +#define USB_HHSRTN_HHSRTN_M 0x0000FFFF // HIgh Speed to UTM Operating + // Delay +#define USB_HHSRTN_HHSRTN_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_HSBT register. +// +//***************************************************************************** +#define USB_HSBT_HSBT_M 0x0000000F // High Speed Timeout Adder +#define USB_HSBT_HSBT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LPMATTR register. +// +//***************************************************************************** +#define USB_LPMATTR_ENDPT_M 0x0000F000 // Endpoint +#define USB_LPMATTR_RMTWAK 0x00000100 // Remote Wake +#define USB_LPMATTR_HIRD_M 0x000000F0 // Host Initiated Resume Duration +#define USB_LPMATTR_LS_M 0x0000000F // Link State +#define USB_LPMATTR_LS_L1 0x00000001 // Sleep State (L1) +#define USB_LPMATTR_ENDPT_S 12 +#define USB_LPMATTR_HIRD_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LPMCNTRL register. +// +//***************************************************************************** +#define USB_LPMCNTRL_NAK 0x00000010 // LPM NAK +#define USB_LPMCNTRL_EN_M 0x0000000C // LPM Enable +#define USB_LPMCNTRL_EN_NONE 0x00000000 // LPM and Extended transactions + // are not supported. In this case, + // the USB does not respond to LPM + // transactions and LPM + // transactions cause a timeout +#define USB_LPMCNTRL_EN_EXT 0x00000004 // LPM is not supported but + // extended transactions are + // supported. In this case, the USB + // does respond to an LPM + // transaction with a STALL +#define USB_LPMCNTRL_EN_LPMEXT 0x0000000C // The USB supports LPM extended + // transactions. In this case, the + // USB responds with a NYET or an + // ACK as determined by the value + // of TXLPM and other conditions +#define USB_LPMCNTRL_RES 0x00000002 // LPM Resume +#define USB_LPMCNTRL_TXLPM 0x00000001 // Transmit LPM Transaction Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LPMIM register. +// +//***************************************************************************** +#define USB_LPMIM_ERR 0x00000020 // LPM Error Interrupt Mask +#define USB_LPMIM_RES 0x00000010 // LPM Resume Interrupt Mask +#define USB_LPMIM_NC 0x00000008 // LPM NC Interrupt Mask +#define USB_LPMIM_ACK 0x00000004 // LPM ACK Interrupt Mask +#define USB_LPMIM_NY 0x00000002 // LPM NY Interrupt Mask +#define USB_LPMIM_STALL 0x00000001 // LPM STALL Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LPMRIS register. +// +//***************************************************************************** +#define USB_LPMRIS_ERR 0x00000020 // LPM Interrupt Status +#define USB_LPMRIS_RES 0x00000010 // LPM Resume Interrupt Status +#define USB_LPMRIS_NC 0x00000008 // LPM NC Interrupt Status +#define USB_LPMRIS_ACK 0x00000004 // LPM ACK Interrupt Status +#define USB_LPMRIS_NY 0x00000002 // LPM NY Interrupt Status +#define USB_LPMRIS_LPMST 0x00000001 // LPM STALL Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LPMFADDR register. +// +//***************************************************************************** +#define USB_LPMFADDR_ADDR_M 0x0000007F // LPM Function Address +#define USB_LPMFADDR_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPC register. +// +//***************************************************************************** +#define USB_EPC_PFLTACT_M 0x00000300 // Power Fault Action +#define USB_EPC_PFLTACT_UNCHG 0x00000000 // Unchanged +#define USB_EPC_PFLTACT_TRIS 0x00000100 // Tristate +#define USB_EPC_PFLTACT_LOW 0x00000200 // Low +#define USB_EPC_PFLTACT_HIGH 0x00000300 // High +#define USB_EPC_PFLTAEN 0x00000040 // Power Fault Action Enable +#define USB_EPC_PFLTSEN_HIGH 0x00000020 // Power Fault Sense +#define USB_EPC_PFLTEN 0x00000010 // Power Fault Input Enable +#define USB_EPC_EPENDE 0x00000004 // EPEN Drive Enable +#define USB_EPC_EPEN_M 0x00000003 // External Power Supply Enable + // Configuration +#define USB_EPC_EPEN_LOW 0x00000000 // Power Enable Active Low +#define USB_EPC_EPEN_HIGH 0x00000001 // Power Enable Active High +#define USB_EPC_EPEN_VBLOW 0x00000002 // Power Enable High if VBUS Low + // (OTG only) +#define USB_EPC_EPEN_VBHIGH 0x00000003 // Power Enable High if VBUS High + // (OTG only) + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCRIS register. +// +//***************************************************************************** +#define USB_EPCRIS_PF 0x00000001 // USB Power Fault Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCIM register. +// +//***************************************************************************** +#define USB_EPCIM_PF 0x00000001 // USB Power Fault Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCISC register. +// +//***************************************************************************** +#define USB_EPCISC_PF 0x00000001 // USB Power Fault Interrupt Status + // and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRRIS register. +// +//***************************************************************************** +#define USB_DRRIS_RESUME 0x00000001 // RESUME Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRIM register. +// +//***************************************************************************** +#define USB_DRIM_RESUME 0x00000001 // RESUME Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRISC register. +// +//***************************************************************************** +#define USB_DRISC_RESUME 0x00000001 // RESUME Interrupt Status and + // Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_GPCS register. +// +//***************************************************************************** +#define USB_GPCS_DEVMOD_M 0x00000007 // Device Mode +#define USB_GPCS_DEVMOD_OTG 0x00000000 // Use USB0VBUS and USB0ID pin +#define USB_GPCS_DEVMOD_HOST 0x00000002 // Force USB0VBUS and USB0ID low +#define USB_GPCS_DEVMOD_DEV 0x00000003 // Force USB0VBUS and USB0ID high +#define USB_GPCS_DEVMOD_HOSTVBUS \ + 0x00000004 // Use USB0VBUS and force USB0ID + // low +#define USB_GPCS_DEVMOD_DEVVBUS 0x00000005 // Use USB0VBUS and force USB0ID + // high + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDC register. +// +//***************************************************************************** +#define USB_VDC_VBDEN 0x00000001 // VBUS Droop Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCRIS register. +// +//***************************************************************************** +#define USB_VDCRIS_VD 0x00000001 // VBUS Droop Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCIM register. +// +//***************************************************************************** +#define USB_VDCIM_VD 0x00000001 // VBUS Droop Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCISC register. +// +//***************************************************************************** +#define USB_VDCISC_VD 0x00000001 // VBUS Droop Interrupt Status and + // Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_PP register. +// +//***************************************************************************** +#define USB_PP_ECNT_M 0x0000FF00 // Endpoint Count +#define USB_PP_USB_M 0x000000C0 // USB Capability +#define USB_PP_USB_DEVICE 0x00000040 // DEVICE +#define USB_PP_USB_HOSTDEVICE 0x00000080 // HOST +#define USB_PP_USB_OTG 0x000000C0 // OTG +#define USB_PP_ULPI 0x00000020 // ULPI Present +#define USB_PP_PHY 0x00000010 // PHY Present +#define USB_PP_TYPE_M 0x0000000F // Controller Type +#define USB_PP_TYPE_0 0x00000000 // The first-generation USB + // controller +#define USB_PP_TYPE_1 0x00000001 // The second-generation USB + // controller revision +#define USB_PP_ECNT_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_PC register. +// +//***************************************************************************** +#define USB_PC_ULPIEN 0x00010000 // ULPI Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CC register. +// +//***************************************************************************** +#define USB_CC_CLKEN 0x00000200 // USB Clock Enable +#define USB_CC_CSD 0x00000100 // Clock Source/Direction +#define USB_CC_CLKDIV_M 0x0000000F // PLL Clock Divisor +#define USB_CC_CLKDIV_S 0 + +#ifdef __cplusplus + } +#endif + +#endif -- cgit v1.3.1 From 1e308dd6c096d9078b3cbe8ff387dcec6e83e71d Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 8 Nov 2021 19:18:52 +0700 Subject: reduce CFG_TUD_DFU_XFER_BUFSIZE for max compatible --- examples/device/dfu/src/tusb_config.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/examples/device/dfu/src/tusb_config.h b/examples/device/dfu/src/tusb_config.h index 66e357021..012d50019 100644 --- a/examples/device/dfu/src/tusb_config.h +++ b/examples/device/dfu/src/tusb_config.h @@ -80,7 +80,7 @@ #define CFG_TUD_DFU 1 // DFU buffer size, it has to be set to the buffer size used in TUD_DFU_DESCRIPTOR -#define CFG_TUD_DFU_XFER_BUFSIZE 512 +#define CFG_TUD_DFU_XFER_BUFSIZE ( OPT_MODE_HIGH_SPEED ? 512 : 64 ) #ifdef __cplusplus } -- cgit v1.3.1 From 1c77f9f6694151beca9a490eadf545b30557e9a0 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 8 Nov 2021 20:03:47 +0700 Subject: msp432e4 ci typo, skip dfu example for tm4c123 --- .github/workflows/build_arm.yml | 2 +- examples/device/dfu/.skip.MCU_TM4C123 | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) create mode 100644 examples/device/dfu/.skip.MCU_TM4C123 diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml index e4d64826e..dc4d9fcfb 100644 --- a/.github/workflows/build_arm.yml +++ b/.github/workflows/build_arm.yml @@ -45,7 +45,7 @@ jobs: - 'lpc54' - 'lpc55' - 'mm32' - - 'msp430e4' + - 'msp432e4' - 'nrf' - 'rp2040' - 'samd11' diff --git a/examples/device/dfu/.skip.MCU_TM4C123 b/examples/device/dfu/.skip.MCU_TM4C123 new file mode 100644 index 000000000..6260e6e25 --- /dev/null +++ b/examples/device/dfu/.skip.MCU_TM4C123 @@ -0,0 +1,4 @@ +LINK _build/ek-tm4c123gxl/dfu.elf +/home/runner/cache/toolchain/xpack-arm-none-eabi-gcc-10.2.1-1.1/bin/../lib/gcc/arm-none-eabi/10.2.1/../../../../arm-none-eabi/bin/ld: section .ARM.exidx.text._close LMA [0000000000002980,0000000000002987] overlaps section .data LMA [0000000000002980,0000000000002a03] +collect2: error: ld returned 1 exit status +make: *** [../../rules.mk:94: _build/ek-tm4c123gxl/dfu.elf] Error 1 \ No newline at end of file -- cgit v1.3.1 From 12e96ce571e3ca8d9771d4729eb65bd296acb72e Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 15 Nov 2021 12:18:28 +0700 Subject: set DCFG_XCVRDLY when using external ULPI highspeed phy --- src/portable/synopsys/dwc2/dcd_dwc2.c | 4 ++++ src/portable/synopsys/dwc2/dwc2_type.h | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 44a5f8932..30b8aed69 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -444,6 +444,10 @@ static void phy_hs_init(dwc2_regs_t * dwc2) // Set max speed dwc2->dcfg = (dwc2->dcfg & ~DCFG_DSPD_Msk) | (DCFG_DSPD_HS << DCFG_DSPD_Pos); + + // XCVRDLY: transceiver delay between xcvr_sel and txvalid during device chirp is required + // when using with some PHYs such as USB334x (USB3341, USB3343, USB3346, USB3347) + if (dwc2->ghwcfg2_bm.hs_phy_type == HS_PHY_TYPE_ULPI) dwc2->dcfg |= DCFG_XCVRDLY; } static bool check_dwc2(dwc2_regs_t * dwc2) diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index 6e52ebc7b..dbef20314 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -416,6 +416,10 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define DCFG_PFIVL_0 (0x1UL << DCFG_PFIVL_Pos) // 0x00000800 */ #define DCFG_PFIVL_1 (0x2UL << DCFG_PFIVL_Pos) // 0x00001000 */ +#define DCFG_XCVRDLY_Pos (14U) +#define DCFG_XCVRDLY_Msk (0x1UL << DCFG_XCVRDLY_Pos) /*!< 0x00004000 */ +#define DCFG_XCVRDLY DCFG_XCVRDLY_Msk // Enables delay between xcvr_sel and txvalid during device chirp + #define DCFG_PERSCHIVL_Pos (24U) #define DCFG_PERSCHIVL_Msk (0x3UL << DCFG_PERSCHIVL_Pos) // 0x03000000 */ #define DCFG_PERSCHIVL DCFG_PERSCHIVL_Msk // Periodic scheduling interval */ -- cgit v1.3.1 From 301d6b413382e6601c6ca54522e207776e2316fb Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 17 Nov 2021 09:48:08 +0700 Subject: clean up --- src/portable/synopsys/dwc2/dcd_dwc2.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 30b8aed69..bb21b3dcd 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -443,11 +443,15 @@ static void phy_hs_init(dwc2_regs_t * dwc2) dwc2_phy_update(dwc2, dwc2->ghwcfg2_bm.hs_phy_type); // Set max speed - dwc2->dcfg = (dwc2->dcfg & ~DCFG_DSPD_Msk) | (DCFG_DSPD_HS << DCFG_DSPD_Pos); + uint32_t dcfg = dwc2->dcfg; + dcfg &= ~DCFG_DSPD_Msk; + dcfg |= DCFG_DSPD_HS << DCFG_DSPD_Pos; // XCVRDLY: transceiver delay between xcvr_sel and txvalid during device chirp is required // when using with some PHYs such as USB334x (USB3341, USB3343, USB3346, USB3347) - if (dwc2->ghwcfg2_bm.hs_phy_type == HS_PHY_TYPE_ULPI) dwc2->dcfg |= DCFG_XCVRDLY; + if (dwc2->ghwcfg2_bm.hs_phy_type == HS_PHY_TYPE_ULPI) dcfg |= DCFG_XCVRDLY; + + dwc2->dcfg = dcfg; } static bool check_dwc2(dwc2_regs_t * dwc2) -- cgit v1.3.1 From dac7574c98cc6db1b40c244c5bedb81a2b78d0ca Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 22 Nov 2021 10:52:28 +0700 Subject: use USB_OTG_GLOBAL_BASE instead of hard code value --- src/portable/synopsys/dwc2/dwc2_bcm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/portable/synopsys/dwc2/dwc2_bcm.h b/src/portable/synopsys/dwc2/dwc2_bcm.h index fcec0b0d2..353bc21ee 100644 --- a/src/portable/synopsys/dwc2/dwc2_bcm.h +++ b/src/portable/synopsys/dwc2/dwc2_bcm.h @@ -34,7 +34,7 @@ #include "broadcom/interrupts.h" #include "broadcom/caches.h" -#define DWC2_REG_BASE 0xFE980000UL +#define DWC2_REG_BASE USB_OTG_GLOBAL_BASE #define DWC2_EP_MAX 8 #define DWC2_EP_FIFO_SIZE 4096 -- cgit v1.3.1 From 21787ecdd355917db3790be20f35f6f2d5a05a66 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 22 Nov 2021 10:52:53 +0700 Subject: update bcm prph --- hw/mcu/broadcom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/mcu/broadcom b/hw/mcu/broadcom index d126323fc..5bff1d5e0 160000 --- a/hw/mcu/broadcom +++ b/hw/mcu/broadcom @@ -1 +1 @@ -Subproject commit d126323fc77e81d1f18677a439685a4754ea02aa +Subproject commit 5bff1d5e02c37c38ee1e5cf3f7fe82fdc7e1517e -- cgit v1.3.1 From 8a18c22c2f7c15b5c7869428877c1e50157d5856 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 22 Nov 2021 10:59:22 +0700 Subject: add BCM_VERSION --- hw/bsp/raspberrypi4/boards/raspberrypi_cm4/board.mk | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/bsp/raspberrypi4/boards/raspberrypi_cm4/board.mk b/hw/bsp/raspberrypi4/boards/raspberrypi_cm4/board.mk index e69de29bb..897342479 100644 --- a/hw/bsp/raspberrypi4/boards/raspberrypi_cm4/board.mk +++ b/hw/bsp/raspberrypi4/boards/raspberrypi_cm4/board.mk @@ -0,0 +1 @@ +CFLAGS += -DBCM_VERSION=2711 -- cgit v1.3.1 From 64e6170224d86a41db782d5e23fd4baa7f0bc695 Mon Sep 17 00:00:00 2001 From: Ha Thach Date: Mon, 22 Nov 2021 11:26:23 +0700 Subject: Update bug_report.yml --- .github/ISSUE_TEMPLATE/bug_report.yml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/.github/ISSUE_TEMPLATE/bug_report.yml b/.github/ISSUE_TEMPLATE/bug_report.yml index 291b22079..624d0ab7a 100644 --- a/.github/ISSUE_TEMPLATE/bug_report.yml +++ b/.github/ISSUE_TEMPLATE/bug_report.yml @@ -34,7 +34,10 @@ body: label: Firmware placeholder: | e.g examples/device/cdc_msc. - If it is custom firmware, please provide links to your minimal sources or as attached files. + If it is custom firmware, it is preferably compiled like one in example folder and reviewable for people to comment on. The easiest way is + - Fork this repo, checkout a new branch + - Add your-own-example based on stock one + - Push and post it here. validations: required: true @@ -49,6 +52,7 @@ body: attributes: label: How to reproduce ? placeholder: | + Exact steps in chronological order, details should be specific e.g if you use a command/script to test with, please post it as well. 1. Go to '...' 2. Click on '....' 3. See error -- cgit v1.3.1 From e5adc4680547a03ef2d9412305167e5d188dd5d0 Mon Sep 17 00:00:00 2001 From: Ha Thach Date: Mon, 22 Nov 2021 11:27:37 +0700 Subject: Update bug_report.yml --- .github/ISSUE_TEMPLATE/bug_report.yml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/.github/ISSUE_TEMPLATE/bug_report.yml b/.github/ISSUE_TEMPLATE/bug_report.yml index 624d0ab7a..fc41d8ff1 100644 --- a/.github/ISSUE_TEMPLATE/bug_report.yml +++ b/.github/ISSUE_TEMPLATE/bug_report.yml @@ -33,8 +33,7 @@ body: attributes: label: Firmware placeholder: | - e.g examples/device/cdc_msc. - If it is custom firmware, it is preferably compiled like one in example folder and reviewable for people to comment on. The easiest way is + e.g examples/device/cdc_msc. If it is custom firmware, it is preferably compiled like one in example folder and reviewable for people to comment on. The easiest way is - Fork this repo, checkout a new branch - Add your-own-example based on stock one - Push and post it here. -- cgit v1.3.1 From a994540860306e7da80a6925633f1ac8486fbfd9 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 23 Nov 2021 09:36:28 +0700 Subject: fix nrf easy dma race condition --- src/class/cdc/cdc_device.c | 10 +-- src/portable/nordic/nrf5x/dcd_nrf5x.c | 126 +++++++++++++++++----------------- 2 files changed, 70 insertions(+), 66 deletions(-) diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c index 74c116192..08f2af253 100644 --- a/src/class/cdc/cdc_device.c +++ b/src/class/cdc/cdc_device.c @@ -80,7 +80,7 @@ typedef struct //--------------------------------------------------------------------+ CFG_TUSB_MEM_SECTION static cdcd_interface_t _cdcd_itf[CFG_TUD_CDC]; -static void _prep_out_transaction (cdcd_interface_t* p_cdc) +static bool _prep_out_transaction (cdcd_interface_t* p_cdc) { uint8_t const rhport = TUD_OPT_RHPORT; uint16_t available = tu_fifo_remaining(&p_cdc->rx_ff); @@ -89,21 +89,23 @@ static void _prep_out_transaction (cdcd_interface_t* p_cdc) // TODO Actually we can still carry out the transfer, keeping count of received bytes // and slowly move it to the FIFO when read(). // This pre-check reduces endpoint claiming - TU_VERIFY(available >= sizeof(p_cdc->epout_buf), ); + TU_VERIFY(available >= sizeof(p_cdc->epout_buf)); // claim endpoint - TU_VERIFY(usbd_edpt_claim(rhport, p_cdc->ep_out), ); + TU_VERIFY(usbd_edpt_claim(rhport, p_cdc->ep_out)); // fifo can be changed before endpoint is claimed available = tu_fifo_remaining(&p_cdc->rx_ff); if ( available >= sizeof(p_cdc->epout_buf) ) { - usbd_edpt_xfer(rhport, p_cdc->ep_out, p_cdc->epout_buf, sizeof(p_cdc->epout_buf)); + return usbd_edpt_xfer(rhport, p_cdc->ep_out, p_cdc->epout_buf, sizeof(p_cdc->epout_buf)); }else { // Release endpoint since we don't make any transfer usbd_edpt_release(rhport, p_cdc->ep_out); + + return false; } } diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c index 9d7db11b2..b10a29083 100644 --- a/src/portable/nordic/nrf5x/dcd_nrf5x.c +++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c @@ -63,7 +63,7 @@ typedef struct uint8_t* buffer; uint16_t total_len; volatile uint16_t actual_len; - uint16_t mps; // max packet size + uint16_t mps; // max packet size // nRF will auto accept OUT packet after DMA is done // indicate packet is already ACK @@ -84,8 +84,6 @@ static struct // Number of pending DMA that is started but not handled yet by dcd_int_handler(). // Since nRF can only carry one DMA can run at a time, this value is normally be either 0 or 1. - // However, in critical section with interrupt disabled, the DMA can be finished and added up - // until handled by dcd_int_handler() when exiting critical section. volatile uint8_t dma_pending; }_dcd; @@ -115,67 +113,68 @@ TU_ATTR_ALWAYS_INLINE static inline bool is_in_isr(void) } // helper to start DMA +static void start_dma(volatile uint32_t* reg_startep) +{ + _dcd.dma_pending = true; + + (*reg_startep) = 1; + __ISB(); __DSB(); + + // TASKS_EP0STATUS, TASKS_EP0RCVOUT seem to need EasyDMA to be available + // However these don't trigger any DMA transfer and got ENDED event subsequently + // Therefore dma_pending is corrected right away + if ( (reg_startep == &NRF_USBD->TASKS_EP0STATUS) || (reg_startep == &NRF_USBD->TASKS_EP0RCVOUT) ) + { + _dcd.dma_pending = false; + } +} + +// only 1 EasyDMA can be active at any time // TODO use Cortex M4 LDREX and STREX command (atomic) to have better mutex access to EasyDMA // since current implementation does not 100% guarded against race condition static void edpt_dma_start(volatile uint32_t* reg_startep) { - // Only one dma can be active - if ( _dcd.dma_pending ) + // Called in critical section i.e within USB ISR, or USB/Global interrupt disabled + if ( is_in_isr() || __get_PRIMASK() || !NVIC_GetEnableIRQ(USBD_IRQn) ) { - if (is_in_isr()) + if (_dcd.dma_pending) { - // Called within ISR, use usbd task to defer later + //use usbd task to defer later usbd_defer_func((osal_task_func_t) edpt_dma_start, (void*) (uintptr_t) reg_startep, true); - return; + }else + { + start_dma(reg_startep); } - else + }else + { + // Called in non-critical thread-mode, should be 99% of the time. + // Should be safe to blocking wait until previous DMA transfer complete + uint8_t const rhport = 0; + bool started = false; + while(!started) { - if ( __get_PRIMASK() || !NVIC_GetEnableIRQ(USBD_IRQn) ) - { - // Called in critical section with interrupt disabled. We have to manually check - // for the DMA complete by comparing current pending DMA with number of ENDED Events - uint32_t ended = 0; + // LDREX/STREX may be needed in form of std atomic (required C11) or + // use osal mutex to guard against multiple core MCUs such as nRF53 + dcd_int_disable(rhport); - while ( _dcd.dma_pending > ((uint8_t) ended) ) - { - ended = NRF_USBD->EVENTS_ENDISOIN + NRF_USBD->EVENTS_ENDISOOUT; - - for (uint8_t i=0; iEVENTS_ENDEPIN[i] + NRF_USBD->EVENTS_ENDEPOUT[i]; - } - } - }else + if ( !_dcd.dma_pending ) { - // Called in non-critical thread-mode, should be 99% of the time. - // Should be safe to blocking wait until previous DMA transfer complete - while ( _dcd.dma_pending ) { } + start_dma(reg_startep); + started = true; } - } - } - _dcd.dma_pending++; + dcd_int_enable(rhport); - (*reg_startep) = 1; - __ISB(); __DSB(); + // osal_yield(); + } + } } // DMA is complete static void edpt_dma_end(void) { TU_ASSERT(_dcd.dma_pending, ); - _dcd.dma_pending = 0; -} - -// helper to set TASKS_EP0STATUS / TASKS_EP0RCVOUT since they also need EasyDMA -// However TASKS_EP0STATUS doesn't trigger any DMA transfer and got ENDED event subsequently -// Therefore dma_running state will be corrected right away -void start_ep0_task(volatile uint32_t* reg_task) -{ - edpt_dma_start(reg_task); - - // correct the dma_running++ in dma start - if (_dcd.dma_pending) _dcd.dma_pending--; + _dcd.dma_pending = false; } // helper getting td @@ -194,7 +193,10 @@ static void xact_out_dma(uint8_t epnum) { xact_len = NRF_USBD->SIZE.ISOOUT; // If ZERO bit is set, ignore ISOOUT length - if (xact_len & USBD_SIZE_ISOOUT_ZERO_Msk) xact_len = 0; + if (xact_len & USBD_SIZE_ISOOUT_ZERO_Msk) + { + xact_len = 0; + } else { // Trigger DMA move data from Endpoint -> SRAM @@ -216,8 +218,8 @@ static void xact_out_dma(uint8_t epnum) edpt_dma_start(&NRF_USBD->TASKS_STARTEPOUT[epnum]); } - xfer->buffer += xact_len; - xfer->actual_len += xact_len; +// xfer->buffer += xact_len; +// xfer->actual_len += xact_len; } // Prepare for a CBI transaction IN, call at the start @@ -232,7 +234,7 @@ static void xact_in_dma(uint8_t epnum) NRF_USBD->EPIN[epnum].PTR = (uint32_t) xfer->buffer; NRF_USBD->EPIN[epnum].MAXCNT = xact_len; - xfer->buffer += xact_len; + //xfer->buffer += xact_len; edpt_dma_start(&NRF_USBD->TASKS_STARTEPIN[epnum]); } @@ -242,6 +244,7 @@ static void xact_in_dma(uint8_t epnum) //--------------------------------------------------------------------+ void dcd_init (uint8_t rhport) { + TU_LOG1("dcd init\r\n"); (void) rhport; } @@ -466,7 +469,7 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t if ( control_status ) { // Status Phase also requires EasyDMA has to be available as well !!!! - start_ep0_task(&NRF_USBD->TASKS_EP0STATUS); + edpt_dma_start(&NRF_USBD->TASKS_EP0STATUS); // The nRF doesn't interrupt on status transmit so we queue up a success response. dcd_event_xfer_complete(0, ep_addr, 0, XFER_RESULT_SUCCESS, is_in_isr()); @@ -476,7 +479,7 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t if ( epnum == 0 ) { // Accept next Control Out packet. TASKS_EP0RCVOUT also require EasyDMA - start_ep0_task(&NRF_USBD->TASKS_EP0RCVOUT); + edpt_dma_start(&NRF_USBD->TASKS_EP0RCVOUT); }else { if ( xfer->data_received ) @@ -522,7 +525,6 @@ void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr) // There maybe data in endpoint fifo already, we need to pull it out if ( (dir == TUSB_DIR_OUT) && xfer->data_received ) { - TU_LOG_LOCATION(); xfer->data_received = false; xact_out_dma(epnum); } @@ -717,7 +719,8 @@ void dcd_int_handler(uint8_t rhport) if ( int_status & EDPT_END_ALL_MASK ) { - // DMA complete move data from SRAM -> Endpoint + // DMA complete move data from SRAM <-> Endpoint + // Must before endpoint transfer handling edpt_dma_end(); } @@ -732,7 +735,7 @@ void dcd_int_handler(uint8_t rhport) * - Host -> Endpoint * EPDATA (or EP0DATADONE) interrupted, check EPDATASTATUS.EPOUT[i] * to start DMA. For Bulk/Interrupt, this step can occur automatically (without sw), - * which means data may or may not be ready (data_received flag). + * which means data may or may not be ready (out_received flag). * - Endpoint -> RAM * ENDEPOUT[i] interrupted, transaction complete, sw prepare next transaction * @@ -764,20 +767,16 @@ void dcd_int_handler(uint8_t rhport) xfer_td_t* xfer = get_td(epnum, TUSB_DIR_OUT); uint8_t const xact_len = NRF_USBD->EPOUT[epnum].AMOUNT; + xfer->buffer += xact_len; + xfer->actual_len += xact_len; + // Transfer complete if transaction len < Max Packet Size or total len is transferred if ( (epnum != EP_ISO_NUM) && (xact_len == xfer->mps) && (xfer->actual_len < xfer->total_len) ) { if ( epnum == 0 ) { // Accept next Control Out packet. TASKS_EP0RCVOUT also require EasyDMA - if ( _dcd.dma_pending ) - { - // use usbd task to defer later - usbd_defer_func((osal_task_func_t) start_ep0_task, (void*) (uintptr_t) &NRF_USBD->TASKS_EP0RCVOUT, true); - }else - { - start_ep0_task(&NRF_USBD->TASKS_EP0RCVOUT); - } + edpt_dma_start(&NRF_USBD->TASKS_EP0RCVOUT); }else { // nRF auto accept next Bulk/Interrupt OUT packet @@ -814,8 +813,10 @@ void dcd_int_handler(uint8_t rhport) if ( tu_bit_test(data_status, epnum) || (epnum == 0 && is_control_in) ) { xfer_td_t* xfer = get_td(epnum, TUSB_DIR_IN); + uint8_t const xact_len = NRF_USBD->EPIN[epnum].AMOUNT; // MAXCNT - xfer->actual_len += NRF_USBD->EPIN[epnum].MAXCNT; + xfer->buffer += xact_len; + xfer->actual_len += xact_len; if ( xfer->actual_len < xfer->total_len ) { @@ -842,6 +843,7 @@ void dcd_int_handler(uint8_t rhport) }else { // Data overflow !!! Nah, nRF will auto accept next Bulk/Interrupt OUT packet + // If USBD is already queued this // Mark this endpoint with data received xfer->data_received = true; } -- cgit v1.3.1 From 0fc11746c0e6d9f64750e02d1d46d901c11e0373 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 23 Nov 2021 09:46:45 +0700 Subject: clean up --- src/portable/nordic/nrf5x/dcd_nrf5x.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c index b10a29083..bee9fc0b6 100644 --- a/src/portable/nordic/nrf5x/dcd_nrf5x.c +++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c @@ -217,9 +217,6 @@ static void xact_out_dma(uint8_t epnum) edpt_dma_start(&NRF_USBD->TASKS_STARTEPOUT[epnum]); } - -// xfer->buffer += xact_len; -// xfer->actual_len += xact_len; } // Prepare for a CBI transaction IN, call at the start @@ -234,8 +231,6 @@ static void xact_in_dma(uint8_t epnum) NRF_USBD->EPIN[epnum].PTR = (uint32_t) xfer->buffer; NRF_USBD->EPIN[epnum].MAXCNT = xact_len; - //xfer->buffer += xact_len; - edpt_dma_start(&NRF_USBD->TASKS_STARTEPIN[epnum]); } @@ -813,7 +808,7 @@ void dcd_int_handler(uint8_t rhport) if ( tu_bit_test(data_status, epnum) || (epnum == 0 && is_control_in) ) { xfer_td_t* xfer = get_td(epnum, TUSB_DIR_IN); - uint8_t const xact_len = NRF_USBD->EPIN[epnum].AMOUNT; // MAXCNT + uint8_t const xact_len = NRF_USBD->EPIN[epnum].AMOUNT; xfer->buffer += xact_len; xfer->actual_len += xact_len; @@ -843,7 +838,6 @@ void dcd_int_handler(uint8_t rhport) }else { // Data overflow !!! Nah, nRF will auto accept next Bulk/Interrupt OUT packet - // If USBD is already queued this // Mark this endpoint with data received xfer->data_received = true; } -- cgit v1.3.1 From c9e9f4785f68c9f9e99c4832af8615847c5fae92 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 23 Nov 2021 09:52:11 +0700 Subject: more clean up --- src/portable/nordic/nrf5x/dcd_nrf5x.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c index bee9fc0b6..2bcd56b8a 100644 --- a/src/portable/nordic/nrf5x/dcd_nrf5x.c +++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c @@ -82,9 +82,8 @@ static struct // +1 for ISO endpoints xfer_td_t xfer[EP_CBI_COUNT + 1][2]; - // Number of pending DMA that is started but not handled yet by dcd_int_handler(). - // Since nRF can only carry one DMA can run at a time, this value is normally be either 0 or 1. - volatile uint8_t dma_pending; + // nRF can only carry one DMA at a time, this is used to guard the access to EasyDMA + volatile bool dma_running; }_dcd; /*------------------------------------------------------------------*/ @@ -115,7 +114,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool is_in_isr(void) // helper to start DMA static void start_dma(volatile uint32_t* reg_startep) { - _dcd.dma_pending = true; + _dcd.dma_running = true; (*reg_startep) = 1; __ISB(); __DSB(); @@ -125,7 +124,7 @@ static void start_dma(volatile uint32_t* reg_startep) // Therefore dma_pending is corrected right away if ( (reg_startep == &NRF_USBD->TASKS_EP0STATUS) || (reg_startep == &NRF_USBD->TASKS_EP0RCVOUT) ) { - _dcd.dma_pending = false; + _dcd.dma_running = false; } } @@ -137,7 +136,7 @@ static void edpt_dma_start(volatile uint32_t* reg_startep) // Called in critical section i.e within USB ISR, or USB/Global interrupt disabled if ( is_in_isr() || __get_PRIMASK() || !NVIC_GetEnableIRQ(USBD_IRQn) ) { - if (_dcd.dma_pending) + if (_dcd.dma_running) { //use usbd task to defer later usbd_defer_func((osal_task_func_t) edpt_dma_start, (void*) (uintptr_t) reg_startep, true); @@ -157,7 +156,7 @@ static void edpt_dma_start(volatile uint32_t* reg_startep) // use osal mutex to guard against multiple core MCUs such as nRF53 dcd_int_disable(rhport); - if ( !_dcd.dma_pending ) + if ( !_dcd.dma_running ) { start_dma(reg_startep); started = true; @@ -173,8 +172,8 @@ static void edpt_dma_start(volatile uint32_t* reg_startep) // DMA is complete static void edpt_dma_end(void) { - TU_ASSERT(_dcd.dma_pending, ); - _dcd.dma_pending = false; + TU_ASSERT(_dcd.dma_running, ); + _dcd.dma_running = false; } // helper getting td -- cgit v1.3.1 From 225e7182707510bc57fb433271a41ccd13c55624 Mon Sep 17 00:00:00 2001 From: Mengsk Date: Thu, 25 Nov 2021 17:20:51 +0100 Subject: Update iar project template. --- tools/iar_template.ipcf | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/tools/iar_template.ipcf b/tools/iar_template.ipcf index b8e50a1d2..ba54fe057 100644 --- a/tools/iar_template.ipcf +++ b/tools/iar_template.ipcf @@ -41,7 +41,8 @@ $TUSB_DIR$/src/class/msc/msc_host.c - $TUSB_DIR$/src/class/net/net_device.c + $TUSB_DIR$/src/class/net/ecm_rndis_device.c + $TUSB_DIR$/src/class/net/ncm_device.c $TUSB_DIR$/src/class/usbtmc/usbtmc_device.c @@ -58,6 +59,9 @@ $TUSB_DIR$/src/host/usbh.c $TUSB_DIR$/src/host/usbh_control.c + + $TUSB_DIR$/src/portable/synopsys/dwc2/dcd_dwc2.c + $TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c @@ -67,6 +71,9 @@ $TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c + + $TUSB_DIR$/src/portable/mentor/musb/dcd_musb.c + $TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c @@ -116,21 +123,12 @@ $TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c - - $TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c - $TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c $TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c - - $TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c - - - $TUSB_DIR$/src/portable/template/dcd_template.c - $TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c -- cgit v1.3.1 From 7413b6b02074d806ee2290b53c46ceaa3e76ef42 Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Sat, 27 Nov 2021 10:25:39 +0900 Subject: Add a compile condition for dcd --- src/portable/mentor/musb/dcd_musb.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c index 4b4c2f9b2..0464eea19 100644 --- a/src/portable/mentor/musb/dcd_musb.c +++ b/src/portable/mentor/musb/dcd_musb.c @@ -26,7 +26,8 @@ #include "tusb_option.h" -#if TU_CHECK_MCU(OPT_MCU_MSP432E4, OPT_MCU_TM4C123, OPT_MCU_TM4C129) +#if TUSB_OPT_DEVICE_ENABLED && \ + TU_CHECK_MCU(OPT_MCU_MSP432E4, OPT_MCU_TM4C123, OPT_MCU_TM4C129) #if __GNUC__ > 8 && defined(__ARM_FEATURE_UNALIGNED) /* GCC warns that an address may be unaligned, even though -- cgit v1.3.1 From b50cf856b323c4948883a9834d289fe5dd7f67ff Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Sun, 28 Nov 2021 16:49:27 +0900 Subject: Add hcd_musb.c --- src/portable/mentor/musb/hcd_musb.c | 858 ++++++++++++++++++++++++++++++++++++ 1 file changed, 858 insertions(+) create mode 100644 src/portable/mentor/musb/hcd_musb.c diff --git a/src/portable/mentor/musb/hcd_musb.c b/src/portable/mentor/musb/hcd_musb.c new file mode 100644 index 000000000..b4931a793 --- /dev/null +++ b/src/portable/mentor/musb/hcd_musb.c @@ -0,0 +1,858 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Koji KITAYAMA + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "tusb_option.h" + +#if TUSB_OPT_HOST_ENABLED && \ + TU_CHECK_MCU(OPT_MCU_MSP432E4, OPT_MCU_TM4C123, OPT_MCU_TM4C129) + +#if __GNUC__ > 8 && defined(__ARM_FEATURE_UNALIGNED) +/* GCC warns that an address may be unaligned, even though + * the target CPU has the capability for unaligned memory access. */ +_Pragma("GCC diagnostic ignored \"-Waddress-of-packed-member\""); +#endif + +#include "host/hcd.h" + +#if TU_CHECK_MCU(OPT_MCU_MSP432E4) + #include "musb_msp432e.h" + +#elif TU_CHECK_MCU(OPT_MCU_TM4C123, OPT_MCU_TM4C129) + #include "musb_tm4c.h" + + // HACK generalize later + #include "musb_type.h" + #define FIFO0_WORD FIFO0 + +#else + #error "Unsupported MCUs" +#endif + +#ifndef HCD_ATTR_ENDPOINT_MAX +# define HCD_ATTR_ENDPOINT_MAX 8 +#endif + +/*------------------------------------------------------------------ + * MACRO TYPEDEF CONSTANT ENUM DECLARATION + *------------------------------------------------------------------*/ +#define REQUEST_TYPE_INVALID (0xFFu) + +typedef struct { + uint_fast16_t beg; /* offset of including first element */ + uint_fast16_t end; /* offset of excluding the last element */ +} free_block_t; + +typedef struct TU_ATTR_PACKED { + uint8_t TXFUNCADDR; + uint8_t RESERVED0; + uint8_t TXHUBADDR; + uint8_t TXHUBPORT; + uint8_t RXFUNCADDR; + uint8_t RESERVED1; + uint8_t RXHUBADDR; + uint8_t RXHUBPORT; +} hw_addr_t; + +typedef struct TU_ATTR_PACKED { + uint16_t TXMAXP; + uint8_t TXCSRL; + uint8_t TXCSRH; + uint16_t RXMAXP; + uint8_t RXCSRL; + uint8_t RXCSRH; + uint16_t RXCOUNT; + uint8_t TXTYPE; + uint8_t TXINTERVAL; + uint8_t RXTYPE; + uint8_t RXINTERVAL; + uint16_t RESERVED; +} hw_endpoint_t; + +typedef union { + uint8_t u8; + uint16_t u16; + uint32_t u32; +} hw_fifo_t; + +typedef struct TU_ATTR_PACKED +{ + void *buf; /* the start address of a transfer data buffer */ + uint16_t length; /* the number of bytes in the buffer */ + uint16_t remaining; /* the number of bytes remaining in the buffer */ +} pipe_state_t; + +typedef struct TU_ATTR_PACKED +{ + uint8_t dev; + uint8_t ep; +} pipe_addr_t; + +typedef struct +{ + bool need_reset; /* The device has not been reset after connection. */ + uint8_t bmRequestType; + uint8_t ctl_mps[7]; /* EP0 max packet size for each device */ + pipe_state_t pipe0; + pipe_state_t pipe[7][2]; /* pipe[pipe number - 1][direction 0:RX 1:TX] */ + pipe_addr_t addr[7][2]; /* addr[pipe number - 1][direction 0:RX 1:TX] */ +} hcd_data_t; + +/*------------------------------------------------------------------ + * INTERNAL OBJECT & FUNCTION DECLARATION + *------------------------------------------------------------------*/ +static hcd_data_t _hcd; + +static inline free_block_t *find_containing_block(free_block_t *beg, free_block_t *end, uint_fast16_t addr) +{ + free_block_t *cur = beg; + for (; cur < end && ((addr < cur->beg) || (cur->end <= addr)); ++cur) ; + return cur; +} + +static inline int update_free_block_list(free_block_t *blks, unsigned num, uint_fast16_t addr, uint_fast16_t size) +{ + free_block_t *p = find_containing_block(blks, blks + num, addr); + TU_ASSERT(p != blks + num, -2); + if (p->beg == addr) { + /* Shrink block */ + p->beg = addr + size; + if (p->beg != p->end) return 0; + /* remove block */ + free_block_t *end = blks + num; + while (p + 1 < end) { + *p = *(p + 1); + ++p; + } + return -1; + } else { + /* Split into 2 blocks */ + free_block_t tmp = { + .beg = addr + size, + .end = p->end + }; + p->end = addr; + if (p->beg == p->end) { + if (tmp.beg != tmp.end) { + *p = tmp; + return 0; + } + /* remove block */ + free_block_t *end = blks + num; + while (p + 1 < end) { + *p = *(p + 1); + ++p; + } + return -1; + } + if (tmp.beg == tmp.end) return 0; + blks[num] = tmp; + return 1; + } +} + +static inline unsigned free_block_size(free_block_t const *blk) +{ + return blk->end - blk->beg; +} + +static unsigned find_free_memory(uint_fast16_t size_in_log2_minus3) +{ + free_block_t free_blocks[2 * (HCD_ATTR_ENDPOINT_MAX - 1)]; + unsigned num_blocks = 1; + + /* Initialize free memory block list */ + free_blocks[0].beg = 64 / 8; + free_blocks[0].end = (4 << 10) / 8; /* 4KiB / 8 bytes */ + for (int i = 1; i < HCD_ATTR_ENDPOINT_MAX; ++i) { + uint_fast16_t addr; + int num; + USB0->EPIDX = i; + addr = USB0->TXFIFOADD; + if (addr) { + unsigned sz = USB0->TXFIFOSZ; + unsigned sft = (sz & USB_TXFIFOSZ_SIZE_M) + ((sz & USB_TXFIFOSZ_DPB) ? 1: 0); + num = update_free_block_list(free_blocks, num_blocks, addr, 1 << sft); + TU_ASSERT(-2 < num, 0); + num_blocks += num; + } + addr = USB0->RXFIFOADD; + if (addr) { + unsigned sz = USB0->RXFIFOSZ; + unsigned sft = (sz & USB_RXFIFOSZ_SIZE_M) + ((sz & USB_RXFIFOSZ_DPB) ? 1: 0); + num = update_free_block_list(free_blocks, num_blocks, addr, 1 << sft); + TU_ASSERT(-2 < num, 0); + num_blocks += num; + } + } + + /* Find the best fit memory block */ + uint_fast16_t size_in_8byte_unit = 1 << size_in_log2_minus3; + free_block_t const *min = NULL; + uint_fast16_t min_sz = 0xFFFFu; + free_block_t const *end = &free_blocks[num_blocks]; + for (free_block_t const *cur = &free_blocks[0]; cur < end; ++cur) { + uint_fast16_t sz = free_block_size(cur); + if (sz < size_in_8byte_unit) continue; + if (size_in_8byte_unit == sz) return cur->beg; + if (sz < min_sz) min = cur; + } + TU_ASSERT(min, 0); + return min->beg; +} + +static inline volatile hw_endpoint_t* edpt_regs(unsigned epnum_minus1) +{ + volatile hw_endpoint_t *regs = (volatile hw_endpoint_t*)((uintptr_t)&USB0->TXMAXP1); + return regs + epnum_minus1; +} + +static unsigned find_pipe(uint_fast8_t dev_addr, uint_fast8_t ep_addr) +{ + unsigned const dir_tx = tu_edpt_dir(ep_addr) ? 0: 1; + pipe_addr_t const *p = &_hcd.addr[0][dir_tx]; + for (unsigned i = 0; i < sizeof(_hcd.addr)/sizeof(_hcd.addr[0]); ++i, p += 2) { + if ((dev_addr == p->dev) && (ep_addr == p->ep)) + return i + 1; + } + return 0; +} + +static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) +{ + volatile hw_fifo_t *reg = (volatile hw_fifo_t*)fifo; + uintptr_t addr = (uintptr_t)buf; + while (len >= 4) { + reg->u32 = *(uint32_t const *)addr; + addr += 4; + len -= 4; + } + if (len >= 2) { + reg->u16 = *(uint16_t const *)addr; + addr += 2; + len -= 2; + } + if (len) { + reg->u8 = *(uint8_t const *)addr; + } +} + +static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len) +{ + volatile hw_fifo_t *reg = (volatile hw_fifo_t*)fifo; + uintptr_t addr = (uintptr_t)buf; + while (len >= 4) { + *(uint32_t *)addr = reg->u32; + addr += 4; + len -= 4; + } + if (len >= 2) { + *(uint32_t *)addr = reg->u16; + addr += 2; + len -= 2; + } + if (len) { + *(uint32_t *)addr = reg->u8; + } +} + +static bool edpt0_xfer_out(void) +{ + pipe_state_t *pipe = &_hcd.pipe0; + unsigned const rem = pipe->remaining; + if (!rem) { + pipe->buf = NULL; + return true; + } + unsigned const dev_addr = USB0->TXFUNCADDR0; + unsigned const mps = _hcd.ctl_mps[dev_addr]; + unsigned const len = TU_MIN(rem, mps); + void *buf = pipe->buf; + if (len) { + pipe_write_packet(buf, &USB0->FIFO0_WORD, len); + pipe->buf = (uint8_t*)buf + len; + } + pipe->remaining = rem - len; + USB0->CSRL0 = USB_CSRL0_TXRDY; + return false; +} + +static bool edpt0_xfer_in(void) +{ + pipe_state_t *pipe = &_hcd.pipe0; + unsigned const rem = pipe->remaining; + unsigned const dev_addr = USB0->TXFUNCADDR0; + unsigned const mps = _hcd.ctl_mps[dev_addr]; + unsigned const vld = USB0->COUNT0; + unsigned const len = TU_MIN(TU_MIN(rem, mps), vld); + void *buf = pipe->buf; + if (len) { + pipe_read_packet(buf, &USB0->FIFO0_WORD, len); + pipe->buf = (uint8_t*)buf + len; + } + pipe->remaining = rem - len; + if ((len < mps) || (rem == len)) { + pipe->buf = NULL; + return true; + } + USB0->CSRL0 = USB_CSRL0_REQPKT; + return false; +} + +static bool edpt0_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *buffer, uint16_t buflen) +{ + (void)rhport; + + const unsigned req = _hcd.bmRequestType; + TU_ASSERT(req != REQUEST_TYPE_INVALID); + TU_ASSERT(dev_addr < sizeof(_hcd.ctl_mps)); + + USB0->TXFUNCADDR0 = dev_addr; + const unsigned dir_in = tu_edpt_dir(ep_addr); + if (tu_edpt_dir(req) == dir_in) { /* DATA stage */ + TU_ASSERT(buffer); + _hcd.pipe0.buf = buffer; + _hcd.pipe0.length = buflen; + _hcd.pipe0.remaining = buflen; + if (dir_in) + USB0->CSRL0 = USB_CSRL0_REQPKT; + else + edpt0_xfer_out(); + } else { /* STATUS stage */ + _hcd.pipe0.buf = NULL; + _hcd.pipe0.length = 0; + _hcd.pipe0.remaining = 0; + USB0->CSRL0 = USB_CSRL0_STATUS | (dir_in ? USB_CSRL0_REQPKT: USB_CSRL0_TXRDY); + } + return true; +} + +static bool pipe_xfer_out(uint_fast8_t pipenum) +{ + pipe_state_t *pipe = &_hcd.pipe[pipenum - 1][1]; + unsigned const rem = pipe->remaining; + if (!rem) { + pipe->buf = NULL; + return true; + } + hw_endpoint_t volatile *regs = edpt_regs(pipenum - 1); + unsigned const mps = regs->TXMAXP; + unsigned const len = TU_MIN(rem, mps); + void *buf = pipe->buf; + if (len) { + pipe_write_packet(buf, &USB0->FIFO0_WORD + pipenum, len); + pipe->buf = (uint8_t*)buf + len; + } + pipe->remaining = rem - len; + regs->TXCSRL = USB_TXCSRL1_TXRDY; + return false; +} + +static bool pipe_xfer_in(uint_fast8_t pipenum) +{ + pipe_state_t *pipe = &_hcd.pipe[pipenum - 1][0]; + volatile hw_endpoint_t *regs = edpt_regs(pipenum - 1); + + TU_ASSERT(regs->RXCSRL & USB_RXCSRL1_RXRDY); + + const unsigned mps = regs->RXMAXP; + const unsigned rem = pipe->remaining; + const unsigned vld = regs->RXCOUNT; + const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); + void *buf = pipe->buf; + if (len) { + pipe_read_packet(buf, &USB0->FIFO0_WORD + pipenum, len); + pipe->buf = buf + len; + pipe->remaining = rem - len; + } + if ((len < mps) || (rem == len)) { + pipe->buf = NULL; + return NULL != buf; + } + regs->RXCSRL = USB_RXCSRL1_REQPKT; + return false; +} + +static bool edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *buffer, uint16_t buflen) +{ + (void)rhport; + unsigned const pipenum = find_pipe(dev_addr, ep_addr); + unsigned const dir_tx = tu_edpt_dir(ep_addr) ? 0: 1; + pipe_state_t *pipe = &_hcd.pipe[pipenum - 1][dir_tx]; + pipe->buf = buffer; + pipe->length = buflen; + pipe->remaining = buflen; + if (dir_tx) { + pipe_xfer_out(pipenum); + } else { + volatile hw_endpoint_t *regs = edpt_regs(pipenum - 1); + regs->RXCSRL = USB_RXCSRL1_REQPKT; + } + return true; +} + +static void process_ep0(uint8_t rhport) +{ + (void)rhport; + + uint_fast8_t csrl = USB0->CSRL0; + // TU_LOG1(" EP0 CSRL = %x\n", csrl); + + unsigned const dev_addr = USB0->TXFUNCADDR0; + unsigned const req = _hcd.bmRequestType; + if (csrl & (USB_CSRL0_ERROR | USB_CSRL0_NAKTO | USB_CSRL0_STALLED)) { + /* No response / NAK timed out / Stall received */ + if (csrl & (USB_CSRL0_RXRDY | USB_CSRL0_TXRDY)) + USB0->CSRH0 = USB_CSRH0_FLUSH; + USB0->CSRL0 = 0; + _hcd.bmRequestType = REQUEST_TYPE_INVALID; + uint8_t result = (csrl & USB_CSRL0_STALLED) ? XFER_RESULT_STALLED: XFER_RESULT_FAILED; + if (REQUEST_TYPE_INVALID == req) { /* SETUP */ + uint8_t const ep_addr = tu_edpt_addr(0, TUSB_DIR_OUT); + hcd_event_xfer_complete(dev_addr, ep_addr, + _hcd.pipe0.length - _hcd.pipe0.remaining, + result, true); + } else if (csrl & USB_CSRL0_STATUS) { /* STATUS */ + uint8_t const ep_addr = tu_edpt_dir(req) ? + tu_edpt_addr(0, TUSB_DIR_OUT): tu_edpt_addr(0, TUSB_DIR_IN); + hcd_event_xfer_complete(dev_addr, ep_addr, + _hcd.pipe0.length - _hcd.pipe0.remaining, + result, true); + } else { /* DATA */ + uint8_t const ep_addr = tu_edpt_dir(req) ? + tu_edpt_addr(0, TUSB_DIR_IN): tu_edpt_addr(0, TUSB_DIR_OUT); + hcd_event_xfer_complete(dev_addr, ep_addr, + _hcd.pipe0.length - _hcd.pipe0.remaining, + result, true); + } + return; + } + if (csrl & USB_CSRL0_STATUS) { + /* STATUS IN */ + TU_ASSERT(USB_CSRL0_RXRDY == (csrl & USB_CSRL0_RXRDY),); + TU_ASSERT(0 == USB0->COUNT0,); + USB0->CSRL0 = 0; + _hcd.bmRequestType = REQUEST_TYPE_INVALID; + hcd_event_xfer_complete(dev_addr, tu_edpt_addr(0, TUSB_DIR_IN), + 0, XFER_RESULT_SUCCESS, true); + return; + } + if (csrl & USB_CSRL0_RXRDY) { + /* DATA IN */ + TU_ASSERT(REQUEST_TYPE_INVALID != req,); + TU_ASSERT(_hcd.pipe0.buf,); + if (edpt0_xfer_in()) { + hcd_event_xfer_complete(dev_addr, tu_edpt_addr(0, TUSB_DIR_IN), + _hcd.pipe0.length - _hcd.pipe0.remaining, + XFER_RESULT_SUCCESS, true); + } + return; + } + + /* When CSRL0 is zero, it means that completion of sending a any length packet. */ + if (!_hcd.pipe0.buf) { + /* STATUS OUT */ + TU_ASSERT(REQUEST_TYPE_INVALID != req,); + _hcd.bmRequestType = REQUEST_TYPE_INVALID; + /* EP address is the reverse direction of DATA stage */ + uint8_t const ep_addr = tu_edpt_dir(req) ? + tu_edpt_addr(0, TUSB_DIR_OUT): tu_edpt_addr(0, TUSB_DIR_IN); + hcd_event_xfer_complete(dev_addr, ep_addr, 0, XFER_RESULT_SUCCESS, true); + return; + } + if (REQUEST_TYPE_INVALID == req) { + /* SETUP */ + _hcd.bmRequestType = *(uint8_t*)_hcd.pipe0.buf; + _hcd.pipe0.buf = NULL; + hcd_event_xfer_complete(dev_addr, tu_edpt_addr(0, TUSB_DIR_OUT), + 8, XFER_RESULT_SUCCESS, true); + return; + } + + /* DATA OUT */ + if (edpt0_xfer_out()) { + hcd_event_xfer_complete(dev_addr, tu_edpt_addr(0, TUSB_DIR_OUT), + _hcd.pipe0.length - _hcd.pipe0.remaining, + XFER_RESULT_SUCCESS, true); + } +} + +static void process_pipe_tx(uint8_t rhport, uint_fast8_t pipenum) +{ + (void)rhport; + bool completed; + uint8_t result; + + volatile hw_endpoint_t *regs = edpt_regs(pipenum - 1); + unsigned const csrl = regs->TXCSRL; + // TU_LOG1(" TXCSRL%d = %x\n", pipenum, csrl); + if (csrl & (USB_TXCSRL1_STALLED | USB_TXCSRL1_ERROR)) { + if (csrl & USB_TXCSRL1_TXRDY) + regs->TXCSRL = (csrl & ~(USB_TXCSRL1_STALLED | USB_TXCSRL1_ERROR)) | USB_TXCSRL1_FLUSH; + else + regs->TXCSRL = csrl & ~(USB_TXCSRL1_STALLED | USB_TXCSRL1_ERROR); + completed = true; + result = (csrl & USB_TXCSRL1_STALLED) ? XFER_RESULT_STALLED: XFER_RESULT_FAILED; + } else { + completed = pipe_xfer_out(pipenum); + result = XFER_RESULT_SUCCESS; + } + if (completed) { + pipe_addr_t *addr = &_hcd.addr[pipenum - 1][1]; + pipe_state_t *pipe = &_hcd.pipe[pipenum - 1][1]; + hcd_event_xfer_complete(addr->dev, addr->ep, + pipe->length - pipe->remaining, + result, true); + } +} + +static void process_pipe_rx(uint8_t rhport, uint_fast8_t pipenum) +{ + (void)rhport; + bool completed; + uint8_t result; + + volatile hw_endpoint_t *regs = edpt_regs(pipenum - 1); + unsigned const csrl = regs->RXCSRL; + // TU_LOG1(" RXCSRL%d = %x\n", pipenum, csrl); + if (csrl & (USB_RXCSRL1_STALLED | USB_RXCSRL1_ERROR)) { + if (csrl & USB_RXCSRL1_RXRDY) + regs->RXCSRL = (csrl & ~(USB_RXCSRL1_STALLED | USB_RXCSRL1_ERROR)) | USB_RXCSRL1_FLUSH; + else + regs->RXCSRL = csrl & ~(USB_RXCSRL1_STALLED | USB_RXCSRL1_ERROR); + completed = true; + result = (csrl & USB_RXCSRL1_STALLED) ? XFER_RESULT_STALLED: XFER_RESULT_FAILED; + } else { + completed = pipe_xfer_in(pipenum); + result = XFER_RESULT_SUCCESS; + } + if (completed) { + pipe_addr_t *addr = &_hcd.addr[pipenum - 1][0]; + pipe_state_t *pipe = &_hcd.pipe[pipenum - 1][0]; + hcd_event_xfer_complete(addr->dev, addr->ep, + pipe->length - pipe->remaining, + result, true); + } +} + +/*------------------------------------------------------------------ + * Host API + *------------------------------------------------------------------*/ + +bool hcd_init(uint8_t rhport) +{ + (void)rhport; + + NVIC_ClearPendingIRQ(USB0_IRQn); + _hcd.bmRequestType = REQUEST_TYPE_INVALID; + USB0->DEVCTL |= USB_DEVCTL_SESSION; + USB0->IE = USB_IE_DISCON | USB_IE_CONN | USB_IE_BABBLE | USB_IE_RESUME; + return true; +} + +void hcd_int_enable(uint8_t rhport) +{ + (void)rhport; + NVIC_EnableIRQ(USB0_IRQn); +} + +void hcd_int_disable(uint8_t rhport) +{ + (void)rhport; + NVIC_DisableIRQ(USB0_IRQn); +} + +uint32_t hcd_frame_number(uint8_t rhport) +{ + (void)rhport; + /* The device must be reset at least once after connection + * in order to start the frame counter. */ + if (_hcd.need_reset) hcd_port_reset(rhport); + return USB0->FRAME; +} + +//--------------------------------------------------------------------+ +// Port API +//--------------------------------------------------------------------+ + +bool hcd_port_connect_status(uint8_t rhport) +{ + (void)rhport; + unsigned devctl = USB0->DEVCTL; + if (!(devctl & USB_DEVCTL_HOST)) return false; + if (devctl & (USB_DEVCTL_LSDEV | USB_DEVCTL_FSDEV)) return true; + return false; +} + +void hcd_port_reset(uint8_t rhport) +{ + (void)rhport; + USB0->POWER |= USB_POWER_HSENAB | USB_POWER_RESET; + unsigned cnt = SystemCoreClock / 1000 * 20; + while (cnt--) __NOP(); + USB0->POWER &= ~USB_POWER_RESET; + _hcd.need_reset = false; +} + +tusb_speed_t hcd_port_speed_get(uint8_t rhport) +{ + (void)rhport; + unsigned devctl = USB0->DEVCTL; + if (devctl & USB_DEVCTL_LSDEV) return TUSB_SPEED_LOW; + if (!(devctl & USB_DEVCTL_FSDEV)) return TUSB_SPEED_INVALID; + if (USB0->POWER & USB_POWER_HSMODE) return TUSB_SPEED_HIGH; + return TUSB_SPEED_FULL; +} + +void hcd_device_close(uint8_t rhport, uint8_t dev_addr) +{ + (void)rhport; + if (sizeof(_hcd.ctl_mps) <= dev_addr) return; + + unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn); + NVIC_DisableIRQ(USB0_IRQn); + _hcd.ctl_mps[dev_addr] = 0; + if (!dev_addr) return; + + pipe_addr_t *p = &_hcd.addr[0][0]; + for (unsigned i = 0; i < sizeof(_hcd.addr)/sizeof(_hcd.addr[0]); ++i) { + for (unsigned j = 0; j < 2; ++j, ++p) { + if (dev_addr != p->dev) continue; + hw_addr_t volatile *fadr = (hw_addr_t volatile*)&USB0->TXFUNCADDR0 + i + 1; + hw_endpoint_t volatile *regs = edpt_regs(i); + USB0->EPIDX = i + 1; + if (j) { + USB0->TXIE &= ~TU_BIT(i + 1); + if (regs->TXCSRL & USB_TXCSRL1_TXRDY) + regs->TXCSRL = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH; + else + regs->TXCSRL = USB_TXCSRL1_CLRDT; + regs->TXMAXP = 0; + regs->TXTYPE = 0; + regs->TXINTERVAL = 0; + fadr->TXFUNCADDR = 0; + fadr->TXHUBADDR = 0; + fadr->TXHUBPORT = 0; + USB0->TXFIFOADD = 0; + USB0->TXFIFOSZ = 0; + } else { + USB0->RXIE &= ~TU_BIT(i + 1); + if (regs->RXCSRL & USB_RXCSRL1_RXRDY) + regs->RXCSRL = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH; + else + regs->RXCSRL = USB_RXCSRL1_CLRDT; + regs->RXMAXP = 0; + regs->RXTYPE = 0; + regs->RXINTERVAL = 0; + fadr->RXFUNCADDR = 0; + fadr->RXHUBADDR = 0; + fadr->RXHUBPORT = 0; + USB0->RXFIFOADD = 0; + USB0->RXFIFOSZ = 0; + } + p->dev = 0; + p->ep = 0; + pipe_state_t *pipe = &_hcd.pipe[i][j]; + pipe->buf = NULL; + pipe->length = 0; + pipe->remaining = 0; + } + } + if (ie) NVIC_EnableIRQ(USB0_IRQn); +} + +//--------------------------------------------------------------------+ +// Endpoints API +//--------------------------------------------------------------------+ + +bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) +{ + (void)rhport; + pipe_write_packet((void*)(uintptr_t)setup_packet, &USB0->FIFO0_WORD, 8); + _hcd.pipe0.buf = (void*)(uintptr_t)setup_packet; + _hcd.pipe0.length = 8; + _hcd.pipe0.remaining = 0; + _hcd.bmRequestType = REQUEST_TYPE_INVALID; + USB0->TXFUNCADDR0 = dev_addr; + USB0->CSRL0 = USB_CSRL0_TXRDY | USB_CSRL0_SETUP; + return true; +} + +bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) +{ + if (sizeof(_hcd.ctl_mps) <= dev_addr) return false; + unsigned const ep_addr = ep_desc->bEndpointAddress; + unsigned const epn = tu_edpt_number(ep_addr); + if (0 == epn) { + _hcd.ctl_mps[dev_addr] = ep_desc->wMaxPacketSize; + return true; + } + + unsigned const dir_tx = tu_edpt_dir(ep_addr) ? 0: 1; + /* Find a free pipe */ + unsigned pipenum = 0; + pipe_addr_t *p = &_hcd.addr[0][dir_tx]; + for (unsigned i = 0; i < sizeof(_hcd.addr)/sizeof(_hcd.addr[0]); ++i, p += 2) { + if (0 == p->ep) { + p->dev = dev_addr; + p->ep = ep_addr; + pipenum = i + 1; + break; + } + } + if (!pipenum) return false; + + unsigned const xfer = ep_desc->bmAttributes.xfer; + unsigned const mps = tu_edpt_packet_size(ep_desc); + + pipe_state_t *pipe = &_hcd.pipe[pipenum - 1][dir_tx]; + pipe->buf = NULL; + pipe->length = 0; + pipe->remaining = 0; + + uint8_t pipe_type = 0; + switch (hcd_port_speed_get(rhport)) { + default: return false; + case TUSB_SPEED_LOW: pipe_type |= USB_TXTYPE1_SPEED_LOW; break; + case TUSB_SPEED_FULL: pipe_type |= USB_TXTYPE1_SPEED_FULL; break; + case TUSB_SPEED_HIGH: pipe_type |= USB_TXTYPE1_SPEED_HIGH; break; + } + switch (xfer) { + default: return false; + case TUSB_XFER_BULK: pipe_type |= USB_TXTYPE1_PROTO_BULK; break; + case TUSB_XFER_INTERRUPT: pipe_type |= USB_TXTYPE1_PROTO_INT; break; + case TUSB_XFER_ISOCHRONOUS: pipe_type |= USB_TXTYPE1_PROTO_ISOC; break; + } + + hw_addr_t volatile *fadr = (hw_addr_t volatile*)&USB0->TXFUNCADDR0 + pipenum; + hw_endpoint_t volatile *regs = edpt_regs(pipenum - 1); + if (dir_tx) { + fadr->TXFUNCADDR = dev_addr; + regs->TXMAXP = mps; + regs->TXTYPE = pipe_type | epn; + regs->TXINTERVAL = ep_desc->bInterval; + if (regs->TXCSRL & USB_TXCSRL1_TXRDY) + regs->TXCSRL = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH; + else + regs->TXCSRL = USB_TXCSRL1_CLRDT; + USB0->TXIE |= TU_BIT(pipenum); + } else { + fadr->RXFUNCADDR = dev_addr; + regs->RXMAXP = mps; + regs->RXTYPE = pipe_type | epn; + regs->RXINTERVAL = ep_desc->bInterval; + if (regs->RXCSRL & USB_RXCSRL1_RXRDY) + regs->RXCSRL = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH; + else + regs->RXCSRL = USB_RXCSRL1_CLRDT; + USB0->RXIE |= TU_BIT(pipenum); + } + + /* Setup FIFO */ + int size_in_log2_minus3 = 28 - TU_MIN(28, __CLZ((uint32_t)mps)); + if ((8u << size_in_log2_minus3) < mps) ++size_in_log2_minus3; + unsigned addr = find_free_memory(size_in_log2_minus3); + TU_ASSERT(addr); + + USB0->EPIDX = pipenum; + if (dir_tx) { + USB0->TXFIFOADD = addr; + USB0->TXFIFOSZ = size_in_log2_minus3; + } else { + USB0->RXFIFOADD = addr; + USB0->RXFIFOSZ = size_in_log2_minus3; + } + return true; +} + +bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *buffer, uint16_t buflen) +{ + (void)rhport; + bool ret = false; + if (0 == tu_edpt_number(ep_addr)) { + ret = edpt0_xfer(rhport, dev_addr, ep_addr, buffer, buflen); + } else { + ret = edpt_xfer(rhport, dev_addr, ep_addr, buffer, buflen); + } + return ret; +} + +// clear stall, data toggle is also reset to DATA0 +bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr) +{ + unsigned const pipenum = find_pipe(dev_addr, ep_addr); + if (!pipenum) return false; + hw_endpoint_t volatile *regs = edpt_regs(pipenum - 1); + unsigned const dir_tx = tu_edpt_dir(ep_addr) ? 0: 1; + if (dir_tx) + regs->TXCSRL = USB_TXCSRL1_CLRDT; + else + regs->RXCSRL = USB_RXCSRL1_CLRDT; + return true; +} + +/*------------------------------------------------------------------- + * ISR + *-------------------------------------------------------------------*/ +void hcd_int_handler(uint8_t rhport) +{ + uint_fast8_t is, txis, rxis; + + is = USB0->IS; /* read and clear interrupt status */ + txis = USB0->TXIS; /* read and clear interrupt status */ + rxis = USB0->RXIS; /* read and clear interrupt status */ + // TU_LOG1("D%2x T%2x R%2x\n", is, txis, rxis); + + is &= USB0->IE; /* Clear disabled interrupts */ + if (is & USB_IS_RESUME) { + } + if (is & USB_IS_CONN) { + _hcd.need_reset = true; + hcd_event_device_attach(rhport, true); + } + if (is & USB_IS_DISCON) { + hcd_event_device_remove(rhport, true); + } + if (is & USB_IS_BABBLE) { + } + txis &= USB0->TXIE; /* Clear disabled interrupts */ + if (txis & USB_TXIE_EP0) { + process_ep0(rhport); + txis &= ~TU_BIT(0); + } + while (txis) { + unsigned const num = __builtin_ctz(txis); + process_pipe_tx(rhport, num); + txis &= ~TU_BIT(num); + } + rxis &= USB0->RXIE; /* Clear disabled interrupts */ + while (rxis) { + unsigned const num = __builtin_ctz(rxis); + process_pipe_rx(rhport, num); + rxis &= ~TU_BIT(num); + } +} + +#endif -- cgit v1.3.1 From b3dddc77eb4527372640e1712c9e248b60dd8869 Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Mon, 29 Nov 2021 00:40:23 +0900 Subject: Add initialization sequence as a HOST --- hw/bsp/msp432e4/family.c | 49 +++++++++++++++++++++++++++++++++++++----------- 1 file changed, 38 insertions(+), 11 deletions(-) diff --git a/hw/bsp/msp432e4/family.c b/hw/bsp/msp432e4/family.c index 7114da693..262dc1d30 100644 --- a/hw/bsp/msp432e4/family.c +++ b/hw/bsp/msp432e4/family.c @@ -33,7 +33,12 @@ //--------------------------------------------------------------------+ void USB0_IRQHandler(void) { +#if TUSB_OPT_HOST_ENABLED + tuh_int_handler(0); +#endif +#if TUSB_OPT_DEVICE_ENABLED tud_int_handler(0); +#endif } //--------------------------------------------------------------------+ @@ -42,6 +47,7 @@ void USB0_IRQHandler(void) void board_init(void) { + unsigned bits; /* Turn off power domains that unused peripherals belong to */ SYSCTL->PCCAN = 0u; #ifdef __MCU_HAS_LCD0__ @@ -80,20 +86,23 @@ void board_init(void) #endif /* USR_LED1 ON1 */ - SYSCTL->RCGCGPIO |= TU_BIT(CLK_LED); - while (!(SYSCTL->PRGPIO & TU_BIT(CLK_LED))) ; + bits = TU_BIT(CLK_LED); + SYSCTL->RCGCGPIO |= bits; + while (bits != (SYSCTL->RCGCGPIO & bits)) ; GPIO_LED->DIR = TU_BIT(GPIO_LED_PIN); GPIO_LED->DEN = TU_BIT(GPIO_LED_PIN); /* USR_SW1 PJ0 */ - SYSCTL->RCGCGPIO |= TU_BIT(CLK_BUTTON); - while (!(SYSCTL->PRGPIO & TU_BIT(CLK_BUTTON))) ; + bits = TU_BIT(CLK_BUTTON); + SYSCTL->RCGCGPIO |= bits; + while (bits != (SYSCTL->RCGCGPIO & bits)) ; GPIO_BUTTON->PUR = TU_BIT(GPIO_BUTTON_PIN); GPIO_BUTTON->DEN = TU_BIT(GPIO_BUTTON_PIN); /* UART PA0,1 */ - SYSCTL->RCGCGPIO |= 1u << 0; - while (!(SYSCTL->PRGPIO & (1u << 0))) ; + bits = TU_BIT(0); + SYSCTL->RCGCGPIO |= bits; + while (bits != (SYSCTL->RCGCGPIO & bits)) ; GPIOA->AFSEL = 3u; GPIOA->PCTL = 0x11u; GPIOA->DEN = 3u; @@ -107,11 +116,22 @@ void board_init(void) UART0->CC = UART_CC_CS_PIOSC; /* Set the baud clock to PIOSC */ UART0->CTL = UART_CTL_RXE | UART_CTL_TXE | UART_CTL_UARTEN; - /* USB PB1(VBUS) PL6,7(DP,DM) */ - SYSCTL->RCGCGPIO |= (1u << 1) | (1u << 10); - while (((1u << 1) | (1u << 10)) != (SYSCTL->PRGPIO & ((1u << 1) | (1u << 10)))) ; - GPIOB->AMSEL = 1u << 1; - GPIOL->AMSEL = (1u << 6) | (1u << 7); + /* USB PB0(ID) PB1(VBUS) PL6,7(DP,DM) */ + bits = TU_BIT(1) | TU_BIT(10); + SYSCTL->RCGCGPIO |= bits; + while (bits != (SYSCTL->RCGCGPIO & bits)) ; + GPIOB->AMSEL = TU_BIT(0) | TU_BIT(1); + GPIOL->AMSEL = TU_BIT(6) | TU_BIT(7); + +#if TUSB_OPT_HOST_ENABLED + /* USB PD6(EPEN) */ + bits = TU_BIT(3); + SYSCTL->RCGCGPIO |= bits; + while (bits != (SYSCTL->RCGCGPIO & bits)) ; + GPIOD->AFSEL = TU_BIT(6); + GPIOD->PCTL = 0x05000000u; + GPIOD->DEN = TU_BIT(6); +#endif SYSCTL->RCGCUSB = 1u; /* Open the clock gate for SYSCLK */ while (!(SYSCTL->PRUSB & (1u << 0))) ; @@ -124,6 +144,13 @@ void board_init(void) USB0->CC = USB_CC_CLKEN | (3u << USB_CC_CLKDIV_S); /* 60MHz = 240MHz / 4 */ __DMB(); /* Wait for completion of opening of the clock gate */ +#if TUSB_OPT_HOST_ENABLED + USB0->GPCS = USB_GPCS_DEVMOD_OTG; + USB0->EPC = USB_EPC_EPENDE | USB_EPC_EPEN_HIGH; +#endif +#if TUSB_OPT_DEVICE_ENABLED + USB0->GPCS = USB_GPCS_DEVMOD_DEVVBUS; +#endif } //--------------------------------------------------------------------+ -- cgit v1.3.1 From ae9a39ec1fec596a7578a137a392b48cdab5ac39 Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Mon, 29 Nov 2021 00:42:18 +0900 Subject: Add musb driver --- examples/host/cdc_msc_hid/Makefile | 3 ++- examples/host/hid_controller/Makefile | 5 +++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/examples/host/cdc_msc_hid/Makefile b/examples/host/cdc_msc_hid/Makefile index 0ad9dd856..fd68a7849 100644 --- a/examples/host/cdc_msc_hid/Makefile +++ b/examples/host/cdc_msc_hid/Makefile @@ -23,6 +23,7 @@ SRC_C += \ src/portable/ehci/ehci.c \ src/portable/ohci/ohci.c \ src/portable/nxp/transdimension/hcd_transdimension.c \ - src/portable/nxp/lpc17_40/hcd_lpc17_40.c + src/portable/nxp/lpc17_40/hcd_lpc17_40.c \ + src/portable/mentor/musb/hcd_musb.c include ../../rules.mk diff --git a/examples/host/hid_controller/Makefile b/examples/host/hid_controller/Makefile index 2595ec4a7..776cfcb88 100644 --- a/examples/host/hid_controller/Makefile +++ b/examples/host/hid_controller/Makefile @@ -9,7 +9,7 @@ INC += \ EXAMPLE_SOURCE += \ src/hid_app.c \ src/main.c - + SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE)) # TODO: suppress warning caused by host stack @@ -26,6 +26,7 @@ SRC_C += \ src/portable/ehci/ehci.c \ src/portable/ohci/ohci.c \ src/portable/nxp/transdimension/hcd_transdimension.c \ - src/portable/nxp/lpc17_40/hcd_lpc17_40.c + src/portable/nxp/lpc17_40/hcd_lpc17_40.c \ + src/portable/mentor/musb/hcd_musb.c include ../../rules.mk -- cgit v1.3.1 From 24614de419f5a7c5871bf6bbd78ec4d01bdca31b Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Mon, 29 Nov 2021 00:45:57 +0900 Subject: Fix build errors --- examples/host/hid_controller/src/hid_app.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/examples/host/hid_controller/src/hid_app.c b/examples/host/hid_controller/src/hid_app.c index bbfea8182..582e01959 100644 --- a/examples/host/hid_controller/src/hid_app.c +++ b/examples/host/hid_controller/src/hid_app.c @@ -138,6 +138,8 @@ void hid_app_task(void) // therefore report_desc = NULL, desc_len = 0 void tuh_hid_mount_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_report, uint16_t desc_len) { + (void)desc_report; + (void)desc_len; uint16_t vid, pid; tuh_vid_pid_get(dev_addr, &vid, &pid); -- cgit v1.3.1 From ab223eb1df187b0fd845fec17b6bf5365216e4f2 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 29 Nov 2021 13:07:46 +0700 Subject: correct 32 button in gamepad hid descriptor template --- src/class/hid/hid_device.h | 64 +++++++++++++++++++++++----------------------- 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/src/class/hid/hid_device.h b/src/class/hid/hid_device.h index 7f67fa9cf..078b67349 100644 --- a/src/class/hid/hid_device.h +++ b/src/class/hid/hid_device.h @@ -310,8 +310,8 @@ static inline bool tud_hid_gamepad_report(uint8_t report_id, int8_t x, int8_t y HID_COLLECTION_END \ // Gamepad Report Descriptor Template -// with 16 buttons, 2 joysticks and 1 hat/dpad with following layout -// | X | Y | Z | Rz | Rx | Ry (1 byte each) | hat/DPAD (1 byte) | Button Map (2 bytes) | +// with 32 buttons, 2 joysticks and 1 hat/dpad with following layout +// | X | Y | Z | Rz | Rx | Ry (1 byte each) | hat/DPAD (1 byte) | Button Map (4 bytes) | #define TUD_HID_REPORT_DESC_GAMEPAD(...) \ HID_USAGE_PAGE ( HID_USAGE_PAGE_DESKTOP ) ,\ HID_USAGE ( HID_USAGE_DESKTOP_GAMEPAD ) ,\ @@ -319,37 +319,37 @@ static inline bool tud_hid_gamepad_report(uint8_t report_id, int8_t x, int8_t y /* Report ID if any */\ __VA_ARGS__ \ /* 8 bit X, Y, Z, Rz, Rx, Ry (min -127, max 127 ) */ \ - HID_USAGE_PAGE ( HID_USAGE_PAGE_DESKTOP ) ,\ - HID_USAGE ( HID_USAGE_DESKTOP_X ) ,\ - HID_USAGE ( HID_USAGE_DESKTOP_Y ) ,\ - HID_USAGE ( HID_USAGE_DESKTOP_Z ) ,\ - HID_USAGE ( HID_USAGE_DESKTOP_RZ ) ,\ - HID_USAGE ( HID_USAGE_DESKTOP_RX ) ,\ - HID_USAGE ( HID_USAGE_DESKTOP_RY ) ,\ - HID_LOGICAL_MIN ( 0x81 ) ,\ - HID_LOGICAL_MAX ( 0x7f ) ,\ - HID_REPORT_COUNT ( 6 ) ,\ - HID_REPORT_SIZE ( 8 ) ,\ - HID_INPUT ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ) ,\ + HID_USAGE_PAGE ( HID_USAGE_PAGE_DESKTOP ) ,\ + HID_USAGE ( HID_USAGE_DESKTOP_X ) ,\ + HID_USAGE ( HID_USAGE_DESKTOP_Y ) ,\ + HID_USAGE ( HID_USAGE_DESKTOP_Z ) ,\ + HID_USAGE ( HID_USAGE_DESKTOP_RZ ) ,\ + HID_USAGE ( HID_USAGE_DESKTOP_RX ) ,\ + HID_USAGE ( HID_USAGE_DESKTOP_RY ) ,\ + HID_LOGICAL_MIN ( 0x81 ) ,\ + HID_LOGICAL_MAX ( 0x7f ) ,\ + HID_REPORT_COUNT ( 6 ) ,\ + HID_REPORT_SIZE ( 8 ) ,\ + HID_INPUT ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ) ,\ /* 8 bit DPad/Hat Button Map */ \ - HID_USAGE_PAGE ( HID_USAGE_PAGE_DESKTOP ) ,\ - HID_USAGE ( HID_USAGE_DESKTOP_HAT_SWITCH ) ,\ - HID_LOGICAL_MIN ( 1 ) ,\ - HID_LOGICAL_MAX ( 8 ) ,\ - HID_PHYSICAL_MIN ( 0 ) ,\ - HID_PHYSICAL_MAX_N ( 315, 2 ) ,\ - HID_REPORT_COUNT ( 1 ) ,\ - HID_REPORT_SIZE ( 8 ) ,\ - HID_INPUT ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ) ,\ - /* 16 bit Button Map */ \ - HID_USAGE_PAGE ( HID_USAGE_PAGE_BUTTON ) ,\ - HID_USAGE_MIN ( 1 ) ,\ - HID_USAGE_MAX ( 32 ) ,\ - HID_LOGICAL_MIN ( 0 ) ,\ - HID_LOGICAL_MAX ( 1 ) ,\ - HID_REPORT_COUNT ( 32 ) ,\ - HID_REPORT_SIZE ( 1 ) ,\ - HID_INPUT ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ) ,\ + HID_USAGE_PAGE ( HID_USAGE_PAGE_DESKTOP ) ,\ + HID_USAGE ( HID_USAGE_DESKTOP_HAT_SWITCH ) ,\ + HID_LOGICAL_MIN ( 1 ) ,\ + HID_LOGICAL_MAX ( 8 ) ,\ + HID_PHYSICAL_MIN ( 0 ) ,\ + HID_PHYSICAL_MAX_N ( 315, 2 ) ,\ + HID_REPORT_COUNT ( 1 ) ,\ + HID_REPORT_SIZE ( 8 ) ,\ + HID_INPUT ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ) ,\ + /* 32 bit Button Map */ \ + HID_USAGE_PAGE ( HID_USAGE_PAGE_BUTTON ) ,\ + HID_USAGE_MIN ( 1 ) ,\ + HID_USAGE_MAX ( 32 ) ,\ + HID_LOGICAL_MIN ( 0 ) ,\ + HID_LOGICAL_MAX ( 1 ) ,\ + HID_REPORT_COUNT ( 32 ) ,\ + HID_REPORT_SIZE ( 1 ) ,\ + HID_INPUT ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ) ,\ HID_COLLECTION_END \ // HID Generic Input & Output -- cgit v1.3.1 From 7ad0af64cc172331413aa634aa28002171fe31ab Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 29 Nov 2021 13:24:10 +0700 Subject: use 4k stack for example with esp32sx --- examples/device/cdc_msc_freertos/src/main.c | 14 ++++++-------- examples/device/hid_composite_freertos/src/main.c | 14 +++++++------- 2 files changed, 13 insertions(+), 15 deletions(-) diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c index 2d3426f1d..0a1c964ae 100644 --- a/examples/device/cdc_msc_freertos/src/main.c +++ b/examples/device/cdc_msc_freertos/src/main.c @@ -38,12 +38,17 @@ #include "freertos/queue.h" #include "freertos/task.h" #include "freertos/timers.h" + + #define USBD_STACK_SIZE 4096 #else #include "FreeRTOS.h" #include "semphr.h" #include "queue.h" #include "task.h" #include "timers.h" + + // Increase stack size when debug log is enabled + #define USBD_STACK_SIZE (3*configMINIMAL_STACK_SIZE/2) * (CFG_TUSB_DEBUG ? 2 : 1) #endif //--------------------------------------------------------------------+ @@ -65,14 +70,7 @@ enum { StaticTimer_t blinky_tmdef; TimerHandle_t blinky_tm; -// static task for usbd -// Increase stack size when debug log is enabled -#if CFG_TUSB_DEBUG - #define USBD_STACK_SIZE (3*configMINIMAL_STACK_SIZE) -#else - #define USBD_STACK_SIZE (3*configMINIMAL_STACK_SIZE/2) -#endif - +// static task StackType_t usb_device_stack[USBD_STACK_SIZE]; StaticTask_t usb_device_taskdef; diff --git a/examples/device/hid_composite_freertos/src/main.c b/examples/device/hid_composite_freertos/src/main.c index 336f5d426..1695f968c 100644 --- a/examples/device/hid_composite_freertos/src/main.c +++ b/examples/device/hid_composite_freertos/src/main.c @@ -39,12 +39,18 @@ #include "freertos/queue.h" #include "freertos/task.h" #include "freertos/timers.h" + + #define USBD_STACK_SIZE 4096 + #else #include "FreeRTOS.h" #include "semphr.h" #include "queue.h" #include "task.h" #include "timers.h" + + // Increase stack size when debug log is enabled + #define USBD_STACK_SIZE (3*configMINIMAL_STACK_SIZE/2) * (CFG_TUSB_DEBUG ? 2 : 1) #endif //--------------------------------------------------------------------+ @@ -66,13 +72,7 @@ enum { StaticTimer_t blinky_tmdef; TimerHandle_t blinky_tm; -// static task for usbd -#if CFG_TUSB_DEBUG - #define USBD_STACK_SIZE (3*configMINIMAL_STACK_SIZE) -#else - #define USBD_STACK_SIZE (3*configMINIMAL_STACK_SIZE/2) -#endif - +// static task StackType_t usb_device_stack[USBD_STACK_SIZE]; StaticTask_t usb_device_taskdef; -- cgit v1.3.1 From 33506675c51e11f3b04cc7a0a4f11af244a0ba11 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 30 Nov 2021 00:33:55 +0700 Subject: update supported doc --- README.rst | 10 +- docs/reference/supported.rst | 234 +++++++++++++++++++++++-------------------- 2 files changed, 131 insertions(+), 113 deletions(-) diff --git a/README.rst b/README.rst index 60df78ca4..a8ce9399c 100644 --- a/README.rst +++ b/README.rst @@ -32,8 +32,10 @@ Supported MCUs The stack supports the following MCUs: +- **Broadcom:** BCM2837, BCM2711 - **Dialog:** DA1469x - **Espressif:** ESP32-S2, ESP32-S3 +- **GigaDevice:** GD32VF103 - **Infineon:** XMC4500 - **MicroChip:** SAMD11, SAMD21, SAMD51, SAME5x, SAMG55, SAML21, SAML22, SAME7x - **NordicSemi:** nRF52833, nRF52840, nRF5340 @@ -41,15 +43,15 @@ The stack supports the following MCUs: - **NXP:** - iMX RT Series: RT1011, RT1015, RT1021, RT1052, RT1062, RT1064 - - Kinetis: KL25, K32L2Bxx + - Kinetis: KL25, K32L2 - LPC Series: 11u, 13, 15, 17, 18, 40, 43, 51u, 54, 55 - **Raspberry Pi:** RP2040 -- **Renesas:** RX63N, RX65N +- **Renesas:** RX63N, RX65N, RX72N - **Silabs:** EFM32GG - **Sony:** CXD56 -- **ST:** STM32 series: L0, L1, L4, L4+, F0, F1, F2, F3, F4, F7, H7 -- **TI:** MSP430 +- **ST:** STM32 series: F0, F1, F2, F3, F4, F7, H7, L0, L1, L4, L4+ +- **TI:** MSP430, MSP432E4, TM4C123 - **ValentyUSB:** eptri Here is the list of `Supported Devices`_ that can be used with provided examples. diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst index 1d2b4db51..254a0d95d 100644 --- a/docs/reference/supported.rst +++ b/docs/reference/supported.rst @@ -11,117 +11,120 @@ Supported MCUs This table is a WIP! the data is not correct, tho if a device is listed, it likely works as a usb full speed device at the least. -+--------------+--------------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| Manufacturer | Family | Device | Host | FS | HS | Known Issues | -+==============+====================+===================+====================+===================+===================+==============+ -| Dialog | DA1469x | |:green_square:| | |:x:| | |:green_square:| | |:x:| | | -+--------------+--------------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| Espressif | ESP32-S2 | |:green_square:| | |:x:| | |:green_square:| | |:x:| | | -| +--------------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| | ESP32-S3 | |:green_square:| | |:x:| | |:green_square:| | |:x:| | | -+--------------+--------------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| MicroChip | SAMD11 | |:green_square:| | |:x:| | |:green_square:| | |:x:| | | -| +--------------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| | SAMD21 | |:green_square:| | |:x:| | |:green_square:| | |:x:| | | -| +--------------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| | SAMD51 | |:green_square:| | |:x:| | |:green_square:| | |:x:| | | -| +--------------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| | SAME5x | |:green_square:| | |:x:| | |:green_square:| | |:x:| | | -| +--------------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| | SAMG55 | |:green_square:| | |:x:| | |:green_square:| | |:x:| | | -| +--------------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| | SAML21 | |:green_square:| | |:x:| | |:green_square:| | |:x:| | | -| +--------------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| | SAML22 | |:green_square:| | |:x:| | |:green_square:| | |:x:| | | -| +--------------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| | SAME70,S70,V70,V71 | |:green_square:| | |:red_square:| | |:green_square:| | |:green_square:| | | -+--------------+--------------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| NordicSemi | nRF52833 | |:green_square:| | |:x:| | |:green_square:| | |:x:| | | -| +--------------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| | nRF52840 | |:green_square:| | |:x:| | |:green_square:| | |:x:| | | -+--------------+--------------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| Nuvoton | NUC120 | |:green_square:| | |:x:| | |:green_square:| | |:x:| | | -| +--------------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| | NUC121/NUC125 | |:green_square:| | |:x:| | |:green_square:| | |:x:| | | -| +--------------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| | NUC126 | |:green_square:| | |:x:| | |:green_square:| | |:x:| | | -| +--------------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| | NUC505 | |:green_square:| | |:x:| | |:green_square:| | |:x:| | | -+--------------+-------+------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| NXP | iMX | RT1011 | |:green_square:| | |:yellow_square:| | |:green_square:| | |:x:| | | -| | +------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| | | RT1015 | |:green_square:| | |:yellow_square:| | |:green_square:| | |:x:| | | -| | +------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| | | RT1021 | |:green_square:| | |:yellow_square:| | |:green_square:| | |:x:| | | -| | +------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| | | RT1052 | |:green_square:| | |:yellow_square:| | |:green_square:| | |:x:| | | -| | +------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| | | RT1062 | |:green_square:| | |:yellow_square:| | |:green_square:| | |:x:| | | -| | +------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| | | RT1064 | |:green_square:| | |:yellow_square:| | |:green_square:| | |:x:| | | -| +-------+------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| | Kinetis KL25 | |:green_square:| | |:x:| | |:green_square:| | |:x:| | | -| +-------+------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| | LPC | 11u | |:green_square:| | |:x:| | |:green_square:| | |:x:| | | -| | +------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| | | 13 | |:green_square:| | |:x:| | |:green_square:| | |:x:| | | -| | +------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| | | 15 | |:green_square:| | |:x:| | |:green_square:| | |:x:| | | -| | +------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| | | 17 | |:green_square:| | |:x:| | |:green_square:| | |:x:| | | -| | +------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| | | 18 | | |:yellow_square:| | |:green_square:| | |:x:| | | -| | +------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| | | 40 | | |:x:| | |:green_square:| | |:x:| | | -| | +------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| | | 43 | |:green_square:| | |:yellow_square:| | |:green_square:| | |:x:| | | -| | +------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| | | 51u | |:green_square:| | |:x:| | |:green_square:| | |:x:| | | -| | +------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| | | 54 | |:green_square:| | |:x:| | |:green_square:| | |:x:| | | -| | +------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| | | 55 | |:green_square:| | |:x:| | |:green_square:| | | | -+--------------+-------+------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| Raspberry Pi | RP2040 | |:green_square:| | |:x:| | |:green_square:| | | | -+--------------+--------------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| Renesas | RX63N | |:green_square:| | | |:green_square:| | |:x:| | | -| +--------------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| | RX65N | |:green_square:| | | |:green_square:| | |:x:| | | -+--------------+--------------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| Silabs | EFM32GG12 | |:green_square:| | |:x:| | |:green_square:| | |:x:| | | -+--------------+--------------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| Sony | CXD56 | |:green_square:| | |:x:| | |:green_square:| | |:x:| | | -+--------------+-------+------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| ST | STM32 | L0 | |:green_square:| | | |:green_square:| | | | -| | +------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| | | F0 | |:green_square:| | | |:green_square:| | | | -| | +------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| | | F1 | |:green_square:| | | |:green_square:| | | | -| | +------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| | | F2 | |:green_square:| | | |:green_square:| | | | -| | +------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| | | F3 | |:green_square:| | | |:green_square:| | | | -| | +------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| | | F4 | |:green_square:| | | |:green_square:| | | | -| | +------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| | | F7 | |:green_square:| | | |:green_square:| | | | -| | +------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| | | H7 | |:green_square:| | | |:green_square:| | |:green_square:| | | -+--------------+-------+------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| TI | MSP430 | |:green_square:| | | |:green_square:| | | | -+--------------+--------------------+-------------------+--------------------+-------------------+-------------------+--------------+ -| ValentyUSB | eptri | |:green_square:| | | |:green_square:| | | | -+--------------+--------------------+-------------------+--------------------+-------------------+-------------------+--------------+ ++--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| Manufacturer | Family | Device | Host | Highspeed | Driver | Note | ++==============+=======================+======================+======================+======================+=================+==============+ +| Broadcom | BCM2711, BCM2837 | |:heavy_check_mark:| | | |:heavy_check_mark:| | dwc2 | | ++--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| Dialog | DA1469x | |:heavy_check_mark:| | |:x:| | |:x:| | da146xx | | ++--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| Espressif | ESP32 S2, S3 | |:heavy_check_mark:| | | |:x:| | dwc2 or esp32sx | | ++--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| GigaDevice | GD32VF103 | |:heavy_check_mark:| | | |:x:| | dwc2 | | ++--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| Infineon | XMC4500 | |:heavy_check_mark:| | | |:x:| | dwc2 | | ++--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| MicroChip | SAM D11, D21 | |:heavy_check_mark:| | | |:x:| | samd | | +| +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| | SAM D51, E5x | |:heavy_check_mark:| | | |:x:| | samd | | +| +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| | SAM G55 | |:heavy_check_mark:| | | |:x:| | samg | | +| +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| | SAM L21, L22 | |:heavy_check_mark:| | | |:x:| | samd | | +| +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| | SAM E70,S70,V70,V71 | |:heavy_check_mark:| | | |:heavy_check_mark:| | samx7x | | ++--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| NordicSemi | nRF52833, nRF52840 | |:heavy_check_mark:| | |:x:| | |:x:| | nrf5x | | +| +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| | nRF5340 | |:heavy_check_mark:| | |:x:| | |:x:| | nrf5x | | ++--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| Nuvoton | NUC120 | |:heavy_check_mark:| | |:x:| | |:x:| | | | +| +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| | NUC121/NUC125 | |:heavy_check_mark:| | |:x:| | |:x:| | | | +| +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| | NUC126 | |:heavy_check_mark:| | |:x:| | |:x:| | | | +| +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| | NUC505 | |:heavy_check_mark:| | | |:heavy_check_mark:| | | | ++--------------+---------+-------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| NXP | iMXRT | RT1011 | |:heavy_check_mark:| | |:heavy_check_mark:| | |:heavy_check_mark:| | | | +| | +-------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| | | RT1015 | |:heavy_check_mark:| | |:heavy_check_mark:| | |:heavy_check_mark:| | | | +| | +-------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| | | RT1021 | |:heavy_check_mark:| | |:heavy_check_mark:| | |:heavy_check_mark:| | | | +| | +-------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| | | RT1052 | |:heavy_check_mark:| | |:heavy_check_mark:| | |:heavy_check_mark:| | | | +| | +-------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| | | RT1062 | |:heavy_check_mark:| | |:heavy_check_mark:| | |:heavy_check_mark:| | | | +| | +-------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| | | RT1064 | |:heavy_check_mark:| | |:heavy_check_mark:| | |:heavy_check_mark:| | | | +| +---------+-------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| | Kinetis | KL25 | |:heavy_check_mark:| | | |:x:| | | | +| | +-------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| | | K32L2 | |:heavy_check_mark:| | | |:x:| | | | +| +---------+-------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| | LPC | 11u, 13, 15 | |:heavy_check_mark:| | |:x:| | |:x:| | lpc_ip3511 | | +| | +-------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| | | 17, 40 | |:heavy_check_mark:| | |:construction:| | |:x:| | lpc17_40 | | +| | +-------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| | | 18, 43 | |:heavy_check_mark:| | |:heavy_check_mark:| | |:x:| | | | +| | +-------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| | | 51u | |:heavy_check_mark:| | |:x:| | |:x:| | lpc_ip3511 | | +| | +-------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| | | 54 | |:heavy_check_mark:| | | |:heavy_check_mark:| | lpc_ip3511 | | +| | +-------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| | | 55 | |:heavy_check_mark:| | | |:heavy_check_mark:| | lpc_ip3511 | | ++--------------+---------+-------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| Raspberry Pi | RP2040 | |:heavy_check_mark:| | |:heavy_check_mark:| | |:x:| | rp2040 | | ++--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| Renesas | RX 63N, 65N, 72N | |:heavy_check_mark:| | |:x:| | |:x:| | usba | | ++--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| Silabs | EFM32GG12 | |:heavy_check_mark:| | | |:x:| | dwc2 | | ++--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| Sony | CXD56 | |:heavy_check_mark:| | |:x:| | |:heavy_check_mark:| | cxd56 | | ++--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| ST STM32 | F0 | |:heavy_check_mark:| | |:x:| | |:x:| | stm32_fsdev | | +| +----+------------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| | F1 | 102, 103 | |:heavy_check_mark:| | |:x:| | |:x:| | stm32_fsdev | | +| | +------------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| | | 105, 107 | |:heavy_check_mark:| | | |:x:| | dwc2 | | +| +----+------------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| | F2 | |:heavy_check_mark:| | | |:heavy_check_mark:| | dwc2 | | +| +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| | F3 | |:heavy_check_mark:| | |:x:| | |:x:| | stm32_fsdev | | +| +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| | F4 | |:heavy_check_mark:| | | |:heavy_check_mark:| | dwc2 | | +| +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| | F7 | |:heavy_check_mark:| | | |:heavy_check_mark:| | dwc2 | | +| +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| | H7 | |:heavy_check_mark:| | | |:heavy_check_mark:| | dwc2 | | +| +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| | L0, L1 | |:heavy_check_mark:| | |:x:| | |:x:| | stm32_fsdev | | +| +----+------------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| | L4 | 4x2, 4x3 | |:heavy_check_mark:| | |:x:| | |:x:| | stm32_fsdev | | +| | +------------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| | | 4x5, 4x6 | |:heavy_check_mark:| | | | dwc2 | | +| +----+------------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| | L4+ | |:heavy_check_mark:| | | | dwc2 | | +| +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| | U5 | |:construction:| | | | dwc2 | | ++--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| TI | MSP430 | |:heavy_check_mark:| | |:x:| | |:x:| | msp430x5xx | | +| +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| | MSP432E4 | |:heavy_check_mark:| | | |:x:| | musb | | +| +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| | TM4C123 | |:heavy_check_mark:| | | |:x:| | musb | | ++--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ +| ValentyUSB | eptri | |:heavy_check_mark:| | |:x:| | |:x:| | eptri | | ++--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ Table Legend ------------ -================= =================== -|:x:| Not available -|:red_square:| Not supported -|:yellow_square:| WIP/partial support -|:green_square:| Supported -================= =================== +==================== =================== +|:heavy_check_mark:| Supported +|:construction:| WIP/partial support +|:x:| Not supported +==================== =================== Supported Boards ================ @@ -134,6 +137,11 @@ The board support code is only used for self-contained examples and testing. It The following boards are supported (sorted alphabetically): +Broadcom +-------- + +- `Raspberry Pi CM4 `__ + Dialog DA146xx -------------- @@ -143,12 +151,17 @@ Dialog DA146xx Espressif ESP32-S2 ------------------ -- Adafruit Feather ESP32-S2 +- `Adafruit Feather ESP32-S2 `__ - `Adafruit Magtag 2.9" E-Ink WiFi Display `__ - `Adafruit Metro ESP32-S2 `__ - `ESP32-S2-Kaluga-1 `__ - `ESP32-S2-Saola-1 `__ +GigaDevice +---------- + +- `Sipeed Longan Nano `__ + Infineon --------- @@ -243,7 +256,8 @@ iMX RT Kinetis ^^^^^^^ -- `FRDM-KL25Z `__ +- `Freedom FRDM-KL25Z `__ +- `Freedom FRDM-K32L2B3 `__ LPC 11-13-15 ^^^^^^^^^^^^ @@ -374,6 +388,8 @@ TI -- - `MSP430F5529 USB LaunchPad Evaluation Kit `__ +- `MSP-EXP432E401Y LaunchPad Evaluation Kit `__ +- `TM4C123GXL LaunchPad Evaluation Kit `__ Tomu ---- -- cgit v1.3.1 From 4678a4142e8dff8c0c7b959dd6862eeb9e9d62f1 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 30 Nov 2021 00:35:39 +0700 Subject: remove warnings --- docs/reference/supported.rst | 5 ----- 1 file changed, 5 deletions(-) diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst index 254a0d95d..dfaffe6e3 100644 --- a/docs/reference/supported.rst +++ b/docs/reference/supported.rst @@ -6,11 +6,6 @@ Supported Devices Supported MCUs ============== -.. admonition:: Warning - :class: warning - - This table is a WIP! the data is not correct, tho if a device is listed, it likely works as a usb full speed device at the least. - +--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ | Manufacturer | Family | Device | Host | Highspeed | Driver | Note | +==============+=======================+======================+======================+======================+=================+==============+ -- cgit v1.3.1 From 06f99c220ef4f53677c5e5354a309cad3b4d11ef Mon Sep 17 00:00:00 2001 From: rppicomidi Date: Fri, 12 Nov 2021 14:58:51 -0800 Subject: implement hcd device close --- src/portable/raspberrypi/rp2040/hcd_rp2040.c | 36 ++++++++++++++++++++++++++-- 1 file changed, 34 insertions(+), 2 deletions(-) diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c index 768cccc86..97dae480d 100644 --- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c @@ -64,6 +64,8 @@ enum { USB_SIE_CTRL_PULLDOWN_EN_BITS | USB_SIE_CTRL_EP0_INT_1BUF_BITS }; +enum { ADDR_INVALID = 0xFFu }; + static struct hw_endpoint *get_dev_ep(uint8_t dev_addr, uint8_t ep_addr) { uint8_t num = tu_edpt_number(ep_addr); @@ -346,6 +348,21 @@ static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t dev_addr, uint8_t } } +// return struct hw_endpoint* pointing to the endpoint in the pool or NULL if the dev_addr is not found +static struct hw_endpoint *_hw_find_first_endpoint(uint8_t dev_addr) +{ + struct hw_endpoint *ep = NULL; + for (uint i = 1; i < TU_ARRAY_SIZE(ep_pool); i++) + { + ep = &ep_pool[i]; + if (ep->dev_addr == dev_addr && ep->configured) + { + return ep; + } + } + return NULL; +} + //--------------------------------------------------------------------+ // HCD API //--------------------------------------------------------------------+ @@ -412,9 +429,24 @@ tusb_speed_t hcd_port_speed_get(uint8_t rhport) // Close all opened endpoint belong to this device void hcd_device_close(uint8_t rhport, uint8_t dev_addr) { - (void) rhport; - (void) dev_addr; + assert(rhport == 0); + if (dev_addr == 0) + return; + struct hw_endpoint *ep = _hw_find_first_endpoint(dev_addr); + while (ep) + { + // in case it is an interrupt endpoint, disable it + usb_hw_clear->int_ep_ctrl = (1 << (ep->interrupt_num + 1)); + usb_hw->int_ep_addr_ctrl[ep->interrupt_num] = 0; + // unconfigure the endpoint + ep->configured = false; + *ep->endpoint_control = 0; + *ep->buffer_control = 0; + hw_endpoint_reset_transfer(ep); + ep->dev_addr = ADDR_INVALID; // don't find this one again + ep = _hw_find_first_endpoint(dev_addr); + } pico_trace("hcd_device_close %d\n", dev_addr); } -- cgit v1.3.1 From 006522e4375d58bfe01b9745ff7df35fb3d48868 Mon Sep 17 00:00:00 2001 From: rppicomidi Date: Fri, 12 Nov 2021 14:59:19 -0800 Subject: on unplug release device endpoints --- src/host/usbh.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/host/usbh.c b/src/host/usbh.c index f74e7114c..eca72a1c5 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -546,6 +546,9 @@ void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port hcd_device_close(rhport, dev_addr); + // release all endpoints associated with the device + tu_memclr(dev->ep_status, sizeof(dev->ep_status)); + dev->state = TUSB_DEVICE_STATE_UNPLUG; } } -- cgit v1.3.1 From 3e3fe1e429aed7bd0000f49b1ef15f83eb815a19 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 30 Nov 2021 17:36:52 +0700 Subject: improve hcd_device_close() for rp2040 --- src/host/usbh.c | 5 ++- src/portable/raspberrypi/rp2040/hcd_rp2040.c | 52 ++++++++++------------------ 2 files changed, 21 insertions(+), 36 deletions(-) diff --git a/src/host/usbh.c b/src/host/usbh.c index eca72a1c5..b8439addc 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -541,12 +541,11 @@ void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port usbh_class_drivers[drv_id].close(dev_addr); } - memset(dev->itf2drv, DRVID_INVALID, sizeof(dev->itf2drv)); // invalid mapping - memset(dev->ep2drv , DRVID_INVALID, sizeof(dev->ep2drv )); // invalid mapping - hcd_device_close(rhport, dev_addr); // release all endpoints associated with the device + memset(dev->itf2drv, DRVID_INVALID, sizeof(dev->itf2drv)); // invalid mapping + memset(dev->ep2drv , DRVID_INVALID, sizeof(dev->ep2drv )); // invalid mapping tu_memclr(dev->ep_status, sizeof(dev->ep_status)); dev->state = TUSB_DEVICE_STATE_UNPLUG; diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c index 97dae480d..3e80dd872 100644 --- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c @@ -64,8 +64,6 @@ enum { USB_SIE_CTRL_PULLDOWN_EN_BITS | USB_SIE_CTRL_EP0_INT_1BUF_BITS }; -enum { ADDR_INVALID = 0xFFu }; - static struct hw_endpoint *get_dev_ep(uint8_t dev_addr, uint8_t ep_addr) { uint8_t num = tu_edpt_number(ep_addr); @@ -348,21 +346,6 @@ static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t dev_addr, uint8_t } } -// return struct hw_endpoint* pointing to the endpoint in the pool or NULL if the dev_addr is not found -static struct hw_endpoint *_hw_find_first_endpoint(uint8_t dev_addr) -{ - struct hw_endpoint *ep = NULL; - for (uint i = 1; i < TU_ARRAY_SIZE(ep_pool); i++) - { - ep = &ep_pool[i]; - if (ep->dev_addr == dev_addr && ep->configured) - { - return ep; - } - } - return NULL; -} - //--------------------------------------------------------------------+ // HCD API //--------------------------------------------------------------------+ @@ -429,25 +412,28 @@ tusb_speed_t hcd_port_speed_get(uint8_t rhport) // Close all opened endpoint belong to this device void hcd_device_close(uint8_t rhport, uint8_t dev_addr) { - assert(rhport == 0); - if (dev_addr == 0) - return; + pico_trace("hcd_device_close %d\n", dev_addr); + (void) rhport; - struct hw_endpoint *ep = _hw_find_first_endpoint(dev_addr); - while (ep) + if (dev_addr == 0) return; + + for (size_t i = 1; i < TU_ARRAY_SIZE(ep_pool); i++) + { + hw_endpoint_t* ep = &ep_pool[i]; + + if (ep->dev_addr == dev_addr && ep->configured) { - // in case it is an interrupt endpoint, disable it - usb_hw_clear->int_ep_ctrl = (1 << (ep->interrupt_num + 1)); - usb_hw->int_ep_addr_ctrl[ep->interrupt_num] = 0; - // unconfigure the endpoint - ep->configured = false; - *ep->endpoint_control = 0; - *ep->buffer_control = 0; - hw_endpoint_reset_transfer(ep); - ep->dev_addr = ADDR_INVALID; // don't find this one again - ep = _hw_find_first_endpoint(dev_addr); + // in case it is an interrupt endpoint, disable it + usb_hw_clear->int_ep_ctrl = (1 << (ep->interrupt_num + 1)); + usb_hw->int_ep_addr_ctrl[ep->interrupt_num] = 0; + + // unconfigure the endpoint + ep->configured = false; + *ep->endpoint_control = 0; + *ep->buffer_control = 0; + hw_endpoint_reset_transfer(ep); } - pico_trace("hcd_device_close %d\n", dev_addr); + } } uint32_t hcd_frame_number(uint8_t rhport) -- cgit v1.3.1 From 9bccc8068baf6efef0bd040ec5238369c0a03c0f Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Tue, 30 Nov 2021 23:13:20 +0900 Subject: Add register settings to handle a HUB --- src/portable/mentor/musb/hcd_musb.c | 24 +++++++++++++++++++++--- 1 file changed, 21 insertions(+), 3 deletions(-) diff --git a/src/portable/mentor/musb/hcd_musb.c b/src/portable/mentor/musb/hcd_musb.c index b4931a793..dc614d074 100644 --- a/src/portable/mentor/musb/hcd_musb.c +++ b/src/portable/mentor/musb/hcd_musb.c @@ -325,7 +325,7 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_ { (void)rhport; - const unsigned req = _hcd.bmRequestType; + unsigned const req = _hcd.bmRequestType; TU_ASSERT(req != REQUEST_TYPE_INVALID); TU_ASSERT(dev_addr < sizeof(_hcd.ctl_mps)); @@ -453,6 +453,7 @@ static void process_ep0(uint8_t rhport) /* STATUS IN */ TU_ASSERT(USB_CSRL0_RXRDY == (csrl & USB_CSRL0_RXRDY),); TU_ASSERT(0 == USB0->COUNT0,); + USB0->CSRH0 = USB_CSRH0_FLUSH; USB0->CSRL0 = 0; _hcd.bmRequestType = REQUEST_TYPE_INVALID; hcd_event_xfer_complete(dev_addr, tu_edpt_addr(0, TUSB_DIR_IN), @@ -694,7 +695,17 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet _hcd.pipe0.buf = (void*)(uintptr_t)setup_packet; _hcd.pipe0.length = 8; _hcd.pipe0.remaining = 0; - _hcd.bmRequestType = REQUEST_TYPE_INVALID; + + hcd_devtree_info_t devtree; + hcd_devtree_get_info(dev_addr, &devtree); + switch (devtree.speed) { + default: return false; + case TUSB_SPEED_LOW: USB0->TYPE0 = USB_TYPE0_SPEED_LOW; break; + case TUSB_SPEED_FULL: USB0->TYPE0 = USB_TYPE0_SPEED_FULL; break; + case TUSB_SPEED_HIGH: USB0->TYPE0 = USB_TYPE0_SPEED_HIGH; break; + } + USB0->TXHUBADDR0 = devtree.hub_addr; + USB0->TXHUBPORT0 = devtree.hub_port; USB0->TXFUNCADDR0 = dev_addr; USB0->CSRL0 = USB_CSRL0_TXRDY | USB_CSRL0_SETUP; return true; @@ -702,6 +713,7 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) { + (void)rhport; if (sizeof(_hcd.ctl_mps) <= dev_addr) return false; unsigned const ep_addr = ep_desc->bEndpointAddress; unsigned const epn = tu_edpt_number(ep_addr); @@ -733,7 +745,9 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const pipe->remaining = 0; uint8_t pipe_type = 0; - switch (hcd_port_speed_get(rhport)) { + hcd_devtree_info_t devtree; + hcd_devtree_get_info(dev_addr, &devtree); + switch (devtree.speed) { default: return false; case TUSB_SPEED_LOW: pipe_type |= USB_TXTYPE1_SPEED_LOW; break; case TUSB_SPEED_FULL: pipe_type |= USB_TXTYPE1_SPEED_FULL; break; @@ -750,6 +764,8 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const hw_endpoint_t volatile *regs = edpt_regs(pipenum - 1); if (dir_tx) { fadr->TXFUNCADDR = dev_addr; + fadr->TXHUBADDR = devtree.hub_addr; + fadr->TXHUBPORT = devtree.hub_port; regs->TXMAXP = mps; regs->TXTYPE = pipe_type | epn; regs->TXINTERVAL = ep_desc->bInterval; @@ -760,6 +776,8 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const USB0->TXIE |= TU_BIT(pipenum); } else { fadr->RXFUNCADDR = dev_addr; + fadr->RXHUBADDR = devtree.hub_addr; + fadr->RXHUBPORT = devtree.hub_port; regs->RXMAXP = mps; regs->RXTYPE = pipe_type | epn; regs->RXINTERVAL = ep_desc->bInterval; -- cgit v1.3.1 From 0612433eef6e6a7029b314a4a59ef591e72341f5 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 1 Dec 2021 12:14:44 +0700 Subject: add chipidea highspeed controller add warning to transdimension for the rename --- examples/host/cdc_msc_hid/Makefile | 2 - hw/bsp/lpc18/family.mk | 4 +- src/device/dcd_attr.h | 2 + src/portable/chipidea/ci_hs/ci_hs_type.h | 136 +++++ src/portable/chipidea/ci_hs/dcd_ci_hs.c | 662 +++++++++++++++++++++ src/portable/chipidea/ci_hs/hcd_ci_hs.c | 117 ++++ .../nxp/transdimension/dcd_transdimension.c | 2 + .../nxp/transdimension/hcd_transdimension.c | 2 + 8 files changed, 924 insertions(+), 3 deletions(-) create mode 100644 src/portable/chipidea/ci_hs/ci_hs_type.h create mode 100644 src/portable/chipidea/ci_hs/dcd_ci_hs.c create mode 100644 src/portable/chipidea/ci_hs/hcd_ci_hs.c diff --git a/examples/host/cdc_msc_hid/Makefile b/examples/host/cdc_msc_hid/Makefile index 0ad9dd856..ce0dd1a40 100644 --- a/examples/host/cdc_msc_hid/Makefile +++ b/examples/host/cdc_msc_hid/Makefile @@ -20,9 +20,7 @@ SRC_C += \ src/host/hub.c \ src/host/usbh.c \ src/host/usbh_control.c \ - src/portable/ehci/ehci.c \ src/portable/ohci/ohci.c \ - src/portable/nxp/transdimension/hcd_transdimension.c \ src/portable/nxp/lpc17_40/hcd_lpc17_40.c include ../../rules.mk diff --git a/hw/bsp/lpc18/family.mk b/hw/bsp/lpc18/family.mk index 79a00cb2d..7aa36abc4 100644 --- a/hw/bsp/lpc18/family.mk +++ b/hw/bsp/lpc18/family.mk @@ -18,7 +18,9 @@ CFLAGS += -Wno-error=unused-parameter -Wno-error=strict-prototypes -Wno-error=ca MCU_DIR = hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx SRC_C += \ - src/portable/nxp/transdimension/dcd_transdimension.c \ + src/portable/chipidea/ci_hs/dcd_ci_hs.c \ + src/portable/chipidea/ci_hs/hcd_ci_hs.c \ + src/portable/ehci/ehci.c \ $(MCU_DIR)/../gcc/cr_startup_lpc18xx.c \ $(MCU_DIR)/src/chip_18xx_43xx.c \ $(MCU_DIR)/src/clock_18xx_43xx.c \ diff --git a/src/device/dcd_attr.h b/src/device/dcd_attr.h index 73d592e5c..3c5dadaf4 100644 --- a/src/device/dcd_attr.h +++ b/src/device/dcd_attr.h @@ -44,6 +44,7 @@ #elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX) // TODO USB0 has 6, USB1 has 4 + #define DCD_ATTR_CONTROLLER_CHIPIDEA_HS #define DCD_ATTR_ENDPOINT_MAX 6 #elif TU_CHECK_MCU(OPT_MCU_LPC51UXX) @@ -58,6 +59,7 @@ #define DCD_ATTR_ENDPOINT_MAX 6 #elif TU_CHECK_MCU(OPT_MCU_MIMXRT10XX) + #define DCD_ATTR_CONTROLLER_CHIPIDEA_HS #define DCD_ATTR_ENDPOINT_MAX 8 #elif TU_CHECK_MCU(OPT_MCU_MKL25ZXX, OPT_MCU_K32L2BXX) diff --git a/src/portable/chipidea/ci_hs/ci_hs_type.h b/src/portable/chipidea/ci_hs/ci_hs_type.h new file mode 100644 index 000000000..402c26334 --- /dev/null +++ b/src/portable/chipidea/ci_hs/ci_hs_type.h @@ -0,0 +1,136 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef CI_HS_TYPE_H_ +#define CI_HS_TYPE_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +// USBCMD +enum { + USBCMD_RUN_STOP = TU_BIT(0), + USBCMD_RESET = TU_BIT(1), + USBCMD_SETUP_TRIPWIRE = TU_BIT(13), + USBCMD_ADD_QTD_TRIPWIRE = TU_BIT(14) ///< This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint’s linked list. This bit is set and cleared by software during the process of adding a new dTD +// Interrupt Threshold bit 23:16 +}; + +// PORTSC1 +#define PORTSC1_PORT_SPEED_POS 26 + +enum { + PORTSC1_CURRENT_CONNECT_STATUS = TU_BIT(0), + PORTSC1_FORCE_PORT_RESUME = TU_BIT(6), + PORTSC1_SUSPEND = TU_BIT(7), + PORTSC1_FORCE_FULL_SPEED = TU_BIT(24), + PORTSC1_PORT_SPEED = TU_BIT(26) | TU_BIT(27) +}; + +// OTGSC +enum { + OTGSC_VBUS_DISCHARGE = TU_BIT(0), + OTGSC_VBUS_CHARGE = TU_BIT(1), +// OTGSC_HWASSIST_AUTORESET = TU_BIT(2), + OTGSC_OTG_TERMINATION = TU_BIT(3), ///< Must set to 1 when OTG go to device mode + OTGSC_DATA_PULSING = TU_BIT(4), + OTGSC_ID_PULLUP = TU_BIT(5), +// OTGSC_HWASSIT_DATA_PULSE = TU_BIT(6), +// OTGSC_HWASSIT_BDIS_ACONN = TU_BIT(7), + OTGSC_ID = TU_BIT(8), ///< 0 = A device, 1 = B Device + OTGSC_A_VBUS_VALID = TU_BIT(9), + OTGSC_A_SESSION_VALID = TU_BIT(10), + OTGSC_B_SESSION_VALID = TU_BIT(11), + OTGSC_B_SESSION_END = TU_BIT(12), + OTGSC_1MS_TOGGLE = TU_BIT(13), + OTGSC_DATA_BUS_PULSING_STATUS = TU_BIT(14), +}; + +// USBMode +enum { + USBMODE_CM_DEVICE = 2, + USBMODE_CM_HOST = 3, + + USBMODE_SLOM = TU_BIT(3), + USBMODE_SDIS = TU_BIT(4), + + USBMODE_VBUS_POWER_SELECT = TU_BIT(5), // Need to be enabled for LPC18XX/43XX in host mode +}; + +// Device Registers +typedef struct +{ + //------------- ID + HW Parameter Registers-------------// + __I uint32_t TU_RESERVED[64]; ///< For iMX RT10xx, but not used by LPC18XX/LPC43XX + + //------------- Capability Registers-------------// + __I uint8_t CAPLENGTH; ///< Capability Registers Length + __I uint8_t TU_RESERVED[1]; + __I uint16_t HCIVERSION; ///< Host Controller Interface Version + + __I uint32_t HCSPARAMS; ///< Host Controller Structural Parameters + __I uint32_t HCCPARAMS; ///< Host Controller Capability Parameters + __I uint32_t TU_RESERVED[5]; + + __I uint16_t DCIVERSION; ///< Device Controller Interface Version + __I uint8_t TU_RESERVED[2]; + + __I uint32_t DCCPARAMS; ///< Device Controller Capability Parameters + __I uint32_t TU_RESERVED[6]; + + //------------- Operational Registers -------------// + __IO uint32_t USBCMD; ///< USB Command Register + __IO uint32_t USBSTS; ///< USB Status Register + __IO uint32_t USBINTR; ///< Interrupt Enable Register + __IO uint32_t FRINDEX; ///< USB Frame Index + __I uint32_t TU_RESERVED; + __IO uint32_t DEVICEADDR; ///< Device Address + __IO uint32_t ENDPTLISTADDR; ///< Endpoint List Address + __I uint32_t TU_RESERVED; + __IO uint32_t BURSTSIZE; ///< Programmable Burst Size + __IO uint32_t TXFILLTUNING; ///< TX FIFO Fill Tuning + uint32_t TU_RESERVED[4]; + __IO uint32_t ENDPTNAK; ///< Endpoint NAK + __IO uint32_t ENDPTNAKEN; ///< Endpoint NAK Enable + __I uint32_t TU_RESERVED; + __IO uint32_t PORTSC1; ///< Port Status & Control + __I uint32_t TU_RESERVED[7]; + __IO uint32_t OTGSC; ///< On-The-Go Status & control + __IO uint32_t USBMODE; ///< USB Device Mode + __IO uint32_t ENDPTSETUPSTAT; ///< Endpoint Setup Status + __IO uint32_t ENDPTPRIME; ///< Endpoint Prime + __IO uint32_t ENDPTFLUSH; ///< Endpoint Flush + __I uint32_t ENDPTSTAT; ///< Endpoint Status + __IO uint32_t ENDPTCOMPLETE; ///< Endpoint Complete + __IO uint32_t ENDPTCTRL[8]; ///< Endpoint Control 0 - 7 +} dcd_registers_t, hcd_registers_t; + +#ifdef __cplusplus + } +#endif + +#endif /* CI_HS_TYPE_H_ */ diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c new file mode 100644 index 000000000..e531cd842 --- /dev/null +++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c @@ -0,0 +1,662 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "tusb_option.h" + +#if TUSB_OPT_DEVICE_ENABLED && \ + (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX) + +//--------------------------------------------------------------------+ +// INCLUDE +//--------------------------------------------------------------------+ +#if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX + #include "fsl_device_registers.h" + #define INCLUDE_FSL_DEVICE_REGISTERS +#else + // LPCOpen for 18xx & 43xx + #include "chip.h" +#endif + +#include "common/tusb_common.h" +#include "device/dcd.h" +#include "ci_hs_type.h" + +#if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1 + #define CleanInvalidateDCache_by_Addr SCB_CleanInvalidateDCache_by_Addr +#else + #define CleanInvalidateDCache_by_Addr(_addr, _dsize) +#endif + +//--------------------------------------------------------------------+ +// MACRO CONSTANT TYPEDEF +//--------------------------------------------------------------------+ + +// ENDPTCTRL +enum { + ENDPTCTRL_STALL = TU_BIT(0), + ENDPTCTRL_TOGGLE_INHIBIT = TU_BIT(5), // used for test only + ENDPTCTRL_TOGGLE_RESET = TU_BIT(6), + ENDPTCTRL_ENABLE = TU_BIT(7) +}; + +enum { + ENDPTCTRL_TYPE_POS = 2, // Endpoint type is 2-bit field +}; + +// USBSTS, USBINTR +enum { + INTR_USB = TU_BIT(0), + INTR_ERROR = TU_BIT(1), + INTR_PORT_CHANGE = TU_BIT(2), + INTR_RESET = TU_BIT(6), + INTR_SOF = TU_BIT(7), + INTR_SUSPEND = TU_BIT(8), + INTR_NAK = TU_BIT(16) +}; + +// Queue Transfer Descriptor +typedef struct +{ + // Word 0: Next QTD Pointer + uint32_t next; ///< Next link pointer This field contains the physical memory address of the next dTD to be processed + + // Word 1: qTQ Token + uint32_t : 3 ; + volatile uint32_t xact_err : 1 ; + uint32_t : 1 ; + volatile uint32_t buffer_err : 1 ; + volatile uint32_t halted : 1 ; + volatile uint32_t active : 1 ; + uint32_t : 2 ; + uint32_t iso_mult_override : 2 ; ///< This field can be used for transmit ISOs to override the MULT field in the dQH. This field must be zero for all packet types that are not transmit-ISO. + uint32_t : 3 ; + uint32_t int_on_complete : 1 ; + volatile uint32_t total_bytes : 15 ; + uint32_t : 1 ; + + // Word 2-6: Buffer Page Pointer List, Each element in the list is a 4K page aligned, physical memory address. The lower 12 bits in each pointer are reserved (except for the first one) as each memory pointer must reference the start of a 4K page + uint32_t buffer[5]; ///< buffer1 has frame_n for TODO Isochronous + + //--------------------------------------------------------------------+ + // TD is 32 bytes aligned but occupies only 28 bytes + // Therefore there are 4 bytes padding that we can use. + //--------------------------------------------------------------------+ + uint16_t expected_bytes; + uint8_t reserved[2]; +} dcd_qtd_t; + +TU_VERIFY_STATIC( sizeof(dcd_qtd_t) == 32, "size is not correct"); + +// Queue Head +typedef struct +{ + // Word 0: Capabilities and Characteristics + uint32_t : 15 ; ///< Number of packets executed per transaction descriptor 00 - Execute N transactions as demonstrated by the USB variable length protocol where N is computed using Max_packet_length and the Total_bytes field in the dTD. 01 - Execute one transaction 10 - Execute two transactions 11 - Execute three transactions Remark: Non-isochronous endpoints must set MULT = 00. Remark: Isochronous endpoints must set MULT = 01, 10, or 11 as needed. + uint32_t int_on_setup : 1 ; ///< Interrupt on setup This bit is used on control type endpoints to indicate if USBINT is set in response to a setup being received. + uint32_t max_packet_size : 11 ; ///< Endpoint's wMaxPacketSize + uint32_t : 2 ; + uint32_t zero_length_termination : 1 ; ///< This bit is used for non-isochronous endpoints to indicate when a zero-length packet is received to terminate transfers in case the total transfer length is “multiple”. 0 - Enable zero-length packet to terminate transfers equal to a multiple of Max_packet_length (default). 1 - Disable zero-length packet on transfers that are equal in length to a multiple Max_packet_length. + uint32_t iso_mult : 2 ; ///< + + // Word 1: Current qTD Pointer + volatile uint32_t qtd_addr; + + // Word 2-9: Transfer Overlay + volatile dcd_qtd_t qtd_overlay; + + // Word 10-11: Setup request (control OUT only) + volatile tusb_control_request_t setup_request; + + //--------------------------------------------------------------------+ + // QHD is 64 bytes aligned but occupies only 48 bytes + // Therefore there are 16 bytes padding that we can use. + //--------------------------------------------------------------------+ + tu_fifo_t * ff; + uint8_t reserved[12]; +} dcd_qhd_t; + +TU_VERIFY_STATIC( sizeof(dcd_qhd_t) == 64, "size is not correct"); + +//--------------------------------------------------------------------+ +// Variables +//--------------------------------------------------------------------+ + +typedef struct +{ + dcd_registers_t* regs; // registers + const IRQn_Type irqnum; // IRQ number + const uint8_t ep_count; // Max bi-directional Endpoints +}dcd_controller_t; + +#if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX + static const dcd_controller_t _dcd_controller[] = + { + // RT1010 and RT1020 only has 1 USB controller + #if FSL_FEATURE_SOC_USBHS_COUNT == 1 + { .regs = (dcd_registers_t*) USB_BASE , .irqnum = USB_OTG1_IRQn, .ep_count = 8 } + #else + { .regs = (dcd_registers_t*) USB1_BASE, .irqnum = USB_OTG1_IRQn, .ep_count = 8 }, + { .regs = (dcd_registers_t*) USB2_BASE, .irqnum = USB_OTG2_IRQn, .ep_count = 8 } + #endif + }; + +#else + static const dcd_controller_t _dcd_controller[] = + { + { .regs = (dcd_registers_t*) LPC_USB0_BASE, .irqnum = USB0_IRQn, .ep_count = 6 }, + { .regs = (dcd_registers_t*) LPC_USB1_BASE, .irqnum = USB1_IRQn, .ep_count = 4 } + }; +#endif + +#define QTD_NEXT_INVALID 0x01 + +typedef struct { + // Must be at 2K alignment + // Each endpoint with direction (IN/OUT) occupies a queue head + // for portability, TinyUSB only queue 1 TD for each Qhd + dcd_qhd_t qhd[DCD_ATTR_ENDPOINT_MAX][2] TU_ATTR_ALIGNED(64); + dcd_qtd_t qtd[DCD_ATTR_ENDPOINT_MAX][2] TU_ATTR_ALIGNED(32); +}dcd_data_t; + +CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(2048) +static dcd_data_t _dcd_data; + +//--------------------------------------------------------------------+ +// Controller API +//--------------------------------------------------------------------+ + +/// follows LPC43xx User Manual 23.10.3 +static void bus_reset(uint8_t rhport) +{ + dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; + + // The reset value for all endpoint types is the control endpoint. If one endpoint + // direction is enabled and the paired endpoint of opposite direction is disabled, then the + // endpoint type of the unused direction must be changed from the control type to any other + // type (e.g. bulk). Leaving an un-configured endpoint control will cause undefined behavior + // for the data PID tracking on the active endpoint. + for( uint8_t i=1; i < _dcd_controller[rhport].ep_count; i++) + { + dcd_reg->ENDPTCTRL[i] = (TUSB_XFER_BULK << ENDPTCTRL_TYPE_POS) | (TUSB_XFER_BULK << (16+ENDPTCTRL_TYPE_POS)); + } + + //------------- Clear All Registers -------------// + dcd_reg->ENDPTNAK = dcd_reg->ENDPTNAK; + dcd_reg->ENDPTNAKEN = 0; + dcd_reg->USBSTS = dcd_reg->USBSTS; + dcd_reg->ENDPTSETUPSTAT = dcd_reg->ENDPTSETUPSTAT; + dcd_reg->ENDPTCOMPLETE = dcd_reg->ENDPTCOMPLETE; + + while (dcd_reg->ENDPTPRIME) {} + dcd_reg->ENDPTFLUSH = 0xFFFFFFFF; + while (dcd_reg->ENDPTFLUSH) {} + + // read reset bit in portsc + + //------------- Queue Head & Queue TD -------------// + tu_memclr(&_dcd_data, sizeof(dcd_data_t)); + + //------------- Set up Control Endpoints (0 OUT, 1 IN) -------------// + _dcd_data.qhd[0][0].zero_length_termination = _dcd_data.qhd[0][1].zero_length_termination = 1; + _dcd_data.qhd[0][0].max_packet_size = _dcd_data.qhd[0][1].max_packet_size = CFG_TUD_ENDPOINT0_SIZE; + _dcd_data.qhd[0][0].qtd_overlay.next = _dcd_data.qhd[0][1].qtd_overlay.next = QTD_NEXT_INVALID; + + _dcd_data.qhd[0][0].int_on_setup = 1; // OUT only +} + +void dcd_init(uint8_t rhport) +{ + tu_memclr(&_dcd_data, sizeof(dcd_data_t)); + + dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; + + // Reset controller + dcd_reg->USBCMD |= USBCMD_RESET; + while( dcd_reg->USBCMD & USBCMD_RESET ) {} + + // Set mode to device, must be set immediately after reset + dcd_reg->USBMODE = USBMODE_CM_DEVICE; + dcd_reg->OTGSC = OTGSC_VBUS_DISCHARGE | OTGSC_OTG_TERMINATION; + +#if !TUD_OPT_HIGH_SPEED + dcd_reg->PORTSC1 = PORTSC1_FORCE_FULL_SPEED; +#endif + + CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t)); + + dcd_reg->ENDPTLISTADDR = (uint32_t) _dcd_data.qhd; // Endpoint List Address has to be 2K alignment + dcd_reg->USBSTS = dcd_reg->USBSTS; + dcd_reg->USBINTR = INTR_USB | INTR_ERROR | INTR_PORT_CHANGE | INTR_SUSPEND; + + dcd_reg->USBCMD &= ~0x00FF0000; // Interrupt Threshold Interval = 0 + dcd_reg->USBCMD |= USBCMD_RUN_STOP; // Connect +} + +void dcd_int_enable(uint8_t rhport) +{ + NVIC_EnableIRQ(_dcd_controller[rhport].irqnum); +} + +void dcd_int_disable(uint8_t rhport) +{ + NVIC_DisableIRQ(_dcd_controller[rhport].irqnum); +} + +void dcd_set_address(uint8_t rhport, uint8_t dev_addr) +{ + // Response with status first before changing device address + dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0); + + dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; + dcd_reg->DEVICEADDR = (dev_addr << 25) | TU_BIT(24); +} + +void dcd_remote_wakeup(uint8_t rhport) +{ + dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; + dcd_reg->PORTSC1 |= PORTSC1_FORCE_PORT_RESUME; +} + +void dcd_connect(uint8_t rhport) +{ + dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; + dcd_reg->USBCMD |= USBCMD_RUN_STOP; +} + +void dcd_disconnect(uint8_t rhport) +{ + dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; + dcd_reg->USBCMD &= ~USBCMD_RUN_STOP; +} + +//--------------------------------------------------------------------+ +// HELPER +//--------------------------------------------------------------------+ + +static void qtd_init(dcd_qtd_t* p_qtd, void * data_ptr, uint16_t total_bytes) +{ + // Force the CPU to flush the buffer. We increase the size by 31 because the call aligns the + // address to 32-byte boundaries. Buffer must be word aligned + CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) data_ptr, 4), total_bytes + 31); + + tu_memclr(p_qtd, sizeof(dcd_qtd_t)); + + p_qtd->next = QTD_NEXT_INVALID; + p_qtd->active = 1; + p_qtd->total_bytes = p_qtd->expected_bytes = total_bytes; + p_qtd->int_on_complete = true; + + if (data_ptr != NULL) + { + p_qtd->buffer[0] = (uint32_t) data_ptr; + + uint32_t const bufend = p_qtd->buffer[0] + total_bytes; + for(uint8_t i=1; i<5; i++) + { + uint32_t const next_page = tu_align4k( p_qtd->buffer[i-1] ) + 4096; + if ( bufend <= next_page ) break; + + p_qtd->buffer[i] = next_page; + + // TODO page[1] FRAME_N for ISO transfer + } + } +} + +//--------------------------------------------------------------------+ +// DCD Endpoint Port +//--------------------------------------------------------------------+ +void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) +{ + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; + dcd_reg->ENDPTCTRL[epnum] |= ENDPTCTRL_STALL << (dir ? 16 : 0); + + // flush to abort any primed buffer + dcd_reg->ENDPTFLUSH = TU_BIT(epnum + (dir ? 16 : 0)); +} + +void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) +{ + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + // data toggle also need to be reset + dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; + dcd_reg->ENDPTCTRL[epnum] |= ENDPTCTRL_TOGGLE_RESET << ( dir ? 16 : 0 ); + dcd_reg->ENDPTCTRL[epnum] &= ~(ENDPTCTRL_STALL << ( dir ? 16 : 0)); +} + +bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) +{ + uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress); + uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress); + + // Must not exceed max endpoint number + TU_ASSERT( epnum < _dcd_controller[rhport].ep_count ); + + //------------- Prepare Queue Head -------------// + dcd_qhd_t * p_qhd = &_dcd_data.qhd[epnum][dir]; + tu_memclr(p_qhd, sizeof(dcd_qhd_t)); + + p_qhd->zero_length_termination = 1; + p_qhd->max_packet_size = tu_edpt_packet_size(p_endpoint_desc); + if (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) + { + p_qhd->iso_mult = 1; + } + + p_qhd->qtd_overlay.next = QTD_NEXT_INVALID; + + CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t)); + + // Enable EP Control + dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; + + uint32_t const epctrl = (p_endpoint_desc->bmAttributes.xfer << ENDPTCTRL_TYPE_POS) | ENDPTCTRL_ENABLE | ENDPTCTRL_TOGGLE_RESET; + + if ( dir == TUSB_DIR_OUT ) + { + dcd_reg->ENDPTCTRL[epnum] = (dcd_reg->ENDPTCTRL[epnum] & 0xFFFF0000u) | epctrl; + }else + { + dcd_reg->ENDPTCTRL[epnum] = (dcd_reg->ENDPTCTRL[epnum] & 0x0000FFFFu) | (epctrl << 16); + } + + return true; +} + +void dcd_edpt_close_all (uint8_t rhport) +{ + dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; + + // Disable all non-control endpoints + for( uint8_t epnum=1; epnum < _dcd_controller[rhport].ep_count; epnum++) + { + _dcd_data.qhd[epnum][TUSB_DIR_OUT].qtd_overlay.halted = 1; + _dcd_data.qhd[epnum][TUSB_DIR_IN ].qtd_overlay.halted = 1; + + dcd_reg->ENDPTFLUSH = TU_BIT(epnum) | TU_BIT(epnum+16); + dcd_reg->ENDPTCTRL[epnum] = (TUSB_XFER_BULK << ENDPTCTRL_TYPE_POS) | (TUSB_XFER_BULK << (16+ENDPTCTRL_TYPE_POS)); + } +} + +void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) +{ + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; + + _dcd_data.qhd[epnum][dir].qtd_overlay.halted = 1; + + // Flush EP + uint32_t const flush_mask = TU_BIT(epnum + (dir ? 16 : 0)); + dcd_reg->ENDPTFLUSH = flush_mask; + while(dcd_reg->ENDPTFLUSH & flush_mask); + + // Clear EP enable + dcd_reg->ENDPTCTRL[epnum] &=~(ENDPTCTRL_ENABLE << (dir ? 16 : 0)); +} + +static void qhd_start_xfer(uint8_t rhport, uint8_t epnum, uint8_t dir) +{ + dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; + dcd_qhd_t* p_qhd = &_dcd_data.qhd[epnum][dir]; + dcd_qtd_t* p_qtd = &_dcd_data.qtd[epnum][dir]; + + p_qhd->qtd_overlay.halted = false; // clear any previous error + p_qhd->qtd_overlay.next = (uint32_t) p_qtd; // link qtd to qhd + + // flush cache + CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t)); + + if ( epnum == 0 ) + { + // follows UM 24.10.8.1.1 Setup packet handling using setup lockout mechanism + // wait until ENDPTSETUPSTAT before priming data/status in response TODO add time out + while(dcd_reg->ENDPTSETUPSTAT & TU_BIT(0)) {} + } + + // start transfer + dcd_reg->ENDPTPRIME = TU_BIT(epnum + (dir ? 16 : 0)); +} + +bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) +{ + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + dcd_qhd_t* p_qhd = &_dcd_data.qhd[epnum][dir]; + dcd_qtd_t* p_qtd = &_dcd_data.qtd[epnum][dir]; + + // Prepare qtd + qtd_init(p_qtd, buffer, total_bytes); + + // Start qhd transfer + p_qhd->ff = NULL; + qhd_start_xfer(rhport, epnum, dir); + + return true; +} + +// fifo has to be aligned to 4k boundary +bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes) +{ + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + dcd_qhd_t * p_qhd = &_dcd_data.qhd[epnum][dir]; + dcd_qtd_t * p_qtd = &_dcd_data.qtd[epnum][dir]; + + tu_fifo_buffer_info_t fifo_info; + + if (dir) + { + tu_fifo_get_read_info(ff, &fifo_info); + } else + { + tu_fifo_get_write_info(ff, &fifo_info); + } + + if ( fifo_info.len_lin >= total_bytes ) + { + // Linear length is enough for this transfer + qtd_init(p_qtd, fifo_info.ptr_lin, total_bytes); + } + else + { + // linear part is not enough + + // prepare TD up to linear length + qtd_init(p_qtd, fifo_info.ptr_lin, fifo_info.len_lin); + + if ( !tu_offset4k((uint32_t) fifo_info.ptr_wrap) && !tu_offset4k(tu_fifo_depth(ff)) ) + { + // If buffer is aligned to 4K & buffer size is multiple of 4K + // We can make use of buffer page array to also combine the linear + wrapped length + p_qtd->total_bytes = p_qtd->expected_bytes = total_bytes; + + for(uint8_t i = 1, page = 0; i < 5; i++) + { + // pick up buffer array where linear ends + if (p_qtd->buffer[i] == 0) + { + p_qtd->buffer[i] = (uint32_t) fifo_info.ptr_wrap + 4096 * page; + page++; + } + } + + CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) fifo_info.ptr_wrap, 4), total_bytes - fifo_info.len_wrap + 31); + } + else + { + // TODO we may need to carry the wrapped length after the linear part complete + // for now only transfer up to linear part + } + } + + // Start qhd transfer + p_qhd->ff = ff; + qhd_start_xfer(rhport, epnum, dir); + + return true; +} + +//--------------------------------------------------------------------+ +// ISR +//--------------------------------------------------------------------+ + +static void process_edpt_complete_isr(uint8_t rhport, uint8_t epnum, uint8_t dir) +{ + dcd_qhd_t * p_qhd = &_dcd_data.qhd[epnum][dir]; + dcd_qtd_t * p_qtd = &_dcd_data.qtd[epnum][dir]; + + uint8_t result = p_qtd->halted ? XFER_RESULT_STALLED : + ( p_qtd->xact_err || p_qtd->buffer_err ) ? XFER_RESULT_FAILED : XFER_RESULT_SUCCESS; + + if ( result != XFER_RESULT_SUCCESS ) + { + dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; + // flush to abort error buffer + dcd_reg->ENDPTFLUSH = TU_BIT(epnum + (dir ? 16 : 0)); + } + + uint16_t const xferred_bytes = p_qtd->expected_bytes - p_qtd->total_bytes; + + if (p_qhd->ff) + { + if (dir == TUSB_DIR_IN) + { + tu_fifo_advance_read_pointer(p_qhd->ff, xferred_bytes); + } else + { + tu_fifo_advance_write_pointer(p_qhd->ff, xferred_bytes); + } + } + + // only number of bytes in the IOC qtd + dcd_event_xfer_complete(rhport, tu_edpt_addr(epnum, dir), xferred_bytes, result, true); +} + +void dcd_int_handler(uint8_t rhport) +{ + dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; + + uint32_t const int_enable = dcd_reg->USBINTR; + uint32_t const int_status = dcd_reg->USBSTS & int_enable; + dcd_reg->USBSTS = int_status; // Acknowledge handled interrupt + + // disabled interrupt sources + if (int_status == 0) return; + + // Set if the port controller enters the full or high-speed operational state. + // either from Bus Reset or Suspended state + if (int_status & INTR_PORT_CHANGE) + { + // TU_LOG2("PortChange %08lx\r\n", dcd_reg->PORTSC1); + + // Reset interrupt is not enabled, we manually check if Port Change is due + // to connection / disconnection + if ( dcd_reg->USBSTS & INTR_RESET ) + { + dcd_reg->USBSTS = INTR_RESET; + + if (dcd_reg->PORTSC1 & PORTSC1_CURRENT_CONNECT_STATUS) + { + uint32_t const speed = (dcd_reg->PORTSC1 & PORTSC1_PORT_SPEED) >> PORTSC1_PORT_SPEED_POS; + bus_reset(rhport); + dcd_event_bus_reset(rhport, (tusb_speed_t) speed, true); + }else + { + dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true); + } + } + else + { + // Triggered by resuming from suspended state + if ( !(dcd_reg->PORTSC1 & PORTSC1_SUSPEND) ) + { + dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true); + } + } + } + + if (int_status & INTR_SUSPEND) + { + // TU_LOG2("Suspend %08lx\r\n", dcd_reg->PORTSC1); + + if (dcd_reg->PORTSC1 & PORTSC1_SUSPEND) + { + // Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration. + // Skip suspend event if we are not addressed + if ((dcd_reg->DEVICEADDR >> 25) & 0x0f) + { + dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); + } + } + } + + if (int_status & INTR_USB) + { + // Make sure we read the latest version of _dcd_data. + CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t)); + + uint32_t const edpt_complete = dcd_reg->ENDPTCOMPLETE; + dcd_reg->ENDPTCOMPLETE = edpt_complete; // acknowledge + + if (dcd_reg->ENDPTSETUPSTAT) + { + //------------- Set up Received -------------// + // 23.10.10.2 Operational model for setup transfers + dcd_reg->ENDPTSETUPSTAT = dcd_reg->ENDPTSETUPSTAT; + + dcd_event_setup_received(rhport, (uint8_t*)(uintptr_t) &_dcd_data.qhd[0][0].setup_request, true); + } + + // 23.10.12.3 Failed QTD also get ENDPTCOMPLETE set + // nothing to do, we will submit xfer as error to usbd + // if (int_status & INTR_ERROR) { } + + if ( edpt_complete ) + { + for(uint8_t epnum = 0; epnum < DCD_ATTR_ENDPOINT_MAX; epnum++) + { + if ( tu_bit_test(edpt_complete, epnum) ) process_edpt_complete_isr(rhport, epnum, TUSB_DIR_OUT); + if ( tu_bit_test(edpt_complete, epnum+16) ) process_edpt_complete_isr(rhport, epnum, TUSB_DIR_IN); + } + } + } + + if (int_status & INTR_SOF) + { + dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true); + } +} + +#endif diff --git a/src/portable/chipidea/ci_hs/hcd_ci_hs.c b/src/portable/chipidea/ci_hs/hcd_ci_hs.c new file mode 100644 index 000000000..a62ebf2a3 --- /dev/null +++ b/src/portable/chipidea/ci_hs/hcd_ci_hs.c @@ -0,0 +1,117 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "tusb_option.h" + +// Chipidea Highspeed USB IP implement EHCI for host functionality + +#if TUSB_OPT_HOST_ENABLED && \ + (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX) + +//--------------------------------------------------------------------+ +// INCLUDE +//--------------------------------------------------------------------+ +#if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX + #include "fsl_device_registers.h" +#else + // LPCOpen for 18xx & 43xx + #include "chip.h" +#endif + +#include "common/tusb_common.h" +#include "ci_hs_type.h" +#include "portable/ehci/ehci_api.h" + +//--------------------------------------------------------------------+ +// MACRO CONSTANT TYPEDEF +//--------------------------------------------------------------------+ + +// TODO can be merged with dcd_controller_t +typedef struct +{ + uint32_t regs_base; // registers base + const IRQn_Type irqnum; // IRQ number +}hcd_controller_t; + +#if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX + static const hcd_controller_t _hcd_controller[] = + { + // RT1010 and RT1020 only has 1 USB controller + #if FSL_FEATURE_SOC_USBHS_COUNT == 1 + { .regs_base = USB_BASE , .irqnum = USB_OTG1_IRQn } + #else + { .regs_base = USB1_BASE, .irqnum = USB_OTG1_IRQn }, + { .regs_base = USB2_BASE, .irqnum = USB_OTG2_IRQn } + #endif + }; + +#else + static const hcd_controller_t _hcd_controller[] = + { + { .regs_base = LPC_USB0_BASE, .irqnum = USB0_IRQn }, + { .regs_base = LPC_USB1_BASE, .irqnum = USB1_IRQn } + }; +#endif + +//--------------------------------------------------------------------+ +// Controller API +//--------------------------------------------------------------------+ + +bool hcd_init(uint8_t rhport) +{ + hcd_registers_t* hcd_reg = (hcd_registers_t*) _hcd_controller[rhport].regs_base; + + // Reset controller + hcd_reg->USBCMD |= USBCMD_RESET; + while( hcd_reg->USBCMD & USBCMD_RESET ) {} + + // Set mode to device, must be set immediately after reset +#if CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX + // LPC18XX/43XX need to set VBUS Power Select to HIGH + // RHPORT1 is fullspeed only (need external PHY for Highspeed) + hcd_reg->USBMODE = USBMODE_CM_HOST | USBMODE_VBUS_POWER_SELECT; + if (rhport == 1) hcd_reg->PORTSC1 |= PORTSC1_FORCE_FULL_SPEED; +#else + hcd_reg->USBMODE = USBMODE_CM_HOST; +#endif + + // FIXME force full speed, still have issue with Highspeed enumeration + hcd_reg->PORTSC1 |= PORTSC1_FORCE_FULL_SPEED; + + return ehci_init(rhport, (uint32_t) &hcd_reg->CAPLENGTH, (uint32_t) &hcd_reg->USBCMD); +} + +void hcd_int_enable(uint8_t rhport) +{ + NVIC_EnableIRQ(_hcd_controller[rhport].irqnum); +} + +void hcd_int_disable(uint8_t rhport) +{ + NVIC_DisableIRQ(_hcd_controller[rhport].irqnum); +} + +#endif diff --git a/src/portable/nxp/transdimension/dcd_transdimension.c b/src/portable/nxp/transdimension/dcd_transdimension.c index 5ac041fbf..f6433293d 100644 --- a/src/portable/nxp/transdimension/dcd_transdimension.c +++ b/src/portable/nxp/transdimension/dcd_transdimension.c @@ -29,6 +29,8 @@ #if TUSB_OPT_DEVICE_ENABLED && \ (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX) +#warning "transdimenion is renamed to chipidea (portable/chipidea/ci_hs) to match other opensource naming convention such as linux. This file will be removed in the future, please update your makefile accordingly" + //--------------------------------------------------------------------+ // INCLUDE //--------------------------------------------------------------------+ diff --git a/src/portable/nxp/transdimension/hcd_transdimension.c b/src/portable/nxp/transdimension/hcd_transdimension.c index d216f0728..81ad3152d 100644 --- a/src/portable/nxp/transdimension/hcd_transdimension.c +++ b/src/portable/nxp/transdimension/hcd_transdimension.c @@ -31,6 +31,8 @@ #if TUSB_OPT_HOST_ENABLED && \ (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX) +#warning "transdimenion is renamed to chipidea (portable/chipidea/ci_hs) to match other opensource naming convention such as linux. This file will be removed in the future, please update your makefile accordingly" + //--------------------------------------------------------------------+ // INCLUDE //--------------------------------------------------------------------+ -- cgit v1.3.1 From c9d9bfab924244da285895d1d594900e8de303fe Mon Sep 17 00:00:00 2001 From: Sebastien COUDREAU Date: Wed, 1 Dec 2021 17:10:31 +0100 Subject: Remove unused-parameter errors when LOGGER=SWO --- hw/bsp/board.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/bsp/board.c b/hw/bsp/board.c index 6a26f55b7..98addca99 100644 --- a/hw/bsp/board.c +++ b/hw/bsp/board.c @@ -126,6 +126,8 @@ TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count) TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count) { (void) fhdl; + (void) buf; + (void) count; return 0; } -- cgit v1.3.1 From 61a9e125db82ed73b56e7111c3b63c85edbf8d0b Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 1 Dec 2021 23:19:17 +0700 Subject: more ci abstract --- hw/bsp/imxrt/family.mk | 4 +- src/portable/chipidea/ci_hs/ci_hs_imxrt.h | 61 ++++++++++++++++++++ src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h | 57 +++++++++++++++++++ src/portable/chipidea/ci_hs/ci_hs_type.h | 80 ++++++++++++++------------ src/portable/chipidea/ci_hs/dcd_ci_hs.c | 84 ++++++++-------------------- 5 files changed, 188 insertions(+), 98 deletions(-) create mode 100644 src/portable/chipidea/ci_hs/ci_hs_imxrt.h create mode 100644 src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h diff --git a/hw/bsp/imxrt/family.mk b/hw/bsp/imxrt/family.mk index a919d3698..d086d503f 100644 --- a/hw/bsp/imxrt/family.mk +++ b/hw/bsp/imxrt/family.mk @@ -28,7 +28,9 @@ LDFLAGS += \ -Wl,--defsym,__stack_size__=0x800 \ SRC_C += \ - src/portable/nxp/transdimension/dcd_transdimension.c \ + src/portable/chipidea/ci_hs/dcd_ci_hs.c \ + src/portable/chipidea/ci_hs/hcd_ci_hs.c \ + src/portable/ehci/ehci.c \ $(MCU_DIR)/system_$(MCU_VARIANT).c \ $(MCU_DIR)/xip/fsl_flexspi_nor_boot.c \ $(MCU_DIR)/project_template/clock_config.c \ diff --git a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h new file mode 100644 index 000000000..3c92dccb6 --- /dev/null +++ b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h @@ -0,0 +1,61 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef _CI_HS_IMXRT_H_ +#define _CI_HS_IMXRT_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "fsl_device_registers.h" + +static const dcd_controller_t _dcd_controller[] = +{ + // RT1010 and RT1020 only has 1 USB controller + #if FSL_FEATURE_SOC_USBHS_COUNT == 1 + { .regs = (ci_hs_regs_t*) USB_BASE , .irqnum = USB_OTG1_IRQn, .ep_count = 8 } + #else + { .regs = (ci_hs_regs_t*) USB1_BASE, .irqnum = USB_OTG1_IRQn, .ep_count = 8 }, + { .regs = (ci_hs_regs_t*) USB2_BASE, .irqnum = USB_OTG2_IRQn, .ep_count = 8 } + #endif +}; + +void dcd_int_enable(uint8_t rhport) +{ + NVIC_EnableIRQ(_dcd_controller[rhport].irqnum); +} + +void dcd_int_disable(uint8_t rhport) +{ + NVIC_DisableIRQ(_dcd_controller[rhport].irqnum); +} + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h b/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h new file mode 100644 index 000000000..c4f94820d --- /dev/null +++ b/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h @@ -0,0 +1,57 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef _CI_HS_LPC18_43_H_ +#define _CI_HS_LPC18_43_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +// LPCOpen for 18xx & 43xx +#include "chip.h" + +static const dcd_controller_t _dcd_controller[] = +{ + { .regs = (ci_hs_regs_t*) LPC_USB0_BASE, .irqnum = USB0_IRQn, .ep_count = 6 }, + { .regs = (ci_hs_regs_t*) LPC_USB1_BASE, .irqnum = USB1_IRQn, .ep_count = 4 } +}; + +void dcd_int_enable(uint8_t rhport) +{ + NVIC_EnableIRQ(_dcd_controller[rhport].irqnum); +} + +void dcd_int_disable(uint8_t rhport) +{ + NVIC_DisableIRQ(_dcd_controller[rhport].irqnum); +} + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/src/portable/chipidea/ci_hs/ci_hs_type.h b/src/portable/chipidea/ci_hs/ci_hs_type.h index 402c26334..772a7e413 100644 --- a/src/portable/chipidea/ci_hs/ci_hs_type.h +++ b/src/portable/chipidea/ci_hs/ci_hs_type.h @@ -85,49 +85,57 @@ enum { typedef struct { //------------- ID + HW Parameter Registers-------------// - __I uint32_t TU_RESERVED[64]; ///< For iMX RT10xx, but not used by LPC18XX/LPC43XX + volatile uint32_t TU_RESERVED[64]; ///< For iMX RT10xx, but not used by LPC18XX/LPC43XX //------------- Capability Registers-------------// - __I uint8_t CAPLENGTH; ///< Capability Registers Length - __I uint8_t TU_RESERVED[1]; - __I uint16_t HCIVERSION; ///< Host Controller Interface Version + volatile uint8_t CAPLENGTH; ///< Capability Registers Length + volatile uint8_t TU_RESERVED[1]; + volatile uint16_t HCIVERSION; ///< Host Controller Interface Version - __I uint32_t HCSPARAMS; ///< Host Controller Structural Parameters - __I uint32_t HCCPARAMS; ///< Host Controller Capability Parameters - __I uint32_t TU_RESERVED[5]; + volatile uint32_t HCSPARAMS; ///< Host Controller Structural Parameters + volatile uint32_t HCCPARAMS; ///< Host Controller Capability Parameters + volatile uint32_t TU_RESERVED[5]; - __I uint16_t DCIVERSION; ///< Device Controller Interface Version - __I uint8_t TU_RESERVED[2]; + volatile uint16_t DCIVERSION; ///< Device Controller Interface Version + volatile uint8_t TU_RESERVED[2]; - __I uint32_t DCCPARAMS; ///< Device Controller Capability Parameters - __I uint32_t TU_RESERVED[6]; + volatile uint32_t DCCPARAMS; ///< Device Controller Capability Parameters + volatile uint32_t TU_RESERVED[6]; //------------- Operational Registers -------------// - __IO uint32_t USBCMD; ///< USB Command Register - __IO uint32_t USBSTS; ///< USB Status Register - __IO uint32_t USBINTR; ///< Interrupt Enable Register - __IO uint32_t FRINDEX; ///< USB Frame Index - __I uint32_t TU_RESERVED; - __IO uint32_t DEVICEADDR; ///< Device Address - __IO uint32_t ENDPTLISTADDR; ///< Endpoint List Address - __I uint32_t TU_RESERVED; - __IO uint32_t BURSTSIZE; ///< Programmable Burst Size - __IO uint32_t TXFILLTUNING; ///< TX FIFO Fill Tuning - uint32_t TU_RESERVED[4]; - __IO uint32_t ENDPTNAK; ///< Endpoint NAK - __IO uint32_t ENDPTNAKEN; ///< Endpoint NAK Enable - __I uint32_t TU_RESERVED; - __IO uint32_t PORTSC1; ///< Port Status & Control - __I uint32_t TU_RESERVED[7]; - __IO uint32_t OTGSC; ///< On-The-Go Status & control - __IO uint32_t USBMODE; ///< USB Device Mode - __IO uint32_t ENDPTSETUPSTAT; ///< Endpoint Setup Status - __IO uint32_t ENDPTPRIME; ///< Endpoint Prime - __IO uint32_t ENDPTFLUSH; ///< Endpoint Flush - __I uint32_t ENDPTSTAT; ///< Endpoint Status - __IO uint32_t ENDPTCOMPLETE; ///< Endpoint Complete - __IO uint32_t ENDPTCTRL[8]; ///< Endpoint Control 0 - 7 -} dcd_registers_t, hcd_registers_t; + volatile uint32_t USBCMD; ///< USB Command Register + volatile uint32_t USBSTS; ///< USB Status Register + volatile uint32_t USBINTR; ///< Interrupt Enable Register + volatile uint32_t FRINDEX; ///< USB Frame Index + volatile uint32_t TU_RESERVED; + volatile uint32_t DEVICEADDR; ///< Device Address + volatile uint32_t ENDPTLISTADDR; ///< Endpoint List Address + volatile uint32_t TU_RESERVED; + volatile uint32_t BURSTSIZE; ///< Programmable Burst Size + volatile uint32_t TXFILLTUNING; ///< TX FIFO Fill Tuning + uint32_t TU_RESERVED[4]; + volatile uint32_t ENDPTNAK; ///< Endpoint NAK + volatile uint32_t ENDPTNAKEN; ///< Endpoint NAK Enable + volatile uint32_t TU_RESERVED; + volatile uint32_t PORTSC1; ///< Port Status & Control + volatile uint32_t TU_RESERVED[7]; + volatile uint32_t OTGSC; ///< On-The-Go Status & control + volatile uint32_t USBMODE; ///< USB Device Mode + volatile uint32_t ENDPTSETUPSTAT; ///< Endpoint Setup Status + volatile uint32_t ENDPTPRIME; ///< Endpoint Prime + volatile uint32_t ENDPTFLUSH; ///< Endpoint Flush + volatile uint32_t ENDPTSTAT; ///< Endpoint Status + volatile uint32_t ENDPTCOMPLETE; ///< Endpoint Complete + volatile uint32_t ENDPTCTRL[8]; ///< Endpoint Control 0 - 7 +} ci_hs_regs_t, hcd_registers_t; + + +typedef struct +{ + ci_hs_regs_t* regs; + const uint32_t irqnum; + const uint8_t ep_count; // Max bi-directional Endpoints +}dcd_controller_t; #ifdef __cplusplus } diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c index e531cd842..1824aea86 100644 --- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c +++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c @@ -25,25 +25,24 @@ */ #include "tusb_option.h" +#include "device/dcd_attr.h" -#if TUSB_OPT_DEVICE_ENABLED && \ - (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX) +#if TUSB_OPT_DEVICE_ENABLED && defined(DCD_ATTR_CONTROLLER_CHIPIDEA_HS) //--------------------------------------------------------------------+ // INCLUDE //--------------------------------------------------------------------+ +#include "device/dcd.h" +#include "ci_hs_type.h" + #if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX - #include "fsl_device_registers.h" - #define INCLUDE_FSL_DEVICE_REGISTERS + #include "ci_hs_imxrt.h" +#elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX) + #include "ci_hs_lpc18_43.h" #else - // LPCOpen for 18xx & 43xx - #include "chip.h" + #error "Unsupported MCUs" #endif -#include "common/tusb_common.h" -#include "device/dcd.h" -#include "ci_hs_type.h" - #if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1 #define CleanInvalidateDCache_by_Addr SCB_CleanInvalidateDCache_by_Addr #else @@ -144,33 +143,6 @@ TU_VERIFY_STATIC( sizeof(dcd_qhd_t) == 64, "size is not correct"); // Variables //--------------------------------------------------------------------+ -typedef struct -{ - dcd_registers_t* regs; // registers - const IRQn_Type irqnum; // IRQ number - const uint8_t ep_count; // Max bi-directional Endpoints -}dcd_controller_t; - -#if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX - static const dcd_controller_t _dcd_controller[] = - { - // RT1010 and RT1020 only has 1 USB controller - #if FSL_FEATURE_SOC_USBHS_COUNT == 1 - { .regs = (dcd_registers_t*) USB_BASE , .irqnum = USB_OTG1_IRQn, .ep_count = 8 } - #else - { .regs = (dcd_registers_t*) USB1_BASE, .irqnum = USB_OTG1_IRQn, .ep_count = 8 }, - { .regs = (dcd_registers_t*) USB2_BASE, .irqnum = USB_OTG2_IRQn, .ep_count = 8 } - #endif - }; - -#else - static const dcd_controller_t _dcd_controller[] = - { - { .regs = (dcd_registers_t*) LPC_USB0_BASE, .irqnum = USB0_IRQn, .ep_count = 6 }, - { .regs = (dcd_registers_t*) LPC_USB1_BASE, .irqnum = USB1_IRQn, .ep_count = 4 } - }; -#endif - #define QTD_NEXT_INVALID 0x01 typedef struct { @@ -191,7 +163,7 @@ static dcd_data_t _dcd_data; /// follows LPC43xx User Manual 23.10.3 static void bus_reset(uint8_t rhport) { - dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; + ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs; // The reset value for all endpoint types is the control endpoint. If one endpoint // direction is enabled and the paired endpoint of opposite direction is disabled, then the @@ -231,7 +203,7 @@ void dcd_init(uint8_t rhport) { tu_memclr(&_dcd_data, sizeof(dcd_data_t)); - dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; + ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs; // Reset controller dcd_reg->USBCMD |= USBCMD_RESET; @@ -255,40 +227,30 @@ void dcd_init(uint8_t rhport) dcd_reg->USBCMD |= USBCMD_RUN_STOP; // Connect } -void dcd_int_enable(uint8_t rhport) -{ - NVIC_EnableIRQ(_dcd_controller[rhport].irqnum); -} - -void dcd_int_disable(uint8_t rhport) -{ - NVIC_DisableIRQ(_dcd_controller[rhport].irqnum); -} - void dcd_set_address(uint8_t rhport, uint8_t dev_addr) { // Response with status first before changing device address dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0); - dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; + ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs; dcd_reg->DEVICEADDR = (dev_addr << 25) | TU_BIT(24); } void dcd_remote_wakeup(uint8_t rhport) { - dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; + ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs; dcd_reg->PORTSC1 |= PORTSC1_FORCE_PORT_RESUME; } void dcd_connect(uint8_t rhport) { - dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; + ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs; dcd_reg->USBCMD |= USBCMD_RUN_STOP; } void dcd_disconnect(uint8_t rhport) { - dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; + ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs; dcd_reg->USBCMD &= ~USBCMD_RUN_STOP; } @@ -334,7 +296,7 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); - dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; + ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs; dcd_reg->ENDPTCTRL[epnum] |= ENDPTCTRL_STALL << (dir ? 16 : 0); // flush to abort any primed buffer @@ -347,7 +309,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) uint8_t const dir = tu_edpt_dir(ep_addr); // data toggle also need to be reset - dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; + ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs; dcd_reg->ENDPTCTRL[epnum] |= ENDPTCTRL_TOGGLE_RESET << ( dir ? 16 : 0 ); dcd_reg->ENDPTCTRL[epnum] &= ~(ENDPTCTRL_STALL << ( dir ? 16 : 0)); } @@ -376,7 +338,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t)); // Enable EP Control - dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; + ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs; uint32_t const epctrl = (p_endpoint_desc->bmAttributes.xfer << ENDPTCTRL_TYPE_POS) | ENDPTCTRL_ENABLE | ENDPTCTRL_TOGGLE_RESET; @@ -393,7 +355,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) void dcd_edpt_close_all (uint8_t rhport) { - dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; + ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs; // Disable all non-control endpoints for( uint8_t epnum=1; epnum < _dcd_controller[rhport].ep_count; epnum++) @@ -411,7 +373,7 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); - dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; + ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs; _dcd_data.qhd[epnum][dir].qtd_overlay.halted = 1; @@ -426,7 +388,7 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) static void qhd_start_xfer(uint8_t rhport, uint8_t epnum, uint8_t dir) { - dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; + ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs; dcd_qhd_t* p_qhd = &_dcd_data.qhd[epnum][dir]; dcd_qtd_t* p_qtd = &_dcd_data.qtd[epnum][dir]; @@ -542,7 +504,7 @@ static void process_edpt_complete_isr(uint8_t rhport, uint8_t epnum, uint8_t dir if ( result != XFER_RESULT_SUCCESS ) { - dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; + ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs; // flush to abort error buffer dcd_reg->ENDPTFLUSH = TU_BIT(epnum + (dir ? 16 : 0)); } @@ -566,7 +528,7 @@ static void process_edpt_complete_isr(uint8_t rhport, uint8_t epnum, uint8_t dir void dcd_int_handler(uint8_t rhport) { - dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; + ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs; uint32_t const int_enable = dcd_reg->USBINTR; uint32_t const int_status = dcd_reg->USBSTS & int_enable; -- cgit v1.3.1 From 83dc3e25f002a49f05919c3d8ebac37756641786 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 1 Dec 2021 23:30:09 +0700 Subject: more work to abstract chipidea driver --- hw/bsp/ea4357/board.mk | 4 ++- hw/bsp/ngx4330/board.mk | 4 ++- src/portable/chipidea/ci_hs/ci_hs_imxrt.h | 12 ++++----- src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h | 10 ++++---- src/portable/chipidea/ci_hs/ci_hs_type.h | 8 +++--- src/portable/chipidea/ci_hs/dcd_ci_hs.c | 37 +++++++++++++++------------- 6 files changed, 41 insertions(+), 34 deletions(-) diff --git a/hw/bsp/ea4357/board.mk b/hw/bsp/ea4357/board.mk index 4390d1eda..6f243c6a2 100644 --- a/hw/bsp/ea4357/board.mk +++ b/hw/bsp/ea4357/board.mk @@ -21,7 +21,9 @@ MCU_DIR = hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx LD_FILE = hw/bsp/$(BOARD)/lpc4357.ld SRC_C += \ - src/portable/nxp/transdimension/dcd_transdimension.c \ + src/portable/chipidea/ci_hs/dcd_ci_hs.c \ + src/portable/chipidea/ci_hs/hcd_ci_hs.c \ + src/portable/ehci/ehci.c \ $(MCU_DIR)/../gcc/cr_startup_lpc43xx.c \ $(MCU_DIR)/src/chip_18xx_43xx.c \ $(MCU_DIR)/src/clock_18xx_43xx.c \ diff --git a/hw/bsp/ngx4330/board.mk b/hw/bsp/ngx4330/board.mk index 3b193c0a5..3e901567c 100644 --- a/hw/bsp/ngx4330/board.mk +++ b/hw/bsp/ngx4330/board.mk @@ -21,7 +21,9 @@ MCU_DIR = hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx LD_FILE = hw/bsp/$(BOARD)/ngx4330.ld SRC_C += \ - src/portable/nxp/transdimension/dcd_transdimension.c \ + src/portable/chipidea/ci_hs/dcd_ci_hs.c \ + src/portable/chipidea/ci_hs/hcd_ci_hs.c \ + src/portable/ehci/ehci.c \ $(MCU_DIR)/../gcc/cr_startup_lpc43xx.c \ $(MCU_DIR)/src/chip_18xx_43xx.c \ $(MCU_DIR)/src/clock_18xx_43xx.c \ diff --git a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h index 3c92dccb6..52671509b 100644 --- a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h +++ b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h @@ -33,25 +33,25 @@ #include "fsl_device_registers.h" -static const dcd_controller_t _dcd_controller[] = +static const ci_hs_controller_t _ci_controller[] = { // RT1010 and RT1020 only has 1 USB controller #if FSL_FEATURE_SOC_USBHS_COUNT == 1 - { .regs = (ci_hs_regs_t*) USB_BASE , .irqnum = USB_OTG1_IRQn, .ep_count = 8 } + { .reg_base = USB_BASE , .irqnum = USB_OTG1_IRQn, .ep_count = 8 } #else - { .regs = (ci_hs_regs_t*) USB1_BASE, .irqnum = USB_OTG1_IRQn, .ep_count = 8 }, - { .regs = (ci_hs_regs_t*) USB2_BASE, .irqnum = USB_OTG2_IRQn, .ep_count = 8 } + { .reg_base = USB1_BASE, .irqnum = USB_OTG1_IRQn, .ep_count = 8 }, + { .reg_base = USB2_BASE, .irqnum = USB_OTG2_IRQn, .ep_count = 8 } #endif }; void dcd_int_enable(uint8_t rhport) { - NVIC_EnableIRQ(_dcd_controller[rhport].irqnum); + NVIC_EnableIRQ(_ci_controller[rhport].irqnum); } void dcd_int_disable(uint8_t rhport) { - NVIC_DisableIRQ(_dcd_controller[rhport].irqnum); + NVIC_DisableIRQ(_ci_controller[rhport].irqnum); } #ifdef __cplusplus diff --git a/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h b/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h index c4f94820d..1d6accded 100644 --- a/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h +++ b/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h @@ -34,20 +34,20 @@ // LPCOpen for 18xx & 43xx #include "chip.h" -static const dcd_controller_t _dcd_controller[] = +static const ci_hs_controller_t _ci_controller[] = { - { .regs = (ci_hs_regs_t*) LPC_USB0_BASE, .irqnum = USB0_IRQn, .ep_count = 6 }, - { .regs = (ci_hs_regs_t*) LPC_USB1_BASE, .irqnum = USB1_IRQn, .ep_count = 4 } + { .reg_base = LPC_USB0_BASE, .irqnum = USB0_IRQn, .ep_count = 6 }, + { .reg_base = LPC_USB1_BASE, .irqnum = USB1_IRQn, .ep_count = 4 } }; void dcd_int_enable(uint8_t rhport) { - NVIC_EnableIRQ(_dcd_controller[rhport].irqnum); + NVIC_EnableIRQ(_ci_controller[rhport].irqnum); } void dcd_int_disable(uint8_t rhport) { - NVIC_DisableIRQ(_dcd_controller[rhport].irqnum); + NVIC_DisableIRQ(_ci_controller[rhport].irqnum); } #ifdef __cplusplus diff --git a/src/portable/chipidea/ci_hs/ci_hs_type.h b/src/portable/chipidea/ci_hs/ci_hs_type.h index 772a7e413..810ec15ce 100644 --- a/src/portable/chipidea/ci_hs/ci_hs_type.h +++ b/src/portable/chipidea/ci_hs/ci_hs_type.h @@ -132,10 +132,10 @@ typedef struct typedef struct { - ci_hs_regs_t* regs; - const uint32_t irqnum; - const uint8_t ep_count; // Max bi-directional Endpoints -}dcd_controller_t; + uint32_t reg_base; + uint32_t irqnum; + uint8_t ep_count; // Max bi-directional Endpoints +}ci_hs_controller_t; #ifdef __cplusplus } diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c index 1824aea86..6f28862b7 100644 --- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c +++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c @@ -43,6 +43,9 @@ #error "Unsupported MCUs" #endif + +#define CI_HS_REG(_port) ((ci_hs_regs_t*) _ci_controller[_port].reg_base) + #if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1 #define CleanInvalidateDCache_by_Addr SCB_CleanInvalidateDCache_by_Addr #else @@ -163,14 +166,14 @@ static dcd_data_t _dcd_data; /// follows LPC43xx User Manual 23.10.3 static void bus_reset(uint8_t rhport) { - ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs; + ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport); // The reset value for all endpoint types is the control endpoint. If one endpoint // direction is enabled and the paired endpoint of opposite direction is disabled, then the // endpoint type of the unused direction must be changed from the control type to any other // type (e.g. bulk). Leaving an un-configured endpoint control will cause undefined behavior // for the data PID tracking on the active endpoint. - for( uint8_t i=1; i < _dcd_controller[rhport].ep_count; i++) + for( uint8_t i=1; i < _ci_controller[rhport].ep_count; i++) { dcd_reg->ENDPTCTRL[i] = (TUSB_XFER_BULK << ENDPTCTRL_TYPE_POS) | (TUSB_XFER_BULK << (16+ENDPTCTRL_TYPE_POS)); } @@ -203,7 +206,7 @@ void dcd_init(uint8_t rhport) { tu_memclr(&_dcd_data, sizeof(dcd_data_t)); - ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs; + ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport); // Reset controller dcd_reg->USBCMD |= USBCMD_RESET; @@ -232,25 +235,25 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr) // Response with status first before changing device address dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0); - ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs; + ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport); dcd_reg->DEVICEADDR = (dev_addr << 25) | TU_BIT(24); } void dcd_remote_wakeup(uint8_t rhport) { - ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs; + ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport); dcd_reg->PORTSC1 |= PORTSC1_FORCE_PORT_RESUME; } void dcd_connect(uint8_t rhport) { - ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs; + ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport); dcd_reg->USBCMD |= USBCMD_RUN_STOP; } void dcd_disconnect(uint8_t rhport) { - ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs; + ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport); dcd_reg->USBCMD &= ~USBCMD_RUN_STOP; } @@ -296,7 +299,7 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); - ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs; + ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport); dcd_reg->ENDPTCTRL[epnum] |= ENDPTCTRL_STALL << (dir ? 16 : 0); // flush to abort any primed buffer @@ -309,7 +312,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) uint8_t const dir = tu_edpt_dir(ep_addr); // data toggle also need to be reset - ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs; + ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport); dcd_reg->ENDPTCTRL[epnum] |= ENDPTCTRL_TOGGLE_RESET << ( dir ? 16 : 0 ); dcd_reg->ENDPTCTRL[epnum] &= ~(ENDPTCTRL_STALL << ( dir ? 16 : 0)); } @@ -320,7 +323,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress); // Must not exceed max endpoint number - TU_ASSERT( epnum < _dcd_controller[rhport].ep_count ); + TU_ASSERT( epnum < _ci_controller[rhport].ep_count ); //------------- Prepare Queue Head -------------// dcd_qhd_t * p_qhd = &_dcd_data.qhd[epnum][dir]; @@ -338,7 +341,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t)); // Enable EP Control - ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs; + ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport); uint32_t const epctrl = (p_endpoint_desc->bmAttributes.xfer << ENDPTCTRL_TYPE_POS) | ENDPTCTRL_ENABLE | ENDPTCTRL_TOGGLE_RESET; @@ -355,10 +358,10 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) void dcd_edpt_close_all (uint8_t rhport) { - ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs; + ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport); // Disable all non-control endpoints - for( uint8_t epnum=1; epnum < _dcd_controller[rhport].ep_count; epnum++) + for( uint8_t epnum=1; epnum < _ci_controller[rhport].ep_count; epnum++) { _dcd_data.qhd[epnum][TUSB_DIR_OUT].qtd_overlay.halted = 1; _dcd_data.qhd[epnum][TUSB_DIR_IN ].qtd_overlay.halted = 1; @@ -373,7 +376,7 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); - ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs; + ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport); _dcd_data.qhd[epnum][dir].qtd_overlay.halted = 1; @@ -388,7 +391,7 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) static void qhd_start_xfer(uint8_t rhport, uint8_t epnum, uint8_t dir) { - ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs; + ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport); dcd_qhd_t* p_qhd = &_dcd_data.qhd[epnum][dir]; dcd_qtd_t* p_qtd = &_dcd_data.qtd[epnum][dir]; @@ -504,7 +507,7 @@ static void process_edpt_complete_isr(uint8_t rhport, uint8_t epnum, uint8_t dir if ( result != XFER_RESULT_SUCCESS ) { - ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs; + ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport); // flush to abort error buffer dcd_reg->ENDPTFLUSH = TU_BIT(epnum + (dir ? 16 : 0)); } @@ -528,7 +531,7 @@ static void process_edpt_complete_isr(uint8_t rhport, uint8_t epnum, uint8_t dir void dcd_int_handler(uint8_t rhport) { - ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs; + ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport); uint32_t const int_enable = dcd_reg->USBINTR; uint32_t const int_status = dcd_reg->USBSTS & int_enable; -- cgit v1.3.1 From 207c60d055dd810525db11666b029f322cbaf9e8 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 2 Dec 2021 00:03:44 +0700 Subject: more chipidea --- src/portable/chipidea/ci_hs/ci_hs_imxrt.h | 19 +++-------- src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h | 20 +++--------- src/portable/chipidea/ci_hs/ci_hs_type.h | 2 +- src/portable/chipidea/ci_hs/dcd_ci_hs.c | 16 ++++++++-- src/portable/chipidea/ci_hs/hcd_ci_hs.c | 48 +++++++--------------------- 5 files changed, 34 insertions(+), 71 deletions(-) diff --git a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h index 52671509b..78ca5a5a2 100644 --- a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h +++ b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h @@ -27,10 +27,6 @@ #ifndef _CI_HS_IMXRT_H_ #define _CI_HS_IMXRT_H_ -#ifdef __cplusplus - extern "C" { -#endif - #include "fsl_device_registers.h" static const ci_hs_controller_t _ci_controller[] = @@ -44,18 +40,11 @@ static const ci_hs_controller_t _ci_controller[] = #endif }; -void dcd_int_enable(uint8_t rhport) -{ - NVIC_EnableIRQ(_ci_controller[rhport].irqnum); -} +#define CI_DCD_INT_ENABLE(_p) NVIC_EnableIRQ (_ci_controller[_p].irqnum) +#define CI_DCD_INT_DISABLE(_p) NVIC_DisableIRQ(_ci_controller[_p].irqnum) -void dcd_int_disable(uint8_t rhport) -{ - NVIC_DisableIRQ(_ci_controller[rhport].irqnum); -} +#define CI_HCD_INT_ENABLE(_p) NVIC_EnableIRQ (_ci_controller[_p].irqnum) +#define CI_HCD_INT_DISABLE(_p) NVIC_DisableIRQ(_ci_controller[_p].irqnum) -#ifdef __cplusplus - } -#endif #endif diff --git a/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h b/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h index 1d6accded..8c2e7dfa6 100644 --- a/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h +++ b/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h @@ -27,10 +27,6 @@ #ifndef _CI_HS_LPC18_43_H_ #define _CI_HS_LPC18_43_H_ -#ifdef __cplusplus - extern "C" { -#endif - // LPCOpen for 18xx & 43xx #include "chip.h" @@ -40,18 +36,10 @@ static const ci_hs_controller_t _ci_controller[] = { .reg_base = LPC_USB1_BASE, .irqnum = USB1_IRQn, .ep_count = 4 } }; -void dcd_int_enable(uint8_t rhport) -{ - NVIC_EnableIRQ(_ci_controller[rhport].irqnum); -} - -void dcd_int_disable(uint8_t rhport) -{ - NVIC_DisableIRQ(_ci_controller[rhport].irqnum); -} +#define CI_DCD_INT_ENABLE(_p) NVIC_EnableIRQ (_ci_controller[_p].irqnum) +#define CI_DCD_INT_DISABLE(_p) NVIC_DisableIRQ(_ci_controller[_p].irqnum) -#ifdef __cplusplus - } -#endif +#define CI_HCD_INT_ENABLE(_p) NVIC_EnableIRQ (_ci_controller[_p].irqnum) +#define CI_HCD_INT_DISABLE(_p) NVIC_DisableIRQ(_ci_controller[_p].irqnum) #endif diff --git a/src/portable/chipidea/ci_hs/ci_hs_type.h b/src/portable/chipidea/ci_hs/ci_hs_type.h index 810ec15ce..728a86b86 100644 --- a/src/portable/chipidea/ci_hs/ci_hs_type.h +++ b/src/portable/chipidea/ci_hs/ci_hs_type.h @@ -127,7 +127,7 @@ typedef struct volatile uint32_t ENDPTSTAT; ///< Endpoint Status volatile uint32_t ENDPTCOMPLETE; ///< Endpoint Complete volatile uint32_t ENDPTCTRL[8]; ///< Endpoint Control 0 - 7 -} ci_hs_regs_t, hcd_registers_t; +} ci_hs_regs_t; typedef struct diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c index 6f28862b7..c943396fc 100644 --- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c +++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c @@ -43,6 +43,9 @@ #error "Unsupported MCUs" #endif +//--------------------------------------------------------------------+ +// MACRO CONSTANT TYPEDEF +//--------------------------------------------------------------------+ #define CI_HS_REG(_port) ((ci_hs_regs_t*) _ci_controller[_port].reg_base) @@ -52,9 +55,6 @@ #define CleanInvalidateDCache_by_Addr(_addr, _dsize) #endif -//--------------------------------------------------------------------+ -// MACRO CONSTANT TYPEDEF -//--------------------------------------------------------------------+ // ENDPTCTRL enum { @@ -230,6 +230,16 @@ void dcd_init(uint8_t rhport) dcd_reg->USBCMD |= USBCMD_RUN_STOP; // Connect } +void dcd_int_enable(uint8_t rhport) +{ + CI_DCD_INT_ENABLE(rhport); +} + +void dcd_int_disable(uint8_t rhport) +{ + CI_DCD_INT_DISABLE(rhport); +} + void dcd_set_address(uint8_t rhport, uint8_t dev_addr) { // Response with status first before changing device address diff --git a/src/portable/chipidea/ci_hs/hcd_ci_hs.c b/src/portable/chipidea/ci_hs/hcd_ci_hs.c index a62ebf2a3..3d028bf32 100644 --- a/src/portable/chipidea/ci_hs/hcd_ci_hs.c +++ b/src/portable/chipidea/ci_hs/hcd_ci_hs.c @@ -34,47 +34,23 @@ //--------------------------------------------------------------------+ // INCLUDE //--------------------------------------------------------------------+ +#include "common/tusb_common.h" +#include "portable/ehci/ehci_api.h" +#include "ci_hs_type.h" + #if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX - #include "fsl_device_registers.h" + #include "ci_hs_imxrt.h" +#elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX) + #include "ci_hs_lpc18_43.h" #else - // LPCOpen for 18xx & 43xx - #include "chip.h" + #error "Unsupported MCUs" #endif -#include "common/tusb_common.h" -#include "ci_hs_type.h" -#include "portable/ehci/ehci_api.h" - //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF //--------------------------------------------------------------------+ -// TODO can be merged with dcd_controller_t -typedef struct -{ - uint32_t regs_base; // registers base - const IRQn_Type irqnum; // IRQ number -}hcd_controller_t; - -#if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX - static const hcd_controller_t _hcd_controller[] = - { - // RT1010 and RT1020 only has 1 USB controller - #if FSL_FEATURE_SOC_USBHS_COUNT == 1 - { .regs_base = USB_BASE , .irqnum = USB_OTG1_IRQn } - #else - { .regs_base = USB1_BASE, .irqnum = USB_OTG1_IRQn }, - { .regs_base = USB2_BASE, .irqnum = USB_OTG2_IRQn } - #endif - }; - -#else - static const hcd_controller_t _hcd_controller[] = - { - { .regs_base = LPC_USB0_BASE, .irqnum = USB0_IRQn }, - { .regs_base = LPC_USB1_BASE, .irqnum = USB1_IRQn } - }; -#endif +#define CI_HS_REG(_port) ((ci_hs_regs_t*) _ci_controller[_port].reg_base) //--------------------------------------------------------------------+ // Controller API @@ -82,7 +58,7 @@ typedef struct bool hcd_init(uint8_t rhport) { - hcd_registers_t* hcd_reg = (hcd_registers_t*) _hcd_controller[rhport].regs_base; + ci_hs_regs_t* hcd_reg = CI_HS_REG(rhport); // Reset controller hcd_reg->USBCMD |= USBCMD_RESET; @@ -106,12 +82,12 @@ bool hcd_init(uint8_t rhport) void hcd_int_enable(uint8_t rhport) { - NVIC_EnableIRQ(_hcd_controller[rhport].irqnum); + CI_HCD_INT_ENABLE(rhport); } void hcd_int_disable(uint8_t rhport) { - NVIC_DisableIRQ(_hcd_controller[rhport].irqnum); + CI_HCD_INT_DISABLE(rhport); } #endif -- cgit v1.3.1 From eae4132fbb216329e9a0d8b624baf1c5aad56359 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 2 Dec 2021 11:31:27 +0700 Subject: update supported doc --- docs/reference/supported.rst | 212 +++++++++++++++++++++---------------------- 1 file changed, 101 insertions(+), 111 deletions(-) diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst index dfaffe6e3..83cf874da 100644 --- a/docs/reference/supported.rst +++ b/docs/reference/supported.rst @@ -2,124 +2,114 @@ Supported Devices ***************** - Supported MCUs ============== -+--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| Manufacturer | Family | Device | Host | Highspeed | Driver | Note | -+==============+=======================+======================+======================+======================+=================+==============+ -| Broadcom | BCM2711, BCM2837 | |:heavy_check_mark:| | | |:heavy_check_mark:| | dwc2 | | -+--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| Dialog | DA1469x | |:heavy_check_mark:| | |:x:| | |:x:| | da146xx | | -+--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| Espressif | ESP32 S2, S3 | |:heavy_check_mark:| | | |:x:| | dwc2 or esp32sx | | -+--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| GigaDevice | GD32VF103 | |:heavy_check_mark:| | | |:x:| | dwc2 | | -+--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| Infineon | XMC4500 | |:heavy_check_mark:| | | |:x:| | dwc2 | | -+--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| MicroChip | SAM D11, D21 | |:heavy_check_mark:| | | |:x:| | samd | | -| +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| | SAM D51, E5x | |:heavy_check_mark:| | | |:x:| | samd | | -| +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| | SAM G55 | |:heavy_check_mark:| | | |:x:| | samg | | -| +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| | SAM L21, L22 | |:heavy_check_mark:| | | |:x:| | samd | | -| +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| | SAM E70,S70,V70,V71 | |:heavy_check_mark:| | | |:heavy_check_mark:| | samx7x | | -+--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| NordicSemi | nRF52833, nRF52840 | |:heavy_check_mark:| | |:x:| | |:x:| | nrf5x | | -| +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| | nRF5340 | |:heavy_check_mark:| | |:x:| | |:x:| | nrf5x | | -+--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| Nuvoton | NUC120 | |:heavy_check_mark:| | |:x:| | |:x:| | | | -| +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| | NUC121/NUC125 | |:heavy_check_mark:| | |:x:| | |:x:| | | | -| +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| | NUC126 | |:heavy_check_mark:| | |:x:| | |:x:| | | | -| +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| | NUC505 | |:heavy_check_mark:| | | |:heavy_check_mark:| | | | -+--------------+---------+-------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| NXP | iMXRT | RT1011 | |:heavy_check_mark:| | |:heavy_check_mark:| | |:heavy_check_mark:| | | | -| | +-------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| | | RT1015 | |:heavy_check_mark:| | |:heavy_check_mark:| | |:heavy_check_mark:| | | | -| | +-------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| | | RT1021 | |:heavy_check_mark:| | |:heavy_check_mark:| | |:heavy_check_mark:| | | | -| | +-------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| | | RT1052 | |:heavy_check_mark:| | |:heavy_check_mark:| | |:heavy_check_mark:| | | | -| | +-------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| | | RT1062 | |:heavy_check_mark:| | |:heavy_check_mark:| | |:heavy_check_mark:| | | | -| | +-------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| | | RT1064 | |:heavy_check_mark:| | |:heavy_check_mark:| | |:heavy_check_mark:| | | | -| +---------+-------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| | Kinetis | KL25 | |:heavy_check_mark:| | | |:x:| | | | -| | +-------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| | | K32L2 | |:heavy_check_mark:| | | |:x:| | | | -| +---------+-------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| | LPC | 11u, 13, 15 | |:heavy_check_mark:| | |:x:| | |:x:| | lpc_ip3511 | | -| | +-------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| | | 17, 40 | |:heavy_check_mark:| | |:construction:| | |:x:| | lpc17_40 | | -| | +-------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| | | 18, 43 | |:heavy_check_mark:| | |:heavy_check_mark:| | |:x:| | | | -| | +-------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| | | 51u | |:heavy_check_mark:| | |:x:| | |:x:| | lpc_ip3511 | | -| | +-------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| | | 54 | |:heavy_check_mark:| | | |:heavy_check_mark:| | lpc_ip3511 | | -| | +-------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| | | 55 | |:heavy_check_mark:| | | |:heavy_check_mark:| | lpc_ip3511 | | -+--------------+---------+-------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| Raspberry Pi | RP2040 | |:heavy_check_mark:| | |:heavy_check_mark:| | |:x:| | rp2040 | | -+--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| Renesas | RX 63N, 65N, 72N | |:heavy_check_mark:| | |:x:| | |:x:| | usba | | -+--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| Silabs | EFM32GG12 | |:heavy_check_mark:| | | |:x:| | dwc2 | | -+--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| Sony | CXD56 | |:heavy_check_mark:| | |:x:| | |:heavy_check_mark:| | cxd56 | | -+--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| ST STM32 | F0 | |:heavy_check_mark:| | |:x:| | |:x:| | stm32_fsdev | | -| +----+------------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| | F1 | 102, 103 | |:heavy_check_mark:| | |:x:| | |:x:| | stm32_fsdev | | -| | +------------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| | | 105, 107 | |:heavy_check_mark:| | | |:x:| | dwc2 | | -| +----+------------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| | F2 | |:heavy_check_mark:| | | |:heavy_check_mark:| | dwc2 | | -| +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| | F3 | |:heavy_check_mark:| | |:x:| | |:x:| | stm32_fsdev | | -| +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| | F4 | |:heavy_check_mark:| | | |:heavy_check_mark:| | dwc2 | | -| +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| | F7 | |:heavy_check_mark:| | | |:heavy_check_mark:| | dwc2 | | -| +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| | H7 | |:heavy_check_mark:| | | |:heavy_check_mark:| | dwc2 | | -| +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| | L0, L1 | |:heavy_check_mark:| | |:x:| | |:x:| | stm32_fsdev | | -| +----+------------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| | L4 | 4x2, 4x3 | |:heavy_check_mark:| | |:x:| | |:x:| | stm32_fsdev | | -| | +------------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| | | 4x5, 4x6 | |:heavy_check_mark:| | | | dwc2 | | -| +----+------------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| | L4+ | |:heavy_check_mark:| | | | dwc2 | | -| +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| | U5 | |:construction:| | | | dwc2 | | -+--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| TI | MSP430 | |:heavy_check_mark:| | |:x:| | |:x:| | msp430x5xx | | -| +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| | MSP432E4 | |:heavy_check_mark:| | | |:x:| | musb | | -| +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| | TM4C123 | |:heavy_check_mark:| | | |:x:| | musb | | -+--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ -| ValentyUSB | eptri | |:heavy_check_mark:| | |:x:| | |:x:| | eptri | | -+--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+ ++--------------+-----------------------+--------+------+-----------+-------------------+--------------+ +| Manufacturer | Family | Device | Host | Highspeed | Driver | Note | ++==============+=======================+========+======+===========+===================+==============+ +| Broadcom | BCM2711, BCM2837 | ✔ | | ✔ | dwc2 | | ++--------------+-----------------------+--------+------+-----------+-------------------+--------------+ +| Dialog | DA1469x | ✔ | ✖ | ✖ | da146xx | | ++--------------+-----------------------+--------+------+-----------+-------------------+--------------+ +| Espressif | ESP32 S2, S3 | ✔ | | ✖ | dwc2 or esp32sx | | ++--------------+-----------------------+--------+------+-----------+-------------------+--------------+ +| GigaDevice | GD32VF103 | ✔ | | ✖ | dwc2 | | ++--------------+-----------------------+--------+------+-----------+-------------------+--------------+ +| Infineon | XMC4500 | ✔ | | ✖ | dwc2 | | ++--------------+-----------------------+--------+------+-----------+-------------------+--------------+ +| MicroChip | SAM D11, D21 | ✔ | | ✖ | samd | | +| +-----------------------+--------+------+-----------+-------------------+--------------+ +| | SAM D51, E5x | ✔ | | ✖ | samd | | +| +-----------------------+--------+------+-----------+-------------------+--------------+ +| | SAM G55 | ✔ | | ✖ | samg | | +| +-----------------------+--------+------+-----------+-------------------+--------------+ +| | SAM L21, L22 | ✔ | | ✖ | samd | | +| +-----------------------+--------+------+-----------+-------------------+--------------+ +| | SAM E70,S70,V70,V71 | ✔ | | ✔ | samx7x | | ++--------------+-----------------------+--------+------+-----------+-------------------+--------------+ +| NordicSemi | nRF52833, nRF52840 | ✔ | ✖ | ✖ | nrf5x | | +| +-----------------------+--------+------+-----------+-------------------+--------------+ +| | nRF5340 | ✔ | ✖ | ✖ | nrf5x | | ++--------------+-----------------------+--------+------+-----------+-------------------+--------------+ +| Nuvoton | NUC120 | ✔ | ✖ | ✖ | | | +| +-----------------------+--------+------+-----------+-------------------+--------------+ +| | NUC121/NUC125 | ✔ | ✖ | ✖ | | | +| +-----------------------+--------+------+-----------+-------------------+--------------+ +| | NUC126 | ✔ | ✖ | ✖ | | | +| +-----------------------+--------+------+-----------+-------------------+--------------+ +| | NUC505 | ✔ | | ✔ | | | ++--------------+-----------------------+--------+------+-----------+-------------------+--------------+ +| NXP | iMXRT | RT10xx | ✔ | ✔ | ✔ | ci_hs | | +| +---------+-------------+--------+------+-----------+-------------------+--------------+ +| | Kinetis | KL25 | ✔ | | ✖ | | | +| | +-------------+--------+------+-----------+-------------------+--------------+ +| | | K32L2 | ✔ | | ✖ | | | +| +---------+-------------+--------+------+-----------+-------------------+--------------+ +| | LPC | 11u, 13, 15 | ✔ | ✖ | ✖ | lpc_ip3511 | | +| | +-------------+--------+------+-----------+-------------------+--------------+ +| | | 17, 40 | ✔ | ⚠ | ✖ | lpc17_40 | | +| | +-------------+--------+------+-----------+-------------------+--------------+ +| | | 18, 43 | ✔ | ✔ | ✔ | ci_hs | | +| | +-------------+--------+------+-----------+-------------------+--------------+ +| | | 51u | ✔ | ✖ | ✖ | lpc_ip3511 | | +| | +-------------+--------+------+-----------+-------------------+--------------+ +| | | 54 | ✔ | | ✔ | lpc_ip3511 | | +| | +-------------+--------+------+-----------+-------------------+--------------+ +| | | 55 | ✔ | | ✔ | lpc_ip3511 | | ++--------------+---------+-------------+--------+------+-----------+-------------------+--------------+ +| Raspberry Pi | RP2040 | ✔ | ✔ | ✖ | rp2040 | | ++--------------+-----------------------+--------+------+-----------+-------------------+--------------+ +| Renesas | RX 63N, 65N, 72N | ✔ | ✖ | ✖ | usba | | ++--------------+-----------------------+--------+------+-----------+-------------------+--------------+ +| Silabs | EFM32GG12 | ✔ | | ✖ | dwc2 | | ++--------------+-----------------------+--------+------+-----------+-------------------+--------------+ +| Sony | CXD56 | ✔ | ✖ | ✔ | cxd56 | | ++--------------+-----------------------+--------+------+-----------+-------------------+--------------+ +| ST STM32 | F0 | ✔ | ✖ | ✖ | stm32_fsdev | | +| +----+------------------+--------+------+-----------+-------------------+--------------+ +| | F1 | 102, 103 | ✔ | ✖ | ✖ | stm32_fsdev | | +| | +------------------+--------+------+-----------+-------------------+--------------+ +| | | 105, 107 | ✔ | | ✖ | dwc2 | | +| +----+------------------+--------+------+-----------+-------------------+--------------+ +| | F2 | ✔ | | ✔ | dwc2 | | +| +-----------------------+--------+------+-----------+-------------------+--------------+ +| | F3 | ✔ | ✖ | ✖ | stm32_fsdev | | +| +-----------------------+--------+------+-----------+-------------------+--------------+ +| | F4 | ✔ | | ✔ | dwc2 | | +| +-----------------------+--------+------+-----------+-------------------+--------------+ +| | F7 | ✔ | | ✔ | dwc2 | | +| +-----------------------+--------+------+-----------+-------------------+--------------+ +| | H7 | ✔ | | ✔ | dwc2 | | +| +-----------------------+--------+------+-----------+-------------------+--------------+ +| | L0, L1 | ✔ | ✖ | ✖ | stm32_fsdev | | +| +----+------------------+--------+------+-----------+-------------------+--------------+ +| | L4 | 4x2, 4x3 | ✔ | ✖ | ✖ | stm32_fsdev | | +| | +------------------+--------+------+-----------+-------------------+--------------+ +| | | 4x5, 4x6 | ✔ | | | dwc2 | | +| +----+------------------+--------+------+-----------+-------------------+--------------+ +| | L4+ | ✔ | | | dwc2 | | +| +-----------------------+--------+------+-----------+-------------------+--------------+ +| | U5 | ⚠ | | | dwc2 | | ++--------------+-----------------------+--------+------+-----------+-------------------+--------------+ +| TI | MSP430 | ✔ | ✖ | ✖ | msp430x5xx | | +| +-----------------------+--------+------+-----------+-------------------+--------------+ +| | MSP432E4 | ✔ | | ✖ | musb | | +| +-----------------------+--------+------+-----------+-------------------+--------------+ +| | TM4C123 | ✔ | | ✖ | musb | | ++--------------+-----------------------+--------+------+-----------+-------------------+--------------+ +| ValentyUSB | eptri | ✔ | ✖ | ✖ | eptri | | ++--------------+-----------------------+--------+------+-----------+-------------------+--------------+ + Table Legend ------------ -==================== =================== -|:heavy_check_mark:| Supported -|:construction:| WIP/partial support -|:x:| Not supported -==================== =================== += =================== +✔ Supported +⚠ WIP/partial support +✖ Not supported += =================== Supported Boards ================ -- cgit v1.3.1 From 369f11fe5c21ca19538e9165100115d34fdc72f4 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 2 Dec 2021 11:50:28 +0700 Subject: fix ci --- examples/host/hid_controller/Makefile | 2 -- 1 file changed, 2 deletions(-) diff --git a/examples/host/hid_controller/Makefile b/examples/host/hid_controller/Makefile index 2595ec4a7..a4eaf0816 100644 --- a/examples/host/hid_controller/Makefile +++ b/examples/host/hid_controller/Makefile @@ -23,9 +23,7 @@ SRC_C += \ src/host/hub.c \ src/host/usbh.c \ src/host/usbh_control.c \ - src/portable/ehci/ehci.c \ src/portable/ohci/ohci.c \ - src/portable/nxp/transdimension/hcd_transdimension.c \ src/portable/nxp/lpc17_40/hcd_lpc17_40.c include ../../rules.mk -- cgit v1.3.1 From 1d1e75236c4bed4346e6ed840869de2c3acf7220 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 2 Dec 2021 12:02:25 +0700 Subject: temporarily skip s3 build on ci --- .github/workflows/build_esp.yml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.github/workflows/build_esp.yml b/.github/workflows/build_esp.yml index 15071b178..57dbf33e3 100644 --- a/.github/workflows/build_esp.yml +++ b/.github/workflows/build_esp.yml @@ -18,7 +18,8 @@ jobs: # ESP32-S2 - 'espressif_saola_1' # ESP32-S3 - - 'espressif_addax_1' + #- 'espressif_addax_1' + # S3 compile error with "dangerous relocation: call8: call target out of range: memcpy" steps: - name: Setup Python -- cgit v1.3.1 From 94c35de0d2632574b8833a3310082a7e25aa6dd2 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 2 Dec 2021 13:19:27 +0700 Subject: minor doc update --- docs/reference/supported.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst index 83cf874da..e3cb8c679 100644 --- a/docs/reference/supported.rst +++ b/docs/reference/supported.rst @@ -39,7 +39,7 @@ Supported MCUs | | NUC126 | ✔ | ✖ | ✖ | | | | +-----------------------+--------+------+-----------+-------------------+--------------+ | | NUC505 | ✔ | | ✔ | | | -+--------------+-----------------------+--------+------+-----------+-------------------+--------------+ ++--------------+---------+-------------+--------+------+-----------+-------------------+--------------+ | NXP | iMXRT | RT10xx | ✔ | ✔ | ✔ | ci_hs | | | +---------+-------------+--------+------+-----------+-------------------+--------------+ | | Kinetis | KL25 | ✔ | | ✖ | | | -- cgit v1.3.1 From c52c9cda913a828da4d6b2da4df8a0ef1751c425 Mon Sep 17 00:00:00 2001 From: Rafael Silva Date: Thu, 2 Dec 2021 10:22:24 +0000 Subject: after commit: eae4132 this dependency is no longer required Signed-off-by: Rafael Silva --- docs/conf.py | 1 - docs/requirements.txt | 1 - 2 files changed, 2 deletions(-) diff --git a/docs/conf.py b/docs/conf.py index c7a17478f..878b29645 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -21,7 +21,6 @@ extensions = [ 'sphinx.ext.intersphinx', 'sphinx.ext.todo', 'sphinx_autodoc_typehints', - 'sphinxemoji.sphinxemoji', ] templates_path = ['_templates'] diff --git a/docs/requirements.txt b/docs/requirements.txt index e415ae03e..8ae9ae73b 100644 --- a/docs/requirements.txt +++ b/docs/requirements.txt @@ -1,4 +1,3 @@ sphinx~=3.0 furo>=2020.12.30.b24 -sphinxemoji>=0.1.8 sphinx-autodoc-typehints>=1.10 -- cgit v1.3.1 From 81285273a6b5cacace52e74890ff9863a6a92d1a Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Sat, 4 Dec 2021 01:18:42 +0900 Subject: Fix memory overrun at pipe_read_packet() --- src/portable/mentor/musb/hcd_musb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/portable/mentor/musb/hcd_musb.c b/src/portable/mentor/musb/hcd_musb.c index dc614d074..acccb7674 100644 --- a/src/portable/mentor/musb/hcd_musb.c +++ b/src/portable/mentor/musb/hcd_musb.c @@ -269,12 +269,12 @@ static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len) len -= 4; } if (len >= 2) { - *(uint32_t *)addr = reg->u16; + *(uint16_t *)addr = reg->u16; addr += 2; len -= 2; } if (len) { - *(uint32_t *)addr = reg->u8; + *(uint8_t *)addr = reg->u8; } } -- cgit v1.3.1 From 7137a0a92f5623e06d7457aba0eaa65f077010a2 Mon Sep 17 00:00:00 2001 From: kkitayam <45088311+kkitayam@users.noreply.github.com> Date: Sat, 4 Dec 2021 01:25:34 +0900 Subject: Fix buffer overrun at pipe_read_packet() --- src/portable/mentor/musb/dcd_musb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c index 4b4c2f9b2..512beff97 100644 --- a/src/portable/mentor/musb/dcd_musb.c +++ b/src/portable/mentor/musb/dcd_musb.c @@ -250,12 +250,12 @@ static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len) len -= 4; } if (len >= 2) { - *(uint32_t *)addr = reg->u16; + *(uint16_t *)addr = reg->u16; addr += 2; len -= 2; } if (len) { - *(uint32_t *)addr = reg->u8; + *(uint8_t *)addr = reg->u8; } } -- cgit v1.3.1 From 03835c818361bb6c5eafd8cb51e8a9bb6b4f16fb Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 7 Dec 2021 16:27:48 +0700 Subject: move hcd_musb.c include to family.mk --- examples/host/cdc_msc_hid/.only.MCU_MSP432E4 | 0 examples/host/cdc_msc_hid/.only.MCU_TM4C123 | 0 examples/host/cdc_msc_hid/Makefile | 3 +-- examples/host/hid_controller/.only.MCU_MSP432E4 | 0 examples/host/hid_controller/.only.MCU_TM4C123 | 0 examples/host/hid_controller/Makefile | 3 +-- hw/bsp/msp432e4/family.mk | 1 + 7 files changed, 3 insertions(+), 4 deletions(-) create mode 100644 examples/host/cdc_msc_hid/.only.MCU_MSP432E4 create mode 100644 examples/host/cdc_msc_hid/.only.MCU_TM4C123 create mode 100644 examples/host/hid_controller/.only.MCU_MSP432E4 create mode 100644 examples/host/hid_controller/.only.MCU_TM4C123 diff --git a/examples/host/cdc_msc_hid/.only.MCU_MSP432E4 b/examples/host/cdc_msc_hid/.only.MCU_MSP432E4 new file mode 100644 index 000000000..e69de29bb diff --git a/examples/host/cdc_msc_hid/.only.MCU_TM4C123 b/examples/host/cdc_msc_hid/.only.MCU_TM4C123 new file mode 100644 index 000000000..e69de29bb diff --git a/examples/host/cdc_msc_hid/Makefile b/examples/host/cdc_msc_hid/Makefile index 8c8735a56..ce0dd1a40 100644 --- a/examples/host/cdc_msc_hid/Makefile +++ b/examples/host/cdc_msc_hid/Makefile @@ -21,7 +21,6 @@ SRC_C += \ src/host/usbh.c \ src/host/usbh_control.c \ src/portable/ohci/ohci.c \ - src/portable/nxp/lpc17_40/hcd_lpc17_40.c \ - src/portable/mentor/musb/hcd_musb.c + src/portable/nxp/lpc17_40/hcd_lpc17_40.c include ../../rules.mk diff --git a/examples/host/hid_controller/.only.MCU_MSP432E4 b/examples/host/hid_controller/.only.MCU_MSP432E4 new file mode 100644 index 000000000..e69de29bb diff --git a/examples/host/hid_controller/.only.MCU_TM4C123 b/examples/host/hid_controller/.only.MCU_TM4C123 new file mode 100644 index 000000000..e69de29bb diff --git a/examples/host/hid_controller/Makefile b/examples/host/hid_controller/Makefile index 909abe8a6..c58df562b 100644 --- a/examples/host/hid_controller/Makefile +++ b/examples/host/hid_controller/Makefile @@ -24,7 +24,6 @@ SRC_C += \ src/host/usbh.c \ src/host/usbh_control.c \ src/portable/ohci/ohci.c \ - src/portable/nxp/lpc17_40/hcd_lpc17_40.c \ - src/portable/mentor/musb/hcd_musb.c + src/portable/nxp/lpc17_40/hcd_lpc17_40.c include ../../rules.mk diff --git a/hw/bsp/msp432e4/family.mk b/hw/bsp/msp432e4/family.mk index b664c4c1b..e3cb90abc 100644 --- a/hw/bsp/msp432e4/family.mk +++ b/hw/bsp/msp432e4/family.mk @@ -23,6 +23,7 @@ MCU_DIR = hw/mcu/ti/msp432e4 SRC_C += \ src/portable/mentor/musb/dcd_musb.c \ + src/portable/mentor/musb/hcd_musb.c \ $(MCU_DIR)/Source/system_msp432e401y.c INC += \ -- cgit v1.3.1 From 8e0400d531bbbb8faf45576a3b5e55be9406cf6b Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 7 Dec 2021 16:28:24 +0700 Subject: change uart baudrate for tm4c123 to 115200 --- hw/bsp/tm4c123/family.c | 25 ++++++++++++++++++------- hw/bsp/tm4c123/family.mk | 1 + 2 files changed, 19 insertions(+), 7 deletions(-) diff --git a/hw/bsp/tm4c123/family.c b/hw/bsp/tm4c123/family.c index 048832dc9..449781ce1 100644 --- a/hw/bsp/tm4c123/family.c +++ b/hw/bsp/tm4c123/family.c @@ -7,7 +7,13 @@ //--------------------------------------------------------------------+ void USB0_Handler(void) { +#if TUSB_OPT_HOST_ENABLED + tuh_int_handler(0); +#endif + +#if TUSB_OPT_DEVICE_ENABLED tud_int_handler(0); +#endif } //--------------------------------------------------------------------+ @@ -23,10 +29,12 @@ static void board_uart_init (void) GPIOA->PCTL |= (1 << 0) | (1 << 4); // Configure the GPIOPCTL register to select UART0 in PA0 and PA1 GPIOA->DEN |= (1 << 0) | (1 << 1); // Enable the digital functionality in PA0 and PA1 - /** BAUDRATE = 9600 bits per second, refer manual for calculation **/ + // BAUDRATE = 115200, with SystemCoreClock = 50 Mhz refer manual for calculation + // - BRDI = SystemCoreClock / (16* baud) + // - BRDF = int(fraction*64 + 0.5) UART0->CTL &= ~(1 << 0); // Disable UART0 by clearing UARTEN bit in the UARTCTL register - UART0->IBRD = 325; // Write the integer portion of the BRD to the UARTIRD register - UART0->FBRD = 33; // Write the fractional portion of the BRD to the UARTFBRD registerer + UART0->IBRD = 27; // Write the integer portion of the BRD to the UARTIRD register + UART0->FBRD = 8; // Write the fractional portion of the BRD to the UARTFBRD registerer UART0->LCRH = (0x3 << 5); // 8-bit, no parity, 1 stop bit UART0->CC = 0x0; // Configure the UART clock source as system clock @@ -40,8 +48,7 @@ static void initialize_board_led (GPIOA_Type *port, uint8_t PinMsk, uint8_t dirm SYSCTL->RCGCGPIO |= (1 << 5); /* Let the clock stabilize */ - while ( !((SYSCTL->PRGPIO) & (1 << 5)) ) - ; + while ( !((SYSCTL->PRGPIO) & (1 << 5)) ) {} /* Port Digital Enable */ port->DEN |= PinMsk; @@ -60,9 +67,13 @@ static void board_switch_init (void) static void WriteGPIOPin (GPIOA_Type *port, uint8_t PinMsk, bool state) { if ( state ) + { port->DATA |= PinMsk; + } else + { port->DATA &= ~(PinMsk); + } } static uint32_t ReadGPIOPin (GPIOA_Type *port, uint8_t pinMsk) @@ -99,8 +110,7 @@ void board_init (void) SYSCTL->RCGCGPIO |= (1u << 3); /* Let the clock stabilize */ - while ( !(SYSCTL->PRGPIO & (1u << 3)) ) - ; + while ( !(SYSCTL->PRGPIO & (1u << 3)) ) {} /* USB IOs to Analog Mode */ GPIOD->AFSEL &= ~((1u << 4) | (1u << 5)); @@ -119,6 +129,7 @@ void board_init (void) /* Initialize board UART */ board_uart_init(); + TU_LOG1_INT(SystemCoreClock); } void board_led_write (bool state) diff --git a/hw/bsp/tm4c123/family.mk b/hw/bsp/tm4c123/family.mk index 9665a2d7d..751076196 100644 --- a/hw/bsp/tm4c123/family.mk +++ b/hw/bsp/tm4c123/family.mk @@ -28,6 +28,7 @@ INC += \ SRC_C += \ src/portable/mentor/musb/dcd_musb.c \ + src/portable/mentor/musb/hcd_musb.c \ $(MCU_DIR)/Source/system_TM4C123.c \ $(MCU_DIR)/Source/GCC/tm4c123_startup.c -- cgit v1.3.1 From a5251cb86bb35a2da1248e6d32106c694891b02b Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 7 Dec 2021 17:14:20 +0700 Subject: skip host ci for tm4c due to sram overflow --- examples/host/cdc_msc_hid/.only.MCU_TM4C123 | 0 examples/host/hid_controller/.only.MCU_TM4C123 | 0 2 files changed, 0 insertions(+), 0 deletions(-) delete mode 100644 examples/host/cdc_msc_hid/.only.MCU_TM4C123 delete mode 100644 examples/host/hid_controller/.only.MCU_TM4C123 diff --git a/examples/host/cdc_msc_hid/.only.MCU_TM4C123 b/examples/host/cdc_msc_hid/.only.MCU_TM4C123 deleted file mode 100644 index e69de29bb..000000000 diff --git a/examples/host/hid_controller/.only.MCU_TM4C123 b/examples/host/hid_controller/.only.MCU_TM4C123 deleted file mode 100644 index e69de29bb..000000000 -- cgit v1.3.1